STM32U5 : update HAL on U5 to version 1.3.0
Change-Id: Id3831ae44dcce0e304df095b3b916d95966645bb
Signed-off-by: Ahmad EL JOUAID <ahmad.eljouaid@st.com>
diff --git a/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.c b/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.c
index aacb741..c81caa2 100644
--- a/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.c
+++ b/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.c
@@ -1,31 +1,31 @@
/**
- ******************************************************************************
- * @file mx25lm51245g.c
- * @modify MCD Application Team
- * @brief This file provides the MX25LM51245G OSPI drivers.
- ******************************************************************************
- * MX25LM51245G action :
- * STR Octal IO protocol (SOPI) and DTR Octal IO protocol (DOPI) bits of
- * Configuration Register 2 :
- * DOPI = 1 and SOPI = 0: Operates in DTR Octal IO protocol (accepts 8-8-8 commands)
- * DOPI = 0 and SOPI = 1: Operates in STR Octal IO protocol (accepts 8-8-8 commands)
- * DOPI = 0 and SOPI = 0: Operates in Single IO protocol (accepts 1-1-1 commands)
- * Enter SOPI mode by configuring DOPI = 0 and SOPI = 1 in CR2-Addr0
- * Exit SOPI mode by configuring DOPI = 0 and SOPI = 0 in CR2-Addr0
- * Enter DOPI mode by configuring DOPI = 1 and SOPI = 0 in CR2-Addr0
- * Exit DOPI mode by configuring DOPI = 0 and SOPI = 0 in CR2-Addr0
- *
- * Memory commands support STR(Single Transfer Rate) &
- * DTR(Double Transfer Rate) modes in OPI
- *
- * Memory commands support STR(Single Transfer Rate) &
- * DTR(Double Transfer Rate) modes in SPI
- *
- ******************************************************************************
+ ******************************************************************************
+ * @file mx25lm51245g.c
+ * @modify MCD Application Team
+ * @brief This file provides the MX25LM51245G OSPI drivers.
+ ******************************************************************************
+ * MX25LM51245G action :
+ * STR Octal IO protocol (SOPI) and DTR Octal IO protocol (DOPI) bits of
+ * Configuration Register 2 :
+ * DOPI = 1 and SOPI = 0: Operates in DTR Octal IO protocol (accepts 8-8-8 commands)
+ * DOPI = 0 and SOPI = 1: Operates in STR Octal IO protocol (accepts 8-8-8 commands)
+ * DOPI = 0 and SOPI = 0: Operates in Single IO protocol (accepts 1-1-1 commands)
+ * Enter SOPI mode by configuring DOPI = 0 and SOPI = 1 in CR2-Addr0
+ * Exit SOPI mode by configuring DOPI = 0 and SOPI = 0 in CR2-Addr0
+ * Enter DOPI mode by configuring DOPI = 1 and SOPI = 0 in CR2-Addr0
+ * Exit DOPI mode by configuring DOPI = 0 and SOPI = 0 in CR2-Addr0
+ *
+ * Memory commands support STR(Single Transfer Rate) &
+ * DTR(Double Transfer Rate) modes in OPI
+ *
+ * Memory commands support STR(Single Transfer Rate) &
+ * DTR(Double Transfer Rate) modes in SPI
+ *
+ ******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2018 - 2025 STMicroelectronics.
+ * All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
@@ -33,7 +33,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "mx25lm51245g.h"
@@ -64,13 +64,13 @@
/* Configure the structure with the memory configuration */
pInfo->FlashSize = MX25LM51245G_FLASH_SIZE;
pInfo->EraseSectorSize = MX25LM51245G_SECTOR_64K;
- pInfo->EraseSectorsNumber = (MX25LM51245G_FLASH_SIZE/MX25LM51245G_SECTOR_64K);
+ pInfo->EraseSectorsNumber = (MX25LM51245G_FLASH_SIZE / MX25LM51245G_SECTOR_64K);
pInfo->EraseSubSectorSize = MX25LM51245G_SUBSECTOR_4K;
- pInfo->EraseSubSectorNumber = (MX25LM51245G_FLASH_SIZE/MX25LM51245G_SUBSECTOR_4K);
+ pInfo->EraseSubSectorNumber = (MX25LM51245G_FLASH_SIZE / MX25LM51245G_SUBSECTOR_4K);
pInfo->EraseSubSector1Size = MX25LM51245G_SUBSECTOR_4K;
- pInfo->EraseSubSector1Number = (MX25LM51245G_FLASH_SIZE/MX25LM51245G_SUBSECTOR_4K);
+ pInfo->EraseSubSector1Number = (MX25LM51245G_FLASH_SIZE / MX25LM51245G_SUBSECTOR_4K);
pInfo->ProgPageSize = MX25LM51245G_PAGE_SIZE;
- pInfo->ProgPagesNumber = (MX25LM51245G_FLASH_SIZE/MX25LM51245G_PAGE_SIZE);
+ pInfo->ProgPagesNumber = (MX25LM51245G_FLASH_SIZE / MX25LM51245G_PAGE_SIZE);
return MX25LM51245G_OK;
};
@@ -83,7 +83,8 @@
* @param Rate Transfer rate
* @retval error status
*/
-int32_t MX25LM51245G_AutoPollingMemReady(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate)
+int32_t MX25LM51245G_AutoPollingMemReady(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate)
{
OSPI_RegularCmdTypeDef s_command = {0};
OSPI_AutoPollingTypeDef s_config = {0};
@@ -96,23 +97,35 @@
/* Configure automatic polling mode to wait for memory ready */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_STATUS_REG_CMD : MX25LM51245G_OCTA_READ_STATUS_REG_CMD;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_READ_STATUS_REG_CMD
+ : MX25LM51245G_OCTA_READ_STATUS_REG_CMD;
s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES;
- s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
+ s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_ADDRESS_DTR_ENABLE
+ : HAL_OSPI_ADDRESS_DTR_DISABLE;
s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
s_command.Address = 0U;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
- s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
- s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL);
+ s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_DATA_DTR_ENABLE
+ : HAL_OSPI_DATA_DTR_DISABLE;
+ s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE)
+ ? 0U
+ : ((Rate == MX25LM51245G_DTR_TRANSFER)
+ ? DUMMY_CYCLES_REG_OCTAL_DTR
+ : DUMMY_CYCLES_REG_OCTAL);
s_command.NbData = (Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U;
s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE;
s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
@@ -148,7 +161,8 @@
* @param Size Size of data to read
* @retval OSPI memory status
*/
-int32_t MX25LM51245G_ReadSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t ReadAddr, uint32_t Size)
+int32_t MX25LM51245G_ReadSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t ReadAddr, uint32_t Size)
{
OSPI_RegularCmdTypeDef s_command = {0};
@@ -160,18 +174,26 @@
/* Initialize the read command */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? ((AddressSize == MX25LM51245G_3BYTES_SIZE) ? MX25LM51245G_FAST_READ_CMD : MX25LM51245G_4_BYTE_ADDR_FAST_READ_CMD) : MX25LM51245G_OCTA_READ_CMD;
- s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_8_LINES;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? ((AddressSize == MX25LM51245G_3BYTES_SIZE)
+ ? MX25LM51245G_FAST_READ_CMD
+ : MX25LM51245G_4_BYTE_ADDR_FAST_READ_CMD)
+ : MX25LM51245G_OCTA_READ_CMD;
+ s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_ADDRESS_1_LINE
+ : HAL_OSPI_ADDRESS_8_LINES;
s_command.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE;
- s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE) ? HAL_OSPI_ADDRESS_24_BITS : HAL_OSPI_ADDRESS_32_BITS;
+ s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE)
+ ? HAL_OSPI_ADDRESS_24_BITS
+ : HAL_OSPI_ADDRESS_32_BITS;
s_command.Address = ReadAddr;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
@@ -202,7 +224,7 @@
* @param Ctx Component object pointer
* @param AddressSize Address size
* @param pData Pointer to data to be read
- * @param ReadAddr Read start addressS
+ * @param ReadAddr Read start address
* @param Size Size of data to read
* @note Only OPI mode support DTR transfer rate
* @retval OSPI memory status
@@ -213,11 +235,7 @@
/* Initialize the read command */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
s_command.InstructionMode = HAL_OSPI_INSTRUCTION_8_LINES;
s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_ENABLE;
s_command.InstructionSize = HAL_OSPI_INSTRUCTION_16_BITS;
@@ -262,7 +280,9 @@
* command is not available for the specified interface mode
* @retval OSPI memory status
*/
-int32_t MX25LM51245G_PageProgram(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t WriteAddr, uint32_t Size)
+int32_t MX25LM51245G_PageProgram(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t WriteAddr,
+ uint32_t Size)
{
OSPI_RegularCmdTypeDef s_command = {0};
@@ -274,18 +294,26 @@
/* Initialize the program command */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? ((AddressSize == MX25LM51245G_3BYTES_SIZE) ? MX25LM51245G_PAGE_PROG_CMD : MX25LM51245G_4_BYTE_PAGE_PROG_CMD) : MX25LM51245G_OCTA_PAGE_PROG_CMD;
- s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_8_LINES;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? ((AddressSize == MX25LM51245G_3BYTES_SIZE)
+ ? MX25LM51245G_PAGE_PROG_CMD
+ : MX25LM51245G_4_BYTE_PAGE_PROG_CMD)
+ : MX25LM51245G_OCTA_PAGE_PROG_CMD;
+ s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_ADDRESS_1_LINE
+ : HAL_OSPI_ADDRESS_8_LINES;
s_command.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE;
- s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE) ? HAL_OSPI_ADDRESS_24_BITS : HAL_OSPI_ADDRESS_32_BITS;
+ s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE)
+ ? HAL_OSPI_ADDRESS_24_BITS
+ : HAL_OSPI_ADDRESS_32_BITS;
s_command.Address = WriteAddr;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
@@ -326,11 +354,7 @@
/* Initialize the program command */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
s_command.InstructionMode = HAL_OSPI_INSTRUCTION_8_LINES;
s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_ENABLE;
s_command.InstructionSize = HAL_OSPI_INSTRUCTION_16_BITS;
@@ -373,7 +397,9 @@
* @param BlockSize Block size to erase
* @retval OSPI memory status
*/
-int32_t MX25LM51245G_BlockErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, MX25LM51245G_AddressSize_t AddressSize, uint32_t BlockAddress, MX25LM51245G_Erase_t BlockSize)
+int32_t MX25LM51245G_BlockErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate,
+ MX25LM51245G_AddressSize_t AddressSize, uint32_t BlockAddress,
+ MX25LM51245G_Erase_t BlockSize)
{
OSPI_RegularCmdTypeDef s_command = {0};
@@ -391,17 +417,23 @@
/* Initialize the erase command */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_8_LINES;
- s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
- s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE) ? HAL_OSPI_ADDRESS_24_BITS : HAL_OSPI_ADDRESS_32_BITS;
+ s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_ADDRESS_DTR_ENABLE
+ : HAL_OSPI_ADDRESS_DTR_DISABLE;
+ s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE)
+ ? HAL_OSPI_ADDRESS_24_BITS
+ : HAL_OSPI_ADDRESS_32_BITS;
s_command.Address = BlockAddress;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = HAL_OSPI_DATA_NONE;
@@ -409,34 +441,38 @@
s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
- switch(Mode)
+ switch (Mode)
{
- case MX25LM51245G_OPI_MODE :
- if(BlockSize == MX25LM51245G_ERASE_64K)
- {
- s_command.Instruction = MX25LM51245G_OCTA_SECTOR_ERASE_64K_CMD;
- }
- else
- {
- s_command.Instruction = MX25LM51245G_OCTA_SUBSECTOR_ERASE_4K_CMD;
- }
- break;
+ case MX25LM51245G_OPI_MODE :
+ if (BlockSize == MX25LM51245G_ERASE_64K)
+ {
+ s_command.Instruction = MX25LM51245G_OCTA_SECTOR_ERASE_64K_CMD;
+ }
+ else
+ {
+ s_command.Instruction = MX25LM51245G_OCTA_SUBSECTOR_ERASE_4K_CMD;
+ }
+ break;
- case MX25LM51245G_SPI_MODE :
- default:
- if(BlockSize == MX25LM51245G_ERASE_64K)
- {
- s_command.Instruction = (AddressSize == MX25LM51245G_3BYTES_SIZE) ? MX25LM51245G_SECTOR_ERASE_64K_CMD : MX25LM51245G_4_BYTE_SECTOR_ERASE_64K_CMD;
- }
- else
- {
- s_command.Instruction = (AddressSize == MX25LM51245G_3BYTES_SIZE) ? MX25LM51245G_SUBSECTOR_ERASE_4K_CMD : MX25LM51245G_4_BYTE_SUBSECTOR_ERASE_4K_CMD;
- }
- break;
+ case MX25LM51245G_SPI_MODE :
+ default:
+ if (BlockSize == MX25LM51245G_ERASE_64K)
+ {
+ s_command.Instruction = (AddressSize == MX25LM51245G_3BYTES_SIZE)
+ ? MX25LM51245G_SECTOR_ERASE_64K_CMD
+ : MX25LM51245G_4_BYTE_SECTOR_ERASE_64K_CMD;
+ }
+ else
+ {
+ s_command.Instruction = (AddressSize == MX25LM51245G_3BYTES_SIZE)
+ ? MX25LM51245G_SUBSECTOR_ERASE_4K_CMD
+ : MX25LM51245G_4_BYTE_SUBSECTOR_ERASE_4K_CMD;
+ }
+ break;
}
/* Send the command */
- if(HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
return MX25LM51245G_ERROR;
}
@@ -463,15 +499,19 @@
/* Initialize the erase command */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_BULK_ERASE_CMD : MX25LM51245G_OCTA_BULK_ERASE_CMD;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_BULK_ERASE_CMD
+ : MX25LM51245G_OCTA_BULK_ERASE_CMD;
s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = HAL_OSPI_DATA_NONE;
@@ -480,7 +520,7 @@
s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
/* Send the command */
- if(HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
return MX25LM51245G_ERROR;
}
@@ -496,7 +536,8 @@
* @param AddressSize Address size
* @retval OSPI memory status
*/
-int32_t MX25LM51245G_EnableSTRMemoryMappedMode(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize)
+int32_t MX25LM51245G_EnableSTRMemoryMappedMode(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_AddressSize_t AddressSize)
{
OSPI_RegularCmdTypeDef s_command = {0};
OSPI_MemoryMappedTypeDef s_mem_mapped_cfg = {0};
@@ -509,18 +550,24 @@
/* Initialize the read command */
s_command.OperationType = HAL_OSPI_OPTYPE_READ_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? ((AddressSize == MX25LM51245G_3BYTES_SIZE) ? MX25LM51245G_FAST_READ_CMD : MX25LM51245G_4_BYTE_ADDR_FAST_READ_CMD) : MX25LM51245G_OCTA_READ_CMD;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? ((AddressSize == MX25LM51245G_3BYTES_SIZE)
+ ? MX25LM51245G_FAST_READ_CMD
+ : MX25LM51245G_4_BYTE_ADDR_FAST_READ_CMD)
+ : MX25LM51245G_OCTA_READ_CMD;
s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_8_LINES;
s_command.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE;
- s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE) ? HAL_OSPI_ADDRESS_24_BITS : HAL_OSPI_ADDRESS_32_BITS;
+ s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE)
+ ? HAL_OSPI_ADDRESS_24_BITS
+ : HAL_OSPI_ADDRESS_32_BITS;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
s_command.DataDtrMode = HAL_OSPI_DATA_DTR_DISABLE;
@@ -536,7 +583,11 @@
/* Initialize the program command */
s_command.OperationType = HAL_OSPI_OPTYPE_WRITE_CFG;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? ((AddressSize == MX25LM51245G_3BYTES_SIZE) ? MX25LM51245G_PAGE_PROG_CMD : MX25LM51245G_4_BYTE_PAGE_PROG_CMD) : MX25LM51245G_OCTA_PAGE_PROG_CMD;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? ((AddressSize == MX25LM51245G_3BYTES_SIZE)
+ ? MX25LM51245G_PAGE_PROG_CMD
+ : MX25LM51245G_4_BYTE_PAGE_PROG_CMD)
+ : MX25LM51245G_OCTA_PAGE_PROG_CMD;
s_command.DummyCycles = 0U;
/* Send the write command */
@@ -574,11 +625,7 @@
/* Initialize the read command */
s_command.OperationType = HAL_OSPI_OPTYPE_READ_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
s_command.InstructionMode = HAL_OSPI_INSTRUCTION_8_LINES;
s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_ENABLE;
s_command.InstructionSize = HAL_OSPI_INSTRUCTION_16_BITS;
@@ -641,15 +688,19 @@
/* Initialize the suspend command */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_PROG_ERASE_SUSPEND_CMD : MX25LM51245G_OCTA_PROG_ERASE_SUSPEND_CMD;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_PROG_ERASE_SUSPEND_CMD
+ : MX25LM51245G_OCTA_PROG_ERASE_SUSPEND_CMD;
s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = HAL_OSPI_DATA_NONE;
@@ -686,15 +737,19 @@
/* Initialize the resume command */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_PROG_ERASE_RESUME_CMD : MX25LM51245G_OCTA_PROG_ERASE_RESUME_CMD;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_PROG_ERASE_RESUME_CMD
+ : MX25LM51245G_OCTA_PROG_ERASE_RESUME_CMD;
s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = HAL_OSPI_DATA_NONE;
@@ -733,15 +788,19 @@
/* Initialize the write enable command */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_WRITE_ENABLE_CMD : MX25LM51245G_OCTA_WRITE_ENABLE_CMD;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_WRITE_ENABLE_CMD
+ : MX25LM51245G_OCTA_WRITE_ENABLE_CMD;
s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = HAL_OSPI_DATA_NONE;
@@ -756,14 +815,22 @@
}
/* Configure automatic polling mode to wait for write enabling */
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_STATUS_REG_CMD : MX25LM51245G_OCTA_READ_STATUS_REG_CMD;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_READ_STATUS_REG_CMD
+ : MX25LM51245G_OCTA_READ_STATUS_REG_CMD;
s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES;
- s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
+ s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_ADDRESS_DTR_ENABLE
+ : HAL_OSPI_ADDRESS_DTR_DISABLE;
s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
s_command.Address = 0U;
s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
- s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL);
+ s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE)
+ ? 0U
+ : ((Rate == MX25LM51245G_DTR_TRANSFER)
+ ? DUMMY_CYCLES_REG_OCTAL_DTR
+ : DUMMY_CYCLES_REG_OCTAL);
s_command.NbData = (Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U;
s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE;
@@ -807,15 +874,19 @@
/* Initialize the write disable command */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_WRITE_DISABLE_CMD : MX25LM51245G_OCTA_WRITE_DISABLE_CMD;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_WRITE_DISABLE_CMD
+ : MX25LM51245G_OCTA_WRITE_DISABLE_CMD;
s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = HAL_OSPI_DATA_NONE;
@@ -841,7 +912,8 @@
* @param Value Status register value pointer
* @retval error status
*/
-int32_t MX25LM51245G_ReadStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value)
+int32_t MX25LM51245G_ReadStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate, uint8_t *Value)
{
OSPI_RegularCmdTypeDef s_command = {0};
@@ -853,23 +925,35 @@
/* Initialize the reading of status register */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_STATUS_REG_CMD : MX25LM51245G_OCTA_READ_STATUS_REG_CMD;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_READ_STATUS_REG_CMD
+ : MX25LM51245G_OCTA_READ_STATUS_REG_CMD;
s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES;
- s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
+ s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_ADDRESS_DTR_ENABLE
+ : HAL_OSPI_ADDRESS_DTR_DISABLE;
s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
s_command.Address = 0U;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
- s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
- s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL);
+ s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_DATA_DTR_ENABLE
+ : HAL_OSPI_DATA_DTR_DISABLE;
+ s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE)
+ ? 0U
+ : ((Rate == MX25LM51245G_DTR_TRANSFER)
+ ? DUMMY_CYCLES_REG_OCTAL_DTR
+ : DUMMY_CYCLES_REG_OCTAL);
s_command.NbData = (Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U;
s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE;
s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
@@ -898,7 +982,8 @@
* @param Value Value to write to Status register
* @retval error status
*/
-int32_t MX25LM51245G_WriteStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value)
+int32_t MX25LM51245G_WriteStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate, uint8_t Value)
{
OSPI_RegularCmdTypeDef s_command = {0};
uint8_t reg[2];
@@ -921,22 +1006,30 @@
/* Initialize the writing of status register */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_WRITE_STATUS_REG_CMD : MX25LM51245G_OCTA_WRITE_STATUS_REG_CMD;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_WRITE_STATUS_REG_CMD
+ : MX25LM51245G_OCTA_WRITE_STATUS_REG_CMD;
s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES;
- s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
+ s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_ADDRESS_DTR_ENABLE
+ : HAL_OSPI_ADDRESS_DTR_DISABLE;
s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
s_command.Address = 0U;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
- s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
+ s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_DATA_DTR_ENABLE
+ : HAL_OSPI_DATA_DTR_DISABLE;
s_command.DummyCycles = 0U;
s_command.NbData = (Mode == MX25LM51245G_SPI_MODE) ? 2U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U);
s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
@@ -965,7 +1058,8 @@
* @param Value Value to write to configuration register
* @retval error status
*/
-int32_t MX25LM51245G_WriteCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value)
+int32_t MX25LM51245G_WriteCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate, uint8_t Value)
{
OSPI_RegularCmdTypeDef s_command = {0};
uint8_t reg[2];
@@ -992,22 +1086,30 @@
/* Initialize the writing of configuration register */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_WRITE_STATUS_REG_CMD : MX25LM51245G_OCTA_WRITE_STATUS_REG_CMD;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_WRITE_STATUS_REG_CMD
+ : MX25LM51245G_OCTA_WRITE_STATUS_REG_CMD;
s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES;
- s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
+ s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_ADDRESS_DTR_ENABLE
+ : HAL_OSPI_ADDRESS_DTR_DISABLE;
s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
s_command.Address = 1U;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
- s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
+ s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_DATA_DTR_ENABLE
+ : HAL_OSPI_DATA_DTR_DISABLE;
s_command.DummyCycles = 0U;
s_command.NbData = (Mode == MX25LM51245G_SPI_MODE) ? 2U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U);
s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
@@ -1036,7 +1138,8 @@
* @param Value configuration register value pointer
* @retval error status
*/
-int32_t MX25LM51245G_ReadCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value)
+int32_t MX25LM51245G_ReadCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate, uint8_t *Value)
{
OSPI_RegularCmdTypeDef s_command = {0};
@@ -1048,23 +1151,35 @@
/* Initialize the reading of configuration register */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_CFG_REG_CMD : MX25LM51245G_OCTA_READ_CFG_REG_CMD;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_READ_CFG_REG_CMD
+ : MX25LM51245G_OCTA_READ_CFG_REG_CMD;
s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES;
- s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
+ s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_ADDRESS_DTR_ENABLE
+ : HAL_OSPI_ADDRESS_DTR_DISABLE;
s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
s_command.Address = 1U;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
- s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
- s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL);
+ s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_DATA_DTR_ENABLE
+ : HAL_OSPI_DATA_DTR_DISABLE;
+ s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE)
+ ? 0U
+ : ((Rate == MX25LM51245G_DTR_TRANSFER)
+ ? DUMMY_CYCLES_REG_OCTAL_DTR
+ : DUMMY_CYCLES_REG_OCTAL);
s_command.NbData = (Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U;
s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE;
s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
@@ -1093,7 +1208,8 @@
* @param Value Value to write to configuration register
* @retval error status
*/
-int32_t MX25LM51245G_WriteCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint32_t WriteAddr, uint8_t Value)
+int32_t MX25LM51245G_WriteCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate, uint32_t WriteAddr, uint8_t Value)
{
OSPI_RegularCmdTypeDef s_command = {0};
@@ -1105,22 +1221,30 @@
/* Initialize the writing of configuration register 2 */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_WRITE_CFG_REG2_CMD : MX25LM51245G_OCTA_WRITE_CFG_REG2_CMD;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_WRITE_CFG_REG2_CMD
+ : MX25LM51245G_OCTA_WRITE_CFG_REG2_CMD;
s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_8_LINES;
- s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
+ s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_ADDRESS_DTR_ENABLE
+ : HAL_OSPI_ADDRESS_DTR_DISABLE;
s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
s_command.Address = WriteAddr;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
- s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
+ s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_DATA_DTR_ENABLE
+ : HAL_OSPI_DATA_DTR_DISABLE;
s_command.DummyCycles = 0U;
s_command.NbData = (Mode == MX25LM51245G_SPI_MODE) ? 1U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U);
s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
@@ -1149,7 +1273,8 @@
* @param Value configuration register 2 value pointer
* @retval error status
*/
-int32_t MX25LM51245G_ReadCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint32_t ReadAddr, uint8_t *Value)
+int32_t MX25LM51245G_ReadCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate, uint32_t ReadAddr, uint8_t *Value)
{
OSPI_RegularCmdTypeDef s_command = {0};
@@ -1161,23 +1286,35 @@
/* Initialize the reading of status register */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_CFG_REG2_CMD : MX25LM51245G_OCTA_READ_CFG_REG2_CMD;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_READ_CFG_REG2_CMD
+ : MX25LM51245G_OCTA_READ_CFG_REG2_CMD;
s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_8_LINES;
- s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
+ s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_ADDRESS_DTR_ENABLE
+ : HAL_OSPI_ADDRESS_DTR_DISABLE;
s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
s_command.Address = ReadAddr;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
- s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
- s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL);
+ s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_DATA_DTR_ENABLE
+ : HAL_OSPI_DATA_DTR_DISABLE;
+ s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE)
+ ? 0U
+ : ((Rate == MX25LM51245G_DTR_TRANSFER)
+ ? DUMMY_CYCLES_REG_OCTAL_DTR
+ : DUMMY_CYCLES_REG_OCTAL);
s_command.NbData = (Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U;
s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE;
s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
@@ -1206,7 +1343,8 @@
* @param Value Value to write to Security register
* @retval error status
*/
-int32_t MX25LM51245G_WriteSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value)
+int32_t MX25LM51245G_WriteSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate, uint8_t Value)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(Value);
@@ -1221,15 +1359,19 @@
/* Initialize the write of security register */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_WRITE_SECURITY_REG_CMD : MX25LM51245G_OCTA_WRITE_SECURITY_REG_CMD;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_WRITE_SECURITY_REG_CMD
+ : MX25LM51245G_OCTA_WRITE_SECURITY_REG_CMD;
s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = HAL_OSPI_DATA_NONE;
@@ -1255,7 +1397,8 @@
* @param Value Security register value pointer
* @retval error status
*/
-int32_t MX25LM51245G_ReadSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value)
+int32_t MX25LM51245G_ReadSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate, uint8_t *Value)
{
OSPI_RegularCmdTypeDef s_command = {0};
@@ -1267,23 +1410,35 @@
/* Initialize the reading of security register */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_SECURITY_REG_CMD : MX25LM51245G_OCTA_READ_SECURITY_REG_CMD;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_READ_SECURITY_REG_CMD
+ : MX25LM51245G_OCTA_READ_SECURITY_REG_CMD;
s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES;
- s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
+ s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_ADDRESS_DTR_ENABLE
+ : HAL_OSPI_ADDRESS_DTR_DISABLE;
s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
s_command.Address = 0U;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
- s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
- s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL);
+ s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_DATA_DTR_ENABLE
+ : HAL_OSPI_DATA_DTR_DISABLE;
+ s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE)
+ ? 0U
+ : ((Rate == MX25LM51245G_DTR_TRANSFER)
+ ? DUMMY_CYCLES_REG_OCTAL_DTR
+ : DUMMY_CYCLES_REG_OCTAL);
s_command.NbData = (Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U;
s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE;
s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
@@ -1315,7 +1470,8 @@
* @param DualFlash Dual flash mode state
* @retval error status
*/
-int32_t MX25LM51245G_ReadID(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *ID)
+int32_t MX25LM51245G_ReadID(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate,
+ uint8_t *ID)
{
OSPI_RegularCmdTypeDef s_command = {0};
@@ -1327,23 +1483,37 @@
/* Initialize the read ID command */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_ID_CMD : MX25LM51245G_OCTA_READ_ID_CMD;
- s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES;
- s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_READ_ID_CMD
+ : MX25LM51245G_OCTA_READ_ID_CMD;
+ s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_ADDRESS_NONE
+ : HAL_OSPI_ADDRESS_8_LINES;
+ s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_ADDRESS_DTR_ENABLE
+ : HAL_OSPI_ADDRESS_DTR_DISABLE;
s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
s_command.Address = 0U;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
- s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
- s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL);
+ s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_DATA_DTR_ENABLE
+ : HAL_OSPI_DATA_DTR_DISABLE;
+ s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE)
+ ? 0U
+ : ((Rate == MX25LM51245G_DTR_TRANSFER)
+ ? DUMMY_CYCLES_REG_OCTAL_DTR
+ : DUMMY_CYCLES_REG_OCTAL);
s_command.NbData = 3U;
s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE;
s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
@@ -1384,15 +1554,19 @@
/* Initialize the reset enable command */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_RESET_ENABLE_CMD : MX25LM51245G_OCTA_RESET_ENABLE_CMD;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_RESET_ENABLE_CMD
+ : MX25LM51245G_OCTA_RESET_ENABLE_CMD;
s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = HAL_OSPI_DATA_NONE;
@@ -1429,15 +1603,19 @@
/* Initialize the reset enable command */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_RESET_MEMORY_CMD : MX25LM51245G_OCTA_RESET_MEMORY_CMD;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_RESET_MEMORY_CMD
+ : MX25LM51245G_OCTA_RESET_MEMORY_CMD;
s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = HAL_OSPI_DATA_NONE;
@@ -1474,14 +1652,16 @@
/* Initialize the no operation command */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_NOP_CMD : MX25LM51245G_OCTA_NOP_CMD;
s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
@@ -1507,7 +1687,8 @@
* @param Rate Transfer rate STR or DTR
* @retval error status
*/
-int32_t MX25LM51245G_EnterPowerDown(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate)
+int32_t MX25LM51245G_EnterPowerDown(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate)
{
OSPI_RegularCmdTypeDef s_command = {0};
@@ -1519,15 +1700,20 @@
/* Initialize the enter power down command */
s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
-#if defined (OCTOSPI_CR_MSEL)
- s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
-#else
s_command.FlashId = HAL_OSPI_FLASH_ID_1;
-#endif
- s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
- s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_ENTER_DEEP_POWER_DOWN_CMD : MX25LM51245G_OCTA_ENTER_DEEP_POWER_DOWN_CMD;
+
+ s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_1_LINE
+ : HAL_OSPI_INSTRUCTION_8_LINES;
+ s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER)
+ ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
+ : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+ s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE)
+ ? HAL_OSPI_INSTRUCTION_8_BITS
+ : HAL_OSPI_INSTRUCTION_16_BITS;
+ s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE)
+ ? MX25LM51245G_ENTER_DEEP_POWER_DOWN_CMD
+ : MX25LM51245G_OCTA_ENTER_DEEP_POWER_DOWN_CMD;
s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = HAL_OSPI_DATA_NONE;
@@ -1559,5 +1745,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.h b/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.h
index 2127bce..f65b226 100644
--- a/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.h
+++ b/platform/ext/target/stm/common/hal/Components/mx25lm51245g/mx25lm51245g.h
@@ -7,8 +7,8 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2018 - 2025 STMicroelectronics.
+ * All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
@@ -23,7 +23,7 @@
#define MX25LM51245G_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -257,7 +257,8 @@
/** @defgroup MX25LM51245G_Exported_Types MX25LM51245G Exported Types
* @{
*/
-typedef struct {
+typedef struct
+{
uint32_t FlashSize; /*!< Size of the flash */
uint32_t EraseSectorSize; /*!< Size of sectors for the erase operation */
uint32_t EraseSectorsNumber; /*!< Number of sectors for the erase operation */
@@ -269,23 +270,27 @@
uint32_t ProgPagesNumber; /*!< Number of pages for the program operation */
} MX25LM51245G_Info_t;
-typedef enum {
+typedef enum
+{
MX25LM51245G_SPI_MODE = 0, /*!< 1-1-1 commands, Power on H/W default setting */
MX25LM51245G_OPI_MODE /*!< 8-8-8 commands */
} MX25LM51245G_Interface_t;
-typedef enum {
+typedef enum
+{
MX25LM51245G_STR_TRANSFER = 0, /*!< Single Transfer Rate */
MX25LM51245G_DTR_TRANSFER /*!< Double Transfer Rate */
} MX25LM51245G_Transfer_t;
-typedef enum {
+typedef enum
+{
MX25LM51245G_ERASE_4K = 0, /*!< 4K size Sector erase */
MX25LM51245G_ERASE_64K, /*!< 64K size Block erase */
MX25LM51245G_ERASE_BULK /*!< Whole bulk erase */
} MX25LM51245G_Erase_t;
-typedef enum {
+typedef enum
+{
MX25LM51245G_3BYTES_SIZE = 0, /*!< 3 Bytes address mode */
MX25LM51245G_4BYTES_SIZE /*!< 4 Bytes address mode */
} MX25LM51245G_AddressSize_t;
@@ -299,16 +304,23 @@
*/
/* Function by commands combined */
int32_t MX25LM51245G_GetFlashInfo(MX25LM51245G_Info_t *pInfo);
-int32_t MX25LM51245G_AutoPollingMemReady(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
+int32_t MX25LM51245G_AutoPollingMemReady(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate);
/* Read/Write Array Commands **************************************************/
-int32_t MX25LM51245G_ReadSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t ReadAddr, uint32_t Size);
+int32_t MX25LM51245G_ReadSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t ReadAddr, uint32_t Size);
int32_t MX25LM51245G_ReadDTR(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t ReadAddr, uint32_t Size);
-int32_t MX25LM51245G_PageProgram(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t WriteAddr, uint32_t Size);
+int32_t MX25LM51245G_PageProgram(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t WriteAddr,
+ uint32_t Size);
int32_t MX25LM51245G_PageProgramDTR(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t WriteAddr, uint32_t Size);
-int32_t MX25LM51245G_BlockErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, MX25LM51245G_AddressSize_t AddressSize, uint32_t BlockAddress, MX25LM51245G_Erase_t BlockSize);
+int32_t MX25LM51245G_BlockErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate,
+ MX25LM51245G_AddressSize_t AddressSize, uint32_t BlockAddress,
+ MX25LM51245G_Erase_t BlockSize);
int32_t MX25LM51245G_ChipErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
-int32_t MX25LM51245G_EnableMemoryMappedModeSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize);
+int32_t MX25LM51245G_EnableMemoryMappedModeSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_AddressSize_t AddressSize);
int32_t MX25LM51245G_EnableMemoryMappedModeDTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode);
int32_t MX25LM51245G_Suspend(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
int32_t MX25LM51245G_Resume(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
@@ -316,23 +328,33 @@
/* Register/Setting Commands **************************************************/
int32_t MX25LM51245G_WriteEnable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
int32_t MX25LM51245G_WriteDisable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
-int32_t MX25LM51245G_ReadStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value);
-int32_t MX25LM51245G_WriteStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value);
-int32_t MX25LM51245G_WriteCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value);
-int32_t MX25LM51245G_ReadCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value);
-int32_t MX25LM51245G_WriteCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint32_t WriteAddr, uint8_t Value);
-int32_t MX25LM51245G_ReadCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint32_t ReadAddr, uint8_t *Value);
-int32_t MX25LM51245G_WriteSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value);
-int32_t MX25LM51245G_ReadSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value);
+int32_t MX25LM51245G_ReadStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate, uint8_t *Value);
+int32_t MX25LM51245G_WriteStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate, uint8_t Value);
+int32_t MX25LM51245G_WriteCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate, uint8_t Value);
+int32_t MX25LM51245G_ReadCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate, uint8_t *Value);
+int32_t MX25LM51245G_WriteCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate, uint32_t WriteAddr, uint8_t Value);
+int32_t MX25LM51245G_ReadCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate, uint32_t ReadAddr, uint8_t *Value);
+int32_t MX25LM51245G_WriteSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate, uint8_t Value);
+int32_t MX25LM51245G_ReadSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate, uint8_t *Value);
/* ID/Security Commands *******************************************************/
-int32_t MX25LM51245G_ReadID(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *ID);
+int32_t MX25LM51245G_ReadID(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate,
+ uint8_t *ID);
/* Reset Commands *************************************************************/
int32_t MX25LM51245G_ResetEnable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
int32_t MX25LM51245G_ResetMemory(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
int32_t MX25LM51245G_NoOperation(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
-int32_t MX25LM51245G_EnterPowerDown(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
+int32_t MX25LM51245G_EnterPowerDown(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode,
+ MX25LM51245G_Transfer_t Rate);
/**
* @}
@@ -355,5 +377,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u585xx.h b/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u585xx.h
index 0a66164..a0ffef9 100644
--- a/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u585xx.h
+++ b/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u585xx.h
@@ -7,18 +7,18 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripheral’s registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
+ * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -68,10 +68,10 @@
/* =========================================== STM32U585xx Specific Interrupt Numbers ================================= */
WWDG_IRQn = 0, /*!< Window WatchDog interrupt */
- PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */
+ PVD_PVM_IRQn = 1, /*!< PVD/PVM through EXTI Line detection Interrupt */
RTC_IRQn = 2, /*!< RTC non-secure interrupt */
RTC_S_IRQn = 3, /*!< RTC secure interrupt */
- TAMP_IRQn = 4, /*!< Tamper non-secure interrupt */
+ TAMP_IRQn = 4, /*!< Tamper global interrupt */
RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */
FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */
FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */
@@ -192,6 +192,7 @@
MDF1_FLT5_IRQn = 122, /*!< MDF1 Filter 5 global interrupt */
CORDIC_IRQn = 123, /*!< CORDIC global interrupt */
FMAC_IRQn = 124, /*!< FMAC global interrupt */
+ LSECSSD_IRQn = 125, /*!< LSECSSD and MSI_PLL_UNLOCK global interrupts */
} IRQn_Type;
/* =========================================================================================================================== */
@@ -783,7 +784,7 @@
*/
typedef struct
{
- __IO uint32_t CSR; /*!< Comparator control/status register , Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */
} COMP_TypeDef;
typedef struct
@@ -802,8 +803,12 @@
__IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
} OPAMP_TypeDef;
-/*Aliases */
-#define OPAMP_Common_TypeDef OPAMP_TypeDef
+typedef struct
+{
+ __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to
+ several OPAMP instances, Address offset: 0x00 */
+} OPAMP_Common_TypeDef;
+
/**
* @brief MDF/ADF
@@ -850,56 +855,59 @@
typedef struct
{
- __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */
- uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */
- __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */
- __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */
- __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */
- __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */
- uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
- __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */
- __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */
- uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
- __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */
- uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */
- __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */
- uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */
- __IO uint32_t DR; /*!< OCTOPSI Data register, Address offset: 0x050 */
- uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
- __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */
- uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */
- __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */
- uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */
- __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */
- uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
- __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */
- uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */
- __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */
- uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */
- __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */
- uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
- __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */
- uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
- __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */
- uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */
- __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */
- uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */
- __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */
- uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */
- __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */
- uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */
- __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */
- uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */
- __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */
- uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */
- __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */
- uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */
- __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */
- uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */
- __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
- uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
- __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
-} OCTOSPI_TypeDef;
+ __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */
+ __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */
+ __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */
+ __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */
+ __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
+ __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */
+ __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
+ __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */
+ __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */
+ __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */
+ uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
+ __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */
+ uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */
+ __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */
+ __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */
+ uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
+ __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */
+ uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */
+ __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */
+ uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */
+ __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */
+ uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
+ __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */
+ uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
+ __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */
+ uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */
+ __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */
+ uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */
+ __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */
+ __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */
+ uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */
+ __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */
+ uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */
+ __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */
+ uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */
+ __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */
+ uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */
+ __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */
+ uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */
+ __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */
+ uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
+ __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
+} XSPI_TypeDef;
+
+typedef XSPI_TypeDef OCTOSPI_TypeDef;
+
/**
* @brief OTFDEC register
@@ -928,14 +936,17 @@
__IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */
} OTFDEC_TypeDef;
+
/**
- * @brief OCTO Serial Peripheral Interface IO Manager
+ * @brief Serial Peripheral Interface IO Manager
*/
typedef struct
{
- __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */
- __IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */
-} OCTOSPIM_TypeDef;
+ __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */
+ __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */
+} XSPIM_TypeDef;
+
+typedef XSPIM_TypeDef OCTOSPIM_TypeDef;
/**
* @brief Power Control
@@ -1285,7 +1296,6 @@
/**
* @brief Delay Block DLYB
*/
-
typedef struct
{
__IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
@@ -1299,7 +1309,7 @@
{
__IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */
__IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */
- uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */
+ __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */
__IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */
__IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */
__IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */
@@ -1558,7 +1568,7 @@
__IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/
__IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/
__IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
- __IO uint32_t PW; /*!< ADC power register, Address offset: 0x44 */
+ __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */
uint32_t RESERVED1; /*!< Reserved, 0x048 */
__IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/
uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */
@@ -1593,6 +1603,10 @@
__IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */
} ADC_Common_TypeDef;
+
+/* Legacy registers naming */
+#define PW PWRR
+
/**
* @brief CORDIC
*/
@@ -1830,7 +1844,6 @@
#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL)
#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL)
#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL)
-
#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL)
#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL)
#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL)
@@ -1855,7 +1868,7 @@
#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08308UL)
#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL)
#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL)
-#define OTG_FS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL)
+#define USB_OTG_FS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL)
#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL)
#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL)
#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL)
@@ -1967,7 +1980,7 @@
#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL)
#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL)
#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL)
-#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4300UL)
+#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL)
#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL)
#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL)
#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL)
@@ -2040,7 +2053,7 @@
#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08308UL)
#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL)
#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL)
-#define OTG_FS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL)
+#define USB_OTG_FS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL)
#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL)
#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL)
#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL)
@@ -2048,7 +2061,6 @@
#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL)
#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL)
#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL)
-#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */
#define OTFDEC1_BASE_S (AHB2PERIPH_BASE_S + 0xA5000UL)
#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL)
#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL)
@@ -2059,6 +2071,7 @@
#define OTFDEC2_REGION2_BASE_S (OTFDEC2_BASE_S + 0x50UL)
#define OTFDEC2_REGION3_BASE_S (OTFDEC2_BASE_S + 0x80UL)
#define OTFDEC2_REGION4_BASE_S (OTFDEC2_BASE_S + 0xB0UL)
+#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */
#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL)
#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL)
#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL)
@@ -2238,6 +2251,7 @@
#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS)
#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS)
#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS)
+#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS)
#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS)
#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS)
#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS)
@@ -2304,7 +2318,7 @@
#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS)
#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS)
#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS)
-#define USB_OTG_FS_NS ((USB_OTG_GlobalTypeDef *) OTG_FS_BASE_NS)
+#define USB_OTG_FS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_BASE_NS)
#define AES_NS ((AES_TypeDef *) AES_BASE_NS)
#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS)
#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS)
@@ -2321,7 +2335,6 @@
#define OTFDEC2_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_NS)
#define OTFDEC2_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_NS)
#define OTFDEC2_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_NS)
-#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS)
#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS)
#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS)
#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS)
@@ -2331,6 +2344,7 @@
#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS)
#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS)
#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS)
+#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS)
#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS)
#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS)
@@ -2402,6 +2416,7 @@
#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S)
#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S)
#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S)
+#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S)
#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S)
#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S)
#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S)
@@ -2468,7 +2483,7 @@
#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S)
#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S)
#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S)
-#define USB_OTG_FS_S ((USB_OTG_GlobalTypeDef *) OTG_FS_BASE_S)
+#define USB_OTG_FS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_BASE_S)
#define AES_S ((AES_TypeDef *) AES_BASE_S)
#define HASH_S ((HASH_TypeDef *) HASH_BASE_S)
#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S)
@@ -2485,7 +2500,6 @@
#define OTFDEC2_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_S)
#define OTFDEC2_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_S)
#define OTFDEC2_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_S)
-#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S)
#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S)
#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S)
#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S)
@@ -2495,6 +2509,7 @@
#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S)
#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S)
#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S)
+#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S)
#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S)
#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S)
@@ -2809,6 +2824,9 @@
#define OPAMP2 OPAMP2_S
#define OPAMP2_BASE OPAMP2_BASE_S
+#define OPAMP12_COMMON OPAMP12_COMMON_S
+#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S
+
#define LPTIM1 LPTIM1_S
#define LPTIM1_BASE LPTIM1_BASE_S
@@ -3128,7 +3146,6 @@
#define GPIOI GPIOI_NS
#define GPIOI_BASE GPIOI_BASE_NS
-
#define LPGPIO1 LPGPIO1_NS
#define LPGPIO1_BASE LPGPIO1_BASE_NS
@@ -3286,6 +3303,9 @@
#define OPAMP2 OPAMP2_NS
#define OPAMP2_BASE OPAMP2_BASE_NS
+#define OPAMP12_COMMON OPAMP12_COMMON_NS
+#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS
+
#define LPTIM1 LPTIM1_NS
#define LPTIM1_BASE LPTIM1_BASE_NS
@@ -3472,9 +3492,17 @@
#define ADF1_Filter0 ADF1_Filter0_NS
#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS
-
#endif
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/******************************************************************************/
/* */
/* Analog to Digital Converter */
@@ -3587,18 +3615,21 @@
#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
+#define ADC_CR_CALINDEX_Pos (24U)
+#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */
+#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */
#define ADC_CR_CALINDEX0_Pos (24U)
#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */
-#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC Linearity calibration ready Word 3 */
+#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */
#define ADC_CR_CALINDEX1_Pos (25U)
#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */
-#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC Linearity calibration ready Word 4 */
+#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */
#define ADC_CR_CALINDEX2_Pos (26U)
#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */
-#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC Linearity calibration ready Word 5 */
+#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */
#define ADC_CR_CALINDEX3_Pos (27U)
#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */
-#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC Linearity calibration ready Word 6 */
+#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */
#define ADC_CR_ADVREGEN_Pos (28U)
#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
@@ -4058,7 +4089,7 @@
#define ADC_HTR_AWDFILT_Pos (29U)
#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */
-#define ADC_HTR_AWDFILT ADC_HTR_HT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */
+#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */
#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */
#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */
#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */
@@ -4224,18 +4255,32 @@
#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
/******************** Bit definition for ADC_PW register ********************/
-#define ADC4_PW_AUTOFF_Pos (0U)
-#define ADC4_PW_AUTOFF_Msk (0x1UL << ADC4_PW_AUTOFF_Pos) /*!< 0x00000001 */
-#define ADC4_PW_AUTOFF ADC4_PW_AUTOFF_Msk /*!< ADC Auto-Off mode */
-#define ADC4_PW_DPD_Pos (1U)
-#define ADC4_PW_DPD_Msk (0x1UL << ADC4_PW_DPD_Pos) /*!< 0x00000002 */
-#define ADC4_PW_DPD ADC4_PW_DPD_Msk /*!< ADC Deep Power mode */
-#define ADC4_PW_VREFPROT_Pos (2U)
-#define ADC4_PW_VREFPROT_Msk (0x1UL << ADC4_PW_VREFPROT_Pos) /*!< 0x00000004 */
-#define ADC4_PW_VREFPROT ADC4_PW_VREFPROT_Msk /*!< ADC Vref protection */
-#define ADC4_PW_VREFSECSMP_Pos (3U)
-#define ADC4_PW_VREFSECSMP_Msk (0x1UL << ADC4_PW_VREFSECSMP_Pos) /*!< 0x00000008 */
-#define ADC4_PW_VREFSECSMP ADC4_PW_VREFSECSMP_Msk /*!< ADC Vref Second Sample */
+#define ADC4_PWRR_AUTOFF_Pos (0U)
+#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */
+#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */
+#define ADC4_PWRR_DPD_Pos (1U)
+#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */
+#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */
+#define ADC4_PWRR_VREFPROT_Pos (2U)
+#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */
+#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */
+#define ADC4_PWRR_VREFSECSMP_Pos (3U)
+#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */
+#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */
+
+/* Legacy definitions */
+#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos
+#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk
+#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF
+#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos
+#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk
+#define ADC4_PW_DPD ADC4_PWRR_DPD
+#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos
+#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk
+#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT
+#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos
+#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk
+#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP
/******************** Bit definition for ADC_JSQR register ********************/
#define ADC_JSQR_JL_Pos (0U)
@@ -4346,7 +4391,7 @@
/******************** Bit definition for ADC_OFR2 register ********************/
#define ADC_OFR2_OFFSET2_Pos (0U)
-#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */
#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
@@ -4378,11 +4423,11 @@
#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
#define ADC_OFR2_USAT_Pos (25U)
#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */
-#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */
+#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */
-#define ADC_OFR2_SSAT_Pos (26U)
-#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */
-#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */
+#define ADC_OFR2_SSAT_Pos (26U)
+#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */
+#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */
#define ADC_OFR2_OFFSET2_CH_Pos (27U)
#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
@@ -4395,7 +4440,7 @@
/******************** Bit definition for ADC_OFR3 register ********************/
#define ADC_OFR3_OFFSET3_Pos (0U)
-#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */
#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
@@ -4444,7 +4489,7 @@
/******************** Bit definition for ADC_OFR4 register ********************/
#define ADC_OFR4_OFFSET4_Pos (0U)
-#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */
#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
@@ -5841,6 +5886,9 @@
#define AES_IER_KEIE_Pos (2U)
#define AES_IER_KEIE_Msk (0x1UL << AES_IER_KEIE_Pos) /*!< 0x00000004 */
#define AES_IER_KEIE AES_IER_KEIE_Msk /*!< Key error interrupt enable */
+#define AES_IER_RNGEIE_Pos (3U)
+#define AES_IER_RNGEIE_Msk (0x1UL << AES_IER_RNGEIE_Pos) /*!< 0x00000008 */
+#define AES_IER_RNGEIE AES_IER_RNGEIE_Msk /*!< Rng error interrupt enable */
/******************* Bit definition for AES_ISR register ******************/
#define AES_ISR_CCF_Pos (0U)
@@ -5852,6 +5900,9 @@
#define AES_ISR_KEIF_Pos (2U)
#define AES_ISR_KEIF_Msk (0x1UL << AES_ISR_KEIF_Pos) /*!< 0x00000004 */
#define AES_ISR_KEIF AES_ISR_KEIF_Msk /*!< Key error interrupt flag */
+#define AES_ISR_RNGEIF_Pos (3U)
+#define AES_ISR_RNGEIF_Msk (0x1UL << AES_ISR_RNGEIF_Pos) /*!< 0x00000008 */
+#define AES_ISR_RNGEIF AES_ISR_RNGEIF_Msk /*!< Rng error interrupt flag */
/******************* Bit definition for AES_ICR register ******************/
#define AES_ICR_CCF_Pos (0U)
@@ -5863,6 +5914,9 @@
#define AES_ICR_KEIF_Pos (2U)
#define AES_ICR_KEIF_Msk (0x1UL << AES_ICR_KEIF_Pos) /*!< 0x00000004 */
#define AES_ICR_KEIF AES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */
+#define AES_ICR_RNGEIF_Pos (3U)
+#define AES_ICR_RNGEIF_Msk (0x1UL << AES_ICR_RNGEIF_Pos) /*!< 0x00000008 */
+#define AES_ICR_RNGEIF AES_ICR_RNGEIF_Msk /*!< Rng error interrupt flag clear */
/******************************************************************************/
/* */
@@ -6029,9 +6083,6 @@
#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos)
#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
-#define DBGMCU_APB1FZR2_DBG_FDCAN_STOP_Pos (9U)
-#define DBGMCU_APB1FZR2_DBG_FDCAN_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_FDCAN_STOP_Pos)
-#define DBGMCU_APB1FZR2_DBG_FDCAN_STOP DBGMCU_APB1FZR2_DBG_FDCAN_STOP_Msk
/******************** Bit definition for DBGMCU_APB2FZR register ***********/
#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U)
@@ -6633,7 +6684,7 @@
#define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */
#define DMA_CSR_SUSPF_Pos (13U)
#define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */
-#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< User setting error flag */
+#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< Completed suspension flag */
#define DMA_CSR_TOF_Pos (14U)
#define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */
#define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun flag */
@@ -6967,11 +7018,6 @@
#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
-#define DMA2D_FGPFCCR_CSS_Pos (18U)
-#define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x000C0000 */
-#define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */
-#define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00040000 */
-#define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00080000 */
#define DMA2D_FGPFCCR_AI_Pos (20U)
#define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */
@@ -7223,9 +7269,6 @@
#define EXTI_RTSR1_RT23_Pos (23U)
#define EXTI_RTSR1_RT23_Msk (0x1UL << EXTI_RTSR1_RT23_Pos) /*!< 0x00800000 */
#define EXTI_RTSR1_RT23 EXTI_RTSR1_RT23_Msk /*!< Rising trigger configuration for input line 23 */
-#define EXTI_RTSR1_RT24_Pos (24U)
-#define EXTI_RTSR1_RT24_Msk (0x1UL << EXTI_RTSR1_RT24_Pos) /*!< 0x01000000 */
-#define EXTI_RTSR1_RT24 EXTI_RTSR1_RT24_Msk /*!< Rising trigger configuration for input line 24 */
/****************** Bit definition for EXTI_FTSR1 register ******************/
#define EXTI_FTSR1_FT0_Pos (0U)
@@ -7300,9 +7343,6 @@
#define EXTI_FTSR1_FT23_Pos (23U)
#define EXTI_FTSR1_FT23_Msk (0x1UL << EXTI_FTSR1_FT23_Pos) /*!< 0x00800000 */
#define EXTI_FTSR1_FT23 EXTI_FTSR1_FT23_Msk /*!< Falling trigger configuration for input line 23 */
-#define EXTI_FTSR1_FT24_Pos (24U)
-#define EXTI_FTSR1_FT24_Msk (0x1UL << EXTI_FTSR1_FT24_Pos) /*!< 0x01000000 */
-#define EXTI_FTSR1_FT24 EXTI_FTSR1_FT24_Msk /*!< Falling trigger configuration for input line 24 */
/****************** Bit definition for EXTI_SWIER1 register *****************/
#define EXTI_SWIER1_SWI0_Pos (0U)
@@ -7377,9 +7417,6 @@
#define EXTI_SWIER1_SWI23_Pos (23U)
#define EXTI_SWIER1_SWI23_Msk (0x1UL << EXTI_SWIER1_SWI23_Pos) /*!< 0x00800000 */
#define EXTI_SWIER1_SWI23 EXTI_SWIER1_SWI23_Msk /*!< Software Interrupt on line 23 */
-#define EXTI_SWIER1_SWI24_Pos (24U)
-#define EXTI_SWIER1_SWI24_Msk (0x1UL << EXTI_SWIER1_SWI24_Pos) /*!< 0x01000000 */
-#define EXTI_SWIER1_SWI24 EXTI_SWIER1_SWI24_Msk /*!< Software Interrupt on line 24 */
/******************* Bit definition for EXTI_RPR1 register ******************/
#define EXTI_RPR1_RPIF0_Pos (0U)
@@ -7454,9 +7491,6 @@
#define EXTI_RPR1_RPIF23_Pos (23U)
#define EXTI_RPR1_RPIF23_Msk (0x1UL << EXTI_RPR1_RPIF23_Pos) /*!< 0x00800000 */
#define EXTI_RPR1_RPIF23 EXTI_RPR1_RPIF23_Msk /*!< Rising Pending Interrupt Flag on line 23 */
-#define EXTI_RPR1_RPIF24_Pos (24U)
-#define EXTI_RPR1_RPIF24_Msk (0x1UL << EXTI_RPR1_RPIF24_Pos) /*!< 0x01000000 */
-#define EXTI_RPR1_RPIF24 EXTI_RPR1_RPIF24_Msk /*!< Rising Pending Interrupt Flag on line 24 */
/******************* Bit definition for EXTI_FPR1 register ******************/
#define EXTI_FPR1_FPIF0_Pos (0U)
@@ -7531,163 +7565,154 @@
#define EXTI_FPR1_FPIF23_Pos (23U)
#define EXTI_FPR1_FPIF23_Msk (0x1UL << EXTI_FPR1_FPIF23_Pos) /*!< 0x00800000 */
#define EXTI_FPR1_FPIF23 EXTI_FPR1_FPIF23_Msk /*!< Falling Pending Interrupt Flag on line 23 */
-#define EXTI_FPR1_FPIF24_Pos (24U)
-#define EXTI_FPR1_FPIF24_Msk (0x1UL << EXTI_FPR1_FPIF24_Pos) /*!< 0x01000000 */
-#define EXTI_FPR1_FPIF24 EXTI_FPR1_FPIF24_Msk /*!< Falling Pending Interrupt Flag on line 24 */
-/******************* Bit definition for EXTI_SECENR1 register ******************/
-#define EXTI_SECENR1_RPIF0_Pos (0U)
-#define EXTI_SECENR1_RPIF0_Msk (0x1UL << EXTI_SECENR1_RPIF0_Pos) /*!< 0x00000001 */
-#define EXTI_SECENR1_RPIF0 EXTI_SECENR1_RPIF0_Msk /*!< Security enable on line 0 */
-#define EXTI_SECENR1_RPIF1_Pos (1U)
-#define EXTI_SECENR1_RPIF1_Msk (0x1UL << EXTI_SECENR1_RPIF1_Pos) /*!< 0x00000002 */
-#define EXTI_SECENR1_RPIF1 EXTI_SECENR1_RPIF1_Msk /*!< Security enable on line 1 */
-#define EXTI_SECENR1_RPIF2_Pos (2U)
-#define EXTI_SECENR1_RPIF2_Msk (0x1UL << EXTI_SECENR1_RPIF2_Pos) /*!< 0x00000004 */
-#define EXTI_SECENR1_RPIF2 EXTI_SECENR1_RPIF2_Msk /*!< Security enable on line 2 */
-#define EXTI_SECENR1_RPIF3_Pos (3U)
-#define EXTI_SECENR1_RPIF3_Msk (0x1UL << EXTI_SECENR1_RPIF3_Pos) /*!< 0x00000008 */
-#define EXTI_SECENR1_RPIF3 EXTI_SECENR1_RPIF3_Msk /*!< Security enable on line 3 */
-#define EXTI_SECENR1_RPIF4_Pos (4U)
-#define EXTI_SECENR1_RPIF4_Msk (0x1UL << EXTI_SECENR1_RPIF4_Pos) /*!< 0x00000010 */
-#define EXTI_SECENR1_RPIF4 EXTI_SECENR1_RPIF4_Msk /*!< Security enable on line 4 */
-#define EXTI_SECENR1_RPIF5_Pos (5U)
-#define EXTI_SECENR1_RPIF5_Msk (0x1UL << EXTI_SECENR1_RPIF5_Pos) /*!< 0x00000020 */
-#define EXTI_SECENR1_RPIF5 EXTI_SECENR1_RPIF5_Msk /*!< Security enable on line 5 */
-#define EXTI_SECENR1_RPIF6_Pos (6U)
-#define EXTI_SECENR1_RPIF6_Msk (0x1UL << EXTI_SECENR1_RPIF6_Pos) /*!< 0x00000040 */
-#define EXTI_SECENR1_RPIF6 EXTI_SECENR1_RPIF6_Msk /*!< Security enable on line 6 */
-#define EXTI_SECENR1_RPIF7_Pos (7U)
-#define EXTI_SECENR1_RPIF7_Msk (0x1UL << EXTI_SECENR1_RPIF7_Pos) /*!< 0x00000080 */
-#define EXTI_SECENR1_RPIF7 EXTI_SECENR1_RPIF7_Msk /*!< Security enable on line 7 */
-#define EXTI_SECENR1_RPIF8_Pos (8U)
-#define EXTI_SECENR1_RPIF8_Msk (0x1UL << EXTI_SECENR1_RPIF8_Pos) /*!< 0x00000100 */
-#define EXTI_SECENR1_RPIF8 EXTI_SECENR1_RPIF8_Msk /*!< Security enable on line 8 */
-#define EXTI_SECENR1_RPIF9_Pos (9U)
-#define EXTI_SECENR1_RPIF9_Msk (0x1UL << EXTI_SECENR1_RPIF9_Pos) /*!< 0x00000200 */
-#define EXTI_SECENR1_RPIF9 EXTI_SECENR1_RPIF9_Msk /*!< Security enable on line 9 */
-#define EXTI_SECENR1_RPIF10_Pos (10U)
-#define EXTI_SECENR1_RPIF10_Msk (0x1UL << EXTI_SECENR1_RPIF10_Pos) /*!< 0x00000400 */
-#define EXTI_SECENR1_RPIF10 EXTI_SECENR1_RPIF10_Msk /*!< Security enable on line 10 */
-#define EXTI_SECENR1_RPIF11_Pos (11U)
-#define EXTI_SECENR1_RPIF11_Msk (0x1UL << EXTI_SECENR1_RPIF11_Pos) /*!< 0x00000800 */
-#define EXTI_SECENR1_RPIF11 EXTI_SECENR1_RPIF11_Msk /*!< Security enable on line 11 */
-#define EXTI_SECENR1_RPIF12_Pos (12U)
-#define EXTI_SECENR1_RPIF12_Msk (0x1UL << EXTI_SECENR1_RPIF12_Pos) /*!< 0x00001000 */
-#define EXTI_SECENR1_RPIF12 EXTI_SECENR1_RPIF12_Msk /*!< Security enable on line 12 */
-#define EXTI_SECENR1_RPIF13_Pos (13U)
-#define EXTI_SECENR1_RPIF13_Msk (0x1UL << EXTI_SECENR1_RPIF13_Pos) /*!< 0x00002000 */
-#define EXTI_SECENR1_RPIF13 EXTI_SECENR1_RPIF13_Msk /*!< Security enable on line 13 */
-#define EXTI_SECENR1_RPIF14_Pos (14U)
-#define EXTI_SECENR1_RPIF14_Msk (0x1UL << EXTI_SECENR1_RPIF14_Pos) /*!< 0x00004000 */
-#define EXTI_SECENR1_RPIF14 EXTI_SECENR1_RPIF14_Msk /*!< Security enable on line 14 */
-#define EXTI_SECENR1_RPIF15_Pos (15U)
-#define EXTI_SECENR1_RPIF15_Msk (0x1UL << EXTI_SECENR1_RPIF15_Pos) /*!< 0x00008000 */
-#define EXTI_SECENR1_RPIF15 EXTI_SECENR1_RPIF15_Msk /*!< Security enable on line 15 */
-#define EXTI_SECENR1_RPIF16_Pos (16U)
-#define EXTI_SECENR1_RPIF16_Msk (0x1UL << EXTI_SECENR1_RPIF16_Pos) /*!< 0x00010000 */
-#define EXTI_SECENR1_RPIF16 EXTI_SECENR1_RPIF16_Msk /*!< Security enable on line 16 */
-#define EXTI_SECENR1_RPIF17_Pos (17U)
-#define EXTI_SECENR1_RPIF17_Msk (0x1UL << EXTI_SECENR1_RPIF17_Pos) /*!< 0x00020000 */
-#define EXTI_SECENR1_RPIF17 EXTI_SECENR1_RPIF17_Msk /*!< Security enable on line 17 */
-#define EXTI_SECENR1_RPIF18_Pos (18U)
-#define EXTI_SECENR1_RPIF18_Msk (0x1UL << EXTI_SECENR1_RPIF18_Pos) /*!< 0x00040000 */
-#define EXTI_SECENR1_RPIF18 EXTI_SECENR1_RPIF18_Msk /*!< Security enable on line 18 */
-#define EXTI_SECENR1_RPIF19_Pos (19U)
-#define EXTI_SECENR1_RPIF19_Msk (0x1UL << EXTI_SECENR1_RPIF19_Pos) /*!< 0x00080000 */
-#define EXTI_SECENR1_RPIF19 EXTI_SECENR1_RPIF19_Msk /*!< Security enable on line 19 */
-#define EXTI_SECENR1_RPIF20_Pos (20U)
-#define EXTI_SECENR1_RPIF20_Msk (0x1UL << EXTI_SECENR1_RPIF20_Pos) /*!< 0x00100000 */
-#define EXTI_SECENR1_RPIF20 EXTI_SECENR1_RPIF20_Msk /*!< Security enable on line 20 */
-#define EXTI_SECENR1_RPIF21_Pos (21U)
-#define EXTI_SECENR1_RPIF21_Msk (0x1UL << EXTI_SECENR1_RPIF21_Pos) /*!< 0x00200000 */
-#define EXTI_SECENR1_RPIF21 EXTI_SECENR1_RPIF21_Msk /*!< Security enable on line 21 */
-#define EXTI_SECENR1_RPIF22_Pos (22U)
-#define EXTI_SECENR1_RPIF22_Msk (0x1UL << EXTI_SECENR1_RPIF22_Pos) /*!< 0x00400000 */
-#define EXTI_SECENR1_RPIF22 EXTI_SECENR1_RPIF22_Msk /*!< Security enable on line 22 */
-#define EXTI_SECENR1_RPIF23_Pos (23U)
-#define EXTI_SECENR1_RPIF23_Msk (0x1UL << EXTI_SECENR1_RPIF23_Pos) /*!< 0x00800000 */
-#define EXTI_SECENR1_RPIF23 EXTI_SECENR1_RPIF23_Msk /*!< Security enable on line 23 */
-#define EXTI_SECENR1_RPIF24_Pos (24U)
-#define EXTI_SECENR1_RPIF24_Msk (0x1UL << EXTI_SECENR1_RPIF24_Pos) /*!< 0x01000000 */
-#define EXTI_SECENR1_RPIF24 EXTI_SECENR1_RPIF24_Msk /*!< Security enable on line 24 */
+/******************* Bit definition for EXTI_SECCFGR1 register ******************/
+#define EXTI_SECCFGR1_SEC0_Pos (0U)
+#define EXTI_SECCFGR1_SEC0_Msk (0x1UL << EXTI_SECCFGR1_SEC0_Pos) /*!< 0x00000001 */
+#define EXTI_SECCFGR1_SEC0 EXTI_SECCFGR1_SEC0_Msk /*!< Security enable on line 0 */
+#define EXTI_SECCFGR1_SEC1_Pos (1U)
+#define EXTI_SECCFGR1_SEC1_Msk (0x1UL << EXTI_SECCFGR1_SEC1_Pos) /*!< 0x00000002 */
+#define EXTI_SECCFGR1_SEC1 EXTI_SECCFGR1_SEC1_Msk /*!< Security enable on line 1 */
+#define EXTI_SECCFGR1_SEC2_Pos (2U)
+#define EXTI_SECCFGR1_SEC2_Msk (0x1UL << EXTI_SECCFGR1_SEC2_Pos) /*!< 0x00000004 */
+#define EXTI_SECCFGR1_SEC2 EXTI_SECCFGR1_SEC2_Msk /*!< Security enable on line 2 */
+#define EXTI_SECCFGR1_SEC3_Pos (3U)
+#define EXTI_SECCFGR1_SEC3_Msk (0x1UL << EXTI_SECCFGR1_SEC3_Pos) /*!< 0x00000008 */
+#define EXTI_SECCFGR1_SEC3 EXTI_SECCFGR1_SEC3_Msk /*!< Security enable on line 3 */
+#define EXTI_SECCFGR1_SEC4_Pos (4U)
+#define EXTI_SECCFGR1_SEC4_Msk (0x1UL << EXTI_SECCFGR1_SEC4_Pos) /*!< 0x00000010 */
+#define EXTI_SECCFGR1_SEC4 EXTI_SECCFGR1_SEC4_Msk /*!< Security enable on line 4 */
+#define EXTI_SECCFGR1_SEC5_Pos (5U)
+#define EXTI_SECCFGR1_SEC5_Msk (0x1UL << EXTI_SECCFGR1_SEC5_Pos) /*!< 0x00000020 */
+#define EXTI_SECCFGR1_SEC5 EXTI_SECCFGR1_SEC5_Msk /*!< Security enable on line 5 */
+#define EXTI_SECCFGR1_SEC6_Pos (6U)
+#define EXTI_SECCFGR1_SEC6_Msk (0x1UL << EXTI_SECCFGR1_SEC6_Pos) /*!< 0x00000040 */
+#define EXTI_SECCFGR1_SEC6 EXTI_SECCFGR1_SEC6_Msk /*!< Security enable on line 6 */
+#define EXTI_SECCFGR1_SEC7_Pos (7U)
+#define EXTI_SECCFGR1_SEC7_Msk (0x1UL << EXTI_SECCFGR1_SEC7_Pos) /*!< 0x00000080 */
+#define EXTI_SECCFGR1_SEC7 EXTI_SECCFGR1_SEC7_Msk /*!< Security enable on line 7 */
+#define EXTI_SECCFGR1_SEC8_Pos (8U)
+#define EXTI_SECCFGR1_SEC8_Msk (0x1UL << EXTI_SECCFGR1_SEC8_Pos) /*!< 0x00000100 */
+#define EXTI_SECCFGR1_SEC8 EXTI_SECCFGR1_SEC8_Msk /*!< Security enable on line 8 */
+#define EXTI_SECCFGR1_SEC9_Pos (9U)
+#define EXTI_SECCFGR1_SEC9_Msk (0x1UL << EXTI_SECCFGR1_SEC9_Pos) /*!< 0x00000200 */
+#define EXTI_SECCFGR1_SEC9 EXTI_SECCFGR1_SEC9_Msk /*!< Security enable on line 9 */
+#define EXTI_SECCFGR1_SEC10_Pos (10U)
+#define EXTI_SECCFGR1_SEC10_Msk (0x1UL << EXTI_SECCFGR1_SEC10_Pos) /*!< 0x00000400 */
+#define EXTI_SECCFGR1_SEC10 EXTI_SECCFGR1_SEC10_Msk /*!< Security enable on line 10 */
+#define EXTI_SECCFGR1_SEC11_Pos (11U)
+#define EXTI_SECCFGR1_SEC11_Msk (0x1UL << EXTI_SECCFGR1_SEC11_Pos) /*!< 0x00000800 */
+#define EXTI_SECCFGR1_SEC11 EXTI_SECCFGR1_SEC11_Msk /*!< Security enable on line 11 */
+#define EXTI_SECCFGR1_SEC12_Pos (12U)
+#define EXTI_SECCFGR1_SEC12_Msk (0x1UL << EXTI_SECCFGR1_SEC12_Pos) /*!< 0x00001000 */
+#define EXTI_SECCFGR1_SEC12 EXTI_SECCFGR1_SEC12_Msk /*!< Security enable on line 12 */
+#define EXTI_SECCFGR1_SEC13_Pos (13U)
+#define EXTI_SECCFGR1_SEC13_Msk (0x1UL << EXTI_SECCFGR1_SEC13_Pos) /*!< 0x00002000 */
+#define EXTI_SECCFGR1_SEC13 EXTI_SECCFGR1_SEC13_Msk /*!< Security enable on line 13 */
+#define EXTI_SECCFGR1_SEC14_Pos (14U)
+#define EXTI_SECCFGR1_SEC14_Msk (0x1UL << EXTI_SECCFGR1_SEC14_Pos) /*!< 0x00004000 */
+#define EXTI_SECCFGR1_SEC14 EXTI_SECCFGR1_SEC14_Msk /*!< Security enable on line 14 */
+#define EXTI_SECCFGR1_SEC15_Pos (15U)
+#define EXTI_SECCFGR1_SEC15_Msk (0x1UL << EXTI_SECCFGR1_SEC15_Pos) /*!< 0x00008000 */
+#define EXTI_SECCFGR1_SEC15 EXTI_SECCFGR1_SEC15_Msk /*!< Security enable on line 15 */
+#define EXTI_SECCFGR1_SEC16_Pos (16U)
+#define EXTI_SECCFGR1_SEC16_Msk (0x1UL << EXTI_SECCFGR1_SEC16_Pos) /*!< 0x00010000 */
+#define EXTI_SECCFGR1_SEC16 EXTI_SECCFGR1_SEC16_Msk /*!< Security enable on line 16 */
+#define EXTI_SECCFGR1_SEC17_Pos (17U)
+#define EXTI_SECCFGR1_SEC17_Msk (0x1UL << EXTI_SECCFGR1_SEC17_Pos) /*!< 0x00020000 */
+#define EXTI_SECCFGR1_SEC17 EXTI_SECCFGR1_SEC17_Msk /*!< Security enable on line 17 */
+#define EXTI_SECCFGR1_SEC18_Pos (18U)
+#define EXTI_SECCFGR1_SEC18_Msk (0x1UL << EXTI_SECCFGR1_SEC18_Pos) /*!< 0x00040000 */
+#define EXTI_SECCFGR1_SEC18 EXTI_SECCFGR1_SEC18_Msk /*!< Security enable on line 18 */
+#define EXTI_SECCFGR1_SEC19_Pos (19U)
+#define EXTI_SECCFGR1_SEC19_Msk (0x1UL << EXTI_SECCFGR1_SEC19_Pos) /*!< 0x00080000 */
+#define EXTI_SECCFGR1_SEC19 EXTI_SECCFGR1_SEC19_Msk /*!< Security enable on line 19 */
+#define EXTI_SECCFGR1_SEC20_Pos (20U)
+#define EXTI_SECCFGR1_SEC20_Msk (0x1UL << EXTI_SECCFGR1_SEC20_Pos) /*!< 0x00100000 */
+#define EXTI_SECCFGR1_SEC20 EXTI_SECCFGR1_SEC20_Msk /*!< Security enable on line 20 */
+#define EXTI_SECCFGR1_SEC21_Pos (21U)
+#define EXTI_SECCFGR1_SEC21_Msk (0x1UL << EXTI_SECCFGR1_SEC21_Pos) /*!< 0x00200000 */
+#define EXTI_SECCFGR1_SEC21 EXTI_SECCFGR1_SEC21_Msk /*!< Security enable on line 21 */
+#define EXTI_SECCFGR1_SEC22_Pos (22U)
+#define EXTI_SECCFGR1_SEC22_Msk (0x1UL << EXTI_SECCFGR1_SEC22_Pos) /*!< 0x00400000 */
+#define EXTI_SECCFGR1_SEC22 EXTI_SECCFGR1_SEC22_Msk /*!< Security enable on line 22 */
+#define EXTI_SECCFGR1_SEC23_Pos (23U)
+#define EXTI_SECCFGR1_SEC23_Msk (0x1UL << EXTI_SECCFGR1_SEC23_Pos) /*!< 0x00800000 */
+#define EXTI_SECCFGR1_SEC23 EXTI_SECCFGR1_SEC23_Msk /*!< Security enable on line 23 */
-/******************* Bit definition for EXTI_PRIVENR1 register ******************/
-#define EXTI_PRIVENR1_RPIF0_Pos (0U)
-#define EXTI_PRIVENR1_RPIF0_Msk (0x1UL << EXTI_PRIVENR1_RPIF0_Pos) /*!< 0x00000001 */
-#define EXTI_PRIVENR1_RPIF0 EXTI_PRIVENR1_RPIF0_Msk /*!< Privilege enable on line 0 */
-#define EXTI_PRIVENR1_RPIF1_Pos (1U)
-#define EXTI_PRIVENR1_RPIF1_Msk (0x1UL << EXTI_PRIVENR1_RPIF1_Pos) /*!< 0x00000002 */
-#define EXTI_PRIVENR1_RPIF1 EXTI_PRIVENR1_RPIF1_Msk /*!< Privilege enable on line 1 */
-#define EXTI_PRIVENR1_RPIF2_Pos (2U)
-#define EXTI_PRIVENR1_RPIF2_Msk (0x1UL << EXTI_PRIVENR1_RPIF2_Pos) /*!< 0x00000004 */
-#define EXTI_PRIVENR1_RPIF2 EXTI_PRIVENR1_RPIF2_Msk /*!< Privilege enable on line 2 */
-#define EXTI_PRIVENR1_RPIF3_Pos (3U)
-#define EXTI_PRIVENR1_RPIF3_Msk (0x1UL << EXTI_PRIVENR1_RPIF3_Pos) /*!< 0x00000008 */
-#define EXTI_PRIVENR1_RPIF3 EXTI_PRIVENR1_RPIF3_Msk /*!< Privilege enable on line 3 */
-#define EXTI_PRIVENR1_RPIF4_Pos (4U)
-#define EXTI_PRIVENR1_RPIF4_Msk (0x1UL << EXTI_PRIVENR1_RPIF4_Pos) /*!< 0x00000010 */
-#define EXTI_PRIVENR1_RPIF4 EXTI_PRIVENR1_RPIF4_Msk /*!< Privilege enable on line 4 */
-#define EXTI_PRIVENR1_RPIF5_Pos (5U)
-#define EXTI_PRIVENR1_RPIF5_Msk (0x1UL << EXTI_PRIVENR1_RPIF5_Pos) /*!< 0x00000020 */
-#define EXTI_PRIVENR1_RPIF5 EXTI_PRIVENR1_RPIF5_Msk /*!< Privilege enable on line 5 */
-#define EXTI_PRIVENR1_RPIF6_Pos (6U)
-#define EXTI_PRIVENR1_RPIF6_Msk (0x1UL << EXTI_PRIVENR1_RPIF6_Pos) /*!< 0x00000040 */
-#define EXTI_PRIVENR1_RPIF6 EXTI_PRIVENR1_RPIF6_Msk /*!< Privilege enable on line 6 */
-#define EXTI_PRIVENR1_RPIF7_Pos (7U)
-#define EXTI_PRIVENR1_RPIF7_Msk (0x1UL << EXTI_PRIVENR1_RPIF7_Pos) /*!< 0x00000080 */
-#define EXTI_PRIVENR1_RPIF7 EXTI_PRIVENR1_RPIF7_Msk /*!< Privilege enable on line 7 */
-#define EXTI_PRIVENR1_RPIF8_Pos (8U)
-#define EXTI_PRIVENR1_RPIF8_Msk (0x1UL << EXTI_PRIVENR1_RPIF8_Pos) /*!< 0x00000100 */
-#define EXTI_PRIVENR1_RPIF8 EXTI_PRIVENR1_RPIF8_Msk /*!< Privilege enable on line 8 */
-#define EXTI_PRIVENR1_RPIF9_Pos (9U)
-#define EXTI_PRIVENR1_RPIF9_Msk (0x1UL << EXTI_PRIVENR1_RPIF9_Pos) /*!< 0x00000200 */
-#define EXTI_PRIVENR1_RPIF9 EXTI_PRIVENR1_RPIF9_Msk /*!< Privilege enable on line 9 */
-#define EXTI_PRIVENR1_RPIF10_Pos (10U)
-#define EXTI_PRIVENR1_RPIF10_Msk (0x1UL << EXTI_PRIVENR1_RPIF10_Pos) /*!< 0x00000400 */
-#define EXTI_PRIVENR1_RPIF10 EXTI_PRIVENR1_RPIF10_Msk /*!< Privilege enable on line 10 */
-#define EXTI_PRIVENR1_RPIF11_Pos (11U)
-#define EXTI_PRIVENR1_RPIF11_Msk (0x1UL << EXTI_PRIVENR1_RPIF11_Pos) /*!< 0x00000800 */
-#define EXTI_PRIVENR1_RPIF11 EXTI_PRIVENR1_RPIF11_Msk /*!< Privilege enable on line 11 */
-#define EXTI_PRIVENR1_RPIF12_Pos (12U)
-#define EXTI_PRIVENR1_RPIF12_Msk (0x1UL << EXTI_PRIVENR1_RPIF12_Pos) /*!< 0x00001000 */
-#define EXTI_PRIVENR1_RPIF12 EXTI_PRIVENR1_RPIF12_Msk /*!< Privilege enable on line 12 */
-#define EXTI_PRIVENR1_RPIF13_Pos (13U)
-#define EXTI_PRIVENR1_RPIF13_Msk (0x1UL << EXTI_PRIVENR1_RPIF13_Pos) /*!< 0x00002000 */
-#define EXTI_PRIVENR1_RPIF13 EXTI_PRIVENR1_RPIF13_Msk /*!< Privilege enable on line 13 */
-#define EXTI_PRIVENR1_RPIF14_Pos (14U)
-#define EXTI_PRIVENR1_RPIF14_Msk (0x1UL << EXTI_PRIVENR1_RPIF14_Pos) /*!< 0x00004000 */
-#define EXTI_PRIVENR1_RPIF14 EXTI_PRIVENR1_RPIF14_Msk /*!< Privilege enable on line 14 */
-#define EXTI_PRIVENR1_RPIF15_Pos (15U)
-#define EXTI_PRIVENR1_RPIF15_Msk (0x1UL << EXTI_PRIVENR1_RPIF15_Pos) /*!< 0x00008000 */
-#define EXTI_PRIVENR1_RPIF15 EXTI_PRIVENR1_RPIF15_Msk /*!< Privilege enable on line 15 */
-#define EXTI_PRIVENR1_RPIF16_Pos (16U)
-#define EXTI_PRIVENR1_RPIF16_Msk (0x1UL << EXTI_PRIVENR1_RPIF16_Pos) /*!< 0x00010000 */
-#define EXTI_PRIVENR1_RPIF16 EXTI_PRIVENR1_RPIF16_Msk /*!< Privilege enable on line 16 */
-#define EXTI_PRIVENR1_RPIF17_Pos (17U)
-#define EXTI_PRIVENR1_RPIF17_Msk (0x1UL << EXTI_PRIVENR1_RPIF17_Pos) /*!< 0x00020000 */
-#define EXTI_PRIVENR1_RPIF17 EXTI_PRIVENR1_RPIF17_Msk /*!< Privilege enable on line 17 */
-#define EXTI_PRIVENR1_RPIF18_Pos (18U)
-#define EXTI_PRIVENR1_RPIF18_Msk (0x1UL << EXTI_PRIVENR1_RPIF18_Pos) /*!< 0x00040000 */
-#define EXTI_PRIVENR1_RPIF18 EXTI_PRIVENR1_RPIF18_Msk /*!< Privilege enable on line 18 */
-#define EXTI_PRIVENR1_RPIF19_Pos (19U)
-#define EXTI_PRIVENR1_RPIF19_Msk (0x1UL << EXTI_PRIVENR1_RPIF19_Pos) /*!< 0x00080000 */
-#define EXTI_PRIVENR1_RPIF19 EXTI_PRIVENR1_RPIF19_Msk /*!< Privilege enable on line 19 */
-#define EXTI_PRIVENR1_RPIF20_Pos (20U)
-#define EXTI_PRIVENR1_RPIF20_Msk (0x1UL << EXTI_PRIVENR1_RPIF20_Pos) /*!< 0x00100000 */
-#define EXTI_PRIVENR1_RPIF20 EXTI_PRIVENR1_RPIF20_Msk /*!< Privilege enable on line 20 */
-#define EXTI_PRIVENR1_RPIF21_Pos (21U)
-#define EXTI_PRIVENR1_RPIF21_Msk (0x1UL << EXTI_PRIVENR1_RPIF21_Pos) /*!< 0x00200000 */
-#define EXTI_PRIVENR1_RPIF21 EXTI_PRIVENR1_RPIF21_Msk /*!< Privilege enable on line 21 */
-#define EXTI_PRIVENR1_RPIF22_Pos (22U)
-#define EXTI_PRIVENR1_RPIF22_Msk (0x1UL << EXTI_PRIVENR1_RPIF22_Pos) /*!< 0x00400000 */
-#define EXTI_PRIVENR1_RPIF22 EXTI_PRIVENR1_RPIF22_Msk /*!< Privilege enable on line 22 */
-#define EXTI_PRIVENR1_RPIF23_Pos (23U)
-#define EXTI_PRIVENR1_RPIF23_Msk (0x1UL << EXTI_PRIVENR1_RPIF23_Pos) /*!< 0x00800000 */
-#define EXTI_PRIVENR1_RPIF23 EXTI_PRIVENR1_RPIF23_Msk /*!< Privilege enable on line 23 */
-#define EXTI_PRIVENR1_RPIF24_Pos (24U)
-#define EXTI_PRIVENR1_RPIF24_Msk (0x1UL << EXTI_PRIVENR1_RPIF24_Pos) /*!< 0x01000000 */
-#define EXTI_PRIVENR1_RPIF24 EXTI_PRIVENR1_RPIF24_Msk /*!< Privilege enable on line 24 */
+/******************* Bit definition for EXTI_PRIVCFGR1 register ******************/
+#define EXTI_PRIVCFGR1_PRIV0_Pos (0U)
+#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */
+#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on line 0 */
+#define EXTI_PRIVCFGR1_PRIV1_Pos (1U)
+#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */
+#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on line 1 */
+#define EXTI_PRIVCFGR1_PRIV2_Pos (2U)
+#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */
+#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on line 2 */
+#define EXTI_PRIVCFGR1_PRIV3_Pos (3U)
+#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */
+#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on line 3 */
+#define EXTI_PRIVCFGR1_PRIV4_Pos (4U)
+#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */
+#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on line 4 */
+#define EXTI_PRIVCFGR1_PRIV5_Pos (5U)
+#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */
+#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on line 5 */
+#define EXTI_PRIVCFGR1_PRIV6_Pos (6U)
+#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */
+#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on line 6 */
+#define EXTI_PRIVCFGR1_PRIV7_Pos (7U)
+#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */
+#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on line 7 */
+#define EXTI_PRIVCFGR1_PRIV8_Pos (8U)
+#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */
+#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on line 8 */
+#define EXTI_PRIVCFGR1_PRIV9_Pos (9U)
+#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */
+#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on line 9 */
+#define EXTI_PRIVCFGR1_PRIV10_Pos (10U)
+#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */
+#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on line 10 */
+#define EXTI_PRIVCFGR1_PRIV11_Pos (11U)
+#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */
+#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on line 11 */
+#define EXTI_PRIVCFGR1_PRIV12_Pos (12U)
+#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */
+#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on line 12 */
+#define EXTI_PRIVCFGR1_PRIV13_Pos (13U)
+#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */
+#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on line 13 */
+#define EXTI_PRIVCFGR1_PRIV14_Pos (14U)
+#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */
+#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on line 14 */
+#define EXTI_PRIVCFGR1_PRIV15_Pos (15U)
+#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */
+#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on line 15 */
+#define EXTI_PRIVCFGR1_PRIV16_Pos (16U)
+#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */
+#define EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk /*!< Privilege enable on line 16 */
+#define EXTI_PRIVCFGR1_PRIV17_Pos (17U)
+#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */
+#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on line 17 */
+#define EXTI_PRIVCFGR1_PRIV18_Pos (18U)
+#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */
+#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on line 18 */
+#define EXTI_PRIVCFGR1_PRIV19_Pos (19U)
+#define EXTI_PRIVCFGR1_PRIV19_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */
+#define EXTI_PRIVCFGR1_PRIV19 EXTI_PRIVCFGR1_PRIV19_Msk /*!< Privilege enable on line 19 */
+#define EXTI_PRIVCFGR1_PRIV20_Pos (20U)
+#define EXTI_PRIVCFGR1_PRIV20_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */
+#define EXTI_PRIVCFGR1_PRIV20 EXTI_PRIVCFGR1_PRIV20_Msk /*!< Privilege enable on line 20 */
+#define EXTI_PRIVCFGR1_PRIV21_Pos (21U)
+#define EXTI_PRIVCFGR1_PRIV21_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */
+#define EXTI_PRIVCFGR1_PRIV21 EXTI_PRIVCFGR1_PRIV21_Msk /*!< Privilege enable on line 21 */
+#define EXTI_PRIVCFGR1_PRIV22_Pos (22U)
+#define EXTI_PRIVCFGR1_PRIV22_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */
+#define EXTI_PRIVCFGR1_PRIV22 EXTI_PRIVCFGR1_PRIV22_Msk /*!< Privilege enable on line 22 */
+#define EXTI_PRIVCFGR1_PRIV23_Pos (23U)
+#define EXTI_PRIVCFGR1_PRIV23_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */
+#define EXTI_PRIVCFGR1_PRIV23 EXTI_PRIVCFGR1_PRIV23_Msk /*!< Privilege enable on line 23 */
/***************** Bit definition for EXTI_EXTICR1 register **************/
#define EXTI_EXTICR1_EXTI0_Pos (0U)
@@ -7809,6 +7834,11 @@
#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */
#define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */
+/***************** Bit definition for EXTI_LOCKR register **************/
+#define EXTI_LOCKR_LOCK_Pos (0U)
+#define EXTI_LOCKR_LOCK_Msk (0x1UL << EXTI_LOCKR_LOCK_Pos) /*!< 0x00000001 */
+#define EXTI_LOCKR_LOCK EXTI_LOCKR_LOCK_Msk /*!< Global security and privilege configuration registers lock */
+
/******************* Bit definition for EXTI_IMR1 register ******************/
#define EXTI_IMR1_IM0_Pos (0U)
#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
@@ -7882,9 +7912,6 @@
#define EXTI_IMR1_IM23_Pos (23U)
#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR1_IM24_Pos (24U)
-#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
-#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
/******************* Bit definition for EXTI_EMR1 register ******************/
#define EXTI_EMR1_EM0_Pos (0U)
@@ -7959,9 +7986,6 @@
#define EXTI_EMR1_EM23_Pos (23U)
#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
-#define EXTI_EMR1_EM24_Pos (24U)
-#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
-#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
/******************************************************************************/
/* */
@@ -8546,13 +8570,14 @@
/* FLASH */
/* */
/******************************************************************************/
-#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */
+#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
-#define FLASH_BLOCKBASED_NB_REG (4U) /* 4 Block-based registers for each Flash bank */
+#define FLASH_SIZE_DEFAULT 0x200000U /*!< Flash memory default size */
+#define FLASH_BLOCKBASED_NB_REG (4U) /*!< 4 Block-based registers for each Flash bank */
-#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x200000U : \
- ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x200000U : \
- (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x0FFFU)) << 10U)))
+#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? FLASH_SIZE_DEFAULT : \
+ ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? FLASH_SIZE_DEFAULT : \
+ (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U)))
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1U)
@@ -8807,9 +8832,9 @@
#define FLASH_OPTR_nRST_SHDW_Pos (14U)
#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */
-#define FLASH_OPTR_SRAM134_RST_Pos (15U)
-#define FLASH_OPTR_SRAM134_RST_Msk (0x1UL << FLASH_OPTR_SRAM134_RST_Pos) /*!< 0x00008000 */
-#define FLASH_OPTR_SRAM134_RST FLASH_OPTR_SRAM134_RST_Msk /*!< SRAM1, SRAM3 and SRAM4 erase upon system reset */
+#define FLASH_OPTR_SRAM_RST_Pos (15U)
+#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */
+#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */
#define FLASH_OPTR_IWDG_SW_Pos (16U)
#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */
@@ -10251,6 +10276,7 @@
#define GPIO_SECCFGR_SEC15_Pos (15U)
#define GPIO_SECCFGR_SEC15_Msk (0x1UL << GPIO_SECCFGR_SEC15_Pos) /*!< 0x00008000 */
#define GPIO_SECCFGR_SEC15 GPIO_SECCFGR_SEC15_Msk
+
/******************************************************************************/
/* */
/* Low Power General Purpose IOs (LPGPIO) */
@@ -10765,55 +10791,58 @@
/* Analog Comparators (COMP) */
/* */
/******************************************************************************/
-/*!< ****************** Bit definition for COMPx_CSR register ********************/
+
+#define COMP_WINDOW_MODE_SUPPORT /*!< COMP feature available only on specific devices */
+
+/********************** Bit definition for COMP_CSR register ****************/
#define COMP_CSR_EN_Pos (0U)
#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */
-#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< COMPx enable bit */
+#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
#define COMP_CSR_INMSEL_Pos (4U)
-#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00070000 */
-#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< COMPx input minus selection bit */
-#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00010000 */
-#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00020000 */
-#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00040000 */
-#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00080000 */
+#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x000000F0 */
+#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
+#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
+#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */
#define COMP_CSR_INPSEL_Pos (8U)
-#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00100000 */
-#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< COMPx input plus selection bit */
-#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos)
-#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos)
+#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000300 */
+#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
+#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
+#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000200 */
#define COMP_CSR_WINMODE_Pos (11U)
-#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000010 */
-#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< COMPx Windows mode selection bit */
+#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000800 */
+#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
#define COMP_CSR_WINOUT_Pos (14U)
-#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00000008 */
-#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< COMPx polarity selection bit */
+#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00004000 */
+#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
#define COMP_CSR_POLARITY_Pos (15U)
-#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00000008 */
-#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< COMPx polarity selection bit */
+#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
#define COMP_CSR_HYST_Pos (16U)
-#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00000300 */
-#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< COMPx hysteresis selection bits */
-#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00000100 */
-#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00000200 */
+#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */
+#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator input hysteresis */
+#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
+#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
#define COMP_CSR_PWRMODE_Pos (18U)
-#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00003000 */
-#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */
-#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00001000 */
-#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00002000 */
+#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x000C0000 */
+#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */
+#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00040000 */
+#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00080000 */
#define COMP_CSR_BLANKSEL_Pos (20U)
-#define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x0F000000 */
-#define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< COMPx blanking source selection bits */
-#define COMP_CSR_BLANKSEL_0 (0x1UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */
-#define COMP_CSR_BLANKSEL_1 (0x2UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x02000000 */
-#define COMP_CSR_BLANKSEL_2 (0x4UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x04000000 */
-#define COMP_CSR_BLANKSEL_3 (0x8UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x08000000 */
+#define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01F00000 */
+#define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< Comparator blanking source */
+#define COMP_CSR_BLANKSEL_0 (0x01UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00100000 */
+#define COMP_CSR_BLANKSEL_1 (0x02UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00200000 */
+#define COMP_CSR_BLANKSEL_2 (0x04UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00400000 */
+#define COMP_CSR_BLANKSEL_3 (0x08UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00800000 */
#define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */
#define COMP_CSR_VALUE_Pos (30U)
-#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x00000001 */
-#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< COMPx enable bit */
+#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
#define COMP_CSR_LOCK_Pos (31U)
#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
-#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< COMPx Lock Bit */
+#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
/******************************************************************************/
/* */
@@ -11961,10 +11990,10 @@
#define TIM_DCR_DBSS_Pos (16U)
#define TIM_DCR_DBSS_Msk (0xFUL << TIM_DCR_DBSS_Pos) /*!< 0x00000F00 */
#define TIM_DCR_DBSS TIM_DCR_DBSS_Msk /*!<DBSS[19:16] bits (DMA Burst Source Selection) */
-#define TIM_DCR_DBSS_0 (0x01UL << TIM_DCR_DBSS_Pos) /*!< 0x00000100 */
-#define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200 */
-#define TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00000400 */
-#define TIM_DCR_DBSS_3 (0x08UL << TIM_DCR_DBSS_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBSS_0 (0x01UL << TIM_DCR_DBSS_Pos) /*!< 0x00010000 */
+#define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000 */
+#define TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00040000 */
+#define TIM_DCR_DBSS_3 (0x08UL << TIM_DCR_DBSS_Pos) /*!< 0x00080000 */
/******************* Bit definition for TIM1_AF1 register *******************/
#define TIM1_AF1_BKINE_Pos (0U)
@@ -12087,7 +12116,7 @@
#define TIM_ECR_IDIR_0 (0x01UL << TIM_ECR_IDIR_Pos) /*!< 0x00000001 */
#define TIM_ECR_IDIR_1 (0x02UL << TIM_ECR_IDIR_Pos) /*!< 0x00000002 */
#define TIM_ECR_IBLK_Pos (3U)
-#define TIM_ECR_IBLK_Msk (0x5UL << TIM_ECR_IBLK_Pos) /*!< 0x00000018 */
+#define TIM_ECR_IBLK_Msk (0x3UL << TIM_ECR_IBLK_Pos) /*!< 0x00000018 */
#define TIM_ECR_IBLK TIM_ECR_IBLK_Msk /*!<IBLK[1:0] bits (Index blanking)*/
#define TIM_ECR_IBLK_0 (0x01UL << TIM_ECR_IBLK_Pos) /*!< 0x00000008 */
#define TIM_ECR_IBLK_1 (0x02UL << TIM_ECR_IBLK_Pos) /*!< 0x00000010 */
@@ -12929,418 +12958,885 @@
/******************************************************************************/
/* */
+/* XSPI (OCTOSPI) */
+/* */
+/******************************************************************************/
+/************ Bit definition for XSPI_CR register **************************/
+#define XSPI_CR_EN_Pos (0U)
+#define XSPI_CR_EN_Msk (0x1UL << XSPI_CR_EN_Pos) /*!< 0x00000001 */
+#define XSPI_CR_EN XSPI_CR_EN_Msk /*!< Enable */
+#define XSPI_CR_ABORT_Pos (1U)
+#define XSPI_CR_ABORT_Msk (0x1UL << XSPI_CR_ABORT_Pos) /*!< 0x00000002 */
+#define XSPI_CR_ABORT XSPI_CR_ABORT_Msk /*!< Abort request */
+#define XSPI_CR_DMAEN_Pos (2U)
+#define XSPI_CR_DMAEN_Msk (0x1UL << XSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
+#define XSPI_CR_DMAEN XSPI_CR_DMAEN_Msk /*!< DMA Enable */
+#define XSPI_CR_TCEN_Pos (3U)
+#define XSPI_CR_TCEN_Msk (0x1UL << XSPI_CR_TCEN_Pos) /*!< 0x00000008 */
+#define XSPI_CR_TCEN XSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
+#define XSPI_CR_DMM_Pos (6U)
+#define XSPI_CR_DMM_Msk (0x1UL << XSPI_CR_DMM_Pos) /*!< 0x00000040 */
+#define XSPI_CR_DMM XSPI_CR_DMM_Msk /*!< Dual Memory Mode */
+#define XSPI_OCTOSPI_CR_MSEL_Pos (7U)
+#define XSPI_OCTOSPI_CR_MSEL_Msk (0x1UL << XSPI_OCTOSPI_CR_MSEL_Pos) /*!< 0x00000080 */
+#define XSPI_OCTOSPI_CR_MSEL XSPI_OCTOSPI_CR_MSEL_Msk /*!< Memory Select */
+#define XSPI_CR_FTHRES_Pos (8U)
+#define XSPI_CR_FTHRES_Msk (0x3FUL << XSPI_CR_FTHRES_Pos) /*!< 0x00003F00 */
+#define XSPI_CR_FTHRES XSPI_CR_FTHRES_Msk /*!< FIFO Threshold Level */
+#define XSPI_CR_TEIE_Pos (16U)
+#define XSPI_CR_TEIE_Msk (0x1UL << XSPI_CR_TEIE_Pos) /*!< 0x00010000 */
+#define XSPI_CR_TEIE XSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
+#define XSPI_CR_TCIE_Pos (17U)
+#define XSPI_CR_TCIE_Msk (0x1UL << XSPI_CR_TCIE_Pos) /*!< 0x00020000 */
+#define XSPI_CR_TCIE XSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
+#define XSPI_CR_FTIE_Pos (18U)
+#define XSPI_CR_FTIE_Msk (0x1UL << XSPI_CR_FTIE_Pos) /*!< 0x00040000 */
+#define XSPI_CR_FTIE XSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
+#define XSPI_CR_SMIE_Pos (19U)
+#define XSPI_CR_SMIE_Msk (0x1UL << XSPI_CR_SMIE_Pos) /*!< 0x00080000 */
+#define XSPI_CR_SMIE XSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
+#define XSPI_CR_TOIE_Pos (20U)
+#define XSPI_CR_TOIE_Msk (0x1UL << XSPI_CR_TOIE_Pos) /*!< 0x00100000 */
+#define XSPI_CR_TOIE XSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
+#define XSPI_CR_APMS_Pos (22U)
+#define XSPI_CR_APMS_Msk (0x1UL << XSPI_CR_APMS_Pos) /*!< 0x00400000 */
+#define XSPI_CR_APMS XSPI_CR_APMS_Msk /*!< Automatic Poll Mode Stop */
+#define XSPI_CR_PMM_Pos (23U)
+#define XSPI_CR_PMM_Msk (0x1UL << XSPI_CR_PMM_Pos) /*!< 0x00800000 */
+#define XSPI_CR_PMM XSPI_CR_PMM_Msk /*!< Polling Match Mode */
+#define XSPI_CR_FMODE_Pos (28U)
+#define XSPI_CR_FMODE_Msk (0x3UL << XSPI_CR_FMODE_Pos) /*!< 0x30000000 */
+#define XSPI_CR_FMODE XSPI_CR_FMODE_Msk /*!< Functional Mode */
+#define XSPI_CR_FMODE_0 (0x1UL << XSPI_CR_FMODE_Pos) /*!< 0x10000000 */
+#define XSPI_CR_FMODE_1 (0x2UL << XSPI_CR_FMODE_Pos) /*!< 0x20000000 */
+
+/************* Bit definition for XSPI_DCR1 register ***********************/
+#define XSPI_DCR1_CKMODE_Pos (0U)
+#define XSPI_DCR1_CKMODE_Msk (0x1UL << XSPI_DCR1_CKMODE_Pos) /*!< 0x00000001 */
+#define XSPI_DCR1_CKMODE XSPI_DCR1_CKMODE_Msk /*!< Mode 0 / Mode 3 */
+#define XSPI_DCR1_FRCK_Pos (1U)
+#define XSPI_DCR1_FRCK_Msk (0x1UL << XSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */
+#define XSPI_DCR1_FRCK XSPI_DCR1_FRCK_Msk /*!< Free Running Clock */
+#define XSPI_OCTOSPI_DCR1_DLYBYP_Pos (3U)
+#define XSPI_OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << XSPI_OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
+#define XSPI_OCTOSPI_DCR1_DLYBYP XSPI_OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass only for OCTOSPI */
+#define XSPI_DCR1_CSHT_Pos (8U)
+#define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x00003F00 */
+#define XSPI_DCR1_CSHT XSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
+#define XSPI_DCR1_DEVSIZE_Pos (16U)
+#define XSPI_DCR1_DEVSIZE_Msk (0x1FUL << XSPI_DCR1_DEVSIZE_Pos) /*!< 0x001F0000 */
+#define XSPI_DCR1_DEVSIZE XSPI_DCR1_DEVSIZE_Msk /*!< Device Size */
+#define XSPI_DCR1_MTYP_Pos (24U)
+#define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07000000 */
+#define XSPI_DCR1_MTYP XSPI_DCR1_MTYP_Msk /*!< Memory Type */
+#define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */
+#define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
+#define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
+
+/**************** Bit definition for XSPI_DCR2 register *********************/
+#define XSPI_DCR2_PRESCALER_Pos (0U)
+#define XSPI_DCR2_PRESCALER_Msk (0xFFUL << XSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
+#define XSPI_DCR2_PRESCALER XSPI_DCR2_PRESCALER_Msk /*!< Clock prescaler */
+#define XSPI_DCR2_WRAPSIZE_Pos (16U)
+#define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */
+#define XSPI_DCR2_WRAPSIZE XSPI_DCR2_WRAPSIZE_Msk /*!< Wrap Size */
+#define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */
+#define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */
+#define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */
+
+/**************** Bit definition for XSPI_DCR3 register ********************/
+#define XSPI_OCTOSPI_DCR3_MAXTRAN_Pos (0U)
+#define XSPI_OCTOSPI_DCR3_MAXTRAN_Msk (0xFFUL << XSPI_OCTOSPI_DCR3_MAXTRAN_Pos) /*!< 0x000000FF */
+#define XSPI_OCTOSPI_DCR3_MAXTRAN XSPI_OCTOSPI_DCR3_MAXTRAN_Msk /*!< Maximum transfer only for OCTOSPI */
+#define XSPI_DCR3_CSBOUND_Pos (16U)
+#define XSPI_DCR3_CSBOUND_Msk (0x1FUL << XSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */
+#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< Maximum transfer */
+/**************** Bit definition for XSPI_DCR4 register ********************/
+#define XSPI_DCR4_REFRESH_Pos (0U)
+#define XSPI_DCR4_REFRESH_Msk (0xFFFFFFFFUL << XSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_DCR4_REFRESH XSPI_DCR4_REFRESH_Msk /*!< Refresh rate */
+
+/***************** Bit definition for XSPI_SR register ********************/
+#define XSPI_SR_TEF_Pos (0U)
+#define XSPI_SR_TEF_Msk (0x1UL << XSPI_SR_TEF_Pos) /*!< 0x00000001 */
+#define XSPI_SR_TEF XSPI_SR_TEF_Msk /*!< Transfer Error Flag */
+#define XSPI_SR_TCF_Pos (1U)
+#define XSPI_SR_TCF_Msk (0x1UL << XSPI_SR_TCF_Pos) /*!< 0x00000002 */
+#define XSPI_SR_TCF XSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
+#define XSPI_SR_FTF_Pos (2U)
+#define XSPI_SR_FTF_Msk (0x1UL << XSPI_SR_FTF_Pos) /*!< 0x00000004 */
+#define XSPI_SR_FTF XSPI_SR_FTF_Msk /*!< FIFO Threshold Flag */
+#define XSPI_SR_SMF_Pos (3U)
+#define XSPI_SR_SMF_Msk (0x1UL << XSPI_SR_SMF_Pos) /*!< 0x00000008 */
+#define XSPI_SR_SMF XSPI_SR_SMF_Msk /*!< Status Match Flag */
+#define XSPI_SR_TOF_Pos (4U)
+#define XSPI_SR_TOF_Msk (0x1UL << XSPI_SR_TOF_Pos) /*!< 0x00000010 */
+#define XSPI_SR_TOF XSPI_SR_TOF_Msk /*!< Timeout Flag */
+#define XSPI_SR_BUSY_Pos (5U)
+#define XSPI_SR_BUSY_Msk (0x1UL << XSPI_SR_BUSY_Pos) /*!< 0x00000020 */
+#define XSPI_SR_BUSY XSPI_SR_BUSY_Msk /*!< Busy */
+#define XSPI_SR_FLEVEL_Pos (8U)
+#define XSPI_SR_FLEVEL_Msk (0x7FUL << XSPI_SR_FLEVEL_Pos) /*!< 0x00007F00 */
+#define XSPI_SR_FLEVEL XSPI_SR_FLEVEL_Msk /*!< FIFO Level */
+
+/**************** Bit definition for XSPI_FCR register *********************/
+#define XSPI_FCR_CTEF_Pos (0U)
+#define XSPI_FCR_CTEF_Msk (0x1UL << XSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
+#define XSPI_FCR_CTEF XSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
+#define XSPI_FCR_CTCF_Pos (1U)
+#define XSPI_FCR_CTCF_Msk (0x1UL << XSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
+#define XSPI_FCR_CTCF XSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
+#define XSPI_FCR_CSMF_Pos (3U)
+#define XSPI_FCR_CSMF_Msk (0x1UL << XSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
+#define XSPI_FCR_CSMF XSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
+#define XSPI_FCR_CTOF_Pos (4U)
+#define XSPI_FCR_CTOF_Msk (0x1UL << XSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
+#define XSPI_FCR_CTOF XSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
+
+/**************** Bit definition for XSPI_DLR register *********************/
+#define XSPI_DLR_DL_Pos (0U)
+#define XSPI_DLR_DL_Msk (0xFFFFFFFFUL << XSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_DLR_DL XSPI_DLR_DL_Msk /*!< Data Length */
+
+/***************** Bit definition for XSPI_AR register *********************/
+#define XSPI_AR_ADDRESS_Pos (0U)
+#define XSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << XSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_AR_ADDRESS XSPI_AR_ADDRESS_Msk /*!< Address */
+
+/***************** Bit definition for XSPI_DR register *********************/
+#define XSPI_DR_DATA_Pos (0U)
+#define XSPI_DR_DATA_Msk (0xFFFFFFFFUL << XSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_DR_DATA XSPI_DR_DATA_Msk /*!< Data */
+
+/*************** Bit definition for XSPI_PSMKR register ********************/
+#define XSPI_PSMKR_MASK_Pos (0U)
+#define XSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << XSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_PSMKR_MASK XSPI_PSMKR_MASK_Msk /*!< Status mask */
+
+/*************** Bit definition for XSPI_PSMAR register ********************/
+#define XSPI_PSMAR_MATCH_Pos (0U)
+#define XSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << XSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_PSMAR_MATCH XSPI_PSMAR_MATCH_Msk /*!< Status match */
+
+/**************** Bit definition for XSPI_PIR register *********************/
+#define XSPI_PIR_INTERVAL_Pos (0U)
+#define XSPI_PIR_INTERVAL_Msk (0xFFFFUL << XSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
+#define XSPI_PIR_INTERVAL XSPI_PIR_INTERVAL_Msk /*!< Polling Interval */
+
+/**************** Bit definition for XSPI_CCR register *********************/
+#define XSPI_CCR_IMODE_Pos (0U)
+#define XSPI_CCR_IMODE_Msk (0x7UL << XSPI_CCR_IMODE_Pos) /*!< 0x00000007 */
+#define XSPI_CCR_IMODE XSPI_CCR_IMODE_Msk /*!< Instruction Mode */
+#define XSPI_CCR_IMODE_0 (0x1UL << XSPI_CCR_IMODE_Pos) /*!< 0x00000001 */
+#define XSPI_CCR_IMODE_1 (0x2UL << XSPI_CCR_IMODE_Pos) /*!< 0x00000002 */
+#define XSPI_CCR_IMODE_2 (0x4UL << XSPI_CCR_IMODE_Pos) /*!< 0x00000004 */
+#define XSPI_CCR_IDTR_Pos (3U)
+#define XSPI_CCR_IDTR_Msk (0x1UL << XSPI_CCR_IDTR_Pos) /*!< 0x00000008 */
+#define XSPI_CCR_IDTR XSPI_CCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
+#define XSPI_CCR_ISIZE_Pos (4U)
+#define XSPI_CCR_ISIZE_Msk (0x3UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00000030 */
+#define XSPI_CCR_ISIZE XSPI_CCR_ISIZE_Msk /*!< Instruction Size */
+#define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00000010 */
+#define XSPI_CCR_ISIZE_1 (0x2UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00000020 */
+#define XSPI_CCR_ADMODE_Pos (8U)
+#define XSPI_CCR_ADMODE_Msk (0x7UL << XSPI_CCR_ADMODE_Pos) /*!< 0x00000700 */
+#define XSPI_CCR_ADMODE XSPI_CCR_ADMODE_Msk /*!< Address Mode */
+#define XSPI_CCR_ADMODE_0 (0x1UL << XSPI_CCR_ADMODE_Pos) /*!< 0x00000100 */
+#define XSPI_CCR_ADMODE_1 (0x2UL << XSPI_CCR_ADMODE_Pos) /*!< 0x00000200 */
+#define XSPI_CCR_ADMODE_2 (0x4UL << XSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
+#define XSPI_CCR_ADDTR_Pos (11U)
+#define XSPI_CCR_ADDTR_Msk (0x1UL << XSPI_CCR_ADDTR_Pos) /*!< 0x00000800 */
+#define XSPI_CCR_ADDTR XSPI_CCR_ADDTR_Msk /*!< Address Double Transfer Rate */
+#define XSPI_CCR_ADSIZE_Pos (12U)
+#define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
+#define XSPI_CCR_ADSIZE XSPI_CCR_ADSIZE_Msk /*!< Address Size */
+#define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
+#define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
+#define XSPI_CCR_ABMODE_Pos (16U)
+#define XSPI_CCR_ABMODE_Msk (0x7UL << XSPI_CCR_ABMODE_Pos) /*!< 0x00070000 */
+#define XSPI_CCR_ABMODE XSPI_CCR_ABMODE_Msk /*!< Alternate Bytes Mode */
+#define XSPI_CCR_ABMODE_0 (0x1UL << XSPI_CCR_ABMODE_Pos) /*!< 0x00010000 */
+#define XSPI_CCR_ABMODE_1 (0x2UL << XSPI_CCR_ABMODE_Pos) /*!< 0x00020000 */
+#define XSPI_CCR_ABMODE_2 (0x4UL << XSPI_CCR_ABMODE_Pos) /*!< 0x00040000 */
+#define XSPI_CCR_ABDTR_Pos (19U)
+#define XSPI_CCR_ABDTR_Msk (0x1UL << XSPI_CCR_ABDTR_Pos) /*!< 0x00080000 */
+#define XSPI_CCR_ABDTR XSPI_CCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
+#define XSPI_CCR_ABSIZE_Pos (20U)
+#define XSPI_CCR_ABSIZE_Msk (0x3UL << XSPI_CCR_ABSIZE_Pos) /*!< 0x00300000 */
+#define XSPI_CCR_ABSIZE XSPI_CCR_ABSIZE_Msk /*!< Alternate Bytes Size */
+#define XSPI_CCR_ABSIZE_0 (0x1UL << XSPI_CCR_ABSIZE_Pos) /*!< 0x00100000 */
+#define XSPI_CCR_ABSIZE_1 (0x2UL << XSPI_CCR_ABSIZE_Pos) /*!< 0x00200000 */
+#define XSPI_CCR_DMODE_Pos (24U)
+#define XSPI_CCR_DMODE_Msk (0x7UL << XSPI_CCR_DMODE_Pos) /*!< 0x07000000 */
+#define XSPI_CCR_DMODE XSPI_CCR_DMODE_Msk /*!< Data Mode */
+#define XSPI_CCR_DMODE_0 (0x1UL << XSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
+#define XSPI_CCR_DMODE_1 (0x2UL << XSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
+#define XSPI_CCR_DMODE_2 (0x4UL << XSPI_CCR_DMODE_Pos) /*!< 0x04000000 */
+#define XSPI_CCR_DDTR_Pos (27U)
+#define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08000000 */
+#define XSPI_CCR_DDTR XSPI_CCR_DDTR_Msk /*!< Data Double Transfer Rate */
+#define XSPI_CCR_DQSE_Pos (29U)
+#define XSPI_CCR_DQSE_Msk (0x1UL << XSPI_CCR_DQSE_Pos) /*!< 0x20000000 */
+#define XSPI_CCR_DQSE XSPI_CCR_DQSE_Msk /*!< DQS Enable */
+#define XSPI_CCR_SIOO_Pos (31U)
+#define XSPI_CCR_SIOO_Msk (0x1UL << XSPI_CCR_SIOO_Pos) /*!< 0x80000000 */
+#define XSPI_CCR_SIOO XSPI_CCR_SIOO_Msk /*!< Send Instruction Only Once Mode */
+
+/**************** Bit definition for XSPI_TCR register *********************/
+#define XSPI_TCR_DCYC_Pos (0U)
+#define XSPI_TCR_DCYC_Msk (0x1FUL << XSPI_TCR_DCYC_Pos) /*!< 0x0000001F */
+#define XSPI_TCR_DCYC XSPI_TCR_DCYC_Msk /*!< Number of Dummy Cycles */
+#define XSPI_TCR_DHQC_Pos (28U)
+#define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10000000 */
+#define XSPI_TCR_DHQC XSPI_TCR_DHQC_Msk /*!< Delay Hold Quarter Cycle */
+#define XSPI_TCR_SSHIFT_Pos (30U)
+#define XSPI_TCR_SSHIFT_Msk (0x1UL << XSPI_TCR_SSHIFT_Pos) /*!< 0x40000000 */
+#define XSPI_TCR_SSHIFT XSPI_TCR_SSHIFT_Msk /*!< Sample Shift */
+
+/***************** Bit definition for XSPI_IR register *********************/
+#define XSPI_IR_INSTRUCTION_Pos (0U)
+#define XSPI_IR_INSTRUCTION_Msk (0xFFFFFFFFUL << XSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_IR_INSTRUCTION XSPI_IR_INSTRUCTION_Msk /*!< Instruction */
+
+/**************** Bit definition for XSPI_ABR register *********************/
+#define XSPI_ABR_ALTERNATE_Pos (0U)
+#define XSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << XSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_ABR_ALTERNATE XSPI_ABR_ALTERNATE_Msk /*!< Alternate Bytes */
+
+/**************** Bit definition for XSPI_LPTR register ********************/
+#define XSPI_LPTR_TIMEOUT_Pos (0U)
+#define XSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << XSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
+#define XSPI_LPTR_TIMEOUT XSPI_LPTR_TIMEOUT_Msk /*!< Timeout period */
+
+/**************** Bit definition for XSPI_WPCCR register *******************/
+#define XSPI_WPCCR_IMODE_Pos (0U)
+#define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000007 */
+#define XSPI_WPCCR_IMODE XSPI_WPCCR_IMODE_Msk /*!< Instruction Mode */
+#define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000001 */
+#define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000002 */
+#define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000004 */
+#define XSPI_WPCCR_IDTR_Pos (3U)
+#define XSPI_WPCCR_IDTR_Msk (0x1UL << XSPI_WPCCR_IDTR_Pos) /*!< 0x00000008 */
+#define XSPI_WPCCR_IDTR XSPI_WPCCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
+#define XSPI_WPCCR_ISIZE_Pos (4U)
+#define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
+#define XSPI_WPCCR_ISIZE XSPI_WPCCR_ISIZE_Msk /*!< Instruction Size */
+#define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
+#define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
+#define XSPI_WPCCR_ADMODE_Pos (8U)
+#define XSPI_WPCCR_ADMODE_Msk (0x7UL << XSPI_WPCCR_ADMODE_Pos) /*!< 0x00000700 */
+#define XSPI_WPCCR_ADMODE XSPI_WPCCR_ADMODE_Msk /*!< Address Mode */
+#define XSPI_WPCCR_ADMODE_0 (0x1UL << XSPI_WPCCR_ADMODE_Pos) /*!< 0x00000100 */
+#define XSPI_WPCCR_ADMODE_1 (0x2UL << XSPI_WPCCR_ADMODE_Pos) /*!< 0x00000200 */
+#define XSPI_WPCCR_ADMODE_2 (0x4UL << XSPI_WPCCR_ADMODE_Pos) /*!< 0x00000400 */
+#define XSPI_WPCCR_ADDTR_Pos (11U)
+#define XSPI_WPCCR_ADDTR_Msk (0x1UL << XSPI_WPCCR_ADDTR_Pos) /*!< 0x00000800 */
+#define XSPI_WPCCR_ADDTR XSPI_WPCCR_ADDTR_Msk /*!< Address Double Transfer Rate */
+#define XSPI_WPCCR_ADSIZE_Pos (12U)
+#define XSPI_WPCCR_ADSIZE_Msk (0x3UL << XSPI_WPCCR_ADSIZE_Pos) /*!< 0x00003000 */
+#define XSPI_WPCCR_ADSIZE XSPI_WPCCR_ADSIZE_Msk /*!< Address Size */
+#define XSPI_WPCCR_ADSIZE_0 (0x1UL << XSPI_WPCCR_ADSIZE_Pos) /*!< 0x00001000 */
+#define XSPI_WPCCR_ADSIZE_1 (0x2UL << XSPI_WPCCR_ADSIZE_Pos) /*!< 0x00002000 */
+#define XSPI_WPCCR_ABMODE_Pos (16U)
+#define XSPI_WPCCR_ABMODE_Msk (0x7UL << XSPI_WPCCR_ABMODE_Pos) /*!< 0x00070000 */
+#define XSPI_WPCCR_ABMODE XSPI_WPCCR_ABMODE_Msk /*!< Alternate Bytes Mode */
+#define XSPI_WPCCR_ABMODE_0 (0x1UL << XSPI_WPCCR_ABMODE_Pos) /*!< 0x00010000 */
+#define XSPI_WPCCR_ABMODE_1 (0x2UL << XSPI_WPCCR_ABMODE_Pos) /*!< 0x00020000 */
+#define XSPI_WPCCR_ABMODE_2 (0x4UL << XSPI_WPCCR_ABMODE_Pos) /*!< 0x00040000 */
+#define XSPI_WPCCR_ABDTR_Pos (19U)
+#define XSPI_WPCCR_ABDTR_Msk (0x1UL << XSPI_WPCCR_ABDTR_Pos) /*!< 0x00080000 */
+#define XSPI_WPCCR_ABDTR XSPI_WPCCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
+#define XSPI_WPCCR_ABSIZE_Pos (20U)
+#define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00300000 */
+#define XSPI_WPCCR_ABSIZE XSPI_WPCCR_ABSIZE_Msk /*!< Alternate Bytes Size */
+#define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00100000 */
+#define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00200000 */
+#define XSPI_WPCCR_DMODE_Pos (24U)
+#define XSPI_WPCCR_DMODE_Msk (0x7UL << XSPI_WPCCR_DMODE_Pos) /*!< 0x07000000 */
+#define XSPI_WPCCR_DMODE XSPI_WPCCR_DMODE_Msk /*!< Data Mode */
+#define XSPI_WPCCR_DMODE_0 (0x1UL << XSPI_WPCCR_DMODE_Pos) /*!< 0x01000000 */
+#define XSPI_WPCCR_DMODE_1 (0x2UL << XSPI_WPCCR_DMODE_Pos) /*!< 0x02000000 */
+#define XSPI_WPCCR_DMODE_2 (0x4UL << XSPI_WPCCR_DMODE_Pos) /*!< 0x04000000 */
+#define XSPI_WPCCR_DDTR_Pos (27U)
+#define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08000000 */
+#define XSPI_WPCCR_DDTR XSPI_WPCCR_DDTR_Msk /*!< Data Double Transfer Rate */
+#define XSPI_WPCCR_DQSE_Pos (29U)
+#define XSPI_WPCCR_DQSE_Msk (0x1UL << XSPI_WPCCR_DQSE_Pos) /*!< 0x20000000 */
+#define XSPI_WPCCR_DQSE XSPI_WPCCR_DQSE_Msk /*!< DQS Enable */
+
+/**************** Bit definition for XSPI_WPTCR register *******************/
+#define XSPI_WPTCR_DCYC_Pos (0U)
+#define XSPI_WPTCR_DCYC_Msk (0x1FUL << XSPI_WPTCR_DCYC_Pos) /*!< 0x0000001F */
+#define XSPI_WPTCR_DCYC XSPI_WPTCR_DCYC_Msk /*!< Number of Dummy Cycles */
+#define XSPI_WPTCR_DHQC_Pos (28U)
+#define XSPI_WPTCR_DHQC_Msk (0x1UL << XSPI_WPTCR_DHQC_Pos) /*!< 0x10000000 */
+#define XSPI_WPTCR_DHQC XSPI_WPTCR_DHQC_Msk /*!< Delay Hold Quarter Cycle */
+#define XSPI_WPTCR_SSHIFT_Pos (30U)
+#define XSPI_WPTCR_SSHIFT_Msk (0x1UL << XSPI_WPTCR_SSHIFT_Pos) /*!< 0x40000000 */
+#define XSPI_WPTCR_SSHIFT XSPI_WPTCR_SSHIFT_Msk /*!< Sample Shift */
+
+/***************** Bit definition for XSPI_WPIR register *******************/
+#define XSPI_WPIR_INSTRUCTION_Pos (0U)
+#define XSPI_WPIR_INSTRUCTION_Msk (0xFFFFFFFFUL << XSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WPIR_INSTRUCTION XSPI_WPIR_INSTRUCTION_Msk /*!< Instruction */
+
+/**************** Bit definition for XSPI_WPABR register *******************/
+#define XSPI_WPABR_ALTERNATE_Pos (0U)
+#define XSPI_WPABR_ALTERNATE_Msk (0xFFFFFFFFUL << XSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WPABR_ALTERNATE XSPI_WPABR_ALTERNATE_Msk /*!< Alternate Bytes */
+
+/**************** Bit definition for XSPI_WCCRregister *********************/
+#define XSPI_WCCR_IMODE_Pos (0U)
+#define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000007 */
+#define XSPI_WCCR_IMODE XSPI_WCCR_IMODE_Msk /*!< Instruction Mode */
+#define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000001 */
+#define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000002 */
+#define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000004 */
+#define XSPI_WCCR_IDTR_Pos (3U)
+#define XSPI_WCCR_IDTR_Msk (0x1UL << XSPI_WCCR_IDTR_Pos) /*!< 0x00000008 */
+#define XSPI_WCCR_IDTR XSPI_WCCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
+#define XSPI_WCCR_ISIZE_Pos (4U)
+#define XSPI_WCCR_ISIZE_Msk (0x3UL << XSPI_WCCR_ISIZE_Pos) /*!< 0x00000030 */
+#define XSPI_WCCR_ISIZE XSPI_WCCR_ISIZE_Msk /*!< Instruction Size */
+#define XSPI_WCCR_ISIZE_0 (0x1UL << XSPI_WCCR_ISIZE_Pos) /*!< 0x00000010 */
+#define XSPI_WCCR_ISIZE_1 (0x2UL << XSPI_WCCR_ISIZE_Pos) /*!< 0x00000020 */
+#define XSPI_WCCR_ADMODE_Pos (8U)
+#define XSPI_WCCR_ADMODE_Msk (0x7UL << XSPI_WCCR_ADMODE_Pos) /*!< 0x00000700 */
+#define XSPI_WCCR_ADMODE XSPI_WCCR_ADMODE_Msk /*!< Address Mode */
+#define XSPI_WCCR_ADMODE_0 (0x1UL << XSPI_WCCR_ADMODE_Pos) /*!< 0x00000100 */
+#define XSPI_WCCR_ADMODE_1 (0x2UL << XSPI_WCCR_ADMODE_Pos) /*!< 0x00000200 */
+#define XSPI_WCCR_ADMODE_2 (0x4UL << XSPI_WCCR_ADMODE_Pos) /*!< 0x00000400 */
+#define XSPI_WCCR_ADDTR_Pos (11U)
+#define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00000800 */
+#define XSPI_WCCR_ADDTR XSPI_WCCR_ADDTR_Msk /*!< Address Double Transfer Rate */
+#define XSPI_WCCR_ADSIZE_Pos (12U)
+#define XSPI_WCCR_ADSIZE_Msk (0x3UL << XSPI_WCCR_ADSIZE_Pos) /*!< 0x00003000 */
+#define XSPI_WCCR_ADSIZE XSPI_WCCR_ADSIZE_Msk /*!< Address Size */
+#define XSPI_WCCR_ADSIZE_0 (0x1UL << XSPI_WCCR_ADSIZE_Pos) /*!< 0x00001000 */
+#define XSPI_WCCR_ADSIZE_1 (0x2UL << XSPI_WCCR_ADSIZE_Pos) /*!< 0x00002000 */
+#define XSPI_WCCR_ABMODE_Pos (16U)
+#define XSPI_WCCR_ABMODE_Msk (0x7UL << XSPI_WCCR_ABMODE_Pos) /*!< 0x00070000 */
+#define XSPI_WCCR_ABMODE XSPI_WCCR_ABMODE_Msk /*!< Alternate Bytes Mode */
+#define XSPI_WCCR_ABMODE_0 (0x1UL << XSPI_WCCR_ABMODE_Pos) /*!< 0x00010000 */
+#define XSPI_WCCR_ABMODE_1 (0x2UL << XSPI_WCCR_ABMODE_Pos) /*!< 0x00020000 */
+#define XSPI_WCCR_ABMODE_2 (0x4UL << XSPI_WCCR_ABMODE_Pos) /*!< 0x00040000 */
+#define XSPI_WCCR_ABDTR_Pos (19U)
+#define XSPI_WCCR_ABDTR_Msk (0x1UL << XSPI_WCCR_ABDTR_Pos) /*!< 0x00080000 */
+#define XSPI_WCCR_ABDTR XSPI_WCCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
+#define XSPI_WCCR_ABSIZE_Pos (20U)
+#define XSPI_WCCR_ABSIZE_Msk (0x3UL << XSPI_WCCR_ABSIZE_Pos) /*!< 0x00300000 */
+#define XSPI_WCCR_ABSIZE XSPI_WCCR_ABSIZE_Msk /*!< Alternate Bytes Size */
+#define XSPI_WCCR_ABSIZE_0 (0x1UL << XSPI_WCCR_ABSIZE_Pos) /*!< 0x00100000 */
+#define XSPI_WCCR_ABSIZE_1 (0x2UL << XSPI_WCCR_ABSIZE_Pos) /*!< 0x00200000 */
+#define XSPI_WCCR_DMODE_Pos (24U)
+#define XSPI_WCCR_DMODE_Msk (0x7UL << XSPI_WCCR_DMODE_Pos) /*!< 0x07000000 */
+#define XSPI_WCCR_DMODE XSPI_WCCR_DMODE_Msk /*!< Data Mode */
+#define XSPI_WCCR_DMODE_0 (0x1UL << XSPI_WCCR_DMODE_Pos) /*!< 0x01000000 */
+#define XSPI_WCCR_DMODE_1 (0x2UL << XSPI_WCCR_DMODE_Pos) /*!< 0x02000000 */
+#define XSPI_WCCR_DMODE_2 (0x4UL << XSPI_WCCR_DMODE_Pos) /*!< 0x04000000 */
+#define XSPI_WCCR_DDTR_Pos (27U)
+#define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08000000 */
+#define XSPI_WCCR_DDTR XSPI_WCCR_DDTR_Msk /*!< Data Double Transfer Rate */
+#define XSPI_WCCR_DQSE_Pos (29U)
+#define XSPI_WCCR_DQSE_Msk (0x1UL << XSPI_WCCR_DQSE_Pos) /*!< 0x20000000 */
+#define XSPI_WCCR_DQSE XSPI_WCCR_DQSE_Msk /*!< DQS Enable */
+
+/**************** Bit definition for XSPI_WTCR register ********************/
+#define XSPI_WTCR_DCYC_Pos (0U)
+#define XSPI_WTCR_DCYC_Msk (0x1FUL << XSPI_WTCR_DCYC_Pos) /*!< 0x0000001F */
+#define XSPI_WTCR_DCYC XSPI_WTCR_DCYC_Msk /*!< Number of Dummy Cycles */
+
+/**************** Bit definition for XSPI_WIR register *********************/
+#define XSPI_WIR_INSTRUCTION_Pos (0U)
+#define XSPI_WIR_INSTRUCTION_Msk (0xFFFFFFFFUL << XSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WIR_INSTRUCTION XSPI_WIR_INSTRUCTION_Msk /*!< Instruction */
+
+/**************** Bit definition for XSPI_WABR register ********************/
+#define XSPI_WABR_ALTERNATE_Pos (0U)
+#define XSPI_WABR_ALTERNATE_Msk (0xFFFFFFFFUL << XSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WABR_ALTERNATE XSPI_WABR_ALTERNATE_Msk /*!< Alternate Bytes */
+
+/**************** Bit definition for XSPI_HLCR register ********************/
+#define XSPI_HLCR_LM_Pos (0U)
+#define XSPI_HLCR_LM_Msk (0x1UL << XSPI_HLCR_LM_Pos) /*!< 0x00000001 */
+#define XSPI_HLCR_LM XSPI_HLCR_LM_Msk /*!< Latency Mode */
+#define XSPI_HLCR_WZL_Pos (1U)
+#define XSPI_HLCR_WZL_Msk (0x1UL << XSPI_HLCR_WZL_Pos) /*!< 0x00000002 */
+#define XSPI_HLCR_WZL XSPI_HLCR_WZL_Msk /*!< Write Zero Latency */
+#define XSPI_HLCR_TACC_Pos (8U)
+#define XSPI_HLCR_TACC_Msk (0xFFUL << XSPI_HLCR_TACC_Pos) /*!< 0x0000FF00 */
+#define XSPI_HLCR_TACC XSPI_HLCR_TACC_Msk /*!< Access Time */
+#define XSPI_HLCR_TRWR_Pos (16U)
+#define XSPI_HLCR_TRWR_Msk (0xFFUL << XSPI_HLCR_TRWR_Pos) /*!< 0x00FF0000 */
+#define XSPI_HLCR_TRWR XSPI_HLCR_TRWR_Msk /*!< Read Write Recovery Time */
+
+/******************************************************************************/
+/* */
/* OCTOSPI */
/* */
/******************************************************************************/
/***************** Bit definition for OCTOSPI_CR register *******************/
-#define OCTOSPI_CR_EN_Pos (0U)
-#define OCTOSPI_CR_EN_Msk (0x1UL << OCTOSPI_CR_EN_Pos) /*!< 0x00000001 */
-#define OCTOSPI_CR_EN OCTOSPI_CR_EN_Msk /*!< Enable */
-#define OCTOSPI_CR_ABORT_Pos (1U)
-#define OCTOSPI_CR_ABORT_Msk (0x1UL << OCTOSPI_CR_ABORT_Pos) /*!< 0x00000002 */
-#define OCTOSPI_CR_ABORT OCTOSPI_CR_ABORT_Msk /*!< Abort request */
-#define OCTOSPI_CR_DMAEN_Pos (2U)
-#define OCTOSPI_CR_DMAEN_Msk (0x1UL << OCTOSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
-#define OCTOSPI_CR_DMAEN OCTOSPI_CR_DMAEN_Msk /*!< DMA Enable */
-#define OCTOSPI_CR_TCEN_Pos (3U)
-#define OCTOSPI_CR_TCEN_Msk (0x1UL << OCTOSPI_CR_TCEN_Pos) /*!< 0x00000008 */
-#define OCTOSPI_CR_TCEN OCTOSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
-#define OCTOSPI_CR_DQM_Pos (6U)
-#define OCTOSPI_CR_DQM_Msk (0x1UL << OCTOSPI_CR_DQM_Pos) /*!< 0x00000040 */
-#define OCTOSPI_CR_DQM OCTOSPI_CR_DQM_Msk /*!< Dual-Quad Mode */
-#define OCTOSPI_CR_FSEL_Pos (7U)
-#define OCTOSPI_CR_FSEL_Msk (0x1UL << OCTOSPI_CR_FSEL_Pos) /*!< 0x00000080 */
-#define OCTOSPI_CR_FSEL OCTOSPI_CR_FSEL_Msk /*!< Flash Select */
-#define OCTOSPI_CR_FTHRES_Pos (8U)
-#define OCTOSPI_CR_FTHRES_Msk (0x1FUL << OCTOSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
-#define OCTOSPI_CR_FTHRES OCTOSPI_CR_FTHRES_Msk /*!< FIFO Threshold Level */
-#define OCTOSPI_CR_TEIE_Pos (16U)
-#define OCTOSPI_CR_TEIE_Msk (0x1UL << OCTOSPI_CR_TEIE_Pos) /*!< 0x00010000 */
-#define OCTOSPI_CR_TEIE OCTOSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
-#define OCTOSPI_CR_TCIE_Pos (17U)
-#define OCTOSPI_CR_TCIE_Msk (0x1UL << OCTOSPI_CR_TCIE_Pos) /*!< 0x00020000 */
-#define OCTOSPI_CR_TCIE OCTOSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
-#define OCTOSPI_CR_FTIE_Pos (18U)
-#define OCTOSPI_CR_FTIE_Msk (0x1UL << OCTOSPI_CR_FTIE_Pos) /*!< 0x00040000 */
-#define OCTOSPI_CR_FTIE OCTOSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
-#define OCTOSPI_CR_SMIE_Pos (19U)
-#define OCTOSPI_CR_SMIE_Msk (0x1UL << OCTOSPI_CR_SMIE_Pos) /*!< 0x00080000 */
-#define OCTOSPI_CR_SMIE OCTOSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
-#define OCTOSPI_CR_TOIE_Pos (20U)
-#define OCTOSPI_CR_TOIE_Msk (0x1UL << OCTOSPI_CR_TOIE_Pos) /*!< 0x00100000 */
-#define OCTOSPI_CR_TOIE OCTOSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
-#define OCTOSPI_CR_APMS_Pos (22U)
-#define OCTOSPI_CR_APMS_Msk (0x1UL << OCTOSPI_CR_APMS_Pos) /*!< 0x00400000 */
-#define OCTOSPI_CR_APMS OCTOSPI_CR_APMS_Msk /*!< Automatic Poll Mode Stop */
-#define OCTOSPI_CR_PMM_Pos (23U)
-#define OCTOSPI_CR_PMM_Msk (0x1UL << OCTOSPI_CR_PMM_Pos) /*!< 0x00800000 */
-#define OCTOSPI_CR_PMM OCTOSPI_CR_PMM_Msk /*!< Polling Match Mode */
-#define OCTOSPI_CR_FMODE_Pos (28U)
-#define OCTOSPI_CR_FMODE_Msk (0x3UL << OCTOSPI_CR_FMODE_Pos) /*!< 0x30000000 */
-#define OCTOSPI_CR_FMODE OCTOSPI_CR_FMODE_Msk /*!< Functional Mode */
-#define OCTOSPI_CR_FMODE_0 (0x1UL << OCTOSPI_CR_FMODE_Pos) /*!< 0x10000000 */
-#define OCTOSPI_CR_FMODE_1 (0x2UL << OCTOSPI_CR_FMODE_Pos) /*!< 0x20000000 */
+#define OCTOSPI_CR_EN_Pos XSPI_CR_EN_Pos
+#define OCTOSPI_CR_EN_Msk XSPI_CR_EN_Msk /*!< 0x00000001 */
+#define OCTOSPI_CR_EN XSPI_CR_EN /*!< Enable */
+#define OCTOSPI_CR_ABORT_Pos XSPI_CR_ABORT_Pos
+#define OCTOSPI_CR_ABORT_Msk XSPI_CR_ABORT_Msk /*!< 0x00000002 */
+#define OCTOSPI_CR_ABORT XSPI_CR_ABORT /*!< Abort request */
+#define OCTOSPI_CR_DMAEN_Pos XSPI_CR_DMAEN_Pos
+#define OCTOSPI_CR_DMAEN_Msk XSPI_CR_DMAEN_Msk /*!< 0x00000004 */
+#define OCTOSPI_CR_DMAEN XSPI_CR_DMAEN /*!< DMA Enable */
+#define OCTOSPI_CR_TCEN_Pos XSPI_CR_TCEN_Pos
+#define OCTOSPI_CR_TCEN_Msk XSPI_CR_TCEN_Msk /*!< 0x00000008 */
+#define OCTOSPI_CR_TCEN XSPI_CR_TCEN /*!< Timeout Counter Enable */
+#define OCTOSPI_CR_DMM_Pos XSPI_CR_DMM_Pos
+#define OCTOSPI_CR_DMM_Msk XSPI_CR_DMM_Msk /*!< 0x00000040 */
+#define OCTOSPI_CR_DMM XSPI_CR_DMM /*!< Dual Memory Mode */
+#define OCTOSPI_CR_MSEL_Pos XSPI_OCTOSPI_CR_MSEL_Pos
+#define OCTOSPI_CR_MSEL_Msk XSPI_OCTOSPI_CR_MSEL_Msk /*!< 0x00000080 */
+#define OCTOSPI_CR_MSEL XSPI_OCTOSPI_CR_MSEL /*!< Memory Select */
+#define OCTOSPI_CR_FTHRES_Pos XSPI_CR_FTHRES_Pos
+#define OCTOSPI_CR_FTHRES_Msk (0x1FUL << OCTOSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
+#define OCTOSPI_CR_FTHRES XSPI_CR_FTHRES /*!< FIFO Threshold Level */
+#define OCTOSPI_CR_TEIE_Pos XSPI_CR_TEIE_Pos
+#define OCTOSPI_CR_TEIE_Msk XSPI_CR_TEIE_Msk /*!< 0x00010000 */
+#define OCTOSPI_CR_TEIE XSPI_CR_TEIE /*!< Transfer Error Interrupt Enable */
+#define OCTOSPI_CR_TCIE_Pos XSPI_CR_TCIE_Pos
+#define OCTOSPI_CR_TCIE_Msk XSPI_CR_TCIE_Msk /*!< 0x00020000 */
+#define OCTOSPI_CR_TCIE XSPI_CR_TCIE /*!< Transfer Complete Interrupt Enable */
+#define OCTOSPI_CR_FTIE_Pos XSPI_CR_FTIE_Pos
+#define OCTOSPI_CR_FTIE_Msk XSPI_CR_FTIE_Msk) /*!< 0x00040000 */
+#define OCTOSPI_CR_FTIE XSPI_CR_FTIE /*!< FIFO Threshold Interrupt Enable */
+#define OCTOSPI_CR_SMIE_Pos XSPI_CR_SMIE_Pos
+#define OCTOSPI_CR_SMIE_Msk XSPI_CR_SMIE_Msk /*!< 0x00080000 */
+#define OCTOSPI_CR_SMIE XSPI_CR_SMIE /*!< Status Match Interrupt Enable */
+#define OCTOSPI_CR_TOIE_Pos XSPI_CR_TOIE_Pos
+#define OCTOSPI_CR_TOIE_Msk XSPI_CR_TOIE_Msk /*!< 0x00100000 */
+#define OCTOSPI_CR_TOIE XSPI_CR_TOIE /*!< TimeOut Interrupt Enable */
+#define OCTOSPI_CR_APMS_Pos XSPI_CR_APMS_Pos
+#define OCTOSPI_CR_APMS_Msk XSPI_CR_APMS_Msk /*!< 0x00400000 */
+#define OCTOSPI_CR_APMS XSPI_CR_APMS /*!< Automatic Poll Mode Stop */
+#define OCTOSPI_CR_PMM_Pos XSPI_CR_PMM_Pos
+#define OCTOSPI_CR_PMM_Msk XSPI_CR_PMM_Msk /*!< 0x00800000 */
+#define OCTOSPI_CR_PMM XSPI_CR_PMM /*!< Polling Match Mode */
+#define OCTOSPI_CR_FMODE_Pos XSPI_CR_FMODE_Pos
+#define OCTOSPI_CR_FMODE_Msk XSPI_CR_FMODE_Msk /*!< 0x30000000 */
+#define OCTOSPI_CR_FMODE XSPI_CR_FMODE /*!< Functional Mode */
+#define OCTOSPI_CR_FMODE_0 XSPI_CR_FMODE_0 /*!< 0x10000000 */
+#define OCTOSPI_CR_FMODE_1 XSPI_CR_FMODE_1 /*!< 0x20000000 */
+
+/* Legacy Bit definition for OCTOSPI_CR register */
+#define OCTOSPI_CR_DQM XSPI_CR_DMM /*!< Legacy Dual Memory Mode */
+#define OCTOSPI_CR_FSEL XSPI_OCTOSPI_CR_MSEL /*!< Legacy Memory Select */
/**************** Bit definition for OCTOSPI_DCR1 register ******************/
-#define OCTOSPI_DCR1_CKMODE_Pos (0U)
-#define OCTOSPI_DCR1_CKMODE_Msk (0x1UL << OCTOSPI_DCR1_CKMODE_Pos) /*!< 0x00000001 */
-#define OCTOSPI_DCR1_CKMODE OCTOSPI_DCR1_CKMODE_Msk /*!< Mode 0 / Mode 3 */
-#define OCTOSPI_DCR1_FRCK_Pos (1U)
-#define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */
-#define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */
-#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
-#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
-#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */
-#define OCTOSPI_DCR1_CSHT_Pos (8U)
-#define OCTOSPI_DCR1_CSHT_Msk (0x3FUL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00003F00 */
-#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
-#define OCTOSPI_DCR1_DEVSIZE_Pos (16U)
-#define OCTOSPI_DCR1_DEVSIZE_Msk (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos) /*!< 0x001F0000 */
-#define OCTOSPI_DCR1_DEVSIZE OCTOSPI_DCR1_DEVSIZE_Msk /*!< Device Size */
-#define OCTOSPI_DCR1_MTYP_Pos (24U)
-#define OCTOSPI_DCR1_MTYP_Msk (0x7UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x07000000 */
-#define OCTOSPI_DCR1_MTYP OCTOSPI_DCR1_MTYP_Msk /*!< Memory Type */
-#define OCTOSPI_DCR1_MTYP_0 (0x1UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */
-#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
-#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
+#define OCTOSPI_DCR1_CKMODE_Pos XSPI_DCR1_CKMODE_Pos
+#define OCTOSPI_DCR1_CKMODE_Msk XSPI_DCR1_CKMODE_Msk /*!< 0x00000001 */
+#define OCTOSPI_DCR1_CKMODE XSPI_DCR1_CKMODE /*!< Mode 0 / Mode 3 */
+#define OCTOSPI_DCR1_FRCK_Pos XSPI_DCR1_FRCK_Pos
+#define OCTOSPI_DCR1_FRCK_Msk XSPI_DCR1_FRCK_Msk /*!< 0x00000002 */
+#define OCTOSPI_DCR1_FRCK XSPI_DCR1_FRCK /*!< Free Running Clock */
+#define OCTOSPI_DCR1_DLYBYP_Pos XSPI_OCTOSPI_DCR1_DLYBYP_Pos
+#define OCTOSPI_DCR1_DLYBYP_Msk XSPI_OCTOSPI_DCR1_DLYBYP_Msk /*!< 0x00000008 */
+#define OCTOSPI_DCR1_DLYBYP XSPI_OCTOSPI_DCR1_DLYBYP /*!< Delay Block Bypass */
+#define OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
+#define OCTOSPI_DCR1_CSHT_Msk XSPI_DCR1_CSHT_Msk /*!< 0x00003F00 */
+#define OCTOSPI_DCR1_CSHT XSPI_DCR1_CSHT /*!< Chip Select High Time */
+#define OCTOSPI_DCR1_DEVSIZE_Pos XSPI_DCR1_DEVSIZE_Pos
+#define OCTOSPI_DCR1_DEVSIZE_Msk XSPI_DCR1_DEVSIZE_Msk /*!< 0x001F0000 */
+#define OCTOSPI_DCR1_DEVSIZE XSPI_DCR1_DEVSIZE /*!< Device Size */
+#define OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
+#define OCTOSPI_DCR1_MTYP_Msk XSPI_DCR1_MTYP_Msk /*!< 0x07000000 */
+#define OCTOSPI_DCR1_MTYP XSPI_DCR1_MTYP /*!< Memory Type */
+#define OCTOSPI_DCR1_MTYP_0 XSPI_DCR1_MTYP_0 /*!< 0x01000000 */
+#define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02000000 */
+#define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04000000 */
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
-#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
-#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
-#define OCTOSPI_DCR2_PRESCALER OCTOSPI_DCR2_PRESCALER_Msk /*!< Clock prescaler */
-#define OCTOSPI_DCR2_WRAPSIZE_Pos (16U)
-#define OCTOSPI_DCR2_WRAPSIZE_Msk (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */
-#define OCTOSPI_DCR2_WRAPSIZE OCTOSPI_DCR2_WRAPSIZE_Msk /*!< Wrap Size */
-#define OCTOSPI_DCR2_WRAPSIZE_0 (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */
-#define OCTOSPI_DCR2_WRAPSIZE_1 (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */
-#define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */
+#define OCTOSPI_DCR2_PRESCALER_Pos XSPI_DCR2_PRESCALER_Pos
+#define OCTOSPI_DCR2_PRESCALER_Msk XSPI_DCR2_PRESCALER_Msk /*!< 0x000000FF */
+#define OCTOSPI_DCR2_PRESCALER XSPI_DCR2_PRESCALER /*!< Clock prescaler */
+#define OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
+#define OCTOSPI_DCR2_WRAPSIZE_Msk XSPI_DCR2_WRAPSIZE_Msk /*!< 0x00070000 */
+#define OCTOSPI_DCR2_WRAPSIZE XSPI_DCR2_WRAPSIZE /*!< Wrap Size */
+#define OCTOSPI_DCR2_WRAPSIZE_0 XSPI_DCR2_WRAPSIZE_0 /*!< 0x00010000 */
+#define OCTOSPI_DCR2_WRAPSIZE_1 XSPI_DCR2_WRAPSIZE_1 /*!< 0x00020000 */
+#define OCTOSPI_DCR2_WRAPSIZE_2 XSPI_DCR2_WRAPSIZE_2 /*!< 0x00040000 */
/**************** Bit definition for OCTOSPI_DCR3 register ******************/
-#define OCTOSPI_DCR3_MAXTRAN_Pos (0U)
-#define OCTOSPI_DCR3_MAXTRAN_Msk (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos) /*!< 0x000000FF */
-#define OCTOSPI_DCR3_MAXTRAN OCTOSPI_DCR3_MAXTRAN_Msk /*!< Maximum transfer */
-#define OCTOSPI_DCR3_CSBOUND_Pos (16U)
-#define OCTOSPI_DCR3_CSBOUND_Msk (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */
-#define OCTOSPI_DCR3_CSBOUND OCTOSPI_DCR3_CSBOUND_Msk /*!< Maximum transfer */
+#define OCTOSPI_DCR3_MAXTRAN_Pos XSPI_OCTOSPI_DCR3_MAXTRAN_Pos
+#define OCTOSPI_DCR3_MAXTRAN_Msk XSPI_OCTOSPI_DCR3_MAXTRAN_Msk /*!< 0x000000FF */
+#define OCTOSPI_DCR3_MAXTRAN XSPI_OCTOSPI_DCR3_MAXTRAN /*!< Maximum transfer */
+#define OCTOSPI_DCR3_CSBOUND_Pos XSPI_DCR3_CSBOUND_Pos
+#define OCTOSPI_DCR3_CSBOUND_Msk XSPI_DCR3_CSBOUND_Msk /*!< 0x001F0000 */
+#define OCTOSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND /*!< Maximum transfer */
/**************** Bit definition for OCTOSPI_DCR4 register ******************/
-#define OCTOSPI_DCR4_REFRESH_Pos (0U)
-#define OCTOSPI_DCR4_REFRESH_Msk (0xFFFFFFFFUL << OCTOSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */
-#define OCTOSPI_DCR4_REFRESH OCTOSPI_DCR4_REFRESH_Msk /*!< Refresh rate */
+#define OCTOSPI_DCR4_REFRESH_Pos XSPI_DCR4_REFRESH_Pos
+#define OCTOSPI_DCR4_REFRESH_Msk XSPI_DCR4_REFRESH_Msk /*!< 0xFFFFFFFF */
+#define OCTOSPI_DCR4_REFRESH XSPI_DCR4_REFRESH /*!< Refresh rate */
/***************** Bit definition for OCTOSPI_SR register *******************/
-#define OCTOSPI_SR_TEF_Pos (0U)
-#define OCTOSPI_SR_TEF_Msk (0x1UL << OCTOSPI_SR_TEF_Pos) /*!< 0x00000001 */
-#define OCTOSPI_SR_TEF OCTOSPI_SR_TEF_Msk /*!< Transfer Error Flag */
-#define OCTOSPI_SR_TCF_Pos (1U)
-#define OCTOSPI_SR_TCF_Msk (0x1UL << OCTOSPI_SR_TCF_Pos) /*!< 0x00000002 */
-#define OCTOSPI_SR_TCF OCTOSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
-#define OCTOSPI_SR_FTF_Pos (2U)
-#define OCTOSPI_SR_FTF_Msk (0x1UL << OCTOSPI_SR_FTF_Pos) /*!< 0x00000004 */
-#define OCTOSPI_SR_FTF OCTOSPI_SR_FTF_Msk /*!< FIFO Threshold Flag */
-#define OCTOSPI_SR_SMF_Pos (3U)
-#define OCTOSPI_SR_SMF_Msk (0x1UL << OCTOSPI_SR_SMF_Pos) /*!< 0x00000008 */
-#define OCTOSPI_SR_SMF OCTOSPI_SR_SMF_Msk /*!< Status Match Flag */
-#define OCTOSPI_SR_TOF_Pos (4U)
-#define OCTOSPI_SR_TOF_Msk (0x1UL << OCTOSPI_SR_TOF_Pos) /*!< 0x00000010 */
-#define OCTOSPI_SR_TOF OCTOSPI_SR_TOF_Msk /*!< Timeout Flag */
-#define OCTOSPI_SR_BUSY_Pos (5U)
-#define OCTOSPI_SR_BUSY_Msk (0x1UL << OCTOSPI_SR_BUSY_Pos) /*!< 0x00000020 */
-#define OCTOSPI_SR_BUSY OCTOSPI_SR_BUSY_Msk /*!< Busy */
-#define OCTOSPI_SR_FLEVEL_Pos (8U)
-#define OCTOSPI_SR_FLEVEL_Msk (0x3FUL << OCTOSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
-#define OCTOSPI_SR_FLEVEL OCTOSPI_SR_FLEVEL_Msk /*!< FIFO Level */
+#define OCTOSPI_SR_TEF_Pos XSPI_SR_TEF_Pos
+#define OCTOSPI_SR_TEF_Msk XSPI_SR_TEF_Msk /*!< 0x00000001 */
+#define OCTOSPI_SR_TEF XSPI_SR_TEF /*!< Transfer Error Flag */
+#define OCTOSPI_SR_TCF_Pos XSPI_SR_TCF_Pos
+#define OCTOSPI_SR_TCF_Msk XSPI_SR_TCF_Msk /*!< 0x00000002 */
+#define OCTOSPI_SR_TCF XSPI_SR_TCF /*!< Transfer Complete Flag */
+#define OCTOSPI_SR_FTF_Pos XSPI_SR_FTF_Pos
+#define OCTOSPI_SR_FTF_Msk XSPI_SR_FTF_Msk /*!< 0x00000004 */
+#define OCTOSPI_SR_FTF XSPI_SR_FTF /*!< FIFO Threshold Flag */
+#define OCTOSPI_SR_SMF_Pos XSPI_SR_SMF_Pos
+#define OCTOSPI_SR_SMF_Msk XSPI_SR_SMF_Msk /*!< 0x00000008 */
+#define OCTOSPI_SR_SMF XSPI_SR_SMF /*!< Status Match Flag */
+#define OCTOSPI_SR_TOF_Pos XSPI_SR_TOF_Pos
+#define OCTOSPI_SR_TOF_Msk XSPI_SR_TOF_Msk /*!< 0x00000010 */
+#define OCTOSPI_SR_TOF XSPI_SR_TOF /*!< Timeout Flag */
+#define OCTOSPI_SR_BUSY_Pos XSPI_SR_BUSY_Pos
+#define OCTOSPI_SR_BUSY_Msk XSPI_SR_BUSY_Msk /*!< 0x00000020 */
+#define OCTOSPI_SR_BUSY XSPI_SR_BUSY /*!< Busy */
+#define OCTOSPI_SR_FLEVEL_Pos XSPI_SR_FLEVEL_Pos
+#define OCTOSPI_SR_FLEVEL_Msk (0x3FUL << OCTOSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
+#define OCTOSPI_SR_FLEVEL XSPI_SR_FLEVEL /*!< FIFO Level */
/**************** Bit definition for OCTOSPI_FCR register *******************/
-#define OCTOSPI_FCR_CTEF_Pos (0U)
-#define OCTOSPI_FCR_CTEF_Msk (0x1UL << OCTOSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
-#define OCTOSPI_FCR_CTEF OCTOSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
-#define OCTOSPI_FCR_CTCF_Pos (1U)
-#define OCTOSPI_FCR_CTCF_Msk (0x1UL << OCTOSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
-#define OCTOSPI_FCR_CTCF OCTOSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
-#define OCTOSPI_FCR_CSMF_Pos (3U)
-#define OCTOSPI_FCR_CSMF_Msk (0x1UL << OCTOSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
-#define OCTOSPI_FCR_CSMF OCTOSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
-#define OCTOSPI_FCR_CTOF_Pos (4U)
-#define OCTOSPI_FCR_CTOF_Msk (0x1UL << OCTOSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
-#define OCTOSPI_FCR_CTOF OCTOSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
+#define OCTOSPI_FCR_CTEF_Pos XSPI_FCR_CTEF_Pos
+#define OCTOSPI_FCR_CTEF_Msk XSPI_FCR_CTEF_Msk /*!< 0x00000001 */
+#define OCTOSPI_FCR_CTEF XSPI_FCR_CTEF /*!< Clear Transfer Error Flag */
+#define OCTOSPI_FCR_CTCF_Pos XSPI_FCR_CTCF_Pos
+#define OCTOSPI_FCR_CTCF_Msk XSPI_FCR_CTCF_Msk /*!< 0x00000002 */
+#define OCTOSPI_FCR_CTCF XSPI_FCR_CTCF /*!< Clear Transfer Complete Flag */
+#define OCTOSPI_FCR_CSMF_Pos XSPI_FCR_CSMF_Pos
+#define OCTOSPI_FCR_CSMF_Msk XSPI_FCR_CSMF_Msk /*!< 0x00000008 */
+#define OCTOSPI_FCR_CSMF XSPI_FCR_CSMF /*!< Clear Status Match Flag */
+#define OCTOSPI_FCR_CTOF_Pos XSPI_FCR_CTOF_Pos
+#define OCTOSPI_FCR_CTOF_Msk XSPI_FCR_CTOF_Msk /*!< 0x00000010 */
+#define OCTOSPI_FCR_CTOF XSPI_FCR_CTOF /*!< Clear Timeout Flag */
/**************** Bit definition for OCTOSPI_DLR register *******************/
-#define OCTOSPI_DLR_DL_Pos (0U)
-#define OCTOSPI_DLR_DL_Msk (0xFFFFFFFFUL << OCTOSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
-#define OCTOSPI_DLR_DL OCTOSPI_DLR_DL_Msk /*!< Data Length */
+#define OCTOSPI_DLR_DL_Pos XSPI_DLR_DL_Pos
+#define OCTOSPI_DLR_DL_Msk XSPI_DLR_DL_Msk /*!< 0xFFFFFFFF */
+#define OCTOSPI_DLR_DL XSPI_DLR_DL /*!< Data Length */
/***************** Bit definition for OCTOSPI_AR register *******************/
-#define OCTOSPI_AR_ADDRESS_Pos (0U)
-#define OCTOSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << OCTOSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define OCTOSPI_AR_ADDRESS OCTOSPI_AR_ADDRESS_Msk /*!< Address */
+#define OCTOSPI_AR_ADDRESS_Pos XSPI_AR_ADDRESS_Pos
+#define OCTOSPI_AR_ADDRESS_Msk XSPI_AR_ADDRESS_Msk /*!< 0xFFFFFFFF */
+#define OCTOSPI_AR_ADDRESS XSPI_AR_ADDRESS /*!< Address */
/***************** Bit definition for OCTOSPI_DR register *******************/
-#define OCTOSPI_DR_DATA_Pos (0U)
-#define OCTOSPI_DR_DATA_Msk (0xFFFFFFFFUL << OCTOSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
-#define OCTOSPI_DR_DATA OCTOSPI_DR_DATA_Msk /*!< Data */
+#define OCTOSPI_DR_DATA_Pos XSPI_DR_DATA_Pos
+#define OCTOSPI_DR_DATA_Msk XSPI_DR_DATA_Msk /*!< 0xFFFFFFFF */
+#define OCTOSPI_DR_DATA XSPI_DR_DATA /*!< Data */
/*************** Bit definition for OCTOSPI_PSMKR register ******************/
-#define OCTOSPI_PSMKR_MASK_Pos (0U)
-#define OCTOSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << OCTOSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
-#define OCTOSPI_PSMKR_MASK OCTOSPI_PSMKR_MASK_Msk /*!< Status mask */
+#define OCTOSPI_PSMKR_MASK_Pos XSPI_PSMKR_MASK_Pos
+#define OCTOSPI_PSMKR_MASK_Msk XSPI_PSMKR_MASK_Msk /*!< 0xFFFFFFFF */
+#define OCTOSPI_PSMKR_MASK XSPI_PSMKR_MASK /*!< Status mask */
/*************** Bit definition for OCTOSPI_PSMAR register ******************/
-#define OCTOSPI_PSMAR_MATCH_Pos (0U)
-#define OCTOSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << OCTOSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
-#define OCTOSPI_PSMAR_MATCH OCTOSPI_PSMAR_MATCH_Msk /*!< Status match */
+#define OCTOSPI_PSMAR_MATCH_Pos XSPI_PSMAR_MATCH_Pos
+#define OCTOSPI_PSMAR_MATCH_Msk XSPI_PSMAR_MATCH_Msk /*!< 0xFFFFFFFF */
+#define OCTOSPI_PSMAR_MATCH XSPI_PSMAR_MATCH /*!< Status match */
/**************** Bit definition for OCTOSPI_PIR register *******************/
-#define OCTOSPI_PIR_INTERVAL_Pos (0U)
-#define OCTOSPI_PIR_INTERVAL_Msk (0xFFFFUL << OCTOSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
-#define OCTOSPI_PIR_INTERVAL OCTOSPI_PIR_INTERVAL_Msk /*!< Polling Interval */
+#define OCTOSPI_PIR_INTERVAL_Pos XSPI_PIR_INTERVAL_Pos
+#define OCTOSPI_PIR_INTERVAL_Msk XSPI_PIR_INTERVAL_Msk /*!< 0x0000FFFF */
+#define OCTOSPI_PIR_INTERVAL XSPI_PIR_INTERVAL /*!< Polling Interval */
/**************** Bit definition for OCTOSPI_CCR register *******************/
-#define OCTOSPI_CCR_IMODE_Pos (0U)
-#define OCTOSPI_CCR_IMODE_Msk (0x7UL << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000007 */
-#define OCTOSPI_CCR_IMODE OCTOSPI_CCR_IMODE_Msk /*!< Instruction Mode */
-#define OCTOSPI_CCR_IMODE_0 (0x1UL << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000001 */
-#define OCTOSPI_CCR_IMODE_1 (0x2UL << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000002 */
-#define OCTOSPI_CCR_IMODE_2 (0x4UL << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000004 */
-#define OCTOSPI_CCR_IDTR_Pos (3U)
-#define OCTOSPI_CCR_IDTR_Msk (0x1UL << OCTOSPI_CCR_IDTR_Pos) /*!< 0x00000008 */
-#define OCTOSPI_CCR_IDTR OCTOSPI_CCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
-#define OCTOSPI_CCR_ISIZE_Pos (4U)
-#define OCTOSPI_CCR_ISIZE_Msk (0x3UL << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000030 */
-#define OCTOSPI_CCR_ISIZE OCTOSPI_CCR_ISIZE_Msk /*!< Instruction Size */
-#define OCTOSPI_CCR_ISIZE_0 (0x1UL << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000010 */
-#define OCTOSPI_CCR_ISIZE_1 (0x2UL << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000020 */
-#define OCTOSPI_CCR_ADMODE_Pos (8U)
-#define OCTOSPI_CCR_ADMODE_Msk (0x7UL << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000700 */
-#define OCTOSPI_CCR_ADMODE OCTOSPI_CCR_ADMODE_Msk /*!< Address Mode */
-#define OCTOSPI_CCR_ADMODE_0 (0x1UL << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000100 */
-#define OCTOSPI_CCR_ADMODE_1 (0x2UL << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000200 */
-#define OCTOSPI_CCR_ADMODE_2 (0x4UL << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
-#define OCTOSPI_CCR_ADDTR_Pos (11U)
-#define OCTOSPI_CCR_ADDTR_Msk (0x1UL << OCTOSPI_CCR_ADDTR_Pos) /*!< 0x00000800 */
-#define OCTOSPI_CCR_ADDTR OCTOSPI_CCR_ADDTR_Msk /*!< Address Double Transfer Rate */
-#define OCTOSPI_CCR_ADSIZE_Pos (12U)
-#define OCTOSPI_CCR_ADSIZE_Msk (0x3UL << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
-#define OCTOSPI_CCR_ADSIZE OCTOSPI_CCR_ADSIZE_Msk /*!< Address Size */
-#define OCTOSPI_CCR_ADSIZE_0 (0x1UL << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
-#define OCTOSPI_CCR_ADSIZE_1 (0x2UL << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
-#define OCTOSPI_CCR_ABMODE_Pos (16U)
-#define OCTOSPI_CCR_ABMODE_Msk (0x7UL << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00070000 */
-#define OCTOSPI_CCR_ABMODE OCTOSPI_CCR_ABMODE_Msk /*!< Alternate Bytes Mode */
-#define OCTOSPI_CCR_ABMODE_0 (0x1UL << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00010000 */
-#define OCTOSPI_CCR_ABMODE_1 (0x2UL << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00020000 */
-#define OCTOSPI_CCR_ABMODE_2 (0x4UL << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00040000 */
-#define OCTOSPI_CCR_ABDTR_Pos (19U)
-#define OCTOSPI_CCR_ABDTR_Msk (0x1UL << OCTOSPI_CCR_ABDTR_Pos) /*!< 0x00080000 */
-#define OCTOSPI_CCR_ABDTR OCTOSPI_CCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
-#define OCTOSPI_CCR_ABSIZE_Pos (20U)
-#define OCTOSPI_CCR_ABSIZE_Msk (0x3UL << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00300000 */
-#define OCTOSPI_CCR_ABSIZE OCTOSPI_CCR_ABSIZE_Msk /*!< Alternate Bytes Size */
-#define OCTOSPI_CCR_ABSIZE_0 (0x1UL << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00100000 */
-#define OCTOSPI_CCR_ABSIZE_1 (0x2UL << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00200000 */
-#define OCTOSPI_CCR_DMODE_Pos (24U)
-#define OCTOSPI_CCR_DMODE_Msk (0x7UL << OCTOSPI_CCR_DMODE_Pos) /*!< 0x07000000 */
-#define OCTOSPI_CCR_DMODE OCTOSPI_CCR_DMODE_Msk /*!< Data Mode */
-#define OCTOSPI_CCR_DMODE_0 (0x1UL << OCTOSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
-#define OCTOSPI_CCR_DMODE_1 (0x2UL << OCTOSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
-#define OCTOSPI_CCR_DMODE_2 (0x4UL << OCTOSPI_CCR_DMODE_Pos) /*!< 0x04000000 */
-#define OCTOSPI_CCR_DDTR_Pos (27U)
-#define OCTOSPI_CCR_DDTR_Msk (0x1UL << OCTOSPI_CCR_DDTR_Pos) /*!< 0x08000000 */
-#define OCTOSPI_CCR_DDTR OCTOSPI_CCR_DDTR_Msk /*!< Data Double Transfer Rate */
-#define OCTOSPI_CCR_DQSE_Pos (29U)
-#define OCTOSPI_CCR_DQSE_Msk (0x1UL << OCTOSPI_CCR_DQSE_Pos) /*!< 0x20000000 */
-#define OCTOSPI_CCR_DQSE OCTOSPI_CCR_DQSE_Msk /*!< DQS Enable */
-#define OCTOSPI_CCR_SIOO_Pos (31U)
-#define OCTOSPI_CCR_SIOO_Msk (0x1UL << OCTOSPI_CCR_SIOO_Pos) /*!< 0x80000000 */
-#define OCTOSPI_CCR_SIOO OCTOSPI_CCR_SIOO_Msk /*!< Send Instruction Only Once Mode */
+#define OCTOSPI_CCR_IMODE_Pos XSPI_CCR_IMODE_Pos
+#define OCTOSPI_CCR_IMODE_Msk XSPI_CCR_IMODE_Msk /*!< 0x00000007 */
+#define OCTOSPI_CCR_IMODE XSPI_CCR_IMODE /*!< Instruction Mode */
+#define OCTOSPI_CCR_IMODE_0 XSPI_CCR_IMODE_0 /*!< 0x00000001 */
+#define OCTOSPI_CCR_IMODE_1 XSPI_CCR_IMODE_1 /*!< 0x00000002 */
+#define OCTOSPI_CCR_IMODE_2 XSPI_CCR_IMODE_2 /*!< 0x00000004 */
+#define OCTOSPI_CCR_IDTR_Pos XSPI_CCR_IDTR_Pos
+#define OCTOSPI_CCR_IDTR_Msk XSPI_CCR_IDTR_Msk /*!< 0x00000008 */
+#define OCTOSPI_CCR_IDTR XSPI_CCR_IDTR /*!< Instruction Double Transfer Rate */
+#define OCTOSPI_CCR_ISIZE_Pos XSPI_CCR_ISIZE_Pos
+#define OCTOSPI_CCR_ISIZE_Msk XSPI_CCR_ISIZE_Msk /*!< 0x00000030 */
+#define OCTOSPI_CCR_ISIZE XSPI_CCR_ISIZE /*!< Instruction Size */
+#define OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00000010 */
+#define OCTOSPI_CCR_ISIZE_1 XSPI_CCR_ISIZE_1 /*!< 0x00000020 */
+#define OCTOSPI_CCR_ADMODE_Pos XSPI_CCR_ADMODE_Pos
+#define OCTOSPI_CCR_ADMODE_Msk XSPI_CCR_ADMODE_Msk /*!< 0x00000700 */
+#define OCTOSPI_CCR_ADMODE XSPI_CCR_ADMODE /*!< Address Mode */
+#define OCTOSPI_CCR_ADMODE_0 XSPI_CCR_ADMODE_0 /*!< 0x00000100 */
+#define OCTOSPI_CCR_ADMODE_1 XSPI_CCR_ADMODE_1 /*!< 0x00000200 */
+#define OCTOSPI_CCR_ADMODE_2 XSPI_CCR_ADMODE_2 /*!< 0x00000400 */
+#define OCTOSPI_CCR_ADDTR_Pos XSPI_CCR_ADDTR_Pos
+#define OCTOSPI_CCR_ADDTR_Msk XSPI_CCR_ADDTR_Msk /*!< 0x00000800 */
+#define OCTOSPI_CCR_ADDTR XSPI_CCR_ADDTR /*!< Address Double Transfer Rate */
+#define OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
+#define OCTOSPI_CCR_ADSIZE_Msk XSPI_CCR_ADSIZE_Msk /*!< 0x00003000 */
+#define OCTOSPI_CCR_ADSIZE XSPI_CCR_ADSIZE /*!< Address Size */
+#define OCTOSPI_CCR_ADSIZE_0 XSPI_CCR_ADSIZE_0 /*!< 0x00001000 */
+#define OCTOSPI_CCR_ADSIZE_1 XSPI_CCR_ADSIZE_1 /*!< 0x00002000 */
+#define OCTOSPI_CCR_ABMODE_Pos XSPI_CCR_ABMODE_Pos
+#define OCTOSPI_CCR_ABMODE_Msk XSPI_CCR_ABMODE_Msk /*!< 0x00070000 */
+#define OCTOSPI_CCR_ABMODE XSPI_CCR_ABMODE /*!< Alternate Bytes Mode */
+#define OCTOSPI_CCR_ABMODE_0 XSPI_CCR_ABMODE_0 /*!< 0x00010000 */
+#define OCTOSPI_CCR_ABMODE_1 XSPI_CCR_ABMODE_1 /*!< 0x00020000 */
+#define OCTOSPI_CCR_ABMODE_2 XSPI_CCR_ABMODE_2 /*!< 0x00040000 */
+#define OCTOSPI_CCR_ABDTR_Pos XSPI_CCR_ABDTR_Pos
+#define OCTOSPI_CCR_ABDTR_Msk XSPI_CCR_ABDTR_Msk /*!< 0x00080000 */
+#define OCTOSPI_CCR_ABDTR XSPI_CCR_ABDTR /*!< Alternate Bytes Double Transfer Rate */
+#define OCTOSPI_CCR_ABSIZE_Pos XSPI_CCR_ABSIZE_Pos
+#define OCTOSPI_CCR_ABSIZE_Msk XSPI_CCR_ABSIZE_Msk /*!< 0x00300000 */
+#define OCTOSPI_CCR_ABSIZE XSPI_CCR_ABSIZE /*!< Alternate Bytes Size */
+#define OCTOSPI_CCR_ABSIZE_0 XSPI_CCR_ABSIZE_0 /*!< 0x00100000 */
+#define OCTOSPI_CCR_ABSIZE_1 XSPI_CCR_ABSIZE_1 /*!< 0x00200000 */
+#define OCTOSPI_CCR_DMODE_Pos XSPI_CCR_DMODE_Pos
+#define OCTOSPI_CCR_DMODE_Msk XSPI_CCR_DMODE_Msk /*!< 0x07000000 */
+#define OCTOSPI_CCR_DMODE XSPI_CCR_DMODE /*!< Data Mode */
+#define OCTOSPI_CCR_DMODE_0 XSPI_CCR_DMODE_0 /*!< 0x01000000 */
+#define OCTOSPI_CCR_DMODE_1 XSPI_CCR_DMODE_1 /*!< 0x02000000 */
+#define OCTOSPI_CCR_DMODE_2 XSPI_CCR_DMODE_2 /*!< 0x04000000 */
+#define OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
+#define OCTOSPI_CCR_DDTR_Msk XSPI_CCR_DDTR_Msk /*!< 0x08000000 */
+#define OCTOSPI_CCR_DDTR XSPI_CCR_DDTR /*!< Data Double Transfer Rate */
+#define OCTOSPI_CCR_DQSE_Pos XSPI_CCR_DQSE_Pos
+#define OCTOSPI_CCR_DQSE_Msk XSPI_CCR_DQSE_Msk /*!< 0x20000000 */
+#define OCTOSPI_CCR_DQSE XSPI_CCR_DQSE /*!< DQS Enable */
+#define OCTOSPI_CCR_SIOO_Pos XSPI_CCR_SIOO_Pos
+#define OCTOSPI_CCR_SIOO_Msk XSPI_CCR_SIOO_Msk /*!< 0x80000000 */
+#define OCTOSPI_CCR_SIOO XSPI_CCR_SIOO /*!< Send Instruction Only Once Mode */
/**************** Bit definition for OCTOSPI_TCR register *******************/
-#define OCTOSPI_TCR_DCYC_Pos (0U)
-#define OCTOSPI_TCR_DCYC_Msk (0x1FUL << OCTOSPI_TCR_DCYC_Pos) /*!< 0x0000001F */
-#define OCTOSPI_TCR_DCYC OCTOSPI_TCR_DCYC_Msk /*!< Number of Dummy Cycles */
-#define OCTOSPI_TCR_DHQC_Pos (28U)
-#define OCTOSPI_TCR_DHQC_Msk (0x1UL << OCTOSPI_TCR_DHQC_Pos) /*!< 0x10000000 */
-#define OCTOSPI_TCR_DHQC OCTOSPI_TCR_DHQC_Msk /*!< Delay Hold Quarter Cycle */
-#define OCTOSPI_TCR_SSHIFT_Pos (30U)
-#define OCTOSPI_TCR_SSHIFT_Msk (0x1UL << OCTOSPI_TCR_SSHIFT_Pos) /*!< 0x40000000 */
-#define OCTOSPI_TCR_SSHIFT OCTOSPI_TCR_SSHIFT_Msk /*!< Sample Shift */
+#define OCTOSPI_TCR_DCYC_Pos XSPI_TCR_DCYC_Pos
+#define OCTOSPI_TCR_DCYC_Msk XSPI_TCR_DCYC_Msk /*!< 0x0000001F */
+#define OCTOSPI_TCR_DCYC XSPI_TCR_DCYC /*!< Number of Dummy Cycles */
+#define OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
+#define OCTOSPI_TCR_DHQC_Msk XSPI_TCR_DHQC_Msk /*!< 0x10000000 */
+#define OCTOSPI_TCR_DHQC XSPI_TCR_DHQC /*!< Delay Hold Quarter Cycle */
+#define OCTOSPI_TCR_SSHIFT_Pos XSPI_TCR_SSHIFT_Pos
+#define OCTOSPI_TCR_SSHIFT_Msk XSPI_TCR_SSHIFT_Msk /*!< 0x40000000 */
+#define OCTOSPI_TCR_SSHIFT XSPI_TCR_SSHIFT /*!< Sample Shift */
/***************** Bit definition for OCTOSPI_IR register *******************/
-#define OCTOSPI_IR_INSTRUCTION_Pos (0U)
-#define OCTOSPI_IR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
-#define OCTOSPI_IR_INSTRUCTION OCTOSPI_IR_INSTRUCTION_Msk /*!< Instruction */
+#define OCTOSPI_IR_INSTRUCTION_Pos XSPI_IR_INSTRUCTION_Pos
+#define OCTOSPI_IR_INSTRUCTION_Msk XSPI_IR_INSTRUCTION_Msk /*!< 0xFFFFFFFF */
+#define OCTOSPI_IR_INSTRUCTION XSPI_IR_INSTRUCTION /*!< Instruction */
/**************** Bit definition for OCTOSPI_ABR register *******************/
-#define OCTOSPI_ABR_ALTERNATE_Pos (0U)
-#define OCTOSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
-#define OCTOSPI_ABR_ALTERNATE OCTOSPI_ABR_ALTERNATE_Msk /*!< Alternate Bytes */
+#define OCTOSPI_ABR_ALTERNATE_Pos XSPI_ABR_ALTERNATE_Pos
+#define OCTOSPI_ABR_ALTERNATE_Msk XSPI_ABR_ALTERNATE_Msk /*!< 0xFFFFFFFF */
+#define OCTOSPI_ABR_ALTERNATE XSPI_ABR_ALTERNATE /*!< Alternate Bytes */
/**************** Bit definition for OCTOSPI_LPTR register ******************/
-#define OCTOSPI_LPTR_TIMEOUT_Pos (0U)
-#define OCTOSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << OCTOSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
-#define OCTOSPI_LPTR_TIMEOUT OCTOSPI_LPTR_TIMEOUT_Msk /*!< Timeout period */
+#define OCTOSPI_LPTR_TIMEOUT_Pos XSPI_LPTR_TIMEOUT_Pos
+#define OCTOSPI_LPTR_TIMEOUT_Msk XSPI_LPTR_TIMEOUT_Msk /*!< 0x0000FFFF */
+#define OCTOSPI_LPTR_TIMEOUT XSPI_LPTR_TIMEOUT /*!< Timeout period */
/**************** Bit definition for OCTOSPI_WPCCR register *******************/
-#define OCTOSPI_WPCCR_IMODE_Pos (0U)
-#define OCTOSPI_WPCCR_IMODE_Msk (0x7UL << OCTOSPI_WPCCR_IMODE_Pos) /*!< 0x00000007 */
-#define OCTOSPI_WPCCR_IMODE OCTOSPI_WPCCR_IMODE_Msk /*!< Instruction Mode */
-#define OCTOSPI_WPCCR_IMODE_0 (0x1UL << OCTOSPI_WPCCR_IMODE_Pos) /*!< 0x00000001 */
-#define OCTOSPI_WPCCR_IMODE_1 (0x2UL << OCTOSPI_WPCCR_IMODE_Pos) /*!< 0x00000002 */
-#define OCTOSPI_WPCCR_IMODE_2 (0x4UL << OCTOSPI_WPCCR_IMODE_Pos) /*!< 0x00000004 */
-#define OCTOSPI_WPCCR_IDTR_Pos (3U)
-#define OCTOSPI_WPCCR_IDTR_Msk (0x1UL << OCTOSPI_WPCCR_IDTR_Pos) /*!< 0x00000008 */
-#define OCTOSPI_WPCCR_IDTR OCTOSPI_WPCCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
-#define OCTOSPI_WPCCR_ISIZE_Pos (4U)
-#define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
-#define OCTOSPI_WPCCR_ISIZE OCTOSPI_WPCCR_ISIZE_Msk /*!< Instruction Size */
-#define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
-#define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
-#define OCTOSPI_WPCCR_ADMODE_Pos (8U)
-#define OCTOSPI_WPCCR_ADMODE_Msk (0x7UL << OCTOSPI_WPCCR_ADMODE_Pos) /*!< 0x00000700 */
-#define OCTOSPI_WPCCR_ADMODE OCTOSPI_WPCCR_ADMODE_Msk /*!< Address Mode */
-#define OCTOSPI_WPCCR_ADMODE_0 (0x1UL << OCTOSPI_WPCCR_ADMODE_Pos) /*!< 0x00000100 */
-#define OCTOSPI_WPCCR_ADMODE_1 (0x2UL << OCTOSPI_WPCCR_ADMODE_Pos) /*!< 0x00000200 */
-#define OCTOSPI_WPCCR_ADMODE_2 (0x4UL << OCTOSPI_WPCCR_ADMODE_Pos) /*!< 0x00000400 */
-#define OCTOSPI_WPCCR_ADDTR_Pos (11U)
-#define OCTOSPI_WPCCR_ADDTR_Msk (0x1UL << OCTOSPI_WPCCR_ADDTR_Pos) /*!< 0x00000800 */
-#define OCTOSPI_WPCCR_ADDTR OCTOSPI_WPCCR_ADDTR_Msk /*!< Address Double Transfer Rate */
-#define OCTOSPI_WPCCR_ADSIZE_Pos (12U)
-#define OCTOSPI_WPCCR_ADSIZE_Msk (0x3UL << OCTOSPI_WPCCR_ADSIZE_Pos) /*!< 0x00003000 */
-#define OCTOSPI_WPCCR_ADSIZE OCTOSPI_WPCCR_ADSIZE_Msk /*!< Address Size */
-#define OCTOSPI_WPCCR_ADSIZE_0 (0x1UL << OCTOSPI_WPCCR_ADSIZE_Pos) /*!< 0x00001000 */
-#define OCTOSPI_WPCCR_ADSIZE_1 (0x2UL << OCTOSPI_WPCCR_ADSIZE_Pos) /*!< 0x00002000 */
-#define OCTOSPI_WPCCR_ABMODE_Pos (16U)
-#define OCTOSPI_WPCCR_ABMODE_Msk (0x7UL << OCTOSPI_WPCCR_ABMODE_Pos) /*!< 0x00070000 */
-#define OCTOSPI_WPCCR_ABMODE OCTOSPI_WPCCR_ABMODE_Msk /*!< Alternate Bytes Mode */
-#define OCTOSPI_WPCCR_ABMODE_0 (0x1UL << OCTOSPI_WPCCR_ABMODE_Pos) /*!< 0x00010000 */
-#define OCTOSPI_WPCCR_ABMODE_1 (0x2UL << OCTOSPI_WPCCR_ABMODE_Pos) /*!< 0x00020000 */
-#define OCTOSPI_WPCCR_ABMODE_2 (0x4UL << OCTOSPI_WPCCR_ABMODE_Pos) /*!< 0x00040000 */
-#define OCTOSPI_WPCCR_ABDTR_Pos (19U)
-#define OCTOSPI_WPCCR_ABDTR_Msk (0x1UL << OCTOSPI_WPCCR_ABDTR_Pos) /*!< 0x00080000 */
-#define OCTOSPI_WPCCR_ABDTR OCTOSPI_WPCCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
-#define OCTOSPI_WPCCR_ABSIZE_Pos (20U)
-#define OCTOSPI_WPCCR_ABSIZE_Msk (0x3UL << OCTOSPI_WPCCR_ABSIZE_Pos) /*!< 0x00300000 */
-#define OCTOSPI_WPCCR_ABSIZE OCTOSPI_WPCCR_ABSIZE_Msk /*!< Alternate Bytes Size */
-#define OCTOSPI_WPCCR_ABSIZE_0 (0x1UL << OCTOSPI_WPCCR_ABSIZE_Pos) /*!< 0x00100000 */
-#define OCTOSPI_WPCCR_ABSIZE_1 (0x2UL << OCTOSPI_WPCCR_ABSIZE_Pos) /*!< 0x00200000 */
-#define OCTOSPI_WPCCR_DMODE_Pos (24U)
-#define OCTOSPI_WPCCR_DMODE_Msk (0x7UL << OCTOSPI_WPCCR_DMODE_Pos) /*!< 0x07000000 */
-#define OCTOSPI_WPCCR_DMODE OCTOSPI_WPCCR_DMODE_Msk /*!< Data Mode */
-#define OCTOSPI_WPCCR_DMODE_0 (0x1UL << OCTOSPI_WPCCR_DMODE_Pos) /*!< 0x01000000 */
-#define OCTOSPI_WPCCR_DMODE_1 (0x2UL << OCTOSPI_WPCCR_DMODE_Pos) /*!< 0x02000000 */
-#define OCTOSPI_WPCCR_DMODE_2 (0x4UL << OCTOSPI_WPCCR_DMODE_Pos) /*!< 0x04000000 */
-#define OCTOSPI_WPCCR_DDTR_Pos (27U)
-#define OCTOSPI_WPCCR_DDTR_Msk (0x1UL << OCTOSPI_WPCCR_DDTR_Pos) /*!< 0x08000000 */
-#define OCTOSPI_WPCCR_DDTR OCTOSPI_WPCCR_DDTR_Msk /*!< Data Double Transfer Rate */
-#define OCTOSPI_WPCCR_DQSE_Pos (29U)
-#define OCTOSPI_WPCCR_DQSE_Msk (0x1UL << OCTOSPI_WPCCR_DQSE_Pos) /*!< 0x20000000 */
-#define OCTOSPI_WPCCR_DQSE OCTOSPI_WPCCR_DQSE_Msk /*!< DQS Enable */
+#define OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
+#define OCTOSPI_WPCCR_IMODE_Msk XSPI_WPCCR_IMODE_Msk /*!< 0x00000007 */
+#define OCTOSPI_WPCCR_IMODE XSPI_WPCCR_IMODE /*!< Instruction Mode */
+#define OCTOSPI_WPCCR_IMODE_0 XSPI_WPCCR_IMODE_0 /*!< 0x00000001 */
+#define OCTOSPI_WPCCR_IMODE_1 XSPI_WPCCR_IMODE_1 /*!< 0x00000002 */
+#define OCTOSPI_WPCCR_IMODE_2 XSPI_WPCCR_IMODE_2 /*!< 0x00000004 */
+#define OCTOSPI_WPCCR_IDTR_Pos XSPI_WPCCR_IDTR_Pos
+#define OCTOSPI_WPCCR_IDTR_Msk XSPI_WPCCR_IDTR_Msk /*!< 0x00000008 */
+#define OCTOSPI_WPCCR_IDTR XSPI_WPCCR_IDTR /*!< Instruction Double Transfer Rate */
+#define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
+#define OCTOSPI_WPCCR_ISIZE_Msk XSPI_WPCCR_ISIZE_Msk /*!< 0x00000030 */
+#define OCTOSPI_WPCCR_ISIZE XSPI_WPCCR_ISIZE /*!< Instruction Size */
+#define OCTOSPI_WPCCR_ISIZE_0 XSPI_WPCCR_ISIZE_0 /*!< 0x00000010 */
+#define OCTOSPI_WPCCR_ISIZE_1 XSPI_WPCCR_ISIZE_1 /*!< 0x00000020 */
+#define OCTOSPI_WPCCR_ADMODE_Pos XSPI_WPCCR_ADMODE_Pos
+#define OCTOSPI_WPCCR_ADMODE_Msk XSPI_WPCCR_ADMODE_Msk /*!< 0x00000700 */
+#define OCTOSPI_WPCCR_ADMODE XSPI_WPCCR_ADMODE /*!< Address Mode */
+#define OCTOSPI_WPCCR_ADMODE_0 XSPI_WPCCR_ADMODE_0 /*!< 0x00000100 */
+#define OCTOSPI_WPCCR_ADMODE_1 XSPI_WPCCR_ADMODE_1 /*!< 0x00000200 */
+#define OCTOSPI_WPCCR_ADMODE_2 XSPI_WPCCR_ADMODE_2 /*!< 0x00000400 */
+#define OCTOSPI_WPCCR_ADDTR_Pos XSPI_WPCCR_ADDTR_Pos
+#define OCTOSPI_WPCCR_ADDTR_Msk XSPI_WPCCR_ADDTR_Msk /*!< 0x00000800 */
+#define OCTOSPI_WPCCR_ADDTR XSPI_WPCCR_ADDTR /*!< Address Double Transfer Rate */
+#define OCTOSPI_WPCCR_ADSIZE_Pos XSPI_WPCCR_ADSIZE_Pos
+#define OCTOSPI_WPCCR_ADSIZE_Msk XSPI_WPCCR_ADSIZE_Msk /*!< 0x00003000 */
+#define OCTOSPI_WPCCR_ADSIZE XSPI_WPCCR_ADSIZE /*!< Address Size */
+#define OCTOSPI_WPCCR_ADSIZE_0 XSPI_WPCCR_ADSIZE_0 /*!< 0x00001000 */
+#define OCTOSPI_WPCCR_ADSIZE_1 XSPI_WPCCR_ADSIZE_1 /*!< 0x00002000 */
+#define OCTOSPI_WPCCR_ABMODE_Pos XSPI_WPCCR_ABMODE_Pos
+#define OCTOSPI_WPCCR_ABMODE_Msk XSPI_WPCCR_ABMODE_Msk /*!< 0x00070000 */
+#define OCTOSPI_WPCCR_ABMODE XSPI_WPCCR_ABMODE /*!< Alternate Bytes Mode */
+#define OCTOSPI_WPCCR_ABMODE_0 XSPI_WPCCR_ABMODE_0 /*!< 0x00010000 */
+#define OCTOSPI_WPCCR_ABMODE_1 XSPI_WPCCR_ABMODE_1 /*!< 0x00020000 */
+#define OCTOSPI_WPCCR_ABMODE_2 XSPI_WPCCR_ABMODE_2 /*!< 0x00040000 */
+#define OCTOSPI_WPCCR_ABDTR_Pos XSPI_WPCCR_ABDTR_Pos
+#define OCTOSPI_WPCCR_ABDTR_Msk XSPI_WPCCR_ABDTR_Msk /*!< 0x00080000 */
+#define OCTOSPI_WPCCR_ABDTR XSPI_WPCCR_ABDTR /*!< Alternate Bytes Double Transfer Rate */
+#define OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
+#define OCTOSPI_WPCCR_ABSIZE_Msk XSPI_WPCCR_ABSIZE_Msk /*!< 0x00300000 */
+#define OCTOSPI_WPCCR_ABSIZE XSPI_WPCCR_ABSIZE /*!< Alternate Bytes Size */
+#define OCTOSPI_WPCCR_ABSIZE_0 XSPI_WPCCR_ABSIZE_0 /*!< 0x00100000 */
+#define OCTOSPI_WPCCR_ABSIZE_1 XSPI_WPCCR_ABSIZE_1 /*!< 0x00200000 */
+#define OCTOSPI_WPCCR_DMODE_Pos XSPI_WPCCR_DMODE_Pos
+#define OCTOSPI_WPCCR_DMODE_Msk XSPI_WPCCR_DMODE_Msk /*!< 0x07000000 */
+#define OCTOSPI_WPCCR_DMODE XSPI_WPCCR_DMODE /*!< Data Mode */
+#define OCTOSPI_WPCCR_DMODE_0 XSPI_WPCCR_DMODE_0 /*!< 0x01000000 */
+#define OCTOSPI_WPCCR_DMODE_1 XSPI_WPCCR_DMODE_1 /*!< 0x02000000 */
+#define OCTOSPI_WPCCR_DMODE_2 XSPI_WPCCR_DMODE_2 /*!< 0x04000000 */
+#define OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
+#define OCTOSPI_WPCCR_DDTR_Msk XSPI_WPCCR_DDTR_Msk /*!< 0x08000000 */
+#define OCTOSPI_WPCCR_DDTR XSPI_WPCCR_DDTR /*!< Data Double Transfer Rate */
+#define OCTOSPI_WPCCR_DQSE_Pos XSPI_WPCCR_DQSE_Pos
+#define OCTOSPI_WPCCR_DQSE_Msk XSPI_WPCCR_DQSE_Msk /*!< 0x20000000 */
+#define OCTOSPI_WPCCR_DQSE XSPI_WPCCR_DQSE /*!< DQS Enable */
/**************** Bit definition for OCTOSPI_WPTCR register *******************/
-#define OCTOSPI_WPTCR_DCYC_Pos (0U)
-#define OCTOSPI_WPTCR_DCYC_Msk (0x1FUL << OCTOSPI_WPTCR_DCYC_Pos) /*!< 0x0000001F */
-#define OCTOSPI_WPTCR_DCYC OCTOSPI_WPTCR_DCYC_Msk /*!< Number of Dummy Cycles */
-#define OCTOSPI_WPTCR_DHQC_Pos (28U)
-#define OCTOSPI_WPTCR_DHQC_Msk (0x1UL << OCTOSPI_WPTCR_DHQC_Pos) /*!< 0x10000000 */
-#define OCTOSPI_WPTCR_DHQC OCTOSPI_WPTCR_DHQC_Msk /*!< Delay Hold Quarter Cycle */
-#define OCTOSPI_WPTCR_SSHIFT_Pos (30U)
-#define OCTOSPI_WPTCR_SSHIFT_Msk (0x1UL << OCTOSPI_WPTCR_SSHIFT_Pos) /*!< 0x40000000 */
-#define OCTOSPI_WPTCR_SSHIFT OCTOSPI_WPTCR_SSHIFT_Msk /*!< Sample Shift */
+#define OCTOSPI_WPTCR_DCYC_Pos XSPI_WPTCR_DCYC_Pos
+#define OCTOSPI_WPTCR_DCYC_Msk XSPI_WPTCR_DCYC_Msk /*!< 0x0000001F */
+#define OCTOSPI_WPTCR_DCYC XSPI_WPTCR_DCYC /*!< Number of Dummy Cycles */
+#define OCTOSPI_WPTCR_DHQC_Pos XSPI_WPTCR_DHQC_Pos
+#define OCTOSPI_WPTCR_DHQC_Msk XSPI_WPTCR_DHQC_Msk /*!< 0x10000000 */
+#define OCTOSPI_WPTCR_DHQC XSPI_WPTCR_DHQC /*!< Delay Hold Quarter Cycle */
+#define OCTOSPI_WPTCR_SSHIFT_Pos XSPI_WPTCR_SSHIFT_Pos
+#define OCTOSPI_WPTCR_SSHIFT_Msk XSPI_WPTCR_SSHIFT_Msk /*!< 0x40000000 */
+#define OCTOSPI_WPTCR_SSHIFT XSPI_WPTCR_SSHIFT /*!< Sample Shift */
/***************** Bit definition for OCTOSPI_WPIR register *******************/
-#define OCTOSPI_WPIR_INSTRUCTION_Pos (0U)
-#define OCTOSPI_WPIR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
-#define OCTOSPI_WPIR_INSTRUCTION OCTOSPI_WPIR_INSTRUCTION_Msk /*!< Instruction */
+#define OCTOSPI_WPIR_INSTRUCTION_Pos XSPI_WPIR_INSTRUCTION_Pos
+#define OCTOSPI_WPIR_INSTRUCTION_Msk XSPI_WPIR_INSTRUCTION_Msk /*!< 0xFFFFFFFF */
+#define OCTOSPI_WPIR_INSTRUCTION XSPI_WPIR_INSTRUCTION /*!< Instruction */
/**************** Bit definition for OCTOSPI_WPABR register *******************/
-#define OCTOSPI_WPABR_ALTERNATE_Pos (0U)
-#define OCTOSPI_WPABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
-#define OCTOSPI_WPABR_ALTERNATE OCTOSPI_WPABR_ALTERNATE_Msk /*!< Alternate Bytes */
+#define OCTOSPI_WPABR_ALTERNATE_Pos XSPI_WPABR_ALTERNATE_Pos
+#define OCTOSPI_WPABR_ALTERNATE_Msk XSPI_WPABR_ALTERNATE_Msk /*!< 0xFFFFFFFF */
+#define OCTOSPI_WPABR_ALTERNATE XSPI_WPABR_ALTERNATE /*!< Alternate Bytes */
/**************** Bit definition for OCTOSPI_WCCR register ******************/
-#define OCTOSPI_WCCR_IMODE_Pos (0U)
-#define OCTOSPI_WCCR_IMODE_Msk (0x7UL << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000007 */
-#define OCTOSPI_WCCR_IMODE OCTOSPI_WCCR_IMODE_Msk /*!< Instruction Mode */
-#define OCTOSPI_WCCR_IMODE_0 (0x1UL << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000001 */
-#define OCTOSPI_WCCR_IMODE_1 (0x2UL << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000002 */
-#define OCTOSPI_WCCR_IMODE_2 (0x4UL << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000004 */
-#define OCTOSPI_WCCR_IDTR_Pos (3U)
-#define OCTOSPI_WCCR_IDTR_Msk (0x1UL << OCTOSPI_WCCR_IDTR_Pos) /*!< 0x00000008 */
-#define OCTOSPI_WCCR_IDTR OCTOSPI_WCCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
-#define OCTOSPI_WCCR_ISIZE_Pos (4U)
-#define OCTOSPI_WCCR_ISIZE_Msk (0x3UL << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000030 */
-#define OCTOSPI_WCCR_ISIZE OCTOSPI_WCCR_ISIZE_Msk /*!< Instruction Size */
-#define OCTOSPI_WCCR_ISIZE_0 (0x1UL << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000010 */
-#define OCTOSPI_WCCR_ISIZE_1 (0x2UL << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000020 */
-#define OCTOSPI_WCCR_ADMODE_Pos (8U)
-#define OCTOSPI_WCCR_ADMODE_Msk (0x7UL << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000700 */
-#define OCTOSPI_WCCR_ADMODE OCTOSPI_WCCR_ADMODE_Msk /*!< Address Mode */
-#define OCTOSPI_WCCR_ADMODE_0 (0x1UL << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000100 */
-#define OCTOSPI_WCCR_ADMODE_1 (0x2UL << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000200 */
-#define OCTOSPI_WCCR_ADMODE_2 (0x4UL << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000400 */
-#define OCTOSPI_WCCR_ADDTR_Pos (11U)
-#define OCTOSPI_WCCR_ADDTR_Msk (0x1UL << OCTOSPI_WCCR_ADDTR_Pos) /*!< 0x00000800 */
-#define OCTOSPI_WCCR_ADDTR OCTOSPI_WCCR_ADDTR_Msk /*!< Address Double Transfer Rate */
-#define OCTOSPI_WCCR_ADSIZE_Pos (12U)
-#define OCTOSPI_WCCR_ADSIZE_Msk (0x3UL << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00003000 */
-#define OCTOSPI_WCCR_ADSIZE OCTOSPI_WCCR_ADSIZE_Msk /*!< Address Size */
-#define OCTOSPI_WCCR_ADSIZE_0 (0x1UL << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00001000 */
-#define OCTOSPI_WCCR_ADSIZE_1 (0x2UL << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00002000 */
-#define OCTOSPI_WCCR_ABMODE_Pos (16U)
-#define OCTOSPI_WCCR_ABMODE_Msk (0x7UL << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00070000 */
-#define OCTOSPI_WCCR_ABMODE OCTOSPI_WCCR_ABMODE_Msk /*!< Alternate Bytes Mode */
-#define OCTOSPI_WCCR_ABMODE_0 (0x1UL << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00010000 */
-#define OCTOSPI_WCCR_ABMODE_1 (0x2UL << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00020000 */
-#define OCTOSPI_WCCR_ABMODE_2 (0x4UL << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00040000 */
-#define OCTOSPI_WCCR_ABDTR_Pos (19U)
-#define OCTOSPI_WCCR_ABDTR_Msk (0x1UL << OCTOSPI_WCCR_ABDTR_Pos) /*!< 0x00080000 */
-#define OCTOSPI_WCCR_ABDTR OCTOSPI_WCCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
-#define OCTOSPI_WCCR_ABSIZE_Pos (20U)
-#define OCTOSPI_WCCR_ABSIZE_Msk (0x3UL << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00300000 */
-#define OCTOSPI_WCCR_ABSIZE OCTOSPI_WCCR_ABSIZE_Msk /*!< Alternate Bytes Size */
-#define OCTOSPI_WCCR_ABSIZE_0 (0x1UL << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00100000 */
-#define OCTOSPI_WCCR_ABSIZE_1 (0x2UL << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00200000 */
-#define OCTOSPI_WCCR_DMODE_Pos (24U)
-#define OCTOSPI_WCCR_DMODE_Msk (0x7UL << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x07000000 */
-#define OCTOSPI_WCCR_DMODE OCTOSPI_WCCR_DMODE_Msk /*!< Data Mode */
-#define OCTOSPI_WCCR_DMODE_0 (0x1UL << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x01000000 */
-#define OCTOSPI_WCCR_DMODE_1 (0x2UL << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x02000000 */
-#define OCTOSPI_WCCR_DMODE_2 (0x4UL << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x04000000 */
-#define OCTOSPI_WCCR_DDTR_Pos (27U)
-#define OCTOSPI_WCCR_DDTR_Msk (0x1UL << OCTOSPI_WCCR_DDTR_Pos) /*!< 0x08000000 */
-#define OCTOSPI_WCCR_DDTR OCTOSPI_WCCR_DDTR_Msk /*!< Data Double Transfer Rate */
-#define OCTOSPI_WCCR_DQSE_Pos (29U)
-#define OCTOSPI_WCCR_DQSE_Msk (0x1UL << OCTOSPI_WCCR_DQSE_Pos) /*!< 0x20000000 */
-#define OCTOSPI_WCCR_DQSE OCTOSPI_WCCR_DQSE_Msk /*!< DQS Enable */
+#define OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
+#define OCTOSPI_WCCR_IMODE_Msk XSPI_WCCR_IMODE_Msk /*!< 0x00000007 */
+#define OCTOSPI_WCCR_IMODE XSPI_WCCR_IMODE /*!< Instruction Mode */
+#define OCTOSPI_WCCR_IMODE_0 XSPI_WCCR_IMODE_0 /*!< 0x00000001 */
+#define OCTOSPI_WCCR_IMODE_1 XSPI_WCCR_IMODE_1 /*!< 0x00000002 */
+#define OCTOSPI_WCCR_IMODE_2 XSPI_WCCR_IMODE_2 /*!< 0x00000004 */
+#define OCTOSPI_WCCR_IDTR_Pos XSPI_WCCR_IDTR_Pos
+#define OCTOSPI_WCCR_IDTR_Msk XSPI_WCCR_IDTR_Msk /*!< 0x00000008 */
+#define OCTOSPI_WCCR_IDTR XSPI_WCCR_IDTR /*!< Instruction Double Transfer Rate */
+#define OCTOSPI_WCCR_ISIZE_Pos XSPI_WCCR_ISIZE_Pos
+#define OCTOSPI_WCCR_ISIZE_Msk XSPI_WCCR_ISIZE_Msk /*!< 0x00000030 */
+#define OCTOSPI_WCCR_ISIZE XSPI_WCCR_ISIZE /*!< Instruction Size */
+#define OCTOSPI_WCCR_ISIZE_0 XSPI_WCCR_ISIZE_0 /*!< 0x00000010 */
+#define OCTOSPI_WCCR_ISIZE_1 XSPI_WCCR_ISIZE_1 /*!< 0x00000020 */
+#define OCTOSPI_WCCR_ADMODE_Pos XSPI_WCCR_ADMODE_Pos
+#define OCTOSPI_WCCR_ADMODE_Msk XSPI_WCCR_ADMODE_Msk /*!< 0x00000700 */
+#define OCTOSPI_WCCR_ADMODE XSPI_WCCR_ADMODE /*!< Address Mode */
+#define OCTOSPI_WCCR_ADMODE_0 XSPI_WCCR_ADMODE_0 /*!< 0x00000100 */
+#define OCTOSPI_WCCR_ADMODE_1 XSPI_WCCR_ADMODE_1 /*!< 0x00000200 */
+#define OCTOSPI_WCCR_ADMODE_2 XSPI_WCCR_ADMODE_2 /*!< 0x00000400 */
+#define OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
+#define OCTOSPI_WCCR_ADDTR_Msk XSPI_WCCR_ADDTR_Msk /*!< 0x00000800 */
+#define OCTOSPI_WCCR_ADDTR XSPI_WCCR_ADDTR /*!< Address Double Transfer Rate */
+#define OCTOSPI_WCCR_ADSIZE_Pos XSPI_WCCR_ADSIZE_Pos
+#define OCTOSPI_WCCR_ADSIZE_Msk XSPI_WCCR_ADSIZE_Msk /*!< 0x00003000 */
+#define OCTOSPI_WCCR_ADSIZE XSPI_WCCR_ADSIZE /*!< Address Size */
+#define OCTOSPI_WCCR_ADSIZE_0 XSPI_WCCR_ADSIZE_0 /*!< 0x00001000 */
+#define OCTOSPI_WCCR_ADSIZE_1 XSPI_WCCR_ADSIZE_1 /*!< 0x00002000 */
+#define OCTOSPI_WCCR_ABMODE_Pos XSPI_WCCR_ABMODE_Pos
+#define OCTOSPI_WCCR_ABMODE_Msk XSPI_WCCR_ABMODE_Msk /*!< 0x00070000 */
+#define OCTOSPI_WCCR_ABMODE XSPI_WCCR_ABMODE /*!< Alternate Bytes Mode */
+#define OCTOSPI_WCCR_ABMODE_0 XSPI_WCCR_ABMODE_0 /*!< 0x00010000 */
+#define OCTOSPI_WCCR_ABMODE_1 XSPI_WCCR_ABMODE_1 /*!< 0x00020000 */
+#define OCTOSPI_WCCR_ABMODE_2 XSPI_WCCR_ABMODE_2 /*!< 0x00040000 */
+#define OCTOSPI_WCCR_ABDTR_Pos XSPI_WCCR_ABDTR_Pos
+#define OCTOSPI_WCCR_ABDTR_Msk XSPI_WCCR_ABDTR_Msk /*!< 0x00080000 */
+#define OCTOSPI_WCCR_ABDTR XSPI_WCCR_ABDTR /*!< Alternate Bytes Double Transfer Rate */
+#define OCTOSPI_WCCR_ABSIZE_Pos XSPI_WCCR_ABSIZE_Pos
+#define OCTOSPI_WCCR_ABSIZE_Msk XSPI_WCCR_ABSIZE_Msk /*!< 0x00300000 */
+#define OCTOSPI_WCCR_ABSIZE XSPI_WCCR_ABSIZE /*!< Alternate Bytes Size */
+#define OCTOSPI_WCCR_ABSIZE_0 XSPI_WCCR_ABSIZE_0 /*!< 0x00100000 */
+#define OCTOSPI_WCCR_ABSIZE_1 XSPI_WCCR_ABSIZE_1 /*!< 0x00200000 */
+#define OCTOSPI_WCCR_DMODE_Pos XSPI_WCCR_DMODE_Pos
+#define OCTOSPI_WCCR_DMODE_Msk XSPI_WCCR_DMODE_Msk /*!< 0x07000000 */
+#define OCTOSPI_WCCR_DMODE XSPI_WCCR_DMODE /*!< Data Mode */
+#define OCTOSPI_WCCR_DMODE_0 XSPI_WCCR_DMODE_0 /*!< 0x01000000 */
+#define OCTOSPI_WCCR_DMODE_1 XSPI_WCCR_DMODE_1 /*!< 0x02000000 */
+#define OCTOSPI_WCCR_DMODE_2 XSPI_WCCR_DMODE_2 /*!< 0x04000000 */
+#define OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
+#define OCTOSPI_WCCR_DDTR_Msk XSPI_WCCR_DDTR_Msk /*!< 0x08000000 */
+#define OCTOSPI_WCCR_DDTR XSPI_WCCR_DDTR /*!< Data Double Transfer Rate */
+#define OCTOSPI_WCCR_DQSE_Pos XSPI_WCCR_DQSE_Pos
+#define OCTOSPI_WCCR_DQSE_Msk XSPI_WCCR_DQSE_Msk /*!< 0x20000000 */
+#define OCTOSPI_WCCR_DQSE XSPI_WCCR_DQSE /*!< DQS Enable */
/**************** Bit definition for OCTOSPI_WTCR register ******************/
-#define OCTOSPI_WTCR_DCYC_Pos (0U)
-#define OCTOSPI_WTCR_DCYC_Msk (0x1FUL << OCTOSPI_WTCR_DCYC_Pos) /*!< 0x0000001F */
-#define OCTOSPI_WTCR_DCYC OCTOSPI_WTCR_DCYC_Msk /*!< Number of Dummy Cycles */
+#define OCTOSPI_WTCR_DCYC_Pos XSPI_WTCR_DCYC_Pos
+#define OCTOSPI_WTCR_DCYC_Msk XSPI_WTCR_DCYC_Msk /*!< 0x0000001F */
+#define OCTOSPI_WTCR_DCYC XSPI_WTCR_DCYC /*!< Number of Dummy Cycles */
/**************** Bit definition for OCTOSPI_WIR register *******************/
-#define OCTOSPI_WIR_INSTRUCTION_Pos (0U)
-#define OCTOSPI_WIR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
-#define OCTOSPI_WIR_INSTRUCTION OCTOSPI_WIR_INSTRUCTION_Msk /*!< Instruction */
+#define OCTOSPI_WIR_INSTRUCTION_Pos XSPI_WIR_INSTRUCTION_Pos
+#define OCTOSPI_WIR_INSTRUCTION_Msk XSPI_WIR_INSTRUCTION_Msk /*!< 0xFFFFFFFF */
+#define OCTOSPI_WIR_INSTRUCTION XSPI_WIR_INSTRUCTION /*!< Instruction */
/**************** Bit definition for OCTOSPI_WABR register ******************/
-#define OCTOSPI_WABR_ALTERNATE_Pos (0U)
-#define OCTOSPI_WABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
-#define OCTOSPI_WABR_ALTERNATE OCTOSPI_WABR_ALTERNATE_Msk /*!< Alternate Bytes */
+#define OCTOSPI_WABR_ALTERNATE_Pos XSPI_WABR_ALTERNATE_Pos
+#define OCTOSPI_WABR_ALTERNATE_Msk XSPI_WABR_ALTERNATE_Msk /*!< 0xFFFFFFFF */
+#define OCTOSPI_WABR_ALTERNATE XSPI_WABR_ALTERNATE /*!< Alternate Bytes */
/**************** Bit definition for OCTOSPI_HLCR register ******************/
-#define OCTOSPI_HLCR_LM_Pos (0U)
-#define OCTOSPI_HLCR_LM_Msk (0x1UL << OCTOSPI_HLCR_LM_Pos) /*!< 0x00000001 */
-#define OCTOSPI_HLCR_LM OCTOSPI_HLCR_LM_Msk /*!< Latency Mode */
-#define OCTOSPI_HLCR_WZL_Pos (1U)
-#define OCTOSPI_HLCR_WZL_Msk (0x1UL << OCTOSPI_HLCR_WZL_Pos) /*!< 0x00000002 */
-#define OCTOSPI_HLCR_WZL OCTOSPI_HLCR_WZL_Msk /*!< Write Zero Latency */
-#define OCTOSPI_HLCR_TACC_Pos (8U)
-#define OCTOSPI_HLCR_TACC_Msk (0xFFUL << OCTOSPI_HLCR_TACC_Pos) /*!< 0x0000FF00 */
-#define OCTOSPI_HLCR_TACC OCTOSPI_HLCR_TACC_Msk /*!< Access Time */
-#define OCTOSPI_HLCR_TRWR_Pos (16U)
-#define OCTOSPI_HLCR_TRWR_Msk (0xFFUL << OCTOSPI_HLCR_TRWR_Pos) /*!< 0x00FF0000 */
-#define OCTOSPI_HLCR_TRWR OCTOSPI_HLCR_TRWR_Msk /*!< Read Write Recovery Time */
+#define OCTOSPI_HLCR_LM_Pos XSPI_HLCR_LM_Pos
+#define OCTOSPI_HLCR_LM_Msk XSPI_HLCR_LM_Msk /*!< 0x00000001 */
+#define OCTOSPI_HLCR_LM XSPI_HLCR_LM /*!< Latency Mode */
+#define OCTOSPI_HLCR_WZL_Pos XSPI_HLCR_WZL_Pos
+#define OCTOSPI_HLCR_WZL_Msk XSPI_HLCR_WZL_Msk /*!< 0x00000002 */
+#define OCTOSPI_HLCR_WZL XSPI_HLCR_WZL /*!< Write Zero Latency */
+#define OCTOSPI_HLCR_TACC_Pos XSPI_HLCR_TACC_Pos
+#define OCTOSPI_HLCR_TACC_Msk XSPI_HLCR_TACC_Msk /*!< 0x0000FF00 */
+#define OCTOSPI_HLCR_TACC XSPI_HLCR_TACC /*!< Access Time */
+#define OCTOSPI_HLCR_TRWR_Pos XSPI_HLCR_TRWR_Pos
+#define OCTOSPI_HLCR_TRWR_Msk XSPI_HLCR_TRWR_Msk /*!< 0x00FF0000 */
+#define OCTOSPI_HLCR_TRWR XSPI_HLCR_TRWR /*!< Read Write Recovery Time */
+
+/******************************************************************************/
+/* */
+/* XSPIM (OCTOSPIM) */
+/* */
+/******************************************************************************/
+/*************** Bit definition for XSPIM_CR register ********************/
+#define XSPIM_CR_MUXEN_Pos (0U)
+#define XSPIM_CR_MUXEN_Msk (0x1UL << XSPIM_CR_MUXEN_Pos) /*!< 0x00000001 */
+#define XSPIM_CR_MUXEN XSPIM_CR_MUXEN_Msk /*!< Multiplexed Mode Enable */
+#define XSPIM_CR_REQ2ACK_TIME_Pos (16U)
+#define XSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << XSPIM_CR_REQ2ACK_TIME_Pos) /*!< 0x00FF0000 */
+#define XSPIM_CR_REQ2ACK_TIME XSPIM_CR_REQ2ACK_TIME_Msk /*!< REQ to ACK Time */
+
+/*************** Bit definition for XSPIM_PCR register *****************/
+#define XSPIM_PCR_CLKEN_Pos (0U)
+#define XSPIM_PCR_CLKEN_Msk (0x1UL << XSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */
+#define XSPIM_PCR_CLKEN XSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */
+#define XSPIM_PCR_CLKSRC_Pos (1U)
+#define XSPIM_PCR_CLKSRC_Msk (0x1UL << XSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */
+#define XSPIM_PCR_CLKSRC XSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n*/
+#define XSPIM_PCR_DQSEN_Pos (4U)
+#define XSPIM_PCR_DQSEN_Msk (0x1UL << XSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */
+#define XSPIM_PCR_DQSEN XSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */
+#define XSPIM_PCR_DQSSRC_Pos (5U)
+#define XSPIM_PCR_DQSSRC_Msk (0x1UL << XSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */
+#define XSPIM_PCR_DQSSRC XSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */
+#define XSPIM_PCR_NCSEN_Pos (8U)
+#define XSPIM_PCR_NCSEN_Msk (0x1UL << XSPIM_PCR_NCSEN_Pos) /*!< 0x00000100U */
+#define XSPIM_PCR_NCSEN XSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n*/
+#define XSPIM_PCR_NCSSRC_Pos (9U)
+#define XSPIM_PCR_NCSSRC_Msk (0x1UL << XSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200U */
+#define XSPIM_PCR_NCSSRC XSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */
+#define XSPIM_PCR_IOLEN_Pos (16U)
+#define XSPIM_PCR_IOLEN_Msk (0x1UL << XSPIM_PCR_IOLEN_Pos) /*!< 0x00010000U */
+#define XSPIM_PCR_IOLEN XSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */
+#define XSPIM_PCR_IOLSRC_Pos (17U)
+#define XSPIM_PCR_IOLSRC_Msk (0x3UL << XSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000U */
+#define XSPIM_PCR_IOLSRC XSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */
+#define XSPIM_PCR_IOLSRC_0 (0x1UL << XSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */
+#define XSPIM_PCR_IOLSRC_1 (0x2UL << XSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */
+#define XSPIM_PCR_IOHEN_Pos (24U)
+#define XSPIM_PCR_IOHEN_Msk (0x1UL << XSPIM_PCR_IOHEN_Pos) /*!< 0x01000000U */
+#define XSPIM_PCR_IOHEN XSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */
+#define XSPIM_PCR_IOHSRC_Pos (25U)
+#define XSPIM_PCR_IOHSRC_Msk (0x3UL << XSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000U */
+#define XSPIM_PCR_IOHSRC XSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */
+#define XSPIM_PCR_IOHSRC_0 (0x1UL << XSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000U */
+#define XSPIM_PCR_IOHSRC_1 (0x2UL << XSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000U */
/******************************************************************************/
/* */
@@ -13348,48 +13844,48 @@
/* */
/******************************************************************************/
/*************** Bit definition for OCTOSPIM_CR register ********************/
-#define OCTOSPIM_CR_MUXEN_Pos (0U)
-#define OCTOSPIM_CR_MUXEN_Msk (0x1UL << OCTOSPIM_CR_MUXEN_Pos) /*!< 0x00000001 */
-#define OCTOSPIM_CR_MUXEN OCTOSPIM_CR_MUXEN_Msk /*!< Multiplexed Mode Enable */
-#define OCTOSPIM_CR_REQ2ACK_TIME_Pos (16U)
-#define OCTOSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos) /*!< 0x00FF0000 */
-#define OCTOSPIM_CR_REQ2ACK_TIME OCTOSPIM_CR_REQ2ACK_TIME_Msk /*!< REQ to ACK Time */
+#define OCTOSPIM_CR_MUXEN_Pos XSPIM_CR_MUXEN_Pos
+#define OCTOSPIM_CR_MUXEN_Msk XSPIM_CR_MUXEN_Msk /*!< 0x00000001 */
+#define OCTOSPIM_CR_MUXEN XSPIM_CR_MUXEN /*!< Multiplexed Mode Enable */
+#define OCTOSPIM_CR_REQ2ACK_TIME_Pos XSPIM_CR_REQ2ACK_TIME_Pos
+#define OCTOSPIM_CR_REQ2ACK_TIME_Msk XSPIM_CR_REQ2ACK_TIME_Msk /*!< 0x00FF0000 */
+#define OCTOSPIM_CR_REQ2ACK_TIME XSPIM_CR_REQ2ACK_TIME /*!< REQ to ACK Time */
/*************** Bit definition for OCTOSPIM_PCR register *****************/
-#define OCTOSPIM_PCR_CLKEN_Pos (0U)
-#define OCTOSPIM_PCR_CLKEN_Msk (0x1UL << OCTOSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */
-#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */
-#define OCTOSPIM_PCR_CLKSRC_Pos (1U)
-#define OCTOSPIM_PCR_CLKSRC_Msk (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */
-#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n*/
-#define OCTOSPIM_PCR_DQSEN_Pos (4U)
-#define OCTOSPIM_PCR_DQSEN_Msk (0x1UL << OCTOSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */
-#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */
-#define OCTOSPIM_PCR_DQSSRC_Pos (5U)
-#define OCTOSPIM_PCR_DQSSRC_Msk (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */
-#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */
-#define OCTOSPIM_PCR_NCSEN_Pos (8U)
-#define OCTOSPIM_PCR_NCSEN_Msk (0x1UL << OCTOSPIM_PCR_NCSEN_Pos) /*!< 0x00000100U */
-#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n*/
-#define OCTOSPIM_PCR_NCSSRC_Pos (9U)
-#define OCTOSPIM_PCR_NCSSRC_Msk (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200U */
-#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */
-#define OCTOSPIM_PCR_IOLEN_Pos (16U)
-#define OCTOSPIM_PCR_IOLEN_Msk (0x1UL << OCTOSPIM_PCR_IOLEN_Pos) /*!< 0x00010000U */
-#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */
-#define OCTOSPIM_PCR_IOLSRC_Pos (17U)
-#define OCTOSPIM_PCR_IOLSRC_Msk (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000U */
-#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */
-#define OCTOSPIM_PCR_IOLSRC_0 (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */
-#define OCTOSPIM_PCR_IOLSRC_1 (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */
-#define OCTOSPIM_PCR_IOHEN_Pos (24U)
-#define OCTOSPIM_PCR_IOHEN_Msk (0x1UL << OCTOSPIM_PCR_IOHEN_Pos) /*!< 0x01000000U */
-#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */
-#define OCTOSPIM_PCR_IOHSRC_Pos (25U)
-#define OCTOSPIM_PCR_IOHSRC_Msk (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000U */
-#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */
-#define OCTOSPIM_PCR_IOHSRC_0 (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000U */
-#define OCTOSPIM_PCR_IOHSRC_1 (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000U */
+#define OCTOSPIM_PCR_CLKEN_Pos XSPIM_PCR_CLKEN_Pos
+#define OCTOSPIM_PCR_CLKEN_Msk XSPIM_PCR_CLKEN_Msk /*!< 0x00000001 */
+#define OCTOSPIM_PCR_CLKEN XSPIM_PCR_CLKEN /*!< CLK/CLKn Enable for Port n */
+#define OCTOSPIM_PCR_CLKSRC_Pos XSPIM_PCR_CLKSRC_Pos
+#define OCTOSPIM_PCR_CLKSRC_Msk XSPIM_PCR_CLKSRC_Msk /*!< 0x00000002 */
+#define OCTOSPIM_PCR_CLKSRC XSPIM_PCR_CLKSRC /*!< CLK/CLKn Source for Port n*/
+#define OCTOSPIM_PCR_DQSEN_Pos XSPIM_PCR_DQSEN_Pos
+#define OCTOSPIM_PCR_DQSEN_Msk XSPIM_PCR_DQSEN_Msk /*!< 0x00000010 */
+#define OCTOSPIM_PCR_DQSEN XSPIM_PCR_DQSEN /*!< DQS Enable for Port n */
+#define OCTOSPIM_PCR_DQSSRC_Pos XSPIM_PCR_DQSSRC_Pos
+#define OCTOSPIM_PCR_DQSSRC_Msk XSPIM_PCR_DQSSRC_Msk /*!< 0x00000020 */
+#define OCTOSPIM_PCR_DQSSRC XSPIM_PCR_DQSSRC /*!< DQS Source for Port n */
+#define OCTOSPIM_PCR_NCSEN_Pos XSPIM_PCR_NCSEN_Pos
+#define OCTOSPIM_PCR_NCSEN_Msk XSPIM_PCR_NCSEN_Msk /*!< 0x00000100U */
+#define OCTOSPIM_PCR_NCSEN XSPIM_PCR_NCSEN /*!< nCS Enable for Port n*/
+#define OCTOSPIM_PCR_NCSSRC_Pos XSPIM_PCR_NCSSRC_Pos
+#define OCTOSPIM_PCR_NCSSRC_Msk XSPIM_PCR_NCSSRC_Msk /*!< 0x00000200U */
+#define OCTOSPIM_PCR_NCSSRC XSPIM_PCR_NCSSRC /*!< nCS Source for Port n */
+#define OCTOSPIM_PCR_IOLEN_Pos XSPIM_PCR_IOLEN_Pos
+#define OCTOSPIM_PCR_IOLEN_Msk XSPIM_PCR_IOLEN_Msk /*!< 0x00010000U */
+#define OCTOSPIM_PCR_IOLEN XSPIM_PCR_IOLEN /*!< IO[3:0] Enable for Port n */
+#define OCTOSPIM_PCR_IOLSRC_Pos XSPIM_PCR_IOLSRC_Pos
+#define OCTOSPIM_PCR_IOLSRC_Msk XSPIM_PCR_IOLSRC_Msk /*!< 0x00060000U */
+#define OCTOSPIM_PCR_IOLSRC XSPIM_PCR_IOLSRC /*!< IO[3:0] Source for Port n */
+#define OCTOSPIM_PCR_IOLSRC_0 XSPIM_PCR_IOLSRC_0 /*!< 0x00020000 */
+#define OCTOSPIM_PCR_IOLSRC_1 XSPIM_PCR_IOLSRC_1 /*!< 0x00040000 */
+#define OCTOSPIM_PCR_IOHEN_Pos XSPIM_PCR_IOHEN_Pos
+#define OCTOSPIM_PCR_IOHEN_Msk XSPIM_PCR_IOHEN_Msk /*!< 0x01000000U */
+#define OCTOSPIM_PCR_IOHEN XSPIM_PCR_IOHEN /*!< IO[7:4] Enable for Port n */
+#define OCTOSPIM_PCR_IOHSRC_Pos XSPIM_PCR_IOHSRC_Pos
+#define OCTOSPIM_PCR_IOHSRC_Msk XSPIM_PCR_IOHSRC_Msk /*!< 0x06000000U */
+#define OCTOSPIM_PCR_IOHSRC XSPIM_PCR_IOHSRC /*!< IO[7:4] Source for Port n */
+#define OCTOSPIM_PCR_IOHSRC_0 XSPIM_PCR_IOHSRC_0 /*!< 0x02000000U */
+#define OCTOSPIM_PCR_IOHSRC_1 XSPIM_PCR_IOHSRC_1 /*!< 0x04000000U */
/******************************************************************************/
/* */
@@ -15816,10 +16312,10 @@
#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000001 */
#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk /*!< GPDMA1 Reset */
#define RCC_AHB1RSTR_CORDICRST_Pos (1U)
-#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos) /*!< 0x00000002 */
#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk /*!< CORDIC Reset */
#define RCC_AHB1RSTR_FMACRST_Pos (2U)
-#define RCC_AHB1RSTR_FMACRST_Msk (0x1UL << RCC_AHB1RSTR_FMACRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_FMACRST_Msk (0x1UL << RCC_AHB1RSTR_FMACRST_Pos) /*!< 0x00000004 */
#define RCC_AHB1RSTR_FMACRST RCC_AHB1RSTR_FMACRST_Msk /*!< FMAC Reset */
#define RCC_AHB1RSTR_MDF1RST_Pos (3U)
#define RCC_AHB1RSTR_MDF1RST_Msk (0x1UL << RCC_AHB1RSTR_MDF1RST_Pos) /*!< 0x00000008 */
@@ -15831,7 +16327,7 @@
#define RCC_AHB1RSTR_TSCRST_Msk (0x1UL << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
#define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk /*!< TSC Reset */
#define RCC_AHB1RSTR_RAMCFGRST_Pos (17U)
-#define RCC_AHB1RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB1RSTR_RAMCFGRST_Pos) /*!< 0x00040000 */
+#define RCC_AHB1RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB1RSTR_RAMCFGRST_Pos) /*!< 0x00020000 */
#define RCC_AHB1RSTR_RAMCFGRST RCC_AHB1RSTR_RAMCFGRST_Msk /*!< RAMCFG Reset */
#define RCC_AHB1RSTR_DMA2DRST_Pos (18U)
#define RCC_AHB1RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00040000 */
@@ -15865,9 +16361,9 @@
#define RCC_AHB2RSTR1_GPIOIRST_Pos (8U)
#define RCC_AHB2RSTR1_GPIOIRST_Msk (0x1UL << RCC_AHB2RSTR1_GPIOIRST_Pos) /*!< 0x00000100 */
#define RCC_AHB2RSTR1_GPIOIRST RCC_AHB2RSTR1_GPIOIRST_Msk /*!< IO port I Reset */
-#define RCC_AHB2RSTR1_ADC1RST_Pos (10U)
-#define RCC_AHB2RSTR1_ADC1RST_Msk (0x1UL << RCC_AHB2RSTR1_ADC1RST_Pos) /*!< 0x00000400 */
-#define RCC_AHB2RSTR1_ADC1RST RCC_AHB2RSTR1_ADC1RST_Msk /*!< ADC1 Reset */
+#define RCC_AHB2RSTR1_ADC12RST_Pos (10U)
+#define RCC_AHB2RSTR1_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR1_ADC12RST_Pos) /*!< 0x00000400 */
+#define RCC_AHB2RSTR1_ADC12RST RCC_AHB2RSTR1_ADC12RST_Msk /*!< ADC1 Reset */
#define RCC_AHB2RSTR1_DCMI_PSSIRST_Pos (12U)
#define RCC_AHB2RSTR1_DCMI_PSSIRST_Msk (0x1UL << RCC_AHB2RSTR1_DCMI_PSSIRST_Pos) /*!< 0x00001000 */
#define RCC_AHB2RSTR1_DCMI_PSSIRST RCC_AHB2RSTR1_DCMI_PSSIRST_Msk /*!< DCMI and PSSI Reset */
@@ -16075,7 +16571,7 @@
#define RCC_AHB1ENR_TSCEN_Msk (0x1UL << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */
#define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk /*!< Touch Sensing Controller Clock Enable */
#define RCC_AHB1ENR_RAMCFGEN_Pos (17U)
-#define RCC_AHB1ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos) /*!< 0x00020000 */
#define RCC_AHB1ENR_RAMCFGEN RCC_AHB1ENR_RAMCFGEN_Msk /*!< RAMCFG Clock Enable */
#define RCC_AHB1ENR_DMA2DEN_Pos (18U)
#define RCC_AHB1ENR_DMA2DEN_Msk (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00040000 */
@@ -16087,96 +16583,96 @@
#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x10000000 */
#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk /*!< BKPSRAM Clock Enable */
#define RCC_AHB1ENR_DCACHE1EN_Pos (30U)
-#define RCC_AHB1ENR_DCACHE1EN_Msk (0x1UL << RCC_AHB1ENR_DCACHE1EN_Pos) /*!< 0x40000000 */
-#define RCC_AHB1ENR_DCACHE1EN RCC_AHB1ENR_DCACHE1EN_Msk /*!< DCACHE Clock Enable */
+#define RCC_AHB1ENR_DCACHE1EN_Msk (0x1UL << RCC_AHB1ENR_DCACHE1EN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1ENR_DCACHE1EN RCC_AHB1ENR_DCACHE1EN_Msk /*!< DCACHE1 Clock Enable */
#define RCC_AHB1ENR_SRAM1EN_Pos (31U)
#define RCC_AHB1ENR_SRAM1EN_Msk (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos) /*!< 0x80000000 */
#define RCC_AHB1ENR_SRAM1EN RCC_AHB1ENR_SRAM1EN_Msk /*!< SRAM1 Clock Enable */
/******************** Bit definition for RCC_AHB2ENR1 register **************/
#define RCC_AHB2ENR1_GPIOAEN_Pos (0U)
-#define RCC_AHB2ENR1_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOAEN_Pos) /*!< 0x00000001 */
-#define RCC_AHB2ENR1_GPIOAEN RCC_AHB2ENR1_GPIOAEN_Msk /*!< IO port A Clock Enable */
+#define RCC_AHB2ENR1_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2ENR1_GPIOAEN RCC_AHB2ENR1_GPIOAEN_Msk /*!< IO port A Clock Enable */
#define RCC_AHB2ENR1_GPIOBEN_Pos (1U)
-#define RCC_AHB2ENR1_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOBEN_Pos) /*!< 0x00000002 */
-#define RCC_AHB2ENR1_GPIOBEN RCC_AHB2ENR1_GPIOBEN_Msk /*!< IO port B Clock Enable */
+#define RCC_AHB2ENR1_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB2ENR1_GPIOBEN RCC_AHB2ENR1_GPIOBEN_Msk /*!< IO port B Clock Enable */
#define RCC_AHB2ENR1_GPIOCEN_Pos (2U)
-#define RCC_AHB2ENR1_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOCEN_Pos) /*!< 0x00000004 */
-#define RCC_AHB2ENR1_GPIOCEN RCC_AHB2ENR1_GPIOCEN_Msk /*!< IO port C Clock Enable */
+#define RCC_AHB2ENR1_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB2ENR1_GPIOCEN RCC_AHB2ENR1_GPIOCEN_Msk /*!< IO port C Clock Enable */
#define RCC_AHB2ENR1_GPIODEN_Pos (3U)
-#define RCC_AHB2ENR1_GPIODEN_Msk (0x1UL << RCC_AHB2ENR1_GPIODEN_Pos) /*!< 0x00000008 */
-#define RCC_AHB2ENR1_GPIODEN RCC_AHB2ENR1_GPIODEN_Msk /*!< IO port D Clock Enable */
+#define RCC_AHB2ENR1_GPIODEN_Msk (0x1UL << RCC_AHB2ENR1_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB2ENR1_GPIODEN RCC_AHB2ENR1_GPIODEN_Msk /*!< IO port D Clock Enable */
#define RCC_AHB2ENR1_GPIOEEN_Pos (4U)
-#define RCC_AHB2ENR1_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOEEN_Pos) /*!< 0x00000010 */
-#define RCC_AHB2ENR1_GPIOEEN RCC_AHB2ENR1_GPIOEEN_Msk /*!< IO port E Clock Enable */
+#define RCC_AHB2ENR1_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2ENR1_GPIOEEN RCC_AHB2ENR1_GPIOEEN_Msk /*!< IO port E Clock Enable */
#define RCC_AHB2ENR1_GPIOFEN_Pos (5U)
-#define RCC_AHB2ENR1_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOFEN_Pos) /*!< 0x00000020 */
-#define RCC_AHB2ENR1_GPIOFEN RCC_AHB2ENR1_GPIOFEN_Msk /*!< IO port F Clock Enable */
+#define RCC_AHB2ENR1_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2ENR1_GPIOFEN RCC_AHB2ENR1_GPIOFEN_Msk /*!< IO port F Clock Enable */
#define RCC_AHB2ENR1_GPIOGEN_Pos (6U)
-#define RCC_AHB2ENR1_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOGEN_Pos) /*!< 0x00000040 */
-#define RCC_AHB2ENR1_GPIOGEN RCC_AHB2ENR1_GPIOGEN_Msk /*!< IO port G Clock Enable */
+#define RCC_AHB2ENR1_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2ENR1_GPIOGEN RCC_AHB2ENR1_GPIOGEN_Msk /*!< IO port G Clock Enable */
#define RCC_AHB2ENR1_GPIOHEN_Pos (7U)
-#define RCC_AHB2ENR1_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOHEN_Pos) /*!< 0x00000080 */
-#define RCC_AHB2ENR1_GPIOHEN RCC_AHB2ENR1_GPIOHEN_Msk /*!< IO port H Clock Enable */
+#define RCC_AHB2ENR1_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR1_GPIOHEN RCC_AHB2ENR1_GPIOHEN_Msk /*!< IO port H Clock Enable */
#define RCC_AHB2ENR1_GPIOIEN_Pos (8U)
-#define RCC_AHB2ENR1_GPIOIEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOIEN_Pos) /*!< 0x00000100 */
-#define RCC_AHB2ENR1_GPIOIEN RCC_AHB2ENR1_GPIOIEN_Msk /*!< IO port I Clock Enable */
-#define RCC_AHB2ENR1_ADC1EN_Pos (10U)
-#define RCC_AHB2ENR1_ADC1EN_Msk (0x1UL << RCC_AHB2ENR1_ADC1EN_Pos) /*!< 0x00000400 */
-#define RCC_AHB2ENR1_ADC1EN RCC_AHB2ENR1_ADC1EN_Msk /*!< ADC1 Clock Enable */
+#define RCC_AHB2ENR1_GPIOIEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOIEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB2ENR1_GPIOIEN RCC_AHB2ENR1_GPIOIEN_Msk /*!< IO port I Clock Enable */
+#define RCC_AHB2ENR1_ADC12EN_Pos (10U)
+#define RCC_AHB2ENR1_ADC12EN_Msk (0x1UL << RCC_AHB2ENR1_ADC12EN_Pos) /*!< 0x00000400 */
+#define RCC_AHB2ENR1_ADC12EN RCC_AHB2ENR1_ADC12EN_Msk /*!< ADC1 Clock Enable */
#define RCC_AHB2ENR1_DCMI_PSSIEN_Pos (12U)
-#define RCC_AHB2ENR1_DCMI_PSSIEN_Msk (0x1UL << RCC_AHB2ENR1_DCMI_PSSIEN_Pos) /*!< 0x00001000 */
-#define RCC_AHB2ENR1_DCMI_PSSIEN RCC_AHB2ENR1_DCMI_PSSIEN_Msk /*!< DCMI and PSSI Clock Enable */
+#define RCC_AHB2ENR1_DCMI_PSSIEN_Msk (0x1UL << RCC_AHB2ENR1_DCMI_PSSIEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB2ENR1_DCMI_PSSIEN RCC_AHB2ENR1_DCMI_PSSIEN_Msk /*!< DCMI and PSSI Clock Enable */
#define RCC_AHB2ENR1_OTGEN_Pos (14U)
-#define RCC_AHB2ENR1_OTGEN_Msk (0x1UL << RCC_AHB2ENR1_OTGEN_Pos) /*!< 0x00004000 */
-#define RCC_AHB2ENR1_OTGEN RCC_AHB2ENR1_OTGEN_Msk /*!< OTG Clock Enable */
+#define RCC_AHB2ENR1_OTGEN_Msk (0x1UL << RCC_AHB2ENR1_OTGEN_Pos) /*!< 0x00004000 */
+#define RCC_AHB2ENR1_OTGEN RCC_AHB2ENR1_OTGEN_Msk /*!< OTG Clock Enable */
#define RCC_AHB2ENR1_AESEN_Pos (16U)
-#define RCC_AHB2ENR1_AESEN_Msk (0x1UL << RCC_AHB2ENR1_AESEN_Pos) /*!< 0x00010000 */
-#define RCC_AHB2ENR1_AESEN RCC_AHB2ENR1_AESEN_Msk /*!< AES Clock Enable */
+#define RCC_AHB2ENR1_AESEN_Msk (0x1UL << RCC_AHB2ENR1_AESEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB2ENR1_AESEN RCC_AHB2ENR1_AESEN_Msk /*!< AES Clock Enable */
#define RCC_AHB2ENR1_HASHEN_Pos (17U)
-#define RCC_AHB2ENR1_HASHEN_Msk (0x1UL << RCC_AHB2ENR1_HASHEN_Pos) /*!< 0x00020000 */
-#define RCC_AHB2ENR1_HASHEN RCC_AHB2ENR1_HASHEN_Msk /*!< HASH Clock Enable */
+#define RCC_AHB2ENR1_HASHEN_Msk (0x1UL << RCC_AHB2ENR1_HASHEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB2ENR1_HASHEN RCC_AHB2ENR1_HASHEN_Msk /*!< HASH Clock Enable */
#define RCC_AHB2ENR1_RNGEN_Pos (18U)
-#define RCC_AHB2ENR1_RNGEN_Msk (0x1UL << RCC_AHB2ENR1_RNGEN_Pos) /*!< 0x00040000 */
-#define RCC_AHB2ENR1_RNGEN RCC_AHB2ENR1_RNGEN_Msk /*!< RNG Clock Enable */
+#define RCC_AHB2ENR1_RNGEN_Msk (0x1UL << RCC_AHB2ENR1_RNGEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB2ENR1_RNGEN RCC_AHB2ENR1_RNGEN_Msk /*!< RNG Clock Enable */
#define RCC_AHB2ENR1_PKAEN_Pos (19U)
-#define RCC_AHB2ENR1_PKAEN_Msk (0x1UL << RCC_AHB2ENR1_PKAEN_Pos) /*!< 0x00080000 */
-#define RCC_AHB2ENR1_PKAEN RCC_AHB2ENR1_PKAEN_Msk /*!< PKA Clock Enable */
+#define RCC_AHB2ENR1_PKAEN_Msk (0x1UL << RCC_AHB2ENR1_PKAEN_Pos) /*!< 0x00080000 */
+#define RCC_AHB2ENR1_PKAEN RCC_AHB2ENR1_PKAEN_Msk /*!< PKA Clock Enable */
#define RCC_AHB2ENR1_SAESEN_Pos (20U)
-#define RCC_AHB2ENR1_SAESEN_Msk (0x1UL << RCC_AHB2ENR1_SAESEN_Pos) /*!< 0x00100000 */
-#define RCC_AHB2ENR1_SAESEN RCC_AHB2ENR1_SAESEN_Msk /*!< SAES Clock Enable */
+#define RCC_AHB2ENR1_SAESEN_Msk (0x1UL << RCC_AHB2ENR1_SAESEN_Pos) /*!< 0x00100000 */
+#define RCC_AHB2ENR1_SAESEN RCC_AHB2ENR1_SAESEN_Msk /*!< SAES Clock Enable */
#define RCC_AHB2ENR1_OCTOSPIMEN_Pos (21U)
-#define RCC_AHB2ENR1_OCTOSPIMEN_Msk (0x1UL << RCC_AHB2ENR1_OCTOSPIMEN_Pos) /*!< 0x00200000 */
-#define RCC_AHB2ENR1_OCTOSPIMEN RCC_AHB2ENR1_OCTOSPIMEN_Msk /*!< OCTOSPIM Clock Enable */
+#define RCC_AHB2ENR1_OCTOSPIMEN_Msk (0x1UL << RCC_AHB2ENR1_OCTOSPIMEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB2ENR1_OCTOSPIMEN RCC_AHB2ENR1_OCTOSPIMEN_Msk /*!< OCTOSPIM Clock Enable */
#define RCC_AHB2ENR1_OTFDEC1EN_Pos (23U)
-#define RCC_AHB2ENR1_OTFDEC1EN_Msk (0x1UL << RCC_AHB2ENR1_OTFDEC1EN_Pos) /*!< 0x00800000 */
-#define RCC_AHB2ENR1_OTFDEC1EN RCC_AHB2ENR1_OTFDEC1EN_Msk /*!< OTFDEC1 Clock Enable */
+#define RCC_AHB2ENR1_OTFDEC1EN_Msk (0x1UL << RCC_AHB2ENR1_OTFDEC1EN_Pos) /*!< 0x00800000 */
+#define RCC_AHB2ENR1_OTFDEC1EN RCC_AHB2ENR1_OTFDEC1EN_Msk /*!< OTFDEC1 Clock Enable */
#define RCC_AHB2ENR1_OTFDEC2EN_Pos (24U)
-#define RCC_AHB2ENR1_OTFDEC2EN_Msk (0x1UL << RCC_AHB2ENR1_OTFDEC2EN_Pos) /*!< 0x01000000 */
-#define RCC_AHB2ENR1_OTFDEC2EN RCC_AHB2ENR1_OTFDEC2EN_Msk /*!< OTFDEC2 Clock Enable */
+#define RCC_AHB2ENR1_OTFDEC2EN_Msk (0x1UL << RCC_AHB2ENR1_OTFDEC2EN_Pos) /*!< 0x01000000 */
+#define RCC_AHB2ENR1_OTFDEC2EN RCC_AHB2ENR1_OTFDEC2EN_Msk /*!< OTFDEC2 Clock Enable */
#define RCC_AHB2ENR1_SDMMC1EN_Pos (27U)
-#define RCC_AHB2ENR1_SDMMC1EN_Msk (0x1UL << RCC_AHB2ENR1_SDMMC1EN_Pos) /*!< 0x08000000 */
-#define RCC_AHB2ENR1_SDMMC1EN RCC_AHB2ENR1_SDMMC1EN_Msk /*!< SDMMC1 Clock Enable */
+#define RCC_AHB2ENR1_SDMMC1EN_Msk (0x1UL << RCC_AHB2ENR1_SDMMC1EN_Pos) /*!< 0x08000000 */
+#define RCC_AHB2ENR1_SDMMC1EN RCC_AHB2ENR1_SDMMC1EN_Msk /*!< SDMMC1 Clock Enable */
#define RCC_AHB2ENR1_SDMMC2EN_Pos (28U)
-#define RCC_AHB2ENR1_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR1_SDMMC2EN_Pos) /*!< 0x10000000 */
-#define RCC_AHB2ENR1_SDMMC2EN RCC_AHB2ENR1_SDMMC2EN_Msk /*!< SDMMC2 Clock Enable */
+#define RCC_AHB2ENR1_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR1_SDMMC2EN_Pos) /*!< 0x10000000 */
+#define RCC_AHB2ENR1_SDMMC2EN RCC_AHB2ENR1_SDMMC2EN_Msk /*!< SDMMC2 Clock Enable */
#define RCC_AHB2ENR1_SRAM2EN_Pos (30U)
-#define RCC_AHB2ENR1_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR1_SRAM2EN_Pos) /*!< 0x40000000 */
-#define RCC_AHB2ENR1_SRAM2EN RCC_AHB2ENR1_SRAM2EN_Msk /*!< SRAM2 Clock Enable */
+#define RCC_AHB2ENR1_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR1_SRAM2EN_Pos) /*!< 0x40000000 */
+#define RCC_AHB2ENR1_SRAM2EN RCC_AHB2ENR1_SRAM2EN_Msk /*!< SRAM2 Clock Enable */
#define RCC_AHB2ENR1_SRAM3EN_Pos (31U)
-#define RCC_AHB2ENR1_SRAM3EN_Msk (0x1UL << RCC_AHB2ENR1_SRAM3EN_Pos) /*!< 0x80000000 */
-#define RCC_AHB2ENR1_SRAM3EN RCC_AHB2ENR1_SRAM3EN_Msk /*!< SRAM3 Clock Enable */
+#define RCC_AHB2ENR1_SRAM3EN_Msk (0x1UL << RCC_AHB2ENR1_SRAM3EN_Pos) /*!< 0x80000000 */
+#define RCC_AHB2ENR1_SRAM3EN RCC_AHB2ENR1_SRAM3EN_Msk /*!< SRAM3 Clock Enable */
/******************** Bit definition for RCC_AHB2ENR2 register **************/
#define RCC_AHB2ENR2_FSMCEN_Pos (0U)
-#define RCC_AHB2ENR2_FSMCEN_Msk (0x1UL << RCC_AHB2ENR2_FSMCEN_Pos) /*!< 0x00000001 */
-#define RCC_AHB2ENR2_FSMCEN RCC_AHB2ENR2_FSMCEN_Msk /*!< FSMC Clock Enable */
+#define RCC_AHB2ENR2_FSMCEN_Msk (0x1UL << RCC_AHB2ENR2_FSMCEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2ENR2_FSMCEN RCC_AHB2ENR2_FSMCEN_Msk /*!< FSMC Clock Enable */
#define RCC_AHB2ENR2_OCTOSPI1EN_Pos (4U)
-#define RCC_AHB2ENR2_OCTOSPI1EN_Msk (0x1UL << RCC_AHB2ENR2_OCTOSPI1EN_Pos) /*!< 0x00000010 */
-#define RCC_AHB2ENR2_OCTOSPI1EN RCC_AHB2ENR2_OCTOSPI1EN_Msk /*!< OCTOSPI1 Clock Enable */
+#define RCC_AHB2ENR2_OCTOSPI1EN_Msk (0x1UL << RCC_AHB2ENR2_OCTOSPI1EN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2ENR2_OCTOSPI1EN RCC_AHB2ENR2_OCTOSPI1EN_Msk /*!< OCTOSPI1 Clock Enable */
#define RCC_AHB2ENR2_OCTOSPI2EN_Pos (8U)
-#define RCC_AHB2ENR2_OCTOSPI2EN_Msk (0x1UL << RCC_AHB2ENR2_OCTOSPI2EN_Pos) /*!< 0x00000100 */
-#define RCC_AHB2ENR2_OCTOSPI2EN RCC_AHB2ENR2_OCTOSPI2EN_Msk /*!< OCTOSPI2 Clock Enable */
+#define RCC_AHB2ENR2_OCTOSPI2EN_Msk (0x1UL << RCC_AHB2ENR2_OCTOSPI2EN_Pos) /*!< 0x00000100 */
+#define RCC_AHB2ENR2_OCTOSPI2EN RCC_AHB2ENR2_OCTOSPI2EN_Msk /*!< OCTOSPI2 Clock Enable */
/******************** Bit definition for RCC_AHB3ENR register **************/
#define RCC_AHB3ENR_LPGPIO1EN_Pos (0U)
@@ -16296,82 +16792,82 @@
/******************** Bit definition for RCC_APB3ENR register **************/
#define RCC_APB3ENR_SYSCFGEN_Pos (1U)
-#define RCC_APB3ENR_SYSCFGEN_Msk (0x1UL << RCC_APB3ENR_SYSCFGEN_Pos) /*!< 0x00000002 */
-#define RCC_APB3ENR_SYSCFGEN RCC_APB3ENR_SYSCFGEN_Msk /*!< SYSCFG Clock Enable */
+#define RCC_APB3ENR_SYSCFGEN_Msk (0x1UL << RCC_APB3ENR_SYSCFGEN_Pos) /*!< 0x00000002 */
+#define RCC_APB3ENR_SYSCFGEN RCC_APB3ENR_SYSCFGEN_Msk /*!< SYSCFG Clock Enable */
#define RCC_APB3ENR_SPI3EN_Pos (5U)
-#define RCC_APB3ENR_SPI3EN_Msk (0x1UL << RCC_APB3ENR_SPI3EN_Pos) /*!< 0x00000010 */
-#define RCC_APB3ENR_SPI3EN RCC_APB3ENR_SPI3EN_Msk /*!< SPI3 Clock Enable */
+#define RCC_APB3ENR_SPI3EN_Msk (0x1UL << RCC_APB3ENR_SPI3EN_Pos) /*!< 0x00000010 */
+#define RCC_APB3ENR_SPI3EN RCC_APB3ENR_SPI3EN_Msk /*!< SPI3 Clock Enable */
#define RCC_APB3ENR_LPUART1EN_Pos (6U)
-#define RCC_APB3ENR_LPUART1EN_Msk (0x1UL << RCC_APB3ENR_LPUART1EN_Pos) /*!< 0x00000040 */
-#define RCC_APB3ENR_LPUART1EN RCC_APB3ENR_LPUART1EN_Msk /*!< LPUART1 Clock Enable */
+#define RCC_APB3ENR_LPUART1EN_Msk (0x1UL << RCC_APB3ENR_LPUART1EN_Pos) /*!< 0x00000040 */
+#define RCC_APB3ENR_LPUART1EN RCC_APB3ENR_LPUART1EN_Msk /*!< LPUART1 Clock Enable */
#define RCC_APB3ENR_I2C3EN_Pos (7U)
-#define RCC_APB3ENR_I2C3EN_Msk (0x1UL << RCC_APB3ENR_I2C3EN_Pos) /*!< 0x000000080 */
-#define RCC_APB3ENR_I2C3EN RCC_APB3ENR_I2C3EN_Msk /*!< I2C3 Clock Enable */
+#define RCC_APB3ENR_I2C3EN_Msk (0x1UL << RCC_APB3ENR_I2C3EN_Pos) /*!< 0x000000080 */
+#define RCC_APB3ENR_I2C3EN RCC_APB3ENR_I2C3EN_Msk /*!< I2C3 Clock Enable */
#define RCC_APB3ENR_LPTIM1EN_Pos (11U)
-#define RCC_APB3ENR_LPTIM1EN_Msk (0x1UL << RCC_APB3ENR_LPTIM1EN_Pos) /*!< 0x000000800 */
-#define RCC_APB3ENR_LPTIM1EN RCC_APB3ENR_LPTIM1EN_Msk /*!< LPTIM1 Clock Enable */
+#define RCC_APB3ENR_LPTIM1EN_Msk (0x1UL << RCC_APB3ENR_LPTIM1EN_Pos) /*!< 0x000000800 */
+#define RCC_APB3ENR_LPTIM1EN RCC_APB3ENR_LPTIM1EN_Msk /*!< LPTIM1 Clock Enable */
#define RCC_APB3ENR_LPTIM3EN_Pos (12U)
-#define RCC_APB3ENR_LPTIM3EN_Msk (0x1UL << RCC_APB3ENR_LPTIM3EN_Pos) /*!< 0x000001000 */
-#define RCC_APB3ENR_LPTIM3EN RCC_APB3ENR_LPTIM3EN_Msk /*!< LPTIM3 Clock Enable */
+#define RCC_APB3ENR_LPTIM3EN_Msk (0x1UL << RCC_APB3ENR_LPTIM3EN_Pos) /*!< 0x000001000 */
+#define RCC_APB3ENR_LPTIM3EN RCC_APB3ENR_LPTIM3EN_Msk /*!< LPTIM3 Clock Enable */
#define RCC_APB3ENR_LPTIM4EN_Pos (13U)
-#define RCC_APB3ENR_LPTIM4EN_Msk (0x1UL << RCC_APB3ENR_LPTIM4EN_Pos) /*!< 0x0000002000 */
-#define RCC_APB3ENR_LPTIM4EN RCC_APB3ENR_LPTIM4EN_Msk /*!< LPTIM4 Clock Enable */
+#define RCC_APB3ENR_LPTIM4EN_Msk (0x1UL << RCC_APB3ENR_LPTIM4EN_Pos) /*!< 0x0000002000 */
+#define RCC_APB3ENR_LPTIM4EN RCC_APB3ENR_LPTIM4EN_Msk /*!< LPTIM4 Clock Enable */
#define RCC_APB3ENR_OPAMPEN_Pos (14U)
-#define RCC_APB3ENR_OPAMPEN_Msk (0x1UL << RCC_APB3ENR_OPAMPEN_Pos) /*!< 0x000004000 */
-#define RCC_APB3ENR_OPAMPEN RCC_APB3ENR_OPAMPEN_Msk /*!< OPAMP Clock Enable */
+#define RCC_APB3ENR_OPAMPEN_Msk (0x1UL << RCC_APB3ENR_OPAMPEN_Pos) /*!< 0x000004000 */
+#define RCC_APB3ENR_OPAMPEN RCC_APB3ENR_OPAMPEN_Msk /*!< OPAMP Clock Enable */
#define RCC_APB3ENR_COMPEN_Pos (15U)
-#define RCC_APB3ENR_COMPEN_Msk (0x1UL << RCC_APB3ENR_COMPEN_Pos) /*!< 0x000004000 */
-#define RCC_APB3ENR_COMPEN RCC_APB3ENR_COMPEN_Msk /*!< COMP Clock Enable */
+#define RCC_APB3ENR_COMPEN_Msk (0x1UL << RCC_APB3ENR_COMPEN_Pos) /*!< 0x000004000 */
+#define RCC_APB3ENR_COMPEN RCC_APB3ENR_COMPEN_Msk /*!< COMP Clock Enable */
#define RCC_APB3ENR_VREFEN_Pos (20U)
-#define RCC_APB3ENR_VREFEN_Msk (0x1UL << RCC_APB3ENR_VREFEN_Pos) /*!< 0x000100000 */
-#define RCC_APB3ENR_VREFEN RCC_APB3ENR_VREFEN_Msk /*!< VREFBUF Clock Enable */
+#define RCC_APB3ENR_VREFEN_Msk (0x1UL << RCC_APB3ENR_VREFEN_Pos) /*!< 0x000100000 */
+#define RCC_APB3ENR_VREFEN RCC_APB3ENR_VREFEN_Msk /*!< VREFBUF Clock Enable */
#define RCC_APB3ENR_RTCAPBEN_Pos (21U)
-#define RCC_APB3ENR_RTCAPBEN_Msk (0x1UL << RCC_APB3ENR_RTCAPBEN_Pos) /*!< 0x000200000 */
-#define RCC_APB3ENR_RTCAPBEN RCC_APB3ENR_RTCAPBEN_Msk /*!< RTC APB Clock Enable */
+#define RCC_APB3ENR_RTCAPBEN_Msk (0x1UL << RCC_APB3ENR_RTCAPBEN_Pos) /*!< 0x000200000 */
+#define RCC_APB3ENR_RTCAPBEN RCC_APB3ENR_RTCAPBEN_Msk /*!< RTC APB Clock Enable */
/******************** Bit definition for RCC_AHB1SMENR register **************/
#define RCC_AHB1SMENR_GPDMA1SMEN_Pos (0U)
-#define RCC_AHB1SMENR_GPDMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_GPDMA1SMEN_Pos) /*!< 0x00000000*/
-#define RCC_AHB1SMENR_GPDMA1SMEN RCC_AHB1SMENR_GPDMA1SMEN_Msk /*!< GPDMA1 Clocks Enable During Sleep and Stop Modes */
+#define RCC_AHB1SMENR_GPDMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_GPDMA1SMEN_Pos) /*!< 0x00000000*/
+#define RCC_AHB1SMENR_GPDMA1SMEN RCC_AHB1SMENR_GPDMA1SMEN_Msk /*!< GPDMA1 Clocks Enable During Sleep and Stop Modes */
#define RCC_AHB1SMENR_CORDICSMEN_Pos (1U)
-#define RCC_AHB1SMENR_CORDICSMEN_Msk (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos) /*!< 0x00000001*/
-#define RCC_AHB1SMENR_CORDICSMEN RCC_AHB1SMENR_CORDICSMEN_Msk /*!< CORDIC Clocks Enable During Sleep and Stop Modes */
+#define RCC_AHB1SMENR_CORDICSMEN_Msk (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos) /*!< 0x00000001*/
+#define RCC_AHB1SMENR_CORDICSMEN RCC_AHB1SMENR_CORDICSMEN_Msk /*!< CORDIC Clocks Enable During Sleep and Stop Modes */
#define RCC_AHB1SMENR_FMACSMEN_Pos (2U)
-#define RCC_AHB1SMENR_FMACSMEN_Msk (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos) /*!< 0x00000002*/
-#define RCC_AHB1SMENR_FMACSMEN RCC_AHB1SMENR_FMACSMEN_Msk /*!< FMAC Clocks Enable During Sleep and Stop Modes */
+#define RCC_AHB1SMENR_FMACSMEN_Msk (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos) /*!< 0x00000002*/
+#define RCC_AHB1SMENR_FMACSMEN RCC_AHB1SMENR_FMACSMEN_Msk /*!< FMAC Clocks Enable During Sleep and Stop Modes */
#define RCC_AHB1SMENR_MDF1SMEN_Pos (3U)
-#define RCC_AHB1SMENR_MDF1SMEN_Msk (0x1UL << RCC_AHB1SMENR_MDF1SMEN_Pos) /*!< 0x00000004 */
-#define RCC_AHB1SMENR_MDF1SMEN RCC_AHB1SMENR_MDF1SMEN_Msk /*!< MDF1 Clocks Enable During Sleep and Stop Modes */
+#define RCC_AHB1SMENR_MDF1SMEN_Msk (0x1UL << RCC_AHB1SMENR_MDF1SMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1SMENR_MDF1SMEN RCC_AHB1SMENR_MDF1SMEN_Msk /*!< MDF1 Clocks Enable During Sleep and Stop Modes */
#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
-#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
-#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk /*!< FLASH Clocks Enable During Sleep and Stop Modes */
+#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk /*!< FLASH Clocks Enable During Sleep and Stop Modes */
#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
-#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
-#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk /*!< CRC Clocks Enable During Sleep and Stop Modes */
+#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk /*!< CRC Clocks Enable During Sleep and Stop Modes */
#define RCC_AHB1SMENR_TSCSMEN_Pos (16U)
-#define RCC_AHB1SMENR_TSCSMEN_Msk (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
-#define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk /*!< TSC Clocks Enable During Sleep and Stop Modes */
+#define RCC_AHB1SMENR_TSCSMEN_Msk (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk /*!< TSC Clocks Enable During Sleep and Stop Modes */
#define RCC_AHB1SMENR_RAMCFGSMEN_Pos (17U)
-#define RCC_AHB1SMENR_RAMCFGSMEN_Msk (0x1UL << RCC_AHB1SMENR_RAMCFGSMEN_Pos) /*!< 0x00020000 */
-#define RCC_AHB1SMENR_RAMCFGSMEN RCC_AHB1SMENR_RAMCFGSMEN_Msk /*!< RAMCFG Clocks Enable During Sleep and Stop Modes */
+#define RCC_AHB1SMENR_RAMCFGSMEN_Msk (0x1UL << RCC_AHB1SMENR_RAMCFGSMEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1SMENR_RAMCFGSMEN RCC_AHB1SMENR_RAMCFGSMEN_Msk /*!< RAMCFG Clocks Enable During Sleep and Stop Modes */
#define RCC_AHB1SMENR_DMA2DSMEN_Pos (18U)
-#define RCC_AHB1SMENR_DMA2DSMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2DSMEN_Pos) /*!< 0x00040000 */
-#define RCC_AHB1SMENR_DMA2DSMEN RCC_AHB1SMENR_DMA2DSMEN_Msk /*!< DMA2D Clocks Enable During Sleep and Stop Modes */
+#define RCC_AHB1SMENR_DMA2DSMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2DSMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1SMENR_DMA2DSMEN RCC_AHB1SMENR_DMA2DSMEN_Msk /*!< DMA2D Clocks Enable During Sleep and Stop Modes */
#define RCC_AHB1SMENR_GTZC1SMEN_Pos (24U)
-#define RCC_AHB1SMENR_GTZC1SMEN_Msk (0x1UL << RCC_AHB1SMENR_GTZC1SMEN_Pos) /*!< 0x01000000 */
-#define RCC_AHB1SMENR_GTZC1SMEN RCC_AHB1SMENR_GTZC1SMEN_Msk /*!< GTZC1 Clocks Enable During Sleep and Stop Modes */
+#define RCC_AHB1SMENR_GTZC1SMEN_Msk (0x1UL << RCC_AHB1SMENR_GTZC1SMEN_Pos) /*!< 0x01000000 */
+#define RCC_AHB1SMENR_GTZC1SMEN RCC_AHB1SMENR_GTZC1SMEN_Msk /*!< GTZC1 Clocks Enable During Sleep and Stop Modes */
#define RCC_AHB1SMENR_BKPSRAMSMEN_Pos (28U)
#define RCC_AHB1SMENR_BKPSRAMSMEN_Msk (0x1UL << RCC_AHB1SMENR_BKPSRAMSMEN_Pos) /*!< 0x10000000 */
#define RCC_AHB1SMENR_BKPSRAMSMEN RCC_AHB1SMENR_BKPSRAMSMEN_Msk /*!< BKPSRAM Clocks Enable During Sleep and Stop Modes */
#define RCC_AHB1SMENR_ICACHESMEN_Pos (29U)
-#define RCC_AHB1SMENR_ICACHESMEN_Msk (0x1UL << RCC_AHB1SMENR_ICACHESMEN_Pos) /*!< 0x20000000 */
-#define RCC_AHB1SMENR_ICACHESMEN RCC_AHB1SMENR_ICACHESMEN_Msk /*!< ICACHE Clocks Enable During Sleep and Stop Modes */
+#define RCC_AHB1SMENR_ICACHESMEN_Msk (0x1UL << RCC_AHB1SMENR_ICACHESMEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB1SMENR_ICACHESMEN RCC_AHB1SMENR_ICACHESMEN_Msk /*!< ICACHE Clocks Enable During Sleep and Stop Modes */
#define RCC_AHB1SMENR_DCACHE1SMEN_Pos (30U)
#define RCC_AHB1SMENR_DCACHE1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DCACHE1SMEN_Pos) /*!< 0x40000000 */
-#define RCC_AHB1SMENR_DCACHE1SMEN RCC_AHB1SMENR_DCACHE1SMEN_Msk /*!< DCACHE Clocks Enable During Sleep and Stop Modes */
+#define RCC_AHB1SMENR_DCACHE1SMEN RCC_AHB1SMENR_DCACHE1SMEN_Msk /*!< DCACHE1 Clocks Enable During Sleep and Stop Modes */
#define RCC_AHB1SMENR_SRAM1SMEN_Pos (31U)
-#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk /*!< SRAM1 Clocks Enable During Sleep and Stop Modes */
+#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk /*!< SRAM1 Clocks Enable During Sleep and Stop Modes */
/******************** Bit definition for RCC_AHB2SMENR1 register **************/
#define RCC_AHB2SMENR1_GPIOASMEN_Pos (0U)
@@ -16401,16 +16897,16 @@
#define RCC_AHB2SMENR1_GPIOISMEN_Pos (8U)
#define RCC_AHB2SMENR1_GPIOISMEN_Msk (0x1UL << RCC_AHB2SMENR1_GPIOISMEN_Pos) /*!< 0x00000100 */
#define RCC_AHB2SMENR1_GPIOISMEN RCC_AHB2SMENR1_GPIOISMEN_Msk /*!< IO port I Clocks Enable During Sleep and Stop Modes */
-#define RCC_AHB2SMENR1_ADC1SMEN_Pos (10U)
-#define RCC_AHB2SMENR1_ADC1SMEN_Msk (0x1UL << RCC_AHB2SMENR1_ADC1SMEN_Pos) /*!< 0x00000400 */
-#define RCC_AHB2SMENR1_ADC1SMEN RCC_AHB2SMENR1_ADC1SMEN_Msk /*!< ADC1 Clocks Enable During Sleep and Stop Modes */
+#define RCC_AHB2SMENR1_ADC12SMEN_Pos (10U)
+#define RCC_AHB2SMENR1_ADC12SMEN_Msk (0x1UL << RCC_AHB2SMENR1_ADC12SMEN_Pos) /*!< 0x00000400 */
+#define RCC_AHB2SMENR1_ADC12SMEN RCC_AHB2SMENR1_ADC12SMEN_Msk /*!< ADC1 Clocks Enable During Sleep and Stop Modes */
#define RCC_AHB2SMENR1_DCMI_PSSISMEN_Pos (12U)
#define RCC_AHB2SMENR1_DCMI_PSSISMEN_Msk (0x1UL << RCC_AHB2SMENR1_DCMI_PSSISMEN_Pos) /*!< 0x00001000 */
#define RCC_AHB2SMENR1_DCMI_PSSISMEN RCC_AHB2SMENR1_DCMI_PSSISMEN_Msk /*!< DCMI and PSSI Clocks Enable During Sleep and Stop Modes */
#define RCC_AHB2SMENR1_OTGSMEN_Pos (14U)
#define RCC_AHB2SMENR1_OTGSMEN_Msk (0x1UL << RCC_AHB2SMENR1_OTGSMEN_Pos) /*!< 0x00004000 */
#define RCC_AHB2SMENR1_OTGSMEN RCC_AHB2SMENR1_OTGSMEN_Msk /*!< OTG Clocks Enable During Sleep and Stop Modes */
-#define RCC_AHB2SMENR1_AESSMEN_Pos (16U)
+#define RCC_AHB2SMENR1_AESSMEN_Pos (16U)
#define RCC_AHB2SMENR1_AESSMEN_Msk (0x1UL << RCC_AHB2SMENR1_AESSMEN_Pos) /*!< 0x00010000 */
#define RCC_AHB2SMENR1_AESSMEN RCC_AHB2SMENR1_AESSMEN_Msk /*!< AES Clocks Enable During Sleep and Stop Modes */
#define RCC_AHB2SMENR1_HASHSMEN_Pos (17U)
@@ -16486,50 +16982,50 @@
/******************** Bit definition for RCC_APB1SMENR1 register **************/
#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
-#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk /*!< TIM2 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk /*!< TIM2 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
-#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk /*!< TIM3 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk /*!< TIM3 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
-#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk /*!< TIM4 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk /*!< TIM4 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
-#define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */
-#define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk /*!< TIM5 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk /*!< TIM5 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
-#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk /*!< TIM6 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk /*!< TIM6 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
-#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk /*!< TIM7 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk /*!< TIM7 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
-#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk /*!< Window Watchdog Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk /*!< Window Watchdog Clocks Enable During Sleep and Stop Modes */
#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
-#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk /*!< SPI2 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk /*!< SPI2 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
-#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk /*!< USART2 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
-#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk /*!< USART3 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
-#define RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */
-#define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk /*!< UART4 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk /*!< UART4 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
-#define RCC_APB1SMENR1_UART5SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */
-#define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk /*!< UART5 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB1SMENR1_UART5SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk /*!< UART5 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
-#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk /*!< I2C1 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk /*!< I2C1 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
-#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk /*!< I2C2 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk /*!< I2C2 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB1SMENR1_CRSSMEN_Pos (24U)
-#define RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */
-#define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk /*!< CRS Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */
+#define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk /*!< CRS Clocks Enable During Sleep and Stop Modes */
/******************** Bit definition for RCC_APB1SMENR2 register **************/
#define RCC_APB1SMENR2_I2C4SMEN_Pos (1U)
@@ -16547,268 +17043,268 @@
/******************** Bit definition for RCC_APB2SMENR register **************/
#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
-#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
-#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk /*!< TIM1 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk /*!< TIM1 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
-#define RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */
-#define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk /*!< TIM8 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk /*!< TIM8 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
-#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
-#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
-#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk /*!< TIM15 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk /*!< TIM15 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
-#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk /*!< TIM16 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk /*!< TIM16 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
-#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk /*!< TIM17 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk /*!< TIM17 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
-#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
-#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk /*!< SAI1 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk /*!< SAI1 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB2SMENR_SAI2SMEN_Pos (22U)
-#define RCC_APB2SMENR_SAI2SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */
-#define RCC_APB2SMENR_SAI2SMEN RCC_APB2SMENR_SAI2SMEN_Msk /*!< SAI2 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB2SMENR_SAI2SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_SAI2SMEN RCC_APB2SMENR_SAI2SMEN_Msk /*!< SAI2 Clocks Enable During Sleep and Stop Modes */
/******************** Bit definition for RCC_APB3SMENR register **************/
#define RCC_APB3SMENR_SYSCFGSMEN_Pos (1U)
-#define RCC_APB3SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB3SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB3SMENR_SYSCFGSMEN RCC_APB3SMENR_SYSCFGSMEN_Msk /*!< SYSCFG Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB3SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB3SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB3SMENR_SYSCFGSMEN RCC_APB3SMENR_SYSCFGSMEN_Msk /*!< SYSCFG Clocks Enable During Sleep and Stop Modes */
#define RCC_APB3SMENR_SPI3SMEN_Pos (5U)
-#define RCC_APB3SMENR_SPI3SMEN_Msk (0x1UL << RCC_APB3SMENR_SPI3SMEN_Pos) /*!< 0x00000010 */
-#define RCC_APB3SMENR_SPI3SMEN RCC_APB3SMENR_SPI3SMEN_Msk /*!< SPI3 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB3SMENR_SPI3SMEN_Msk (0x1UL << RCC_APB3SMENR_SPI3SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB3SMENR_SPI3SMEN RCC_APB3SMENR_SPI3SMEN_Msk /*!< SPI3 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB3SMENR_LPUART1SMEN_Pos (6U)
-#define RCC_APB3SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB3SMENR_LPUART1SMEN_Pos) /*!< 0x00000040 */
-#define RCC_APB3SMENR_LPUART1SMEN RCC_APB3SMENR_LPUART1SMEN_Msk /*!< LPUART1 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB3SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB3SMENR_LPUART1SMEN_Pos) /*!< 0x00000040 */
+#define RCC_APB3SMENR_LPUART1SMEN RCC_APB3SMENR_LPUART1SMEN_Msk /*!< LPUART1 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB3SMENR_I2C3SMEN_Pos (7U)
-#define RCC_APB3SMENR_I2C3SMEN_Msk (0x1UL << RCC_APB3SMENR_I2C3SMEN_Pos) /*!< 0x000000080 */
-#define RCC_APB3SMENR_I2C3SMEN RCC_APB3SMENR_I2C3SMEN_Msk /*!< I2C3 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB3SMENR_I2C3SMEN_Msk (0x1UL << RCC_APB3SMENR_I2C3SMEN_Pos) /*!< 0x000000080 */
+#define RCC_APB3SMENR_I2C3SMEN RCC_APB3SMENR_I2C3SMEN_Msk /*!< I2C3 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB3SMENR_LPTIM1SMEN_Pos (11U)
-#define RCC_APB3SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB3SMENR_LPTIM1SMEN_Pos) /*!< 0x000000800 */
-#define RCC_APB3SMENR_LPTIM1SMEN RCC_APB3SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB3SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB3SMENR_LPTIM1SMEN_Pos) /*!< 0x000000800 */
+#define RCC_APB3SMENR_LPTIM1SMEN RCC_APB3SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB3SMENR_LPTIM3SMEN_Pos (12U)
-#define RCC_APB3SMENR_LPTIM3SMEN_Msk (0x1UL << RCC_APB3SMENR_LPTIM3SMEN_Pos) /*!< 0x000001000 */
-#define RCC_APB3SMENR_LPTIM3SMEN RCC_APB3SMENR_LPTIM3SMEN_Msk /*!< LPTIM3 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB3SMENR_LPTIM3SMEN_Msk (0x1UL << RCC_APB3SMENR_LPTIM3SMEN_Pos) /*!< 0x000001000 */
+#define RCC_APB3SMENR_LPTIM3SMEN RCC_APB3SMENR_LPTIM3SMEN_Msk /*!< LPTIM3 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB3SMENR_LPTIM4SMEN_Pos (13U)
-#define RCC_APB3SMENR_LPTIM4SMEN_Msk (0x1UL << RCC_APB3SMENR_LPTIM4SMEN_Pos) /*!< 0x0000002000*/
-#define RCC_APB3SMENR_LPTIM4SMEN RCC_APB3SMENR_LPTIM4SMEN_Msk /*!< LPTIM4 Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB3SMENR_LPTIM4SMEN_Msk (0x1UL << RCC_APB3SMENR_LPTIM4SMEN_Pos) /*!< 0x0000002000*/
+#define RCC_APB3SMENR_LPTIM4SMEN RCC_APB3SMENR_LPTIM4SMEN_Msk /*!< LPTIM4 Clocks Enable During Sleep and Stop Modes */
#define RCC_APB3SMENR_OPAMPSMEN_Pos (14U)
-#define RCC_APB3SMENR_OPAMPSMEN_Msk (0x1UL << RCC_APB3SMENR_OPAMPSMEN_Pos) /*!< 0x000004000 */
-#define RCC_APB3SMENR_OPAMPSMEN RCC_APB3SMENR_OPAMPSMEN_Msk /*!< OPAMP Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB3SMENR_OPAMPSMEN_Msk (0x1UL << RCC_APB3SMENR_OPAMPSMEN_Pos) /*!< 0x000004000 */
+#define RCC_APB3SMENR_OPAMPSMEN RCC_APB3SMENR_OPAMPSMEN_Msk /*!< OPAMP Clocks Enable During Sleep and Stop Modes */
#define RCC_APB3SMENR_COMPSMEN_Pos (15U)
-#define RCC_APB3SMENR_COMPSMEN_Msk (0x1UL << RCC_APB3SMENR_COMPSMEN_Pos) /*!< 0x000004000 */
-#define RCC_APB3SMENR_COMPSMEN RCC_APB3SMENR_COMPSMEN_Msk /*!< COMP Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB3SMENR_COMPSMEN_Msk (0x1UL << RCC_APB3SMENR_COMPSMEN_Pos) /*!< 0x000004000 */
+#define RCC_APB3SMENR_COMPSMEN RCC_APB3SMENR_COMPSMEN_Msk /*!< COMP Clocks Enable During Sleep and Stop Modes */
#define RCC_APB3SMENR_VREFSMEN_Pos (20U)
-#define RCC_APB3SMENR_VREFSMEN_Msk (0x1UL << RCC_APB3SMENR_VREFSMEN_Pos) /*!< 0x000100000 */
-#define RCC_APB3SMENR_VREFSMEN RCC_APB3SMENR_VREFSMEN_Msk /*!< VREFBUF Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB3SMENR_VREFSMEN_Msk (0x1UL << RCC_APB3SMENR_VREFSMEN_Pos) /*!< 0x000100000 */
+#define RCC_APB3SMENR_VREFSMEN RCC_APB3SMENR_VREFSMEN_Msk /*!< VREFBUF Clocks Enable During Sleep and Stop Modes */
#define RCC_APB3SMENR_RTCAPBSMEN_Pos (21U)
-#define RCC_APB3SMENR_RTCAPBSMEN_Msk (0x1UL << RCC_APB3SMENR_RTCAPBSMEN_Pos) /*!< 0x000100000 */
-#define RCC_APB3SMENR_RTCAPBSMEN RCC_APB3SMENR_RTCAPBSMEN_Msk /*!< RTC APB Clocks Enable During Sleep and Stop Modes */
+#define RCC_APB3SMENR_RTCAPBSMEN_Msk (0x1UL << RCC_APB3SMENR_RTCAPBSMEN_Pos) /*!< 0x000100000 */
+#define RCC_APB3SMENR_RTCAPBSMEN RCC_APB3SMENR_RTCAPBSMEN_Msk /*!< RTC APB Clocks Enable During Sleep and Stop Modes */
/******************** Bit definition for RCC_SRDAMR register ********************/
#define RCC_SRDAMR_SPI3AMEN_Pos (5U)
-#define RCC_SRDAMR_SPI3AMEN_Msk (0x1UL << RCC_SRDAMR_SPI3AMEN_Pos) /*!< 0x00000020 */
-#define RCC_SRDAMR_SPI3AMEN RCC_SRDAMR_SPI3AMEN_Msk /*!< SPI3 Autonomous Mode Enable in Stop 0,1,2 Mode */
+#define RCC_SRDAMR_SPI3AMEN_Msk (0x1UL << RCC_SRDAMR_SPI3AMEN_Pos) /*!< 0x00000020 */
+#define RCC_SRDAMR_SPI3AMEN RCC_SRDAMR_SPI3AMEN_Msk /*!< SPI3 Autonomous Mode Enable in Stop 0,1,2 Mode */
#define RCC_SRDAMR_LPUART1AMEN_Pos (6U)
-#define RCC_SRDAMR_LPUART1AMEN_Msk (0x1UL << RCC_SRDAMR_LPUART1AMEN_Pos) /*!< 0x00000040 */
-#define RCC_SRDAMR_LPUART1AMEN RCC_SRDAMR_LPUART1AMEN_Msk /*!< LPUART1 Autonomous Mode Enable in Stop 0,1,2 Mode */
+#define RCC_SRDAMR_LPUART1AMEN_Msk (0x1UL << RCC_SRDAMR_LPUART1AMEN_Pos) /*!< 0x00000040 */
+#define RCC_SRDAMR_LPUART1AMEN RCC_SRDAMR_LPUART1AMEN_Msk /*!< LPUART1 Autonomous Mode Enable in Stop 0,1,2 Mode */
#define RCC_SRDAMR_I2C3AMEN_Pos (7U)
-#define RCC_SRDAMR_I2C3AMEN_Msk (0x1UL << RCC_SRDAMR_I2C3AMEN_Pos) /*!< 0x00000080 */
-#define RCC_SRDAMR_I2C3AMEN RCC_SRDAMR_I2C3AMEN_Msk /*!< I2C3 Autonomous Mode Enable in Stop 0,1,2 Mode */
+#define RCC_SRDAMR_I2C3AMEN_Msk (0x1UL << RCC_SRDAMR_I2C3AMEN_Pos) /*!< 0x00000080 */
+#define RCC_SRDAMR_I2C3AMEN RCC_SRDAMR_I2C3AMEN_Msk /*!< I2C3 Autonomous Mode Enable in Stop 0,1,2 Mode */
#define RCC_SRDAMR_LPTIM1AMEN_Pos (11U)
-#define RCC_SRDAMR_LPTIM1AMEN_Msk (0x1UL << RCC_SRDAMR_LPTIM1AMEN_Pos) /*!< 0x00000800 */
-#define RCC_SRDAMR_LPTIM1AMEN RCC_SRDAMR_LPTIM1AMEN_Msk /*!< LPTIM1 Autonomous Mode Enable in Stop 0,1,2 Mode */
+#define RCC_SRDAMR_LPTIM1AMEN_Msk (0x1UL << RCC_SRDAMR_LPTIM1AMEN_Pos) /*!< 0x00000800 */
+#define RCC_SRDAMR_LPTIM1AMEN RCC_SRDAMR_LPTIM1AMEN_Msk /*!< LPTIM1 Autonomous Mode Enable in Stop 0,1,2 Mode */
#define RCC_SRDAMR_LPTIM3AMEN_Pos (12U)
-#define RCC_SRDAMR_LPTIM3AMEN_Msk (0x1UL << RCC_SRDAMR_LPTIM3AMEN_Pos) /*!< 0x00001000 */
-#define RCC_SRDAMR_LPTIM3AMEN RCC_SRDAMR_LPTIM3AMEN_Msk /*!< LPTIM3 Autonomous Mode Enable in Stop 0,1,2 Mode */
+#define RCC_SRDAMR_LPTIM3AMEN_Msk (0x1UL << RCC_SRDAMR_LPTIM3AMEN_Pos) /*!< 0x00001000 */
+#define RCC_SRDAMR_LPTIM3AMEN RCC_SRDAMR_LPTIM3AMEN_Msk /*!< LPTIM3 Autonomous Mode Enable in Stop 0,1,2 Mode */
#define RCC_SRDAMR_LPTIM4AMEN_Pos (13U)
-#define RCC_SRDAMR_LPTIM4AMEN_Msk (0x1UL << RCC_SRDAMR_LPTIM4AMEN_Pos) /*!< 0x00002000 */
-#define RCC_SRDAMR_LPTIM4AMEN RCC_SRDAMR_LPTIM4AMEN_Msk /*!< LPTIM4 Autonomous Mode Enable in Stop 0,1,2 Mode */
+#define RCC_SRDAMR_LPTIM4AMEN_Msk (0x1UL << RCC_SRDAMR_LPTIM4AMEN_Pos) /*!< 0x00002000 */
+#define RCC_SRDAMR_LPTIM4AMEN RCC_SRDAMR_LPTIM4AMEN_Msk /*!< LPTIM4 Autonomous Mode Enable in Stop 0,1,2 Mode */
#define RCC_SRDAMR_OPAMPAMEN_Pos (14U)
-#define RCC_SRDAMR_OPAMPAMEN_Msk (0x1UL << RCC_SRDAMR_OPAMPAMEN_Pos) /*!< 0x00004000 */
-#define RCC_SRDAMR_OPAMPAMEN RCC_SRDAMR_OPAMPAMEN_Msk /*!< OPAMP Autonomous Mode Enable in Stop 0,1,2 Mode */
+#define RCC_SRDAMR_OPAMPAMEN_Msk (0x1UL << RCC_SRDAMR_OPAMPAMEN_Pos) /*!< 0x00004000 */
+#define RCC_SRDAMR_OPAMPAMEN RCC_SRDAMR_OPAMPAMEN_Msk /*!< OPAMP Autonomous Mode Enable in Stop 0,1,2 Mode */
#define RCC_SRDAMR_COMPAMEN_Pos (15U)
-#define RCC_SRDAMR_COMPAMEN_Msk (0x1UL << RCC_SRDAMR_COMPAMEN_Pos) /*!< 0x00008000 */
-#define RCC_SRDAMR_COMPAMEN RCC_SRDAMR_COMPAMEN_Msk /*!< COMP Autonomous Mode Enable in Stop 0,1,2 Mode */
+#define RCC_SRDAMR_COMPAMEN_Msk (0x1UL << RCC_SRDAMR_COMPAMEN_Pos) /*!< 0x00008000 */
+#define RCC_SRDAMR_COMPAMEN RCC_SRDAMR_COMPAMEN_Msk /*!< COMP Autonomous Mode Enable in Stop 0,1,2 Mode */
#define RCC_SRDAMR_VREFAMEN_Pos (20U)
-#define RCC_SRDAMR_VREFAMEN_Msk (0x1UL << RCC_SRDAMR_VREFAMEN_Pos) /*!< 0x00100000 */
-#define RCC_SRDAMR_VREFAMEN RCC_SRDAMR_VREFAMEN_Msk /*!< VREFBUF Autonomous Mode Enable in Stop 0,1,2 Mode */
+#define RCC_SRDAMR_VREFAMEN_Msk (0x1UL << RCC_SRDAMR_VREFAMEN_Pos) /*!< 0x00100000 */
+#define RCC_SRDAMR_VREFAMEN RCC_SRDAMR_VREFAMEN_Msk /*!< VREFBUF Autonomous Mode Enable in Stop 0,1,2 Mode */
#define RCC_SRDAMR_RTCAPBAMEN_Pos (21U)
-#define RCC_SRDAMR_RTCAPBAMEN_Msk (0x1UL << RCC_SRDAMR_RTCAPBAMEN_Pos) /*!< 0x00200000 */
-#define RCC_SRDAMR_RTCAPBAMEN RCC_SRDAMR_RTCAPBAMEN_Msk /*!< RTC Autonomous Mode Enable in Stop 0,1,2 Mode */
+#define RCC_SRDAMR_RTCAPBAMEN_Msk (0x1UL << RCC_SRDAMR_RTCAPBAMEN_Pos) /*!< 0x00200000 */
+#define RCC_SRDAMR_RTCAPBAMEN RCC_SRDAMR_RTCAPBAMEN_Msk /*!< RTC Autonomous Mode Enable in Stop 0,1,2 Mode */
#define RCC_SRDAMR_ADC4AMEN_Pos (25U)
-#define RCC_SRDAMR_ADC4AMEN_Msk (0x1UL << RCC_SRDAMR_ADC4AMEN_Pos) /*!< 0x02000000 */
-#define RCC_SRDAMR_ADC4AMEN RCC_SRDAMR_ADC4AMEN_Msk /*!< ADC4 Autonomous Mode Enable in Stop 0,1,2 Mode */
+#define RCC_SRDAMR_ADC4AMEN_Msk (0x1UL << RCC_SRDAMR_ADC4AMEN_Pos) /*!< 0x02000000 */
+#define RCC_SRDAMR_ADC4AMEN RCC_SRDAMR_ADC4AMEN_Msk /*!< ADC4 Autonomous Mode Enable in Stop 0,1,2 Mode */
#define RCC_SRDAMR_LPGPIO1AMEN_Pos (26U)
-#define RCC_SRDAMR_LPGPIO1AMEN_Msk (0x1UL << RCC_SRDAMR_LPGPIO1AMEN_Pos) /*!< 0x04000000 */
-#define RCC_SRDAMR_LPGPIO1AMEN RCC_SRDAMR_LPGPIO1AMEN_Msk /*!< LPGPIO1 Autonomous Mode Enable in Stop 0,1,2 Mode */
+#define RCC_SRDAMR_LPGPIO1AMEN_Msk (0x1UL << RCC_SRDAMR_LPGPIO1AMEN_Pos) /*!< 0x04000000 */
+#define RCC_SRDAMR_LPGPIO1AMEN RCC_SRDAMR_LPGPIO1AMEN_Msk /*!< LPGPIO1 Autonomous Mode Enable in Stop 0,1,2 Mode */
#define RCC_SRDAMR_DAC1AMEN_Pos (27U)
-#define RCC_SRDAMR_DAC1AMEN_Msk (0x1UL << RCC_SRDAMR_DAC1AMEN_Pos) /*!< 0x08000000 */
-#define RCC_SRDAMR_DAC1AMEN RCC_SRDAMR_DAC1AMEN_Msk /*!< DAC1 Autonomous Mode Enable in Stop 0,1,2 Mode */
+#define RCC_SRDAMR_DAC1AMEN_Msk (0x1UL << RCC_SRDAMR_DAC1AMEN_Pos) /*!< 0x08000000 */
+#define RCC_SRDAMR_DAC1AMEN RCC_SRDAMR_DAC1AMEN_Msk /*!< DAC1 Autonomous Mode Enable in Stop 0,1,2 Mode */
#define RCC_SRDAMR_LPDMA1AMEN_Pos (28U)
-#define RCC_SRDAMR_LPDMA1AMEN_Msk (0x1UL << RCC_SRDAMR_LPDMA1AMEN_Pos) /*!< 0x10000000 */
-#define RCC_SRDAMR_LPDMA1AMEN RCC_SRDAMR_LPDMA1AMEN_Msk /*!< LPDMA1 Autonomous Mode Enable in Stop 0,1,2 Mode */
+#define RCC_SRDAMR_LPDMA1AMEN_Msk (0x1UL << RCC_SRDAMR_LPDMA1AMEN_Pos) /*!< 0x10000000 */
+#define RCC_SRDAMR_LPDMA1AMEN RCC_SRDAMR_LPDMA1AMEN_Msk /*!< LPDMA1 Autonomous Mode Enable in Stop 0,1,2 Mode */
#define RCC_SRDAMR_ADF1AMEN_Pos (29U)
-#define RCC_SRDAMR_ADF1AMEN_Msk (0x1UL << RCC_SRDAMR_ADF1AMEN_Pos) /*!< 0x20000000 */
-#define RCC_SRDAMR_ADF1AMEN RCC_SRDAMR_ADF1AMEN_Msk /*!< ADF1 Autonomous Mode Enable in Stop 0,1,2 Mode */
+#define RCC_SRDAMR_ADF1AMEN_Msk (0x1UL << RCC_SRDAMR_ADF1AMEN_Pos) /*!< 0x20000000 */
+#define RCC_SRDAMR_ADF1AMEN RCC_SRDAMR_ADF1AMEN_Msk /*!< ADF1 Autonomous Mode Enable in Stop 0,1,2 Mode */
#define RCC_SRDAMR_SRAM4AMEN_Pos (31U)
-#define RCC_SRDAMR_SRAM4AMEN_Msk (0x1UL << RCC_SRDAMR_SRAM4AMEN_Pos) /*!< 0x80000000 */
-#define RCC_SRDAMR_SRAM4AMEN RCC_SRDAMR_SRAM4AMEN_Msk /*!< SRAM4 Autonomous Mode Enable in Stop 0,1,2 Mode */
+#define RCC_SRDAMR_SRAM4AMEN_Msk (0x1UL << RCC_SRDAMR_SRAM4AMEN_Pos) /*!< 0x80000000 */
+#define RCC_SRDAMR_SRAM4AMEN RCC_SRDAMR_SRAM4AMEN_Msk /*!< SRAM4 Autonomous Mode Enable in Stop 0,1,2 Mode */
/******************** Bit definition for RCC_CCIPR1 register ******************/
#define RCC_CCIPR1_USART1SEL_Pos (0U)
-#define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003 */
-#define RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk /*!< USART1SEL[1:0]: bits (USART1 Kernel Clock Source Selection) */
-#define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001 */
-#define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002 */
+#define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk /*!< USART1SEL[1:0]: bits (USART1 Kernel Clock Source Selection) */
+#define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002 */
#define RCC_CCIPR1_USART2SEL_Pos (2U)
-#define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C */
-#define RCC_CCIPR1_USART2SEL RCC_CCIPR1_USART2SEL_Msk /*!< USART2SEL[1:0]: bits (USART2 Kernel Clock Source Selection) */
-#define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004 */
-#define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008 */
+#define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR1_USART2SEL RCC_CCIPR1_USART2SEL_Msk /*!< USART2SEL[1:0]: bits (USART2 Kernel Clock Source Selection) */
+#define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008 */
#define RCC_CCIPR1_USART3SEL_Pos (4U)
-#define RCC_CCIPR1_USART3SEL_Msk (0x3UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000030 */
-#define RCC_CCIPR1_USART3SEL RCC_CCIPR1_USART3SEL_Msk /*!< USART3SEL[1:0]: bits (USART3 Kernel Clock Source Selection) */
-#define RCC_CCIPR1_USART3SEL_0 (0x1UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000010 */
-#define RCC_CCIPR1_USART3SEL_1 (0x2UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000020 */
+#define RCC_CCIPR1_USART3SEL_Msk (0x3UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000030 */
+#define RCC_CCIPR1_USART3SEL RCC_CCIPR1_USART3SEL_Msk /*!< USART3SEL[1:0]: bits (USART3 Kernel Clock Source Selection) */
+#define RCC_CCIPR1_USART3SEL_0 (0x1UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000010 */
+#define RCC_CCIPR1_USART3SEL_1 (0x2UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000020 */
#define RCC_CCIPR1_UART4SEL_Pos (6U)
-#define RCC_CCIPR1_UART4SEL_Msk (0x3UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x000000C0 */
-#define RCC_CCIPR1_UART4SEL RCC_CCIPR1_UART4SEL_Msk /*!< UART4SEL[1:0]: bits (UART4 Kernel Clock Source Selection) */
-#define RCC_CCIPR1_UART4SEL_0 (0x1UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000040 */
-#define RCC_CCIPR1_UART4SEL_1 (0x2UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000080 */
+#define RCC_CCIPR1_UART4SEL_Msk (0x3UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x000000C0 */
+#define RCC_CCIPR1_UART4SEL RCC_CCIPR1_UART4SEL_Msk /*!< UART4SEL[1:0]: bits (UART4 Kernel Clock Source Selection) */
+#define RCC_CCIPR1_UART4SEL_0 (0x1UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000040 */
+#define RCC_CCIPR1_UART4SEL_1 (0x2UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000080 */
#define RCC_CCIPR1_UART5SEL_Pos (8U)
-#define RCC_CCIPR1_UART5SEL_Msk (0x3UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000300 */
-#define RCC_CCIPR1_UART5SEL RCC_CCIPR1_UART5SEL_Msk /*!< UART5SEL[1:0]: bits (UART5 Kernel Clock Source Selection) */
-#define RCC_CCIPR1_UART5SEL_0 (0x1UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000100 */
-#define RCC_CCIPR1_UART5SEL_1 (0x2UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000200 */
+#define RCC_CCIPR1_UART5SEL_Msk (0x3UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000300 */
+#define RCC_CCIPR1_UART5SEL RCC_CCIPR1_UART5SEL_Msk /*!< UART5SEL[1:0]: bits (UART5 Kernel Clock Source Selection) */
+#define RCC_CCIPR1_UART5SEL_0 (0x1UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000100 */
+#define RCC_CCIPR1_UART5SEL_1 (0x2UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR1_I2C1SEL_Pos (10U)
-#define RCC_CCIPR1_I2C1SEL_Msk (0x3UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000C00 */
-#define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk /*!< I2C1SEL[1:0]: bits (I2C1 Kernel Clock Source Selection) */
-#define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000400 */
-#define RCC_CCIPR1_I2C1SEL_1 (0x2UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000800 */
+#define RCC_CCIPR1_I2C1SEL_Msk (0x3UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk /*!< I2C1SEL[1:0]: bits (I2C1 Kernel Clock Source Selection) */
+#define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000400 */
+#define RCC_CCIPR1_I2C1SEL_1 (0x2UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000800 */
#define RCC_CCIPR1_I2C2SEL_Pos (12U)
-#define RCC_CCIPR1_I2C2SEL_Msk (0x3UL << RCC_CCIPR1_I2C2SEL_Pos) /*!< 0x00003000 */
-#define RCC_CCIPR1_I2C2SEL RCC_CCIPR1_I2C2SEL_Msk /*!< I2C2SEL[1:0]: bits (I2C2 Kernel Clock Source Selection) */
-#define RCC_CCIPR1_I2C2SEL_0 (0x1UL << RCC_CCIPR1_I2C2SEL_Pos) /*!< 0x00001000 */
-#define RCC_CCIPR1_I2C2SEL_1 (0x2UL << RCC_CCIPR1_I2C2SEL_Pos) /*!< 0x00002000 */
+#define RCC_CCIPR1_I2C2SEL_Msk (0x3UL << RCC_CCIPR1_I2C2SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR1_I2C2SEL RCC_CCIPR1_I2C2SEL_Msk /*!< I2C2SEL[1:0]: bits (I2C2 Kernel Clock Source Selection) */
+#define RCC_CCIPR1_I2C2SEL_0 (0x1UL << RCC_CCIPR1_I2C2SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR1_I2C2SEL_1 (0x2UL << RCC_CCIPR1_I2C2SEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR1_I2C4SEL_Pos (14U)
-#define RCC_CCIPR1_I2C4SEL_Msk (0x3UL << RCC_CCIPR1_I2C4SEL_Pos) /*!< 0x0000C000 */
-#define RCC_CCIPR1_I2C4SEL RCC_CCIPR1_I2C4SEL_Msk /*!< I2C4SEL[1:0]: bits (I2C4 Kernel Clock Source Selection) */
-#define RCC_CCIPR1_I2C4SEL_0 (0x1UL << RCC_CCIPR1_I2C4SEL_Pos) /*!< 0x00004000 */
-#define RCC_CCIPR1_I2C4SEL_1 (0x2UL << RCC_CCIPR1_I2C4SEL_Pos) /*!< 0x00008000 */
+#define RCC_CCIPR1_I2C4SEL_Msk (0x3UL << RCC_CCIPR1_I2C4SEL_Pos) /*!< 0x0000C000 */
+#define RCC_CCIPR1_I2C4SEL RCC_CCIPR1_I2C4SEL_Msk /*!< I2C4SEL[1:0]: bits (I2C4 Kernel Clock Source Selection) */
+#define RCC_CCIPR1_I2C4SEL_0 (0x1UL << RCC_CCIPR1_I2C4SEL_Pos) /*!< 0x00004000 */
+#define RCC_CCIPR1_I2C4SEL_1 (0x2UL << RCC_CCIPR1_I2C4SEL_Pos) /*!< 0x00008000 */
#define RCC_CCIPR1_SPI2SEL_Pos (16U)
-#define RCC_CCIPR1_SPI2SEL_Msk (0x3UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00030000 */
-#define RCC_CCIPR1_SPI2SEL RCC_CCIPR1_SPI2SEL_Msk /*!< SPI2SEL[1:0]: bits (SPI2 Kernel Clock Source Selection) */
-#define RCC_CCIPR1_SPI2SEL_0 (0x1UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00010000 */
-#define RCC_CCIPR1_SPI2SEL_1 (0x2UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00020000 */
+#define RCC_CCIPR1_SPI2SEL_Msk (0x3UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00030000 */
+#define RCC_CCIPR1_SPI2SEL RCC_CCIPR1_SPI2SEL_Msk /*!< SPI2SEL[1:0]: bits (SPI2 Kernel Clock Source Selection) */
+#define RCC_CCIPR1_SPI2SEL_0 (0x1UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00010000 */
+#define RCC_CCIPR1_SPI2SEL_1 (0x2UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00020000 */
#define RCC_CCIPR1_LPTIM2SEL_Pos (18U)
-#define RCC_CCIPR1_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x000C0000 */
-#define RCC_CCIPR1_LPTIM2SEL RCC_CCIPR1_LPTIM2SEL_Msk /*!< LPTIM2SEL[1:0]: bits (Low-power Timer 2 Kernel Clock Source Selection) */
-#define RCC_CCIPR1_LPTIM2SEL_0 (0x1UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x00040000 */
-#define RCC_CCIPR1_LPTIM2SEL_1 (0x2UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x00080000 */
+#define RCC_CCIPR1_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR1_LPTIM2SEL RCC_CCIPR1_LPTIM2SEL_Msk /*!< LPTIM2SEL[1:0]: bits (Low-power Timer 2 Kernel Clock Source Selection) */
+#define RCC_CCIPR1_LPTIM2SEL_0 (0x1UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR1_LPTIM2SEL_1 (0x2UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x00080000 */
#define RCC_CCIPR1_SPI1SEL_Pos (20U)
-#define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00300000 */
-#define RCC_CCIPR1_SPI1SEL RCC_CCIPR1_SPI1SEL_Msk /*!< SPI1SEL[1:0]: bits (SPI1 Kernel Clock Source Selection) */
-#define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00100000 */
-#define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00200000 */
+#define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00300000 */
+#define RCC_CCIPR1_SPI1SEL RCC_CCIPR1_SPI1SEL_Msk /*!< SPI1SEL[1:0]: bits (SPI1 Kernel Clock Source Selection) */
+#define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00100000 */
+#define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00200000 */
#define RCC_CCIPR1_SYSTICKSEL_Pos (22U)
-#define RCC_CCIPR1_SYSTICKSEL_Msk (0x3UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00C00000 */
-#define RCC_CCIPR1_SYSTICKSEL RCC_CCIPR1_SYSTICKSEL_Msk /*!< SYSTICKSEL[1:0]: bits (SYSTICK Clock Source Selection) */
-#define RCC_CCIPR1_SYSTICKSEL_0 (0x1UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00400000 */
-#define RCC_CCIPR1_SYSTICKSEL_1 (0x2UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00800000 */
+#define RCC_CCIPR1_SYSTICKSEL_Msk (0x3UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00C00000 */
+#define RCC_CCIPR1_SYSTICKSEL RCC_CCIPR1_SYSTICKSEL_Msk /*!< SYSTICKSEL[1:0]: bits (SYSTICK Clock Source Selection) */
+#define RCC_CCIPR1_SYSTICKSEL_0 (0x1UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00400000 */
+#define RCC_CCIPR1_SYSTICKSEL_1 (0x2UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00800000 */
#define RCC_CCIPR1_FDCANSEL_Pos (24U)
-#define RCC_CCIPR1_FDCANSEL_Msk (0x3UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x03000000 */
-#define RCC_CCIPR1_FDCANSEL RCC_CCIPR1_FDCANSEL_Msk /*!< FDCAN1SEL[1:0]: bits (FDCAN1 Kernel Clock Source Selection) */
-#define RCC_CCIPR1_FDCANSEL_0 (0x1UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x01000000 */
-#define RCC_CCIPR1_FDCANSEL_1 (0x2UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x02000000 */
-#define RCC_CCIPR1_CLK48MSEL_Pos (26U)
-#define RCC_CCIPR1_CLK48MSEL_Msk (0x3UL << RCC_CCIPR1_CLK48MSEL_Pos) /*!< 0x0C000000 */
-#define RCC_CCIPR1_CLK48MSEL RCC_CCIPR1_CLK48MSEL_Msk /*!< CLK48MSEL[1:0]: bits (48 MHz Clock Source Selection) */
-#define RCC_CCIPR1_CLK48MSEL_0 (0x1UL << RCC_CCIPR1_CLK48MSEL_Pos) /*!< 0x04000000 */
-#define RCC_CCIPR1_CLK48MSEL_1 (0x2UL << RCC_CCIPR1_CLK48MSEL_Pos) /*!< 0x08000000 */
+#define RCC_CCIPR1_FDCANSEL_Msk (0x3UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x03000000 */
+#define RCC_CCIPR1_FDCANSEL RCC_CCIPR1_FDCANSEL_Msk /*!< FDCAN1SEL[1:0]: bits (FDCAN1 Kernel Clock Source Selection) */
+#define RCC_CCIPR1_FDCANSEL_0 (0x1UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x01000000 */
+#define RCC_CCIPR1_FDCANSEL_1 (0x2UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x02000000 */
+#define RCC_CCIPR1_ICLKSEL_Pos (26U)
+#define RCC_CCIPR1_ICLKSEL_Msk (0x3UL << RCC_CCIPR1_ICLKSEL_Pos) /*!< 0x0C000000 */
+#define RCC_CCIPR1_ICLKSEL RCC_CCIPR1_ICLKSEL_Msk /*!< ICLKSEL[1:0]: bits (48 MHz Clock Source Selection) */
+#define RCC_CCIPR1_ICLKSEL_0 (0x1UL << RCC_CCIPR1_ICLKSEL_Pos) /*!< 0x04000000 */
+#define RCC_CCIPR1_ICLKSEL_1 (0x2UL << RCC_CCIPR1_ICLKSEL_Pos) /*!< 0x08000000 */
#define RCC_CCIPR1_TIMICSEL_Pos (29U)
-#define RCC_CCIPR1_TIMICSEL_Msk (0x7UL << RCC_CCIPR1_TIMICSEL_Pos) /*!< 0xE0000000 */
-#define RCC_CCIPR1_TIMICSEL RCC_CCIPR1_TIMICSEL_Msk /*!< TIMICSEL[2:0]: bits (Clocks Sources for TIM16,TIM17 and LPTIM2 Internal Input Capture) */
-#define RCC_CCIPR1_TIMICSEL_0 (0x1UL << RCC_CCIPR1_TIMICSEL_Pos) /*!< 0x20000000 */
-#define RCC_CCIPR1_TIMICSEL_1 (0x2UL << RCC_CCIPR1_TIMICSEL_Pos) /*!< 0x40000000 */
-#define RCC_CCIPR1_TIMICSEL_2 (0x4UL << RCC_CCIPR1_TIMICSEL_Pos) /*!< 0x80000000 */
+#define RCC_CCIPR1_TIMICSEL_Msk (0x7UL << RCC_CCIPR1_TIMICSEL_Pos) /*!< 0xE0000000 */
+#define RCC_CCIPR1_TIMICSEL RCC_CCIPR1_TIMICSEL_Msk /*!< TIMICSEL[2:0]: bits (Clocks Sources for TIM16,TIM17 and LPTIM2 Internal Input Capture) */
+#define RCC_CCIPR1_TIMICSEL_0 (0x1UL << RCC_CCIPR1_TIMICSEL_Pos) /*!< 0x20000000 */
+#define RCC_CCIPR1_TIMICSEL_1 (0x2UL << RCC_CCIPR1_TIMICSEL_Pos) /*!< 0x40000000 */
+#define RCC_CCIPR1_TIMICSEL_2 (0x4UL << RCC_CCIPR1_TIMICSEL_Pos) /*!< 0x80000000 */
/******************** Bit definition for RCC_CCIPR2 register ******************/
#define RCC_CCIPR2_MDF1SEL_Pos (0U)
-#define RCC_CCIPR2_MDF1SEL_Msk (0x7UL << RCC_CCIPR2_MDF1SEL_Pos) /*!< 0x00000007 */
-#define RCC_CCIPR2_MDF1SEL RCC_CCIPR2_MDF1SEL_Msk /*!< MDF1SEL[2:0]: bits (MDF1 Kernel Clock Source Selection) */
-#define RCC_CCIPR2_MDF1SEL_0 (0x1UL << RCC_CCIPR2_MDF1SEL_Pos) /*!< 0x00000001 */
-#define RCC_CCIPR2_MDF1SEL_1 (0x2UL << RCC_CCIPR2_MDF1SEL_Pos) /*!< 0x00000002 */
-#define RCC_CCIPR2_MDF1SEL_2 (0x4UL << RCC_CCIPR2_MDF1SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR2_MDF1SEL_Msk (0x7UL << RCC_CCIPR2_MDF1SEL_Pos) /*!< 0x00000007 */
+#define RCC_CCIPR2_MDF1SEL RCC_CCIPR2_MDF1SEL_Msk /*!< MDF1SEL[2:0]: bits (MDF1 Kernel Clock Source Selection) */
+#define RCC_CCIPR2_MDF1SEL_0 (0x1UL << RCC_CCIPR2_MDF1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR2_MDF1SEL_1 (0x2UL << RCC_CCIPR2_MDF1SEL_Pos) /*!< 0x00000002 */
+#define RCC_CCIPR2_MDF1SEL_2 (0x4UL << RCC_CCIPR2_MDF1SEL_Pos) /*!< 0x00000004 */
#define RCC_CCIPR2_SAI1SEL_Pos (5U)
-#define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */
-#define RCC_CCIPR2_SAI1SEL RCC_CCIPR2_SAI1SEL_Msk /*!< SAI1SEL[2:0]: bits (SAI1 Kernel Clock Source Selection) */
-#define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */
-#define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */
-#define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */
+#define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */
+#define RCC_CCIPR2_SAI1SEL RCC_CCIPR2_SAI1SEL_Msk /*!< SAI1SEL[2:0]: bits (SAI1 Kernel Clock Source Selection) */
+#define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */
+#define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */
+#define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */
#define RCC_CCIPR2_SAI2SEL_Pos (8U)
-#define RCC_CCIPR2_SAI2SEL_Msk (0x7UL << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000700 */
-#define RCC_CCIPR2_SAI2SEL RCC_CCIPR2_SAI2SEL_Msk /*!< SAI2SEL[2:0]: bits (SAI2 Kernel Clock Source Selection) */
-#define RCC_CCIPR2_SAI2SEL_0 (0x1UL << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000100 */
-#define RCC_CCIPR2_SAI2SEL_1 (0x2UL << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000200 */
-#define RCC_CCIPR2_SAI2SEL_2 (0x4UL << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000400 */
+#define RCC_CCIPR2_SAI2SEL_Msk (0x7UL << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000700 */
+#define RCC_CCIPR2_SAI2SEL RCC_CCIPR2_SAI2SEL_Msk /*!< SAI2SEL[2:0]: bits (SAI2 Kernel Clock Source Selection) */
+#define RCC_CCIPR2_SAI2SEL_0 (0x1UL << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000100 */
+#define RCC_CCIPR2_SAI2SEL_1 (0x2UL << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000200 */
+#define RCC_CCIPR2_SAI2SEL_2 (0x4UL << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000400 */
#define RCC_CCIPR2_SAESSEL_Pos (11U)
-#define RCC_CCIPR2_SAESSEL_Msk (0x1UL << RCC_CCIPR2_SAESSEL_Pos) /*!< 0x00004000 */
-#define RCC_CCIPR2_SAESSEL RCC_CCIPR2_SAESSEL_Msk /*!< SAES Kernel Clock Source Selection */
+#define RCC_CCIPR2_SAESSEL_Msk (0x1UL << RCC_CCIPR2_SAESSEL_Pos) /*!< 0x00004000 */
+#define RCC_CCIPR2_SAESSEL RCC_CCIPR2_SAESSEL_Msk /*!< SAES Kernel Clock Source Selection */
#define RCC_CCIPR2_RNGSEL_Pos (12U)
-#define RCC_CCIPR2_RNGSEL_Msk (0x3UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00300000 */
-#define RCC_CCIPR2_RNGSEL RCC_CCIPR2_RNGSEL_Msk /*!< RNGSEL[1:0]: bits (RNGSEL Kernel Clock Source Selection) */
-#define RCC_CCIPR2_RNGSEL_0 (0x1UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00100000 */
-#define RCC_CCIPR2_RNGSEL_1 (0x2UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00200000 */
+#define RCC_CCIPR2_RNGSEL_Msk (0x3UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00300000 */
+#define RCC_CCIPR2_RNGSEL RCC_CCIPR2_RNGSEL_Msk /*!< RNGSEL[1:0]: bits (RNGSEL Kernel Clock Source Selection) */
+#define RCC_CCIPR2_RNGSEL_0 (0x1UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00100000 */
+#define RCC_CCIPR2_RNGSEL_1 (0x2UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00200000 */
#define RCC_CCIPR2_SDMMCSEL_Pos (14U)
-#define RCC_CCIPR2_SDMMCSEL_Msk (0x1UL << RCC_CCIPR2_SDMMCSEL_Pos) /*!< 0x00004000 */
-#define RCC_CCIPR2_SDMMCSEL RCC_CCIPR2_SDMMCSEL_Msk /*!< SDMMC1 Kernel Clock Source Selection */
+#define RCC_CCIPR2_SDMMCSEL_Msk (0x1UL << RCC_CCIPR2_SDMMCSEL_Pos) /*!< 0x00004000 */
+#define RCC_CCIPR2_SDMMCSEL RCC_CCIPR2_SDMMCSEL_Msk /*!< SDMMC1 Kernel Clock Source Selection */
#define RCC_CCIPR2_OCTOSPISEL_Pos (20U)
-#define RCC_CCIPR2_OCTOSPISEL_Msk (0x3UL << RCC_CCIPR2_OCTOSPISEL_Pos) /*!< 0x00300000 */
-#define RCC_CCIPR2_OCTOSPISEL RCC_CCIPR2_OCTOSPISEL_Msk /*!< OCTOSPISEL[1:0]: bits (OCTOSPI1 and OCTOSPI2 Kernel Clock Source Selection) */
-#define RCC_CCIPR2_OCTOSPISEL_0 (0x1UL << RCC_CCIPR2_OCTOSPISEL_Pos) /*!< 0x00100000 */
-#define RCC_CCIPR2_OCTOSPISEL_1 (0x2UL << RCC_CCIPR2_OCTOSPISEL_Pos) /*!< 0x00200000 */
+#define RCC_CCIPR2_OCTOSPISEL_Msk (0x3UL << RCC_CCIPR2_OCTOSPISEL_Pos) /*!< 0x00300000 */
+#define RCC_CCIPR2_OCTOSPISEL RCC_CCIPR2_OCTOSPISEL_Msk /*!< OCTOSPISEL[1:0]: bits (OCTOSPI1 and OCTOSPI2 Kernel Clock Source Selection) */
+#define RCC_CCIPR2_OCTOSPISEL_0 (0x1UL << RCC_CCIPR2_OCTOSPISEL_Pos) /*!< 0x00100000 */
+#define RCC_CCIPR2_OCTOSPISEL_1 (0x2UL << RCC_CCIPR2_OCTOSPISEL_Pos) /*!< 0x00200000 */
/******************** Bit definition for RCC_CCIPR3 register ***************/
#define RCC_CCIPR3_LPUART1SEL_Pos (0U)
-#define RCC_CCIPR3_LPUART1SEL_Msk (0x7UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000007 */
-#define RCC_CCIPR3_LPUART1SEL RCC_CCIPR3_LPUART1SEL_Msk /*!< LPUART1SEL[2:0]: bits (LPUART1 Kernel Clock Source Selection) */
-#define RCC_CCIPR3_LPUART1SEL_0 (0x1UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000001 */
-#define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */
-#define RCC_CCIPR3_LPUART1SEL_2 (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR3_LPUART1SEL_Msk (0x7UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000007 */
+#define RCC_CCIPR3_LPUART1SEL RCC_CCIPR3_LPUART1SEL_Msk /*!< LPUART1SEL[2:0]: bits (LPUART1 Kernel Clock Source Selection) */
+#define RCC_CCIPR3_LPUART1SEL_0 (0x1UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */
+#define RCC_CCIPR3_LPUART1SEL_2 (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000004 */
#define RCC_CCIPR3_SPI3SEL_Pos (3U)
-#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */
-#define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk /*!< SPI3SEL[1:0]: bits (SPI3 Kernel Clock Source Selection) */
-#define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */
-#define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */
+#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */
+#define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk /*!< SPI3SEL[1:0]: bits (SPI3 Kernel Clock Source Selection) */
+#define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */
+#define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */
#define RCC_CCIPR3_I2C3SEL_Pos (6U)
-#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000300 */
-#define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk /*!< I2C3SEL[1:0]: bits (I2C3 Kernel Clock Source Selection) */
-#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000100 */
-#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000200 */
+#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000300 */
+#define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk /*!< I2C3SEL[1:0]: bits (I2C3 Kernel Clock Source Selection) */
+#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000100 */
+#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR3_LPTIM34SEL_Pos (8U)
-#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x0000E000 */
-#define RCC_CCIPR3_LPTIM34SEL RCC_CCIPR3_LPTIM34SEL_Msk /*!< LPTIM34SEL[1:0]: bits (LPTIM3 and LPTIM4 Kernel Clock Source Selection) */
-#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00002000 */
-#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00004000 */
+#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x0000E000 */
+#define RCC_CCIPR3_LPTIM34SEL RCC_CCIPR3_LPTIM34SEL_Msk /*!< LPTIM34SEL[1:0]: bits (LPTIM3 and LPTIM4 Kernel Clock Source Selection) */
+#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00002000 */
+#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR3_LPTIM1SEL_Pos (10U)
-#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x0000E000 */
-#define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0]: bits (LPTIM1 Kernel Clock Source Selection) */
-#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00002000 */
-#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00004000 */
+#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x0000E000 */
+#define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0]: bits (LPTIM1 Kernel Clock Source Selection) */
+#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00002000 */
+#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR3_ADCDACSEL_Pos (12U)
-#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00030000 */
-#define RCC_CCIPR3_ADCDACSEL RCC_CCIPR3_ADCDACSEL_Msk /*!< ADCDACSEL[2:0]: bits (ADC1, ADC4 and DAC1 Kernel Clock Source Selection) */
-#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00010000 */
-#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00020000 */
-#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00030000 */
+#define RCC_CCIPR3_ADCDACSEL RCC_CCIPR3_ADCDACSEL_Msk /*!< ADCDACSEL[2:0]: bits (ADC1, ADC4 and DAC1 Kernel Clock Source Selection) */
+#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00010000 */
+#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00020000 */
+#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00040000 */
#define RCC_CCIPR3_DAC1SEL_Pos (15U)
-#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00300000 */
-#define RCC_CCIPR3_DAC1SEL RCC_CCIPR3_DAC1SEL_Msk /*!< DAC1 Sample & Hold Clock Source Selection */
+#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00300000 */
+#define RCC_CCIPR3_DAC1SEL RCC_CCIPR3_DAC1SEL_Msk /*!< DAC1 Sample & Hold Clock Source Selection */
#define RCC_CCIPR3_ADF1SEL_Pos (16U)
#define RCC_CCIPR3_ADF1SEL_Msk (0x7UL << RCC_CCIPR3_ADF1SEL_Pos) /*!< 0x00070000 */
#define RCC_CCIPR3_ADF1SEL RCC_CCIPR3_ADF1SEL_Msk /*!< ADF1SEL[2:0]: bits (ADF1 Kernel Clock Source Selection) */
@@ -16944,9 +17440,9 @@
#define RCC_SECCFGR_PLL3SEC_Pos (9U)
#define RCC_SECCFGR_PLL3SEC_Msk (0x1UL << RCC_SECCFGR_PLL3SEC_Pos) /*!< 0x00000200 */
#define RCC_SECCFGR_PLL3SEC RCC_SECCFGR_PLL3SEC_Msk /*!< PLL3 Clock Configuration and Status Bits Security */
-#define RCC_SECCFGR_CLK48MSEC_Pos (10U)
-#define RCC_SECCFGR_CLK48MSEC_Msk (0x1UL << RCC_SECCFGR_CLK48MSEC_Pos) /*!< 0x00000400 */
-#define RCC_SECCFGR_CLK48MSEC RCC_SECCFGR_CLK48MSEC_Msk /*!< 48 MHz Clock Source Selection Security */
+#define RCC_SECCFGR_ICLKSEC_Pos (10U)
+#define RCC_SECCFGR_ICLKSEC_Msk (0x1UL << RCC_SECCFGR_ICLKSEC_Pos) /*!< 0x00000400 */
+#define RCC_SECCFGR_ICLKSEC RCC_SECCFGR_ICLKSEC_Msk /*!< 48 MHz Clock Source Selection Security */
#define RCC_SECCFGR_HSI48SEC_Pos (11U)
#define RCC_SECCFGR_HSI48SEC_Msk (0x1UL << RCC_SECCFGR_HSI48SEC_Pos) /*!< 0x00000800 */
#define RCC_SECCFGR_HSI48SEC RCC_SECCFGR_HSI48SEC_Msk /*!< HSI48 Clock Configuration and Status Bits Security */
@@ -17869,11 +18365,12 @@
#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */
#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */
#define TAMP_ATCR1_ATCKSEL_Pos (16U)
-#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */
+#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */
#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk
#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */
#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */
#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */
+#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */
#define TAMP_ATCR1_ATPER_Pos (24U)
#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */
#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk
@@ -19394,7 +19891,7 @@
/****************** Bit definition for SYSCFG_CSLCKR register ***************/
#define SYSCFG_CSLCKR_LOCKSVTAIRCR_Pos (0U)
#define SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk (0x1UL << SYSCFG_CSLCKR_LOCKSVTAIRCR_Pos) /*!< 0x00000001 */
-#define SYSCFG_CSLCKR_LOCKSVTAIRCR SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vectror table address, handling of system faults */
+#define SYSCFG_CSLCKR_LOCKSVTAIRCR SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vector table address, handling of system faults */
#define SYSCFG_CSLCKR_LOCKSMPU_Pos (1U)
#define SYSCFG_CSLCKR_LOCKSMPU_Msk (0x1UL << SYSCFG_CSLCKR_LOCKSMPU_Pos) /*!< 0x00000002 */
#define SYSCFG_CSLCKR_LOCKSMPU SYSCFG_CSLCKR_LOCKSMPU_Msk /*!< Disable changes to the secure MPU registers writes by SW or debug agent */
@@ -19519,7 +20016,7 @@
/******* Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers *****/
/******* Bits definition for TZIC _IERx/_SRx/_IFCRx registers ********/
-/*************** Bits definition for register x=1 (TZSC1) *************/
+/*************** Bits definition for register x=1 (GTZC1) *************/
#define GTZC_CFGR1_TIM2_Pos (0U)
#define GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos)
#define GTZC_CFGR1_TIM3_Pos (1U)
@@ -19561,7 +20058,7 @@
#define GTZC_CFGR1_UCPD1_Pos (19U)
#define GTZC_CFGR1_UCPD1_Msk (0x01UL << GTZC_CFGR1_UCPD1_Pos)
-/*************** Bits definition for register x=2 (TZSC1) *************/
+/*************** Bits definition for register x=2 (GTZC1) *************/
#define GTZC_CFGR2_TIM1_Pos (0U)
#define GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos)
#define GTZC_CFGR2_SPI1_Pos (1U)
@@ -19581,7 +20078,7 @@
#define GTZC_CFGR2_SAI2_Pos (8U)
#define GTZC_CFGR2_SAI2_Msk (0x01UL << GTZC_CFGR2_SAI2_Pos)
-/*************** Bits definition for register x=3 (TZSC1) *************/
+/*************** Bits definition for register x=3 (GTZC1) *************/
#define GTZC_CFGR3_MDF1_Pos (0U)
#define GTZC_CFGR3_MDF1_Msk (0x01UL << GTZC_CFGR3_MDF1_Pos)
#define GTZC_CFGR3_CORDIC_Pos (1U)
@@ -19629,7 +20126,7 @@
#define GTZC_CFGR3_RAMCFG_Pos (22U)
#define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos)
-/*************** Bits definition for register x=4 (TZSC1) *************/
+/*************** Bits definition for register x=4 (GTZC1) *************/
#define GTZC_CFGR4_GPDMA1_Pos (0U)
#define GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos)
#define GTZC_CFGR4_FLASH_REG_Pos (1U)
@@ -19665,7 +20162,7 @@
#define GTZC_CFGR4_MPCBB3_REG_Pos (29U)
#define GTZC_CFGR4_MPCBB3_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB3_REG_Pos)
-/*************** Bits definition for register x=1 (TZSC2) *************/
+/*************** Bits definition for register x=1 (GTZC2) *************/
#define GTZC_CFGR1_SPI3_Pos (0U)
#define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
#define GTZC_CFGR1_LPUART1_Pos (1U)
@@ -19691,7 +20188,7 @@
#define GTZC_CFGR1_ADF1_Pos (12U)
#define GTZC_CFGR1_ADF1_Msk (0x01UL << GTZC_CFGR1_ADF1_Pos)
-/*************** Bits definition for register x=2 (TZSC2) *************/
+/*************** Bits definition for register x=2 (GTZC2) *************/
#define GTZC_CFGR2_SYSCFG_Pos (0U)
#define GTZC_CFGR2_SYSCFG_Msk (0x01UL << GTZC_CFGR2_SYSCFG_Pos)
#define GTZC_CFGR2_RTC_Pos (1U)
@@ -20726,6 +21223,20 @@
#define UCPD_CFG2_RXAFILTEN_Msk (0x1UL << UCPD_CFG2_RXAFILTEN_Pos) /*!< 0x00000100 */
#define UCPD_CFG2_RXAFILTEN UCPD_CFG2_RXAFILTEN_Msk /*!< RX Analog Filter enable */
+/******************** Bits definition for UCPD_CFG3 register *******************/
+#define UCPD_CFG3_TRIM_CC1_RD_Pos (0U)
+#define UCPD_CFG3_TRIM_CC1_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RD_Pos) /*!< 0x0000000F */
+#define UCPD_CFG3_TRIM_CC1_RD UCPD_CFG3_TRIM_CC1_RD_Msk /*!< SW trim value for RD resistor (CC1) */
+#define UCPD_CFG3_TRIM_CC1_RP_Pos (9U)
+#define UCPD_CFG3_TRIM_CC1_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RP_Pos) /*!< 0x00001E00 */
+#define UCPD_CFG3_TRIM_CC1_RP UCPD_CFG3_TRIM_CC1_RP_Msk /*!< SW trim value for RP current sources (CC1) */
+#define UCPD_CFG3_TRIM_CC2_RD_Pos (16U)
+#define UCPD_CFG3_TRIM_CC2_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RD_Pos) /*!< 0x000F0000 */
+#define UCPD_CFG3_TRIM_CC2_RD UCPD_CFG3_TRIM_CC2_RD_Msk /*!< SW trim value for RD resistor (CC2) */
+#define UCPD_CFG3_TRIM_CC2_RP_Pos (25U)
+#define UCPD_CFG3_TRIM_CC2_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RP_Pos) /*!< 0x1E000000 */
+#define UCPD_CFG3_TRIM_CC2_RP UCPD_CFG3_TRIM_CC2_RP_Msk /*!< SW trim value for RP current sources (CC2) */
+
/******************** Bits definition for UCPD_CR register ********************/
#define UCPD_CR_TXMODE_Pos (0U)
#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */
@@ -22294,6 +22805,7 @@
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
/* */
/******************************************************************************/
+#define USART_DMAREQUESTS_SW_WA
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_UE_Pos (0U)
#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
@@ -23836,7 +24348,6 @@
*/
/******************************* ADC Instances ********************************/
-/******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS)|| \
((INSTANCE) == ADC1_S) || \
((INSTANCE) == ADC4_NS)|| \
@@ -23864,7 +24375,8 @@
((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S))
/******************** COMP Instances with window mode capability **************/
-#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S))
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \
+ ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S))
/******************************* CORDIC Instances *****************************/
#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S))
@@ -24050,14 +24562,19 @@
#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S))
/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \
- ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \
- ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S))
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \
+ ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \
+ ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S))
#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S))
-#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \
- ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S))
+#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \
+ ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S))
+
+#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \
+ ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S))
+
+#define IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S))
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
@@ -24105,6 +24622,8 @@
/****************** TIM Instances : supporting 32 bits counter ****************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S))
/****************** TIM Instances : supporting the break function *************/
@@ -24171,6 +24690,10 @@
/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
@@ -24303,8 +24826,7 @@
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
- ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
- ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
@@ -24365,8 +24887,7 @@
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
- ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
- ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
@@ -24408,7 +24929,10 @@
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
- ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
+ ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
+ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
/****************** TIM Instances : remapping capability **********************/
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
@@ -24416,10 +24940,7 @@
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
- ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
- ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
- ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
- ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
diff --git a/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u5xx.h b/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u5xx.h
index d1a8db2..2e7ed58 100644
--- a/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u5xx.h
+++ b/platform/ext/target/stm/common/stm32u5xx/Device/Include/stm32u5xx.h
@@ -8,21 +8,21 @@
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32U5xx device used in the target application
- * - To use or not the peripheralÂ’s drivers in application code(i.e.
- * code will be based on direct access to peripheralÂ’s registers
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
+ * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -59,13 +59,22 @@
#if !defined (STM32U575xx) && !defined (STM32U585xx) \
&& !defined (STM32U595xx) && !defined (STM32U599xx) \
- && !defined (STM32U5A5xx) && !defined (STM32U5A9xx)
- /* #define STM32U575xx */ /*!< STM32U575CIU6 STM32U575CIT6 STM32U575RIT6 STM32U575VIT6 STM32U575ZIT6 STM32U575QII6 STM32U575AII6 STM32U575CIU6Q STM32U575CIT6Q STM32U575OIY6Q STM32U575VIT6Q STM32U575QII6Q STM32U575ZIT6Q STM32U575RIT6Q STM32U575CGU6 STM32U575CGT6 STM32U575RGT6 STM32U575VGT6 STM32U575ZGT6 STM32U575QGI6 STM32U575AGI6 STM32U575CGU6Q STM32U575CGT6Q STM32U575OGY6Q STM32U575VGT6Q STM32U575QGI6Q STM32U575ZGT6Q STM32U575RGT6Q STM32U575AGI6Q Devices */
- /* #define STM32U585xx */ /*!< STM32U585CIU6 STM32U585CIT6 STM32U585RIT6 STM32U585VIT6 STM32U585AII6 STM32U585QII6 STM32U585ZIT6 STM32U585OIY6Q STM32U585VIT6Q STM32U585QEI6Q STM32U585RIT6Q STM32U585AII6Q STM32U585CIU6Q STM32U585CIT6Q STM32U585ZET6Q Devices */
- /* #define STM32U595xx */ /*!< STM32U595ZJT6Q Device */
- /* #define STM32U599xx */ /*!< STM32U599NJH6Q STM32U599BJY6Q STM32U599NIH6Q Devices */
- /* #define STM32U5A5xx */ /*!< STM32U5A5ZJT6Q Device */
- /* #define STM32U5A9xx */ /*!< STM32U5A9NJH6Q STM32U5A9BJY6Q Devices */
+ && !defined (STM32U5A5xx) && !defined (STM32U5A9xx) \
+ && !defined (STM32U5F7xx) && !defined (STM32U5G7xx) \
+ && !defined (STM32U5F9xx) && !defined (STM32U5G9xx) \
+ && !defined (STM32U535xx) && !defined (STM32U545xx) \
+ /* #define STM32U575xx */ /*!< STM32U575CIU6 STM32U575CIT6 STM32U575RIT6 STM32U575VIT6 STM32U575ZIT6 STM32U575QII6 STM32U575AII6 STM32U575CIU6Q STM32U575CIT6Q STM32U575OIY6Q STM32U575VIT6Q STM32U575QII6Q STM32U575ZIT6Q STM32U575RIT6Q STM32U575CGU6 STM32U575CGT6 STM32U575RGT6 STM32U575VGT6 STM32U575ZGT6 STM32U575QGI6 STM32U575AGI6 STM32U575CGU6Q STM32U575CGT6Q STM32U575OGY6Q STM32U575VGT6Q STM32U575QGI6Q STM32U575ZGT6Q STM32U575RGT6Q STM32U575AGI6Q Devices */
+ /* #define STM32U585xx */ /*!< STM32U585CIU6 STM32U585CIT6 STM32U585RIT6 STM32U585VIT6 STM32U585AII6 STM32U585QII6 STM32U585ZIT6 STM32U585OIY6Q STM32U585VIT6Q STM32U585QEI6Q STM32U585RIT6Q STM32U585AII6Q STM32U585CIU6Q STM32U585CIT6Q STM32U585ZET6Q Devices */
+ /* #define STM32U595xx */ /*!< STM32U595AJH6 STM32U595ZJT6 STM32U595QJI6 STM32U595VJT6 STM32U595RJT6 STM32U595AJH6Q STM32U595ZJY6QTR STM32U595ZJT6Q STM32U595QJI6Q STM32U595VJT6Q STM32U595RJT6Q STM32U595AIH6 STM32U595ZIT6 STM32U595QII6 STM32U595VIT6 STM32U595RIT6 STM32U595AIH6Q STM32U595ZIY6QTR STM32U595ZIT6Q STM32U595QII6Q STM32U595VIT6Q STM32U595RIT6Q Devices */
+ /* #define STM32U599xx */ /*!< STM32U599VJT6 STM32U599NJH6Q STM32U599BJY6QTR STM32U599ZJY6QTR STM32U599ZJT6Q STM32U599VJT6Q STM32U599NIH6Q STM32U599ZIY6QTR STM32U599ZIT6Q STM32U599VIT6Q Devices */
+ /* #define STM32U5A5xx */ /*!< STM32U5A5AJH6 STM32U5A5ZJT6 STM32U5A5QJI6 STM32U5A5VJT6 STM32U5A5RJT6 STM32U5A5AJH6Q STM32U5A5ZJY6QTR STM32U5A5ZJT6Q STM32U5A5QJI6Q STM32U5A5VJT6Q STM32U5A5RJT6Q Devices */
+ /* #define STM32U5A9xx */ /*!< STM32U5A9NJH6Q STM32U5A9BJY6QTR STM32U5A9ZJY6QTR STM32U5A9ZJT6Q STM32U5A9VJT6Q Devices */
+ /* #define STM32U5F7xx */ /*!< STM32U5F7VJT6Q STM32U5F7VJT6 Devices STM32U5F7VIT6Q STM32U5F7VIT6 Devices */
+ /* #define STM32U5G7xx */ /*!< STM32U5G7VJT6Q STM32U5G7VJT6 Devices */
+ /* #define STM32U5F9xx */ /*!< STM32U5F9NJH6Q STM32U5F9BJY6QTR STM32U5F9ZJJ6QTR STM32U5F9ZJT6Q STM32U5F9VJT6Q Devices */
+ /* #define STM32U5G9xx */ /*!< STM32U5G9NJH6Q STM32U5G9BJY6QTR STM32U5G9ZJJ6QTR STM32U5G9ZJT6Q STM32U5G9VJT6Q Devices */
+ /* #define STM32U535xx */ /*!< STM32U535CET6 STM32U535CEU6 STM32U535RET6 STM32U535REI6 STM32U535VET6 STM32U535VEI6 STM32U535CET6Q STM32U535CEU6Q STM32U535RET6Q STM32U535REI6Q STM32U535VET6Q STM32U535VEI6Q STM32U535NEY6Q STM32U535JEY6Q Device */
+ /* #define STM32U545xx */ /*!< STM32U545CET6 STM32U545CEU6 STM32U545RET6 STM32U545REI6 STM32U545VET6 STM32U545VEI6 STM32U545CET6Q STM32U545CEU6Q STM32U545RET6Q STM32U545REI6Q STM32U545VET6Q STM32U545VEI6Q STM32U545NEY6Q STM32U545JEY6Q Device */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -81,12 +90,12 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number 1.0.0
+ * @brief CMSIS Device version number 1.3.0
*/
-#define __STM32U5_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32U5_CMSIS_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
-#define __STM32U5_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32U5_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32U5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
+#define __STM32U5_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
+#define __STM32U5_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
+#define __STM32U5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32U5_CMSIS_VERSION ((__STM32U5_CMSIS_VERSION_MAIN << 24U)\
|(__STM32U5_CMSIS_VERSION_SUB1 << 16U)\
|(__STM32U5_CMSIS_VERSION_SUB2 << 8U )\
@@ -112,6 +121,18 @@
#include "stm32u5a5xx.h"
#elif defined(STM32U5A9xx)
#include "stm32u5a9xx.h"
+#elif defined(STM32U5F9xx)
+ #include "stm32u5f9xx.h"
+#elif defined(STM32U5G9xx)
+ #include "stm32u5g9xx.h"
+#elif defined(STM32U5F7xx)
+ #include "stm32u5f7xx.h"
+#elif defined(STM32U5G7xx)
+ #include "stm32u5g7xx.h"
+#elif defined(STM32U535xx)
+ #include "stm32u535xx.h"
+#elif defined(STM32U545xx)
+ #include "stm32u545xx.h"
#else
#error "Please select first the target STM32U5xx device used in your application (in stm32u5xx.h file)"
#endif
diff --git a/platform/ext/target/stm/common/stm32u5xx/Device/Include/system_stm32u5xx.h b/platform/ext/target/stm/common/stm32u5xx/Device/Include/system_stm32u5xx.h
index 24f645c..e634c5c 100644
--- a/platform/ext/target/stm/common/stm32u5xx/Device/Include/system_stm32u5xx.h
+++ b/platform/ext/target/stm/common/stm32u5xx/Device/Include/system_stm32u5xx.h
@@ -6,13 +6,13 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
+ * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -35,11 +35,16 @@
/** @addtogroup STM32U5xx_System_Includes
* @{
*/
-
+
/**
* @}
*/
+ /**
+ \brief Exception / Interrupt Handler Function Prototype
+*/
+typedef void(*VECTOR_TABLE_Type)(void);
+
/** @addtogroup STM32U5xx_System_Exported_Variables
* @{
*/
@@ -67,11 +72,6 @@
*/
/**
- \brief Exception / Interrupt Handler Function Prototype
-*/
-typedef void(*VECTOR_TABLE_Type)(void);
-
-/**
* @brief Setup the microcontroller system.
*
* Initialize the System and update the SystemCoreClock variable.
diff --git a/platform/ext/target/stm/common/stm32u5xx/bl2/stm32u5xx_hal_msp.c b/platform/ext/target/stm/common/stm32u5xx/bl2/stm32u5xx_hal_msp.c
index a9e16a8..64430f9 100644
--- a/platform/ext/target/stm/common/stm32u5xx/bl2/stm32u5xx_hal_msp.c
+++ b/platform/ext/target/stm/common/stm32u5xx/bl2/stm32u5xx_hal_msp.c
@@ -99,7 +99,7 @@
.Sai2ClockSelection = 0,
.RngClockSelection = 0,
.SaesClockSelection = 0,
- .Clk48ClockSelection = 0,
+ .IclkClockSelection = 0,
.SdmmcClockSelection = 0,
.AdcDacClockSelection = 0,
.Dac1ClockSelection = 0,
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/Legacy/stm32_hal_legacy.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/Legacy/stm32_hal_legacy.h
index 0185195..aeadc8a 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/Legacy/stm32_hal_legacy.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/Legacy/stm32_hal_legacy.h
@@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -38,14 +38,12 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-#if defined(STM32U5)
+#if defined(STM32H7) || defined(STM32MP1)
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
-#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
-#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
-#endif /* STM32U5 */
+#endif /* STM32H7 || STM32MP1 */
/**
* @}
*/
@@ -105,6 +103,16 @@
#if defined(STM32H7)
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
+#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
+#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE
+#endif /* STM32H5 */
/**
* @}
*/
@@ -132,7 +140,8 @@
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
#if defined(STM32L0)
-#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
+ input 1 for COMP1, LPTIM input 2 for COMP2 */
#endif
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
@@ -206,6 +215,11 @@
#endif
#endif
+
+#if defined(STM32U5)
+#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
+#endif
+
/**
* @}
*/
@@ -214,6 +228,11 @@
* @{
*/
#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+#if defined(STM32U5)
+#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
+#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
+#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
+#endif /* STM32U5 */
/**
* @}
*/
@@ -223,8 +242,10 @@
*/
#if defined(STM32H5) || defined(STM32C0)
#else
-#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
-#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
+#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
+ inter STM32 series compatibility */
+#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
+ inter STM32 series compatibility */
#endif
/**
* @}
@@ -255,12 +276,25 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
+#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
+#if defined(STM32U5)
+#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
+#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
+#endif
+
+#if defined(STM32H5)
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
+ defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
@@ -325,7 +359,8 @@
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
-#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
+ defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
#endif
@@ -402,6 +437,10 @@
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
+#endif /* STM32U5 */
/**
* @}
*/
@@ -506,6 +545,9 @@
#define OB_USER_nBOOT0 OB_USER_NBOOT0
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
#define OB_nBOOT0_SET OB_NBOOT0_SET
+#define OB_USER_SRAM134_RST OB_USER_SRAM_RST
+#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
+#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
#endif /* STM32U5 */
/**
@@ -550,6 +592,106 @@
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
+#if defined(STM32H5)
+#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
+#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
+#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
+#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
+#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
+#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
+
+#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
+#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
+#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
+#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
+
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
+
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
+
+#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
+#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
+#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
+#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
+
+#define SYSCFG_ETH_MII SBS_ETH_MII
+#define SYSCFG_ETH_RMII SBS_ETH_RMII
+#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
+
+#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
+#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
+#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
+
+#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
+
+#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
+#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SYSCFG_SAU SBS_SAU
+#define SYSCFG_MPU_SEC SBS_MPU_SEC
+#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
+#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
+#else
+#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
+#endif /* __ARM_FEATURE_CMSE */
+
+#define SYSCFG_CLK SBS_CLK
+#define SYSCFG_CLASSB SBS_CLASSB
+#define SYSCFG_FPU SBS_FPU
+#define SYSCFG_ALL SBS_ALL
+
+#define SYSCFG_SEC SBS_SEC
+#define SYSCFG_NSEC SBS_NSEC
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
+
+#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
+#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
+#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
+
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
+
+#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
+#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
+
+#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
+#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
+#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
+#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
+#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
+#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
+#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
+
+#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
+#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
+#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
+#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
+#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
+#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
+
+#define HAL_SYSCFG_Lock HAL_SBS_Lock
+#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
+#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
+#endif /* __ARM_FEATURE_CMSE */
+
+#endif /* STM32H5 */
+
+
/**
* @}
*/
@@ -617,14 +759,16 @@
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
-#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
+ STM32H757xx */
#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
+ defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
@@ -645,6 +789,42 @@
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
+
+#if defined(STM32U5) || defined(STM32H5)
+#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
+#endif /* STM32U5 || STM32H5 */
+#if defined(STM32U5)
+#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
+#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32U5)
+#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
+#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
+#endif /* STM32U5 */
+#if defined(STM32H5)
+#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1
+#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC
+#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB
+#endif /* STM32H5 */
+#if defined(STM32H5) || defined(STM32U5)
+#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX
+#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
+#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED
+#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED
+#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC
+#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC
+#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV
+#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV
+#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF
+#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON
+#endif /* STM32H5 || STM32U5 */
/**
* @}
*/
@@ -825,7 +1005,8 @@
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
+ defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
@@ -882,9 +1063,19 @@
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
+/**
+ * @}
+ */
+
#if defined(STM32U5)
#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
+#define LPTIM_CHANNEL_ALL 0x00000000U
#endif /* STM32U5 */
/**
* @}
@@ -953,7 +1144,7 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@@ -1037,8 +1228,8 @@
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
@@ -1049,15 +1240,42 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+#if defined(STM32H5)
+#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
+#endif /* STM32H5 */
+
+#if defined(STM32WBA)
+#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2
+#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK
+#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE
+#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
+#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM
+#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
+#endif /* STM32WBA */
+
+#if defined(STM32H5) || defined(STM32WBA)
+#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
+#endif /* STM32H5 || STM32WBA */
+
+#if defined(STM32F7)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
+#endif /* STM32F7 */
+
#if defined(STM32H7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
+#endif /* STM32H7 */
+#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
-#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
-#endif /* STM32H7 */
+#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
+#endif /* STM32F7 || STM32H7 || STM32L0 */
/**
* @}
@@ -1224,6 +1442,10 @@
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
#endif
+#if defined(STM32U5)
+#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
+#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
+#endif
/**
* @}
*/
@@ -1333,30 +1555,40 @@
#define ETH_MMCRFAECR 0x00000198U
#define ETH_MMCRGUFCR 0x000001C4U
-#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
+ the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
+ MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus
+ or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
+ of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
+ transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
+ frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
+ de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
+ activate threshold */
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
+ (or time-stamp) */
#endif
-#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
+ status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
@@ -1527,7 +1759,8 @@
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
- )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+ )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
+ HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
@@ -1536,8 +1769,10 @@
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
- )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+ )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \
+ HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
+ defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
@@ -1571,16 +1806,21 @@
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
- )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
+ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
+ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
+ defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
+ defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
+ STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
+ defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
@@ -1654,10 +1894,111 @@
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+#if defined (STM32U5)
+#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
+#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
+#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
+#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
+#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
+#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
+#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
+#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
+#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
+#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
+#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
+#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
+#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
+#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
+#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
+
+#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
+#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
+#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
+#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
+#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
+#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
+#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
+#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
+#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
+#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
+#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
+#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
+#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
+#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
+
+#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
+
+#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
+#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
+#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
+#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
+#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
+#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
+#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
+#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
+#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
+#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
+#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
+#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
+#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
+#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
+
+#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP
+#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP
+#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP
+#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP
+#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP
+#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP
+#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP
+#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP
+#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP
+
+
+#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
+#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
+#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
+#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
+#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
+#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
+#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
+#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
+#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP
+
+
+#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
+#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
+#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
+
+#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
+#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
+#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
+#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
+#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
+#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN
+
+#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
+#endif
+
/**
* @}
*/
+/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32H5) || defined(STM32WBA)
+#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
+#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
+#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
+#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
+#endif /* STM32H5 || STM32WBA */
+
+/**
+ * @}
+ */
+
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
*/
@@ -1683,7 +2024,8 @@
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
+ defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
@@ -1940,7 +2282,8 @@
#define COMP_STOP __HAL_COMP_DISABLE
#define COMP_LOCK __HAL_COMP_LOCK
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
+ defined(STM32F334x8) || defined(STM32F328xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
@@ -2112,8 +2455,10 @@
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
* @{
*/
-#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
+ done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
+ done into HAL_COMP_Init() */
/**
* @}
*/
@@ -2272,7 +2617,9 @@
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
@@ -2281,8 +2628,12 @@
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
+ HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
+ } while(0)
+#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
+ HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
+ } while(0)
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
@@ -2318,8 +2669,8 @@
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
- )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
+ HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
@@ -2823,6 +3174,11 @@
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2
+#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2
+#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2
+#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2
+#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2
#endif
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
@@ -3287,10 +3643,8 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32GK)
-#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_DISABLE
-#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_DISABLE
-#elif defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) || defined(STM32V7)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
+ defined(STM32WL) || defined(STM32C0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3392,6 +3746,7 @@
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
+
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
@@ -3403,8 +3758,8 @@
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
#if defined(STM32U5)
-#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
-#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
+#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
@@ -3415,7 +3770,112 @@
#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
-#endif
+#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
+#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
+#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
+#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
+#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
+#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
+#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
+#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
+
+#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE
+#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI
+#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI
+#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE
+#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0
+#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1
+#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2
+#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3
+#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE
+#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM
+
+#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE
+#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE
+#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE
+#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE
+#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE
+#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE
+#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE
+#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE
+#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE
+#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE
+
+#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE
+#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE
+#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE
+#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE
+#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG
+#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG
+#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG
+#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE
+#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE
+#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE
+#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE
+#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE
+#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE
+#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE
+#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE
+#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE
+#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE
+#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE
+#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE
+#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE
+#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
+
+#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0
+#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1
+#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2
+#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3
+
+#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE
+#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM
+
+#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE
+#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI
+#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI
+#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE
+
+#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0
+#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1
+#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2
+#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3
+
+#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE
+#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM
+
+#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE
+#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI
+#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI
+#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE
+
+
+#endif /* STM32H5 */
+
/**
* @}
*/
@@ -3432,7 +3892,9 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32GK) || defined (STM32WB_GEN2) || defined (STM32V7) || defined (STM32H5)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
+ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
+ defined (STM32WBA) || defined (STM32H5) || defined (STM32C0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3467,6 +3929,12 @@
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */
+#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
+ defined (STM32H7) || \
+ defined (STM32L0) || defined (STM32L1)
+#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
+#endif
+
#define IS_ALARM IS_RTC_ALARM
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
#define IS_TAMPER IS_RTC_TAMPER
@@ -3485,6 +3953,11 @@
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+#if defined (STM32H5)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
+#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE
+#endif /* STM32H5 */
+
/**
* @}
*/
@@ -3496,7 +3969,7 @@
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
-#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
+#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal.h
index 378b678..c408bb6 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal.h
@@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -81,6 +81,8 @@
* @}
*/
+
+
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
* @{
*/
@@ -192,6 +194,85 @@
#endif /* __ARM_FEATURE_CMSE */
+#ifdef SYSCFG_OTGHSPHYCR_EN
+/** @defgroup SYSCFG_OTG_PHY_RefenceClockSelection OTG PHY Reference Clock Selection
+ * @{
+ */
+
+/** @brief OTG HS PHY reference clock frequency selection
+ */
+#define SYSCFG_OTG_HS_PHY_CLK_SELECT_1 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1) /*!< 16Mhz */
+#define SYSCFG_OTG_HS_PHY_CLK_SELECT_2 SYSCFG_OTGHSPHYCR_CLKSEL_3 /*!< 19.2Mhz */
+#define SYSCFG_OTG_HS_PHY_CLK_SELECT_3 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 20Mhz */
+#define SYSCFG_OTG_HS_PHY_CLK_SELECT_4 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 24Mhz */
+#define SYSCFG_OTG_HS_PHY_CLK_SELECT_5 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 26Mhz */
+#define SYSCFG_OTG_HS_PHY_CLK_SELECT_6 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 32Mhz */
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_OTG_PHY_PowerDown OTG PHY Power Down
+ * @{
+ */
+
+/** @brief OTG HS PHY Power Down config
+ */
+
+#define SYSCFG_OTG_HS_PHY_POWER_ON 0x00000000U /*!< PHY state machine, bias and OTG PHY PLL are powered down */
+#define SYSCFG_OTG_HS_PHY_POWER_DOWN SYSCFG_OTGHSPHYCR_PDCTRL /*!< PHY state machine, bias and OTG PHY PLL remain powered */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_OTG_PHY_Enable OTG PHY Enable
+ * @{
+ */
+
+#define SYSCFG_OTG_HS_PHY_UNDERRESET 0x00000000U /*!< PHY under reset */
+#define SYSCFG_OTG_HS_PHY_ENABLE SYSCFG_OTGHSPHYCR_EN /*!< PHY enabled */
+
+/** @defgroup SYSCFG_OTG_PHYTUNER_PreemphasisCurrent OTG PHYTUNER Preemphasis Current
+ * @{
+ */
+
+/** @brief High-speed (HS) transmitter preemphasis current control
+ */
+#define SYSCFG_OTG_HS_PHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */
+#define SYSCFG_OTG_HS_PHY_PREEMP_1X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */
+#define SYSCFG_OTG_HS_PHY_PREEMP_2X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */
+#define SYSCFG_OTG_HS_PHY_PREEMP_3X (SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_OTG_PHYTUNER_SquelchThreshold OTG PHYTUNER Squelch Threshold
+ * @{
+ */
+
+/** @brief Squelch threshold adjustment
+ */
+#define SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */
+#define SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT (SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_OTG_PHYTUNER_DisconnectThreshold OTG PHYTUNER Disconnect Threshold
+ * @{
+ */
+
+/** @brief Disconnect threshold adjustment
+ */
+#define SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */
+#define SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */
+
+/**
+ * @}
+ */
+#endif /* SYSCFG_OTGHSPHYCR_EN */
/**
* @}
*/
@@ -259,16 +340,21 @@
#define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
#endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */
+#if defined(DBGMCU_APB1FZR2_DBG_I2C5_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C5() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C5() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP)
+#endif /* DBGMCU_APB1FZR2_DBG_I2C5_STOP */
+
+#if defined(DBGMCU_APB1FZR2_DBG_I2C6_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C6() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C6() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP)
+#endif /* DBGMCU_APB1FZR2_DBG_I2C6_STOP */
+
#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */
-#if defined(DBGMCU_APB1FZR2_DBG_FDCAN_STOP)
-#define __HAL_DBGMCU_FREEZE_FDCAN() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_FDCAN_STOP)
-#define __HAL_DBGMCU_UNFREEZE_FDCAN() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_FDCAN_STOP)
-#endif /* DBGMCU_APB1FZR2_DBG_FDCAN_STOP */
-
#if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP)
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP)
@@ -556,6 +642,33 @@
#endif /* __ARM_FEATURE_CMSE */
+
+#ifdef SYSCFG_OTGHSPHYCR_EN
+#define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \
+ ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \
+ ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \
+ ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_4) || \
+ ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_5) || \
+ ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_6))
+
+#define IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_DOWN) || \
+ ((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_ON))
+
+#define IS_SYSCFG_OTGPHY_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_UNDERRESET) || \
+ ((__VALUE__) == SYSCFG_OTG_HS_PHY_ENABLE))
+
+#define IS_SYSCFG_OTGPHY_DISCONNECT(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT) || \
+ ((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT))
+
+#define IS_SYSCFG_OTGPHY_SQUELCH(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT) || \
+ ((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT))
+
+#define IS_SYSCFG_OTGPHY_PREEMPHASIS(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_DISABLED) || \
+ ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_1X) || \
+ ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_2X) || \
+ ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_3X))
+#endif /* SYSCFG_OTGHSPHYCR_EN */
+
/**
* @}
*/
@@ -606,6 +719,9 @@
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
/**
* @}
@@ -637,10 +753,28 @@
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
void HAL_SYSCFG_DisableVREFBUF(void);
-
+#ifdef SYSCFG_OTGHSPHYCR_EN
+void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClkSelection);
+void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig);
+void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig);
+void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold);
+void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold);
+void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent);
+#endif /* SYSCFG_OTGHSPHYCR_EN */
void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
-
+void HAL_SYSCFG_EnableSRAMCached(void);
+void HAL_SYSCFG_DisableSRAMCached(void);
+void HAL_SYSCFG_EnableVddCompensationCell(void);
+void HAL_SYSCFG_EnableVddIO2CompensationCell(void);
+#if defined(SYSCFG_CCCSR_EN3)
+void HAL_SYSCFG_EnableVddHSPICompensationCell(void);
+#endif /* SYSCFG_CCCSR_EN3 */
+void HAL_SYSCFG_DisableVddCompensationCell(void);
+void HAL_SYSCFG_DisableVddIO2CompensationCell(void);
+#if defined(SYSCFG_CCCSR_EN3)
+void HAL_SYSCFG_DisableVddHSPICompensationCell(void);
+#endif /* SYSCFG_CCCSR_EN3 */
/**
* @}
*/
@@ -685,6 +819,10 @@
* @}
*/
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cortex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cortex.h
index 55e9452..ced44d5 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cortex.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cortex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -204,9 +204,9 @@
/** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes
* @{
*/
-#define MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */
-#define MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */
-#define MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */
+#define MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */
+#define MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */
+#define MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */
#define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */
#define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cryp.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cryp.h
index 7d2ed1c..55989cf 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cryp.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cryp.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -78,7 +78,6 @@
} CRYP_ConfigTypeDef;
-
/**
* @brief CRYP State Structure definition
*/
@@ -93,6 +92,31 @@
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
} HAL_CRYP_STATETypeDef;
+/**
+ * @brief CRYP Context Structure definition
+ */
+
+typedef struct
+{
+ uint32_t DataType; /*!< This parameter can be a value of @ref CRYP_Data_Type */
+ uint32_t KeySize; /*!< This parameter can be a value of @ref CRYP_Key_Size */
+ uint32_t *pKey; /*!< The key used for encryption/decryption */
+ uint32_t *pInitVect; /*!< The initialization vector, counter with CBC and CTR Algorithm */
+ uint32_t Algorithm; /*!< This parameter can be a value of @ref CRYP_Algorithm_Mode */
+ uint32_t DataWidthUnit; /*!< This parameter can be value of @ref CRYP_Data_Width_Unit */
+ uint32_t KeyIVConfigSkip; /*!< This parameter can be a value of @ref CRYP_Configuration_Skip */
+ uint32_t KeyMode; /*!< This parameter can be value of @ref CRYP_Key_Mode */
+ uint32_t Phase; /*!< CRYP peripheral phase */
+ uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag */
+ uint32_t CR_Reg; /*!< CRYP CR register */
+ uint32_t IER_Reg; /*!< CRYP IER register */
+ uint32_t IVR0_Reg; /*!< CRYP IVR0 register */
+ uint32_t IVR1_Reg; /*!< CRYP IVR1 register */
+ uint32_t IVR2_Reg; /*!< CRYP IVR2 register */
+ uint32_t IVR3_Reg; /*!< CRYP IVR3 register */
+
+} CRYP_ContextTypeDef;
+
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
/**
* @brief HAL CRYP mode suspend definitions
@@ -239,6 +263,7 @@
#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
#define HAL_CRYP_ERROR_KEY 0x00000100U /*!< Key error */
+#define HAL_CRYP_ERROR_RNG 0x00000200U /*!< Rng error */
/**
* @}
*/
@@ -340,10 +365,15 @@
* @{
*/
-#define CRYP_NO_SWAP 0x00000000U /*!< 32-bit data type (no swapping) */
-#define CRYP_HALFWORD_SWAP AES_CR_DATATYPE_0 /*!< 16-bit data type (half-word swapping) */
-#define CRYP_BYTE_SWAP AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */
-#define CRYP_BIT_SWAP AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */
+#define CRYP_DATATYPE_32B 0x00000000U
+#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0
+#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1
+#define CRYP_DATATYPE_1B AES_CR_DATATYPE
+
+#define CRYP_NO_SWAP CRYP_DATATYPE_32B /*!< 32-bit data type (no swapping) */
+#define CRYP_HALFWORD_SWAP CRYP_DATATYPE_16B /*!< 16-bit data type (half-word swapping) */
+#define CRYP_BYTE_SWAP CRYP_DATATYPE_8B /*!< 8-bit data type (byte swapping) */
+#define CRYP_BIT_SWAP CRYP_DATATYPE_1B /*!< 1-bit data type (bit swapping) */
/**
* @}
@@ -352,9 +382,10 @@
/** @defgroup CRYP_Interrupt CRYP Interrupt
* @{
*/
-#define CRYP_IT_CCFIE AES_IER_CCFIE /*!< Computation Complete interrupt enable */
-#define CRYP_IT_RWEIE AES_IER_RWEIE /*!< Read or write Error interrupt enable */
-#define CRYP_IT_KEIE AES_IER_KEIE /*!< Key error interrupt enable */
+#define CRYP_IT_CCFIE AES_IER_CCFIE /*!< Computation Complete interrupt enable */
+#define CRYP_IT_RWEIE AES_IER_RWEIE /*!< Read or write Error interrupt enable */
+#define CRYP_IT_KEIE AES_IER_KEIE /*!< Key error interrupt enable */
+#define CRYP_IT_RNGEIE AES_IER_RNGEIE /*!< Rng error interrupt enable */
/**
* @}
@@ -364,14 +395,15 @@
* @{
*/
-#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden
- also set when transferring a shared key from SAES peripheral */
-#define CRYP_FLAG_WRERR (AES_SR_WRERR | 0x80000000U) /*!< Write Error flag */
-#define CRYP_FLAG_RDERR (AES_SR_RDERR | 0x80000000U) /*!< Read error flag */
-#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation completed flag as AES_ISR_CCF */
-#define CRYP_FLAG_KEYVALID AES_SR_KEYVALID /*!< Key Valid flag */
-#define CRYP_FLAG_KEIF AES_ISR_KEIF /*Key error interrupt flag */
-#define CRYP_FLAG_RWEIF AES_ISR_RWEIF /*Read or write error Interrupt flag */
+#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden also set when
+ transferring a shared key from SAES peripheral */
+#define CRYP_FLAG_WRERR (AES_SR_WRERR | 0x80000000U) /*!< Write Error flag */
+#define CRYP_FLAG_RDERR (AES_SR_RDERR | 0x80000000U) /*!< Read error flag */
+#define CRYP_FLAG_CCF AES_ISR_CCF /*!< Computation completed flag as AES_ISR_CCF */
+#define CRYP_FLAG_KEYVALID AES_SR_KEYVALID /*!< Key Valid flag */
+#define CRYP_FLAG_KEIF AES_ISR_KEIF /*!<Key error interrupt flag */
+#define CRYP_FLAG_RWEIF AES_ISR_RWEIF /*!<Read or write error Interrupt flag */
+#define CRYP_FLAG_RNGEIF AES_ISR_RNGEIF /*!<RNG error interrupt flag */
/**
@@ -382,10 +414,12 @@
* @{
*/
-#define CRYP_CLEAR_CCF AES_ICR_CCF /* Computation Complete Flag Clear */
-#define CRYP_CLEAR_RWEIF AES_ICR_RWEIF /* Clear Error Flag : RWEIF in AES_ISR and
+#define CRYP_CLEAR_CCF AES_ICR_CCF /*!< Computation Complete Flag Clear */
+#define CRYP_CLEAR_RWEIF AES_ICR_RWEIF /*!< Clear Error Flag : RWEIF in AES_ISR and
both RDERR and WRERR flags in AES_SR */
-#define CRYP_CLEAR_KEIF AES_ICR_KEIF /* Clear Key Error Flag: KEIF in AES_ISR */
+#define CRYP_CLEAR_KEIF AES_ICR_KEIF /*!< Clear Key Error Flag: KEIF in AES_ISR */
+#define CRYP_CLEAR_RNGEIF AES_ICR_RNGEIF /*!< Clear rng Error Flag: RNGEIF in AES_ISR */
+
/**
* @}
@@ -395,9 +429,10 @@
* @{
*/
-#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
-#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
-#define CRYP_KEYNOCONFIG 0x00000002U /*!< Peripheral Key configuration to not do */
+#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
+#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
+#define CRYP_KEYNOCONFIG 0x00000002U /*!< Peripheral Key configuration to not do */
+#define CRYP_IVCONFIG_ONCE 0x00000004U /*!< Peripheral IV configuration do once for interleave mode */
/**
* @}
@@ -553,6 +588,9 @@
HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp);
#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
+HAL_StatusTypeDef HAL_CRYP_SaveContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont);
+HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont);
+
/**
* @}
*/
@@ -581,11 +619,11 @@
*/
/* Interrupt Handler functions **********************************************/
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
-uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
+uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp);
/**
* @}
@@ -619,6 +657,8 @@
((DATATYPE) == CRYP_BIT_SWAP))
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
+ ((CONFIG) == CRYP_KEYNOCONFIG) || \
+ ((CONFIG) == CRYP_IVCONFIG_ONCE) || \
((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
#define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \
@@ -635,6 +675,13 @@
/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Constants CRYP Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
/* Private defines -----------------------------------------------------------*/
/** @defgroup CRYP_Private_Defines CRYP Private Defines
* @{
@@ -645,6 +692,14 @@
*/
/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Variables CRYP Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRYP_Private_Functions CRYP Private Functions
* @{
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cryp_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cryp_ex.h
index 1bd37e0..0b8f1d3 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cryp_ex.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_cryp_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -40,12 +40,66 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup CRYPEx_Exported_Types CRYPEx Exported Types
+ * @{
+ */
+
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRYPEx_Exported_Constants CRYPEx Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
/* Private types -------------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/* Private macros ------------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
* @{
@@ -54,8 +108,10 @@
/** @addtogroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
* @{
*/
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *pAuthTag, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *pAuthTag, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag,
+ uint32_t Timeout);
/**
* @}
*/
@@ -69,7 +125,7 @@
* @}
*/
-/** @addtogroup CRYPEx_Exported_Functions_Group3 Encrypt/Decrypt Shared key functions
+/** @addtogroup CRYPEx_Exported_Functions_Group3 Encrypt and Decrypt Shared key functions
* @{
*/
HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *pKey, uint32_t *pOutput, uint32_t ID,
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_def.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_def.h
index 9c25629..d724710 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_def.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_def.h
@@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -71,7 +71,9 @@
(__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0)
-#define UNUSED(x) ((void)(x))
+#if !defined(UNUSED)
+#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
+#endif /* UNUSED */
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma.h
index 926a62f..e62dff3 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma.h
@@ -6,7 +6,7 @@
**********************************************************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -278,8 +278,10 @@
#define GPDMA1_REQUEST_I2C4_EVC (23U) /*!< GPDMA1 HW request is I2C4_EVC */
#define GPDMA1_REQUEST_USART1_RX (24U) /*!< GPDMA1 HW request is USART1_RX */
#define GPDMA1_REQUEST_USART1_TX (25U) /*!< GPDMA1 HW request is USART1_TX */
+#if defined(USART2)
#define GPDMA1_REQUEST_USART2_RX (26U) /*!< GPDMA1 HW request is USART2_RX */
#define GPDMA1_REQUEST_USART2_TX (27U) /*!< GPDMA1 HW request is USART2_TX */
+#endif /* USART2 */
#define GPDMA1_REQUEST_USART3_RX (28U) /*!< GPDMA1 HW request is USART3_RX */
#define GPDMA1_REQUEST_USART3_TX (29U) /*!< GPDMA1 HW request is USART3_TX */
#define GPDMA1_REQUEST_UART4_RX (30U) /*!< GPDMA1 HW request is UART4_RX */
@@ -290,10 +292,14 @@
#define GPDMA1_REQUEST_LPUART1_TX (35U) /*!< GPDMA1 HW request is LPUART1_TX */
#define GPDMA1_REQUEST_SAI1_A (36U) /*!< GPDMA1 HW request is SAI1_A */
#define GPDMA1_REQUEST_SAI1_B (37U) /*!< GPDMA1 HW request is SAI1_B */
+#if defined(SAI2)
#define GPDMA1_REQUEST_SAI2_A (38U) /*!< GPDMA1 HW request is SAI2_A */
#define GPDMA1_REQUEST_SAI2_B (39U) /*!< GPDMA1 HW request is SAI2_B */
+#endif /* SAI2 */
#define GPDMA1_REQUEST_OCTOSPI1 (40U) /*!< GPDMA1 HW request is OCTOSPI1 */
+#if defined(OCTOSPI2)
#define GPDMA1_REQUEST_OCTOSPI2 (41U) /*!< GPDMA1 HW request is OCTOSPI2 */
+#endif /* OCTOSPI2 */
#define GPDMA1_REQUEST_TIM1_CH1 (42U) /*!< GPDMA1 HW request is TIM1_CH1 */
#define GPDMA1_REQUEST_TIM1_CH2 (43U) /*!< GPDMA1 HW request is TIM1_CH2 */
#define GPDMA1_REQUEST_TIM1_CH3 (44U) /*!< GPDMA1 HW request is TIM1_CH3 */
@@ -338,12 +344,14 @@
#define GPDMA1_REQUEST_TIM16_UP (83U) /*!< GPDMA1 HW request is TIM16_UP */
#define GPDMA1_REQUEST_TIM17_CH1 (84U) /*!< GPDMA1 HW request is TIM17_CH1 */
#define GPDMA1_REQUEST_TIM17_UP (85U) /*!< GPDMA1 HW request is TIM17_UP */
-#define GPDMA1_REQUEST_DCMI (86U) /*!< GPDMA1 HW request is DCMI */
+#define GPDMA1_REQUEST_DCMI_PSSI (86U) /*!< GPDMA1 HW request is DCMI_PSSI */
#define GPDMA1_REQUEST_AES_IN (87U) /*!< GPDMA1 HW request is AES_IN */
#define GPDMA1_REQUEST_AES_OUT (88U) /*!< GPDMA1 HW request is AES_OUT */
#define GPDMA1_REQUEST_HASH_IN (89U) /*!< GPDMA1 HW request is HASH_IN */
+#if defined(UCPD1)
#define GPDMA1_REQUEST_UCPD1_TX (90U) /*!< GPDMA1 HW request is UCPD1_TX */
#define GPDMA1_REQUEST_UCPD1_RX (91U) /*!< GPDMA1 HW request is UCPD1_RX */
+#endif /* UCPD1 */
#define GPDMA1_REQUEST_MDF1_FLT0 (92U) /*!< GPDMA1 HW request is MDF1_FLT0 */
#define GPDMA1_REQUEST_MDF1_FLT1 (93U) /*!< GPDMA1 HW request is MDF1_FLT1 */
#define GPDMA1_REQUEST_MDF1_FLT2 (94U) /*!< GPDMA1 HW request is MDF1_FLT2 */
@@ -366,6 +374,30 @@
#define GPDMA1_REQUEST_LPTIM3_IC1 (111U) /*!< GPDMA1 HW request is LPTIM3_IC1 */
#define GPDMA1_REQUEST_LPTIM3_IC2 (112U) /*!< GPDMA1 HW request is LPTIM3_IC2 */
#define GPDMA1_REQUEST_LPTIM3_UE (113U) /*!< GPDMA1 HW request is LPTIM3_UE */
+#if defined (HSPI1_BASE)
+#define GPDMA1_REQUEST_HSPI1 (114U) /*!< GPDMA1 HW request is HSPI1 */
+#endif /* defined (HSPI1_BASE) */
+#if defined (I2C5)
+#define GPDMA1_REQUEST_I2C5_RX (115U) /*!< GPDMA1 HW request is I2C5_RX */
+#define GPDMA1_REQUEST_I2C5_TX (116U) /*!< GPDMA1 HW request is I2C5_TX */
+#define GPDMA1_REQUEST_I2C5_EVC (117U) /*!< GPDMA1 HW request is I2C5_EVC */
+#endif /* defined (I2C5) */
+#if defined (I2C6)
+#define GPDMA1_REQUEST_I2C6_RX (118U) /*!< GPDMA1 HW request is I2C6_RX */
+#define GPDMA1_REQUEST_I2C6_TX (119U) /*!< GPDMA1 HW request is I2C6_TX */
+#define GPDMA1_REQUEST_I2C6_EVC (120U) /*!< GPDMA1 HW request is I2C6_EVC */
+#endif /* defined (I2C6) */
+#if defined (USART6)
+#define GPDMA1_REQUEST_USART6_RX (121U) /*!< GPDMA1 HW request is USART6_RX */
+#define GPDMA1_REQUEST_USART6_TX (122U) /*!< GPDMA1 HW request is USART6_TX */
+#endif /* defined (USART6) */
+#if defined (ADC2)
+#define GPDMA1_REQUEST_ADC2 (123U) /*!< GPDMA1 HW request is ADC2 */
+#endif /* defined (ADC2) */
+#if defined (JPEG)
+#define GPDMA1_REQUEST_JPEG_RX (124U) /*!< GPDMA1 HW request is JPEG_TX */
+#define GPDMA1_REQUEST_JPEG_TX (125U) /*!< GPDMA1 HW request is JPEG_RX */
+#endif /* defined (JPEG) */
/* LPDMA1 requests */
#define LPDMA1_REQUEST_LPUART1_RX (0U) /*!< LPDMA1 HW request is LPUART1_RX */
@@ -396,8 +428,8 @@
* @brief DMA Block Request
* @{
*/
-#define DMA_BREQ_SINGLE_BURST 0x00000000U /*!< Hardware request protocol at a single / burst level */
-#define DMA_BREQ_BLOCK DMA_CTR2_BREQ /*!< Hardware request protocol at a block level */
+#define DMA_BREQ_SINGLE_BURST 0x00000000U /*!< Hardware request protocol at a single / burst level */
+#define DMA_BREQ_BLOCK DMA_CTR2_BREQ /*!< Hardware request protocol at a block level */
/**
* @}
*/
@@ -406,9 +438,9 @@
* @brief DMA transfer direction
* @{
*/
-#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
-#define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */
+#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */
/**
* @}
*/
@@ -437,9 +469,9 @@
* @brief DMA Source Data Width
* @{
*/
-#define DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source data width : Byte */
-#define DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width : HalfWord */
-#define DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width : Word */
+#define DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source data width : Byte */
+#define DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width : HalfWord */
+#define DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width : Word */
/**
* @}
*/
@@ -448,9 +480,10 @@
* @brief DMA destination Data Width
* @{
*/
-#define DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination data width : Byte */
-#define DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width : HalfWord */
-#define DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width : Word */
+#define DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination data width : Byte */
+#define DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width : HalfWord */
+#define DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width : Word */
+
/**
* @}
*/
@@ -502,7 +535,7 @@
* @brief DMA Transfer Mode
* @{
*/
-#define DMA_NORMAL (0x00U) /*!< Normal DMA transfer */
+#define DMA_NORMAL (0x00U) /*!< Normal DMA transfer */
/**
* @}
*/
@@ -528,6 +561,8 @@
* @}
*/
+
+
/**
* @}
*/
@@ -728,16 +763,19 @@
* @brief DMA Attributes Functions
* @{
*/
+
HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma,
uint32_t ChannelAttributes);
HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma,
uint32_t *const pChannelAttributes);
+
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma);
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma,
uint32_t *const pLockState);
+
/**
* @}
*/
@@ -760,7 +798,8 @@
#define DMA_CHANNEL_ATTR_SEC_MASK (0x00000020U) /* DMA channel secure mask */
#define DMA_CHANNEL_ATTR_SEC_SRC_MASK (0x00000040U) /* DMA channel source secure mask */
#define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask */
-#define DMA_CHANNEL_ATTR_MASK (0xFFFFFFF0U) /* DMA channel attributes mask */
+#define DMA_CHANNEL_ATTR_VALUE_MASK (0x0000000FU) /* DMA channel attributes value mask */
+#define DMA_CHANNEL_ATTR_ITEM_MASK (0x000000F0U) /* DMA channel attributes item mask */
#define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */
#define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */
/**
@@ -822,9 +861,13 @@
#define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \
(((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U)
-#define IS_DMA_REQUEST(REQUEST) \
- (((REQUEST) == DMA_REQUEST_SW) || \
- ((REQUEST) <= GPDMA1_REQUEST_LPTIM3_UE))
+#if defined (GPDMA1_REQUEST_JPEG_TX)
+#define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_JPEG_TX))
+#elif defined (GPDMA1_REQUEST_ADC2)
+#define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_ADC2))
+#else
+#define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_LPTIM3_UE))
+#endif /* GPDMA1_REQUEST_JPEG_TX */
#define IS_DMA_BLOCK_HW_REQUEST(MODE) \
(((MODE) == DMA_BREQ_SINGLE_BURST) || \
@@ -840,9 +883,10 @@
(((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT))
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
- (((((~((ATTRIBUTE) & DMA_CHANNEL_ATTR_MASK)) >> 4U) & ((ATTRIBUTE) & DMA_CHANNEL_ATTR_MASK)) == 0U) && \
- ((ATTRIBUTE) != 0U))
+#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
+ (((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \
+ (((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \
+ (((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U)))
#else
#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
(((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \
@@ -850,12 +894,12 @@
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-#define IS_DMA_GLOBAL_ACTIVE_FLAG(INSTANCE, GLOBAL_FLAG) \
+#define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \
(((INSTANCE)->SMISR & (GLOBAL_FLAG)))
-#else
-#define IS_DMA_GLOBAL_ACTIVE_FLAG(INSTANCE, GLOBAL_FLAG) \
- (((INSTANCE)->MISR & (GLOBAL_FLAG)))
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+#define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \
+ (((INSTANCE)->MISR & (GLOBAL_FLAG)))
+
/**
* @}
*/
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma_ex.h
index c5ad706..df9b924 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma_ex.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_dma_ex.h
@@ -6,7 +6,7 @@
**********************************************************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -302,7 +302,9 @@
#define GPDMA1_TRIGGER_LPTIM2_CH2 (14U) /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */
#define GPDMA1_TRIGGER_LPTIM4_OUT (15U) /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */
#define GPDMA1_TRIGGER_COMP1_OUT (16U) /*!< GPDMA1 HW Trigger signal is COMP1_OUT */
+#if defined(COMP2)
#define GPDMA1_TRIGGER_COMP2_OUT (17U) /*!< GPDMA1 HW Trigger signal is COMP2_OUT */
+#endif /* COMP2 */
#define GPDMA1_TRIGGER_RTC_ALRA_TRG (18U) /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */
#define GPDMA1_TRIGGER_RTC_ALRB_TRG (19U) /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */
#define GPDMA1_TRIGGER_RTC_WUT_TRG (20U) /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */
@@ -328,8 +330,48 @@
#define GPDMA1_TRIGGER_LPDMA1_CH3_TCF (41U) /*!< GPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */
#define GPDMA1_TRIGGER_TIM2_TRGO (42U) /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */
#define GPDMA1_TRIGGER_TIM15_TRGO (43U) /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */
+#if defined (TIM3_TRGO_TRIGGER_SUPPORT)
+#define GPDMA1_TRIGGER_TIM3_TRGO (44U) /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */
+#endif /* defined (TRIGGER_TIM3_TRGO_SUPPORT) */
+#if defined (TIM4_TRGO_TRIGGER_SUPPORT)
+#define GPDMA1_TRIGGER_TIM4_TRGO (45U) /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */
+#endif /* defined (TRIGGER_TIM4_TRGO_SUPPORT) */
+#if defined (TIM5_TRGO_TRIGGER_SUPPORT)
+#define GPDMA1_TRIGGER_TIM5_TRGO (46U) /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */
+#endif /* defined (TRIGGER_TIM5_TRGO_SUPPORT) */
+#if defined (LTDC)
+#define GPDMA1_TRIGGER_LTDC_LI (47U) /*!< GPDMA1 HW Trigger signal is LTDC_LI */
+#endif /* defined (LTDC) */
+#if defined (DSI)
+#define GPDMA1_TRIGGER_DSI_TE (48U) /*!< GPDMA1 HW Trigger signal is DSI_TE */
+#define GPDMA1_TRIGGER_DSI_ER (49U) /*!< GPDMA1 HW Trigger signal is DSI_ER */
+#endif /* defined (DSI) */
+#if defined (DMA2D_TRIGGER_SUPPORT)
+#define GPDMA1_TRIGGER_DMA2D_TC (50U) /*!< GPDMA1 HW Trigger signal is DMA2D_TC */
+#define GPDMA1_TRIGGER_DMA2D_CTC (51U) /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */
+#define GPDMA1_TRIGGER_DMA2D_TW (52U) /*!< GPDMA1 HW Trigger signal is DMA2D_TW */
+#endif /* defined (DMA2D_TRIGGER_SUPPORT) */
+#if defined (GPU2D)
+#define GPDMA1_TRIGGER_GPU2D_FLAG0 (53U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG0 */
+#define GPDMA1_TRIGGER_GPU2D_FLAG1 (54U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG1 */
+#define GPDMA1_TRIGGER_GPU2D_FLAG2 (55U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG2 */
+#define GPDMA1_TRIGGER_GPU2D_FLAG3 (56U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG3 */
+#endif /* defined (GPU2D) */
#define GPDMA1_TRIGGER_ADC4_AWD1 (57U) /*!< GPDMA1 HW Trigger signal is ADC4_AWD1 */
#define GPDMA1_TRIGGER_ADC1_AWD1 (58U) /*!< GPDMA1 HW Trigger signal is ADC1_AWD1 */
+#if defined (GFXTIM)
+#define GPDMA1_TRIGGER_GFXTIM_EVT3 (59U) /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT3 */
+#define GPDMA1_TRIGGER_GFXTIM_EVT2 (60U) /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT2 */
+#define GPDMA1_TRIGGER_GFXTIM_EVT1 (61U) /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT1 */
+#define GPDMA1_TRIGGER_GFXTIM_EVT0 (62U) /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT0 */
+#endif /* defined (GFXTIM) */
+#if defined (JPEG)
+#define GPDMA1_TRIGGER_JPEG_EOC (63U) /*!< GPDMA1 HW Trigger signal is JPEG_EOC */
+#define GPDMA1_TRIGGER_JPEG_IFNF (64U) /*!< GPDMA1 HW Trigger signal is JPEG_IFNF */
+#define GPDMA1_TRIGGER_JPEG_IFT (65U) /*!< GPDMA1 HW Trigger signal is JPEG_IFT */
+#define GPDMA1_TRIGGER_JPEG_OFNE (66U) /*!< GPDMA1 HW Trigger signal is JPEG_OFNE */
+#define GPDMA1_TRIGGER_JPEG_OFT (67U) /*!< GPDMA1 HW Trigger signal is JPEG_OFT */
+#endif /* defined (JPEG) */
/* LPDMA1 triggers */
#define LPDMA1_TRIGGER_EXTI_LINE0 (0U) /*!< LPDMA1 HW Trigger signal is EXTI_LINE0 */
@@ -345,7 +387,9 @@
#define LPDMA1_TRIGGER_LPTIM3_CH1 (10U) /*!< LPDMA1 HW Trigger signal is LPTIM3_CH1 */
#define LPDMA1_TRIGGER_LPTIM4_OUT (11U) /*!< LPDMA1 HW Trigger signal is LPTIM4_OUT */
#define LPDMA1_TRIGGER_COMP1_OUT (12U) /*!< LPDMA1 HW Trigger signal is COMP1_OUT */
+#if defined(COMP2)
#define LPDMA1_TRIGGER_COMP2_OUT (13U) /*!< LPDMA1 HW Trigger signal is COMP2_OUT */
+#endif /* COMP2 */
#define LPDMA1_TRIGGER_RTC_ALRA_TRG (14U) /*!< LPDMA1 HW Trigger signal is RTC_ALRA_TRG */
#define LPDMA1_TRIGGER_RTC_ALRB_TRG (15U) /*!< LPDMA1 HW Trigger signal is RTC_ALRB_TRG */
#define LPDMA1_TRIGGER_RTC_WUT_TRG (16U) /*!< LPDMA1 HW Trigger signal is RTC_WUT_TRG */
@@ -419,8 +463,8 @@
* @}
*/
-/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List I/O Operation Functions
- * @brief Linked-List I/O Operation Functions
+/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions
+ * @brief Linked-List IO Operation Functions
* @{
*/
HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma);
@@ -564,6 +608,8 @@
#define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */
#define NODE_CLLR_IDX_POS (0x0008U) /* DMA channel node CLLR index position */
+#define NODE_MAXIMUM_SIZE (0x0008U) /* Amount of registers of the node */
+
#define NODE_STATIC_FORMAT (0x0000U) /* DMA channel node static format */
#define NODE_DYNAMIC_FORMAT (0x0001U) /* DMA channel node dynamic format */
@@ -646,8 +692,11 @@
((POLARITY) == DMA_TRIG_POLARITY_RISING) || \
((POLARITY) == DMA_TRIG_POLARITY_FALLING))
-#define IS_DMA_TRIGGER_SELECTION(TRIGGER) \
- ((TRIGGER) <= GPDMA1_TRIGGER_ADC1_AWD1)
+#if defined (GPDMA1_TRIGGER_JPEG_OFT)
+#define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_JPEG_OFT)
+#else
+#define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_ADC1_AWD1)
+#endif /* GPDMA1_TRIGGER_JPEG_OFT */
#define IS_DMA_NODE_TYPE(TYPE) \
(((TYPE) == DMA_LPDMA_LINEAR_NODE) || \
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_flash.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_flash.h
index 752be3a..2c80f85 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_flash.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_flash.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -82,7 +82,7 @@
uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
@ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
- @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST,
+ @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST,
@ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP,
@ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW,
@ref FLASH_OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK,
@@ -325,7 +325,7 @@
#define OB_USER_NRST_STOP 0x00000002U /*!< Reset generated when entering the stop mode */
#define OB_USER_NRST_STDBY 0x00000004U /*!< Reset generated when entering the standby mode */
#define OB_USER_NRST_SHDW 0x00000008U /*!< Reset generated when entering the shutdown mode */
-#define OB_USER_SRAM134_RST 0x00000010U /*!< SRAM1, SRAM3 and SRAM4 erase upon system reset */
+#define OB_USER_SRAM_RST 0x00000010U /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */
#define OB_USER_IWDG_SW 0x00000020U /*!< Independent watchdog selection */
#define OB_USER_IWDG_STOP 0x00000040U /*!< Independent watchdog counter freeze in stop mode */
#define OB_USER_IWDG_STDBY 0x00000080U /*!< Independent watchdog counter freeze in standby mode */
@@ -333,7 +333,9 @@
#define OB_USER_SWAP_BANK 0x00000200U /*!< Swap banks */
#define OB_USER_DUALBANK 0x00000400U /*!< Dual-Bank on 1MB/512kB Flash memory devices */
#define OB_USER_BKPRAM_ECC 0x00000800U /*!< Backup RAM ECC detection and correction enable */
+#if defined(SRAM3_BASE)
#define OB_USER_SRAM3_ECC 0x00001000U /*!< SRAM3 ECC detection and correction enable */
+#endif /* SRAM3_BASE */
#define OB_USER_SRAM2_ECC 0x00002000U /*!< SRAM2 ECC detection and correction enable */
#define OB_USER_SRAM2_RST 0x00004000U /*!< SRAM2 Erase when system reset */
#define OB_USER_NSWBOOT0 0x00008000U /*!< Software BOOT0 */
@@ -390,13 +392,13 @@
* @}
*/
-/** @defgroup FLASH_OB_USER_SRAM134_RST FLASH Option Bytes User SRAM134 Erase On Reset Type
+/** @defgroup FLASH_OB_USER_SRAM_RST FLASH Option Bytes User SRAM Erase On Reset Type
* @{
*/
-#define OB_SRAM134_RST_ERASE 0x00000000U /*!< SRAM1, SRAM3 and SRAM4 erased
- when a system reset occurs */
-#define OB_SRAM134_RST_NOT_ERASE FLASH_OPTR_SRAM134_RST /*!< SRAM1, SRAM3 and SRAM4 are not erased
- when a system reset occurs */
+#define OB_SRAM_RST_ERASE 0x00000000U /*!< All SRAMs (except SRAM2 and BKPSRAM) erased
+ when a system reset occurs */
+#define OB_SRAM_RST_NOT_ERASE FLASH_OPTR_SRAM_RST /*!< All SRAMs (except SRAM2 and BKPSRAM) not erased
+ when a system reset occurs */
/**
* @}
*/
@@ -1021,7 +1023,7 @@
#define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
-#define IS_OB_USER_SRAM134_RST(VALUE) (((VALUE) == OB_SRAM134_RST_ERASE) || ((VALUE) == OB_SRAM134_RST_NOT_ERASE))
+#define IS_OB_USER_SRAM_RST(VALUE) (((VALUE) == OB_SRAM_RST_ERASE) || ((VALUE) == OB_SRAM_RST_NOT_ERASE))
#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_flash_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_flash_ex.h
index 2324ab7..879efc6 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_flash_ex.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_flash_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio.h
index 95ac2be..6d9c019 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -279,6 +279,9 @@
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
+#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \
+ (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u)
+
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
@@ -340,8 +343,9 @@
*/
/* IO operation functions *****************************************************/
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet);
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
@@ -362,7 +366,8 @@
/* IO attributes management functions *****************************************/
void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes);
-HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes);
+HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin,
+ uint32_t *pPinAttributes);
/**
* @}
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio_ex.h
index 2b30d18..e36532d 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio_ex.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gpio_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -51,7 +51,6 @@
*/
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
* @{
*/
@@ -60,189 +59,18 @@
* @{
*/
-#if (defined(STM32U575xx) || defined(STM32U585xx))
-/*--------------STM32U575xx/STM32U585xx---------------------------*/
/**
* @brief AF 0 selection
*/
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_RTC_50HZ ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */
#define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */
+#define GPIO_AF0_CRS ((uint8_t)0x00) /* CRS Alternate Function mapping */
#define GPIO_AF0_SRDSTOP ((uint8_t)0x00) /* SRDSTOP Alternate Function mapping */
-#define GPIO_AF0_CRS ((uint8_t)0x00) /* CRS Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
-#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */
-#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
-#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
-#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /* LPTIM2 Alternate Function mapping */
-#define GPIO_AF2_LPTIM3 ((uint8_t)0x02) /* LPTIM3 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */
-#define GPIO_AF3_OCTOSPI1 ((uint8_t)0x03) /* OCTOSPI1 Alternate Function mapping */
-#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */
-#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */
-#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
-#define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */
-#define GPIO_AF3_ADF1 ((uint8_t)0x03) /* ADF1 Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
-#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
-#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
-#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */
-#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */
-#define GPIO_AF4_LPTIM3 ((uint8_t)0x04) /* LPTIM3 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_DFSDM1 ((uint8_t)0x05) /* DFSDM1 Alternate Function mapping */
-#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */
-#define GPIO_AF5_PSSI ((uint8_t)0x05) /* PSSI Alternate Function mapping */
-#define GPIO_AF5_OCTOSPI1 ((uint8_t)0x05) /* OCTOSPI1 Alternate Function mapping */
-#define GPIO_AF5_OCTOSPI2 ((uint8_t)0x05) /* OCTOSPI2 Alternate Function mapping */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
-#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */
-#define GPIO_AF5_MDF1 ((uint8_t)0x05) /* MDF1 Alternate Function mapping */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_OCTOSPI1 ((uint8_t)0x06) /* OCTOSPI1 Alternate Function mapping */
-#define GPIO_AF6_OCTOSPI2 ((uint8_t)0x06) /* OCTOSPI2 Alternate Function mapping */
-#define GPIO_AF6_MDF1 ((uint8_t)0x06) /* MDF1 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
-#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
-#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
-#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
-#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */
-#define GPIO_AF10_PSSI ((uint8_t)0x0A) /* PSSI Alternate Function mapping */
-#define GPIO_AF10_USB ((uint8_t)0x0A) /* USB Alternate Function mapping */
-#define GPIO_AF10_OCTOSPI1 ((uint8_t)0x0A) /* OCTOSPI1 Alternate Function mapping */
-#define GPIO_AF10_OCTOSPI2 ((uint8_t)0x0A) /* OCTOSPI2 Alternate Function mapping */
-#define GPIO_AF10_CRS ((uint8_t)0x0A) /* CRS Alternate Function mapping */
-
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_UCPD1 ((uint8_t)0x0B) /* UCPD1 Alternate Function mapping */
-#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /*!< SDMMC2 Alternate Function mapping */
-#define GPIO_AF11_LPGPIO ((uint8_t)0x0B) /* LPGPIO Alternate Function mapping */
-#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
-#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
-#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
-#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
-#define GPIO_AF12_SDMMC2 ((uint8_t)0x0C) /* SDMMC2 Alternate Function mapping */
-
-/**
- * @brief AF 13 selection
- */
-#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
-#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */
-#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF13_LPTIM4 ((uint8_t)0x0D) /* LPTIM4 Alternate Function mapping */
-#define GPIO_AF13_LPTIM2 ((uint8_t)0x0D) /* LPTIM2 Alternate Function mapping */
-
-/**
- * @brief AF 14 selection
- */
-#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
-#define GPIO_AF14_LPTIM3 ((uint8_t)0x0E) /* LPTIM3 Alternate Function mapping */
-#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
-#define GPIO_AF14_TIM8_COMP2 ((uint8_t)0x0E) /* TIM8/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
-#define GPIO_AF14_TIM15_COMP1 ((uint8_t)0x0E) /* TIM15/COMP1 Alternate Function mapping */
-#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
-#define GPIO_AF14_TIM16_COMP1 ((uint8_t)0x0E) /* TIM16/COMP1 Alternate Function mapping */
-#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */
-#define GPIO_AF14_TIM17_COMP1 ((uint8_t)0x0E) /* TIM17/COMP1 Alternate Function mapping */
-#define GPIO_AF14_SDMMC2 ((uint8_t)0x0E) /* SDMMC2 Alternate Function mapping */
-
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
-
-#elif (defined(STM32U599xx) || defined(STM32U5A9xx) || defined(STM32U595xx) || defined(STM32U5A5xx))
-
-/*--------------STM32U5xxxx---*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
-#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */
-#define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */
-#define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */
-#define GPIO_AF0_S2DSTOP ((uint8_t)0x00) /* S2DSTOP Alternate Function mapping */
-#define GPIO_AF0_CRS ((uint8_t)0x00) /* CRS Alternate Function mapping */
/**
* @brief AF 1 selection
@@ -265,8 +93,15 @@
#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF2_LPTIM3 ((uint8_t)0x02) /* LPTIM3 Alternate Function mapping */
-#define GPIO_AF2_I2C5 ((uint8_t)0x02) /* I2C4 Alternate Function mapping */
-#define GPIO_AF2_I2C6 ((uint8_t)0x02) /* I2C4 Alternate Function mapping */
+#if defined(I2C5)
+#define GPIO_AF2_I2C5 ((uint8_t)0x02) /* I2C5 Alternate Function mapping */
+#endif /* I2C5 */
+#if defined(I2C6)
+#define GPIO_AF2_I2C6 ((uint8_t)0x02) /* I2C6 Alternate Function mapping */
+#endif /* I2C6 */
+#if defined(GFXTIM)
+#define GPIO_AF2_GFXTIM ((uint8_t)0x02) /* GFXTIM Alternate Function mapping */
+#endif /* GFXTIM */
/**
* @brief AF 3 selection
@@ -275,14 +110,19 @@
#define GPIO_AF3_OCTOSPI1 ((uint8_t)0x03) /* OCTOSPI1 Alternate Function mapping */
#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */
#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */
+#define GPIO_AF3_TIM1 ((uint8_t)0x03) /* TIM1 Alternate Function mapping */
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
#define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */
#define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */
#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */
+#if defined(USART2)
#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */
+#endif /* USART2 */
#define GPIO_AF3_ADF1 ((uint8_t)0x03) /* ADF1 Alternate Function mapping */
+#if defined(USB_OTG_HS)
#define GPIO_AF3_USB_HS ((uint8_t)0x03) /* USB_HS Alternate Function mapping */
+#endif /* USB_OTG_HS */
/**
* @brief AF 4 selection
@@ -291,39 +131,56 @@
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
-#define GPIO_AF4_I2C5 ((uint8_t)0x04) /* I2C5 Alternate Function mapping */
#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */
#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */
#define GPIO_AF4_LPTIM3 ((uint8_t)0x04) /* LPTIM3 Alternate Function mapping */
+#if defined (I2C5)
+#define GPIO_AF4_I2C5 ((uint8_t)0x04) /* I2C5 Alternate Function mapping */
+#endif /* I2C5 */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */
#define GPIO_AF5_OCTOSPI1 ((uint8_t)0x05) /* OCTOSPI1 Alternate Function mapping */
+#if defined(OCTOSPI2)
#define GPIO_AF5_OCTOSPI2 ((uint8_t)0x05) /* OCTOSPI2 Alternate Function mapping */
+#endif /* OCTOSPI2 */
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */
#define GPIO_AF5_MDF1 ((uint8_t)0x05) /* MDF1 Alternate Function mapping */
+#define GPIO_AF5_PSSI ((uint8_t)0x05) /* PSSI Alternate Function mapping */
+#if defined(GFXTIM)
+#define GPIO_AF5_GFXTIM ((uint8_t)0x05) /* GFXTIM Alternate Function mapping */
+#endif /* GFXTIM */
/**
* @brief AF 6 selection
*/
-#define GPIO_AF6_I2C3 ((uint8_t)0x05) /* I2C3 Alternate Function mapping */
+#define GPIO_AF6_OCTOSPI1 ((uint8_t)0x06) /* OCTOSPI1 Alternate Function mapping */
+#if defined(OCTOSPI2)
#define GPIO_AF6_OCTOSPI2 ((uint8_t)0x06) /* OCTOSPI2 Alternate Function mapping */
+#endif /* OCTOPSI2 */
#define GPIO_AF6_MDF1 ((uint8_t)0x06) /* MDF1 Alternate Function mapping */
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
+#define GPIO_AF6_I2C3 ((uint8_t)0x06) /* I2C3 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#if defined(USART2)
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#endif /* USART2 */
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#if defined(USART6)
#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */
+#endif /* USART6 */
+#if defined(LTDC)
#define GPIO_AF7_LTDC ((uint8_t)0x07) /* LTDC Alternate Function mapping */
+#endif /* LTDC */
/**
* @brief AF 8 selection
@@ -332,8 +189,15 @@
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
+#if defined(SDMMC2)
+#define GPIO_AF8_SDMMC2 ((uint8_t)0x08) /* SDMMC2 Alternate Function mapping */
+#endif /* SDMMC2 */
+#if defined(LTDC)
#define GPIO_AF8_LTDC ((uint8_t)0x08) /* LTDC Alternate Function mapping */
+#endif /* LTDC */
+#if defined(HSPI1)
#define GPIO_AF8_HSPI1 ((uint8_t)0x08) /* HSPI1 Alternate Function mapping */
+#endif /* HSPI1 */
/**
* @brief AF 9 selection
@@ -348,38 +212,68 @@
#define GPIO_AF10_PSSI ((uint8_t)0x0A) /* PSSI Alternate Function mapping */
#define GPIO_AF10_USB ((uint8_t)0x0A) /* USB Alternate Function mapping */
#define GPIO_AF10_OCTOSPI1 ((uint8_t)0x0A) /* OCTOSPI1 Alternate Function mapping */
+#if defined(OCTOSPI2)
#define GPIO_AF10_OCTOSPI2 ((uint8_t)0x0A) /* OCTOSPI2 Alternate Function mapping */
+#endif /* OCTOSPI2 */
#define GPIO_AF10_CRS ((uint8_t)0x0A) /* CRS Alternate Function mapping */
+#if defined(USB_OTG_HS)
#define GPIO_AF10_USB_HS ((uint8_t)0x0A) /* USB_HS Alternate Function mapping */
+#endif /* USB_OTG_HS */
+#if defined(DSI)
+#define GPIO_AF10_DSI ((uint8_t)0x0A) /* DSI Alternate Function mapping */
+#endif /* DSI */
+#if defined(GFXTIM)
+#define GPIO_AF10_GFXTIM ((uint8_t)0x0A) /* GFXTIM Alternate Function mapping */
+#endif /* GFXTIM */
/**
* @brief AF 11 selection
*/
+#if defined(UCPD1)
#define GPIO_AF11_UCPD1 ((uint8_t)0x0B) /* UCPD1 Alternate Function mapping */
-#define GPIO_AF11_LPGPIO ((uint8_t)0x0B) /* LPGPIO Alternate Function mapping */
+#endif /* UCPD1 */
+#if defined(SDMMC2)
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */
+#endif /* SDMMC2 */
+#define GPIO_AF11_LPGPIO1 ((uint8_t)0x0B) /* LPGPIO1 Alternate Function mapping */
+#if defined(FMC_BASE)
+#define GPIO_AF11_FMC ((uint8_t)0x0B) /* FMC Alternate Function mapping */
+#endif /* FMC_BASE */
+#if defined(DSI)
#define GPIO_AF11_DSI ((uint8_t)0x0B) /* DSI Alternate Function mapping */
+#endif /* DSI */
+#if defined(GFXTIM)
+#define GPIO_AF11_GFXTIM ((uint8_t)0x0B) /* GFXTIM Alternate Function mapping */
+#endif /* GFXTIM */
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
+#if defined(FMC_BASE)
#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
+#endif /* FMC_BASE */
#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */
#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */
#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
+#if defined(SDMMC2)
#define GPIO_AF12_SDMMC2 ((uint8_t)0x0C) /* SDMMC2 Alternate Function mapping */
+#endif /* SDMMC2 */
/**
* @brief AF 13 selection
*/
#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
+#if defined(SAI2)
#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */
-#define GPIO_AF13_RNG ((uint8_t)0x0D) /* RNG Alternate Function mapping */
+#endif /* SAI2 */
#define GPIO_AF13_LPTIM4 ((uint8_t)0x0D) /* LPTIM4 Alternate Function mapping */
#define GPIO_AF13_LPTIM2 ((uint8_t)0x0D) /* LPTIM2 Alternate Function mapping */
+#if defined(GFXTIM)
+#define GPIO_AF13_GFXTIM ((uint8_t)0x0D) /* GFXTIM Alternate Function mapping */
+#endif /* GFXTIM */
/**
* @brief AF 14 selection
@@ -393,7 +287,9 @@
#define GPIO_AF14_TIM16_COMP1 ((uint8_t)0x0E) /* TIM16/COMP1 Alternate Function mapping */
#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */
#define GPIO_AF14_TIM17_COMP1 ((uint8_t)0x0E) /* TIM17/COMP1 Alternate Function mapping */
-
+#if defined(FMC_BASE)
+#define GPIO_AF14_FMC ((uint8_t)0x0E) /* FMC Alternate Function mapping */
+#endif /* FMC_BASE */
/**
* @brief AF 15 selection
@@ -402,8 +298,6 @@
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
-#endif /* (defined(STM32U575xx) || defined(STM32U585xx)) */
-
/**
* @}
*/
@@ -420,12 +314,10 @@
/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
* @{
*/
-#if (defined(STM32U575xx) || defined(STM32U585xx))
/* GPIO_Peripheral_Memory_Mapping Peripheral Memory Mapping */
#define GPIO_GET_INDEX(__GPIOx__) (((uint32_t )(__GPIOx__) & (~GPIOA_BASE)) >> 10)
-#endif /* (defined(STM32U575xx) || defined(STM32U585xx)) */
/**
* @}
*/
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gtzc.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gtzc.h
index 6faf06d..4e88ffd 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gtzc.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_gtzc.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -42,19 +42,25 @@
*/
/*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */
-#define GTZC_MCPBB_NB_VCTR_REG_MAX (32U)
-#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX (1U)
+#if defined (SRAM5_BASE)
+#define GTZC_MPCBB_NB_VCTR_REG_MAX (52U) /* Up to 52 super-blocks */
+#define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX (2U) /* More than one 32-bit needed */
+#else
+#define GTZC_MPCBB_NB_VCTR_REG_MAX (32U) /* Up to 32 super-blocks */
+#define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX (1U) /* One 32-bit needed */
+#endif /* SRAM5_BASE */
+
typedef struct
{
- uint32_t MPCBB_SecConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for
+ uint32_t MPCBB_SecConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for
a super-block. Each bit corresponds to a block
inside the super-block. 0 means non-secure,
1 means secure */
- uint32_t MPCBB_PrivConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for
+ uint32_t MPCBB_PrivConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for
a super-block. Each bit corresponds to a block
inside the super-block. 0 means non-privilege,
1 means privilege */
- uint32_t MPCBB_LockConfig_array[GTZC_MCPBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of
+ uint32_t MPCBB_LockConfig_array[GTZC_MPCBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of
a super-block (32 blocks). 0 means unlocked,
1 means locked */
} MPCBB_Attribute_ConfigTypeDef;
@@ -191,7 +197,9 @@
#define GTZC_PERIPH_WWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos)
#define GTZC_PERIPH_IWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos)
#define GTZC_PERIPH_SPI2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos)
+#if defined (USART2)
#define GTZC_PERIPH_USART2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos)
+#endif /* USART2 */
#define GTZC_PERIPH_USART3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART3_Pos)
#define GTZC_PERIPH_UART4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART4_Pos)
#define GTZC_PERIPH_UART5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART5_Pos)
@@ -201,7 +209,18 @@
#define GTZC_PERIPH_I2C4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C4_Pos)
#define GTZC_PERIPH_LPTIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos)
#define GTZC_PERIPH_FDCAN1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_FDCAN1_Pos)
+#if defined (UCPD1)
#define GTZC_PERIPH_UCPD1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UCPD1_Pos)
+#endif /* UCPD1 */
+#if defined (USART6)
+#define GTZC_PERIPH_USART6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART6_Pos)
+#endif /* USART6 */
+#if defined (I2C5)
+#define GTZC_PERIPH_I2C5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C5_Pos)
+#endif /* I2C5 */
+#if defined (I2C6)
+#define GTZC_PERIPH_I2C6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C6_Pos)
+#endif /* I2C6 */
#define GTZC_PERIPH_TIM1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos)
#define GTZC_PERIPH_SPI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos)
#define GTZC_PERIPH_TIM8 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM8_Pos)
@@ -210,47 +229,113 @@
#define GTZC_PERIPH_TIM16 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos)
#define GTZC_PERIPH_TIM17 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos)
#define GTZC_PERIPH_SAI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos)
+#if defined (SAI2)
#define GTZC_PERIPH_SAI2 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI2_Pos)
+#endif /* SAI2 */
+#if defined (LTDC) || defined (USB_DRD_FS)
+#define GTZC_PERIPH_LTDCUSB (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LTDCUSB_Pos)
+#endif /* LTDC || USB_DRD_FS */
+#if defined (DSI)
+#define GTZC_PERIPH_DSI (GTZC1_PERIPH_REG2 | GTZC_CFGR2_DSI_Pos)
+#endif /* DSI */
+#if defined (GFXTIM)
+#define GTZC_PERIPH_GFXTIM (GTZC1_PERIPH_REG2 | GTZC_CFGR2_GFXTIM_Pos)
+#endif /* GFXTIM */
#define GTZC_PERIPH_MDF1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_MDF1_Pos)
#define GTZC_PERIPH_CORDIC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CORDIC_Pos)
#define GTZC_PERIPH_FMAC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FMAC_Pos)
#define GTZC_PERIPH_CRC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos)
#define GTZC_PERIPH_TSC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_TSC_Pos)
+#if defined (DMA2D)
#define GTZC_PERIPH_DMA2D (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DMA2D_Pos)
+#endif /* DMA2D */
#define GTZC_PERIPH_ICACHE_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos)
#define GTZC_PERIPH_DCACHE1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE1_REG_Pos)
#define GTZC_PERIPH_ADC12 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ADC12_Pos)
-#define GTZC_PERIPH_DCMI (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCMI_Pos)
+#define GTZC_PERIPH_DCMI_PSSI (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCMI_Pos)
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#define GTZC_PERIPH_OTG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OTG_Pos)
+#endif /* (USB_OTG_FS) || (USB_OTG_HS) */
+#if defined (AES)
#define GTZC_PERIPH_AES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_AES_Pos)
+#endif /* AES */
#define GTZC_PERIPH_HASH (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos)
#define GTZC_PERIPH_RNG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos)
+#if defined (PKA)
#define GTZC_PERIPH_PKA (GTZC1_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos)
+#endif /* PKA */
+#if defined (SAES)
#define GTZC_PERIPH_SAES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SAES_Pos)
+#endif /* SAES */
+#if defined (OCTOSPIM)
#define GTZC_PERIPH_OCTOSPIM (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPIM_Pos)
+#endif /* OCTOSPIM */
#define GTZC_PERIPH_SDMMC1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC1_Pos)
+#if defined (SDMMC2)
#define GTZC_PERIPH_SDMMC2 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC2_Pos)
+#endif /* SDMMC2 */
+#if defined (FMC_BASE)
#define GTZC_PERIPH_FSMC_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FSMC_REG_Pos)
+#endif /* FMC_BASE */
#define GTZC_PERIPH_OCTOSPI1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI1_REG_Pos)
+#if defined (OCTOSPI2)
#define GTZC_PERIPH_OCTOSPI2_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI2_REG_Pos)
+#endif /* OCTOSPI2 */
#define GTZC_PERIPH_RAMCFG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos)
+#if defined (GPU2D)
+#define GTZC_PERIPH_GPU2D (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GPU2D_Pos)
+#endif /* GPU2D */
+#if defined (GFXMMU)
+#define GTZC_PERIPH_GFXMMU (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GFXMMU_Pos)
+#define GTZC_PERIPH_GFXMMU_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GFXMMU_REG_Pos)
+#endif /* GFXMMU */
+#if defined (HSPI1)
+#define GTZC_PERIPH_HSPI1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HSPI1_REG_Pos)
+#endif /* HSPI1 */
+#if defined (DCACHE2)
+#define GTZC_PERIPH_DCACHE2_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE2_REG_Pos)
+#endif /* DCACHE2 */
+#if defined (JPEG)
+#define GTZC_PERIPH_JPEG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_JPEG_Pos)
+#endif /* JPEG */
#define GTZC_PERIPH_GPDMA1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos)
#define GTZC_PERIPH_FLASH_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos)
#define GTZC_PERIPH_FLASH (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos)
+#if defined (OTFDEC2)
#define GTZC_PERIPH_OTFDEC2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC2_Pos)
+#endif /* OTFDEC2 */
+#if defined (OTFDEC1)
#define GTZC_PERIPH_OTFDEC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC1_Pos)
+#endif /* OTFDEC1 */
#define GTZC_PERIPH_TZSC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZSC1_Pos)
#define GTZC_PERIPH_TZIC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZIC1_Pos)
#define GTZC_PERIPH_OCTOSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI1_MEM_Pos)
+#if defined (FMC_BASE)
#define GTZC_PERIPH_FSMC_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FSMC_MEM_Pos)
+#endif /* FMC_BASE */
#define GTZC_PERIPH_BKPSRAM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_BKPSRAM_Pos)
+#if defined (OCTOSPI2)
#define GTZC_PERIPH_OCTOSPI2_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI2_MEM_Pos)
+#endif /* OCTOSPI2 */
+#if defined (HSPI1)
+#define GTZC_PERIPH_HSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_HSPI1_MEM_Pos)
+#endif /* HSPI1 */
+#if defined (SRAM6_BASE)
+#define GTZC_PERIPH_SRAM6 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM6_Pos)
+#define GTZC_PERIPH_MPCBB6_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB6_REG_Pos)
+#endif /* SRAM6_BASE */
#define GTZC_PERIPH_SRAM1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM1_Pos)
#define GTZC_PERIPH_MPCBB1_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos)
#define GTZC_PERIPH_SRAM2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos)
#define GTZC_PERIPH_MPCBB2_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos)
+#if defined (SRAM3_BASE)
#define GTZC_PERIPH_SRAM3 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM3_Pos)
+#endif /* SRAM3_BASE */
#define GTZC_PERIPH_MPCBB3_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB3_REG_Pos)
+#if defined (SRAM5_BASE)
+#define GTZC_PERIPH_SRAM5 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM5_Pos)
+#define GTZC_PERIPH_MPCBB5_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB5_REG_Pos)
+#endif /* SRAM5_BASE */
/* GTZC2 */
#define GTZC_PERIPH_SPI3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_SPI3_Pos)
@@ -366,17 +451,17 @@
/* user-oriented definitions for MPCBB */
#define GTZC_MPCBB_BLOCK_SIZE 0x200U /* 512 Bytes */
#define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 16 KBytes */
-#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED (0U)
-#define GTZC_MCPBB_SUPERBLOCK_LOCKED (1U)
+#define GTZC_MPCBB_SUPERBLOCK_UNLOCKED (0U)
+#define GTZC_MPCBB_SUPERBLOCK_LOCKED (1U)
-#define GTZC_MCPBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U)
-#define GTZC_MCPBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U)
-#define GTZC_MCPBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U)
-#define GTZC_MCPBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U)
+#define GTZC_MPCBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U)
+#define GTZC_MPCBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U)
+#define GTZC_MPCBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U)
+#define GTZC_MPCBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U)
/* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */
-#define GTZC_MCPBB_LOCK_OFF (0U)
-#define GTZC_MCPBB_LOCK_ON (1U)
+#define GTZC_MPCBB_LOCK_OFF (0U)
+#define GTZC_MPCBB_LOCK_ON (1U)
/**
* @}
@@ -482,7 +567,7 @@
* @}
*/
-#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/** @addtogroup GTZC_Exported_Functions_Group2
* @brief MPCWM Initialization and Configuration functions
@@ -490,7 +575,7 @@
*/
HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,
- MPCWM_ConfigTypeDef *pMPCWM_Desc);
+ const MPCWM_ConfigTypeDef *pMPCWM_Desc);
HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,
MPCWM_ConfigTypeDef *pMPCWM_Desc);
/**
@@ -503,45 +588,45 @@
*/
void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance);
-uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSC_Instance);
+uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance);
/**
* @}
*/
-#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/** @addtogroup GTZC_Exported_Functions_Group4
* @brief MPCBB Initialization and Configuration functions
* @{
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
- MPCBB_ConfigTypeDef *pMPCBB_desc);
+ const MPCBB_ConfigTypeDef *pMPCBB_desc);
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
MPCBB_ConfigTypeDef *pMPCBB_desc);
HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
uint32_t NbBlocks,
- uint32_t *pMemAttributes);
+ const uint32_t *pMemAttributes);
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
uint32_t NbBlocks,
uint32_t *pMemAttributes);
-#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
uint32_t NbSuperBlocks,
- uint32_t *pLockAttributes);
+ const uint32_t *pLockAttributes);
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
uint32_t NbSuperBlocks,
uint32_t *pLockAttributes);
HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress);
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,
uint32_t *pLockState);
-#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @}
*/
-#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/** @addtogroup GTZC_Exported_Functions_Group5
* @brief TZIC functions
@@ -569,7 +654,7 @@
* @}
*/
-#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @}
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash.h
index 04478e7..cbc876b 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -628,3 +628,4 @@
#endif /* STM32U5xx_HAL_HASH_H */
+
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash_ex.h
index 170d085..66b4610 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash_ex.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_hash_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -173,3 +173,4 @@
#endif /* STM32U5xx_HAL_HASH_EX_H */
+
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c.h
index 055e368..7ebaa0c 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -814,8 +814,8 @@
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
(~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
- (I2C_CR2_ADD10) | (I2C_CR2_START)) & \
- (~I2C_CR2_RD_WRN)))
+ (I2C_CR2_ADD10) | (I2C_CR2_START) | \
+ (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c_ex.h
index a07779e..9ad1581 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c_ex.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_i2c_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h
index 823ef79..fcaa3ae 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_icache.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_ospi.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_ospi.h
index 8d94c4b..d90709b 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_ospi.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_ospi.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -243,6 +243,7 @@
This parameter can be any value between 0 and 0xFFFF */
} OSPI_MemoryMappedTypeDef;
+#if defined (OCTOSPIM)
/**
* @brief HAL OSPI IO Manager Configuration structure definition
*/
@@ -262,6 +263,7 @@
if some signals are multiplexed in the OSPI IO Manager with the other OSPI.
This parameter can be a value between 1 and 256 */
} OSPIM_CfgTypeDef;
+#endif /*(OCTOSPIM)*/
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
/**
@@ -338,7 +340,7 @@
* @{
*/
#define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */
-#define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */
+#define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DMM) /*!< Dual-Quad mode enabled */
/**
* @}
*/
@@ -427,7 +429,7 @@
* @{
*/
#define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */
-#define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL) /*!< FLASH 2 selected */
+#define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_MSEL) /*!< FLASH 2 selected */
/**
* @}
*/
@@ -654,6 +656,7 @@
* @}
*/
+#if defined (OCTOSPIM)
/** @defgroup OSPIM_IOPort OSPI IO Manager IO Port
* @{
*/
@@ -677,6 +680,7 @@
/**
* @}
*/
+#endif /*(OCTOSPIM)*/
/**
* @}
*/
@@ -749,7 +753,7 @@
* @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR,(__INTERRUPT__)) \
+#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\
== (__INTERRUPT__))
/**
@@ -865,15 +869,16 @@
HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi);
HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi);
HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold);
-uint32_t HAL_OSPI_GetFifoThreshold(OSPI_HandleTypeDef *hospi);
+uint32_t HAL_OSPI_GetFifoThreshold(const OSPI_HandleTypeDef *hospi);
HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout);
-uint32_t HAL_OSPI_GetError(OSPI_HandleTypeDef *hospi);
-uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi);
+uint32_t HAL_OSPI_GetError(const OSPI_HandleTypeDef *hospi);
+uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi);
/**
* @}
*/
+#if defined (OCTOSPIM)
/* OSPI IO Manager configuration function ************************************/
/** @addtogroup OSPI_Exported_Functions_Group4
* @{
@@ -884,13 +889,14 @@
* @}
*/
+#endif /*(OCTOSPIM)*/
/* OSPI Delay Block function ************************************/
/** @addtogroup OSPI_Exported_Functions_Group5 Delay Block function
* @{
*/
HAL_StatusTypeDef HAL_OSPI_DLYB_SetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg);
-HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg);
+HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(const OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg);
HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg);
/**
@@ -899,11 +905,6 @@
/**
* @}
*/
-
-/**
- * @}
- */
-
/* End of exported functions -------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
@@ -1048,6 +1049,7 @@
((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED))
#define IS_OSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U)
+#if defined(OCTOSPIM)
#define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
@@ -1074,6 +1076,7 @@
#if defined (OCTOSPIM_CR_MUXEN)
#define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U))
#endif /*(OCTOSPIM_CR_MUXEN)*/
+#endif /*(OCTOSPIM)*/
/**
@endcond
*/
@@ -1095,4 +1098,3 @@
#endif
#endif /* STM32U5xx_HAL_OSPI_H */
-
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pka.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pka.h
index d90d3c4..fc7e844 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pka.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pka.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -627,8 +627,8 @@
* @{
*/
/* Peripheral State and Error functions ***************************************/
-HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka);
-uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka);
+HAL_PKA_StateTypeDef HAL_PKA_GetState(const PKA_HandleTypeDef *hpka);
+uint32_t HAL_PKA_GetError(const PKA_HandleTypeDef *hpka);
/**
* @}
*/
@@ -652,4 +652,3 @@
#endif
#endif /* STM32U5xx_HAL_PKA_H */
-
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr.h
index aef40b9..99450ce 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -138,6 +138,9 @@
#define PWR_FLAG_TEMPH (0x0CU) /*!< Temperature level flag (versus high threshold) */
#define PWR_FLAG_TEMPL (0x0DU) /*!< Temperature level flag (versus low threshold) */
#define PWR_FLAG_VBATH (0x0EU) /*!< Backup domain voltage level flag (versus high threshold) */
+#if defined (PWR_VOSR_USBBOOSTRDY)
+#define PWR_FLAG_USBBOOSTRDY (0x0FU) /*!< USB EPOD booster ready flag */
+#endif /* defined (PWR_VOSR_USBBOOSTRDY) */
/**
* @}
*/
@@ -307,6 +310,11 @@
* @arg @ref PWR_FLAG_BOOSTRDY : EPOD booster ready flag.
* Indicates that EPOD booster ready,
* frequency could be higher than 50 MHz.
+ * @arg @ref PWR_FLAG_USBBOOSTRDY : USB EPOD booster ready flag.
+ * Indicates that USB EPOD booster ready,
+ * frequency could be higher than 50 MHz.
+ * This flag is available only for STM32U59xxx and STM32U5Axxx
+ * devices.
* @arg @ref PWR_FLAG_STOPF : Stop flag.
* Indicates that the device was resumed from Stop mode.
* @arg @ref PWR_FLAG_SBF : Standby flag.
@@ -356,8 +364,35 @@
* Indicates that a wakeup event was received from the WKUP line 8.
* @retval The state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_PWR_GET_FLAG(__FLAG__) \
- ( \
+#if defined (PWR_FLAG_USBBOOSTRDY)
+#define __HAL_PWR_GET_FLAG(__FLAG__) \
+ ( \
+ ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == PWR_VOSR_VOSRDY) : \
+ ((__FLAG__) == PWR_FLAG_BOOSTRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == PWR_VOSR_BOOSTRDY) : \
+ ((__FLAG__) == PWR_FLAG_USBBOOSTRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTRDY) == PWR_VOSR_USBBOOSTRDY) : \
+ ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF) == PWR_SR_STOPF) : \
+ ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->SR, PWR_SR_SBF) == PWR_SR_SBF) : \
+ ((__FLAG__) == PWR_FLAG_VDDA2RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA2RDY) == PWR_SVMSR_VDDA2RDY) : \
+ ((__FLAG__) == PWR_FLAG_VDDA1RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA1RDY) == PWR_SVMSR_VDDA1RDY) : \
+ ((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDIO2RDY) == PWR_SVMSR_VDDIO2RDY) : \
+ ((__FLAG__) == PWR_FLAG_VDDUSBRDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDUSBRDY) == PWR_SVMSR_VDDUSBRDY) : \
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == PWR_SVMSR_ACTVOSRDY) : \
+ ((__FLAG__) == PWR_FLAG_PVDO) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == PWR_SVMSR_PVDO) : \
+ ((__FLAG__) == PWR_FLAG_REGS) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == PWR_SVMSR_REGS) : \
+ ((__FLAG__) == PWR_FLAG_TEMPH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == PWR_BDSR_TEMPH) : \
+ ((__FLAG__) == PWR_FLAG_TEMPL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == PWR_BDSR_TEMPL) : \
+ ((__FLAG__) == PWR_FLAG_VBATH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == PWR_BDSR_VBATH) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == PWR_WUSR_WUF1) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == PWR_WUSR_WUF2) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == PWR_WUSR_WUF3) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == PWR_WUSR_WUF4) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == PWR_WUSR_WUF5) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == PWR_WUSR_WUF6) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == PWR_WUSR_WUF7) : \
+ (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8))
+#else
+#define __HAL_PWR_GET_FLAG(__FLAG__) \
+ ( \
((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == PWR_VOSR_VOSRDY) : \
((__FLAG__) == PWR_FLAG_BOOSTRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == PWR_VOSR_BOOSTRDY) : \
((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF) == PWR_SR_STOPF) : \
@@ -380,6 +415,7 @@
((__FLAG__) == PWR_WAKEUP_FLAG6) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == PWR_WUSR_WUF6) : \
((__FLAG__) == PWR_WAKEUP_FLAG7) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == PWR_WUSR_WUF7) : \
(READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8))
+#endif /* defined (PWR_FLAG_USBBOOSTRDY) */
/** @brief Clear PWR flags.
* @param __FLAG__ : Specifies the flag to clear.
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr_ex.h
index 538d76c..d3e3a00 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr_ex.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_pwr_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -103,42 +103,117 @@
* @{
*/
/* SRAM1 pages retention defines */
-#define PWR_SRAM1_PAGE1_STOP_RETENTION (SRAM1_ID | PAGE01_ID) /*!< SRAM1 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
-#define PWR_SRAM1_PAGE2_STOP_RETENTION (SRAM1_ID | PAGE02_ID) /*!< SRAM1 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
-#define PWR_SRAM1_PAGE3_STOP_RETENTION (SRAM1_ID | PAGE03_ID) /*!< SRAM1 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
-#define PWR_SRAM1_FULL_STOP_RETENTION (SRAM1_ID | 0x07U) /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM1_PAGE1_STOP (SRAM1_ID | PAGE01_ID) /*!< SRAM1 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM1_PAGE2_STOP (SRAM1_ID | PAGE02_ID) /*!< SRAM1 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM1_PAGE3_STOP (SRAM1_ID | PAGE03_ID) /*!< SRAM1 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#if defined (PWR_CR4_SRAM1PDS4)
+#define PWR_SRAM1_PAGE4_STOP (SRAM1_ID | PAGE04_ID) /*!< SRAM1 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM1_PAGE5_STOP (SRAM1_ID | PAGE05_ID) /*!< SRAM1 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM1_PAGE6_STOP (SRAM1_ID | PAGE06_ID) /*!< SRAM1 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM1_PAGE7_STOP (SRAM1_ID | PAGE07_ID) /*!< SRAM1 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM1_PAGE8_STOP (SRAM1_ID | PAGE08_ID) /*!< SRAM1 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM1_PAGE9_STOP (SRAM1_ID | PAGE09_ID) /*!< SRAM1 page 9 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM1_PAGE10_STOP (SRAM1_ID | PAGE10_ID) /*!< SRAM1 page 10 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM1_PAGE11_STOP (SRAM1_ID | PAGE11_ID) /*!< SRAM1 page 11 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM1_PAGE12_STOP (SRAM1_ID | PAGE12_ID) /*!< SRAM1 page 12 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM1_FULL_STOP (SRAM1_ID | 0x0FFFU) /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */
+#else
+#define PWR_SRAM1_FULL_STOP (SRAM1_ID | 0x07U) /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */
+#endif /* defined (PWR_CR4_SRAM1PDS4) */
/* SRAM2 pages retention defines */
-#define PWR_SRAM2_PAGE1_STOP_RETENTION (SRAM2_ID | PAGE01_ID) /*!< SRAM2 page 1 (8 KB) retention in Stop modes (Stop 0, 1, 2) */
-#define PWR_SRAM2_PAGE2_STOP_RETENTION (SRAM2_ID | PAGE02_ID) /*!< SRAM2 page 2 (54 KB) retention in Stop modes (Stop 0, 1, 2) */
-#define PWR_SRAM2_FULL_STOP_RETENTION (SRAM2_ID | 0x03U) /*!< SRAM2 all pages retention in Stop modes (Stop 0, 1, 2) */
+#define PWR_SRAM2_PAGE1_STOP (SRAM2_ID | PAGE01_ID) /*!< SRAM2 page 1 (8 KB) retention in Stop modes (Stop 0, 1, 2) */
+#define PWR_SRAM2_PAGE2_STOP (SRAM2_ID | PAGE02_ID) /*!< SRAM2 page 2 (54 KB) retention in Stop modes (Stop 0, 1, 2) */
+#define PWR_SRAM2_FULL_STOP (SRAM2_ID | 0x03U) /*!< SRAM2 all pages retention in Stop modes (Stop 0, 1, 2) */
+#if defined (PWR_CR2_SRAM3PDS1)
/* SRAM3 pages retention defines */
-#define PWR_SRAM3_PAGE1_STOP_RETENTION (SRAM3_ID | PAGE01_ID) /*!< SRAM3 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
-#define PWR_SRAM3_PAGE2_STOP_RETENTION (SRAM3_ID | PAGE02_ID) /*!< SRAM3 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
-#define PWR_SRAM3_PAGE3_STOP_RETENTION (SRAM3_ID | PAGE03_ID) /*!< SRAM3 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
-#define PWR_SRAM3_PAGE4_STOP_RETENTION (SRAM3_ID | PAGE04_ID) /*!< SRAM3 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
-#define PWR_SRAM3_PAGE5_STOP_RETENTION (SRAM3_ID | PAGE05_ID) /*!< SRAM3 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
-#define PWR_SRAM3_PAGE6_STOP_RETENTION (SRAM3_ID | PAGE06_ID) /*!< SRAM3 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
-#define PWR_SRAM3_PAGE7_STOP_RETENTION (SRAM3_ID | PAGE07_ID) /*!< SRAM3 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
-#define PWR_SRAM3_PAGE8_STOP_RETENTION (SRAM3_ID | PAGE08_ID) /*!< SRAM3 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
-#define PWR_SRAM3_FULL_STOP_RETENTION (SRAM3_ID | 0xFFU) /*!< SRAM3 all pages retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE1_STOP (SRAM3_ID | PAGE01_ID) /*!< SRAM3 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE2_STOP (SRAM3_ID | PAGE02_ID) /*!< SRAM3 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE3_STOP (SRAM3_ID | PAGE03_ID) /*!< SRAM3 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE4_STOP (SRAM3_ID | PAGE04_ID) /*!< SRAM3 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE5_STOP (SRAM3_ID | PAGE05_ID) /*!< SRAM3 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE6_STOP (SRAM3_ID | PAGE06_ID) /*!< SRAM3 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE7_STOP (SRAM3_ID | PAGE07_ID) /*!< SRAM3 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE8_STOP (SRAM3_ID | PAGE08_ID) /*!< SRAM3 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#if defined (PWR_CR4_SRAM3PDS9)
+#define PWR_SRAM3_PAGE9_STOP (SRAM3_ID | PAGE09_ID) /*!< SRAM3 page 9 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE10_STOP (SRAM3_ID | PAGE10_ID) /*!< SRAM3 page 10 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE11_STOP (SRAM3_ID | PAGE11_ID) /*!< SRAM3 page 11 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE12_STOP (SRAM3_ID | PAGE12_ID) /*!< SRAM3 page 12 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE13_STOP (SRAM3_ID | PAGE13_ID) /*!< SRAM3 page 13 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_FULL_STOP (SRAM3_ID | 0x1FFFU) /*!< SRAM3 all pages retention in Stop modes (Stop 0, 1, 2, 3) */
+#else
+#define PWR_SRAM3_FULL_STOP (SRAM3_ID | 0xFFU) /*!< SRAM3 all pages retention in Stop modes (Stop 0, 1, 2, 3) */
+#endif /* defined (PWR_CR4_SRAM3PDS9) */
+#endif /* PWR_CR2_SRAM3PDS1 */
/* SRAM4 page retention defines */
-#define PWR_SRAM4_FULL_STOP_RETENTION (SRAM4_ID | PAGE01_ID) /*!< SRAM4 retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM4_FULL_STOP (SRAM4_ID | PAGE01_ID) /*!< SRAM4 retention in Stop modes (Stop 0, 1, 2, 3) */
+
+#if defined (PWR_CR4_SRAM5PDS1)
+/* SRAM5 pages retention defines */
+#define PWR_SRAM5_PAGE1_STOP (SRAM5_ID | PAGE01_ID) /*!< SRAM5 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM5_PAGE2_STOP (SRAM5_ID | PAGE02_ID) /*!< SRAM5 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM5_PAGE3_STOP (SRAM5_ID | PAGE03_ID) /*!< SRAM5 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM5_PAGE4_STOP (SRAM5_ID | PAGE04_ID) /*!< SRAM5 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM5_PAGE5_STOP (SRAM5_ID | PAGE05_ID) /*!< SRAM5 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM5_PAGE6_STOP (SRAM5_ID | PAGE06_ID) /*!< SRAM5 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM5_PAGE7_STOP (SRAM5_ID | PAGE07_ID) /*!< SRAM5 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM5_PAGE8_STOP (SRAM5_ID | PAGE08_ID) /*!< SRAM5 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM5_PAGE9_STOP (SRAM5_ID | PAGE09_ID) /*!< SRAM5 page 9 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM5_PAGE10_STOP (SRAM5_ID | PAGE10_ID) /*!< SRAM5 page 10 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM5_PAGE11_STOP (SRAM5_ID | PAGE11_ID) /*!< SRAM5 page 11 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM5_PAGE12_STOP (SRAM5_ID | PAGE12_ID) /*!< SRAM5 page 12 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM5_PAGE13_STOP (SRAM5_ID | PAGE13_ID) /*!< SRAM5 page 13 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM5_FULL_STOP (SRAM5_ID | 0x1FFFU) /*!< SRAM5 all pages retention in Stop modes (Stop 0, 1, 2, 3) */
+#endif /* defined (PWR_CR4_SRAM5PDS1) */
+
+#if defined (PWR_CR5_SRAM6PDS1)
+/* SRAM5 pages retention defines */
+#define PWR_SRAM6_PAGE1_STOP (SRAM6_ID | PAGE01_ID) /*!< SRAM6 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM6_PAGE2_STOP (SRAM6_ID | PAGE02_ID) /*!< SRAM6 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM6_PAGE3_STOP (SRAM6_ID | PAGE03_ID) /*!< SRAM6 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM6_PAGE4_STOP (SRAM6_ID | PAGE04_ID) /*!< SRAM6 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM6_PAGE5_STOP (SRAM6_ID | PAGE05_ID) /*!< SRAM6 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM6_PAGE6_STOP (SRAM6_ID | PAGE06_ID) /*!< SRAM6 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM6_PAGE7_STOP (SRAM6_ID | PAGE07_ID) /*!< SRAM6 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM6_PAGE8_STOP (SRAM6_ID | PAGE08_ID) /*!< SRAM6 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM6_FULL_STOP (SRAM6_ID | 0xFFU) /*!< SRAM6 all pages retention in Stop modes (Stop 0, 1, 2, 3) */
+#endif /* defined (PWR_CR5_SRAM6PDS1) */
/* Cache RAMs retention defines */
-#define PWR_ICACHE_FULL_STOP_RETENTION (ICACHERAM_ID | PAGE01_ID) /*!< ICACHE page retention in Stop modes (Stop 0, 1, 2, 3) */
-#define PWR_DCACHE1_FULL_STOP_RETENTION (DCACHE1RAM_ID | PAGE01_ID) /*!< DCACHE1 page retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_ICACHE_FULL_STOP (ICACHERAM_ID | PAGE01_ID) /*!< ICACHE page retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_DCACHE1_FULL_STOP (DCACHE1RAM_ID | PAGE01_ID) /*!< DCACHE1 page retention in Stop modes (Stop 0, 1, 2, 3) */
+#if defined (PWR_CR2_DC2RAMPDS)
+#define PWR_DCACHE2_FULL_STOP (DCACHE2RAM_ID | PAGE01_ID) /*!< DCACHE2 page retention in Stop modes (Stop 0, 1, 2, 3) */
+#endif /* defined (PWR_CR2_DC2RAMPDS) */
+#if defined (PWR_CR2_DMA2DRAMPDS)
/* DMA2D RAM retention defines */
-#define PWR_DMA2DRAM_FULL_STOP_RETENTION (DMA2DRAM_ID | PAGE01_ID) /*!< DMA2D RAM retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_DMA2DRAM_FULL_STOP (DMA2DRAM_ID | PAGE01_ID) /*!< DMA2D RAM retention in Stop modes (Stop 0, 1, 2, 3) */
+#endif /* PWR_CR2_DMA2DRAMPDS */
/* FMAC, FDCAN and USB RAMs retention defines */
-#define PWR_PERIPHRAM_FULL_STOP_RETENTION (PERIPHRAM_ID | PAGE01_ID) /*!< FMAC, FDCAN and USB RAM retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_PERIPHRAM_FULL_STOP (PERIPHRAM_ID | PAGE01_ID) /*!< FMAC, FDCAN and USB RAM retention in Stop modes (Stop 0, 1, 2, 3) */
/* PKA32 RAM retention defines */
-#define PWR_PKA32RAM_FULL_STOP_RETENTION (PKARAM_ID | PAGE01_ID) /*!< PKA32 RAM retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_PKA32RAM_FULL_STOP (PKARAM_ID | PAGE01_ID) /*!< PKA32 RAM retention in Stop modes (Stop 0, 1, 2, 3) */
+
+#if defined (PWR_CR2_GPRAMPDS)
+/* Graphic peripherals RAM retention defines */
+#define PWR_GRAPHICPRAM_FULL_STOP (GRAPHIPRAM_ID | PAGE01_ID) /*!< LTDC, GFXMMU retention in Stop modes (Stop 0, 1, 2, 3) */
+#endif /* defined (PWR_CR2_GPRAMPDS) */
+
+#if defined (PWR_CR2_DSIRAMPDS)
+/* DSI RAM retention defines */
+#define PWR_DSIRAM_FULL_STOP (DSIRAM_ID | PAGE01_ID) /*!< DSI RAM retention in Stop modes (Stop 0, 1, 2, 3) */
+#endif /* defined (PWR_CR2_DSIRAMPDS) */
+
+#if defined (PWR_CR2_JPEGRAMPDS)
+/* JPEG RAM retention defines */
+#define PWR_JPEGRAM_FULL_STOP (JPEGRAM_ID | PAGE01_ID) /*!< JPEG RAM retention in Stop modes (Stop 0, 1, 2, 3) */
+#endif /* defined (PWR_CR2_JPEGRAMPDS) */
/**
* @}
*/
@@ -148,9 +223,9 @@
* the SRAM2 content is preserved based on the same defines in Stop 3 mode.
* @{
*/
-#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_CR1_RRSB1 /*!< SRAM2 page 1 (8 KB) retention in Stop 3 and Standby modes */
-#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_CR1_RRSB2 /*!< SRAM2 page 2 (54 KB) retention in Stop 3 and Standby modes */
-#define PWR_SRAM2_FULL_STANDBY_RETENTION (PWR_CR1_RRSB1 | PWR_CR1_RRSB2) /*!< SRAM2 all pages retention in Stop 3 and Standby modes */
+#define PWR_SRAM2_PAGE1_STANDBY PWR_CR1_RRSB1 /*!< SRAM2 page 1 (8 KB) retention in Stop 3 and Standby modes */
+#define PWR_SRAM2_PAGE2_STANDBY PWR_CR1_RRSB2 /*!< SRAM2 page 2 (54 KB) retention in Stop 3 and Standby modes */
+#define PWR_SRAM2_FULL_STANDBY (PWR_CR1_RRSB1 | PWR_CR1_RRSB2) /*!< SRAM2 all pages retention in Stop 3 and Standby modes */
/**
* @}
*/
@@ -158,10 +233,18 @@
/** @defgroup PWREx_SRAMx_Contents_Run_Retention PWR Extended SRAM Contents Run Retention
* @{
*/
-#define PWR_SRAM1_FULL_RUN_RETENTION PWR_CR1_SRAM1PD /*!< SRAM1 full retention in Run mode */
-#define PWR_SRAM2_FULL_RUN_RETENTION PWR_CR1_SRAM2PD /*!< SRAM2 full retention in Run mode */
-#define PWR_SRAM3_FULL_RUN_RETENTION PWR_CR1_SRAM3PD /*!< SRAM3 full retention in Run mode */
-#define PWR_SRAM4_FULL_RUN_RETENTION PWR_CR1_SRAM4PD /*!< SRAM4 full retention in Run mode */
+#define PWR_SRAM1_FULL_RUN PWR_CR1_SRAM1PD /*!< SRAM1 full retention in Run mode */
+#define PWR_SRAM2_FULL_RUN PWR_CR1_SRAM2PD /*!< SRAM2 full retention in Run mode */
+#if defined (PWR_CR1_SRAM3PD)
+#define PWR_SRAM3_FULL_RUN PWR_CR1_SRAM3PD /*!< SRAM3 full retention in Run mode */
+#endif /* PWR_CR1_SRAM3PD */
+#define PWR_SRAM4_FULL_RUN PWR_CR1_SRAM4PD /*!< SRAM4 full retention in Run mode */
+#if defined (PWR_CR1_SRAM5PD)
+#define PWR_SRAM5_FULL_RUN PWR_CR1_SRAM5PD /*!< SRAM5 full retention in Run mode */
+#endif /* defined (PWR_CR1_SRAM5PD) */
+#if defined (PWR_CR1_SRAM6PD)
+#define PWR_SRAM6_FULL_RUN PWR_CR1_SRAM6PD /*!< SRAM6 full retention in Run mode */
+#endif /* defined (PWR_CR1_SRAM6PD) */
/**
* @}
*/
@@ -195,15 +278,6 @@
* @}
*/
-/** @defgroup PWREx_VBAT_Battery_Charging_State PWR Extended Battery Charging State
- * @{
- */
-#define PWR_BATTERY_CHARGING_DISABLE (0U) /*!< Disable battery charging */
-#define PWR_BATTERY_CHARGING_ENABLE PWR_BDCR2_VBE /*!< Enable battery charging */
-/**
- * @}
- */
-
/** @defgroup PWREx_GPIO_Port PWR Extended GPIO Port
* @{
*/
@@ -212,10 +286,17 @@
#define PWR_GPIO_C (0x02U) /*!< GPIO port C */
#define PWR_GPIO_D (0x03U) /*!< GPIO port D */
#define PWR_GPIO_E (0x04U) /*!< GPIO port E */
+#if defined (PWR_PUCRF_PU0)
#define PWR_GPIO_F (0x05U) /*!< GPIO port F */
+#endif /* PWR_PUCRF_PU0 */
#define PWR_GPIO_G (0x06U) /*!< GPIO port G */
#define PWR_GPIO_H (0x07U) /*!< GPIO port H */
+#if defined (PWR_PUCRI_PU0)
#define PWR_GPIO_I (0x08U) /*!< GPIO port I */
+#endif /* PWR_PUCRI_PU0 */
+#if defined (PWR_PUCRJ_PU0)
+#define PWR_GPIO_J (0x09U) /*!< GPIO port J */
+#endif /* defined (PWR_PUCRJ_PU0) */
/**
* @}
*/
@@ -674,13 +755,35 @@
#define SRAM_ID_MASK (0xFFFFUL << 16U)
#define SRAM1_ID (0x01UL << 16U)
#define SRAM2_ID (0x01UL << 17U)
+#if defined (PWR_CR2_SRAM3PDS1)
#define SRAM3_ID (0x01UL << 18U)
+#endif /* PWR_CR2_SRAM3PDS1 */
#define SRAM4_ID (0x01UL << 19U)
#define ICACHERAM_ID (0x01UL << 20U)
#define DCACHE1RAM_ID (0x01UL << 21U)
+#if defined (PWR_CR2_DMA2DRAMPDS)
#define DMA2DRAM_ID (0x01UL << 22U)
+#endif /* PWR_CR2_DMA2DRAMPDS */
#define PERIPHRAM_ID (0x01UL << 23U)
#define PKARAM_ID (0x01UL << 24U)
+#if defined (PWR_CR2_DC2RAMPDS)
+#define DCACHE2RAM_ID (0x01UL << 25U)
+#endif /* defined (PWR_CR2_DC2RAMPDS) */
+#if defined (PWR_CR2_GPRAMPDS)
+#define GRAPHIPRAM_ID (0x01UL << 26U)
+#endif /* defined (PWR_CR2_GPRAMPDS) */
+#if defined (PWR_CR2_DSIRAMPDS)
+#define DSIRAM_ID (0x01UL << 27U)
+#endif /* defined (PWR_CR2_DSIRAMPDS) */
+#if defined (PWR_CR4_SRAM5PDS1)
+#define SRAM5_ID (0x01UL << 28U)
+#endif /* defined (PWR_CR4_SRAM5PDS1) */
+#if defined (PWR_CR5_SRAM6PDS1)
+#define SRAM6_ID (0x01UL << 29U)
+#endif /* defined (PWR_CR5_SRAM6PDS1) */
+#if defined (PWR_CR2_JPEGRAMPDS)
+#define JPEGRAM_ID (0x01UL << 30U)
+#endif /* defined (PWR_CR2_JPEGRAMPDS)*/
/* SRAM page retention IDs */
#define PAGE01_ID (0x01UL << 0U)
@@ -698,8 +801,21 @@
#define PAGE13_ID (0x01UL << 12U)
/* All available RAM retention in Run mode define */
-#define PWR_ALL_RAM_RUN_RETENTION_MASK (PWR_SRAM1_FULL_RUN_RETENTION | PWR_SRAM2_FULL_RUN_RETENTION | \
- PWR_SRAM3_FULL_RUN_RETENTION | PWR_SRAM4_FULL_RUN_RETENTION)
+#if defined (PWR_CR1_SRAM6PD)
+#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \
+ PWR_SRAM3_FULL_RUN | PWR_SRAM4_FULL_RUN | \
+ PWR_SRAM5_FULL_RUN | PWR_SRAM6_FULL_RUN)
+#elif defined (PWR_CR1_SRAM5PD)
+#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \
+ PWR_SRAM3_FULL_RUN | PWR_SRAM4_FULL_RUN | \
+ PWR_SRAM5_FULL_RUN)
+#elif defined (PWR_CR2_SRAM3PDS1)
+#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \
+ PWR_SRAM3_FULL_RUN | PWR_SRAM4_FULL_RUN)
+#else
+#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \
+ PWR_SRAM4_FULL_RUN)
+#endif /* defined (PWR_CR1_SRAM5PD) */
/**
* @}
*/
@@ -748,13 +864,21 @@
(((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
-/* Battery charging activation check macro */
-#define IS_PWR_BATTERY_CHARGING(CHARGING) \
- (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
- ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
-
/* GPIO port check macro */
-#define IS_PWR_GPIO_PORT(GPIO_PORT) \
+#if defined (PWR_PUCRJ_PU0)
+#define IS_PWR_GPIO_PORT(GPIO_PORT) \
+ (((GPIO_PORT) == PWR_GPIO_A) ||\
+ ((GPIO_PORT) == PWR_GPIO_B) ||\
+ ((GPIO_PORT) == PWR_GPIO_C) ||\
+ ((GPIO_PORT) == PWR_GPIO_D) ||\
+ ((GPIO_PORT) == PWR_GPIO_E) ||\
+ ((GPIO_PORT) == PWR_GPIO_F) ||\
+ ((GPIO_PORT) == PWR_GPIO_G) ||\
+ ((GPIO_PORT) == PWR_GPIO_H) ||\
+ ((GPIO_PORT) == PWR_GPIO_I) ||\
+ ((GPIO_PORT) == PWR_GPIO_J))
+#elif defined (PWR_PUCRF_PU0) && defined (PWR_PUCRI_PU0)
+#define IS_PWR_GPIO_PORT(GPIO_PORT) \
(((GPIO_PORT) == PWR_GPIO_A) ||\
((GPIO_PORT) == PWR_GPIO_B) ||\
((GPIO_PORT) == PWR_GPIO_C) ||\
@@ -764,6 +888,16 @@
((GPIO_PORT) == PWR_GPIO_G) ||\
((GPIO_PORT) == PWR_GPIO_H) ||\
((GPIO_PORT) == PWR_GPIO_I))
+#else
+#define IS_PWR_GPIO_PORT(GPIO_PORT) \
+ (((GPIO_PORT) == PWR_GPIO_A) ||\
+ ((GPIO_PORT) == PWR_GPIO_B) ||\
+ ((GPIO_PORT) == PWR_GPIO_C) ||\
+ ((GPIO_PORT) == PWR_GPIO_D) ||\
+ ((GPIO_PORT) == PWR_GPIO_E) ||\
+ ((GPIO_PORT) == PWR_GPIO_G) ||\
+ ((GPIO_PORT) == PWR_GPIO_H))
+#endif /* defined (PWR_PUCRJ_PU0) */
/* GPIO pin mask check macro */
#define IS_PWR_GPIO_PIN_MASK(BIT_MASK) \
@@ -771,41 +905,75 @@
/* SRAM2 retention in Standby mode check macro */
#define IS_PWR_SRAM2_STANDBY_RETENTION(CONTENT) \
- (((CONTENT) == PWR_SRAM2_PAGE1_STANDBY_RETENTION) ||\
- ((CONTENT) == PWR_SRAM2_PAGE2_STANDBY_RETENTION) ||\
- ((CONTENT) == PWR_SRAM2_FULL_STANDBY_RETENTION))
+ (((CONTENT) == PWR_SRAM2_PAGE1_STANDBY) ||\
+ ((CONTENT) == PWR_SRAM2_PAGE2_STANDBY) ||\
+ ((CONTENT) == PWR_SRAM2_FULL_STANDBY))
/* RAMs retention in Stop mode check macros */
#define IS_PWR_SRAM1_STOP_RETENTION(RAMCONTENT) \
- ((((RAMCONTENT) & (~PWR_SRAM1_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U))
+ ((((RAMCONTENT) & (~PWR_SRAM1_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U))
#define IS_PWR_SRAM2_STOP_RETENTION(RAMCONTENT) \
- ((((RAMCONTENT) & (~PWR_SRAM2_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U))
+ ((((RAMCONTENT) & (~PWR_SRAM2_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U))
+#if defined (PWR_CR2_SRAM3PDS1)
#define IS_PWR_SRAM3_STOP_RETENTION(RAMCONTENT) \
- ((((RAMCONTENT) & (~PWR_SRAM3_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U))
+ ((((RAMCONTENT) & (~PWR_SRAM3_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U))
+#endif /* PWR_CR2_SRAM3PDS1 */
#define IS_PWR_SRAM4_STOP_RETENTION(RAMCONTENT) \
- ((((RAMCONTENT) & (~PWR_SRAM4_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U))
+ ((((RAMCONTENT) & (~PWR_SRAM4_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U))
+
+#if defined (PWR_CR4_SRAM5PDS1)
+#define IS_PWR_SRAM5_STOP_RETENTION(RAMCONTENT) \
+ ((((RAMCONTENT) & (~PWR_SRAM5_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U))
+#endif /* defined (PWR_CR4_SRAM5PDS1) */
+
+#if defined (PWR_CR5_SRAM6PDS1)
+#define IS_PWR_SRAM6_STOP_RETENTION(RAMCONTENT) \
+ ((((RAMCONTENT) & (~PWR_SRAM6_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U))
+#endif /* defined (PWR_CR5_SRAM6PDS1) */
#define IS_PWR_ICACHE_STOP_RETENTION(RAMCONTENT) \
- ((((RAMCONTENT) & (~PWR_ICACHE_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U))
+ ((((RAMCONTENT) & (~PWR_ICACHE_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U))
#define IS_PWR_DCACHE1_STOP_RETENTION(RAMCONTENT) \
- ((((RAMCONTENT) & (~PWR_DCACHE1_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U))
+ ((((RAMCONTENT) & (~PWR_DCACHE1_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U))
+#if defined (PWR_CR2_DC2RAMPDS)
+#define IS_PWR_DCACHE2_STOP_RETENTION(RAMCONTENT) \
+ ((((RAMCONTENT) & (~PWR_DCACHE2_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U))
+#endif /* defined (PWR_CR2_DC2RAMPDS) */
+
+#if defined (PWR_CR2_DMA2DRAMPDS)
#define IS_PWR_DMA2DRAM_STOP_RETENTION(RAMCONTENT) \
- ((((RAMCONTENT) & (~PWR_DMA2DRAM_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U))
+ ((((RAMCONTENT) & (~PWR_DMA2DRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U))
+#endif /* PWR_CR2_DMA2DRAMPDS */
#define IS_PWR_PERIPHRAM_STOP_RETENTION(RAMCONTENT) \
- ((((RAMCONTENT) & (~PWR_PERIPHRAM_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U))
+ ((((RAMCONTENT) & (~PWR_PERIPHRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U))
#define IS_PWR_PKA32RAM_STOP_RETENTION(RAMCONTENT) \
- ((((RAMCONTENT) & (~PWR_PKA32RAM_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U))
+ ((((RAMCONTENT) & (~PWR_PKA32RAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U))
+
+#if defined (PWR_CR2_GPRAMPDS)
+#define IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMCONTENT) \
+ ((((RAMCONTENT) & (~PWR_GRAPHICPRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U))
+#endif /* defined (PWR_CR2_GPRAMPDS) */
+
+#if defined (PWR_CR2_DSIRAMPDS)
+#define IS_PWR_DSIRAM_STOP_RETENTION(RAMCONTENT) \
+ ((((RAMCONTENT) & (~PWR_DSIRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U))
+#endif /* defined (PWR_CR2_DSIRAMPDS) */
+
+#if defined (PWR_CR2_JPEGRAMPDS)
+#define IS_PWR_JPEGRAM_STOP_RETENTION(RAMCONTENT) \
+ ((((RAMCONTENT) & (~PWR_JPEGRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U))
+#endif /* defined (PWR_CR2_DSIRAMPDS) */
/* RAMs retention in Run mode check macro */
#define IS_PWR_RAM_RUN_RETENTION(RAMCONTENT) \
- ((((RAMCONTENT) & (~PWR_ALL_RAM_RUN_RETENTION_MASK)) == 0U) && ((RAMCONTENT) != 0U))
+ ((((RAMCONTENT) & (~PWR_ALL_RAM_RUN_MASK)) == 0U) && ((RAMCONTENT) != 0U))
/**
* @}
*/
@@ -862,6 +1030,18 @@
void HAL_PWREx_DisableAVM1(void);
void HAL_PWREx_EnableAVM2(void);
void HAL_PWREx_DisableAVM2(void);
+#if defined (PWR_VOSR_USBPWREN)
+HAL_StatusTypeDef HAL_PWREx_EnableUSBHSTranceiverSupply(void);
+void HAL_PWREx_DisableUSBHSTranceiverSupply(void);
+#endif /* defined (PWR_VOSR_USBPWREN) */
+#if defined (PWR_CR1_FORCE_USBPWR)
+void HAL_PWREx_EnableOTGHSPHYLowPowerRetention(void);
+void HAL_PWREx_DisableOTGHSPHYLowPowerRetention(void);
+#endif /* defined (PWR_CR1_FORCE_USBPWR) */
+#if defined (PWR_VOSR_VDD11USBDIS)
+void HAL_PWREx_EnableVDD11USB(void);
+void HAL_PWREx_DisableVDD11USB(void);
+#endif /* defined (PWR_VOSR_VDD11USBDIS) */
HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *pConfigPVM);
void HAL_PWREx_EnableMonitoring(void);
void HAL_PWREx_DisableMonitoring(void);
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc.h
index 176ad63..f82be56 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -61,21 +61,21 @@
uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
This parameter must be a number between Min_Data = 4 and Max_Data = 512 */
- uint32_t PLLP; /*!< PLLP: Division factor for system clock.
- This parameter must be a number between Min_Data = 1 and Max_Data = 128
- odd division factors are not allowed */
+ uint32_t PLLP; /*!< PLLP: Division factor for peripheral clocks.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks.
This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
- uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks.
- This parameter must be a number between Min_Data = 2 and Max_Data = 128 */
+ uint32_t PLLR; /*!< PLLR: Division factor for system clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 128
+ Only division by 1 and even division factors are allowed */
uint32_t PLLRGE; /*!< PLLRGE: PLL1 clock Input range
- This parameter must be a value of @ref RCC_PLL_VCI_Range */
+ This parameter must be a value of @ref RCC_PLL_VCI_Range */
uint32_t PLLFRACN; /*!< PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for
- PLL1 VCO It should be a value between 0 and 32767 */
+ PLL1 VCO It should be a value between 0 and 8191 */
} RCC_PLLInitTypeDef;
@@ -116,7 +116,7 @@
This parameter can be a value of @ref RCC_MSI_Clock_Range */
uint32_t MSIKClockRange; /*!< The MSIK frequency range.
- This parameter can be a value of @ref RCC_MSIk_Clock_Range */
+ This parameter can be a value of @ref RCC_MSIK_Clock_Range */
uint32_t HSI48State; /*!< The new state of the HSI48.
This parameter can be a value of @ref RCC_HSI48_Config */
@@ -324,12 +324,16 @@
* @}
*/
+
+
+
/** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output
* @{
*/
#define RCC_PLL1_DIVP RCC_PLL1CFGR_PLL1PEN
#define RCC_PLL1_DIVQ RCC_PLL1CFGR_PLL1QEN
#define RCC_PLL1_DIVR RCC_PLL1CFGR_PLL1REN
+
/**
* @}
*/
@@ -366,6 +370,7 @@
#define RCC_PLLSOURCE_MSI RCC_PLL1CFGR_PLL1SRC_0
#define RCC_PLLSOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1
#define RCC_PLLSOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1)
+
/**
* @}
*/
@@ -395,26 +400,26 @@
* @}
*/
-/** @defgroup RCC_MSIk_Clock_Range MSIK Clock Range
+/** @defgroup RCC_MSIK_Clock_Range MSIK Clock Range
* @{
*/
-#define RCC_MSIKRANGE_0 0x00000000U /*!< MSIk = 48 MHz */
-#define RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0 /*!< MSIk = 24 MHz */
-#define RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1 /*!< MSIk = 16 MHz */
-#define RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1) /*!< MSIk = 12 MHz */
-#define RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2 /*!< MSIk = 4 MHz */
-#define RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIk = 2 MHz */
-#define RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIk = 1.33 MHz */
-#define RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIk = 1 MHz */
-#define RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3 /*!< MSIk = 3.072 MHz */
-#define RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 1.536 MHz */
-#define RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 1.024 MHz */
-#define RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 768 KHz */
-#define RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 400 KHz */
-#define RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 200 KHz */
-#define RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 133 KHz */
+#define RCC_MSIKRANGE_0 0x00000000U /*!< MSIK = 48 MHz */
+#define RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0 /*!< MSIK = 24 MHz */
+#define RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1 /*!< MSIK = 16 MHz */
+#define RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1) /*!< MSIK = 12 MHz */
+#define RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2 /*!< MSIK = 4 MHz */
+#define RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 2 MHz */
+#define RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1.33 MHz */
+#define RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1 MHz */
+#define RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3 /*!< MSIK = 3.072 MHz */
+#define RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.536 MHz */
+#define RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.024 MHz */
+#define RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 768 KHz */
+#define RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 400 KHz */
+#define RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 200 KHz */
+#define RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 133 KHz */
#define RCC_MSIKRANGE_15 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 |\
- RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 100 KHz */
+ RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 100 KHz */
/**
* @}
*/
@@ -575,7 +580,6 @@
#define RCC_FLAG_LSESYSRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSESYSRDY_Pos)) /*!< LSESYS Ready flag */
#define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */
#define RCC_FLAG_LSIRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSIRDY_Pos)) /*!< LSI Ready flag */
-
/* Flags in the CSR register */
#define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos)) /*!< Remove reset flag */
#define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)) /*!< Option Byte Loader reset flag */
@@ -634,12 +638,12 @@
#define RCC_PLL1 RCC_SECCFGR_PLL1SEC
#define RCC_PLL2 RCC_SECCFGR_PLL2SEC
#define RCC_PLL3 RCC_SECCFGR_PLL3SEC
-#define RCC_CLK48M RCC_SECCFGR_CLK48MSEC
+#define RCC_ICLK RCC_SECCFGR_ICLKSEC
#define RCC_HSI48 RCC_SECCFGR_HSI48SEC
#define RCC_RMVF RCC_SECCFGR_RMVFSEC
#define RCC_ALL (RCC_HSI|RCC_HSE|RCC_MSI|RCC_LSI|RCC_LSE|RCC_HSI48| \
RCC_SYSCLK|RCC_PRESC|RCC_PLL1|RCC_PLL2| \
- RCC_PLL3|RCC_CLK48M|RCC_RMVF)
+ RCC_PLL3|RCC_ICLK|RCC_RMVF)
/**
* @}
*/
@@ -674,49 +678,60 @@
#define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_CORDIC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_FMAC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_TSC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_CRC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
UNUSED(tmpreg); \
} while(0)
+
+#if defined(JPEG)
+#define __HAL_RCC_JPEG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* JPEG */
+
#define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_FLASH_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
UNUSED(tmpreg); \
} while(0)
@@ -724,23 +739,55 @@
#define __HAL_RCC_MDF1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \
UNUSED(tmpreg); \
} while(0)
+#if defined(DMA2D)
#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
UNUSED(tmpreg); \
} while(0)
+#endif /* DMA2D */
+
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* GFXMMU */
+
+#if defined(GPU2D)
+#define __HAL_RCC_GPU2D_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* GPU2D */
+
+#if defined(DCACHE2)
+#define __HAL_RCC_DCACHE2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* DCACHE2 */
#define __HAL_RCC_GTZC1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \
UNUSED(tmpreg); \
} while(0)
@@ -748,7 +795,7 @@
#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \
UNUSED(tmpreg); \
} while(0)
@@ -756,7 +803,7 @@
#define __HAL_RCC_DCACHE1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \
UNUSED(tmpreg); \
} while(0)
@@ -764,12 +811,12 @@
#define __HAL_RCC_SRAM1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \
UNUSED(tmpreg); \
} while(0)
-#define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN)
+#define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN)
#define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN)
@@ -781,11 +828,29 @@
#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
+#if defined(JPEG)
+#define __HAL_RCC_JPEG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN)
+#endif /* JPEG */
+
#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
#define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN)
+#if defined(DMA2D)
#define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN)
+#endif /* DMA2D */
+
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN)
+#endif /* GFXMMU */
+
+#if defined(GPU2D)
+#define __HAL_RCC_GPU2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN)
+#endif /* GPU2D */
+
+#if defined(DCACHE2)
+#define __HAL_RCC_DCACHE2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN)
+#endif /* DCACHE2 */
#define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN)
@@ -808,7 +873,7 @@
#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \
UNUSED(tmpreg); \
} while(0)
@@ -816,7 +881,7 @@
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \
UNUSED(tmpreg); \
} while(0)
@@ -824,7 +889,7 @@
#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \
UNUSED(tmpreg); \
} while(0)
@@ -832,7 +897,7 @@
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \
UNUSED(tmpreg); \
} while(0)
@@ -840,23 +905,25 @@
#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \
UNUSED(tmpreg); \
} while(0)
+#if defined(GPIOF)
#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \
UNUSED(tmpreg); \
} while(0)
+#endif /* GPIOF */
#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \
UNUSED(tmpreg); \
} while(0)
@@ -864,48 +931,84 @@
#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \
UNUSED(tmpreg); \
} while(0)
+#if defined (GPIOI)
#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \
UNUSED(tmpreg); \
} while(0)
+#endif /* GPIOI */
-#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN); \
- UNUSED(tmpreg); \
- } while(0)
+#if defined(GPIOJ)
+#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN); \
+ UNUSED(tmpreg); \
+ } while(0)
-#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \
+#endif /* GPIOJ */
+
+#define __HAL_RCC_ADC12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \
UNUSED(tmpreg); \
} while(0)
+#if defined (USB_OTG_HS)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* USB_OTG_HS */
+#if defined(USB_OTG_FS)
#define __HAL_RCC_USB_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \
UNUSED(tmpreg); \
} while(0)
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE /*!< alias define for compatibility with legacy code */
+#endif /* defined (USB_OTG_FS) */
+
+#if defined(RCC_AHB2ENR1_USBPHYCEN)
+#define __HAL_RCC_USBPHYC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* defined (RCC_AHB2ENR1_USBPHYCEN) */
+
#if defined(AES)
#define __HAL_RCC_AES_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \
UNUSED(tmpreg); \
} while(0)
@@ -915,7 +1018,7 @@
#define __HAL_RCC_HASH_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \
UNUSED(tmpreg); \
} while(0)
@@ -924,106 +1027,123 @@
#define __HAL_RCC_RNG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \
UNUSED(tmpreg); \
} while(0)
+#if defined(PKA)
#define __HAL_RCC_PKA_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \
UNUSED(tmpreg); \
} while(0)
+#endif /* PKA */
+#if defined(SAES)
#define __HAL_RCC_SAES_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \
UNUSED(tmpreg); \
} while(0)
+#endif /* SAES */
+#if defined(OCTOSPIM)
#define __HAL_RCC_OSPIM_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \
UNUSED(tmpreg); \
} while(0)
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1)
#define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \
UNUSED(tmpreg); \
} while(0)
+#endif /* OTFDEC1 */
+#if defined(OTFDEC2)
#define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \
UNUSED(tmpreg); \
} while(0)
+#endif /* OTFDEC2 */
#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \
UNUSED(tmpreg); \
} while(0)
+#if defined(SDMMC2)
#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \
UNUSED(tmpreg); \
} while(0)
+#endif /* SDMMC2 */
#define __HAL_RCC_SRAM2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \
UNUSED(tmpreg); \
} while(0)
-
+#if defined(SRAM3_BASE)
#define __HAL_RCC_SRAM3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \
UNUSED(tmpreg); \
} while(0)
+#endif /* SRAM3_BASE */
+#if defined(FMC_BASE)
#define __HAL_RCC_FMC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \
UNUSED(tmpreg); \
} while(0)
+#endif /* FMC_BASE */
#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \
UNUSED(tmpreg); \
} while(0)
+#if defined(OCTOSPI2)
#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \
UNUSED(tmpreg); \
} while(0)
+#endif /* OCTOSPI2 */
#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN)
@@ -1035,19 +1155,38 @@
#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN)
+#if defined(GPIOF)
#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN)
+#endif /* GPIOF */
#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN)
#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN)
+#if defined(GPIOI)
#define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN)
+#endif /* GPIOI */
-#define __HAL_RCC_ADC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN)
+#if defined(GPIOJ)
+#define __HAL_RCC_GPIOJ_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN)
+#endif /* GPIOJ */
+
+#define __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN)
#define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN)
+#if defined(USB_OTG_HS)
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN)
+#endif /* USB_OTG_HS */
+
+#if defined(USB_OTG_FS)
#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN)
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE /*!< alias define for compatibility with legacy code */
+#endif /* USB_OTG_FS */
+
+#if defined(RCC_AHB2ENR1_USBPHYCEN)
+#define __HAL_RCC_USBPHYC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN)
+#endif /* defined (RCC_AHB2ENR1_USBPHYCEN) */
#if defined(AES)
#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN)
@@ -1059,29 +1198,89 @@
#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN)
+#if defined(PKA)
#define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN)
+#endif /* PKA */
+#if defined(SAES)
#define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN)
+#endif /* SAES */
+#if defined(OCTOSPIM)
#define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN)
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1)
#define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN)
+#endif /* OTFDEC1 */
+#if defined(OTFDEC2)
#define __HAL_RCC_OTFDEC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN)
+#endif /* OTFDEC2 */
#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN)
+#if defined(SDMMC2)
#define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN)
+#endif /* SDMMC2 */
#define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN)
+#if defined(SRAM3_BASE)
#define __HAL_RCC_SRAM3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN)
+#endif /* SRAM3_BASE */
+#if defined(HSPI1)
+#define __HAL_RCC_HSPI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* HSPI1 */
+
+#if defined (SRAM6_BASE)
+#define __HAL_RCC_SRAM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* SRAM6_BASE */
+
+#if defined (SRAM5_BASE)
+#define __HAL_RCC_SRAM5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* SRAM5_BASE */
+
+#if defined(FMC_BASE)
#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN)
+#endif /* FMC_BASE */
#define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN)
+#if defined(OCTOSPI2)
#define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN)
+#endif /* OCTOSPI2 */
+
+#if defined(HSPI1)
+#define __HAL_RCC_HSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN)
+#endif /* HSPI1 */
+
+#if defined (SRAM6_BASE)
+#define __HAL_RCC_SRAM6_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN)
+#endif /* SRAM6_BASE */
+
+#if defined (SRAM5_BASE)
+#define __HAL_RCC_SRAM5_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN)
+#endif /* SRAM5_BASE */
/**
* @}
*/
@@ -1103,55 +1302,55 @@
#define __HAL_RCC_APB3_CLK_DISABLE() SET_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS);
-#define __HAL_RCC_AHB1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \
- tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \
- UNUSED(tmpreg); \
- } while(0)
+#define __HAL_RCC_AHB1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \
+ tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \
+ UNUSED(tmpreg); \
+ } while(0)
-#define __HAL_RCC_AHB2_1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \
- tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \
- UNUSED(tmpreg); \
- } while(0)
+#define __HAL_RCC_AHB2_1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \
+ tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \
+ UNUSED(tmpreg); \
+ } while(0)
-#define __HAL_RCC_AHB2_2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \
- tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \
- UNUSED(tmpreg); \
- } while(0)
+#define __HAL_RCC_AHB2_2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \
+ tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \
+ UNUSED(tmpreg); \
+ } while(0)
-#define __HAL_RCC_AHB3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \
- tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \
- UNUSED(tmpreg); \
- } while(0)
+#define __HAL_RCC_AHB3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \
+ tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \
+ UNUSED(tmpreg); \
+ } while(0)
-#define __HAL_RCC_APB1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \
- tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \
- UNUSED(tmpreg); \
- } while(0)
+#define __HAL_RCC_APB1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \
+ tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \
+ UNUSED(tmpreg); \
+ } while(0)
-#define __HAL_RCC_APB2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \
- tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \
- UNUSED(tmpreg); \
- } while(0)
+#define __HAL_RCC_APB2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \
+ tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \
+ UNUSED(tmpreg); \
+ } while(0)
-#define __HAL_RCC_APB3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \
- tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \
- UNUSED(tmpreg); \
- } while(0)
+#define __HAL_RCC_APB3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \
+ tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \
+ UNUSED(tmpreg); \
+ } while(0)
/**
* @}
@@ -1164,10 +1363,11 @@
* using it.
* @{
*/
+
#define __HAL_RCC_LPGPIO1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1175,7 +1375,7 @@
#define __HAL_RCC_PWR_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \
UNUSED(tmpreg); \
} while(0)
@@ -1183,7 +1383,7 @@
#define __HAL_RCC_ADC4_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1191,7 +1391,7 @@
#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1199,7 +1399,7 @@
#define __HAL_RCC_LPDMA1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1207,7 +1407,7 @@
#define __HAL_RCC_ADF1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1215,7 +1415,7 @@
#define __HAL_RCC_GTZC2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1223,7 +1423,7 @@
#define __HAL_RCC_SRAM4_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1243,6 +1443,7 @@
#define __HAL_RCC_GTZC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN)
#define __HAL_RCC_SRAM4_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN)
+
/**
* @}
*/
@@ -1254,10 +1455,11 @@
* using it.
* @{
*/
+
#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1265,7 +1467,7 @@
#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1273,7 +1475,7 @@
#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1281,7 +1483,7 @@
#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1289,7 +1491,7 @@
#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1297,7 +1499,7 @@
#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1305,7 +1507,7 @@
#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
UNUSED(tmpreg); \
} while(0)
@@ -1313,23 +1515,25 @@
#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
UNUSED(tmpreg); \
} while(0)
+#if defined(USART2)
#define __HAL_RCC_USART2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
UNUSED(tmpreg); \
} while(0)
+#endif /* USART2 */
#define __HAL_RCC_USART3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1337,7 +1541,7 @@
#define __HAL_RCC_UART4_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1345,7 +1549,7 @@
#define __HAL_RCC_UART5_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1353,7 +1557,7 @@
#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1361,7 +1565,7 @@
#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1369,52 +1573,77 @@
#define __HAL_RCC_CRS_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
UNUSED(tmpreg); \
} while(0)
+
+#if defined(USART6)
+#define __HAL_RCC_USART6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* USART6 */
+
#define __HAL_RCC_I2C4_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
UNUSED(tmpreg); \
} while(0)
-#define __HAL_RCC_DTS_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN); \
- UNUSED(tmpreg); \
- } while(0)
-
#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
UNUSED(tmpreg); \
} while(0)
+#if defined(I2C5)
+#define __HAL_RCC_I2C5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* I2C5 */
+
+#if defined(I2C6)
+#define __HAL_RCC_I2C6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* I2C6 */
+
#define __HAL_RCC_FDCAN1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \
UNUSED(tmpreg); \
} while(0)
+#if defined(UCPD1)
#define __HAL_RCC_UCPD_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
UNUSED(tmpreg); \
} while(0)
+#endif /* UCPD1 */
-#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
+#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
@@ -1426,11 +1655,11 @@
#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
-#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN)
-
#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
+#if defined(USART2)
#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
+#endif /* USART2 */
#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
@@ -1444,15 +1673,28 @@
#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN)
-#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
+#if defined(USART6)
+#define __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN)
+#endif /* USART6 */
-#define __HAL_RCC_DTS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2 , RCC_APB1ENR2_DTSEN)
+#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
+#if defined(I2C5)
+#define __HAL_RCC_I2C5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN)
+#endif /* I2C5 */
+
+#if defined(I2C6)
+#define __HAL_RCC_I2C6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN)
+#endif /* I2C6 */
+
#define __HAL_RCC_FDCAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN)
+#if defined(UCPD1)
#define __HAL_RCC_UCPD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN)
+#endif /* UCPD1 */
+
/**
* @}
*/
@@ -1464,78 +1706,120 @@
* using it.
* @{
*/
-#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
+#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+
+#define __HAL_RCC_USART1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
UNUSED(tmpreg); \
} while(0)
-#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
- UNUSED(tmpreg); \
- } while(0)
+#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
-#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
- UNUSED(tmpreg); \
- } while(0)
+#if defined (SAI2)
+#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* SAI2 */
+#if defined(USB_DRD_FS)
+#define __HAL_RCC_USB_FS_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* USB_DRD_FS */
-#define __HAL_RCC_USART1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
- UNUSED(tmpreg); \
- } while(0)
+#if defined(GFXTIM)
+#define __HAL_RCC_GFXTIM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* GFXTIM */
-#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
- UNUSED(tmpreg); \
- } while(0)
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* LTDC */
-#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
- UNUSED(tmpreg); \
- } while(0)
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* DSI */
#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
@@ -1553,7 +1837,26 @@
#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
+#if defined (SAI2)
#define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
+#endif /* SAI2 */
+
+#if defined (USB_DRD_FS)
+#define __HAL_RCC_USB_FS_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN)
+#endif /* USB_DRD_FS */
+
+#if defined(GFXTIM)
+#define __HAL_RCC_GFXTIM_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN)
+#endif /* GFXTIM */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN)
+#endif /* LTDC */
+
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN)
+#endif /* DSI */
+
/**
* @}
*/
@@ -1568,7 +1871,7 @@
#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \
UNUSED(tmpreg); \
} while(0)
@@ -1576,7 +1879,7 @@
#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1584,7 +1887,7 @@
#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1592,7 +1895,7 @@
#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1600,7 +1903,7 @@
#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1608,7 +1911,7 @@
#define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1616,7 +1919,7 @@
#define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \
UNUSED(tmpreg); \
} while(0)
@@ -1624,7 +1927,7 @@
#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \
UNUSED(tmpreg); \
} while(0)
@@ -1632,7 +1935,7 @@
#define __HAL_RCC_COMP_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \
UNUSED(tmpreg); \
} while(0)
@@ -1640,7 +1943,7 @@
#define __HAL_RCC_VREF_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \
UNUSED(tmpreg); \
} while(0)
@@ -1648,7 +1951,7 @@
#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \
- /* Delay after an RCC peripheral clock enabling */ \
+ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \
UNUSED(tmpreg); \
} while(0)
@@ -1697,11 +2000,29 @@
#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)
+#if defined(JPEG)
+#define __HAL_RCC_JPEG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) != 0U)
+#endif /* JPEG */
+
#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U)
#define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U)
+#if defined(DMA2D)
#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U)
+#endif /* DMA2D */
+
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U)
+#endif /* GFXMMU */
+
+#if defined(GPU2D)
+#define __HAL_RCC_GPU2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) != 0U)
+#endif /* GPU2D */
+
+#if defined(DCACHE2)
+#define __HAL_RCC_DCACHE2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) != 0U)
+#endif /* DCACHE2 */
#define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) != 0U)
@@ -1711,7 +2032,7 @@
#define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U)
-#define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U)
+#define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U)
#define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U)
@@ -1723,11 +2044,29 @@
#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)
+#if defined(JPEG)
+#define __HAL_RCC_JPEG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) == 0U)
+#endif /* JPEG */
+
#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U)
#define __HAL_RCC_RAMCFG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) == 0U)
+#if defined (DMA2D)
#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U)
+#endif /* DMA2D */
+
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U)
+#endif /* GFXMMU */
+
+#if defined(GPU2D)
+#define __HAL_RCC_GPU2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) == 0U)
+#endif /* GPU2D */
+
+#if defined(DCACHE2)
+#define __HAL_RCC_DCACHE2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) == 0U)
+#endif /* DCACHE2 */
#define __HAL_RCC_GTZC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) == 0U)
@@ -1757,19 +2096,34 @@
#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) != 0U)
+#if defined(GPIOF)
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) != 0U)
+#endif /* GPIOF */
#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) != 0U)
#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) != 0U)
+#if defined(GPIOI)
#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) != 0U)
+#endif /* GPIOI */
-#define __HAL_RCC_ADC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN) != 0U)
+#if defined(GPIOJ)
+#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) != 0U)
+#endif /* GPIOJ */
+
+#define __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) != 0U)
#define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) != 0U)
+#if defined(USB_OTG_HS)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) != 0U)
+#endif /* USB_OTG_HS */
+
+#if defined(USB_OTG_FS)
#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) != 0U)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED /*!< alias define for compatibility with legacy code */
+#endif /* USB_OTG_FS */
#if defined(AES)
#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) != 0U)
@@ -1781,29 +2135,59 @@
#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) != 0U)
+#if defined(PKA)
#define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) != 0U)
+#endif /* PKA */
-#define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) != 0U)
+#if defined(SAES)
+#define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) != 0U)
+#endif /* SAES */
+#if defined(OCTOSPIM)
#define __HAL_RCC_OSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) != 0U)
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1)
#define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) != 0U)
+#endif /* OTFDEC1 */
+#if defined(OTFDEC2)
#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) != 0U)
+#endif /* OTFDEC2 */
#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) != 0U)
+#if defined(SDMMC2)
#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) != 0U)
+#endif /* SDMMC2 */
-#define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) != 0U)
+#define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) != 0U)
-#define __HAL_RCC_SRAM3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) != 0U)
+#if defined (SRAM3_BASE)
+#define __HAL_RCC_SRAM3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) != 0U)
+#endif /* SRAM3_BASE */
+#if defined(FMC_BASE)
#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) != 0U)
+#endif /* FMC_BASE */
-#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) != 0U)
+#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) != 0U)
-#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) != 0U)
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) != 0U)
+#endif /* OCTOSPI2 */
+
+#if defined(HSPI1)
+#define __HAL_RCC_HSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2,RCC_AHB2ENR2_HSPI1EN) != 0U)
+#endif /* HSPI1 */
+
+#if defined (SRAM6_BASE)
+#define __HAL_RCC_SRAM6_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) != 0U)
+#endif /* SRAM6_BASE */
+
+#if defined (SRAM5_BASE)
+#define __HAL_RCC_SRAM5_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) != 0U)
+#endif /* SRAM5_BASE */
#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) == 0U)
@@ -1815,19 +2199,34 @@
#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) == 0U)
+#if defined(GPIOF)
#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) == 0U)
+#endif /* GPIOF */
#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) == 0U)
#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) == 0U)
+#if defined(GPIOI)
#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) == 0U)
+#endif /* GPIOI */
-#define __HAL_RCC_ADC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN) == 0U)
+#if defined(GPIOJ)
+#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) == 0U)
+#endif /* GPIOJ */
+
+#define __HAL_RCC_ADC12_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) == 0U)
#define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) == 0U)
+#if defined(USB_OTG_HS)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) == 0U)
+#endif /* USB_OTG_HS */
+
+#if defined(USB_OTG_FS)
#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) == 0U)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED /*!< alias define for compatibility with legacy code */
+#endif /* USB_OTG_FS */
#if defined(AES)
#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) == 0U)
@@ -1839,29 +2238,59 @@
#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) == 0U)
+#if defined(PKA)
#define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) == 0U)
+#endif /* PKA */
+#if defined(SAES)
#define __HAL_RCC_SAES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) == 0U)
+#endif /* SAES */
+#if defined(OCTOSPIM)
#define __HAL_RCC_OSPIM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) == 0U)
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1)
#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) == 0U)
+#endif /* OTFDEC1 */
+#if defined (OTFDEC2)
#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) == 0U)
+#endif /* OTFDEC2 */
#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) == 0U)
+#if defined (SDMMC2)
#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) == 0U)
+#endif /* SDMMC2 */
#define __HAL_RCC_SRAM2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) == 0U)
+#if defined (SRAM3_BASE)
#define __HAL_RCC_SRAM3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) == 0U)
+#endif /* SRAM3_BASE */
-#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) == 0U)
+#if defined(FMC_BASE)
+#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) == 0U)
+#endif /* FMC_BASE */
-#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) == 0U)
+#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) == 0U)
-#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) == 0U)
+#if defined (OCTOSPI2)
+#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) == 0U)
+#endif /* OCTOSPI2 */
+
+#if defined(HSPI1)
+#define __HAL_RCC_HSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN) == 0U)
+#endif /* HSPI1 */
+
+#if defined (SRAM6_BASE)
+#define __HAL_RCC_SRAM6_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) == 0U)
+#endif /* SRAM6_BASE */
+
+#if defined (SRAM5_BASE)
+#define __HAL_RCC_SRAM5_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) == 0U)
+#endif /* SRAM5_BASE */
/**
* @}
*/
@@ -1904,6 +2333,7 @@
#define __HAL_RCC_GTZC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) == 0U)
#define __HAL_RCC_SRAM4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) == 0U)
+
/**
* @}
*/
@@ -1931,7 +2361,9 @@
#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)
+#if defined(USART2)
#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)
+#endif /* USART2 */
#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)
@@ -1945,15 +2377,27 @@
#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)
-#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U)
+#if defined(USART6)
+#define __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) != 0U)
+#endif /* USART6 */
-#define __HAL_RCC_DTS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN) != 0U)
+#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U)
#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U)
+#if defined(I2C5)
+#define __HAL_RCC_I2C5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) != 0U)
+#endif /* I2C5 */
+
+#if defined(I2C6)
+#define __HAL_RCC_I2C6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) != 0U)
+#endif /* I2C6 */
+
#define __HAL_RCC_FDCAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) != 0U)
+#if defined (UCPD1)
#define __HAL_RCC_UCPD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U)
+#endif /* UCPD1 */
#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U)
@@ -1969,7 +2413,9 @@
#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U)
+#if defined(USART2)
#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U)
+#endif /* USART2 */
#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U)
@@ -1983,15 +2429,28 @@
#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)
-#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U)
+#if defined(USART6)
+#define __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) == 0U)
+#endif /* USART6 */
-#define __HAL_RCC_DTS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN) == 0U)
+#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U)
#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U)
+#if defined(I2C5)
+#define __HAL_RCC_I2C5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) == 0U)
+#endif /* I2C5 */
+
+#if defined(I2C6)
+#define __HAL_RCC_I2C6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) == 0U)
+#endif /* I2C6 */
+
#define __HAL_RCC_FDCAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) == 0U)
+#if defined(UCPD1)
#define __HAL_RCC_UCPD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U)
+#endif /* UCPD1 */
+
/**
* @}
*/
@@ -2003,6 +2462,7 @@
* using it.
* @{
*/
+
#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)
#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)
@@ -2019,7 +2479,25 @@
#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)
+#if defined (SAI2)
#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U)
+#endif /* SAI2 */
+
+#if defined (USB_DRD_FS)
+#define __HAL_RCC_USB_FS_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) != 0U)
+#endif /* USB_DRD_FS */
+
+#if defined(GFXTIM)
+#define __HAL_RCC_GFXTIM_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) != 0U)
+#endif /* GFXTIM */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U)
+#endif /* LTDC */
+
+#if defined(DSI)
+#define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) != 0U)
+#endif /* DSI */
#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)
@@ -2037,7 +2515,26 @@
#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)
+#if defined (SAI2)
#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U)
+#endif /* SAI2 */
+
+#if defined (USB_DRD_FS)
+#define __HAL_RCC_USB_FS_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) == 0U)
+#endif /* USB_DRD_FS */
+
+#if defined(GFXTIM)
+#define __HAL_RCC_GFXTIM_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) == 0U)
+#endif /* GFXTIM */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U)
+#endif /* LTDC */
+
+#if defined(DSI)
+#define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) == 0U)
+#endif /* DSI */
+
/**
* @}
*/
@@ -2102,7 +2599,7 @@
*/
#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x0007100FU)
-#define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST)
+#define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST)
#define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
@@ -2112,15 +2609,29 @@
#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
+#if defined(JPEG)
+#define __HAL_RCC_JPEG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_JPEGRST)
+#endif /* JPEG */
+
#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
#define __HAL_RCC_RAMCFG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST)
+#if defined(DMA2D)
#define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
+#endif /* DMA2D */
+
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST)
+#endif /* GFXMMU */
+
+#if defined(GPU2D)
+#define __HAL_RCC_GPU2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPU2DRST)
+#endif /* GPU2D */
#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
-#define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST)
+#define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST)
#define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
@@ -2130,11 +2641,26 @@
#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
+#if defined(JPEG)
+#define __HAL_RCC_JPEG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_JPEGRST)
+#endif /* JPEG */
+
#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
#define __HAL_RCC_RAMCFG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST)
+#if defined(DMA2D)
#define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
+#endif /* DMA2D */
+
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST)
+#endif /* GFXMMU */
+
+#if defined(GPU2D)
+#define __HAL_RCC_GPU2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPU2DRST)
+#endif /* GPU2D */
+
/**
* @}
*/
@@ -2143,115 +2669,190 @@
* @brief Force or release AHB2 peripheral reset.
* @{
*/
-#define __HAL_RCC_AHB2_FORCE_RESET() do{\
- WRITE_REG(RCC->AHB2RSTR1, 0x19BF55FFU);\
- WRITE_REG(RCC->AHB2RSTR2, 0x00000111U);\
- }while(0)
+#define __HAL_RCC_AHB2_FORCE_RESET() do{\
+ WRITE_REG(RCC->AHB2RSTR1, 0x19BF55FFU);\
+ WRITE_REG(RCC->AHB2RSTR2, 0x00000111U);\
+ }while(0)
-#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST)
+#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST)
-#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST)
+#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST)
-#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST)
+#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST)
-#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST)
+#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST)
-#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST)
+#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST)
-#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST)
+#if defined(GPIOF)
+#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST)
+#endif /* GPIOF */
-#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST)
+#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST)
-#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST)
+#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST)
-#define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST)
+#if defined(GPIOI)
+#define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST)
+#endif /* GPIOI */
-#define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC1RST)
+#if defined(GPIOJ)
+#define __HAL_RCC_GPIOJ_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOJRST)
+#endif /* GPIOJ */
-#define __HAL_RCC_DCMI_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST)
+#define __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC12RST)
-#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST)
+#define __HAL_RCC_DCMI_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST)
-#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST)
+#if defined(USB_OTG_HS)
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST)
+#endif /* USB_OTG_HS */
-#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST)
+#if defined(USB_OTG_FS)
+#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST)
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_FORCE_RESET /*!< alias define for compatibility with legacy code */
+#endif /* USB_OTG_FS */
-#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST)
+#if defined(AES)
+#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST)
+#endif /* AES */
-#define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST)
+#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST)
-#define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST)
+#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST)
-#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST)
+#if defined(PKA)
+#define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST)
+#endif /* PKA */
-#define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST)
+#if defined(SAES)
+#define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST)
+#endif /* SAES */
-#define __HAL_RCC_OTFDEC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST)
+#if defined(OCTOSPIM)
+#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST)
+#endif /* OCTOSPIM */
-#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST)
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST)
+#endif /* OTFDEC1 */
-#define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST)
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST)
+#endif /* OTFDEC2 */
-#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST)
+#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST)
-#define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST)
+#if defined(SDMMC2)
+#define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST)
+#endif /* SDMMC2 */
-#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST)
+#if defined(FMC_BASE)
+#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST)
+#endif /* FMC_BASE */
-#define __HAL_RCC_AHB2_RELEASE_RESET() do{\
- WRITE_REG(RCC->AHB2RSTR1, 0x00000000U);\
- WRITE_REG(RCC->AHB2RSTR2, 0x00000000U);\
- }while(0)
+#define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST)
-#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST)
+#if defined (OCTOSPI2)
+#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST)
+#endif /* OCTOSPI2 */
-#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST)
+#if defined(HSPI1)
+#define __HAL_RCC_HSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_HSPI1RST)
+#endif /* HSPI1 */
-#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST)
+#define __HAL_RCC_AHB2_RELEASE_RESET() do{\
+ WRITE_REG(RCC->AHB2RSTR1, 0x00000000U);\
+ WRITE_REG(RCC->AHB2RSTR2, 0x00000000U);\
+ }while(0)
-#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST)
+#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST)
-#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST)
+#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST)
-#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST)
+#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST)
-#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST)
+#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST)
-#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST)
+#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST)
-#define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST)
+#if defined(GPIOF)
+#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST)
+#endif /* GPIOF */
-#define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC1RST)
+#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST)
-#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST)
+#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST)
-#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST)
+#if defined(GPIOI)
+#define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST)
+#endif /* GPIOI */
-#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST)
+#if defined(GPIOJ)
+#define __HAL_RCC_GPIOJ_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOJRST)
+#endif /* GPIOJ */
-#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST)
+#define __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC12RST)
-#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST)
+#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST)
-#define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST)
+#if defined(USB_OTG_HS)
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST)
+#endif /* USB_OTG_HS */
-#define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST)
+#if defined(USB_OTG_FS)
+#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET /*!< alias define for compatibility with legacy code */
+#endif /* USB_OTG_FS */
-#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST)
+#if defined(AES)
+#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST)
+#endif /* AES */
-#define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST)
+#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST)
-#define __HAL_RCC_OTFDEC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST)
+#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST)
-#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST)
+#if defined(PKA)
+#define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST)
+#endif /* PKA */
-#define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST)
+#if defined(SAES)
+#define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST)
+#endif /* SAES */
-#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST)
+#if defined(OCTOSPIM)
+#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST)
+#endif /* OCTOSPIM */
-#define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST)
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST)
+#endif /* OTFDEC1 */
-#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST)
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST)
+#endif /* OTFDEC2 */
+
+#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST)
+
+#if defined(SDMMC2)
+#define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST)
+#endif /* SDMMC2 */
+
+#if defined(FMC_BASE)
+#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST)
+#endif /* FMC_BASE */
+
+#define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST)
+
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST)
+#endif /* OCTOSPI2 */
+
+#if defined(HSPI1)
+#define __HAL_RCC_HSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_HSPI1RST)
+#endif /* HSPI1 */
+
/**
* @}
*/
@@ -2283,13 +2884,16 @@
#define __HAL_RCC_LPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPDMA1RST)
#define __HAL_RCC_ADF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADF1RST)
+
/**
* @}
*/
+
/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
* @brief Force or release APB1 peripheral reset.
* @{
*/
+
#define __HAL_RCC_APB1_FORCE_RESET() do { \
WRITE_REG(RCC->APB1RSTR1, 0x027E403FU); \
WRITE_REG(RCC->APB1RSTR2, 0x00800222U); \
@@ -2309,7 +2913,9 @@
#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
+#if defined (USART2)
#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
+#endif /* USART2 */
#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
@@ -2323,13 +2929,27 @@
#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
+#if defined(USART6)
+#define __HAL_RCC_USART6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART6RST)
+#endif /* USART6 */
+
#define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
+#if defined(I2C5)
+#define __HAL_RCC_I2C5_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C5RST)
+#endif /* I2C5 */
+
+#if defined(I2C6)
+#define __HAL_RCC_I2C6_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C6RST)
+#endif /* I2C6 */
+
#define __HAL_RCC_FDCAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST)
+#if defined(UCPD1)
#define __HAL_RCC_UCPD_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
+#endif /* UCPD1 */
#define __HAL_RCC_APB1_RELEASE_RESET() do { \
WRITE_REG(RCC->APB1RSTR1, 0x00000000U); \
@@ -2350,7 +2970,9 @@
#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
+#if defined(USART2)
#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
+#endif /* USART2 */
#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
@@ -2364,13 +2986,28 @@
#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
+#if defined(USART6)
+#define __HAL_RCC_USART6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART6RST)
+#endif /* USART6 */
+
#define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
+#if defined(I2C5)
+#define __HAL_RCC_I2C5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C5RST)
+#endif /* I2C5 */
+
+#if defined(I2C6)
+#define __HAL_RCC_I2C6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C6RST)
+#endif /* I2C6 */
+
#define __HAL_RCC_FDCAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST)
+#if defined(UCPD1)
#define __HAL_RCC_UCPD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
+#endif /* UCPD1 */
+
/**
* @}
*/
@@ -2397,7 +3034,25 @@
#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
+#if defined(SAI2)
#define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
+#endif /* SAI2 */
+
+#if defined(USB_DRD_FS)
+#define __HAL_RCC_USB_FS_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST)
+#endif /* USB_DRD_FS */
+
+#if defined(GFXTIM)
+#define __HAL_RCC_GFXTIM_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST)
+#endif /* GFXTIM */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST)
+#endif /* LTDC */
+
+#if defined(DSI)
+#define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIHOSTRST)
+#endif /* DSI */
#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
@@ -2417,7 +3072,26 @@
#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
+#if defined(SAI2)
#define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
+#endif /* SAI2 */
+
+#if defined(USB_DRD_FS)
+#define __HAL_RCC_USB_FS_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST)
+#endif /* USB_DRD_FS */
+
+#if defined(GFXTIM)
+#define __HAL_RCC_GFXTIM_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST)
+#endif /* GFXTIM */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST)
+#endif /* LTDC */
+
+#if defined(DSI)
+#define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIHOSTRST)
+#endif /* DSI */
+
/**
* @}
*/
@@ -2469,6 +3143,7 @@
#define __HAL_RCC_COMP_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_COMPRST)
#define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST)
+
/**
* @}
*/
@@ -2494,11 +3169,29 @@
#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
+#if defined(JPEG)
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_JPEGSMEN)
+#endif /* JPEG */
+
#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
#define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN)
+#if defined(DMA2D)
#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
+#endif /* DMA2D */
+
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN)
+#endif /* GFXMMU */
+
+#if defined(GPU2D)
+#define __HAL_RCC_GPU2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPU2DSMEN)
+#endif /* GPU2D */
+
+#if defined(DCACHE2)
+#define __HAL_RCC_DCACHE2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE2SMEN)
+#endif /* DCACHE2 */
#define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN)
@@ -2522,11 +3215,29 @@
#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
+#if defined(JPEG)
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_JPEGSMEN)
+#endif /* JPEG */
+
#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
#define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN)
+#if defined(DMA2D)
#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
+#endif /* DMA2D */
+
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN)
+#endif /* GFXMMU */
+
+#if defined(GPU2D)
+#define __HAL_RCC_GPU2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPU2DSMEN)
+#endif /* GPU2D */
+
+#if defined(DCACHE2)
+#define __HAL_RCC_DCACHE2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE2SMEN)
+#endif /* DCACHE2 */
#define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN)
@@ -2534,9 +3245,10 @@
#define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN)
-#define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN)
+#define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN)
#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
+
/**
* @}
*/
@@ -2560,22 +3272,41 @@
#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN)
+#if defined(GPIOF)
#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN)
+#endif /* GPIOF */
#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN)
#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN)
+#if defined(GPIOI)
#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN)
+#endif /* GPIOI */
-#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC1SMEN)
+#if defined(GPIOJ)
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOJSMEN)
+#endif /* GPIOJ */
+
+#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC12SMEN)
#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN)
+#if defined(USB_OTG_HS)
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN)
+#endif /* USB_OTG_HS */
+
+#if defined(USB_OTG_FS)
#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN)
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE /*!< alias define for compatibility with legacy code */
+#endif /* USB_OTG_FS */
+
+#if defined(RCC_AHB2SMENR1_USBPHYCSMEN)
+#define __HAL_RCC_USBPHYCCLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_USBPHYCSMEN)
+#endif /* RCC_AHB2SMENR1_USBPHYCSMEN */
#if defined(AES)
-#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN);
+#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN)
#endif /* AES */
#if defined(HASH)
@@ -2584,29 +3315,59 @@
#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_RNGSMEN)
+#if defined(PKA)
#define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN)
+#endif /* PKA */
+#if defined(SAES)
#define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN)
+#endif /* SAES */
+#if defined(OCTOSPIM)
#define __HAL_RCC_OCTOSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN)
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1)
#define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN)
+#endif /* OTFDEC1 */
+#if defined(OTFDEC2)
#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN)
+#endif /* OTFDEC2 */
#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN)
+#if defined(SDMMC2)
#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN)
+#endif /* SDMMC2 */
#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN)
+#if defined(SRAM3_BASE)
#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN)
+#endif /* SRAM3_BASE */
+#if defined(FMC_BASE)
#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN)
+#endif /* FMC_BASE */
#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN)
+#if defined(OCTOSPI2)
#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN)
+#endif /* OCTOSPI2 */
+
+#if defined(HSPI1)
+#define __HAL_RCC_HSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_HSPI1SMEN)
+#endif /* HSPI1 */
+
+#if defined(SRAM6_BASE)
+#define __HAL_RCC_SRAM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM6SMEN)
+#endif /* SRAM6_BASE */
+
+#if defined(SRAM5_BASE)
+#define __HAL_RCC_SRAM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM5SMEN)
+#endif /* SRAM5_BASE */
#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOASMEN)
@@ -2618,22 +3379,41 @@
#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN)
+#if defined(GPIOF)
#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN)
+#endif /* GPIOF */
#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN)
#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN)
+#if defined(GPIOI)
#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN)
+#endif /* GPIOI */
-#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC1SMEN)
+#if defined(GPIOJ)
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOJSMEN)
+#endif /* GPIOJ */
+
+#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC12SMEN)
#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN)
+#if defined(USB_OTG_HS)
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN)
+#endif /* USB_OTG_HS */
+
+#if defined(USB_OTG_FS)
#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN)
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE /*!< alias define for compatibility with legacy code */
+#endif /* USB_OTG_FS */
+
+#if defined(RCC_AHB2SMENR1_USBPHYCSMEN)
+#define __HAL_RCC_USBPHYCCLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_USBPHYCSMEN)
+#endif /* RCC_AHB2SMENR1_USBPHYCSMEN */
#if defined(AES)
-#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN);
+#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN)
#endif /* AES */
#if defined(HASH)
@@ -2642,29 +3422,60 @@
#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_RNGSMEN)
+#if defined(PKA)
#define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN)
+#endif /* PKA */
+#if defined(SAES)
#define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN)
+#endif /* SAES */
+#if defined(OCTOSPIM)
#define __HAL_RCC_OCTOSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN)
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1)
#define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN)
+#endif /* OTFDEC1 */
+#if defined(OTFDEC2)
#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN)
+#endif /* OTFDEC2 */
#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN)
+#if defined(SDMMC2)
#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN)
+#endif /* SDMMC2 */
#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN)
+#if defined(SRAM3_BASE)
#define __HAL_RCC_SRAM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN)
+#endif /* SRAM3_BASE */
+#if defined(FMC_BASE)
#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN)
+#endif /* FMC_BASE */
#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN)
+#if defined(OCTOSPI2)
#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN)
+#endif /* OCTOSPI2 */
+
+#if defined(HSPI1)
+#define __HAL_RCC_HSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_HSPI1SMEN)
+#endif /* HSPI1 */
+
+#if defined(SRAM6_BASE)
+#define __HAL_RCC_SRAM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM6SMEN)
+#endif /* SRAM6_BASE */
+
+#if defined(SRAM5_BASE)
+#define __HAL_RCC_SRAM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM5SMEN)
+#endif /* SRAM5_BASE */
+
/**
* @}
*/
@@ -2678,7 +3489,7 @@
* is enabled only when a peripheral requests AHB clock.
* @{
*/
-#define __HAL_RCC_LPGPIO1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN)
+#define __HAL_RCC_LPGPIO1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN)
#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN)
@@ -2686,7 +3497,7 @@
#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN)
-#define __HAL_RCC_LPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN)
+#define __HAL_RCC_LPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN)
#define __HAL_RCC_ADF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN)
@@ -2694,7 +3505,7 @@
#define __HAL_RCC_SRAM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN)
-#define __HAL_RCC_LPGPIO1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN)
+#define __HAL_RCC_LPGPIO1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN)
#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN)
@@ -2702,13 +3513,14 @@
#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN)
-#define __HAL_RCC_LPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN)
+#define __HAL_RCC_LPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN)
#define __HAL_RCC_ADF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN)
#define __HAL_RCC_GTZC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2SMEN)
#define __HAL_RCC_SRAM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN)
+
/**
* @}
*/
@@ -2738,7 +3550,9 @@
#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
+#if defined(USART2)
#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
+#endif /* USART2 */
#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
@@ -2752,13 +3566,27 @@
#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
+#if defined(USART6)
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART6SMEN)
+#endif /* USART6 */
+
#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
+#if defined(I2C5)
+#define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C5SMEN)
+#endif /* I2C5 */
+
+#if defined(I2C6)
+#define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C6SMEN)
+#endif /* I2C6 */
+
#define __HAL_RCC_FDCAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN)
+#if defined(UCPD1)
#define __HAL_RCC_UCPD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
+#endif /* UCPD1 */
#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
@@ -2776,7 +3604,9 @@
#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
+#if defined(USART2)
#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
+#endif /* USART2 */
#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
@@ -2790,13 +3620,28 @@
#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
+#if defined(USART6)
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART6SMEN)
+#endif /* USART6 */
+
#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
+#if defined(I2C5)
+#define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C5SMEN)
+#endif /* I2C5 */
+
+#if defined(I2C6)
+#define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C6SMEN)
+#endif /* I2C6 */
+
#define __HAL_RCC_FDCAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN)
+#if defined(UCPD1)
#define __HAL_RCC_UCPD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
+#endif /* UCPD1 */
+
/**
* @}
*/
@@ -2826,7 +3671,25 @@
#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
+#if defined(SAI2)
#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
+#endif /* SAI2 */
+
+#if defined(USB_DRD_FS)
+#define __HAL_RCC_USB_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN)
+#endif /* USB_DRD_FS */
+
+#if defined(GFXTIM)
+#define __HAL_RCC_GFXTIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_GFXTIMSMEN)
+#endif /* GFXTIM */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN)
+#endif /* LTDC */
+
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSIHOSTSMEN)
+#endif /* DSI */
#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
@@ -2844,7 +3707,25 @@
#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
+#if defined(SAI2)
#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
+#endif /* SAI2 */
+
+#if defined(USB_DRD_FS)
+#define __HAL_RCC_USB_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN)
+#endif /* USB_DRD_FS */
+
+#if defined(GFXTIM)
+#define __HAL_RCC_GFXTIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_GFXTIMSMEN)
+#endif /* GFXTIM */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN)
+#endif /* LTDC */
+
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSIHOSTSMEN)
+#endif /* DSI */
/**
* @}
@@ -2902,6 +3783,7 @@
#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_VREFSMEN)
#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_RTCAPBSMEN)
+
/**
* @}
*/
@@ -2942,7 +3824,6 @@
#define __HAL_RCC_SRAM4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN)
-
#define __HAL_RCC_SPI3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SPI3AMEN)
#define __HAL_RCC_LPUART1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPUART1AMEN)
@@ -2974,10 +3855,12 @@
#define __HAL_RCC_ADF1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_ADF1AMEN)
#define __HAL_RCC_SRAM4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN)
+
/**
* @}
*/
+
/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
* @{
*/
@@ -3047,7 +3930,6 @@
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR3_HSITRIM_Pos)
-
/**
* @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
* in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs.
@@ -3131,6 +4013,7 @@
SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \
MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, (__MSIRANGEVALUE__)); \
} while(0)
+
/**
* @brief Macro configures the Internal Multi Speed kernel oscillator (MSIK) clock range in run mode
* @note After restart from Reset , the MSIK clock is around 4 MHz.
@@ -3185,14 +4068,15 @@
#define __HAL_RCC_LSE_GLITCHFILTER_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSEGFON )
#define __HAL_RCC_LSE_GLITCHFILTER_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEGFON )
+
/**
* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
- * After Standby its frequency can be selected between 5 possible values (4, 2, 1.5, 1, or 3.072 MHz).
+ * After Standby its frequency can be selected between 5 possible values (4, 2, 1.33, 1, or 3.072 MHz).
* @param __MSIRANGEVALUE__: specifies the MSI clock range.
* This parameter must be one of the following values:
* @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset)
* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
- * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.5 MHz
+ * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz
* @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz
* @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz
* @retval None
@@ -3204,21 +4088,22 @@
} while(0)
/**
* @brief Macro configures the Internal Multi Speed oscillator (MSIK) clock range after Standby mode
- * After Standby its frequency can be selected between 5 possible values (4, 2, 1.5, 1, or 3.072 MHz).
- * @param __MSIRANGEVALUE__: specifies the MSI clock range.
+ * After Standby its frequency can be selected between 5 possible values (4, 2, 1.33, 1, or 3.072 MHz).
+ * @param __MSIKRANGEVALUE__: specifies the MSIK clock range.
* This parameter must be one of the following values:
- * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset)
- * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
- * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.5 MHz
- * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz
- * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz
+ * @arg @ref RCC_MSIKRANGE_4 MSIK clock is around 4 MHz (default after Reset)
+ * @arg @ref RCC_MSIKRANGE_5 MSIK clock is around 2 MHz
+ * @arg @ref RCC_MSIKRANGE_6 MSIK clock is around 1.33 MHz
+ * @arg @ref RCC_MSIKRANGE_7 MSIK clock is around 1 MHz
+ * @arg @ref RCC_MSIKRANGE_8 MSIK clock is around 3.072 MHz
* @retval None
*/
-#define __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) do {SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \
- MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE,\
- (__MSIRANGEVALUE__) >> (RCC_ICSCR1_MSISRANGE_Pos -\
- RCC_CSR_MSISSRANGE_Pos));\
- } while(0)
+#define __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(__MSIKRANGEVALUE__) \
+ do { \
+ SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \
+ MODIFY_REG(RCC->CSR, RCC_CSR_MSIKSRANGE, \
+ (__MSIKRANGEVALUE__) >> (RCC_ICSCR1_MSIKRANGE_Pos - RCC_CSR_MSIKSRANGE_Pos)); \
+ } while(0)
/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
* @retval MSI clock range.
@@ -3326,6 +4211,7 @@
{ \
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \
} \
} while(0)
@@ -3340,7 +4226,6 @@
#define __HAL_RCC_LSESYS_DISABLE() CLEAR_BIT(RCC->BDCR,RCC_BDCR_LSESYSEN)
-
/** @brief Macro to set Low-speed clock (LSI) divider.
* @note This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0).
* The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC.
@@ -3377,26 +4262,37 @@
* is stable and can be used to clock the RTC.
* @param __STATE__: specifies the new state of the LSE.
* This parameter can be one of the following values:
- * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
+ * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
* 6 LSE oscillator clock cycles.
- * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
- * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
+ * @arg @ref RCC_LSE_ON_RTC_ONLY Turn ON the LSE oscillator to be used only for RTC.
+ * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator to be used by any peripheral.
+ * @arg @ref RCC_LSE_BYPASS_RTC_ONLY LSE oscillator bypassed with external clock to be used only for RTC.
+ * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock to be used by any peripheral
* @retval None
*/
#define __HAL_RCC_LSE_CONFIG(__STATE__) \
do { \
- if((__STATE__) == RCC_LSE_ON) \
+ if((__STATE__) == RCC_LSE_ON_RTC_ONLY) \
{ \
SET_BIT(RCC->BDCR,RCC_BDCR_LSEON); \
} \
- else if((__STATE__) == RCC_LSE_BYPASS) \
+ else if((__STATE__) == RCC_LSE_ON) \
+ { \
+ SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \
+ } \
+ else if((__STATE__) == RCC_LSE_BYPASS_RTC_ONLY) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
+ else if((__STATE__) == RCC_LSE_BYPASS) \
+ { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \
+ } \
else \
{ \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ CLEAR_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
} while(0)
@@ -3516,9 +4412,9 @@
* @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1
* @retval None
*/
-#define __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN)
+#define __HAL_RCC_PLL_FRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN)
-#define __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN)
+#define __HAL_RCC_PLL_FRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN)
/**
* @brief Macro to configure the main PLL clock source, multiplication and division factors.
@@ -3545,15 +4441,15 @@
* output frequency is between 128 and 544 MHz(Voltage range 1 or 2)
* between 128 and 330 MHZ (Voltage range 3) and not allowed for Voltage range 4.
*
- * @param __PLL1P__: specifies the division factor for system clock.
- * This parameter must be a number between 2 and 128 (where odd numbers not allowed)
- *
- * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks
+ * @param __PLL1P__: specifies the division factor for peripheral kernel clocks.
* This parameter must be a number between 1 and 128
*
- * @param __PLL1R__: specifies the division factor for peripheral kernel clocks
+ * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks.
* This parameter must be a number between 1 and 128
*
+ * @param __PLL1R__: specifies the division factor for system clock.
+ * This parameter must be a number between 1 and 128 (Only division by 1 and even division are allowed)
+ *
* @retval None
*/
#define __HAL_RCC_PLL_CONFIG(__PLL1SOURCE__, __PLL1MBOOST__,__PLL1M__, __PLL1N__, __PLL1P__, __PLL1Q__, __PLL1R__) \
@@ -3591,7 +4487,7 @@
* 150 to 420 MHz if PLL1VCOSEL = 1.
* @retval None
*/
-#define __HAL_RCC_PLLFRACN_CONFIG(__PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN,\
+#define __HAL_RCC_PLL_FRACN_CONFIG(__PLL1FRACN__) WRITE_REG(RCC->PLL1FRACR, \
(uint32_t)(__PLL1FRACN__) << \
RCC_PLL1FRACR_PLL1FRACN_Pos)
@@ -3688,7 +4584,7 @@
* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLL1CLK Main PLL clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
@@ -3821,7 +4717,6 @@
*/
#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_MSI) || \
((SOURCE) == RCC_PLLSOURCE_HSI) || \
- ((SOURCE) == RCC_PLLSOURCE_NONE) || \
((SOURCE) == RCC_PLLSOURCE_HSE))
#define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 16U))
@@ -3873,6 +4768,13 @@
((__RANGE__) == RCC_MSIKRANGE_13) || \
((__RANGE__) == RCC_MSIKRANGE_14) || \
((__RANGE__) == RCC_MSIKRANGE_15))
+
+#define IS_RCC_MSIK_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIKRANGE_4) || \
+ ((__RANGE__) == RCC_MSIKRANGE_5) || \
+ ((__RANGE__) == RCC_MSIKRANGE_6) || \
+ ((__RANGE__) == RCC_MSIKRANGE_7) || \
+ ((__RANGE__) == RCC_MSIKRANGE_8))
+
/**
* @}
*/
@@ -3891,7 +4793,7 @@
/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruct);
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_ClkInitStruct, uint32_t FLatency);
/**
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc_ex.h
index db52909..1498a12 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc_ex.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rcc_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -47,7 +47,7 @@
typedef struct
{
uint32_t PLL2Source; /*!< RCC_PLL2Source: PLL2 entry clock source.
- This parameter must be a value of @ref RCC_PLL_Clock_Source */
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */
uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock.
This parameter must be a number between Min_Data = 1 and Max_Data = 63 */
@@ -56,23 +56,22 @@
This parameter must be a number between Min_Data = 4 and Max_Data = 512 */
uint32_t PLL2P; /*!< PLL2P: Division factor for system clock.
- This parameter must be a number between Min_Data = 2 and Max_Data = 128 */
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks.
This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks.
- This parameter must be a number between Min_Data = 1 and Max_Data = 128
- odd division factors are not allowed */
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
- uint32_t PLL2RGE; /*!<PLL2RGE: PLL2 clock Input range
- This parameter must be a value of @ref RCC_PLL_VCI_Range */
+ uint32_t PLL2RGE; /*!< PLL2RGE: PLL2 clock Input range
+ This parameter must be a value of @ref RCC_PLL_VCI_Range */
- uint32_t PLL2FRACN; /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for
- PLL2 VCO It should be a value between 0 and 8191 */
+ uint32_t PLL2FRACN; /*!< PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for
+ PLL2 VCO It should be a value between 0 and 8191 */
uint32_t PLL2ClockOut; /*!< PLL2ClockOut: specifies PLL2 output clock to be enabled.
- This parameter must be a value of @ref RCC_PLL2_Clock_Output */
+ This parameter must be a value of @ref RCC_PLL2_Clock_Output */
} RCC_PLL2InitTypeDef;
@@ -82,7 +81,7 @@
typedef struct
{
uint32_t PLL3Source; /*!< RCC_PLL3Source: PLL3 entry clock source.
- This parameter must be a value of @ref RCC_PLL_Clock_Source */
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */
uint32_t PLL3M; /*!< PLL3M: Division factor for PLL3 VCO input clock.
This parameter must be a number between Min_Data = 1 and Max_Data = 63 */
@@ -91,23 +90,22 @@
This parameter must be a number between Min_Data = 4 and Max_Data = 512 */
uint32_t PLL3P; /*!< PLL3P: Division factor for system clock.
- This parameter must be a number between Min_Data = 2 and Max_Data = 128 */
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
uint32_t PLL3Q; /*!< PLL3Q: Division factor for peripheral clocks.
This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
uint32_t PLL3R; /*!< PLL3R: Division factor for peripheral clocks.
- This parameter must be a number between Min_Data = 1 and Max_Data = 128
- odd division factors are not allowed */
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
- uint32_t PLL3RGE; /*!<PLL3RGE: PLL3 clock Input range
- This parameter must be a value of @ref RCC_PLL_VCI_Range */
+ uint32_t PLL3RGE; /*!< PLL3RGE: PLL3 clock Input range
+ This parameter must be a value of @ref RCC_PLL_VCI_Range */
- uint32_t PLL3FRACN; /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for
- PLL3 VCO It should be a value between 0 and 8191 */
+ uint32_t PLL3FRACN; /*!< PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for
+ PLL3 VCO It should be a value between 0 and 8191 */
uint32_t PLL3ClockOut; /*!< PLL3ClockOut: specifies PLL3 output clock to be enabled.
- This parameter must be a value of @ref RCC_PLL3_Clock_Output */
+ This parameter must be a value of @ref RCC_PLL3_Clock_Output */
} RCC_PLL3InitTypeDef;
/**
@@ -146,7 +144,7 @@
*/
typedef struct
{
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ uint64_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
RCC_PLL2InitTypeDef PLL2; /*!< PLL2structure parameters.
@@ -160,8 +158,10 @@
uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source.
This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+#if defined(USART2)
uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source.
This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
+#endif /* USART2 */
uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source.
This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
@@ -172,6 +172,11 @@
uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source.
This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+#if defined(USART6)
+ uint32_t Usart6ClockSelection; /*!< Specifies USART6 clock source.
+ This parameter can be a value of @ref RCCEx_USART6_Clock_Source */
+#endif /* USART6 */
+
uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source.
This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
@@ -187,6 +192,16 @@
uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source.
This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
+#if defined(I2C5)
+ uint32_t I2c5ClockSelection; /*!< Specifies I2C5 clock source.
+ This parameter can be a value of @ref RCCEx_I2C5_Clock_Source */
+#endif /* I2C5 */
+
+#if defined(I2C6)
+ uint32_t I2c6ClockSelection; /*!< Specifies I2C6 clock source.
+ This parameter can be a value of @ref RCCEx_I2C6_Clock_Source */
+#endif /* I2C6 */
+
uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source.
This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
@@ -208,17 +223,21 @@
uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source.
This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
+#if defined (SAI2)
uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source.
This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
+#endif /* SAI2 */
uint32_t RngClockSelection; /*!< Specifies RNG clock source
This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
+#if defined(SAES)
uint32_t SaesClockSelection; /*!< Specifies SAES clock source
This parameter can be a value of @ref RCCEx_SAES_Clock_Source */
+#endif /* SAES */
- uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB, RNG and SDMMC1
- This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
+ uint32_t IclkClockSelection; /*!< Specifies intermediate clock source used by USB, RNG and SDMMC1
+ This parameter can be a value of @ref RCCEx_ICLK_Clock_Source */
uint32_t SdmmcClockSelection; /*!< Specifies SDMMC1/2 clock source.
This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source */
@@ -232,6 +251,11 @@
uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source.
This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */
+#if defined(HSPI1)
+ uint32_t HspiClockSelection; /*!< Specifies HexaSPI clock source.
+ This parameter can be a value of @ref RCCEx_HSPI_Clock_Source */
+#endif /* HSPI1 */
+
uint32_t Spi1ClockSelection; /*!< Specifies SPI1 clock source
This parameter can be a value of @ref RCCEx_SPI1_Clock_Source */
@@ -243,6 +267,22 @@
uint32_t RTCClockSelection; /*!< Specifies RTC clock source.
This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+#if defined(LTDC)
+ uint32_t LtdcClockSelection; /*!< Specifies LTDC clock source.
+ This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */
+#endif /* LTDC */
+
+#if defined(DSI)
+ uint32_t DsiClockSelection; /*!< Specifies DSI clock source.
+ This parameter can be a value of @ref RCCEx_DSI_Clock_Source */
+#endif /* DSI */
+
+#if defined(USB_OTG_HS)
+ uint32_t UsbPhyClockSelection; /*!< Specifies USB PHY clock source.
+ This parameter can be a value of @ref RCCEx_USBPHY_Clock_Source */
+#endif /* USB_OTG_HS */
+
} RCC_PeriphCLKInitTypeDef;
#if defined(CRS)
@@ -331,46 +371,156 @@
/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
* @{
*/
-#define RCC_PERIPHCLK_USART1 0x00000001U
-#define RCC_PERIPHCLK_USART2 0x00000002U
-#define RCC_PERIPHCLK_USART3 0x00000004U
-#define RCC_PERIPHCLK_UART4 0x00000008U
-#define RCC_PERIPHCLK_UART5 0x00000010U
-#define RCC_PERIPHCLK_LPUART1 0x00000020U
-#define RCC_PERIPHCLK_I2C1 0x00000040U
-#define RCC_PERIPHCLK_I2C2 0x00000080U
-#define RCC_PERIPHCLK_I2C3 0x00000100U
-#define RCC_PERIPHCLK_LPTIM1 0x00000200U
-#define RCC_PERIPHCLK_LPTIM2 0x00000400U
-#define RCC_PERIPHCLK_LPTIM34 0x00000800U
-#define RCC_PERIPHCLK_SAES 0x00001000U
-#define RCC_PERIPHCLK_SAI1 0x00002000U
-#define RCC_PERIPHCLK_SAI2 0x00004000U
-#define RCC_PERIPHCLK_ADCDAC 0x00008000U
-#define RCC_PERIPHCLK_MDF1 0x00010000U
-#define RCC_PERIPHCLK_ADF1 0x00020000U
-#define RCC_PERIPHCLK_RTC 0x00040000U
-#define RCC_PERIPHCLK_RNG 0x00080000U
-#define RCC_PERIPHCLK_CLK48 0x00100000U
-#define RCC_PERIPHCLK_SDMMC 0x00200000U
-#define RCC_PERIPHCLK_I2C4 0x00400000U
-#define RCC_PERIPHCLK_SPI1 0x00800000U
-#define RCC_PERIPHCLK_SPI2 0x01000000U
-#define RCC_PERIPHCLK_SPI3 0x02000000U
-#define RCC_PERIPHCLK_OSPI 0x04000000U
-#define RCC_PERIPHCLK_FDCAN1 0x08000000U
-#define RCC_PERIPHCLK_DAC1 0x10000000U
-
+#define RCC_PERIPHCLK_USART1 ((uint64_t)0x00000001U)
+#if defined(USART2)
+#define RCC_PERIPHCLK_USART2 ((uint64_t)0x00000002U)
+#endif /* USART2 */
+#define RCC_PERIPHCLK_USART3 ((uint64_t)0x00000004U)
+#define RCC_PERIPHCLK_UART4 ((uint64_t)0x00000008U)
+#define RCC_PERIPHCLK_UART5 ((uint64_t)0x00000010U)
+#define RCC_PERIPHCLK_LPUART1 ((uint64_t)0x00000020U)
+#define RCC_PERIPHCLK_I2C1 ((uint64_t)0x00000040U)
+#define RCC_PERIPHCLK_I2C2 ((uint64_t)0x00000080U)
+#define RCC_PERIPHCLK_I2C3 ((uint64_t)0x00000100U)
+#define RCC_PERIPHCLK_LPTIM1 ((uint64_t)0x00000200U)
+#define RCC_PERIPHCLK_LPTIM2 ((uint64_t)0x00000400U)
+#define RCC_PERIPHCLK_LPTIM34 ((uint64_t)0x00000800U)
+#if defined(SAES)
+#define RCC_PERIPHCLK_SAES ((uint64_t)0x00001000U)
+#endif /* SAES */
+#define RCC_PERIPHCLK_SAI1 ((uint64_t)0x00002000U)
+#if defined(SAI2)
+#define RCC_PERIPHCLK_SAI2 ((uint64_t)0x00004000U)
+#endif /* SAI2 */
+#define RCC_PERIPHCLK_ADCDAC ((uint64_t)0x00008000U)
+#define RCC_PERIPHCLK_MDF1 ((uint64_t)0x00010000U)
+#define RCC_PERIPHCLK_ADF1 ((uint64_t)0x00020000U)
+#define RCC_PERIPHCLK_RTC ((uint64_t)0x00040000U)
+#define RCC_PERIPHCLK_RNG ((uint64_t)0x00080000U)
+#define RCC_PERIPHCLK_ICLK ((uint64_t)0x00100000U)
+#define RCC_PERIPHCLK_SDMMC ((uint64_t)0x00200000U)
+#define RCC_PERIPHCLK_I2C4 ((uint64_t)0x00400000U)
+#define RCC_PERIPHCLK_SPI1 ((uint64_t)0x00800000U)
+#define RCC_PERIPHCLK_SPI2 ((uint64_t)0x01000000U)
+#define RCC_PERIPHCLK_SPI3 ((uint64_t)0x02000000U)
+#define RCC_PERIPHCLK_OSPI ((uint64_t)0x04000000U)
+#define RCC_PERIPHCLK_FDCAN1 ((uint64_t)0x08000000U)
+#define RCC_PERIPHCLK_DAC1 ((uint64_t)0x10000000U)
+#if defined(USART6)
+#define RCC_PERIPHCLK_USART6 ((uint64_t)0x20000000U)
+#endif /* USART6 */
+#if defined(I2C5)
+#define RCC_PERIPHCLK_I2C5 ((uint64_t)0x40000000U)
+#endif /* I2C5 */
+#if defined(I2C6)
+#define RCC_PERIPHCLK_I2C6 ((uint64_t)0x80000000U)
+#endif /* I2C6 */
+#if defined(HSPI1)
+#define RCC_PERIPHCLK_HSPI ((uint64_t)0x100000000U)
+#endif /* HSPI1 */
+#if defined(LTDC)
+#define RCC_PERIPHCLK_LTDC ((uint64_t)0x200000000U)
+#endif /* LTDC */
+#if defined(DSI)
+#define RCC_PERIPHCLK_DSI ((uint64_t)0x400000000U)
+#endif /* DSI */
+#if defined(USB_OTG_HS)
+#define RCC_PERIPHCLK_USBPHY ((uint64_t)0x800000000U)
+#endif /* USB_OTG_HS */
+#if (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx))
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \
+ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \
+ RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \
+ RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \
+ RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \
+ RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \
+ RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_USBPHY)
+#elif defined (STM32U5G7xx)
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \
+ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \
+ RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \
+ RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \
+ RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \
+ RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \
+ RCC_PERIPHCLK_USBPHY | RCC_PERIPHCLK_SAES)
+#elif defined (STM32U5F7xx)
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \
+ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \
+ RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \
+ RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \
+ RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \
+ RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \
+ RCC_PERIPHCLK_USBPHY)
+#elif (defined(STM32U595xx) || defined(STM32U5A5xx))
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \
+ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \
+ RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \
+ RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \
+ RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \
+ RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_USBPHY)
+#elif defined(STM32U585xx)
#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 |RCC_PERIPHCLK_USART3 | \
RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \
RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM34 | \
RCC_PERIPHCLK_SAES | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG |RCC_PERIPHCLK_CLK48 | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG |RCC_PERIPHCLK_ICLK | \
RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | \
RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 |RCC_PERIPHCLK_OSPI | \
RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1)
+#elif defined(STM32U575xx)
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 |RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM34 | \
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
+ RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG |RCC_PERIPHCLK_ICLK | \
+ RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | \
+ RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 |RCC_PERIPHCLK_OSPI | \
+ RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1)
+#elif defined(STM32U535xx)
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 |RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \
+ RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 |RCC_PERIPHCLK_I2C1 | \
+ RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | \
+ RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM34 | \
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | \
+ RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | \
+ RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_I2C4 | \
+ RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \
+ RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1)
+#else
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 |RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \
+ RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 |RCC_PERIPHCLK_I2C1 | \
+ RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | \
+ RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_SAES | \
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | \
+ RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | \
+ RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_I2C4 | \
+ RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \
+ RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1)
+#endif /* (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx)) */
/**
* @}
*/
@@ -407,6 +557,7 @@
* @}
*/
+#if defined(USART2)
/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
* @{
*/
@@ -417,6 +568,7 @@
/**
* @}
*/
+#endif /* USART2 */
/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
* @{
@@ -451,6 +603,19 @@
* @}
*/
+#if defined(USART6)
+/** @defgroup RCCEx_USART6_Clock_Source USART6 Clock Source
+ * @{
+ */
+#define RCC_USART6CLKSOURCE_PCLK1 0x00000000U
+#define RCC_USART6CLKSOURCE_SYSCLK RCC_CCIPR2_USART6SEL_0
+#define RCC_USART6CLKSOURCE_HSI RCC_CCIPR2_USART6SEL_1
+#define RCC_USART6CLKSOURCE_LSE (RCC_CCIPR2_USART6SEL_0 | RCC_CCIPR2_USART6SEL_1)
+/**
+ * @}
+ */
+#endif /* USART6 */
+
/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
* @{
*/
@@ -507,6 +672,32 @@
* @}
*/
+#if defined(I2C5)
+/** @defgroup RCCEx_I2C5_Clock_Source I2C5 Clock Source
+ * @{
+ */
+#define RCC_I2C5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
+#define RCC_I2C5CLKSOURCE_SYSCLK RCC_CCIPR2_I2C5SEL_0
+#define RCC_I2C5CLKSOURCE_HSI RCC_CCIPR2_I2C5SEL_1
+#define RCC_I2C5CLKSOURCE_MSIK (RCC_CCIPR2_I2C5SEL_1 | RCC_CCIPR2_I2C5SEL_0)
+/**
+ * @}
+ */
+#endif /* I2C5 */
+
+#if defined(I2C6)
+/** @defgroup RCCEx_I2C6_Clock_Source I2C6 Clock Source
+ * @{
+ */
+#define RCC_I2C6CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
+#define RCC_I2C6CLKSOURCE_SYSCLK RCC_CCIPR2_I2C6SEL_0
+#define RCC_I2C6CLKSOURCE_HSI RCC_CCIPR2_I2C6SEL_1
+#define RCC_I2C6CLKSOURCE_MSIK (RCC_CCIPR2_I2C6SEL_1 | RCC_CCIPR2_I2C6SEL_0)
+/**
+ * @}
+ */
+#endif /* I2C6 */
+
/** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source
* @{
*/
@@ -517,6 +708,7 @@
* @}
*/
+#if defined(SAES)
/** @defgroup RCCEx_SAES_Clock_Source RCCEx SAES Clock Source
* @{
*/
@@ -525,6 +717,7 @@
/**
* @}
*/
+#endif /* SAES */
/** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source
* @{
@@ -602,13 +795,13 @@
* @}
*/
-/** @defgroup RCCEx_CLK48_Clock_Source CLK48 Clock Source
+/** @defgroup RCCEx_ICLK_Clock_Source ICLK Clock Source
* @{
*/
-#define RCC_CLK48CLKSOURCE_HSI48 0x00000000U
-#define RCC_CLK48CLKSOURCE_PLL2 RCC_CCIPR1_CLK48MSEL_0
-#define RCC_CLK48CLKSOURCE_PLL1 RCC_CCIPR1_CLK48MSEL_1
-#define RCC_CLK48CLKSOURCE_MSIK RCC_CCIPR1_CLK48MSEL
+#define RCC_ICLK_CLKSOURCE_HSI48 0x00000000U
+#define RCC_ICLK_CLKSOURCE_PLL2 RCC_CCIPR1_ICLKSEL_0
+#define RCC_ICLK_CLKSOURCE_PLL1 RCC_CCIPR1_ICLKSEL_1
+#define RCC_ICLK_CLKSOURCE_MSIK RCC_CCIPR1_ICLKSEL
/**
* @}
*/
@@ -662,6 +855,7 @@
* @}
*/
+#if defined(SAI2)
/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
* @{
*/
@@ -673,6 +867,7 @@
/**
* @}
*/
+#endif /* SAI2 */
/** @defgroup RCCEx_SDMMC_Clock_Source SDMMC1/2 Clock Source
* @{
@@ -694,6 +889,19 @@
* @}
*/
+#if defined(HSPI1)
+/** @defgroup RCCEx_HSPI_Clock_Source HexaSPI Clock Source
+ * @{
+ */
+#define RCC_HSPICLKSOURCE_SYSCLK ((uint32_t)0x00000000U)
+#define RCC_HSPICLKSOURCE_PLL1 RCC_CCIPR2_HSPISEL_0
+#define RCC_HSPICLKSOURCE_PLL2 RCC_CCIPR2_HSPISEL_1
+#define RCC_HSPICLKSOURCE_PLL3 RCC_CCIPR2_HSPISEL
+/**
+ * @}
+ */
+#endif /* HSPI1 */
+
/** @defgroup RCCEx_DAC1_Clock_Source DAC1 Clock Source
* @{
*/
@@ -715,6 +923,42 @@
/**
* @}
*/
+
+#if defined(LTDC)
+/** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source
+ * @{
+ */
+#define RCC_LTDCCLKSOURCE_PLL3 ((uint32_t)0x00000000U) /*!< PLL3 divider R clock selected as LTDC kernel clock */
+#define RCC_LTDCCLKSOURCE_PLL2 RCC_CCIPR2_LTDCSEL /*!< PLL2 divider R clock selected as LTDC kernel clock */
+/**
+ * @}
+ */
+#endif /* LTDC */
+
+#if defined(DSI)
+/** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source
+ * @{
+ */
+#define RCC_DSICLKSOURCE_DSIPHY RCC_CCIPR2_DSIHOSTSEL /*!< DSI-PHY is selected as DSI byte lane clock (usual case) */
+#define RCC_DSICLKSOURCE_PLL3 ((uint32_t)0x00000000U) /*!< PLL3 divider P clock selected as DSI byte lane clock (low power case) */
+/**
+ * @}
+ */
+#endif /* DSI */
+
+#if defined(USB_OTG_HS)
+/** @defgroup RCCEx_USBPHY_Clock_Source USB-PHY Clock Source
+ * @{
+ */
+#define RCC_USBPHYCLKSOURCE_HSE ((uint32_t)0x00000000U) /*!< HSE clock selected as USBPHYC clock */
+#define RCC_USBPHYCLKSOURCE_HSE_DIV2 RCC_CCIPR2_USBPHYCSEL_1 /*!< HSE clock divided by 2 selected as USBPHYC clock */
+#define RCC_USBPHYCLKSOURCE_PLL1 RCC_CCIPR2_USBPHYCSEL_0 /*!< PLL1 divider P selected as USBPHYC clock */
+#define RCC_USBPHYCLKSOURCE_PLL1_DIV2 (RCC_CCIPR2_USBPHYCSEL_1 | RCC_CCIPR2_USBPHYCSEL_0) /*!< PLL1 divider P divided by 2 selected as USBPHYC clock */
+/**
+ * @}
+ */
+#endif /* USB_OTG_HS */
+
#if defined(CRS)
/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
@@ -1171,15 +1415,15 @@
*/
#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG(__PLL3_CLOCKOUT__) READ_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__))
-/** @brief Macro to configure the ADC1, ADC4 and DAC interface clock.
+/** @brief Macro to configure the ADC1, ADC2, ADC4 and DAC interface clock.
* @param __ADCDAC_CLKSOURCE__ specifies the ADC1, ADC4 and DAC digital interface clock source.
* This parameter can be one of the following values:
- * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock selected as ADC1, ADC4 and DAC clock
- * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock selected as ADC1, ADC4 and DAC clock
- * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock selected as ADC1, ADC4 and DAC clock
- * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock selected as ADC1, ADC4 and DAC clock
- * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock selected as ADC1, ADC4 and DAC clock
- * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock selected as ADC1, ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock selected as ADC1, ADC2, ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock selected as ADC1, ADC2 ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock selected as ADC1, ADC2 ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock selected as ADC1, ADC2 ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock selected as ADC1, ADC2 ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock selected as ADC1, ADC2 ADC4 and DAC clock
* @retval None
*/
#define __HAL_RCC_ADCDAC_CONFIG(__ADCDAC_CLKSOURCE__) \
@@ -1187,12 +1431,12 @@
/** @brief Macro to get the ADCDAC clock source.
* @retval The clock source can be one of the following values:
- * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock used as ADC1, ADC4 and DAC clock
- * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock used as ADC1, ADC4 and DAC clock
- * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock used as ADC1, ADC4 and DAC clock
- * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock used as ADC1, ADC4 and DAC clock
- * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock used as ADC1, ADC4 and DAC clock
- * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock used as ADC1, ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock used as ADC1, ADC2, ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock used as ADC1, ADC2, ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock used as ADC1, ADC2, ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock used as ADC1, ADC2, ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock used as ADC1, ADC2, ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock used as ADC1, ADC2, ADC4 and DAC clock
*/
#define __HAL_RCC_GET_ADCDAC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_ADCDACSEL)))
@@ -1205,7 +1449,7 @@
* @arg RCC_CLK48CLKSOURCE_MSIK : MSIK selected as CLK48 source
*/
#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
- MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__CLK48_SOURCE__))
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL, (uint32_t)(__CLK48_SOURCE__))
/** @brief macro to get the CLK48 source.
* @retval The clock source can be one of the following values:
@@ -1214,7 +1458,7 @@
* @arg RCC_CLK48CLKSOURCE_PLL1 : PLL1 used as CLK48 source
* @arg RCC_CLK48CLKSOURCE_MSIK : MSIK used as CLK48 source
*/
-#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL)))
+#define __HAL_RCC_GET_ICLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL)))
/** @brief Macro to configure the FDCAN1 kernel clock (FDCAN1CLK).
* @param __FDCAN1_CLKSOURCE__ specifies the FDCAN1 kernel clock source.
@@ -1442,6 +1686,54 @@
*/
#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C4SEL)))
+#if defined(I2C5)
+/** @brief Macro to configure the I2C5 clock (I2C5CLK).
+ *
+ * @param __I2C5_CLKSOURCE__ specifies the I2C5 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C5CLKSOURCE_PCLK1 PCLK1 selected as I2C5 clock
+ * @arg @ref RCC_I2C5CLKSOURCE_SYSCLK System Clock selected as I2C5 clock
+ * @arg @ref RCC_I2C5CLKSOURCE_HSI HSI selected as I2C5 clock
+ * @arg @ref RCC_I2C5CLKSOURCE_MSIK MSIK selected as I2C5 clock
+ * @retval None
+ */
+#define __HAL_RCC_I2C5_CONFIG(__I2C5_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C5SEL, (uint32_t)(__I2C5_CLKSOURCE__))
+
+/** @brief Macro to get the I2C5 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C5CLKSOURCE_PCLK1 PCLK1 selected as I2C5 clock
+ * @arg @ref RCC_I2C5CLKSOURCE_SYSCLK System Clock selected as I2C5 clock
+ * @arg @ref RCC_I2C5CLKSOURCE_HSI HSI selected as I2C5 clock
+ * @arg @ref RCC_I2C5CLKSOURCE_MSIK MSIK selected as I2C5 clock
+ */
+#define __HAL_RCC_GET_I2C5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C5SEL)))
+#endif /* I2C5 */
+
+#if defined(I2C6)
+/** @brief Macro to configure the I2C6 clock (I2C6CLK).
+ *
+ * @param __I2C6_CLKSOURCE__ specifies the I2C6 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C6CLKSOURCE_PCLK1 PCLK1 selected as I2C6 clock
+ * @arg @ref RCC_I2C6CLKSOURCE_SYSCLK System Clock selected as I2C6 clock
+ * @arg @ref RCC_I2C6CLKSOURCE_HSI HSI selected as I2C6 clock
+ * @arg @ref RCC_I2C6CLKSOURCE_MSIK MSIK selected as I2C6 clock
+ * @retval None
+ */
+#define __HAL_RCC_I2C6_CONFIG(__I2C6_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C6SEL, (uint32_t)(__I2C6_CLKSOURCE__))
+
+/** @brief Macro to get the I2C6 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C6CLKSOURCE_PCLK1 PCLK1 selected as I2C6 clock
+ * @arg @ref RCC_I2C6CLKSOURCE_SYSCLK System Clock selected as I2C6 clock
+ * @arg @ref RCC_I2C6CLKSOURCE_HSI HSI selected as I2C6 clock
+ * @arg @ref RCC_I2C6CLKSOURCE_MSIK MSIK selected as I2C6 clock
+ */
+#define __HAL_RCC_GET_I2C6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C6SEL)))
+#endif /* I2C6 */
+
/** @brief Macro to configure the USART1 clock (USART1CLK).
* @param __USART1_CLKSOURCE__ specifies the USART1 clock source.
* This parameter can be one of the following values:
@@ -1463,6 +1755,7 @@
*/
#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART1SEL)))
+#if defined(USART2)
/** @brief Macro to configure the USART2 clock (USART2CLK).
* @param __USART2_CLKSOURCE__ specifies the USART2 clock source.
* This parameter can be one of the following values:
@@ -1483,6 +1776,7 @@
* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
*/
#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART2SEL)))
+#endif /* USART2 */
/** @brief Macro to configure the USART3 clock (USART3CLK).
*
@@ -1549,6 +1843,30 @@
*/
#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART5SEL)))
+#if defined(USART6)
+/** @brief Macro to configure the USART6 clock (USART6CLK).
+ *
+ * @param __USART6_CLKSOURCE__ specifies the USART6 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK1 selected as USART6 clock
+ * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock
+ * @arg @ref RCC_USART6CLKSOURCE_SYSCLK System Clock selected as USART6 clock
+ * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock
+ * @retval None
+ */
+#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
+
+/** @brief Macro to get the USART6 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK1 selected as USART6 clock
+ * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock
+ * @arg @ref RCC_USART6CLKSOURCE_SYSCLK System Clock selected as USART6 clock
+ * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock
+ */
+#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USART6SEL)))
+#endif /* USART6 */
+
/** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
*
* @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
@@ -1573,7 +1891,6 @@
*/
#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL)))
-
/** @brief Macro to configure the OctoSPI clock.
* @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source.
* This parameter can be one of the following values:
@@ -1595,6 +1912,29 @@
*/
#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL)))
+#if defined(HSPI1)
+/** @brief Macro to configure the HexaSPI clock.
+ * @param __HSPI_CLKSOURCE__ specifies the HexaSPI clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_HSPICLKSOURCE_SYSCLK System Clock selected as HexaSPI clock
+ * @arg @ref RCC_HSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as HexaSPI clock
+ * @arg @ref RCC_HSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as HexaSPI clock
+ * @arg @ref RCC_HSPICLKSOURCE_PLL3 PLL3 R divider clock selected as HexaSPI clock
+ * @retval None
+ */
+#define __HAL_RCC_HSPI_CONFIG(__HSPI_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_HSPISEL, (uint32_t)(__HSPI_CLKSOURCE__))
+
+/** @brief Macro to get the HexaSPI clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_HSPICLKSOURCE_SYSCLK System Clock selected as HexaSPI clock
+ * @arg @ref RCC_HSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as HexaSPI clock
+ * @arg @ref RCC_HSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as HexaSPI clock
+ * @arg @ref RCC_HSPICLKSOURCE_PLL3 PLL3 R divider clock selected as HexaSPI clock
+ */
+#define __HAL_RCC_GET_HSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_HSPISEL)))
+#endif /* HSPI1 */
+
/** @brief Macro to configure the SDMMC1/2 clock (SDMMCCLK).
* @param __SDMMC_CLKSOURCE__: specifies the SDMMC1/2 clock source.
* This parameter can be one of the following values:
@@ -1629,6 +1969,7 @@
*/
#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_RNGSEL)))
+#if defined(SAES)
/** @brief macro to configure the SAES clock (SAESCLK).
* @param __SAES_CLKSource__: specifies the SAES clock source.
* This parameter can be one of the following values:
@@ -1644,6 +1985,7 @@
* @arg RCC_SAESCLKSOURCE_SHSI_DIV2: SHSI/2 selected as SAES clock
*/
#define __HAL_RCC_GET_SAES_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAESSEL)))
+#endif /* SAES */
/**
* @brief Macro to configure the SAI1 clock source.
@@ -1674,6 +2016,7 @@
*/
#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL)))
+#if defined(SAI2)
/**
* @brief Macro to configure the SAI2 clock source.
* @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived
@@ -1698,6 +2041,7 @@
* @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16
*/
#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL)))
+#endif /* SAI2 */
/** @brief Macro to configure the MDF1 clock.
* @param __MDF1_CLKSOURCE__ specifies the MDF1 clock source.
@@ -1762,6 +2106,101 @@
*/
#define __HAL_RCC_GET_DAC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_DAC1SEL)))
+#if defined(LTDC)
+
+/** @brief Macro to configure the LTDC clock.
+ * @param __LTDC_CLKSOURCE__ specifies the LTDC clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LTDCCLKSOURCE_PLL3 PLL3 divider R clock selected as LTDC kernel clock
+ * @arg @ref RCC_LTDCCLKSOURCE_PLL2 PLL2 divider R clock selected as LTDC kernel clock
+ * @retval None
+ */
+#define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LTDCSEL, (__LTDC_CLKSOURCE__))
+
+/** @brief Macro to get the LTDC clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_LTDCCLKSOURCE_PLL3 PLL3 divider R clock selected as LTDC kernel clock
+ * @arg @ref RCC_LTDCCLKSOURCE_PLL2 PLL2 divider R clock selected as LTDC kernel clock
+ */
+#define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LTDCSEL))
+
+#endif /* LTDC */
+
+#if defined(DSI)
+
+/** @brief Macro to configure the DSI clock.
+ * @param __DSI_CLKSOURCE__ specifies the DSI clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock
+ * @arg @ref RCC_DSICLKSOURCE_PLL3 PLL3 divider P clock selected as DSI clock (low power case)
+ * @retval None
+ */
+#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSIHOSTSEL, (__DSI_CLKSOURCE__))
+
+/** @brief Macro to get the DSI clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock
+ * @arg @ref RCC_DSICLKSOURCE_PLL3 PLL3 divider P clock selected as DSI clock (low power case)
+ */
+#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSIHOSTSEL))
+
+#endif /* DSI */
+
+#if defined(USB_OTG_HS)
+
+/** @brief Macro to configure the USB PHY clock.
+ * @param __USBPHY_CLKSOURCE__ specifies the USB PHY clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_USBPHYCLKSOURCE_HSE HSE clock selected as USB PHY clock
+ * @arg @ref RCC_USBPHYCLKSOURCE_HSE_DIV2 HSE clock div by 2 selected as USB PHY clock
+ * @arg @ref RCC_USBPHYCLKSOURCE_PLL1 PLL1 P divider clock selected as USB PHY clock
+ * @arg @ref RCC_USBPHYCLKSOURCE_PLL1_DIV2 PLL1 P divider clock div by 2 selected as USB PHY clock
+ * @retval None
+ */
+#define __HAL_RCC_USBPHY_CONFIG(__USBPHY_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBPHYCSEL, (__USBPHY_CLKSOURCE__))
+
+/** @brief Macro to get the USB PHY clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_USBPHYCLKSOURCE_HSE HSE clock selected as USB PHY clock
+ * @arg @ref RCC_USBPHYCLKSOURCE_HSE_DIV2 HSE clock div by 2 selected as USB PHY clock
+ * @arg @ref RCC_USBPHYCLKSOURCE_PLL1 PLL1 P divider clock selected as USB PHY clock
+ * @arg @ref RCC_USBPHYCLKSOURCE_PLL1_DIV2 PLL1 P divider clock div by 2 selected as USB PHY clock
+ */
+#define __HAL_RCC_GET_USBPHY_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBPHYCSEL))
+
+#endif /* USB_OTG_HS */
+
+#if defined(RCC_CFGR2_PPRE_DPHY)
+
+/** @brief Macro to configure the DPHY clock.
+ * @param __PRESCALER__ specifies the DPHY clock source prescaler.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_HCLK_DIV1 HCLK divided by 1 selected as DPHY clock
+ * @arg @ref RCC_HCLK_DIV2 HCLK divided by 2 selected as DPHY clock
+ * @arg @ref RCC_HCLK_DIV4 HCLK divided by 4 selected as DPHY clock
+ * @arg @ref RCC_HCLK_DIV8 HCLK divided by 8 selected as DPHY clock
+ * @arg @ref RCC_HCLK_DIV16 HCLK divided by 16 selected as DPHY clock
+ * @retval None
+ */
+#define __HAL_RCC_DPHY_CONFIG(__PRESCALER__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY, (__PRESCALER__) << 8UL)
+
+/** @brief Macro to get the DPHY clock prescaler configuration.
+ * @retval The clock source prescaler can be one of the following values:
+ * @arg @ref RCC_HCLK_DIV1 HCLK divided by 1 selected as DPHY clock
+ * @arg @ref RCC_HCLK_DIV2 HCLK divided by 2 selected as DPHY clock
+ * @arg @ref RCC_HCLK_DIV4 HCLK divided by 4 selected as DPHY clock
+ * @arg @ref RCC_HCLK_DIV8 HCLK divided by 8 selected as DPHY clock
+ * @arg @ref RCC_HCLK_DIV16 HCLK divided by 16 selected as DPHY clock
+ * @retval None
+ */
+#define __HAL_RCC_GET_DPHY_CONFIG() (READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY) >> 8UL)
+
+#endif /* defined(RCC_CFGR2_PPRE_DPHY) */
+
#if defined(CRS)
/**
@@ -1930,12 +2369,12 @@
* @{
*/
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit);
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit);
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit);
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
-void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks);
-void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks);
-void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks);
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk);
+void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks);
+void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks);
+void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks);
/**
* @}
*/
@@ -1944,9 +2383,9 @@
* @{
*/
-HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init);
+HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(const RCC_PLL2InitTypeDef *PLL2Init);
HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);
-HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *PLL3Init);
+HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(const RCC_PLL3InitTypeDef *PLL3Init);
HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void);
HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLFastStartup(void);
HAL_StatusTypeDef HAL_RCCEx_DisableMSIPLLFastStartup(void);
@@ -1954,15 +2393,19 @@
void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);
void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange);
+void HAL_RCCEx_StandbyMSIKRangeConfig(uint32_t MSIKRange);
void HAL_RCCEx_EnableLSECSS(void);
void HAL_RCCEx_DisableLSECSS(void);
+void HAL_RCCEx_EnableLSECSS_IT(void);
+void HAL_RCCEx_EnableMSIPLLUNLCK_IT(void);
void HAL_RCCEx_LSECSS_IRQHandler(void);
void HAL_RCCEx_LSECSS_Callback(void);
+void HAL_RCCEx_MSIPLLUNLCK_IRQHandler(void);
+void HAL_RCCEx_MSIPLLUNLCK_Callback(void);
void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
void HAL_RCCEx_DisableLSCO(void);
void HAL_RCCEx_EnableMSIPLLMode(void);
void HAL_RCCEx_DisableMSIPLLMode(void);
-
/**
* @}
*/
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng.h
index df9b0d4..49dca85 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -318,7 +318,7 @@
*/
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng);
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
@@ -331,8 +331,8 @@
/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
* @{
*/
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
-uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
+HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng);
/**
* @}
*/
@@ -387,3 +387,4 @@
#endif /* STM32U5xx_HAL_RNG_H */
+
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng_ex.h
index c261ecd..ca8bae8 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng_ex.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rng_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -35,19 +35,19 @@
#if defined(RNG)
#if defined(RNG_CR_CONDRST)
-/** @defgroup RNGEx RNGEx
+/** @defgroup RNG_Ex RNG_Ex
* @brief RNG Extension HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
-/** @defgroup RNGEx_Exported_Types RNGEx Exported Types
- * @brief RNGEx Exported types
+/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types
+ * @brief RNG_Ex Exported types
* @{
*/
/**
- * @brief RNGEX Configuration Structure definition
+ * @brief RNG_Ex Configuration Structure definition
*/
typedef struct
@@ -56,11 +56,11 @@
uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */
uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */
uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can
- be a value of @ref RNGEX_Clock_Divider_Factor */
+ be a value of @ref RNG_Ex_Clock_Divider_Factor */
uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a
- value of @ref RNGEX_NIST_Compliance */
+ value of @ref RNG_Ex_NIST_Compliance */
uint32_t AutoReset; /*!< automatic reset When a noise source error occurs
- value of @ref RNGEX_Auto_Reset */
+ value of @ref RNG_Ex_Auto_Reset */
uint32_t HealthTest; /*!< RNG health test control must be a value
between 0x0FFCABFF and 0x00005200 */
} RNG_ConfigTypeDef;
@@ -70,11 +70,11 @@
*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup RNGEX_Exported_Constants RNGEX Exported Constants
+/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants
* @{
*/
-/** @defgroup RNGEX_Clock_Divider_Factor Value used to configure an internal
+/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal
* programmable divider acting on the incoming RNG clock
* @{
*/
@@ -113,7 +113,7 @@
* @}
*/
-/** @defgroup RNGEX_NIST_Compliance NIST Compliance configuration
+/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration
* @{
*/
#define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/
@@ -122,7 +122,7 @@
/**
* @}
*/
-/** @defgroup RNGEX_Auto_Reset Auto Reset configuration
+/** @defgroup RNG_Ex_Auto_Reset Auto Reset configuration
* @{
*/
#define RNG_ARDIS_ENABLE (0x00000000UL) /*!< automatic reset after seed error*/
@@ -137,7 +137,7 @@
*/
/* Private types -------------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Types RNGEx Private Types
+/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types
* @{
*/
@@ -146,7 +146,7 @@
*/
/* Private variables ---------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Variables RNGEx Private Variables
+/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables
* @{
*/
@@ -155,7 +155,7 @@
*/
/* Private constants ---------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Constants RNGEx Private Constants
+/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants
* @{
*/
@@ -164,7 +164,7 @@
*/
/* Private macros ------------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Macros RNGEx Private Macros
+/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros
* @{
*/
@@ -203,7 +203,7 @@
*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Functions RNGEx Private Functions
+/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions
* @{
*/
@@ -212,14 +212,14 @@
*/
/* Exported functions --------------------------------------------------------*/
-/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions
+/** @addtogroup RNG_Ex_Exported_Functions
* @{
*/
-/** @addtogroup RNGEx_Exported_Functions_Group1
+/** @addtogroup RNG_Ex_Exported_Functions_Group1
* @{
*/
-HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf);
HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng);
@@ -227,7 +227,7 @@
* @}
*/
-/** @addtogroup RNGEx_Exported_Functions_Group2
+/** @addtogroup RNG_Ex_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng);
@@ -260,4 +260,5 @@
#endif
-#endif /* STM32U5xx_HAL_RNGEX_H */
+#endif /* STM32U5xx_HAL_RNG_EX_H */
+
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc.h
index 01f4c82..902b9e3 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -289,7 +289,7 @@
/** @defgroup RTC_Hour_Formats RTC Hour Formats
* @{
*/
-#define RTC_HOURFORMAT_24 0x00000000u
+#define RTC_HOURFORMAT_24 0U
#define RTC_HOURFORMAT_12 RTC_CR_FMT
/**
* @}
@@ -298,7 +298,7 @@
/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition
* @{
*/
-#define RTC_OUTPUT_DISABLE 0x00000000u
+#define RTC_OUTPUT_DISABLE 0U
#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL
@@ -310,7 +310,7 @@
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
* @{
*/
-#define RTC_OUTPUT_POLARITY_HIGH 0x00000000u
+#define RTC_OUTPUT_POLARITY_HIGH 0U
#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
/**
* @}
@@ -319,7 +319,7 @@
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
* @{
*/
-#define RTC_OUTPUT_TYPE_PUSHPULL 0x00000000u
+#define RTC_OUTPUT_TYPE_PUSHPULL 0U
#define RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE
/**
* @}
@@ -328,7 +328,7 @@
/** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT
* @{
*/
-#define RTC_OUTPUT_PULLUP_NONE 0x00000000u
+#define RTC_OUTPUT_PULLUP_NONE 0U
#define RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU
/**
* @}
@@ -337,7 +337,7 @@
/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
* @{
*/
-#define RTC_OUTPUT_REMAP_NONE 0x00000000u
+#define RTC_OUTPUT_REMAP_NONE 0U
#define RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN
/**
* @}
@@ -346,8 +346,8 @@
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
* @{
*/
-#define RTC_HOURFORMAT12_AM 0x0u
-#define RTC_HOURFORMAT12_PM 0x1u
+#define RTC_HOURFORMAT12_AM 0U
+#define RTC_HOURFORMAT12_PM 1U
/**
* @}
*/
@@ -357,7 +357,7 @@
*/
#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
-#define RTC_DAYLIGHTSAVING_NONE 0x00000000u
+#define RTC_DAYLIGHTSAVING_NONE 0U
/**
* @}
*/
@@ -365,7 +365,7 @@
/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
* @{
*/
-#define RTC_STOREOPERATION_RESET 0x00000000u
+#define RTC_STOREOPERATION_RESET 0U
#define RTC_STOREOPERATION_SET RTC_CR_BKP
/**
* @}
@@ -374,8 +374,8 @@
/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
* @{
*/
-#define RTC_FORMAT_BIN 0x00000000u
-#define RTC_FORMAT_BCD 0x00000001u
+#define RTC_FORMAT_BIN 0U
+#define RTC_FORMAT_BCD 1U
/**
* @}
*/
@@ -420,7 +420,7 @@
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
* @{
*/
-#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000u
+#define RTC_ALARMDATEWEEKDAYSEL_DATE 0U
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
/**
@@ -430,7 +430,7 @@
/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
* @{
*/
-#define RTC_ALARMMASK_NONE 0x00000000u
+#define RTC_ALARMMASK_NONE 0U
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
@@ -454,8 +454,8 @@
/** @defgroup RTC_ALARM_Flag_AutoClear_Definitions RTC Alarms Flag Auto Clear Definitions
* @{
*/
-#define ALARM_FLAG_AUTOCLR_ENABLE 0x00000001u
-#define ALARM_FLAG_AUTOCLR_DISABLE 0x00000000u
+#define ALARM_FLAG_AUTOCLR_ENABLE 1U
+#define ALARM_FLAG_AUTOCLR_DISABLE 0U
/**
* @}
*/
@@ -463,7 +463,7 @@
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
* @{
*/
-#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000u /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */
+#define RTC_ALARMSUBSECONDMASK_ALL 0U /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */
#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] not used in Alarmcomparison. Only SS[0] is compared. */
#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] not used in Alarm comparison. Only SS[1:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) /*!< SS[14:3] not used in Alarm comparison. Only SS[2:0] are compared */
@@ -498,7 +498,7 @@
/** @defgroup RTC_Interruption_Mask RTC Interruptions Flag Mask
* @{
*/
-#define RTC_FLAG_MASK 0x001Fu /*!< RTC flags mask */
+#define RTC_FLAG_MASK 0x001FU /*!< RTC flags mask */
/**
* @}
*/
@@ -661,7 +661,10 @@
* @arg @ref RTC_IT_ALRB Alarm B interrupt
* @retval None
*/
-#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__))
+#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)( \
+ ((__INTERRUPT__) == RTC_IT_ALRA) ? (SET_BIT(RTC->CR, RTC_CR_ALRAIE)):\
+ ((__INTERRUPT__) == RTC_IT_ALRB) ? (SET_BIT(RTC->CR, RTC_CR_ALRBIE)):\
+ (0U)) /* Dummy action because is an invalid parameter value */
/**
* @brief Disable the RTC Alarm interrupt.
@@ -672,7 +675,10 @@
* @arg @ref RTC_IT_ALRB Alarm B interrupt
* @retval None
*/
-#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__))
+#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)( \
+ ((__INTERRUPT__) == RTC_IT_ALRA) ? (CLEAR_BIT(RTC->CR, RTC_CR_ALRAIE)):\
+ ((__INTERRUPT__) == RTC_IT_ALRB) ? (CLEAR_BIT(RTC->CR, RTC_CR_ALRBIE)):\
+ (0U)) /* Dummy action because is an invalid parameter value */
/**
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
@@ -681,10 +687,12 @@
* This parameter can be:
* @arg @ref RTC_IT_ALRA Alarm A interrupt
* @arg @ref RTC_IT_ALRB Alarm B interrupt
- * @retval None
+ * @retval The state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR)& ((__INTERRUPT__)>> 12U)) != 0U) \
- ? 1UL : 0UL)
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)( \
+ ((__INTERRUPT__) == RTC_IT_ALRA) ? (READ_BIT(RTC->MISR, RTC_MISR_ALRAMF) == RTC_MISR_ALRAMF):\
+ ((__INTERRUPT__) == RTC_IT_ALRB) ? (READ_BIT(RTC->MISR, RTC_MISR_ALRBMF) == RTC_MISR_ALRBMF):\
+ (0U)) /* Return 0 because it is an invalid parameter value */
/**
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
@@ -693,10 +701,12 @@
* This parameter can be:
* @arg @ref RTC_IT_ALRA Alarm A interrupt
* @arg @ref RTC_IT_ALRB Alarm B interrupt
- * @retval None
+ * @retval The state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) \
- ? 1UL : 0UL)
+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)( \
+ ((__INTERRUPT__) == RTC_IT_ALRA) ? (READ_BIT(RTC->CR, RTC_CR_ALRAIE) == RTC_CR_ALRAIE):\
+ ((__INTERRUPT__) == RTC_IT_ALRB) ? (READ_BIT(RTC->CR, RTC_CR_ALRBIE) == RTC_CR_ALRBIE):\
+ (0U)) /* Return 0 because it is an invalid parameter value */
/**
* @brief Get the selected RTC Alarms flag status.
@@ -705,9 +715,12 @@
* This parameter can be:
* @arg @ref RTC_FLAG_ALRAF
* @arg @ref RTC_FLAG_ALRBF
- * @retval None
+ * @retval The state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)( \
+ ((__FLAG__) == RTC_FLAG_ALRAF) ? (READ_BIT(RTC->SR, RTC_SR_ALRAF) == RTC_SR_ALRAF):\
+ ((__FLAG__) == RTC_FLAG_ALRBF) ? (READ_BIT(RTC->SR, RTC_SR_ALRBF) == RTC_SR_ALRBF):\
+ (0U)) /* Return 0 because it is an invalid parameter value */
/**
* @brief Clear the RTC Alarms pending flags.
@@ -718,9 +731,17 @@
* @arg @ref RTC_FLAG_ALRBF
* @retval None
*/
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_ALRAF) \
- ? ((RTC->SCR = (RTC_CLEAR_ALRAF))) :\
- (RTC->SCR = (RTC_CLEAR_ALRBF)))
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)( \
+ ((__FLAG__) == RTC_FLAG_ALRAF) ? (SET_BIT(RTC->SCR, RTC_SCR_CALRAF)):\
+ ((__FLAG__) == RTC_FLAG_ALRBF) ? (SET_BIT(RTC->SCR, RTC_SCR_CALRBF)):\
+ (0U)) /* Dummy action because is an invalid parameter value */
+
+/**
+ * @brief Check whether if the RTC Calendar is initialized.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval The state of RTC Calendar initialization (TRUE or FALSE).
+ */
+#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS))
/**
* @}
@@ -760,14 +781,14 @@
*/
/* RTC Time and Date functions ************************************************/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
-uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+void HAL_RTC_DST_Add1Hour(const RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_Sub1Hour(const RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_SetStoreOperation(const RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_ClearStoreOperation(const RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTC_DST_ReadStoreOperation(const RTC_HandleTypeDef *hrtc);
/**
* @}
*/
@@ -779,10 +800,10 @@
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm,
+HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm,
uint32_t Format);
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout);
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
/**
* @}
@@ -801,7 +822,7 @@
* @{
*/
/* Peripheral State functions *************************************************/
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
+HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc);
/**
* @}
*/
@@ -823,10 +844,10 @@
#define RTC_DR_RESERVED_MASK (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \
RTC_DR_DU)
-#define RTC_INIT_MASK 0xFFFFFFFFu
+#define RTC_INIT_MASK 0xFFFFFFFFU
#define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
-#define RTC_TIMEOUT_VALUE 1000u
+#define RTC_TIMEOUT_VALUE 1000U
/**
* @}
@@ -874,11 +895,11 @@
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \
((FORMAT) == RTC_FORMAT_BCD))
-#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99u)
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
-#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1u) && ((MONTH) <= 12u))
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
-#define IS_RTC_DATE(DATE) (((DATE) >= 1u) && ((DATE) <= 31u))
+#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
@@ -888,7 +909,7 @@
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0u) && ((DATE) <= 31u))
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
@@ -916,13 +937,13 @@
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos))
-#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0u) && ((HOUR) <= 12u))
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23u)
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
-#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59u)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
-#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59u)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
/**
* @}
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc_ex.h
index e46318e..61e1e37 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc_ex.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_rtc_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -132,7 +132,7 @@
uint32_t Seed[RTC_ATAMP_SEED_NB_UINT32];
/*!< Specifies the RNG Seed value.
- This parameter is an array of value from 0 to 0xFFFFFFFF. */
+ This parameter is an array of value from 0 to 0xFFFFFFFF */
RTC_ATampInputTypeDef TampInput[RTC_TAMP_NB];
/*!< Specifies configuration of all active tampers.
@@ -172,12 +172,12 @@
uint32_t rtcNonSecureFeatures; /*!< Specifies the non-secure features.
This parameter is only relevant if RTC is not fully secure
- (rtcSecureFull == RTC_SECURE_FULL_NO).
+ (rtcSecureFull == RTC_SECURE_FULL_NO).
This parameter can be a combination of
@ref RTCEx_RTC_NonSecure_Features. */
uint32_t tampSecureFull; /*!< Specifies If the TAMP is fully secure or not execpt monotonic counters
- and BackUp registers.
+ and BackUp registers.
This parameter can be a value of @ref RTCEx_TAMP_Secure_Full */
uint32_t backupRegisterStartZone2; /*!< Specifies the backup register start zone 2
@@ -195,7 +195,7 @@
uint32_t MonotonicCounterSecure; /*!< Specifies If the monotonic counter is secure or not
This parameter can be a value of
- @ref RTCEx_TAMP_Monotonic_Counter_Secure */
+ @ref RTCEx_TAMP_Monotonic_Counter_Secure */
} RTC_SecureStateTypeDef;
/**
* @}
@@ -226,8 +226,8 @@
disabled. */
uint32_t backupRegisterStartZone2; /*!< Specifies the backup register start zone 2.
- Zone 1 : read secure write secure.
- Zone 2 : read non-secure write secure.
+ Zone 1 granted accesses : read secure, write secure.
+ Zone 2 granted accesses : read non-secure, write secure.
This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify
the register .
Warning : this parameter is writable in secure mode or if trustzone is
@@ -235,7 +235,7 @@
Warning : this parameter is shared with RTC_SecureStateTypeDef */
uint32_t backupRegisterStartZone3; /*!< Specifies the backup register start zone 3.
- Zone 3 : read non-secure write non-secure.
+ Zone 3 granted accesses : read non-secure, write non-secure.
This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify
the register.
Warning : this parameter is writable in secure mode or if trustzone is
@@ -262,8 +262,8 @@
/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition
* @{
*/
-#define RTC_TIMESTAMPEDGE_RISING 0x00000000u
-#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
+#define RTC_TIMESTAMPEDGE_RISING 0U
+#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
/**
* @}
*/
@@ -271,7 +271,7 @@
/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection
* @{
*/
-#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000u
+#define RTC_TIMESTAMPPIN_DEFAULT 0U
/**
* @}
*/
@@ -279,12 +279,12 @@
/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions
* @{
*/
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000u
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
-#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2
-#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0U
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2
+#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
/**
* @}
*/
@@ -292,12 +292,12 @@
/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions
* @{
*/
-#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000u /*!< If RTCCLK = 32768 Hz, Smooth calibration
- period is 32s, else 2exp20 RTCCLK pulses */
-#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibration
- period is 16s, else 2exp19 RTCCLK pulses */
-#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibration
- period is 8s, else 2exp18 RTCCLK pulses */
+#define RTC_SMOOTHCALIB_PERIOD_32SEC 0U /*!< If RTCCLK = 32768 Hz, Smooth calibration period
+ is 32s, else 2exp20 RTCCLK pulses */
+#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibration period
+ is 16s, else 2exp19 RTCCLK pulses */
+#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibration period
+ is 8s, else 2exp18 RTCCLK pulses */
/**
* @}
*/
@@ -305,11 +305,11 @@
/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions
* @{
*/
-#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added
- during a X -second window = Y - CALM[8:0]
- with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000u /*!< The number of RTCCLK pulses subbstited
- during a 32-second window = CALM[8:0] */
+#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added
+ during a X -second window = Y - CALM[8:0]
+ with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0U /*!< The number of RTCCLK pulses subbstited
+ during a 32-second window = CALM[8:0] */
/**
* @}
*/
@@ -317,13 +317,10 @@
/** @defgroup RTCEx_Smooth_calib_low_power_Definitions RTCEx Smooth calib Low Power Definitions
* @{
*/
-#define RTC_LPCAL_SET RTC_CALR_LPCAL /*!< Calibration window is 220 ck_apre,
- which is the required configuration for
- ultra-low consumption mode. */
-#define RTC_LPCAL_RESET 0x00000000u /*!< Calibration window is 220 RTCCLK,
- which is a high-consumption mode.
- This mode should be set only when less
- than 32s calibration window is required. */
+#define RTC_LPCAL_SET RTC_CALR_LPCAL /*!< Calibration window is 2exp20 ck_apre, which is the required configuration for ultra-low consumption mode. */
+#define RTC_LPCAL_RESET 0U /*!< Calibration window is 2exp20 RTCCLK, which is a high-consumption mode.
+ This mode should be set only when less
+ than 32s calibration window is required. */
/**
* @}
*/
@@ -331,9 +328,8 @@
/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
* @{
*/
-#define RTC_CALIBOUTPUT_512HZ 0x00000000u
-#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
-
+#define RTC_CALIBOUTPUT_512HZ 0U
+#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
/**
* @}
*/
@@ -342,8 +338,8 @@
/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions
* @{
*/
-#define RTC_SHIFTADD1S_RESET 0x00000000u
-#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
+#define RTC_SHIFTADD1S_RESET 0U
+#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
/**
* @}
*/
@@ -401,10 +397,10 @@
/** @defgroup RTCEx_Tamper_Trigger RTCEx Tamper Trigger
* @{
*/
-#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
-#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x01u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
-#define RTC_TAMPERTRIGGER_LOWLEVEL 0x02u /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
-#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x03u /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
+#define RTC_TAMPERTRIGGER_RISINGEDGE 0U /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
+#define RTC_TAMPERTRIGGER_FALLINGEDGE 1U /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
+#define RTC_TAMPERTRIGGER_LOWLEVEL 2U /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
+#define RTC_TAMPERTRIGGER_HIGHLEVEL 3U /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
/**
* @}
*/
@@ -421,8 +417,8 @@
/** @defgroup RTCEx_Tamper_EraseBackUp RTCEx Tamper EraseBackUp
* @{
*/
-#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u
-#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u
+#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0U
+#define RTC_TAMPER_ERASE_BACKUP_DISABLE 1U
/**
* @}
*/
@@ -430,7 +426,7 @@
/** @defgroup RTCEx_Tamper_Filter RTCEx Tamper Filter
* @{
*/
-#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
+#define RTC_TAMPERFILTER_DISABLE 0U /*!< Tamper filter is disabled */
#define RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2
consecutive samples at the active level */
#define RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4
@@ -444,7 +440,7 @@
/** @defgroup RTCEx_Tamper_Sampling_Frequencies RTCEx Tamper Sampling Frequencies
* @{
*/
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */
@@ -460,7 +456,7 @@
/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration RTCEx Tamper Pin Precharge Duration
* @{
*/
-#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */
+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */
#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1) /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
@@ -471,7 +467,7 @@
/** @defgroup RTCEx_Tamper_Pull_UP RTCEx Tamper Pull UP
* @{
*/
-#define RTC_TAMPER_PULLUP_ENABLE 0x00000000u /*!< Tamper pins are pre-charged before sampling */
+#define RTC_TAMPER_PULLUP_ENABLE 0U /*!< Tamper pins are pre-charged before sampling */
#define RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS /*!< Tamper pins pre-charge is disabled */
/**
* @}
@@ -480,7 +476,7 @@
/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection RTCEx Tamper TimeStamp On Tamper Detection Definitions
* @{
*/
-#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000u /*!< TimeStamp on Tamper Detection event is not saved */
+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0U /*!< TimeStamp on Tamper Detection event is not saved */
#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */
/**
* @}
@@ -534,9 +530,9 @@
#define RTC_FLAG_TAMP_6 TAMP_SR_TAMP6F
#define RTC_FLAG_TAMP_7 TAMP_SR_TAMP7F
#define RTC_FLAG_TAMP_8 TAMP_SR_TAMP8F
-#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3 |\
- RTC_FLAG_TAMP_4 | RTC_FLAG_TAMP_5 | RTC_FLAG_TAMP_6 |\
- RTC_FLAG_TAMP_7 | RTC_FLAG_TAMP_8)
+#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3 |\
+ RTC_FLAG_TAMP_4 | RTC_FLAG_TAMP_5 | RTC_FLAG_TAMP_6 |\
+ RTC_FLAG_TAMP_7 | RTC_FLAG_TAMP_8)
#define RTC_FLAG_INT_TAMP_1 TAMP_SR_ITAMP1F
@@ -564,8 +560,8 @@
/** @defgroup RTCEx_ActiveTamper_Enable RTCEx_ActiveTamper_Enable Definitions
* @{
*/
-#define RTC_ATAMP_ENABLE 1u
-#define RTC_ATAMP_DISABLE 0u
+#define RTC_ATAMP_ENABLE 1U
+#define RTC_ATAMP_DISABLE 0U
/**
* @}
*/
@@ -573,8 +569,8 @@
/** @defgroup RTCEx_ActiveTamper_Interrupt RTCEx_ActiveTamper_Interrupt Definitions
* @{
*/
-#define RTC_ATAMP_INTERRUPT_ENABLE 1u
-#define RTC_ATAMP_INTERRUPT_DISABLE 0u
+#define RTC_ATAMP_INTERRUPT_ENABLE 1U
+#define RTC_ATAMP_INTERRUPT_DISABLE 0U
/**
* @}
*/
@@ -583,7 +579,7 @@
* @{
*/
#define RTC_ATAMP_FILTER_ENABLE TAMP_ATCR1_FLTEN
-#define RTC_ATAMP_FILTER_DISABLE 0u
+#define RTC_ATAMP_FILTER_DISABLE 0U
/**
* @}
*/
@@ -591,14 +587,15 @@
/** @defgroup RTCEx_ActiveTamper_Async_prescaler RTCEx Active_Tamper_Asynchronous_Prescaler clock Definitions
* @{
*/
-#define RTC_ATAMP_ASYNCPRES_RTCCLK 0u /*!< RTCCLK */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK 0U /*!< RTCCLK */
#define RTC_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */
#define RTC_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */
-#define RTC_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */
#define RTC_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */
#define RTC_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */
#define RTC_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */
#define RTC_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_2048 (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/2048 */
/**
* @}
*/
@@ -606,14 +603,14 @@
/** @defgroup RTCEx_ActiveTamper_Sel RTCEx Active Tamper selection Definition
* @{
*/
-#define RTC_ATAMP_1 0u /*!< Tamper 1 */
-#define RTC_ATAMP_2 1u /*!< Tamper 2 */
-#define RTC_ATAMP_3 2u /*!< Tamper 3 */
-#define RTC_ATAMP_4 3u /*!< Tamper 4 */
-#define RTC_ATAMP_5 4u /*!< Tamper 5 */
-#define RTC_ATAMP_6 5u /*!< Tamper 6 */
-#define RTC_ATAMP_7 6u /*!< Tamper 7 */
-#define RTC_ATAMP_8 7u /*!< Tamper 8 */
+#define RTC_ATAMP_1 0U /*!< Tamper 1 */
+#define RTC_ATAMP_2 1U /*!< Tamper 2 */
+#define RTC_ATAMP_3 2U /*!< Tamper 3 */
+#define RTC_ATAMP_4 3U /*!< Tamper 4 */
+#define RTC_ATAMP_5 4U /*!< Tamper 5 */
+#define RTC_ATAMP_6 5U /*!< Tamper 6 */
+#define RTC_ATAMP_7 6U /*!< Tamper 7 */
+#define RTC_ATAMP_8 7U /*!< Tamper 8 */
/**
* @}
*/
@@ -621,7 +618,7 @@
/** @defgroup RTCEx_MonotonicCounter_Instance RTCEx Monotonic Counter Instance Definition
* @{
*/
-#define RTC_MONOTONIC_COUNTER_1 0u /*!< Monotonic counter 1 */
+#define RTC_MONOTONIC_COUNTER_1 0U /*!< Monotonic counter 1 */
/**
* @}
*/
@@ -629,39 +626,39 @@
/** @defgroup RTCEx_Backup_Registers RTCEx Backup Registers Definition
* @{
*/
-#define RTC_BKP_NUMBER RTC_BKP_NB
-#define RTC_BKP_DR0 0x00u
-#define RTC_BKP_DR1 0x01u
-#define RTC_BKP_DR2 0x02u
-#define RTC_BKP_DR3 0x03u
-#define RTC_BKP_DR4 0x04u
-#define RTC_BKP_DR5 0x05u
-#define RTC_BKP_DR6 0x06u
-#define RTC_BKP_DR7 0x07u
-#define RTC_BKP_DR8 0x08u
-#define RTC_BKP_DR9 0x09u
-#define RTC_BKP_DR10 0x0Au
-#define RTC_BKP_DR11 0x0Bu
-#define RTC_BKP_DR12 0x0Cu
-#define RTC_BKP_DR13 0x0Du
-#define RTC_BKP_DR14 0x0Eu
-#define RTC_BKP_DR15 0x0Fu
-#define RTC_BKP_DR16 0x10u
-#define RTC_BKP_DR17 0x11u
-#define RTC_BKP_DR18 0x12u
-#define RTC_BKP_DR19 0x13u
-#define RTC_BKP_DR20 0x14u
-#define RTC_BKP_DR21 0x15u
-#define RTC_BKP_DR22 0x16u
-#define RTC_BKP_DR23 0x17u
-#define RTC_BKP_DR24 0x18u
-#define RTC_BKP_DR25 0x19u
-#define RTC_BKP_DR26 0x1Au
-#define RTC_BKP_DR27 0x1Bu
-#define RTC_BKP_DR28 0x1Cu
-#define RTC_BKP_DR29 0x1Du
-#define RTC_BKP_DR30 0x1Eu
-#define RTC_BKP_DR31 0x1Fu
+#define RTC_BKP_NUMBER RTC_BKP_NB
+#define RTC_BKP_DR0 0x00U
+#define RTC_BKP_DR1 0x01U
+#define RTC_BKP_DR2 0x02U
+#define RTC_BKP_DR3 0x03U
+#define RTC_BKP_DR4 0x04U
+#define RTC_BKP_DR5 0x05U
+#define RTC_BKP_DR6 0x06U
+#define RTC_BKP_DR7 0x07U
+#define RTC_BKP_DR8 0x08U
+#define RTC_BKP_DR9 0x09U
+#define RTC_BKP_DR10 0x0AU
+#define RTC_BKP_DR11 0x0BU
+#define RTC_BKP_DR12 0x0CU
+#define RTC_BKP_DR13 0x0DU
+#define RTC_BKP_DR14 0x0EU
+#define RTC_BKP_DR15 0x0FU
+#define RTC_BKP_DR16 0x10U
+#define RTC_BKP_DR17 0x11U
+#define RTC_BKP_DR18 0x12U
+#define RTC_BKP_DR19 0x13U
+#define RTC_BKP_DR20 0x14U
+#define RTC_BKP_DR21 0x15U
+#define RTC_BKP_DR22 0x16U
+#define RTC_BKP_DR23 0x17U
+#define RTC_BKP_DR24 0x18U
+#define RTC_BKP_DR25 0x19U
+#define RTC_BKP_DR26 0x1AU
+#define RTC_BKP_DR27 0x1BU
+#define RTC_BKP_DR28 0x1CU
+#define RTC_BKP_DR29 0x1DU
+#define RTC_BKP_DR30 0x1EU
+#define RTC_BKP_DR31 0x1FU
/**
* @}
*/
@@ -669,25 +666,25 @@
* Warning : It Should not be confused with the Binary format @ref RTC_Input_parameter_format_definitions.
* @{
*/
-#define RTC_BINARY_NONE 0x00000000u /*!< Free running BCD calendar mode (Binary mode disabled). */
-#define RTC_BINARY_ONLY RTC_ICSR_BIN_0 /*!< Free running Binary mode (BCD mode disabled) */
-#define RTC_BINARY_MIX RTC_ICSR_BIN_1 /*!< Free running BCD calendar and Binary modes */
+#define RTC_BINARY_NONE 0U /*!< Free running BCD calendar mode (Binary mode disabled) */
+#define RTC_BINARY_ONLY RTC_ICSR_BIN_0 /*!< Free running Binary mode (BCD mode disabled) */
+#define RTC_BINARY_MIX RTC_ICSR_BIN_1 /*!< Free running BCD calendar and Binary modes */
/**
* @}
*/
/** @defgroup RTCEx_Binary_mix_BCDU If Binary mode is RTC_BINARY_MIX, the BCD calendar second is incremented
- * using the SSR Least Significant Bits.
+ * using the SSR Least Significant Bits.
* @{
*/
-#define RTC_BINARY_MIX_BCDU_0 0x00000000u /*!< The 1s BCD calendar increment is generated each time SS[7:0] = 0 */
-#define RTC_BINARY_MIX_BCDU_1 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[8:0] = 0 */
-#define RTC_BINARY_MIX_BCDU_2 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[9:0] = 0 */
-#define RTC_BINARY_MIX_BCDU_3 (0x3UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[10:0] = 0 */
-#define RTC_BINARY_MIX_BCDU_4 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[11:0] = 0 */
-#define RTC_BINARY_MIX_BCDU_5 (0x5UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[12:0] = 0 */
-#define RTC_BINARY_MIX_BCDU_6 (0x6UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[13:0] = 0 */
-#define RTC_BINARY_MIX_BCDU_7 (0x7UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[14:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_0 0U /*!< The 1s BCD calendar increment is generated each time SS[7:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_1 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[8:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_2 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[9:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_3 (0x3UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[10:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_4 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[11:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_5 (0x5UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[12:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_6 (0x6UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[13:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_7 (0x7UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[14:0] = 0 */
/**
* @}
*/
@@ -695,7 +692,7 @@
/** @defgroup RTCEx_Alarm_Sub_Seconds_binary_Masks_Definitions RTC Alarm Sub Seconds with binary mode Masks Definitions
* @{
*/
-#define RTC_ALARMSUBSECONDBINMASK_ALL 0x00000000u /*!< All Alarm SS fields are masked.There is no comparison on sub seconds for Alarm */
+#define RTC_ALARMSUBSECONDBINMASK_ALL 0U /*!< All Alarm SS fields are masked.There is no comparison on sub seconds for Alarm */
#define RTC_ALARMSUBSECONDBINMASK_SS31_1 (1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:1] are don't care in Alarm comparison. Only SS[0] is compared. */
#define RTC_ALARMSUBSECONDBINMASK_SS31_2 (2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:2] are don't care in Alarm comparison. Only SS[1:0] are compared */
#define RTC_ALARMSUBSECONDBINMASK_SS31_3 (3UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:3] are don't care in Alarm comparison. Only SS[2:0] are compared */
@@ -746,7 +743,7 @@
* @{
*/
#define RTC_SECURE_FULL_YES RTC_SECCFGR_SEC /*!< RTC full secure */
-#define RTC_SECURE_FULL_NO 0u /*!< RTC is not full secure, features can be unsecure. See RTC_LL_EC_UNSECURE_RTC_FEATURE */
+#define RTC_SECURE_FULL_NO 0U /*!< RTC is not full secure, features can be unsecure. See RTC_LL_EC_UNSECURE_RTC_FEATURE */
/**
* @}
*/
@@ -764,7 +761,7 @@
#define RTC_NONSECURE_FEATURE_WUT ~RTC_SECCFGR_WUTSEC /*!< Wake up timer */
#define RTC_NONSECURE_FEATURE_ALRA ~RTC_SECCFGR_ALRASEC /*!< Alarm A */
#define RTC_NONSECURE_FEATURE_ALRB ~RTC_SECCFGR_ALRBSEC /*!< Alarm B */
-#define RTC_NONSECURE_FEATURE_ALL 0u
+#define RTC_NONSECURE_FEATURE_ALL 0U
/**
* @}
*/
@@ -773,7 +770,7 @@
* @{
*/
#define TAMP_SECURE_FULL_YES TAMP_SECCFGR_TAMPSEC /*!< TAMPER full secure */
-#define TAMP_SECURE_FULL_NO 0u /*!< TAMPER is not secure */
+#define TAMP_SECURE_FULL_NO 0U /*!< TAMPER is not secure */
/**
* @}
*/
@@ -782,7 +779,7 @@
* @{
*/
#define TAMP_MONOTONIC_CNT_SECURE_YES TAMP_SECCFGR_CNT1SEC /*!< TAMPER Monotonic Counter secure */
-#define TAMP_MONOTONIC_CNT_SECURE_NO 0u /*!< TAMPER Monotonic Counter is not secure */
+#define TAMP_MONOTONIC_CNT_SECURE_NO 0U /*!< TAMPER Monotonic Counter is not secure */
/**
* @}
*/
@@ -790,7 +787,7 @@
* @{
*/
#define RTC_PRIVILEGE_FULL_YES RTC_PRIVCFGR_PRIV
-#define RTC_PRIVILEGE_FULL_NO 0u
+#define RTC_PRIVILEGE_FULL_NO 0U
/**
* @}
*/
@@ -798,7 +795,7 @@
/** @defgroup RTCEx_RTC_Privilege_Features RTCEx Privilege Features Definition
* @{
*/
-#define RTC_PRIVILEGE_FEATURE_NONE 0u
+#define RTC_PRIVILEGE_FEATURE_NONE 0U
#define RTC_PRIVILEGE_FEATURE_INIT RTC_PRIVCFGR_INITPRIV /*!< Initialization */
#define RTC_PRIVILEGE_FEATURE_CAL RTC_PRIVCFGR_CALPRIV /*!< Calibration */
#define RTC_PRIVILEGE_FEATURE_TS RTC_PRIVCFGR_TSPRIV /*!< Time stamp */
@@ -816,7 +813,7 @@
* @{
*/
#define TAMP_PRIVILEGE_FULL_YES TAMP_PRIVCFGR_TAMPPRIV
-#define TAMP_PRIVILEGE_FULL_NO 0u
+#define TAMP_PRIVILEGE_FULL_NO 0U
/**
* @}
*/
@@ -825,7 +822,7 @@
* @{
*/
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_ERCFGR0
-#define TAMP_SECRETDEVICE_ERASE_DISABLE 0u
+#define TAMP_SECRETDEVICE_ERASE_DISABLE 0U
/**
* @}
*/
@@ -834,7 +831,7 @@
* @{
*/
#define TAMP_MONOTONIC_CNT_PRIVILEGE_YES TAMP_PRIVCFGR_CNT1PRIV
-#define TAMP_MONOTONIC_CNT_PRIVILEGE_NO 0u
+#define TAMP_MONOTONIC_CNT_PRIVILEGE_NO 0U
/**
* @}
*/
@@ -842,7 +839,7 @@
/** @defgroup RTCEx_Backup_Reg_Privilege_zone RTCEx Privilege Backup register privilege zone Definition
* @{
*/
-#define RTC_PRIVILEGE_BKUP_ZONE_NONE 0u
+#define RTC_PRIVILEGE_BKUP_ZONE_NONE 0U
#define RTC_PRIVILEGE_BKUP_ZONE_1 TAMP_PRIVCFGR_BKPRWPRIV
#define RTC_PRIVILEGE_BKUP_ZONE_2 TAMP_PRIVCFGR_BKPWPRIV
#define RTC_PRIVILEGE_BKUP_ZONE_ALL (RTC_PRIVILEGE_BKUP_ZONE_1 | RTC_PRIVILEGE_BKUP_ZONE_2)
@@ -883,24 +880,48 @@
* @arg @ref RTC_FLAG_INITS Initialization status flag
* @arg @ref RTC_FLAG_SHPF Shift operation pending flag
* @arg @ref RTC_FLAG_WUTWF Wakeup timer write flag
- * @arg @ref RTC_FLAG_ALRAF Alarm A write flag
- * @arg @ref RTC_FLAG_ALRBF Alarm B write flag
* @arg @ref RTC_FLAG_ITSF Internal Time-stamp flag
* @arg @ref RTC_FLAG_TSOVF Time-stamp overflow flag
* @arg @ref RTC_FLAG_TSF Time-stamp flag
* @arg @ref RTC_FLAG_WUTF Wakeup timer flag
* @arg @ref RTC_FLAG_ALRBF Alarm B flag
* @arg @ref RTC_FLAG_ALRAF Alarm A flag
- * @retval None
+ * @retval The state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? (RTC->ICSR &\
- (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) : \
- (RTC->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))))
+#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__)( \
+ ((__FLAG__) == RTC_FLAG_RECALPF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) == \
+ RTC_ICSR_RECALPF) : \
+ ((__FLAG__) == RTC_FLAG_INITF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == \
+ RTC_ICSR_INITF) : \
+ ((__FLAG__) == RTC_FLAG_RSF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == \
+ RTC_ICSR_RSF) : \
+ ((__FLAG__) == RTC_FLAG_INITS) ? (READ_BIT(RTC->ICSR, RTC_ICSR_INITS) == \
+ RTC_ICSR_INITS) : \
+ ((__FLAG__) == RTC_FLAG_SHPF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) == \
+ RTC_ICSR_SHPF) : \
+ ((__FLAG__) == RTC_FLAG_WUTWF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == \
+ RTC_ICSR_WUTWF) : \
+ ((__FLAG__) == RTC_FLAG_SSRUF) ? (READ_BIT(RTC->SR, RTC_SR_SSRUF) == \
+ RTC_SR_SSRUF) : \
+ ((__FLAG__) == RTC_FLAG_ITSF) ? (READ_BIT(RTC->SR, RTC_SR_ITSF) == \
+ RTC_SR_ITSF) : \
+ ((__FLAG__) == RTC_FLAG_TSOVF) ? (READ_BIT(RTC->SR, RTC_SR_TSOVF) == \
+ RTC_SR_TSOVF) : \
+ ((__FLAG__) == RTC_FLAG_TSF) ? (READ_BIT(RTC->SR, RTC_SR_TSF) == \
+ RTC_SR_TSF): \
+ ((__FLAG__) == RTC_FLAG_WUTF) ? (READ_BIT(RTC->SR, RTC_SR_WUTF) == \
+ RTC_SR_WUTF): \
+ ((__FLAG__) == RTC_FLAG_ALRBF) ? (READ_BIT(RTC->SR, RTC_SR_ALRBF) == \
+ RTC_SR_ALRBF) : \
+ ((__FLAG__) == RTC_FLAG_ALRAF) ? (READ_BIT(RTC->SR, RTC_SR_ALRAF) == \
+ RTC_SR_ALRAF) : \
+ (0U)) /* Return 0 because it is an invalid parameter value */
/* ---------------------------------WAKEUPTIMER---------------------------------*/
/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
* @{
*/
+
/**
* @brief Enable the RTC WakeUp Timer peripheral.
* @param __HANDLE__ specifies the RTC handle.
@@ -923,7 +944,7 @@
* @arg @ref RTC_IT_WUT WakeUpTimer interrupt
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__))
+#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (RTC_CR_WUTIE))
/**
* @brief Disable the RTC WakeUpTimer interrupt.
@@ -933,8 +954,7 @@
* @arg @ref RTC_IT_WUT WakeUpTimer interrupt
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__))
-
+#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(RTC_CR_WUTIE))
/**
* @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
@@ -942,20 +962,19 @@
* @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
* This parameter can be:
* @arg @ref RTC_IT_WUT WakeUpTimer interrupt
- * @retval None
+ * @retval The state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) !=\
- 0UL) ? 1UL : 0UL)
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & (RTC_MISR_WUTMF)) != 0U)
+
/**
* @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
* This parameter can be:
* @arg @ref RTC_IT_WUT WakeUpTimer interrupt
- * @retval None
+ * @retval The state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != \
- 0UL) ? 1UL : 0UL)
+#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((RTC->CR) & (RTC_CR_WUTIE)) != 0U)
/**
* @brief Get the selected RTC WakeUpTimers flag status.
@@ -964,9 +983,12 @@
* This parameter can be:
* @arg @ref RTC_FLAG_WUTF
* @arg @ref RTC_FLAG_WUTWF
- * @retval None
+ * @retval The state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)( \
+ ((__FLAG__) == RTC_FLAG_WUTF) ? (READ_BIT(RTC->SR, RTC_SR_WUTF) == RTC_SR_WUTF):\
+ ((__FLAG__) == RTC_FLAG_WUTWF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == RTC_ICSR_WUTWF):\
+ (0U)) /* Return 0 because it is an invalid parameter value */
/**
* @brief Clear the RTC Wake Up timers pending flags.
@@ -976,14 +998,17 @@
* @arg @ref RTC_FLAG_WUTF
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF))
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CWUTF))
+
/**
* @}
*/
+
/* ---------------------------------TIMESTAMP---------------------------------*/
/** @defgroup RTCEx_Timestamp RTC Timestamp
* @{
*/
+
/**
* @brief Enable the RTC TimeStamp peripheral.
* @param __HANDLE__ specifies the RTC handle.
@@ -1006,7 +1031,7 @@
* @arg @ref RTC_IT_TS TimeStamp interrupt
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__))
+#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (RTC_CR_TSIE))
/**
* @brief Disable the RTC TimeStamp interrupt.
@@ -1016,7 +1041,7 @@
* @arg @ref RTC_IT_TS TimeStamp interrupt
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__))
+#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(RTC_CR_TSIE))
/**
* @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
@@ -1024,20 +1049,19 @@
* @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
* This parameter can be:
* @arg @ref RTC_IT_TS TimeStamp interrupt
- * @retval None
+ * @retval The state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) != \
- 0U) ? 1UL : 0UL)
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & (RTC_MISR_TSMF)) != 0U)
+
/**
* @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
* This parameter can be:
* @arg @ref RTC_IT_TS TimeStamp interrupt
- * @retval None
+ * @retval The state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) ?\
- 1UL : 0UL)
+#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((RTC->CR) & (RTC_CR_TSIE)) != 0U)
/**
* @brief Get the selected RTC TimeStamps flag status.
@@ -1046,9 +1070,12 @@
* This parameter can be:
* @arg @ref RTC_FLAG_TSF
* @arg @ref RTC_FLAG_TSOVF
- * @retval None
+ * @retval The state of __FLAG__ (TRUE or FALSE) or 255 if invalid parameter.
*/
-#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)( \
+ ((__FLAG__) == RTC_FLAG_TSF) ? (READ_BIT(RTC->SR, RTC_SR_TSF) == RTC_SR_TSF):\
+ ((__FLAG__) == RTC_FLAG_TSOVF) ? (READ_BIT(RTC->SR, RTC_SR_TSOVF) == RTC_SR_TSOVF):\
+ (0U)) /* Return 0 because it is an invalid parameter value */
/**
* @brief Clear the RTC Time Stamps pending flags.
@@ -1059,9 +1086,10 @@
* @arg @ref RTC_FLAG_TSOVF
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_TSF) ? \
- (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSF)) : \
- (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSOVF)))
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)( \
+ ((__FLAG__) == RTC_FLAG_TSF) ? (SET_BIT(RTC->SCR, RTC_SCR_CTSF)):\
+ ((__FLAG__) == RTC_FLAG_TSOVF) ? (SET_BIT(RTC->SCR, RTC_SCR_CTSOVF)):\
+ (0U)) /* Dummy action because is an invalid parameter value */
/**
* @brief Enable the RTC internal TimeStamp peripheral.
@@ -1085,8 +1113,7 @@
* @arg @ref RTC_FLAG_ITSF
* @retval None
*/
-#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),\
- (__FLAG__)))
+#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->SR, RTC_SR_ITSF) == RTC_SR_ITSF))
/**
* @brief Clear the RTC Internal Time Stamps pending flags.
@@ -1096,8 +1123,7 @@
* @arg @ref RTC_FLAG_ITSF
* @retval None
*/
-#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__),\
- RTC_CLEAR_ITSF))
+#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CITSF))
/**
* @brief Enable the RTC TimeStamp on Tamper detection.
@@ -1173,9 +1199,9 @@
* @param __FLAG__ specifies the RTC shift operation Flag is pending or not.
* This parameter can be:
* @arg @ref RTC_FLAG_SHPF
- * @retval None
+ * @retval The state of __FLAG__ (TRUE or FALSE)
*/
-#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
+#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) == RTC_ICSR_SHPF))
/**
* @}
*/
@@ -1184,6 +1210,7 @@
/** @defgroup RTCEx_Tamper RTCEx tamper
* @{
*/
+
/**
* @brief Enable the TAMP Tamper input detection.
* @param __HANDLE__ specifies the RTC handle.
@@ -1219,6 +1246,7 @@
*/
#define __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 &= ~(__TAMPER__))
+
/**************************************************************************************************/
/**
* @brief Enable the TAMP Tamper interrupt.
@@ -1256,6 +1284,7 @@
*/
#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER &= ~(__INTERRUPT__))
+
/**************************************************************************************************/
/**
* @brief Check whether the specified RTC Tamper interrupt has occurred or not.
@@ -1283,7 +1312,7 @@
* @arg RTC_IT_INT_TAMP_11: Internal Tamper11 interrupt
* @arg RTC_IT_INT_TAMP_12: Internal Tamper12 interrupt
* @arg RTC_IT_INT_TAMP_13: Internal Tamper13 interrupt
- * @retval None
+ * @retval The state of __INTERRUPT__ (TRUE or FALSE)
*/
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((TAMP->MISR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)
@@ -1313,7 +1342,7 @@
* @arg RTC_IT_INT_TAMP_11: Internal Tamper11 interrupt
* @arg RTC_IT_INT_TAMP_12: Internal Tamper12 interrupt
* @arg RTC_IT_INT_TAMP_13: Internal Tamper13 interrupt
- * @retval None
+ * @retval The state of __INTERRUPT__ (TRUE or FALSE)
*/
#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((TAMP->IER) & (__INTERRUPT__)) != \
0U) ? 1UL : 0UL)
@@ -1343,7 +1372,7 @@
* @arg RTC_FLAG_INT_TAMP_11: Internal Tamper11 flag
* @arg RTC_FLAG_INT_TAMP_12: Internal Tamper12 flag
* @arg RTC_FLAG_INT_TAMP_13: Internal Tamper13 flag
- * @retval None
+ * @retval The state of __FLAG__ (TRUE or FALSE)
*/
#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((TAMP->SR) & (__FLAG__)) != 0U)
@@ -1394,7 +1423,7 @@
* @arg @ref RTC_IT_SSRU SSRU interrupt
* @retval None
*/
-#define __HAL_RTC_SSRU_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__))
+#define __HAL_RTC_SSRU_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (RTC_CR_SSRUIE))
/**
* @brief Disable the RTC SSRU interrupt.
@@ -1404,7 +1433,8 @@
* @arg @ref RTC_IT_SSRU SSRU interrupt
* @retval None
*/
-#define __HAL_RTC_SSRU_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__))
+#define __HAL_RTC_SSRU_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(RTC_CR_SSRUIE))
+
/**
* @brief Check whether the specified RTC SSRU interrupt has occurred or not.
@@ -1412,19 +1442,18 @@
* @param __INTERRUPT__ specifies the RTC SSRU interrupt to check.
* This parameter can be:
* @arg @ref RTC_IT_SSRU SSRU interrupt
- * @retval None
+ * @retval The state of __INTERRUPT__ (TRUE or FALSE)
*/
-#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & ((__INTERRUPT__) >> 1) != 0U) \
- ? 1U : 0U)
+#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & (RTC_MISR_SSRUMF)) != 0U) ? 1U : 0U)
/**
* @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
* This parameter can be:
* @arg @ref RTC_IT_SSRU SSRU interrupt
- * @retval None
+ * @retval The state of __INTERRUPT__ (TRUE or FALSE)
*/
-#define __HAL_RTC_SSRU_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
+#define __HAL_RTC_SSRU_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (RTC_CR_SSRUIE)) != 0U) ? 1U : 0U)
/**
* @brief Get the selected RTC SSRU's flag status.
@@ -1432,9 +1461,9 @@
* @param __FLAG__ specifies the RTC SSRU Flag is pending or not.
* This parameter can be:
* @arg @ref RTC_FLAG_SSRUF
- * @retval None
+ * @retval The state of __FLAG__ (TRUE or FALSE)
*/
-#define __HAL_RTC_SSRU_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
+#define __HAL_RTC_SSRU_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->SR, RTC_SR_SSRUF) == RTC_SR_SSRUF))
/**
* @brief Clear the RTC Wake Up timer's pending flags.
@@ -1444,14 +1473,15 @@
* @arg @ref RTC_FLAG_SSRUF
* @retval None
*/
-#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_SSRUF))
+#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CSSRUF))
+/**
+ * @}
+ */
/**
* @}
*/
-/**
- * @}
- */
+
/* Exported functions --------------------------------------------------------*/
/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
* @{
@@ -1526,7 +1556,7 @@
*/
void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout);
/**
* @}
*/
@@ -1658,11 +1688,11 @@
((LPCAL) == RTC_LPCAL_RESET))
-#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_ALL) != 0x00U) && \
- (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0x00U))
+#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_ALL) != 0U) && \
+ (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0U))
-#define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__) ((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0x00U) && \
- (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0x00U))
+#define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__) ((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0U) && \
+ (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0U))
#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
@@ -1713,7 +1743,7 @@
#define IS_RTC_SECURE_FULL(__STATE__) (((__STATE__) == RTC_SECURE_FULL_YES) || \
((__STATE__) == RTC_SECURE_FULL_NO))
-#define IS_RTC_NONSECURE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_NONSECURE_FEATURE_NONE) == 0u)
+#define IS_RTC_NONSECURE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_NONSECURE_FEATURE_NONE) == 0U)
#define IS_TAMP_SECURE_FULL(__STATE__) (((__STATE__) == TAMP_SECURE_FULL_YES) || \
((__STATE__) == TAMP_SECURE_FULL_NO))
@@ -1724,7 +1754,7 @@
#define IS_RTC_PRIVILEGE_FULL(__STATE__) (((__STATE__) == RTC_PRIVILEGE_FULL_YES) || \
((__STATE__) == RTC_PRIVILEGE_FULL_NO))
-#define IS_RTC_PRIVILEGE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_PRIVILEGE_FEATURE_ALL) == 0u)
+#define IS_RTC_PRIVILEGE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_PRIVILEGE_FEATURE_ALL) == 0U)
#define IS_TAMP_PRIVILEGE_FULL(__STATE__) (((__STATE__) == TAMP_PRIVILEGE_FULL_YES) || \
((__STATE__) == TAMP_PRIVILEGE_FULL_NO))
@@ -1732,7 +1762,7 @@
#define IS_TAMP_MONOTONIC_CNT_PRIVILEGE(__STATE__) (((__STATE__) == TAMP_MONOTONIC_CNT_PRIVILEGE_YES) || \
((__STATE__) == TAMP_MONOTONIC_CNT_PRIVILEGE_NO))
-#define IS_RTC_PRIVILEGE_BKUP_ZONE(__ZONES__) (((__ZONES__) & ~RTC_PRIVILEGE_BKUP_ZONE_ALL) == 0u)
+#define IS_RTC_PRIVILEGE_BKUP_ZONE(__ZONES__) (((__ZONES__) & ~RTC_PRIVILEGE_BKUP_ZONE_ALL) == 0U)
#define IS_RTC_BINARY_MODE(MODE) (((MODE) == RTC_BINARY_NONE) || \
((MODE) == RTC_BINARY_ONLY) || \
@@ -1747,7 +1777,7 @@
((BDCU) == RTC_BINARY_MIX_BCDU_6) || \
((BDCU) == RTC_BINARY_MIX_BCDU_7))
-#define IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(MASK) (((MASK) == 0u) || \
+#define IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(MASK) (((MASK) == 0U) || \
(((MASK) >= RTC_ALARMSUBSECONDBINMASK_SS31_1) &&\
((MASK) <= RTC_ALARMSUBSECONDBINMASK_NONE)))
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart.h
index e30334a..b78526d 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -123,9 +123,11 @@
uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
This parameter can be a value of @ref UART_Overrun_Disable. */
+#if defined(HAL_DMA_MODULE_ENABLED)
uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
+#endif /* HAL_DMA_MODULE_ENABLED */
uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
This parameter can be a value of @ref UART_AutoBaudRate_Enable. */
@@ -182,7 +184,7 @@
/**
* @brief HAL UART Reception type definition
* @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
- * It is expected to admit following values :
+ * This parameter can be a value of @ref UART_Reception_Type_Values :
* HAL_UART_RECEPTION_STANDARD = 0x00U,
* HAL_UART_RECEPTION_TOIDLE = 0x01U,
* HAL_UART_RECEPTION_TORTO = 0x02U,
@@ -191,6 +193,17 @@
typedef uint32_t HAL_UART_RxTypeTypeDef;
/**
+ * @brief HAL UART Rx Event type definition
+ * @note HAL UART Rx Event type value aims to identify which type of Event has occurred
+ * leading to call of the RxEvent callback.
+ * This parameter can be a value of @ref UART_RxEvent_Type_Values :
+ * HAL_UART_RXEVENT_TC = 0x00U,
+ * HAL_UART_RXEVENT_HT = 0x01U,
+ * HAL_UART_RXEVENT_IDLE = 0x02U,
+ */
+typedef uint32_t HAL_UART_RxEventTypeTypeDef;
+
+/**
* @brief UART handle Structure definition
*/
typedef struct __UART_HandleTypeDef
@@ -201,7 +214,7 @@
UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
- uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
+ const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
uint16_t TxXferSize; /*!< UART Tx Transfer size */
@@ -224,14 +237,18 @@
__IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
+ __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */
+
void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
+#if defined(HAL_DMA_MODULE_ENABLED)
DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
+#endif /* HAL_DMA_MODULE_ENABLED */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
@@ -335,7 +352,9 @@
#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */
#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */
#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#if defined(HAL_DMA_MODULE_ENABLED)
#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#endif /* HAL_DMA_MODULE_ENABLED */
#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -475,6 +494,7 @@
* @}
*/
+#if defined(HAL_DMA_MODULE_ENABLED)
/** @defgroup UART_DMA_Tx UART DMA Tx
* @{
*/
@@ -492,6 +512,7 @@
/**
* @}
*/
+#endif /* HAL_DMA_MODULE_ENABLED */
/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
* @{
@@ -532,7 +553,9 @@
#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */
#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */
#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */
+#if defined(HAL_DMA_MODULE_ENABLED)
#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */
+#endif /* HAL_DMA_MODULE_ENABLED */
#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */
#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */
/**
@@ -593,6 +616,7 @@
* @}
*/
+#if defined(HAL_DMA_MODULE_ENABLED)
/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
* @{
*/
@@ -601,6 +625,7 @@
/**
* @}
*/
+#endif /* HAL_DMA_MODULE_ENABLED */
/** @defgroup UART_MSB_First UART Advanced Feature MSB First
* @{
@@ -788,7 +813,7 @@
* @}
*/
-/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
+/** @defgroup UART_Reception_Type_Values UART Reception type values
* @{
*/
#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
@@ -799,6 +824,16 @@
* @}
*/
+/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values
+ * @{
+ */
+#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */
+#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */
+#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -1366,6 +1401,7 @@
#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Ensure that UART DMA TX state is valid.
* @param __DMATX__ UART DMA TX state.
@@ -1382,6 +1418,7 @@
#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \
((__DMARX__) == UART_DMA_RX_ENABLE))
+#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @brief Ensure that UART half-duplex state is valid.
* @param __HDSEL__ UART half-duplex state.
@@ -1414,6 +1451,7 @@
* @param __INIT__ UART advanced features initialization.
* @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
*/
+#if defined(HAL_DMA_MODULE_ENABLED)
#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \
UART_ADVFEATURE_TXINVERT_INIT | \
UART_ADVFEATURE_RXINVERT_INIT | \
@@ -1423,6 +1461,16 @@
UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
UART_ADVFEATURE_MSBFIRST_INIT))
+#else
+#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \
+ UART_ADVFEATURE_TXINVERT_INIT | \
+ UART_ADVFEATURE_RXINVERT_INIT | \
+ UART_ADVFEATURE_DATAINVERT_INIT | \
+ UART_ADVFEATURE_SWAP_INIT | \
+ UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
+ UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
+ UART_ADVFEATURE_MSBFIRST_INIT))
+#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @brief Ensure that UART frame TX inversion setting is valid.
@@ -1473,6 +1521,7 @@
UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Ensure that UART DMA enabling or disabling on error setting is valid.
* @param __DMA__ UART DMA enabling or disabling on error setting.
@@ -1480,6 +1529,7 @@
*/
#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
+#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @brief Ensure that UART frame MSB first setting is valid.
@@ -1583,15 +1633,17 @@
*/
/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+#if defined(HAL_DMA_MODULE_ENABLED)
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+#endif /* HAL_DMA_MODULE_ENABLED */
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
@@ -1641,8 +1693,8 @@
*/
/* Peripheral State and Errors functions **************************************************/
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
+HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart);
+uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart);
/**
* @}
@@ -1665,7 +1717,9 @@
uint32_t Tickstart, uint32_t Timeout);
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+#if defined(HAL_DMA_MODULE_ENABLED)
HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
@@ -1695,3 +1749,4 @@
#endif
#endif /* STM32U5xx_HAL_UART_H */
+
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart_ex.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart_ex.h
index e4b8363..436e171 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart_ex.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_hal_uart_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -268,12 +268,16 @@
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
uint32_t Timeout);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+#if defined(HAL_DMA_MODULE_ENABLED)
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
/* Autonomous Mode Control functions **********************************************/
HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart,
- UART_AutonomousModeConfTypeDef *sConfig);
-HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(UART_HandleTypeDef *huart,
+ const UART_AutonomousModeConfTypeDef *sConfig);
+HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(const UART_HandleTypeDef *huart,
UART_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart);
@@ -297,72 +301,100 @@
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
#if defined(USART6)
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART1; \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART2; \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
- (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART3; \
- } \
- else if((__HANDLE__)->Instance == UART4) \
- { \
- (__CLOCKSOURCE__) = RCC_PERIPHCLK_UART4; \
- } \
- else if((__HANDLE__)->Instance == UART5) \
- { \
- (__CLOCKSOURCE__) = RCC_PERIPHCLK_UART5; \
- } \
- else if((__HANDLE__)->Instance == USART6) \
- { \
- (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART6; \
- } \
- else if((__HANDLE__)->Instance == LPUART1) \
- { \
- (__CLOCKSOURCE__) = RCC_PERIPHCLK_LPUART1; \
- } \
- else \
- { \
- (__CLOCKSOURCE__) = 0U; \
- } \
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \
+ } \
+ else if((__HANDLE__)->Instance == UART4) \
+ { \
+ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \
+ } \
+ else if((__HANDLE__)->Instance == UART5) \
+ { \
+ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \
+ } \
+ else if((__HANDLE__)->Instance == USART6) \
+ { \
+ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART6; \
+ } \
+ else if((__HANDLE__)->Instance == LPUART1) \
+ { \
+ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = 0U; \
+ } \
+ } while(0U)
+#elif defined(USART2)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \
+ } \
+ else if((__HANDLE__)->Instance == UART4) \
+ { \
+ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \
+ } \
+ else if((__HANDLE__)->Instance == UART5) \
+ { \
+ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \
+ } \
+ else if((__HANDLE__)->Instance == LPUART1) \
+ { \
+ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = 0U; \
+ } \
} while(0U)
#else
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART1; \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART2; \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
- (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART3; \
- } \
- else if((__HANDLE__)->Instance == UART4) \
- { \
- (__CLOCKSOURCE__) = RCC_PERIPHCLK_UART4; \
- } \
- else if((__HANDLE__)->Instance == UART5) \
- { \
- (__CLOCKSOURCE__) = RCC_PERIPHCLK_UART5; \
- } \
- else if((__HANDLE__)->Instance == LPUART1) \
- { \
- (__CLOCKSOURCE__) = RCC_PERIPHCLK_LPUART1; \
- } \
- else \
- { \
- (__CLOCKSOURCE__) = 0U; \
- } \
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \
+ } \
+ else if((__HANDLE__)->Instance == UART4) \
+ { \
+ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \
+ } \
+ else if((__HANDLE__)->Instance == UART5) \
+ { \
+ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \
+ } \
+ else if((__HANDLE__)->Instance == LPUART1) \
+ { \
+ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = 0U; \
+ } \
} while(0U)
#endif /* USART6 */
@@ -513,3 +545,4 @@
#endif
#endif /* STM32U5xx_HAL_UART_EX_H */
+
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_ll_dlyb.h b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_ll_dlyb.h
index c8d9247..cc85ca1 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_ll_dlyb.h
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Inc/stm32u5xx_ll_dlyb.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -32,14 +32,10 @@
* @{
*/
-#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_QSPI_MODULE_ENABLED)|| defined(HAL_OSPI_MODULE_ENABLED)
-
-/** @addtogroup DLYB
- * @{
- */
+#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_OSPI_MODULE_ENABLED) || defined(HAL_XSPI_MODULE_ENABLED)
/* Exported types ------------------------------------------------------------*/
-/** @defgroup DLYB_LL_Exported_Types DLYB Exported Types
+/** @defgroup DLYB_LL DLYB
* @{
*/
@@ -56,17 +52,17 @@
This parameter can be a value between 0 and DLYB_MAX_SELECT */
} LL_DLYB_CfgTypeDef;
-/**
- * @}
- */
-
/* Exported constants --------------------------------------------------------*/
/** @defgroup DLYB_Exported_Constants DLYB Exported Constants
* @{
*/
#define DLYB_MAX_UNIT ((uint32_t)0x00000080U) /*!< Max UNIT value (128) */
-#define DLYB_MAX_SELECT ((uint32_t)0x0000000CU) /*!< Max SELECT value (12) */
+#define DLYB_MAX_SELECT ((uint32_t)0x0000000CU) /*!< Max SELECT value (12) */
+
+/**
+ * @}
+ */
/** @defgroup DLYB_LL_Flags DLYB Flags
* @{
@@ -78,10 +74,6 @@
* @}
*/
-/**
- * @}
- */
-
/* Exported functions --------------------------------------------------------*/
/** @defgroup DLYB_LL_Exported_Functions DLYB Exported Functions
@@ -117,8 +109,7 @@
* @}
*/
-
-/** @addtogroup DLYB_Control_Functions DLYB Control functions
+/** @defgroup DLYB_Control_Functions DLYB Control functions
* @{
*/
@@ -138,7 +129,7 @@
* @}
*/
-#endif /* HAL_SD_MODULE_ENABLED || HAL_QSPI_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED */
+#endif /* HAL_SD_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED || HAL_XSPI_MODULE_ENABLED */
/**
* @}
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal.c
index ccc93a2..62a57cc 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal.c
@@ -8,7 +8,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -17,7 +17,6 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
-
@verbatim
==============================================================================
##### How to use this driver #####
@@ -54,10 +53,10 @@
* @{
*/
/**
- * @brief STM32U5xx HAL Driver version number 1.0.0
+ * @brief STM32U5xx HAL Driver version number 1.3.0
*/
#define __STM32U5xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
-#define __STM32U5xx_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
+#define __STM32U5xx_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
#define __STM32U5xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32U5xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32U5xx_HAL_VERSION ((__STM32U5xx_HAL_VERSION_MAIN << 24U)\
@@ -348,7 +347,8 @@
/**
* @brief Return tick frequency.
- * @retval tick period in Hz
+ * @retval Tick frequency.
+ * Value of @ref HAL_TickFreqTypeDef.
*/
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{
@@ -442,6 +442,33 @@
}
/**
+ * @brief Return the first word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw0(void)
+{
+ return (READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+ * @brief Return the second word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw1(void)
+{
+ return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+ * @brief Return the third word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw2(void)
+{
+ return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+/**
* @}
*/
@@ -622,6 +649,98 @@
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
}
+#if defined(SYSCFG_CFGR1_SRAMCACHED)
+/**
+ * @brief Enable the Cacheability of internal SRAMx by DCACHE2
+ *
+ * @retval None
+ */
+void HAL_SYSCFG_EnableSRAMCached(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED);
+}
+
+/**
+ * @brief Disable the Cacheability of internal SRAMx by DCACHE2
+ *
+ * @retval None
+ */
+void HAL_SYSCFG_DisableSRAMCached(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED);
+}
+#endif /* SYSCFG_CFGR1_SRAMCACHED */
+
+/**
+ * @brief Enable the Compensation Cell of GPIO supplied by VDD
+ * @rmtoll CCCSR EN1 HAL_SYSCFG_EnableVddCompensationCell
+ * @note The vdd compensation cell can be used only when the device supply
+ * voltage ranges from 1.71 to 3.6 V
+ * @retval None
+ */
+void HAL_SYSCFG_EnableVddCompensationCell(void)
+{
+ SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1);
+}
+
+/**
+ * @brief Enable the Compensation Cell of GPIO supplied by VDDIO2
+ * @rmtoll CCCSR EN2 HAL_SYSCFG_EnableVddIO2CompensationCell
+ * @note The Vdd I/O compensation cell can be used only when the device supply
+ * voltage ranges from 1.08 to 3.6 V
+ * @retval None
+ */
+void HAL_SYSCFG_EnableVddIO2CompensationCell(void)
+{
+ SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2);
+}
+
+#if defined(SYSCFG_CCCSR_EN3)
+/**
+ * @brief Enable the Compensation Cell of HSPI IO supplied by VDD
+ * @rmtoll CCCSR EN3 HAL_SYSCFG_EnableVddHSPICompensationCell
+ * @retval None
+ */
+void HAL_SYSCFG_EnableVddHSPICompensationCell(void)
+{
+ SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3);
+}
+#endif /* SYSCFG_CCCSR_EN3 */
+/**
+ * @brief Disable the Compensation Cell of GPIO supplied by VDD
+ * @rmtoll CCCSR EN1 HAL_SYSCFG_DisableVddCompensationCell
+ * @note The Vdd compensation cell can be used only when the device supply
+ * voltage ranges from 1.71 to 3.6 V
+ * @retval None
+ */
+void HAL_SYSCFG_DisableVddCompensationCell(void)
+{
+ CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1);
+}
+
+/**
+ * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2
+ * @rmtoll CCCSR EN2 HAL_SYSCFG_DisableVddIO2CompensationCell
+ * @note The Vdd I/O compensation cell can be used only when the device supply
+ * voltage ranges from 1.08 to 3.6 V
+ * @retval None
+ */
+void HAL_SYSCFG_DisableVddIO2CompensationCell(void)
+{
+ CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2);
+}
+
+#if defined(SYSCFG_CCCSR_EN3)
+/**
+ * @brief Disable the Compensation Cell of HSPI IO supplied by VDD
+ * @rmtoll CCCSR EN3 HAL_SYSCFG_DisableVddHSPICompensationCell
+ * @retval None
+ */
+void HAL_SYSCFG_DisableVddHSPICompensationCell(void)
+{
+ CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3);
+}
+#endif /* SYSCFG_CCCSR_EN3 */
/**
* @}
*/
@@ -781,6 +900,99 @@
#endif /* __ARM_FEATURE_CMSE */
+#ifdef SYSCFG_OTGHSPHYCR_EN
+/**
+ * @brief Enable the OTG PHY .
+ * @param OTGPHYConfig Defines the OTG PHY configuration.
+ This parameter can be one of @ref SYSCFG_OTG_PHY_Enable
+ * @retval None
+ */
+
+void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig)
+{
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_OTGPHY_CONFIG(OTGPHYConfig));
+
+ MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN, OTGPHYConfig);
+}
+
+/**
+ * @brief Set the OTG PHY Power Down config.
+ * @param PowerDownConfig Defines the OTG PHY Power down configuration.
+ This parameter can be one of @ref SYSCFG_OTG_PHY_PowerDown
+ * @retval None
+ */
+void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig)
+{
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(PowerDownConfig));
+
+ MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL, PowerDownConfig);
+}
+
+/**
+ * @brief Set the OTG PHY reference clock selection.
+ * @param RefClkSelection Defines the OTG PHY reference clock selection.
+ This parameter can be one of the @ref SYSCFG_OTG_PHY_RefenceClockSelection
+ * @retval None
+ */
+void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClkSelection)
+{
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(RefClkSelection));
+
+ MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL, RefClkSelection);
+}
+
+/**
+ * @brief Set the OTG PHY Disconnect Threshold.
+ * @param DisconnectThreshold Defines the voltage level for the threshold used to detect a disconnect event.
+ This parameter can be one of the @ref SYSCFG_OTG_PHYTUNER_DisconnectThreshold
+ * @retval None
+ */
+
+void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold)
+{
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_OTGPHY_DISCONNECT(DisconnectThreshold));
+
+ MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE, DisconnectThreshold);
+}
+
+/**
+ * @brief Adjust the voltage level for the threshold used to detect valid high speed data.
+ * @param SquelchThreshold Defines the voltage level.
+ This parameter can be onez of the @ref SYSCFG_OTG_PHYTUNER_SquelchThreshold
+
+ * @retval None
+ */
+
+void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold)
+{
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_OTGPHY_SQUELCH(SquelchThreshold));
+
+ MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_SQRXTUNE, SquelchThreshold);
+}
+
+/**
+ * @brief Set the OTG PHY Current config.
+ * @param PreemphasisCurrent Defines the current configuration.
+ This parameter can be one of the @ref SYSCFG_OTG_PHYTUNER_PreemphasisCurrent
+
+ * @retval None
+ */
+
+void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent)
+{
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_OTGPHY_PREEMPHASIS(PreemphasisCurrent));
+
+ MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE, PreemphasisCurrent);
+}
+
+#endif /* SYSCFG_OTGHSPHYCR_EN */
+
/**
* @}
*/
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cortex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cortex.c
index 003041a..2ece941 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cortex.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cortex.c
@@ -11,7 +11,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -471,6 +471,8 @@
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
+ __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
+
/* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
@@ -478,9 +480,9 @@
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Follow ARM recommendation with */
- /* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */
- __DMB(); /* Force memory writes before continuing */
- __ISB(); /* Flush and refill pipeline with updated permissions */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
@@ -497,6 +499,8 @@
*/
void HAL_MPU_Enable_NS(uint32_t MPU_Control)
{
+ __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
+
/* Enable the MPU */
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
@@ -504,9 +508,9 @@
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Follow ARM recommendation with */
- /* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */
- __DMB(); /* Force memory writes before continuing */
- __ISB(); /* Flush and refill pipeline with updated permissions */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
#endif /* __ARM_FEATURE_CMSE */
@@ -518,8 +522,16 @@
{
__DMB(); /* Force any outstanding transfers to complete before disabling MPU */
+ /* Disable fault exceptions */
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
/* Disable the MPU */
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+
+ /* Follow ARM recommendation with */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
@@ -531,8 +543,16 @@
{
__DMB(); /* Force any outstanding transfers to complete before disabling MPU */
+ /* Disable fault exceptions */
+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
/* Disable the MPU */
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+
+ /* Follow ARM recommendation with */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
#endif /* __ARM_FEATURE_CMSE */
@@ -628,8 +648,8 @@
}
else
{
- MPUx->RBAR = 0U;
MPUx->RLAR = 0U;
+ MPUx->RBAR = 0U;
}
}
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp.c
index ab73a11..c5f0f88 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp.c
@@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -38,7 +38,7 @@
(##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
(+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
(+++) Configure and enable two DMA channels one for managing data transfer from
- memory to peripheral (input channel) and another stream for managing data
+ memory to peripheral (input channel) and another channel for managing data
transfer from peripheral to memory (output channel)
(+++) Associate the initialized DMA handle to the CRYP DMA handle
using __HAL_LINKDMA()
@@ -82,7 +82,7 @@
the CRYP peripheral is configured and processes the buffer in input.
At second call, no need to Initialize the CRYP, user have to get current configuration via
HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set
- new parametres, finally user can start encryption/decryption.
+ new parameters, finally user can start encryption/decryption.
(#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
@@ -191,7 +191,7 @@
(##) To perform message payload encryption or decryption AES is configured in CTR mode.
(##) For authentication two phases are performed :
- Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message
- only cleartext payload (not the ciphertext payload) is used and no outpout.
+ only cleartext payload (not the ciphertext payload) is used and no output.
(##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
HAL_CRYPEx_AESCCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond to the Tag.
user should consider only part of this 4 words, if Tag length is less than 128 bits
@@ -306,10 +306,11 @@
/** @addtogroup CRYP_Private_Defines
* @{
*/
-#define CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/
-#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey
+#define CRYP_GENERAL_TIMEOUT 82U
+#define CRYP_TIMEOUT_KEYPREPARATION 82U /*!< The latency of key preparation operation is 82 clock cycles.*/
+#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /*!< The latency of GCM/CCM init phase to prepare hash subkey
is 299 clock cycles.*/
-#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
+#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /*!< The latency of GCM/CCM header phase is 290 clock cycles.*/
#define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */
#define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */
@@ -421,6 +422,9 @@
(+) Data Type : 32,16, 8 or 1bit
(+) AlgoMode : ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
(+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
+ (+) For interleave mode, API HAL_CRYP_SaveContext and HAL_CRYP_RestoreContext to be used to save then Restore CRYP
+ configuration and parameters. CRYP_IVCONFIG_ONCE should be selected for KeyIVConfigSkip parameter.
+ Only polling mode is supported, interleave mode should be used with HAL_CRYP_Encrypt and HAL_CRYP_Decrypt API.
@endverbatim
* @{
@@ -436,6 +440,9 @@
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
{
uint32_t cr_value;
+#if defined(SAES)
+ uint32_t tickstart;
+#endif /* SAES */
/* Check the CRYP handle allocation */
if (hcryp == NULL)
@@ -487,6 +494,34 @@
}
else
{
+ /* SAES is initializing, fetching random number from the RNG */
+ tickstart = HAL_GetTick();
+ while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > CRYP_GENERAL_TIMEOUT)
+ {
+ __HAL_CRYP_DISABLE(hcryp);
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ /* SAES is initializing, no random number fetching error flagged */
+ tickstart = HAL_GetTick();
+ while (HAL_IS_BIT_SET(hcryp->Instance->ISR, CRYP_FLAG_RNGEIF))
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > CRYP_GENERAL_TIMEOUT)
+ {
+ __HAL_CRYP_DISABLE(hcryp);
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_RNG;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
cr_value = (uint32_t)(hcryp->Init.KeyMode | hcryp->Init.DataType | hcryp->Init.KeySize | \
hcryp->Init.Algorithm | hcryp->Init.KeySelect | hcryp->Init.KeyProtection);
/* Set the key size, data type, algorithm, Key selection and key protection */
@@ -601,8 +636,7 @@
if (hcryp->Instance == AES)
{
- /* Set the key size(This bit field is do not care in the DES or TDES modes)
- data type, AlgoMode and operating mode */
+ /* Set the key size, data type, AlgoMode and operating mode */
MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | AES_CR_KMOD,
hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm | hcryp->Init.KeyMode);
}
@@ -614,14 +648,18 @@
/* In case of HSW, HW or SW key selection, we should specify Key mode selection (SAES_CR_KMOD) */
if ((hcryp->Init.KeySelect != CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_WRAPPED))
{
+ /* Disable AES to change key mode */
+ __HAL_CRYP_DISABLE(hcryp);
/* Set key mode selection (Normal, Wrapped or Shared key )*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED);
}
/* Set the key size data type, AlgoMode and operating mode */
MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | \
- AES_CR_KEYSEL | AES_CR_KEYPROT, hcryp->Init.DataType | hcryp->Init.KeySize | \
- hcryp->Init.Algorithm | hcryp->Init.KeySelect | hcryp->Init.KeyProtection);
+ AES_CR_KEYSEL | AES_CR_KEYPROT | AES_CR_KMOD, hcryp->Init.DataType | hcryp->Init.KeySize | \
+ hcryp->Init.Algorithm | hcryp->Init.KeySelect | hcryp->Init.KeyProtection | hcryp->Init.KeyMode);
+ /* Set to 0 the number of non-valid bytes using NPBLB field of CR register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
}
/* Clear error flags */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF);
@@ -756,7 +794,6 @@
return HAL_ERROR;
}
- __HAL_LOCK(hcryp);
if (hcryp->State == HAL_CRYP_STATE_READY)
{
@@ -818,8 +855,6 @@
status = HAL_ERROR;
}
- __HAL_UNLOCK(hcryp);
-
return status;
}
@@ -840,35 +875,34 @@
{
HAL_StatusTypeDef status = HAL_OK;
- __HAL_LOCK(hcryp);
if (hcryp->State == HAL_CRYP_STATE_READY)
{
switch (CallbackID)
{
case HAL_CRYP_INPUT_COMPLETE_CB_ID :
- hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
+ hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /*!< Legacy weak InCpltCallback */
break;
case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
- hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
+ hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /*!< Legacy weak OutCpltCallback */
break;
case HAL_CRYP_ERROR_CB_ID :
- hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
+ hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /*!< Legacy weak ErrorCallback */
break;
case HAL_CRYP_MSPINIT_CB_ID :
- hcryp->MspInitCallback = HAL_CRYP_MspInit;
+ hcryp->MspInitCallback = HAL_CRYP_MspInit; /*!< Legacy weak MspInit */
break;
case HAL_CRYP_MSPDEINIT_CB_ID :
- hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
+ hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /*!< Legacy weak MspDeInit */
break;
default :
/* Update the error code */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;/*!< Legacy weak ERROR INVALID CALLBACK */
/* Return error status */
status = HAL_ERROR;
break;
@@ -902,8 +936,6 @@
status = HAL_ERROR;
}
- __HAL_UNLOCK(hcryp);
-
return status;
}
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
@@ -1088,6 +1120,120 @@
#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
/**
+ * @brief CRYP peripheral parameters storage when processing Interleaved mode .
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pcont pointer to a CRYP_ContextTypeDef structure where CRYP parameters will be stored.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_SaveContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont)
+{
+ /* Check the CRYP handle allocation */
+ if ((hcryp == NULL) || (pcont == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Save CRYP handle parameters */
+ pcont->DataType = (uint32_t)(hcryp->Init.DataType);
+ pcont->KeySize = (uint32_t)(hcryp->Init.KeySize);
+ pcont->pKey = hcryp->Init.pKey;
+ pcont->pInitVect = hcryp->Init.pInitVect;
+ pcont->Algorithm = (uint32_t)(hcryp->Init.Algorithm);
+ pcont->DataWidthUnit = (uint32_t)(hcryp->Init.DataWidthUnit);
+ pcont->KeyIVConfigSkip = (uint32_t)(hcryp->Init.KeyIVConfigSkip);
+ pcont->KeyMode = (uint32_t)(hcryp->Init.KeyMode);
+ pcont->Phase = (uint32_t)(hcryp->Phase);
+ pcont->KeyIVConfig = (uint32_t)(hcryp->KeyIVConfig);
+
+ /* Save CRYP CR register content */
+ pcont->CR_Reg = READ_REG(hcryp->Instance->CR);
+
+ /* Save IER register content */
+ pcont->IER_Reg = READ_BIT(hcryp->Instance->IER, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+
+ if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \
+ (hcryp->Init.Algorithm == CRYP_AES_CTR))
+ {
+ /* Save Initialisation Vector registers */
+ pcont->IVR0_Reg = READ_REG(hcryp->Instance->IVR0);
+ pcont->IVR1_Reg = READ_REG(hcryp->Instance->IVR1);
+ pcont->IVR2_Reg = READ_REG(hcryp->Instance->IVR2);
+ pcont->IVR3_Reg = READ_REG(hcryp->Instance->IVR3);
+ }
+
+ /* To load Key for next piece of message */
+ hcryp->KeyIVConfig = 0;
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+
+}
+
+/**
+ * @brief Restore CRYP parameters needed for Interleaved mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pcont pointer to a CRYP_ContextTypeDef structure that contains CRYP parameters stored.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont)
+{
+ /* Check the CRYP handle allocation */
+ if ((hcryp == NULL) || (pcont == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Restore CRYP handle parameters */
+ hcryp->Init.DataType = pcont->DataType;
+ hcryp->Init.KeySize = pcont->KeySize;
+ hcryp->Init.pKey = pcont->pKey;
+ hcryp->Init.pInitVect = pcont->pInitVect;
+ hcryp->Init.Algorithm = pcont->Algorithm;
+ hcryp->Init.DataWidthUnit = pcont->DataWidthUnit;
+ hcryp->Init.KeyIVConfigSkip = pcont->KeyIVConfigSkip;
+ hcryp->Init.KeyMode = pcont->KeyMode;
+ hcryp->Phase = pcont->Phase;
+ hcryp->KeyIVConfig = pcont->KeyIVConfig;
+
+ /* Restore CRYP CR register content */
+ WRITE_REG(hcryp->Instance->CR, (uint32_t)(pcont->CR_Reg));
+
+ /* Restore CRYP IER register content */
+ WRITE_REG(hcryp->Instance->IER, (uint32_t)(pcont->IER_Reg));
+
+ if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \
+ (hcryp->Init.Algorithm == CRYP_AES_CTR))
+ {
+ /* Restore Initialisation Vector registers */
+ WRITE_REG(hcryp->Instance->IVR0, (uint32_t)(pcont->IVR0_Reg));
+ WRITE_REG(hcryp->Instance->IVR1, (uint32_t)(pcont->IVR1_Reg));
+ WRITE_REG(hcryp->Instance->IVR2, (uint32_t)(pcont->IVR2_Reg));
+ WRITE_REG(hcryp->Instance->IVR3, (uint32_t)(pcont->IVR3_Reg));
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+}
+
+/**
* @}
*/
@@ -1706,7 +1852,7 @@
/* Peripheral Key configuration to not do, IV to configure for CBC */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYNOCONFIG)
{
- if (hcryp->Init.Algorithm == CRYP_AES_CBC)
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
{
/* Set the Initialization Vector */
CRYP_SetIV(hcryp);
@@ -1921,7 +2067,7 @@
* the configuration information for the CRYP peripheral
* @retval CRYP error code
*/
-uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
+uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp)
{
return hcryp->ErrorCode;
}
@@ -1932,7 +2078,7 @@
* the configuration information for CRYP module.
* @retval HAL state
*/
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp)
{
return hcryp->State;
}
@@ -1948,8 +2094,8 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_InCpltCallback could be implemented in the user file
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYP_InCpltCallback can be implemented in the user file
*/
}
@@ -1964,8 +2110,8 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_OutCpltCallback could be implemented in the user file
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYP_OutCpltCallback can be implemented in the user file
*/
}
@@ -1980,8 +2126,8 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_ErrorCallback could be implemented in the user file
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYP_ErrorCallback can be implemented in the user file
*/
}
/**
@@ -2010,7 +2156,7 @@
uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
uint32_t tickstart;
- if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE))
{
if (hcryp->KeyIVConfig == 1U)
{
@@ -2027,61 +2173,84 @@
}
}
- if ((dokeyivconfig == 1U) && (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG))
+ if (dokeyivconfig == 1U)
{
- if (hcryp->Instance == AES)
+ if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || \
+ (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ALWAYS))
{
- /* Set the Key */
- if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
- {
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- }
- else /* After sharing the key, AES should set KMOD[1:0] to 00.*/
- {
- hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
- }
- }
- else
- {
- /* We should re-write Key, in the case where we change key after first operation */
- if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+ if (hcryp->Instance == AES)
{
/* Set the Key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- }
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID))
- {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
+ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
- if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ else /* After sharing the key, AES should set KMOD[1:0] to 00.*/
+ {
+ hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
+ }
+ }
+ else
+ {
+ /* We should re-write Key, in the case where we change key after first operation */
+ if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+ {
+ /* Set the Key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ /* Get tick */
+ tickstart = HAL_GetTick();
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID))
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
}
}
}
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector */
+ CRYP_SetIV(hcryp);
+ }
}
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ /* key & IV configuration for CBC and CTR in interleave mode */
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE)
{
- /* Set the Initialization Vector */
- CRYP_SetIV(hcryp);
+ /* Set the Key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+ CRYP_SetIV(hcryp);
+ }
}
} /* If (dokeyivconfig == 1U) */
-
+ else
+ {
+ /* interleave mode Key configuration */
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE)
+ {
+ /* Set the Key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ }
/* Peripheral Key configuration to not do, IV to configure for CBC */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYNOCONFIG)
{
- if (hcryp->Init.Algorithm == CRYP_AES_CBC)
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
{
/* Set the Initialization Vector*/
CRYP_SetIV(hcryp);
@@ -2190,7 +2359,7 @@
/* Peripheral Key configuration to not do, IV to configure for CBC */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYNOCONFIG)
{
- if (hcryp->Init.Algorithm == CRYP_AES_CBC)
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
{
/* Set the Initialization Vector*/
CRYP_SetIV(hcryp);
@@ -2202,10 +2371,6 @@
if (hcryp->Size != 0U)
{
-
- /* Enable computation complete flag and Key, Read and Write error interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
-
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
@@ -2218,6 +2383,9 @@
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
+
+ /* Enable computation complete flag and Key, Read and Write error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
}
else
{
@@ -2241,7 +2409,7 @@
uint16_t outcount; /* Temporary CrypOutCount Value */
uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
- if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE))
{
if (hcryp->KeyIVConfig == 1U)
{
@@ -2270,7 +2438,8 @@
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
/* Set the Key */
- if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+ if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || \
+ (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ALWAYS))
{
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
@@ -2282,6 +2451,17 @@
}
}
+ /* interleave mode Key configuration */
+ else if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE)
+ {
+ /* Set the Key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
@@ -2314,32 +2494,35 @@
}
else /*SAES*/
{
- /* key preparation for decryption, operating mode 2*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
-
- /* we should re-write Key, in the case where we change key after first operation*/
- if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/
{
- if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+ /* key preparation for decryption, operating mode 2*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
+
+ /* we should re-write Key, in the case where we change key after first operation*/
+ if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
{
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
}
+
+ /* Enable SAES */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* End of Key preparation for ECB/CBC */
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
}
-
- /* Enable SAES */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Wait for CCF flag to be raised */
- if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- return HAL_ERROR;
- }
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
-
- /* End of Key preparation for ECB/CBC */
- /* Return to decryption operating mode(Mode 3)*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
}
/* Set IV */
if (hcryp->Init.Algorithm != CRYP_AES_ECB)
@@ -2349,7 +2532,47 @@
}
} /* if (dokeyivconfig == 1U) */
+ else /* if (dokeyivconfig == 0U) */
+ {
+ /* interleave mode Key configuration */
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE)
+ {
+ if (hcryp->Instance == AES)
+ {
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/
+ {
+ /* key preparation for decryption, operating mode 2*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_NORMAL);
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
+ /* Set the Key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+ else /*Algorithm CTR */
+ {
+ /* Set the Key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ }
+ }
+ }
+
+ }
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
@@ -2365,7 +2588,6 @@
incount = hcryp->CrypInCount;
outcount = hcryp->CrypOutCount;
}
-
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
@@ -2445,7 +2667,7 @@
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF));
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
@@ -2471,44 +2693,48 @@
}
else /*SAES*/
{
- /* key preparation for decryption, operating mode 2*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
-
- /* we should re-write Key, in the case where we change key after first operation*/
- if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR)
{
- if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+ /* key preparation for decryption, operating mode 2*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
+
+ /* we should re-write Key, in the case where we change key after first operation*/
+ if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
{
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
}
+ /* Enable SAES */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF));
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* End of Key preparation for ECB/CBC */
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
}
- /* Enable SAES */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Wait for CCF flag to be raised */
- count = CRYP_TIMEOUT_KEYPREPARATION;
- do
- {
- count--;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
-
- /* End of Key preparation for ECB/CBC */
- /* Return to decryption operating mode(Mode 3)*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
}
/* Set IV */
if (hcryp->Init.Algorithm != CRYP_AES_ECB)
@@ -2522,9 +2748,6 @@
hcryp->Phase = CRYP_PHASE_PROCESS;
if (hcryp->Size != 0U)
{
- /* Enable computation complete flag and error interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
-
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
@@ -2537,6 +2760,9 @@
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
+
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
}
else
{
@@ -2619,7 +2845,7 @@
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF));
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
@@ -2645,44 +2871,48 @@
}
else /*SAES*/
{
- /* key preparation for decryption, operating mode 2*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
-
- /* we should re-write Key, in the case where we change key after first operation*/
- if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR)
{
- if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+ /* key preparation for decryption, operating mode 2*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
+
+ /* we should re-write Key, in the case where we change key after first operation*/
+ if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
{
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
}
+ /* Enable SAES */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF));
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* End of Key preparation for ECB/CBC */
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
}
- /* Enable SAES */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Wait for CCF flag to be raised */
- count = CRYP_TIMEOUT_KEYPREPARATION;
- do
- {
- count--;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
-
- /* End of Key preparation for ECB/CBC */
- /* Return to decryption operating mode(Mode 3)*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
}
if (hcryp->Init.Algorithm != CRYP_AES_ECB)
@@ -2723,10 +2953,11 @@
uint32_t loopcounter;
uint32_t headersize_in_bytes;
uint32_t tmp;
- uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
- 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
- 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
- }; /* 8-bit data type */
+ const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+ }; /* 8-bit data type */
+ uint32_t algo;
/* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
in the DMACR register */
@@ -2796,14 +3027,30 @@
/* Initiate payload DMA IN and processed data DMA OUT transfers */
(void)CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp);
}
- /* Call input data transfer complete callback */
+ else
+ {
+
+ /* ECB, CBC or CTR end of input data feeding or
+ end of GCM/CCM payload data feeding through DMA */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ /* Don't call input data transfer complete callback only if
+ it remains some input data to write to the peripheral.
+ This case can only occur for GCM and CCM with a payload length
+ not a multiple of 16 bytes */
+ if (!(((algo == CRYP_AES_GCM_GMAC) || (algo == CRYP_AES_CCM)) && \
+ (((hcryp->Size) % 16U) != 0U)))
+ {
+ /* Call input data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered Input complete callback*/
- hcryp->InCpltCallback(hcryp);
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
#else
- /*Call legacy weak Input complete callback*/
- HAL_CRYP_InCpltCallback(hcryp);
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ } /* if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED) */
}
/**
@@ -2869,7 +3116,16 @@
hcryp->Instance->DINR = 0x0U;
count++;
}
+ /* Call input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ /*Wait on CCF flag*/
CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
/*Read the output block from the output FIFO */
@@ -3388,7 +3644,6 @@
/****************************** Init phase **********************************/
CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
-
/* Set the Key */
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
@@ -3398,7 +3653,6 @@
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
-
/* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
CRYP_SetIV(hcryp);
@@ -3549,10 +3803,10 @@
uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
uint32_t headersize_in_bytes;
uint32_t tmp;
- uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
- 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
- 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
- }; /* 8-bit data type */
+ const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+ }; /* 8-bit data type */
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
@@ -3605,7 +3859,6 @@
/******************************* Init phase *********************************/
CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
-
/* Set the Key */
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
@@ -3615,7 +3868,6 @@
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
-
/* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
CRYP_SetIV(hcryp);
@@ -3638,7 +3890,7 @@
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF));
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
@@ -3685,7 +3937,7 @@
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- if (hcryp->CrypInCount == (hcryp->Size / 4U))
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
@@ -3735,6 +3987,14 @@
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
/* Enter header data */
@@ -3829,7 +4089,7 @@
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- if (hcryp->CrypInCount == (hcryp->Size / 4U))
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
@@ -3879,6 +4139,14 @@
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
@@ -3929,7 +4197,6 @@
/*************************** Init phase ************************************/
CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
-
/* Set the Key */
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
@@ -3939,7 +4206,6 @@
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
-
/* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
CRYP_SetIV(hcryp);
@@ -3962,7 +4228,7 @@
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF));
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
@@ -4039,7 +4305,6 @@
/********************** Init phase ******************************************/
CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
-
/* Set the Key */
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
@@ -4049,7 +4314,6 @@
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
-
/* Set the initialization vector (IV) with B0 */
hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
@@ -4196,6 +4460,12 @@
uint32_t npblb;
uint32_t mode;
uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+ }; /* 8-bit data type */
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
@@ -4237,7 +4507,6 @@
/********************** Init phase ******************************************/
CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
-
/* Set the Key */
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
@@ -4247,7 +4516,6 @@
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
-
/* Set the initialization vector (IV) with B0 */
hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
@@ -4273,7 +4541,7 @@
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF));
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
@@ -4289,7 +4557,16 @@
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
- if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
+
+ if (headersize_in_bytes == 0U) /* Header phase is skipped */
{
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
@@ -4371,26 +4648,65 @@
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
- else if ((hcryp->Init.HeaderSize) < 4U) /*HeaderSize < 4 */
+ /* Enter header data */
+ /* Check first whether header length is small enough to enter the full header in one shot */
+ else if (headersize_in_bytes <= 16U)
{
/* Last block optionally pad the data with zeros*/
- for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
+ for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
}
- while (loopcounter < 4U)
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
{
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
- loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
}
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ hcryp->CrypHeaderCount++;
+ loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
else
{
- /* Write the input block in the IN FIFO */
+ /* Write the first input header block in the Input FIFO,
+ the following header data will be fed after interrupt occurrence */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
@@ -4399,7 +4715,7 @@
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
- }
+ }/* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is skipped*/
} /* end of if (dokeyivconfig == 1U) */
else /* Key and IV have already been configured,
@@ -4474,6 +4790,14 @@
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
@@ -4525,7 +4849,6 @@
/********************** Init phase ******************************************/
CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
-
/* Set the Key */
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
@@ -4535,7 +4858,6 @@
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
-
/* Set the initialization vector (IV) with B0 */
hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
@@ -4561,7 +4883,7 @@
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF));
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
@@ -4796,6 +5118,14 @@
hcryp->Instance->DINR = 0U;
index++;
}
+ /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/* Wait for CCF flag to be raised */
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
do
@@ -4814,7 +5144,7 @@
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF));
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
@@ -4837,6 +5167,14 @@
/* Process unlocked */
__HAL_UNLOCK(hcryp);
+ /* Call Output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
return HAL_OK;
@@ -4854,10 +5192,10 @@
uint32_t loopcounter;
uint32_t size_in_bytes;
uint32_t tmp;
- uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
- 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
- 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
- }; /* 8-bit data type */
+ const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+ }; /* 8-bit data type */
/***************************** Header phase for GCM/GMAC or CCM *********************************/
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
@@ -4988,10 +5326,10 @@
uint32_t loopcounter;
uint32_t headersize_in_bytes;
uint32_t tmp;
- uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
- 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
- 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
- }; /* 8-bit data type */
+ const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+ }; /* 8-bit data type */
/***************************** Header phase for GCM/GMAC or CCM *********************************/
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
@@ -5110,10 +5448,10 @@
uint32_t mode;
uint32_t headersize_in_bytes;
uint32_t tmp;
- uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
- 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
- 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
- }; /* 8-bit data type */
+ const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+ }; /* 8-bit data type */
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
{
@@ -5208,6 +5546,14 @@
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
+ /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U))
@@ -5298,7 +5644,7 @@
/* Get timeout */
tickstart = HAL_GetTick();
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
@@ -5351,7 +5697,7 @@
HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
- } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF));
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
@@ -5658,7 +6004,7 @@
hcryp->CrypInCount++;
if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
- /* Call output transfer complete callback */
+ /* Call input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp_ex.c
index cc04974..d57627f 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp_ex.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_cryp_ex.c
@@ -9,7 +9,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -67,7 +67,6 @@
/* Private function prototypes -----------------------------------------------*/
static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
-static void CRYPEx_SetKey(const CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
/* Exported functions---------------------------------------------------------*/
/** @addtogroup CRYPEx_Exported_Functions
* @{
@@ -101,7 +100,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *pAuthTag, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag,
+ uint32_t Timeout)
{
/* Assume first Init.HeaderSize is in words */
uint64_t headerlength = (uint64_t)hcryp->Init.HeaderSize * 32U; /* Header length in bits */
@@ -132,9 +132,6 @@
/* Select final phase */
MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
- /* Set the encrypt operating mode */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
-
/* Write into the AES_DINR register the number of bits in header (64 bits)
followed by the number of bits in the payload */
hcryp->Instance->DINR = 0U;
@@ -144,7 +141,7 @@
/* Wait for CCF flag to be raised */
tickstart = HAL_GetTick();
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
@@ -215,7 +212,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *pAuthTag, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag,
+ uint32_t Timeout)
{
uint32_t tagaddr = (uint32_t)pAuthTag;
uint32_t i;
@@ -240,12 +238,9 @@
/* Select final phase */
MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
- /* Set encrypt operating mode */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
-
/* Wait for CCF flag to be raised */
tickstart = HAL_GetTick();
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
@@ -323,7 +318,6 @@
- Derived hardware unique key (DHUK)
- XOR of DHUK and BHK
- Boot hardware key (BHK)
- - Key registers AES_KEYx
@endverbatim
* @{
@@ -333,8 +327,8 @@
* @brief Wrap (encrypt) application keys.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pInput Pointer to the Key buffer to encrypt
- * @param pOutput Pointer to the Key buffer encrypted
+ * @param pInput Pointer to the Key buffer to encrypt in case of ECB or CBC
+ * @param pOutput Pointer to the Key buffer encrypted in case of ECB or CBC
* @param Timeout Specify Timeout value
* @retval HAL status
*/
@@ -360,6 +354,9 @@
/* Set the operating mode*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED);
+ /* Encryption operating mode(Mode 0)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
status = CRYPEx_KeyEncrypt(hcryp, Timeout);
}
else
@@ -376,7 +373,7 @@
* @brief Unwrap (Decrypt) application keys.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pInput Pointer to the Key buffer to decrypt
+ * @param pInput Pointer to the Key buffer to decrypt.
* @param Timeout Specify Timeout value
* @retval HAL status
*/
@@ -418,14 +415,14 @@
* @}
*/
-/** @defgroup CRYPEx_Exported_Functions_Group3 Encrypt/Decrypt Shared key functions
- * @brief Encrypt/Decrypt Shared key functions.
+/** @defgroup CRYPEx_Exported_Functions_Group3 Encrypt and Decrypt Shared key functions
+ * @brief Encrypt and Decrypt Shared key functions.
*
@verbatim
==============================================================================
- ##### Encrypt/Decrypt Shared key functions #####
+ ##### Encrypt and Decrypt Shared key functions #####
==============================================================================
- [..] This section provides API allowing to Encrypt/Decrypt Shared key
+ [..] This section provides API allowing to Encrypt and Decrypt Shared key
@endverbatim
* @{
@@ -464,6 +461,9 @@
/* Set the operating mode */
MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID);
+ /* Encryption operating mode(Mode 0)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
status = CRYPEx_KeyEncrypt(hcryp, Timeout);
}
else
@@ -546,18 +546,12 @@
/* key preparation for decryption, operating mode 2*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
- /* It is strongly recommended to select hardware secret keys */
- if (hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL)
- {
- /* Set the Key */
- CRYPEx_SetKey(hcryp, hcryp->Init.KeySize);
- }
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
/* Wait for CCF flag to be raised */
tickstart = HAL_GetTick();
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
@@ -614,7 +608,7 @@
}
/* Wait for CCF flag to be raised */
tickstart = HAL_GetTick();
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
@@ -659,8 +653,6 @@
uint32_t tickstart;
uint32_t temp; /* Temporary CrypOutBuff */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
-
if (hcryp->Init.Algorithm != CRYP_AES_ECB)
{
/* Set the Initialization Vector */
@@ -669,31 +661,6 @@
hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
}
- /* It is strongly recommended to select hardware secret keys */
- if (hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL)
- {
- /* Set the Key */
- CRYPEx_SetKey(hcryp, hcryp->Init.KeySize);
- }
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait for Valid KEY flag to set */
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_KEYVALID))
- {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- {
- if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
- {
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- }
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
@@ -718,7 +685,7 @@
}
/* Wait for CCF flag to be raised */
tickstart = HAL_GetTick();
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
@@ -760,41 +727,6 @@
}
/**
- * @brief Write Key in Key registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param KeySize Size of Key
- * @note If pKey is NULL, the Key registers are not written.
- * @retval None
- */
-static void CRYPEx_SetKey(const CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
-{
- if (hcryp->Init.pKey != NULL)
- {
- switch (KeySize)
- {
- case CRYP_KEYSIZE_256B:
- hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
- hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1U);
- hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2U);
- hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3U);
- hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4U);
- hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5U);
- hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6U);
- hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7U);
- break;
- case CRYP_KEYSIZE_128B:
- hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
- hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1U);
- hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2U);
- hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3U);
- break;
- default:
- break;
- }
- }
-}
-/**
* @}
*/
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma.c
index 39b4429..daf3d32 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma.c
@@ -12,7 +12,7 @@
**********************************************************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -25,6 +25,7 @@
======================================================================================================================
############### How to use this driver ###############
======================================================================================================================
+
[..]
DMA transfer modes are divided to 2 major categories :
(+) Normal transfers (legacy)
@@ -59,28 +60,28 @@
(+) Request : Specifies the DMA channel request
Request parameters :
- (++) can be a value of @ref DMA_Request_Selection
+ (++) can be a value of DMA_Request_Selection
(+) BlkHWRequest : Specifies the Block hardware request mode for DMA channel
- (++) can be a value of @ref DMA_Block_Request
+ (++) can be a value of DMA_Block_Request
(+) Direction : Specifies the transfer direction for DMA channel
- (++) can be a value of @ref DMA_Transfer_Direction
+ (++) can be a value of DMA_Transfer_Direction
(+) SrcInc : Specifies the source increment mode for the DMA channel
- (++) can be a value of @ref DMA_Source_Increment_Mode
+ (++) can be a value of DMA_Source_Increment_Mode
(+) DestInc : Specifies the destination increment mode for the DMA channel
- (++) can be a value of @ref DMA_Destination_Increment_Mode
+ (++) can be a value of DMA_Destination_Increment_Mode
(+) SrcDataWidth : Specifies the source data width for the DMA channel
- (++) can be a value of @ref DMA_Source_Data_Width
+ (++) can be a value of DMA_Source_Data_Width
(+) DestDataWidth : Specifies the destination data width for the DMA channel
- (++) can be a value of @ref DMA_Destination_Data_Width
+ (++) can be a value of DMA_Destination_Data_Width
(+) Priority : Specifies the priority for the DMA channel
- (++) can be a value of @ref DMA_Priority_Level
+ (++) can be a value of DMA_Priority_Level
(+) SrcBurstLength : Specifies the source burst length (number of beats) for the DMA channel
(++) can be a value of between 1 and 64
@@ -89,13 +90,13 @@
(++) can be a value of between 1 and 64
(+) TransferAllocatedPort : Specifies the source and destination allocated ports
- (++) can be a value of @ref DMA_Transfer_Allocated_Port
+ (++) can be a value of DMA_Transfer_Allocated_Port
(+) TransferEventMode : Specifies the transfer event mode for the DMA channel
- (++) can be a value of @ref DMA_Transfer_Event_Mode
+ (++) can be a value of DMA_Transfer_Event_Mode
(+) Mode : Specifies the transfer mode for the DMA channel
- (++) can be a value of @ref DMA_Transfer_Mode
+ (++) can be a value of DMA_Transfer_Mode
*** Polling mode IO operation ***
@@ -156,8 +157,9 @@
(++) Privilege : at channel level.
(+) Use HAL_DMA_GetConfigChannelAttributes() function to get the DMA channel attributes.
(+) Use HAL_DMA_LockChannelAttributes() function to lock the DMA channel security and privilege attributes
- configuration. This API is called once after each system boot.
- When this API is called, HAL_DMA_ConfigChannelAttributes() API cannot be used anymore.
+ configuration. This API can be called once after each system boot.
+ If called again, HAL_DMA_ConfigChannelAttributes() API has no effect.
+ Unlock is done either by a system boot or a by an RCC reset.
(+) Use HAL_DMA_GetLockChannelAttributes() function to get the attributes lock status.
@@ -318,7 +320,9 @@
*/
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma)
{
+
DMA_TypeDef *p_dma_instance;
+
uint32_t tickstart = HAL_GetTick();
/* Check the DMA peripheral handle parameter */
@@ -883,11 +887,19 @@
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
{
- DMA_TypeDef *p_dma_instance = GET_DMA_INSTANCE(hdma);
+ const DMA_TypeDef *p_dma_instance = GET_DMA_INSTANCE(hdma);
uint32_t global_it_flag = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
+ uint32_t global_active_flag_ns = IS_DMA_GLOBAL_ACTIVE_FLAG_NS(p_dma_instance, global_it_flag);
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ uint32_t global_active_flag_s = IS_DMA_GLOBAL_ACTIVE_FLAG_S(p_dma_instance, global_it_flag);
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* Global Interrupt Flag management *********************************************************************************/
- if (IS_DMA_GLOBAL_ACTIVE_FLAG(p_dma_instance, global_it_flag) == 0U)
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ if ((global_active_flag_s == 0U) && (global_active_flag_ns == 0U))
+#else
+ if (global_active_flag_ns == 0U)
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
{
return; /* the global interrupt flag for the current channel is down , nothing to do */
}
@@ -984,6 +996,9 @@
/* Reset the channel internal state and reset the FIFO */
hdma->Instance->CCR |= DMA_CCR_RESET;
+ /* Wait one clock cycle to ensure that the reset of DMA channel is done before checking the enable bit */
+ __NOP();
+
if ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
{
/* Update the DMA channel state */
@@ -1000,6 +1015,9 @@
{
/* Update the linked-list queue state */
hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
+
+ /* Clear remaining data size to ensure loading linked-list from memory next start */
+ hdma->Instance->CBR1 = 0U;
}
/* Process Unlocked */
@@ -1082,6 +1100,9 @@
/* Reset the channel internal state and reset the FIFO */
hdma->Instance->CCR |= DMA_CCR_RESET;
+ /* Wait one clock cycle to ensure that the reset of DMA channel is done before checking the enable bit */
+ __NOP();
+
if ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
{
/* Update the DMA channel state */
@@ -1114,6 +1135,8 @@
/**
* @brief Register callback according to specified ID.
+ * @note The HAL_DMA_RegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET
+ * to register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enumeration.
@@ -1132,9 +1155,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hdma);
-
/* Check DMA channel state */
if (hdma->State == HAL_DMA_STATE_READY)
{
@@ -1178,6 +1198,8 @@
default:
{
+ /* Update error status */
+ status = HAL_ERROR;
break;
}
}
@@ -1188,14 +1210,13 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
return status;
}
/**
* @brief Unregister callback according to specified ID.
+ * @note The HAL_DMA_UnRegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET
+ * to un-register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enum.
@@ -1212,9 +1233,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hdma);
-
/* Check DMA channel state */
if (hdma->State == HAL_DMA_STATE_READY)
{
@@ -1281,9 +1299,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
return status;
}
/**
@@ -1462,7 +1477,7 @@
HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma,
uint32_t *const pChannelAttributes)
{
- DMA_TypeDef *p_dma_instance;
+ const DMA_TypeDef *p_dma_instance;
uint32_t attributes;
uint32_t channel_idx;
@@ -1498,6 +1513,7 @@
return HAL_OK;
}
+
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Lock the DMA channel security and privilege attribute(s).
@@ -1543,7 +1559,7 @@
uint32_t channel_idx;
/* Check the DMA peripheral handle and lock state parameters */
- if (hdma == NULL)
+ if ((hdma == NULL) || (pLockState == NULL))
{
return HAL_ERROR;
}
@@ -1619,7 +1635,6 @@
/* Write DMA Channel Control Register (CCR) */
MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg);
-
/* Prepare DMA Channel Transfer Register (CTR1) value ***************************************************************/
tmpreg = hdma->Init.DestInc | hdma->Init.DestDataWidth | hdma->Init.SrcInc | hdma->Init.SrcDataWidth;
@@ -1663,19 +1678,16 @@
/* Write DMA Channel Block Register 1 (CBR1) ************************************************************************/
WRITE_REG(hdma->Instance->CBR1, 0U);
-
/* If 2D Addressing is supported by current channel */
if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U)
{
/* Write DMA Channel Transfer Register 3 (CTR3) *******************************************************************/
WRITE_REG(hdma->Instance->CTR3, 0U);
-
/* Write DMA Channel Block Register 2 (CBR2) **********************************************************************/
WRITE_REG(hdma->Instance->CBR2, 0U);
}
-
/* Write DMA Channel linked-list address register (CLLR) ************************************************************/
WRITE_REG(hdma->Instance->CLLR, 0U);
}
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma_ex.c
index fe9a019..ded17ef 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma_ex.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma_ex.c
@@ -15,7 +15,7 @@
**********************************************************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -163,6 +163,8 @@
in memory.
Placing DMA linked-list in SRAM must be done in accordance to product specification to ensure that the
link access port can access to the specified SRAM.
+ (++) The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte
+ addressable space.
(+) Use HAL_DMAEx_List_GetNodeConfig() to get the specified configuration parameter on building node.
This API can be used when need to change few parameter to build new node.
@@ -377,8 +379,8 @@
In order to avoid some CPU data processing in several cases, the DMA channel provides some features related to
FIFO capabilities titled data handling.
(++) Padding pattern
- Padding selected patter (zero padding or sign extension) when the source data width is smaller than
- the destination data width at single level.
+ Padding selected pattern (zero padding or sign extension) when the source data width is smaller
+ than the destination data width at single level.
Zero padding (Source : 0xABAB ------> Destination : 0xABAB0000)
Sign bit extension (Source : 0x0ABA ------> Destination : 0x00000ABA)
(Source : 0xFABA ------> Destination : 0xFFFFFABA)
@@ -394,16 +396,17 @@
UnPack (Source : 0xABCD ------> Destination : 0xAB, 0xCD)
(++) Exchange :
Exchange data at byte and half-word on the destination and at byte level on the source.
- Source byte exchange (Source : 0xAB12CD34 ------> Destination : 0xABCD1234)
- Destination byte exchange (Source : 0xAB12CD34 ------> Destination : 0x12AB34CD)
- Destination half-word exchange (Source : 0xAB12CD34 ------> Destination : 0xCD34AB12)
+ Considering source and destination are both word type. Exchange operation can be as follows.
+ In examples below, one exchange setting is enabled at a time.
+ Source byte exchange only (Source : 0xAB12CD34 ------> Destination : 0xABCD1234)
+ Destination byte exchange only (Source : 0xAB12CD34 ------> Destination : 0x12AB34CD)
+ Destination half-word exchange only (Source : 0xAB12CD34 ------> Destination : 0xCD34AB12)
(+) Use HAL_DMAEx_ConfigDataHandling() to configure data handling features. Previous elementary explained
can be combined according to application needs.
(++) This API is complementary of normal transfers.
(++) This API must not be called for linked-list transfers as data handling information are configured at
node level.
- (++) This API must be called only for DMA channel that supports data handling feature.
*** User sequence ***
[..]
@@ -535,18 +538,12 @@
DMA_NodeTypeDef *const pNode);
static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
DMA_NodeTypeDef const *const pNode);
-#if (__GNUC__ == 11) || (__GNUC__ == 12)
-static __attribute__((noinline)) uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1,
-#else
static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1,
-#endif
DMA_NodeTypeDef const *const pNode2,
- DMA_NodeTypeDef const *const pNode3,
- DMA_NodeTypeDef const *const pNode4);
+ DMA_NodeTypeDef const *const pNode3);
static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1,
DMA_NodeTypeDef const *const pNode2,
- DMA_NodeTypeDef const *const pNode3,
- DMA_NodeTypeDef const *const pNode4);
+ DMA_NodeTypeDef const *const pNode3);
static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode,
uint32_t *const cllr_mask,
uint32_t *const cllr_offset);
@@ -676,8 +673,11 @@
*/
HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma)
{
+
/* Get DMA instance */
DMA_TypeDef *p_dma_instance;
+
+
/* Get tick number */
uint32_t tickstart = HAL_GetTick();
@@ -690,9 +690,11 @@
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
/* Get DMA instance */
p_dma_instance = GET_DMA_INSTANCE(hdma);
+
/* Disable the selected DMA Channel */
__HAL_DMA_DISABLE(hdma);
@@ -729,9 +731,11 @@
hdma->Instance->CBR2 = 0U;
}
+
/* Clear privilege attribute */
CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU)));
+
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Clear secure attribute */
CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU)));
@@ -748,9 +752,10 @@
hdma->XferAbortCallback = NULL;
hdma->XferSuspendCallback = NULL;
- /* Update the queue state and error code */
- if(hdma->LinkedListQueue != NULL)
+ /* Check the linked-list queue */
+ if (hdma->LinkedListQueue != NULL)
{
+ /* Update the queue state and error code */
hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
@@ -786,7 +791,7 @@
*
@verbatim
======================================================================================================================
- ############### Linked-List I/O Operation Functions ###############
+ ############### Linked-List IO Operation Functions ###############
======================================================================================================================
[..]
This section provides functions allowing to :
@@ -1036,6 +1041,8 @@
* specified DMA linked-list Node.
* @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
* configurations.
+ * @note The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte
+ * addressable space.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
@@ -1060,6 +1067,7 @@
assert_param(IS_DMA_DIRECTION(pNodeConfig->Init.Direction));
assert_param(IS_DMA_TCEM_EVENT_MODE(pNodeConfig->Init.TransferEventMode));
assert_param(IS_DMA_BLOCK_HW_REQUEST(pNodeConfig->Init.BlkHWRequest));
+ assert_param(IS_DMA_MODE(pNodeConfig->Init.Mode));
/* Check DMA channel parameters */
if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA)
@@ -1160,7 +1168,7 @@
}
/* Check nodes base addresses */
- if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode, NULL) != 0U)
+ if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
@@ -1169,7 +1177,7 @@
}
/* Check nodes types compatibility */
- if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode, NULL) != 0U)
+ if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
@@ -1288,7 +1296,7 @@
}
/* Check nodes base addresses */
- if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL, NULL) != 0U)
+ if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
@@ -1297,7 +1305,7 @@
}
/* Check nodes types compatibility */
- if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL, NULL) != 0U)
+ if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
@@ -1368,7 +1376,7 @@
}
/* Check nodes base addresses */
- if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL, NULL) != 0U)
+ if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
@@ -1377,7 +1385,7 @@
}
/* Check nodes types compatibility */
- if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL, NULL) != 0U)
+ if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
@@ -1798,7 +1806,7 @@
}
/* Check nodes base addresses */
- if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode, NULL) != 0U)
+ if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
@@ -1807,7 +1815,7 @@
}
/* Check nodes types compatibility */
- if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode, NULL) != 0U)
+ if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
@@ -1960,7 +1968,7 @@
}
/* Check nodes base addresses */
- if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL, NULL) != 0U)
+ if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
@@ -1969,7 +1977,7 @@
}
/* Check nodes types compatibility */
- if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL, NULL) != 0U)
+ if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
@@ -2240,7 +2248,7 @@
}
/* Check nodes base addresses */
- if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head, NULL) != 0U)
+ if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
@@ -2252,7 +2260,7 @@
}
/* Check nodes types compatibility */
- if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head, NULL) != 0U)
+ if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
@@ -2438,7 +2446,7 @@
}
/* Check nodes base addresses */
- if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U)
+ if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
@@ -2450,7 +2458,7 @@
}
/* Check nodes types compatibility */
- if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U)
+ if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
@@ -2575,7 +2583,7 @@
}
/* Check nodes base addresses */
- if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U)
+ if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
@@ -2587,7 +2595,7 @@
}
/* Check nodes types compatibility */
- if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U)
+ if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
@@ -3500,7 +3508,7 @@
hdma->Instance->CCR |= DMA_CCR_SUSP;
/* Check if the DMA channel is suspended */
- while ((hdma->Instance->CSR & DMA_CSR_SUSPF) != 0U)
+ while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U)
{
/* Check for the timeout */
if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
@@ -3516,10 +3524,10 @@
return HAL_ERROR;
}
-
- /* Update the DMA channel state */
- hdma->State = HAL_DMA_STATE_SUSPEND;
}
+
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_SUSPEND;
}
return HAL_OK;
@@ -3655,7 +3663,13 @@
uint32_t tmpreg;
/* Prepare DMA Channel Control Register (CCR) value */
- tmpreg = hdma->InitLinkedList.Priority | hdma->InitLinkedList.LinkStepMode | hdma->InitLinkedList.LinkAllocatedPort;
+ tmpreg = hdma->InitLinkedList.Priority | hdma->InitLinkedList.LinkStepMode;
+
+ /* Check DMA channel instance */
+ if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)
+ {
+ tmpreg |= hdma->InitLinkedList.LinkAllocatedPort;
+ }
/* Write DMA Channel Control Register (CCR) */
MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg);
@@ -3834,7 +3848,6 @@
pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pNodeConfig->DstAddress;
/*********************************************************************************** CDAR register value is updated */
-
/* Check if the selected channel is 2D addressing */
if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
{
@@ -4075,19 +4088,13 @@
* @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations.
* @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations.
* @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations.
- * @param pNode4 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 4 registers configurations.
* @retval Return 0 when nodes addresses are compatible, 1 otherwise.
*/
-#if (__GNUC__ == 11) || (__GNUC__ == 12)
-static __attribute__((noinline)) uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1,
-#else
static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1,
-#endif
DMA_NodeTypeDef const *const pNode2,
- DMA_NodeTypeDef const *const pNode3,
- DMA_NodeTypeDef const *const pNode4)
+ DMA_NodeTypeDef const *const pNode3)
{
- uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3 | (uint32_t)pNode4) & DMA_CLBAR_LBA);
+ uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3) & DMA_CLBAR_LBA);
uint32_t ref = 0U;
/* Check node 1 address */
@@ -4105,11 +4112,6 @@
{
ref = (uint32_t)pNode3;
}
- /* Check node 4 address */
- else if ((uint32_t)pNode4 != 0U)
- {
- ref = (uint32_t)pNode4;
- }
else
{
/* Prevent MISRA-C2012-Rule-15.7 */
@@ -4129,13 +4131,11 @@
* @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations.
* @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations.
* @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations.
- * @param pNode4 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 4 registers configurations.
* @retval Return 0 when nodes types are compatible, otherwise nodes types are not compatible.
*/
static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1,
DMA_NodeTypeDef const *const pNode2,
- DMA_NodeTypeDef const *const pNode3,
- DMA_NodeTypeDef const *const pNode4)
+ DMA_NodeTypeDef const *const pNode3)
{
uint32_t ref = 0U;
@@ -4154,26 +4154,11 @@
{
ref = pNode3->NodeInfo & NODE_TYPE_MASK;
}
- /* Check node 4 parameter */
- else if (pNode4 != NULL)
- {
- ref = pNode4->NodeInfo & NODE_TYPE_MASK;
- }
else
{
/* Prevent MISRA-C2012-Rule-15.7 */
}
- /* Check node 1 parameter */
- if (pNode1 != NULL)
- {
- /* Check node type compatibility */
- if (ref != (pNode1->NodeInfo & NODE_TYPE_MASK))
- {
- return 1U;
- }
- }
-
/* Check node 2 parameter */
if (pNode2 != NULL)
{
@@ -4194,16 +4179,6 @@
}
}
- /* Check node 4 parameter */
- if (pNode4 != NULL)
- {
- /* Check node type compatibility */
- if (ref != (pNode4->NodeInfo & NODE_TYPE_MASK))
- {
- return 4U;
- }
- }
-
return 0U;
}
@@ -4398,7 +4373,7 @@
DMA_NodeTypeDef *const pDestNode)
{
/* Repeat for all register nodes */
- for (uint32_t reg_idx = 0U; reg_idx < NODE_CLLR_IDX_POS; reg_idx++)
+ for (uint32_t reg_idx = 0U; reg_idx < NODE_MAXIMUM_SIZE; reg_idx++)
{
pDestNode->LinkRegisters[reg_idx] = pSrcNode->LinkRegisters[reg_idx];
}
@@ -4423,12 +4398,12 @@
uint32_t cllr_idx = RegisterNumber - 1U;
DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr;
DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr;
- uint32_t update_link[NODE_CLLR_IDX_POS] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA,
+ uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA,
DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL
};
/* Update ULL position according to register number */
- update_link[cllr_idx] = update_link[NODE_CLLR_IDX_POS - 1U];
+ update_link[cllr_idx] = update_link[NODE_MAXIMUM_SIZE - 1U];
/* Repeat for all node registers */
while (contextnode_reg_counter != RegisterNumber)
@@ -4488,12 +4463,12 @@
uint32_t cllr_mask;
DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr;
DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr;
- uint32_t update_link[NODE_CLLR_IDX_POS] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA,
+ uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA,
DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL
};
/* Update ULL position according to register number */
- update_link[RegisterNumber - 1U] = update_link[NODE_CLLR_IDX_POS - 1U];
+ update_link[RegisterNumber - 1U] = update_link[NODE_MAXIMUM_SIZE - 1U];
/* Get context node CLLR information */
cllr_idx = (context_node->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS;
@@ -4563,7 +4538,7 @@
uint32_t FirstUnusedField)
{
/* Repeat for all unused fields */
- for (uint32_t reg_idx = FirstUnusedField; reg_idx < NODE_CLLR_IDX_POS; reg_idx++)
+ for (uint32_t reg_idx = FirstUnusedField; reg_idx < NODE_MAXIMUM_SIZE; reg_idx++)
{
pNode->LinkRegisters[reg_idx] = 0U;
}
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash.c
index b52314f..20fda2d 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash.c
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash_ex.c
index a18e039..d6d910c 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash_ex.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_flash_ex.c
@@ -10,7 +10,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -1082,7 +1082,7 @@
* @param UserConfig The selected User Option Bytes values.
* This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
* @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
- * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST,
+ * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST,
* @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP,
* @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW,
* @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK,
@@ -1141,14 +1141,14 @@
optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
}
- if ((UserType & OB_USER_SRAM134_RST) != 0U)
+ if ((UserType & OB_USER_SRAM_RST) != 0U)
{
- /* SRAM134_RST option byte should be modified */
- assert_param(IS_OB_USER_SRAM134_RST(UserConfig & FLASH_OPTR_SRAM134_RST));
+ /* SRAM_RST option byte should be modified */
+ assert_param(IS_OB_USER_SRAM_RST(UserConfig & FLASH_OPTR_SRAM_RST));
- /* Set value and mask for SRAM134_RST option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM134_RST);
- optr_reg_mask |= FLASH_OPTR_SRAM134_RST;
+ /* Set value and mask for SRAM_RST option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM_RST);
+ optr_reg_mask |= FLASH_OPTR_SRAM_RST;
}
if ((UserType & OB_USER_IWDG_SW) != 0U)
@@ -1220,7 +1220,7 @@
optr_reg_val |= (UserConfig & FLASH_OPTR_BKPRAM_ECC);
optr_reg_mask |= FLASH_OPTR_BKPRAM_ECC;
}
-
+#if defined(SRAM3_BASE)
if ((UserType & OB_USER_SRAM3_ECC) != 0U)
{
/* SRAM3_ECC option byte should be modified */
@@ -1230,7 +1230,7 @@
optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM3_ECC);
optr_reg_mask |= FLASH_OPTR_SRAM3_ECC;
}
-
+#endif /* SRAM3_BASE */
if ((UserType & OB_USER_SRAM2_ECC) != 0U)
{
/* SRAM2_ECC option byte should be modified */
@@ -1551,7 +1551,7 @@
* @retval The FLASH User Option Bytes values.
* The return value can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
* @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
- * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST,
+ * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST,
* @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP,
* @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW,
* @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK,
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gpio.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gpio.c
index c3bb932..dcfcfb7 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gpio.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gpio.c
@@ -10,7 +10,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -84,7 +84,10 @@
(#) To set/reset the level of a pin configured in output mode use
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
- (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+ (#) To set the level of several pins and reset level of several other pins in
+ same cycle, use HAL_GPIO_WriteMultipleStatePin().
+
+ (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
(#) During and just after reset, the alternate functions are not
active and the GPIO pins are configured in input floating mode (except JTAG
@@ -239,7 +242,7 @@
/* Configure Alternate function mapped with the current IO */
tmp = p_gpio->AFR[(pin_position) >> 3U];
tmp &= ~(0x0FUL << (((pin_position) & 0x07U) * 4U));
- tmp |= ((GPIO_AF11_LPGPIO & 0x0FUL) << (((pin_position) & 0x07U) * 4U));
+ tmp |= ((GPIO_AF11_LPGPIO1 & 0x0FUL) << (((pin_position) & 0x07U) * 4U));
p_gpio->AFR[(pin_position) >> 3U] = tmp;
/* Configure IO Direction mode (Alternate) */
@@ -320,23 +323,6 @@
tmp |= (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U)));
EXTI->EXTICR[position >> 2U] = tmp;
- /* Clear EXTI line configuration */
- tmp = EXTI->IMR1;
- tmp &= ~((uint32_t)iocurrent);
- if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
- {
- tmp |= iocurrent;
- }
- EXTI->IMR1 = tmp;
-
- tmp = EXTI->EMR1;
- tmp &= ~((uint32_t)iocurrent);
- if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
- {
- tmp |= iocurrent;
- }
- EXTI->EMR1 = tmp;
-
/* Clear Rising Falling edge configuration */
tmp = EXTI->RTSR1;
tmp &= ~((uint32_t)iocurrent);
@@ -353,6 +339,23 @@
tmp |= iocurrent;
}
EXTI->FTSR1 = tmp;
+
+ /* Clear EXTI line configuration */
+ tmp = EXTI->EMR1;
+ tmp &= ~((uint32_t)iocurrent);
+ if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ {
+ tmp |= iocurrent;
+ }
+ EXTI->EMR1 = tmp;
+
+ tmp = EXTI->IMR1;
+ tmp &= ~((uint32_t)iocurrent);
+ if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ {
+ tmp |= iocurrent;
+ }
+ EXTI->IMR1 = tmp;
}
}
position++;
@@ -469,7 +472,7 @@
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
GPIO_PinState bitstatus;
@@ -520,6 +523,34 @@
}
/**
+ * @brief Set and clear several pins of a dedicated port in same cycle.
+ * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
+ * accesses.
+ * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
+ * peripheral for STM32U5 family
+ * @param PinReset specifies the port bits to be reset
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero.
+ * @param PinSet specifies the port bits to be set
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero.
+ * @note Both PinReset and PinSet combinations shall not get any common bit, else
+ * assert would be triggered.
+ * @note At least one of the two parameters used to set or reset shall be different from zero.
+ * @retval None
+ */
+void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet)
+{
+ uint32_t tmp;
+
+ /* Check the parameters */
+ /* Make sure at least one parameter is different from zero and that there is no common pin */
+ assert_param(IS_GPIO_PIN((uint32_t)PinReset | (uint32_t)PinSet));
+ assert_param(IS_GPIO_COMMON_PIN(PinReset, PinSet));
+
+ tmp = (((uint32_t)PinReset << 16) | PinSet);
+ GPIOx->BSRR = tmp;
+}
+
+/**
* @brief Toggle the specified GPIO pin.
* @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
* peripheral for STM32U5 family
@@ -876,12 +907,13 @@
* @param pPinAttributes: pointer to return the pin attributes.
* @retval HAL Status.
*/
-HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes)
+HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin,
+ uint32_t *pPinAttributes)
{
uint32_t iocurrent;
uint32_t pin_position;
uint32_t position = 0U;
- GPIO_TypeDef *p_gpio;
+ const GPIO_TypeDef *p_gpio;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gtzc.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gtzc.c
index 090f947..53e805a 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gtzc.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_gtzc.c
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -124,26 +124,68 @@
#define TZSC_MPCWM3_MEM_SIZE 0x10000000U /* 256MB max size */
#define TZSC_MPCWM4_MEM_SIZE 0x00000800U /* 2KB max size */
#define TZSC_MPCWM5_MEM_SIZE 0x10000000U /* 256MB max size */
+#if defined (HSPI1)
+#define TZSC_MPCWM6_MEM_SIZE 0x10000000U /* 256MB max size */
+#endif /* HSPI1 */
/* Definitions for GTZC TZSC & TZIC ALL register values */
/* TZSC1 / TZIC1 instances */
-#define TZSC1_SECCFGR1_ALL (0x001FFFFFUL)
+#if defined(STM32U599xx) || defined(STM32U595xx) || defined(STM32U5A9xx) || defined (STM32U5A5xx)
+#define TZSC1_SECCFGR1_ALL (0x00EFFFFFUL)
+#define TZSC1_SECCFGR2_ALL (0x000007FFUL)
+#define TZSC1_SECCFGR3_ALL (0x0FFFFFFFUL)
+
+#define TZSC1_PRIVCFGR1_ALL (0x00EFFFFFUL)
+#define TZSC1_PRIVCFGR2_ALL (0x000007FFUL)
+#define TZSC1_PRIVCFGR3_ALL (0x0FFFFFFFUL)
+
+#define TZIC1_IER1_ALL (0x00EFFFFFUL)
+#define TZIC1_IER2_ALL (0x000007FFUL)
+#define TZIC1_IER3_ALL (0x0FFFFFFFUL)
+#define TZIC1_IER4_ALL (0xFF1FC01FUL)
+
+#define TZIC1_FCR1_ALL (0x00EFFFFFUL)
+#define TZIC1_FCR2_ALL (0x000007FFUL)
+#define TZIC1_FCR3_ALL (0x0FFFFFFFUL)
+#define TZIC1_FCR4_ALL (0xFF1FC01FUL)
+
+#elif defined(STM32U5F9xx) || defined(STM32U5G9xx)
+#define TZSC1_SECCFGR1_ALL (0x00EFFFFFUL)
+#define TZSC1_SECCFGR2_ALL (0x00000FFFUL)
+#define TZSC1_SECCFGR3_ALL (0x1FFFFFFFUL)
+
+#define TZSC1_PRIVCFGR1_ALL (0x00EFFFFFUL)
+#define TZSC1_PRIVCFGR2_ALL (0x00000FFFUL)
+#define TZSC1_PRIVCFGR3_ALL (0x1FFFFFFFUL)
+
+#define TZIC1_IER1_ALL (0x00EFFFFFUL)
+#define TZIC1_IER2_ALL (0x00000FFFUL)
+#define TZIC1_IER3_ALL (0x1FFFFFFFUL)
+#define TZIC1_IER4_ALL (0xFFDFC01FUL)
+
+#define TZIC1_FCR1_ALL (0x00EFFFFFUL)
+#define TZIC1_FCR2_ALL (0x00000FFFUL)
+#define TZIC1_FCR3_ALL (0x1FFFFFFFUL)
+#define TZIC1_FCR4_ALL (0xFFDFC01FUL)
+#else
+#define TZSC1_SECCFGR1_ALL (0x000FFFFFUL)
#define TZSC1_SECCFGR2_ALL (0x000001FFUL)
#define TZSC1_SECCFGR3_ALL (0x007FFFFFUL)
-#define TZSC1_PRIVCFGR1_ALL (0x001FFFFFUL)
+#define TZSC1_PRIVCFGR1_ALL (0x000FFFFFUL)
#define TZSC1_PRIVCFGR2_ALL (0x000001FFUL)
#define TZSC1_PRIVCFGR3_ALL (0x007FFFFFUL)
-#define TZIC1_IER1_ALL (0x001FFFFFUL)
+#define TZIC1_IER1_ALL (0x000FFFFFUL)
#define TZIC1_IER2_ALL (0x000001FFUL)
#define TZIC1_IER3_ALL (0x007FFFFFUL)
#define TZIC1_IER4_ALL (0x3F0FC01FUL)
-#define TZIC1_FCR1_ALL (0x001FFFFFUL)
+#define TZIC1_FCR1_ALL (0x000FFFFFUL)
#define TZIC1_FCR2_ALL (0x000001FFUL)
#define TZIC1_FCR3_ALL (0x007FFFFFUL)
#define TZIC1_FCR4_ALL (0x3F0FC01FUL)
+#endif /* STM32U599xx || STM32U595xx || STM32U5A9xx || STM32U5A5xx */
/* TZSC2 / TZIC2 instances */
#define TZSC2_SECCFGR1_ALL (0x00001BFFUL)
@@ -156,6 +198,7 @@
#define TZIC2_FCR1_ALL (0x00001BFFUL)
#define TZIC2_FCR2_ALL (0x0300C07FUL)
+#define REG_SIZE 32U
/**
* @}
*/
@@ -166,18 +209,18 @@
* @{
*/
-#define IS_ADDRESS_IN(mem, address)\
- ( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
- && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \
- || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
+#define IS_ADDRESS_IN(mem, address) \
+ ( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
+ && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \
+ || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
&& ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) )
-#define IS_ADDRESS_IN_S(mem, address)\
- ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
+#define IS_ADDRESS_IN_S(mem, address) \
+ ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
&& ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
-#define IS_ADDRESS_IN_NS(mem, address)\
- ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
+#define IS_ADDRESS_IN_NS(mem, address) \
+ ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
&& ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
#define GTZC_BASE_ADDRESS(mem)\
@@ -527,9 +570,8 @@
* The structure description is available in @ref GTZC_Exported_Types.
* @retval HAL status.
*/
-HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(
- uint32_t MemBaseAddress,
- MPCWM_ConfigTypeDef *pMPCWM_Desc)
+HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,
+ const MPCWM_ConfigTypeDef *pMPCWM_Desc)
{
uint32_t register_address;
uint32_t reg_value;
@@ -539,11 +581,15 @@
GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1;
/* check entry parameters */
- if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2)
- || (((MemBaseAddress == FMC_BANK3) || (MemBaseAddress == BKPSRAM_BASE))
- && (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2))
- || ((pMPCWM_Desc->Offset % granularity) != 0U)
- || ((pMPCWM_Desc->Length % granularity) != 0U))
+ if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2) ||
+#if defined (FMC_BANK3)
+ (((MemBaseAddress == BKPSRAM_BASE) || (MemBaseAddress == FMC_BANK3)) &&
+#else
+ ((MemBaseAddress == BKPSRAM_BASE) &&
+#endif /* FMC_BANK3 */
+ (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2)) ||
+ ((pMPCWM_Desc->Offset % granularity) != 0U) ||
+ ((pMPCWM_Desc->Length % granularity) != 0U))
{
return HAL_ERROR;
}
@@ -565,6 +611,7 @@
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR);
}
break;
+#if defined (FMC_BANK1)
case FMC_BANK1:
size = TZSC_MPCWM1_MEM_SIZE;
if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
@@ -579,6 +626,8 @@
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR);
}
break;
+#endif /* FMC_BANK1 */
+#if defined (FMC_BANK3)
case FMC_BANK3:
/* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
* (Parameter already checked)
@@ -586,6 +635,7 @@
size = TZSC_MPCWM3_MEM_SIZE;
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR);
break;
+#endif /* FMC_BANK3 */
case BKPSRAM_BASE:
/* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
* (Parameter already checked)
@@ -593,6 +643,7 @@
size = TZSC_MPCWM4_MEM_SIZE;
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR);
break;
+#if defined (OCTOSPI2_BASE)
case OCTOSPI2_BASE:
size = TZSC_MPCWM5_MEM_SIZE;
if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
@@ -607,15 +658,30 @@
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR);
}
break;
+#endif /* OCTOSPI2_BASE */
+#if defined (HSPI1)
+ case HSPI1_BASE:
+ size = TZSC_MPCWM6_MEM_SIZE;
+ if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
+ {
+ register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6AR);
+ }
+ else
+ {
+ /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
+ * (Parameter already checked)
+ */
+ register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6BR);
+ }
+ break;
+#endif /* HSPI1 */
default:
return HAL_ERROR;
break;
}
- if ((pMPCWM_Desc->Offset > size)
- || ((pMPCWM_Desc->Offset
- + pMPCWM_Desc->Length)
- > size))
+ if ((pMPCWM_Desc->Offset > size) ||
+ ((pMPCWM_Desc->Offset + pMPCWM_Desc->Length) > size))
{
return HAL_ERROR;
}
@@ -643,43 +709,60 @@
* @brief Get a TZSC-MPCWM area configuration.
* @param MemBaseAddress WM identifier.
* @param pMPCWM_Desc pointer to a TZSC-MPCWM descriptor.
+ * When the WaterMark memory supports two sub-regions A and B. pMPCWM_Desc argument must point to an array of
+ * two MPCWM_ConfigTypeDef structures.
* The structure description is available in @ref GTZC_Exported_Types.
* @retval HAL status.
*/
-HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(
- uint32_t MemBaseAddress,
- MPCWM_ConfigTypeDef *pMPCWM_Desc)
+HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,
+ MPCWM_ConfigTypeDef *pMPCWM_Desc)
{
- uint32_t register_address;
+ uint32_t register_address_regionA;
+ uint32_t register_address_regionB = 0U;
uint32_t reg_value;
uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \
GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1;
- /* firstly take care of the first area, present on all MPCWM sub-blocks */
+ /* Loading the subregion A & B addresses into their specific variables */
switch (MemBaseAddress)
{
case OCTOSPI1_BASE:
- register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1AR);
+ register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM1AR);
+ register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR);
break;
+#if defined (FMC_BANK1)
case FMC_BANK1:
- register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR);
+ register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR);
+ register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR);
break;
+#endif /* FMC_BANK1 */
+#if defined (FMC_BANK3)
case FMC_BANK3:
- register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR);
+ register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR);
break;
+#endif /* FMC_BANK3 */
case BKPSRAM_BASE:
- register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR);
+ register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR);
break;
+#if defined (OCTOSPI2_BASE)
case OCTOSPI2_BASE:
- register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5AR);
+ register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM5AR);
+ register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR);
break;
+#endif /* OCTOSPI2_BASE */
+#if defined (HSPI1)
+ case HSPI1_BASE:
+ register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM6AR);
+ register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM6BR);
+ break;
+#endif /* HSPI1 */
default:
return HAL_ERROR;
break;
}
/* read register and update the descriptor for first area*/
- reg_value = READ_REG(*(__IO uint32_t *)register_address);
+ reg_value = READ_REG(*(__IO uint32_t *)register_address_regionA);
pMPCWM_Desc[0].AreaId = GTZC_TZSC_MPCWM_ID1;
pMPCWM_Desc[0].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk)
>> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity;
@@ -687,36 +770,16 @@
>> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity;
/* read configuration register and update the descriptor for first area*/
- reg_value = READ_REG(*(__IO uint32_t *)(register_address - 4U));
+ reg_value = READ_REG(*(__IO uint32_t *)(register_address_regionA - 4U));
pMPCWM_Desc[0].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos;
pMPCWM_Desc[0].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK;
pMPCWM_Desc[0].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN;
- if ((MemBaseAddress != FMC_BANK3) && (MemBaseAddress != BKPSRAM_BASE))
+ if (register_address_regionB != 0U)
{
- /* Here MemBaseAddress = OCTOSPI1_BASE, OCTOSPI2_BASE
- * or FMC_BANK1 (already checked)
- * Now take care of the second area, present on these sub-blocks
- */
- switch (MemBaseAddress)
- {
- case OCTOSPI1_BASE:
- register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR);
- break;
- case FMC_BANK1:
- register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR);
- break;
- case OCTOSPI2_BASE:
- register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR);
- break;
- default:
- return HAL_ERROR;
- break;
- }
-
/* read register and update the descriptor for second area*/
- reg_value = READ_REG(*(__IO uint32_t *)register_address);
+ reg_value = READ_REG(*(__IO uint32_t *)register_address_regionB);
pMPCWM_Desc[1].AreaId = GTZC_TZSC_MPCWM_ID2;
pMPCWM_Desc[1].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk)
>> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity;
@@ -724,9 +787,9 @@
>> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity;
/* read configuration register and update the descriptor for second area*/
- reg_value = READ_REG(*(__IO uint32_t *)(register_address - 4U));
- pMPCWM_Desc[1].Attribute = reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
- GTZC_TZSC_MPCWM_CFGR_SEC);
+ reg_value = READ_REG(*(__IO uint32_t *)(register_address_regionB - 4U));
+ pMPCWM_Desc[1].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
+ GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos;
pMPCWM_Desc[1].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK;
pMPCWM_Desc[1].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN;
}
@@ -768,7 +831,7 @@
* @param TZSC_Instance TZSC sub-block instance.
* @retval Lock State (GTZC_TZSC_LOCK_OFF or GTZC_TZSC_LOCK_ON)
*/
-uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSC_Instance)
+uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance)
{
return READ_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
}
@@ -800,10 +863,9 @@
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
- MPCBB_ConfigTypeDef *pMPCBB_desc)
+ const MPCBB_ConfigTypeDef *pMPCBB_desc)
{
GTZC_MPCBB_TypeDef *mpcbb_ptr;
- uint32_t reg_value;
uint32_t mem_size;
uint32_t size_in_superblocks;
uint32_t i;
@@ -811,24 +873,25 @@
/* check entry parameters */
if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
&& !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
+#if defined (SRAM3_BASE)
&& !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
- && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)))
- || ((pMPCBB_desc->SecureRWIllegalMode
- != GTZC_MPCBB_SRWILADIS_ENABLE)
- && (pMPCBB_desc->SecureRWIllegalMode
- != GTZC_MPCBB_SRWILADIS_DISABLE))
- || ((pMPCBB_desc->InvertSecureState
- != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
- && (pMPCBB_desc->InvertSecureState
- != GTZC_MPCBB_INVSECSTATE_INVERTED)))
+#endif /* SRAM3_BASE */
+ && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
+#if defined (SRAM5_BASE)
+ && !(IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
+#endif /* SRAM5_BASE */
+#if defined (SRAM6_BASE)
+ && !(IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
+#endif /* SRAM6_BASE */
+ )
+ || ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE)
+ && (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE))
+ || ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
+ && (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED)))
{
return HAL_ERROR;
}
- /* write InvertSecureState and SecureRWIllegalMode properties */
- /* assume their Position/Mask is identical for all sub-blocks */
- reg_value = pMPCBB_desc->InvertSecureState;
- reg_value |= pMPCBB_desc->SecureRWIllegalMode;
if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB1;
@@ -839,46 +902,40 @@
mpcbb_ptr = GTZC_MPCBB2;
mem_size = GTZC_MEM_SIZE(SRAM2);
}
+#if defined (SRAM3_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB3;
mem_size = GTZC_MEM_SIZE(SRAM3);
}
- else
+#endif /* SRAM3_BASE */
+ else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
{
- /* Here MemBaseAddress is inside SRAM4 (parameter already checked) */
mpcbb_ptr = GTZC_MPCBB4;
mem_size = GTZC_MEM_SIZE(SRAM4);
}
+#if defined (SRAM5_BASE)
+ else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
+ {
+ mpcbb_ptr = GTZC_MPCBB5;
+ mem_size = GTZC_MEM_SIZE(SRAM5);
+ }
+#endif /* SRAM5_BASE */
+#if defined (SRAM6_BASE)
+ else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
+ {
+ mpcbb_ptr = GTZC_MPCBB6;
+ mem_size = GTZC_MEM_SIZE(SRAM6);
+ }
+#endif /* SRAM6_BASE */
+ else
+ {
+ return HAL_ERROR;
+ }
/* translate mem_size in number of super-blocks */
size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
-#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- uint32_t size_mask;
-
- /* write configuration and lock register information */
- MODIFY_REG(mpcbb_ptr->CR,
- GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value);
- if (size_in_superblocks == 32U)
- {
- size_mask = 0xFFFFFFFFU;
- }
- else
- {
- size_mask = (1UL << size_in_superblocks) - 1U;
- }
- /* limitation: code not portable with memory > 512K */
- MODIFY_REG(mpcbb_ptr->CFGLOCKR1, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]);
-
- /* write SECCFGR register information */
- for (i = 0U; i < size_in_superblocks; i++)
- {
- WRITE_REG(mpcbb_ptr->SECCFGR[i],
- pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]);
- }
-#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
/* write PRIVCFGR register information */
for (i = 0U; i < size_in_superblocks; i++)
{
@@ -886,6 +943,40 @@
pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]);
}
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ uint32_t size_mask;
+ uint32_t reg_value;
+
+ /* write SECCFGR register information */
+ for (i = 0U; i < size_in_superblocks; i++)
+ {
+ WRITE_REG(mpcbb_ptr->SECCFGR[i],
+ pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]);
+ }
+
+#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk)
+ if (size_in_superblocks >= 32U)
+ {
+ size_mask = 0xFFFFFFFFU;
+ MODIFY_REG(mpcbb_ptr->CFGLOCKR2, 0x000FFFFFUL, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[1]);
+ }
+ else
+#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */
+ {
+ size_mask = (1UL << (size_in_superblocks & 0x1FU)) - 1U;
+ }
+ /* limitation: code not portable with memory > 512K */
+ MODIFY_REG(mpcbb_ptr->CFGLOCKR1, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]);
+
+ /* write InvertSecureState and SecureRWIllegalMode properties */
+ reg_value = pMPCBB_desc->InvertSecureState;
+ reg_value |= pMPCBB_desc->SecureRWIllegalMode;
+
+ /* write configuration and lock register information */
+ MODIFY_REG(mpcbb_ptr->CR,
+ GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value);
+#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
return HAL_OK;
}
@@ -907,8 +998,17 @@
/* check entry parameters */
if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
&& !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
+#if defined (SRAM3_BASE)
&& !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
- && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)))
+#endif /* SRAM3_BASE */
+ && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
+#if defined (SRAM5_BASE)
+ && !(IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
+#endif /* SRAM5_BASE */
+#if defined (SRAM6_BASE)
+ && !(IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
+#endif /* SRAM6_BASE */
+ )
{
return HAL_ERROR;
}
@@ -925,39 +1025,55 @@
mpcbb_ptr = GTZC_MPCBB2;
mem_size = GTZC_MEM_SIZE(SRAM2);
}
+#if defined (SRAM3_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB3;
mem_size = GTZC_MEM_SIZE(SRAM3);
}
- else
+#endif /* SRAM3_BASE */
+ else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB4;
mem_size = GTZC_MEM_SIZE(SRAM4);
}
+#if defined (SRAM5_BASE)
+ else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
+ {
+ mpcbb_ptr = GTZC_MPCBB5;
+ mem_size = GTZC_MEM_SIZE(SRAM5);
+ }
+#endif /* SRAM5_BASE */
+#if defined (SRAM6_BASE)
+ else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
+ {
+ mpcbb_ptr = GTZC_MPCBB6;
+ mem_size = GTZC_MEM_SIZE(SRAM6);
+ }
+#endif /* SRAM6_BASE */
+ else
+ {
+ return HAL_ERROR;
+ }
/* translate mem_size in number of super-blocks */
size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
uint32_t reg_value;
- uint32_t size_mask;
/* read configuration and lock register information */
reg_value = READ_REG(mpcbb_ptr->CR);
pMPCBB_desc->InvertSecureState = (reg_value & GTZC_MPCBB_CR_INVSECSTATE_Msk);
pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk);
- if (size_in_superblocks == 32U)
- {
- size_mask = 0xFFFFFFFFU;
- }
- else
- {
- size_mask = (1UL << size_in_superblocks) - 1U;
- }
+
/* limitation: code not portable with memory > 512K */
- pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->CFGLOCKR1)
- & size_mask;
+ pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->CFGLOCKR1);
+
+#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk)
+ pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[1] = READ_REG(mpcbb_ptr->CFGLOCKR2);
+#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */
+
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* read SECCFGR / PRIVCFGR registers information */
@@ -978,13 +1094,13 @@
* @param NbBlocks Number of blocks to configure
* (Block size is 512 Bytes).
* @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
- * with each element must be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC,
- * and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV.
+ * with each element must be GTZC_MPCBB_BLOCK_NSEC or GTZC_MPCBB_BLOCK_SEC,
+ * and GTZC_MPCBB_BLOCK_NPRIV or GTZC_MPCBB_BLOCK_PRIV.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
uint32_t NbBlocks,
- uint32_t *pMemAttributes)
+ const uint32_t *pMemAttributes)
{
GTZC_MPCBB_TypeDef *mpcbb_ptr;
uint32_t base_address;
@@ -1027,6 +1143,7 @@
mpcbb_ptr = GTZC_MPCBB2;
base_address = SRAM2_BASE_S;
}
+#if defined (SRAM3_BASE)
else if (((IS_ADDRESS_IN_NS(SRAM3, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM3, end_address))) != 0U)
{
@@ -1039,6 +1156,7 @@
mpcbb_ptr = GTZC_MPCBB3;
base_address = SRAM3_BASE_S;
}
+#endif /* SRAM3_BASE */
else if (((IS_ADDRESS_IN_NS(SRAM4, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM4, end_address))) != 0U)
{
@@ -1051,6 +1169,34 @@
mpcbb_ptr = GTZC_MPCBB4;
base_address = SRAM4_BASE_S;
}
+#if defined (SRAM5_BASE)
+ else if (((IS_ADDRESS_IN_NS(SRAM5, MemAddress))
+ && (IS_ADDRESS_IN_NS(SRAM5, end_address))) != 0U)
+ {
+ mpcbb_ptr = GTZC_MPCBB5;
+ base_address = SRAM5_BASE_NS;
+ }
+ else if (((IS_ADDRESS_IN_S(SRAM5, MemAddress))
+ && (IS_ADDRESS_IN_S(SRAM5, end_address))) != 0U)
+ {
+ mpcbb_ptr = GTZC_MPCBB5;
+ base_address = SRAM5_BASE_S;
+ }
+#endif /* SRAM5_BASE */
+#if defined (SRAM6_BASE)
+ else if (((IS_ADDRESS_IN_NS(SRAM6, MemAddress))
+ && (IS_ADDRESS_IN_NS(SRAM6, end_address))) != 0U)
+ {
+ mpcbb_ptr = GTZC_MPCBB6;
+ base_address = SRAM6_BASE_NS;
+ }
+ else if (((IS_ADDRESS_IN_S(SRAM6, MemAddress))
+ && (IS_ADDRESS_IN_S(SRAM6, end_address))) != 0U)
+ {
+ mpcbb_ptr = GTZC_MPCBB6;
+ base_address = SRAM6_BASE_S;
+ }
+#endif /* SRAM6_BASE */
else
{
return HAL_ERROR;
@@ -1068,13 +1214,13 @@
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* secure configuration */
- if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_SEC) == GTZC_MCPBB_BLOCK_SEC)
+ if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_SEC) == GTZC_MPCBB_BLOCK_SEC)
{
SET_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1UL << (offset_bit_start % 32U));
do_attr_change = 1U;
}
- else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NSEC) == GTZC_MCPBB_BLOCK_NSEC)
+ else if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_NSEC) == GTZC_MPCBB_BLOCK_NSEC)
{
CLEAR_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1UL << (offset_bit_start % 32U));
@@ -1087,12 +1233,12 @@
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* privilege configuration */
- if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_PRIV) == GTZC_MCPBB_BLOCK_PRIV)
+ if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_PRIV) == GTZC_MPCBB_BLOCK_PRIV)
{
SET_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1UL << (offset_bit_start % 32U));
}
- else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NPRIV) == GTZC_MCPBB_BLOCK_NPRIV)
+ else if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_NPRIV) == GTZC_MPCBB_BLOCK_NPRIV)
{
CLEAR_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1UL << (offset_bit_start % 32U));
@@ -1130,8 +1276,8 @@
* (must be 512 Bytes aligned).
* @param NbBlocks Number of blocks to get configuration.
* @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
- * with each element will be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC,
- * and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV.
+ * with each element will be GTZC_MPCBB_BLOCK_NSEC or GTZC_MPCBB_BLOCK_SEC,
+ * and GTZC_MPCBB_BLOCK_NPRIV or GTZC_MPCBB_BLOCK_PRIV.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
@@ -1178,6 +1324,7 @@
mpcbb_ptr = GTZC_MPCBB2_S;
base_address = SRAM2_BASE_S;
}
+#if defined (SRAM3_BASE)
else if ((IS_ADDRESS_IN_NS(SRAM3, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM3, end_address)))
{
@@ -1190,6 +1337,7 @@
mpcbb_ptr = GTZC_MPCBB3_S;
base_address = SRAM3_BASE_S;
}
+#endif /* SRAM3_BASE */
else if ((IS_ADDRESS_IN_NS(SRAM4, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM4, end_address)))
{
@@ -1202,6 +1350,34 @@
mpcbb_ptr = GTZC_MPCBB4_S;
base_address = SRAM4_BASE_S;
}
+#if defined (SRAM5_BASE)
+ else if ((IS_ADDRESS_IN_NS(SRAM5, MemAddress))
+ && (IS_ADDRESS_IN_NS(SRAM5, end_address)))
+ {
+ mpcbb_ptr = GTZC_MPCBB5_NS;
+ base_address = SRAM5_BASE_NS;
+ }
+ else if ((IS_ADDRESS_IN_S(SRAM5, MemAddress))
+ && (IS_ADDRESS_IN_S(SRAM5, end_address)))
+ {
+ mpcbb_ptr = GTZC_MPCBB5_S;
+ base_address = SRAM5_BASE_S;
+ }
+#endif /* SRAM5_BASE */
+#if defined (SRAM6_BASE)
+ else if ((IS_ADDRESS_IN_NS(SRAM6, MemAddress))
+ && (IS_ADDRESS_IN_NS(SRAM6, end_address)))
+ {
+ mpcbb_ptr = GTZC_MPCBB6_NS;
+ base_address = SRAM6_BASE_NS;
+ }
+ else if ((IS_ADDRESS_IN_S(SRAM6, MemAddress))
+ && (IS_ADDRESS_IN_S(SRAM6, end_address)))
+ {
+ mpcbb_ptr = GTZC_MPCBB6_S;
+ base_address = SRAM6_BASE_S;
+ }
+#endif /* SRAM6_BASE */
else
{
return HAL_ERROR;
@@ -1217,9 +1393,9 @@
pMemAttributes[i] = (READ_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1UL << (offset_bit_start % 32U))
>> (offset_bit_start % 32U)) | GTZC_ATTR_SEC_MASK;
- pMemAttributes[i] |= (READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
- 1UL << (offset_bit_start % 32U))
- >> (offset_bit_start % 32U)) | GTZC_ATTR_PRIV_MASK;
+ pMemAttributes[i] |= ((READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
+ 1UL << (offset_bit_start % 32U))
+ >> (offset_bit_start % 32U)) << 1U) | GTZC_ATTR_PRIV_MASK;
offset_bit_start++;
if (offset_bit_start == 32U)
@@ -1241,19 +1417,19 @@
* @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
* with for each element:
* value 0 super-block is unlocked, value 1 super-block is locked
- * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
- * GTZC_MCPBB_SUPERBLOCK_LOCKED values).
+ * (corresponds to GTZC_MPCBB_SUPERBLOCK_UNLOCKED and
+ * GTZC_MPCBB_SUPERBLOCK_LOCKED values).
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
uint32_t NbSuperBlocks,
- uint32_t *pLockAttributes)
+ const uint32_t *pLockAttributes)
{
__IO uint32_t *reg_mpcbb;
uint32_t base_address;
uint32_t superblock_start;
uint32_t offset_bit_start;
- uint32_t i;
+ uint32_t i = 0U;
/* firstly check that MemAddress is well 16KBytes aligned */
if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
@@ -1268,7 +1444,6 @@
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM1);
- /* limitation: code not portable with memory > 512K */
reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1;
}
else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
@@ -1277,28 +1452,46 @@
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM2);
- /* limitation: code not portable with memory > 512K */
reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1;
}
+#if defined (SRAM3_BASE)
else if ((IS_ADDRESS_IN(SRAM3, MemAddress))
&& (IS_ADDRESS_IN(SRAM3, (MemAddress
+ (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM3);
- /* limitation: code not portable with memory > 512K */
reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1;
}
-
+#endif /* SRAM3_BASE */
else if ((IS_ADDRESS_IN(SRAM4, MemAddress))
&& (IS_ADDRESS_IN(SRAM4, (MemAddress
+ (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM4);
- /* limitation: code not portable with memory > 512K */
reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB4_S->CFGLOCKR1;
}
+#if defined (SRAM5_BASE)
+ else if ((IS_ADDRESS_IN(SRAM5, MemAddress))
+ && (IS_ADDRESS_IN(SRAM5, (MemAddress
+ + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
+ - 1U))))
+ {
+ base_address = GTZC_BASE_ADDRESS(SRAM5);
+ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB5_S->CFGLOCKR1;
+ }
+#endif /* SRAM5_BASE */
+#if defined (SRAM6_BASE)
+ else if ((IS_ADDRESS_IN(SRAM6, MemAddress))
+ && (IS_ADDRESS_IN(SRAM6, (MemAddress
+ + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
+ - 1U))))
+ {
+ base_address = GTZC_BASE_ADDRESS(SRAM6);
+ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB6_S->CFGLOCKR1;
+ }
+#endif /* SRAM6_BASE */
else
{
return HAL_ERROR;
@@ -1308,13 +1501,14 @@
superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
offset_bit_start = superblock_start % 32U;
- for (i = 0U; i < NbSuperBlocks; i++)
+ /* First 32 super-blocks */
+ while ((i < NbSuperBlocks) && (i < 32U) && (superblock_start < 32U))
{
- if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_LOCKED)
+ if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_LOCKED)
{
SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
}
- else if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_UNLOCKED)
+ else if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_UNLOCKED)
{
CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
}
@@ -1324,8 +1518,36 @@
}
offset_bit_start++;
+ i++;
}
+#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk)
+ if ((NbSuperBlocks > 32U) || (superblock_start >= 32U))
+ {
+ /* Point to second configuration lock register */
+ reg_mpcbb++;
+
+ /* Remaining super-blocks */
+ for (; i < NbSuperBlocks; i++)
+ {
+ if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_LOCKED)
+ {
+ SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
+ }
+ else if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_UNLOCKED)
+ {
+ CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
+ }
+ else
+ {
+ break;
+ }
+
+ offset_bit_start++;
+ }
+ }
+#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */
+
/* an unexpected value in pLockAttributes array leads to an error status */
if (i != NbSuperBlocks)
{
@@ -1343,19 +1565,19 @@
* @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
* with for each element:
* value 0 super-block is unlocked, value 1 super-block is locked
- * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
- * GTZC_MCPBB_SUPERBLOCK_LOCKED values).
+ * (corresponds to GTZC_MPCBB_SUPERBLOCK_UNLOCKED and
+ * GTZC_MPCBB_SUPERBLOCK_LOCKED values).
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
uint32_t NbSuperBlocks,
uint32_t *pLockAttributes)
{
- uint32_t reg_mpcbb;
+ __IO uint32_t *reg_mpcbb;
uint32_t base_address;
uint32_t superblock_start;
uint32_t offset_bit_start;
- uint32_t i;
+ uint32_t i = 0U;
/* firstly check that MemAddress is well 16KBytes aligned */
if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
@@ -1370,8 +1592,7 @@
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM1);
- /* limitation: code not portable with memory > 512K */
- reg_mpcbb = GTZC_MPCBB1_S->CFGLOCKR1;
+ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1;
}
else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
&& (IS_ADDRESS_IN(SRAM2, (MemAddress
@@ -1380,9 +1601,9 @@
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM2);
- /* limitation: code not portable with memory > 512K */
- reg_mpcbb = GTZC_MPCBB2_S->CFGLOCKR1;
+ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1;
}
+#if defined (SRAM3_BASE)
else if ((IS_ADDRESS_IN(SRAM3, MemAddress))
&& (IS_ADDRESS_IN(SRAM3, (MemAddress
+ (NbSuperBlocks
@@ -1390,9 +1611,9 @@
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM3);
- /* limitation: code not portable with memory > 512K */
- reg_mpcbb = GTZC_MPCBB3_S->CFGLOCKR1;
+ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1;
}
+#endif /* SRAM3_BASE */
else if ((IS_ADDRESS_IN(SRAM4, MemAddress))
&& (IS_ADDRESS_IN(SRAM4, (MemAddress
+ (NbSuperBlocks
@@ -1400,25 +1621,64 @@
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM4);
- /* limitation: code not portable with memory > 512K */
- reg_mpcbb = GTZC_MPCBB4_S->CFGLOCKR1;
+ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB4_S->CFGLOCKR1;
}
+#if defined (SRAM5_BASE)
+ else if ((IS_ADDRESS_IN(SRAM5, MemAddress))
+ && (IS_ADDRESS_IN(SRAM5, (MemAddress
+ + (NbSuperBlocks
+ * GTZC_MPCBB_SUPERBLOCK_SIZE)
+ - 1U))))
+ {
+ base_address = GTZC_BASE_ADDRESS(SRAM5);
+ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB5_S->CFGLOCKR1;
+ }
+#endif /* SRAM5_BASE */
+
+#if defined (SRAM6_BASE)
+ else if ((IS_ADDRESS_IN(SRAM6, MemAddress))
+ && (IS_ADDRESS_IN(SRAM6, (MemAddress
+ + (NbSuperBlocks
+ * GTZC_MPCBB_SUPERBLOCK_SIZE)
+ - 1U))))
+ {
+ base_address = GTZC_BASE_ADDRESS(SRAM6);
+ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB6_S->CFGLOCKR1;
+ }
+#endif /* SRAM6_BASE */
else
{
return HAL_ERROR;
}
- /* get start coordinates of the configuration */
+ /* Get start coordinates of the configuration */
superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
offset_bit_start = superblock_start % 32U;
- for (i = 0U; i < NbSuperBlocks; i++)
+ while ((i < NbSuperBlocks) && (i < 32U) && (superblock_start < 32U))
{
- pLockAttributes[i] = (reg_mpcbb & (1UL << (offset_bit_start % 32U)))
+ pLockAttributes[i] = ((*reg_mpcbb) & (1UL << (offset_bit_start % 32U)))
>> (offset_bit_start % 32U);
offset_bit_start++;
+ i++;
}
+#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk)
+ if ((NbSuperBlocks > 32U) || (superblock_start >= 32U))
+ {
+ /* Point to second configuration lock register */
+ reg_mpcbb++;
+
+ /* Remaining super-blocks */
+ for (; i < NbSuperBlocks; i++)
+ {
+ pLockAttributes[i] = ((*reg_mpcbb) & (1UL << (offset_bit_start % 32U)))
+ >> (offset_bit_start % 32U);
+ offset_bit_start++;
+ }
+ }
+#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */
+
return HAL_OK;
}
@@ -1439,14 +1699,28 @@
{
SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
+#if defined (SRAM3_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
{
SET_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
+#endif /* SRAM3_BASE*/
else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
{
SET_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
+#if defined (SRAM5_BASE)
+ else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
+ {
+ SET_BIT(GTZC_MPCBB5_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
+ }
+#endif /* SRAM5_BASE */
+#if defined (SRAM6_BASE)
+ else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
+ {
+ SET_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
+ }
+#endif /* SRAM6_BASE */
else
{
return HAL_ERROR;
@@ -1458,7 +1732,7 @@
/**
* @brief Get MPCBB configuration lock state on the SRAM base address passed as parameter.
* @param MemBaseAddress MPCBB identifier.
- * @param pLockState pointer to Lock State (GTZC_MCPBB_LOCK_OFF or GTZC_MCPBB_LOCK_ON).
+ * @param pLockState pointer to Lock State (GTZC_MPCBB_LOCK_OFF or GTZC_MPCBB_LOCK_ON).
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,
@@ -1473,14 +1747,28 @@
{
*pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
+#if defined (SRAM3_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
{
*pLockState = READ_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
+#endif /* SRAM3_BASE */
else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
{
*pLockState = READ_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
+#if defined (SRAM5_BASE)
+ else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
+ {
+ *pLockState = READ_BIT(GTZC_MPCBB5_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
+ }
+#endif /* SRAM5_BASE */
+#if defined (SRAM6_BASE)
+ else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
+ {
+ *pLockState = READ_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
+ }
+#endif /* SRAM6_BASE */
else
{
return HAL_ERROR;
@@ -1618,37 +1906,37 @@
{
/* special case where it is applied to all peripherals */
reg_value = READ_REG(GTZC_TZIC1->SR1);
- for (i = 0U; i < 32U; i++)
+ for (i = 0U; i < REG_SIZE; i++)
{
pFlag[i] = (reg_value & (1UL << i)) >> i;
}
reg_value = READ_REG(GTZC_TZIC1->SR2);
- for (i = 32U; i < 64U; i++)
+ for (i = REG_SIZE; i < (2U * REG_SIZE); i++)
{
pFlag[i] = (reg_value & (1UL << (i - 32U))) >> (i - 32U);
}
reg_value = READ_REG(GTZC_TZIC1->SR3);
- for (i = 64; i < 96U; i++)
+ for (i = 2U * REG_SIZE; i < (3U * REG_SIZE); i++)
{
pFlag[i] = (reg_value & (1UL << (i - 64U))) >> (i - 64U);
}
reg_value = READ_REG(GTZC_TZIC1->SR4);
- for (i = 96U; i < 128U; i++)
+ for (i = 3U * REG_SIZE; i < (4U * REG_SIZE); i++)
{
pFlag[i] = (reg_value & (1UL << (i - 96U))) >> (i - 96U);
}
reg_value = READ_REG(GTZC_TZIC2->SR1);
- for (i = 128U; i < 160U; i++)
+ for (i = 4U * REG_SIZE; i < (5U * REG_SIZE); i++)
{
pFlag[i] = (reg_value & (1UL << (i - 128U))) >> (i - 128U);
}
reg_value = READ_REG(GTZC_TZIC2->SR2);
- for (i = 160U; i < GTZC_TZIC_PERIPH_NUMBER; i++)
+ for (i = 5U * REG_SIZE; i < GTZC_TZIC_PERIPH_NUMBER; i++)
{
pFlag[i] = (reg_value & (1UL << (i - 160U))) >> (i - 160U);
}
@@ -1921,4 +2209,3 @@
/**
* @}
*/
-
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash.c
index 24f6118..6f92988 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash.c
@@ -15,7 +15,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -124,7 +124,7 @@
(#) HAL in interruption mode (interruptions driven)
(##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes.
- This is why, for driver implementation simplicity’s sake, user is requested to enter a message the
+ This is why, for driver implementation simplicity's sake, user is requested to enter a message the
length of which is a multiple of 4 bytes.
(##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR
@@ -159,9 +159,9 @@
[..]
(#) The compilation define USE_HAL_HASH_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use function @ref HAL_HASH_RegisterCallback() to register a user callback.
+ Use function HAL_HASH_RegisterCallback() to register a user callback.
- (#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks:
+ (#) Function HAL_HASH_RegisterCallback() allows to register following callbacks:
(+) InCpltCallback : callback for input completion.
(+) DgstCpltCallback : callback for digest computation completion.
(+) ErrorCallback : callback for error.
@@ -170,9 +170,9 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- (#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default
+ (#) Use function HAL_HASH_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) InCpltCallback : callback for input completion.
@@ -181,13 +181,13 @@
(+) MspInitCallback : HASH MspInit.
(+) MspDeInitCallback : HASH MspDeInit.
- (#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET
+ (#) By default, after the HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
- examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback()
+ examples HAL_HASH_InCpltCallback(), HAL_HASH_DgstCpltCallback()
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init
- and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand)
- If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_HASH_Init
+ and HAL_HASH_DeInit only when these callbacks are null (not registered beforehand)
+ If not, MspInit or MspDeInit are not null, the HAL_HASH_Init and HAL_HASH_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
Callbacks can be registered/unregistered in READY state only.
@@ -195,8 +195,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit
- or @ref HAL_HASH_Init function.
+ using HAL_HASH_RegisterCallback before calling HAL_HASH_DeInit
+ or HAL_HASH_Init function.
When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -2942,6 +2942,14 @@
return HAL_OK;
}
} /* if (polling_step == 1) */
+ else
+ {
+ /* otherwise, carry on in interrupt-mode */
+ hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data
+ to be fed to the Peripheral */
+ hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Points at data which will be fed to the Peripheral at
+ the next interruption */
+ }
/* Process Unlock */
@@ -3557,3 +3565,4 @@
/**
* @}
*/
+
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash_ex.c
index 7cb325f..32a20b5 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash_ex.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_hash_ex.c
@@ -17,7 +17,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -1038,3 +1038,4 @@
/**
* @}
*/
+
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c.c
index af27d75..250041e 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c.c
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -615,7 +615,12 @@
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
- hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
+ }
+ else
+ {
+ /* Clear the I2C ADD10 bit */
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
@@ -2269,11 +2274,11 @@
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
}
return HAL_OK;
@@ -3028,11 +3033,11 @@
to avoid the risk of I2C interrupt handle execution before current
process unlock */
- /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT));
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
return HAL_OK;
}
@@ -4114,11 +4119,11 @@
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
}
return HAL_OK;
@@ -4899,7 +4904,7 @@
* the configuration information for the specified I2C.
* @retval None
*/
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
{
/* Get current IT Flags and IT sources value */
uint32_t itflags = READ_REG(hi2c->Instance->ISR);
@@ -5435,6 +5440,12 @@
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
+ /* Disable Interrupt related to address step */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
direction = I2C_GENERATE_START_READ;
@@ -5802,6 +5813,9 @@
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
+ /* Disable Interrupt related to address step */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
/* Enable only Error interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
@@ -5844,6 +5858,12 @@
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
+ /* Disable Interrupt related to address step */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ /* Enable only Error and NACK interrupt for data transfer */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
direction = I2C_GENERATE_START_READ;
@@ -6531,7 +6551,8 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Disable Interrupts and Store Previous state */
- if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+ (tmpstate == HAL_I2C_STATE_LISTEN))
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
@@ -7561,19 +7582,19 @@
{
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
{
- /* Enable ERR, STOP, NACK, and ADDR interrupts */
+ /* Enable ERR, STOP, NACK and ADDR interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
{
- /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+ /* Enable ERR, TC, STOP, NACK and TXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
}
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
{
- /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+ /* Enable ERR, TC, STOP, NACK and RXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
@@ -7601,13 +7622,13 @@
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
{
- /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+ /* Enable ERR, TC, STOP, NACK and TXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
}
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
{
- /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+ /* Enable ERR, TC, STOP, NACK and RXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
@@ -7623,7 +7644,7 @@
tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
}
- if ((hi2c->XferISR != I2C_Mem_ISR_DMA) && (InterruptRequest == I2C_XFER_RELOAD_IT))
+ if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
@@ -7637,7 +7658,6 @@
__HAL_I2C_ENABLE_IT(hi2c, tmpisr);
}
-
/**
* @brief Manage the disabling of Interrupts.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c_ex.c
index 39d2f3f..ae5e0e1 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c_ex.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_i2c_ex.c
@@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_icache.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_icache.c
index 3560393..36b790e 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_icache.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_icache.c
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -35,7 +35,7 @@
cache invalidate maintenance operation, error management and TrustZone
security support.
- (+) The ICACHE provides additionnaly the possibility to remap input address
+ (+) The ICACHE provides additionally the possibility to remap input address
falling into up to four memory regions (used to remap aliased code in
external memories to the internal Code region, for execution)
@@ -45,10 +45,13 @@
[..]
The ICACHE HAL driver can be used as follows:
- (#) Enable and disable the Instruction Cache with respectively
- @ref HAL_ICACHE_Enable() and @ref HAL_ICACHE_Disable()
+ (#) Optionally configure the Instruction Cache mode with
+ @ref HAL_ICACHE_ConfigAssociativityMode() if the default configuration
+ does not suit the application requirements.
- (#) Configure the Instruction Cache mode with @ref HAL_ICACHE_ConfigAssociativityMode()
+ (#) Enable and disable the Instruction Cache with respectively
+ @ref HAL_ICACHE_Enable() and @ref HAL_ICACHE_Disable().
+ Use @ref HAL_ICACHE_IsEnabled() to get the Instruction Cache status.
(#) Initiate the cache maintenance invalidation procedure with either
@ref HAL_ICACHE_Invalidate() (blocking mode) or @ref HAL_ICACHE_Invalidate_IT()
@@ -234,9 +237,9 @@
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart;
- /* Reset BSYENDF before to disable the instruction cache */
- /* that starts a cache invalidation procedure */
- CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
+ /* Make sure BSYENDF is reset before to disable the instruction cache */
+ /* as it automatically starts a cache invalidation procedure */
+ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
@@ -287,7 +290,7 @@
else
{
/* Make sure BSYENDF is reset before to start cache invalidation */
- CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
+ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
/* Launch cache invalidation */
SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
@@ -317,7 +320,7 @@
}
else
{
- /* Make sure BSYENDF is reset */
+ /* Make sure BSYENDF is reset before to start cache invalidation */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
/* Enable end of cache invalidation interrupt */
@@ -485,7 +488,7 @@
/* Disable error interrupt */
CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
- /* Clear ICACHE error pending flag */
+ /* Clear ERR pending flag */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
/* Instruction cache error interrupt user callback */
@@ -498,7 +501,7 @@
/* Disable end of cache invalidation interrupt */
CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
- /* Clear ICACHE busyend pending flag */
+ /* Clear BSYENDF pending flag */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
/* Instruction cache busyend interrupt user callback */
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_ospi.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_ospi.c
index b4284d4..d888e2a 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_ospi.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_ospi.c
@@ -14,16 +14,18 @@
+ DMA channel configuration for indirect functional mode
+ Errors management and abort functionality
+ IO manager configuration
+
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
+ *
******************************************************************************
@verbatim
===============================================================================
@@ -51,7 +53,7 @@
and the CS boundary using the HAL_OSPI_Init() function.
[..]
When using Hyperbus, configure the RW recovery time, the access time,
- the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg()
+ the write latency and the latency mode using the HAL_OSPI_HyperbusCfg()
function.
*** Indirect functional mode ***
@@ -189,7 +191,7 @@
[..]
Use function HAL_OSPI_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) ErrorCallback : callback when error occurs.
(+) AbortCpltCallback : callback when abort is completed.
(+) FifoThresholdCallback : callback when the fifo threshold is reached.
@@ -207,9 +209,9 @@
[..]
By default, after the HAL_OSPI_Init() and if the state is HAL_OSPI_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_OSPI_Init()
+ reset to the legacy weak (overridden) functions in the HAL_OSPI_Init()
and HAL_OSPI_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_OSPI_Init() and HAL_OSPI_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -226,7 +228,7 @@
[..]
When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -282,7 +284,9 @@
static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State,
uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
+#if defined (OCTOSPIM)
static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg);
+#endif /* OCTOSPIM */
/**
@endcond
*/
@@ -410,7 +414,7 @@
((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
/* Configure Dual Quad mode */
- MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad);
+ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DMM, hospi->Init.DualQuad);
/* Configure sample shifting and delay hold quarter cycle */
MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC),
@@ -2128,7 +2132,7 @@
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User OSPI Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used to override the weak predefined callback
* @param hospi : OSPI handle
* @param CallbackID : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -2238,7 +2242,7 @@
/**
* @brief Unregister a User OSPI Callback
- * OSPI Callback is redirected to the weak (surcharged) predefined callback
+ * OSPI Callback is redirected to the weak predefined callback
* @param hospi : OSPI handle
* @param CallbackID : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -2540,7 +2544,7 @@
* @param hospi : OSPI handle.
* @retval Fifo threshold
*/
-uint32_t HAL_OSPI_GetFifoThreshold(OSPI_HandleTypeDef *hospi)
+uint32_t HAL_OSPI_GetFifoThreshold(const OSPI_HandleTypeDef *hospi)
{
return ((READ_BIT(hospi->Instance->CR, OCTOSPI_CR_FTHRES) >> OCTOSPI_CR_FTHRES_Pos) + 1U);
}
@@ -2561,7 +2565,7 @@
* @param hospi : OSPI handle
* @retval OSPI Error Code
*/
-uint32_t HAL_OSPI_GetError(OSPI_HandleTypeDef *hospi)
+uint32_t HAL_OSPI_GetError(const OSPI_HandleTypeDef *hospi)
{
return hospi->ErrorCode;
}
@@ -2571,7 +2575,7 @@
* @param hospi : OSPI handle
* @retval HAL state
*/
-uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi)
+uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi)
{
/* Return OSPI handle state */
return hospi->State;
@@ -2581,6 +2585,7 @@
* @}
*/
+#if defined (OCTOSPIM)
/** @defgroup OSPI_Exported_Functions_Group4 IO Manager configuration function
* @brief OSPI IO Manager configuration function
*
@@ -2622,7 +2627,7 @@
assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort));
assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort));
- if (hospi->Instance == OCTOSPI1)
+ if (hospi->Instance == (OCTOSPI_TypeDef *)OCTOSPI1)
{
instance = 0U;
other_instance = 1U;
@@ -2673,12 +2678,12 @@
}
if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
{
- SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
+ SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], \
OCTOSPIM_PCR_IOLSRC_1);
}
if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
{
- SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
+ SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], \
OCTOSPIM_PCR_IOHSRC_1);
}
}
@@ -2854,6 +2859,7 @@
/**
* @}
*/
+#endif /* OCTOSPIM */
/**
@cond 0
@@ -3045,7 +3051,7 @@
/* Configure the flash ID */
if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE)
{
- MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FSEL, cmd->FlashId);
+ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_MSEL, cmd->FlashId);
}
if (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)
@@ -3179,8 +3185,8 @@
/* Configure the CCR register with all communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE |
OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
- (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize |
- cmd->DataMode | cmd->DataDtrMode));
+ (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize | cmd->DataMode |
+ cmd->DataDtrMode));
}
else
{
@@ -3206,6 +3212,7 @@
return status;
}
+#if defined (OCTOSPIM)
/**
* @brief Get the current IOM configuration for an OctoSPI instance.
* @param instance_nb : number of the instance
@@ -3320,6 +3327,7 @@
/* Return function status */
return status;
}
+#endif /* OCTOSPIM */
/** @defgroup OSPI_Exported_Functions_Group5 Delay Block function
@@ -3346,11 +3354,13 @@
HAL_StatusTypeDef HAL_OSPI_DLYB_SetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg)
{
HAL_StatusTypeDef status = HAL_ERROR;
- uint32_t tickstart;
/* Enable OCTOSPI Free Running Clock (mandatory) */
SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
+ /* Update OCTOSPI state */
+ hospi->State = HAL_OSPI_STATE_BUSY_CMD;
+
if (hospi->Instance == OCTOSPI1)
{
/* Enable the DelayBlock */
@@ -3361,6 +3371,7 @@
status = HAL_OK;
}
+#if defined (OCTOSPI2)
else if (hospi->Instance == OCTOSPI2)
{
/* Enable the DelayBlock */
@@ -3370,33 +3381,19 @@
LL_DLYB_SetDelay(DLYB_OCTOSPI2, pdlyb_cfg);
status = HAL_OK;
}
+#endif /* OCTOSPI2 */
else
{
/* Nothing to do */
}
- /* Disable OCTOSPI */
- __HAL_OSPI_DISABLE(hospi);
-
- /* Wait till OSPI Disabled or if Time out is reached, exit */
- tickstart = HAL_GetTick();
- while (READ_BIT(hospi->Instance->CR, OCTOSPI_CR_EN) == (uint32_t)SET)
- {
- if ((HAL_GetTick() - tickstart) > hospi->Timeout)
- {
- hospi->State = HAL_OSPI_STATE_ERROR;
- hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
+ /* Abort the current OCTOSPI operation if exist */
+ (void)HAL_OSPI_Abort(hospi);
/* Disable Free Running Clock */
CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
- /* Re-Enable OCTOSPI */
- __HAL_OSPI_ENABLE(hospi);
-
/* Return function status */
return status;
}
@@ -3407,7 +3404,7 @@
* @param pdlyb_cfg: Pointer to DLYB configuration structure.
* @retval HAL status.
*/
-HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg)
+HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(const OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg)
{
HAL_StatusTypeDef status = HAL_ERROR;
@@ -3416,11 +3413,13 @@
LL_DLYB_GetDelay(DLYB_OCTOSPI1, pdlyb_cfg);
status = HAL_OK;
}
+#if defined (OCTOSPI2)
else if (hospi->Instance == OCTOSPI2)
{
LL_DLYB_GetDelay(DLYB_OCTOSPI2, pdlyb_cfg);
status = HAL_OK;
}
+#endif /* OCTOSPI2 */
else
{
@@ -3439,11 +3438,13 @@
HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg)
{
HAL_StatusTypeDef status = HAL_ERROR;
- uint32_t tickstart;
/* Enable OCTOSPI Free Running Clock (mandatory) */
SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
+ /* Update OCTOSPI state */
+ hospi->State = HAL_OSPI_STATE_BUSY_CMD;
+
if (hospi->Instance == OCTOSPI1)
{
/* Enable the DelayBlock */
@@ -3456,9 +3457,10 @@
}
/* Disable the DelayBlock */
- LL_DLYB_Enable(DLYB_OCTOSPI1);
+ LL_DLYB_Disable(DLYB_OCTOSPI1);
}
+#if defined (OCTOSPI2)
else if (hospi->Instance == OCTOSPI2)
{
/* Enable the DelayBlock */
@@ -3471,35 +3473,21 @@
}
/* Disable the DelayBlock */
- LL_DLYB_Enable(DLYB_OCTOSPI2);
+ LL_DLYB_Disable(DLYB_OCTOSPI2);
}
+#endif /* OCTOSPI2 */
else
{
/* Nothing to do */
}
- /* Disable OCTOSPI */
- __HAL_OSPI_DISABLE(hospi);
-
- /* Wait till OSPI Disabled or if Time out is reached, exit */
- tickstart = HAL_GetTick();
- while (READ_BIT(hospi->Instance->CR, OCTOSPI_CR_EN) == (uint32_t)SET)
- {
- if ((HAL_GetTick() - tickstart) > hospi->Timeout)
- {
- hospi->State = HAL_OSPI_STATE_ERROR;
- hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
+ /* Abort the current OctoSPI operation if exist */
+ (void)HAL_OSPI_Abort(hospi);
/* Disable Free Running Clock */
CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
- /* Re-Enable OCTOSPI */
- __HAL_OSPI_ENABLE(hospi);
-
/* Return function status */
return status;
}
@@ -3511,10 +3499,6 @@
* @}
*/
-/**
- * @}
- */
-
#endif /* HAL_OSPI_MODULE_ENABLED */
/**
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pka.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pka.c
index b80d4a0..eab1bf3 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pka.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pka.c
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -200,11 +200,11 @@
The compilation flag USE_HAL_PKA_REGISTER_CALLBACKS, when set to 1,
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_PKA_RegisterCallback()
+ Use Functions HAL_PKA_RegisterCallback()
to register an interrupt callback.
[..]
- Function @ref HAL_PKA_RegisterCallback() allows to register following callbacks:
+ Function HAL_PKA_RegisterCallback() allows to register following callbacks:
(+) OperationCpltCallback : callback for End of operation.
(+) ErrorCallback : callback for error detection.
(+) MspInitCallback : callback for Msp Init.
@@ -213,11 +213,11 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_PKA_UnRegisterCallback to reset a callback to the default
+ Use function HAL_PKA_UnRegisterCallback to reset a callback to the default
weak function.
[..]
- @ref HAL_PKA_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_PKA_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) OperationCpltCallback : callback for End of operation.
@@ -226,27 +226,27 @@
(+) MspDeInitCallback : callback for Msp DeInit.
[..]
- By default, after the @ref HAL_PKA_Init() and when the state is @ref HAL_PKA_STATE_RESET
+ By default, after the HAL_PKA_Init() and when the state is HAL_PKA_STATE_RESET
all callbacks are set to the corresponding weak functions:
- examples @ref HAL_PKA_OperationCpltCallback(), @ref HAL_PKA_ErrorCallback().
+ examples HAL_PKA_OperationCpltCallback(), HAL_PKA_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the @ref HAL_PKA_Init()/ @ref HAL_PKA_DeInit() only when
+ reset to the legacy weak functions in the HAL_PKA_Init()/ HAL_PKA_DeInit() only when
these callbacks are null (not registered beforehand).
[..]
- If MspInit or MspDeInit are not null, the @ref HAL_PKA_Init()/ @ref HAL_PKA_DeInit()
+ If MspInit or MspDeInit are not null, the HAL_PKA_Init()/ HAL_PKA_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
- Callbacks can be registered/unregistered in @ref HAL_PKA_STATE_READY state only.
+ Callbacks can be registered/unregistered in HAL_PKA_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
- in @ref HAL_PKA_STATE_READY or @ref HAL_PKA_STATE_RESET state,
+ in HAL_PKA_STATE_READY or HAL_PKA_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
[..]
Then, the user first registers the MspInit/MspDeInit user callbacks
- using @ref HAL_PKA_RegisterCallback() before calling @ref HAL_PKA_DeInit()
- or @ref HAL_PKA_Init() function.
+ using HAL_PKA_RegisterCallback() before calling HAL_PKA_DeInit()
+ or HAL_PKA_Init() function.
[..]
When the compilation flag USE_HAL_PKA_REGISTER_CALLBACKS is set to 0 or
@@ -288,13 +288,16 @@
*/
/* Private variables ---------------------------------------------------------*/
+static uint32_t primeordersize;
+static uint32_t opsize;
+static uint32_t modulussize;
/* Private function prototypes -----------------------------------------------*/
/** @defgroup PKA_Private_Functions PKA Private Functions
* @{
*/
-uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka);
-HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart);
-uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode);
+uint32_t PKA_GetMode(const PKA_HandleTypeDef *hpka);
+HAL_StatusTypeDef PKA_PollEndOfOperation(const PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart);
+uint32_t PKA_CheckError(const PKA_HandleTypeDef *hpka, uint32_t mode);
uint32_t PKA_GetBitSize_u8(uint32_t byteNumber);
uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb);
uint32_t PKA_GetBitSize_u32(uint32_t wordNumber);
@@ -322,7 +325,7 @@
void PKA_ECCCompleteAddition_Set(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in);
HAL_StatusTypeDef PKA_WaitOnFlagUntilTimeout(PKA_HandleTypeDef *hpka, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout);
-uint32_t PKA_Result_GetSize(PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize);
+uint32_t PKA_Result_GetSize(const PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize);
/**
* @}
*/
@@ -807,6 +810,8 @@
/* Set input parameter in PKA RAM */
PKA_ModExp_Set(hpka, in);
+ opsize = in->OpSize;
+
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout);
}
@@ -822,6 +827,8 @@
/* Set input parameter in PKA RAM */
PKA_ModExp_Set(hpka, in);
+ opsize = in->OpSize;
+
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP);
}
@@ -838,6 +845,8 @@
/* Set input parameter in PKA RAM */
PKA_ModExpFastMode_Set(hpka, in);
+ opsize = in->OpSize;
+
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout);
}
@@ -853,6 +862,8 @@
/* Set input parameter in PKA RAM */
PKA_ModExpFastMode_Set(hpka, in);
+ opsize = in->OpSize;
+
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE);
}
@@ -871,6 +882,8 @@
/* Set input parameter in PKA RAM */
PKA_ModExpProtectMode_Set(hpka, in);
+ opsize = in->OpSize;
+
return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_PROTECT, Timeout);
}
@@ -886,6 +899,8 @@
/* Set input parameter in PKA RAM */
PKA_ModExpProtectMode_Set(hpka, in);
+ opsize = in->OpSize;
+
return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_PROTECT);
}
@@ -900,7 +915,7 @@
uint32_t size;
/* Get output result size */
- size = PKA_Result_GetSize(hpka, PKA_MODULAR_EXP_OUT_RESULT, 130UL);
+ size = opsize;
/* Move the result to appropriate location (indicated in out parameter) */
PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_RESULT], size);
@@ -918,6 +933,8 @@
/* Set input parameter in PKA RAM */
PKA_ECDSASign_Set(hpka, in);
+ primeordersize = in->primeOrderSize;
+
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout);
}
@@ -933,6 +950,8 @@
/* Set input parameter in PKA RAM */
PKA_ECDSASign_Set(hpka, in);
+ primeordersize = in->primeOrderSize;
+
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE);
}
@@ -949,7 +968,8 @@
uint32_t size;
/* Get output result size */
- size = PKA_Result_GetSize(hpka, PKA_ECDSA_SIGN_OUT_SIGNATURE_R, 20UL);
+ size = primeordersize;
+
if (out != NULL)
{
@@ -1110,6 +1130,8 @@
/* Set input parameter in PKA RAM */
PKA_ECCMul_Set(hpka, in);
+ modulussize = in->modulusSize;
+
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout);
}
@@ -1125,6 +1147,8 @@
/* Set input parameter in PKA RAM */
PKA_ECCMul_Set(hpka, in);
+ modulussize = in->modulusSize;
+
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL);
}
@@ -1139,7 +1163,7 @@
uint32_t size;
/* Get output result size */
- size = PKA_Result_GetSize(hpka, PKA_ECC_SCALAR_MUL_OUT_RESULT_X, 20UL);
+ size = modulussize;
/* If a destination buffer is provided */
if (out != NULL)
@@ -1838,7 +1862,7 @@
* @param hpka PKA handle
* @retval HAL status
*/
-HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka)
+HAL_PKA_StateTypeDef HAL_PKA_GetState(const PKA_HandleTypeDef *hpka)
{
/* Return PKA handle state */
return hpka->State;
@@ -1849,7 +1873,7 @@
* @param hpka PKA handle
* @retval PKA error code
*/
-uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka)
+uint32_t HAL_PKA_GetError(const PKA_HandleTypeDef *hpka)
{
/* Return PKA handle error code */
return hpka->ErrorCode;
@@ -1872,7 +1896,7 @@
* @param hpka PKA handle
* @retval Return the current mode
*/
-uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka)
+uint32_t PKA_GetMode(const PKA_HandleTypeDef *hpka)
{
/* return the shifted PKA_CR_MODE value */
return (uint32_t)(READ_BIT(hpka->Instance->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos);
@@ -1885,7 +1909,7 @@
* @param Tickstart Tick start value
* @retval HAL status
*/
-HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart)
+HAL_StatusTypeDef PKA_PollEndOfOperation(const PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart)
{
/* Wait for the end of operation or timeout */
while ((hpka->Instance->SR & PKA_SR_PROCENDF) == 0UL)
@@ -1908,7 +1932,7 @@
* @param mode PKA operating mode
* @retval error code
*/
-uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode)
+uint32_t PKA_CheckError(const PKA_HandleTypeDef *hpka, uint32_t mode)
{
uint32_t err = HAL_PKA_ERROR_NONE;
@@ -2264,15 +2288,15 @@
/* Move the input parameters pOp1 to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize);
- __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL));
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + ((in->OpSize + 3UL) / 4UL));
/* Move the exponent to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize);
- __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL));
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + ((in->expSize + 3UL) / 4UL));
/* Move the modulus to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize);
- __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL));
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + ((in->OpSize + 3UL) / 4UL));
}
/**
@@ -2340,6 +2364,8 @@
* @brief Set input parameters.
* @param hpka PKA handle
* @param in Input information
+ * @note If the modulus size is bigger than the hash size (with a curve SECP521R1 when using a SHA256 hash
+ * for example)the hash value should be written at the end of the buffer with zeros padding at beginning.
*/
void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in)
{
@@ -2544,7 +2570,7 @@
/* Move the input parameters coefficient b to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], in->coefB, in->modulusSize);
- __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + (in->modulusSize / 4UL));
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters modulus value p to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize);
@@ -2564,7 +2590,7 @@
/* Move the input parameters curve prime order N to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize);
- __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + (in->modulusSize / 4UL));
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL));
}
@@ -2606,7 +2632,7 @@
/* Move the input parameters modulus value n to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MODULUS], in->pMod, in->modSize);
- __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_MODULUS + (in->modSize / 4UL));
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_MODULUS + ((in->modSize + 3UL) / 4UL));
}
/**
@@ -2907,7 +2933,7 @@
* @param Maxsize Specifies the possible max size of the result in words
* @retval size
*/
-uint32_t PKA_Result_GetSize(PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize)
+uint32_t PKA_Result_GetSize(const PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize)
{
uint32_t size;
uint32_t current_index = Maxsize - 1UL;
@@ -2936,4 +2962,3 @@
/**
* @}
*/
-
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr.c
index 5acfe51..069dad2 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr.c
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -644,11 +644,6 @@
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
- /* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM)
- __force_stores();
-#endif /*( __CC_ARM)*/
-
/* Wait For Interrupt Request */
__WFI();
}
@@ -870,6 +865,9 @@
}
}
#else
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Item);
+
/* NSecure item management (TZEN = 0) */
if ((Attributes & PWR_ITEM_ATTR_NSEC_PRIV_MASK) == PWR_ITEM_ATTR_NSEC_PRIV_MASK)
{
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr_ex.c
index 1f03758..37265e4 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr_ex.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_pwr_ex.c
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -84,7 +84,7 @@
(#) Call HAL_PWREx_EnableVddUSB(), HAL_PWREx_EnableVddIO2() and
HAL_PWREx_EnableVddA() to enable respectively VDDUSB, VDDIO2 and VDDA
electrical and logical isolation.
- It is recommanded to disable VDDUSB, VDDIO2 and VDDA electrical and
+ It is recommended to disable VDDUSB, VDDIO2 and VDDA electrical and
logical isolation through HAL_PWREx_DisableVddUSB(),
HAL_PWREx_DisableVddIO2() and HAL_PWREx_DisableVddA().
@@ -101,6 +101,23 @@
(++) VDDA versus 1V6
(++) VDDA versus 1V8
+ (#) Call HAL_PWREx_EnableUSBHSTranceiverSupply() and
+ HAL_PWREx_DisableUSBHSTranceiverSupply() to enable / disable the internal
+ USB HS transceiver supply.
+ (+) This feature is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx
+ and STM32U5Gxxx devices
+
+ (#) Call HAL_PWREx_EnableOTGHSPHYLowPowerRetention() and
+ HAL_PWREx_DisableOTGHSPHYLowPowerRetention() to enable / disable OTG_HS PHY power during
+ low power modes (Stop2, Stop3 and Standby).
+ (+) This feature is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx
+ and STM32U5Gxxx devices
+
+ (#) Call HAL_PWREx_EnableVDD11USB() and
+ HAL_PWREx_DisableVDD11USB() to enable/ disable the VDD11USB.
+ (+) This feature is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx
+ and STM32U5Gxxx devices
+
(#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring() to
enable / disable the VBAT and temperature monitoring.
@@ -126,15 +143,29 @@
(+) Retained RAM can be one of the following RAMs :
(++) SRAM1
(++) SRAM2
- (++) SRAM3
+ (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx,
+ STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices)
(++) SRAM4
+ (++) SRAM5 (available only for STM32U59xxx, STM32U5Axxx,
+ STM32U5Fxxx and STM32U5Gxxx devices)
+ (++) SRAM6 (available only for STM32U5Fxxx and STM32U5Gxxx devices)
(++) ICACHE
- (++) DMA2DRAM
+ (++) DMA2DRAM (available only for STM32U575xx, STM32U585xx, STM32U59xxx,
+ STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices)
(++) PKA32RAM
(++) DCACHE1
(++) FMAC
(++) FDCAN
(++) USB
+ (++) DCACHE2 (available only for STM32U59xxx, STM32U5Axxx,
+ STM32U5Fxxx and STM32U5Gxxx devices)
+ (++) LTDC (available only for STM32U59xxx, STM32U5Axxx,
+ STM32U5Fxxx and STM32U5Gxxx devices)
+ (++) GFXMMU (available only for STM32U59xxx, STM32U5Axxx,
+ STM32U5Fxxx and STM32U5Gxxx devices)
+ (++) DSI (available only for STM32U59xxx, STM32U5Axxx,
+ STM32U5Fxxx and STM32U5Gxxx devices)
+ (++) JPEG (available only for STM32U5Fxxx and STM32U5Gxxx devices)
(#) Call HAL_PWREx_EnableRAMsContentRunRetention() and
HAL_PWREx_DisableRAMsContentRunRetention() to
@@ -142,8 +173,12 @@
(+) Retained RAM can be one of the following RAMs :
(++) SRAM1
(++) SRAM2
- (++) SRAM3
+ (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx,
+ STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices)
(++) SRAM4
+ (++) SRAM5 (available only for STM32U59xxx, STM32U5Axxx,
+ STM32U5Fxxx and STM32U5Gxxx devices)
+ (++) SRAM6 (available only for STM32U5Fxxx and STM32U5Gxxx devices)
(#) Call HAL_PWREx_EnableFlashFastWakeUp() and
HAL_PWREx_DisableFlashFastWakeUp() to enable / disable the flash memory
@@ -162,9 +197,9 @@
and pull-down configuration.
(#) Call HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() to
- apply repectively pull-up and pull-down to selected I/O.
+ apply respectively pull-up and pull-down to selected I/O.
Call HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() to
- disable applied repectively pull-up and pull-down to selected I/O.
+ disable applied respectively pull-up and pull-down to selected I/O.
@endverbatim
******************************************************************************
@@ -190,9 +225,17 @@
/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
* @{
*/
-/*!< PORTI pins mask */
-#define PWR_PORTI_AVAILABLE_PINS (0xFFU)
-/*!< Time out value of flags setting */
+#if defined (PWR_PUCRJ_PU0)
+/* PORTI pins mask */
+#define PWR_PORTI_AVAILABLE_PINS (0xFFFFU)
+/* PORTJ pins mask */
+#define PWR_PORTJ_AVAILABLE_PINS (0x0FFFU)
+#else
+/* PORTI pins mask */
+#define PWR_PORTI_AVAILABLE_PINS (0x00FFU)
+#endif /* defined (PWR_PUCRJ_PU0) */
+
+/* Time out value of flags setting */
#define PWR_FLAG_SETTING_DELAY (0x32U)
/** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask
@@ -309,6 +352,13 @@
/* No change, nothing to do */
if (vos_old == VoltageScaling)
{
+ /* Enable USB BOOST after wake up from Stop mode */
+ if (VoltageScaling > PWR_REGULATOR_VOLTAGE_SCALE3)
+ {
+ /* Enable USB BOOST */
+ SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN);
+ }
+
return HAL_OK;
}
@@ -326,7 +376,7 @@
MODIFY_REG(PWR->VOSR, (PWR_VOSR_VOS | PWR_VOSR_BOOSTEN), VoltageScaling);
}
- /* Wait until VOSRDY is rised */
+ /* Wait until VOSRDY is raised */
timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U;
while (HAL_IS_BIT_CLR(PWR->VOSR, PWR_VOSR_VOSRDY) && (timeout != 0U))
{
@@ -336,7 +386,7 @@
/* Check time out */
if (timeout != 0U)
{
- /* Wait until ACTVOSRDY is rised */
+ /* Wait until ACTVOSRDY is raised */
timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U;
while ((HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)) && (timeout != 0U))
{
@@ -538,7 +588,7 @@
*** Stop 3 mode ***
===================
[..]
- The Stop 3 mode is based on the Cortex®-M33 Deepsleep mode combined with
+ The Stop 3 mode is based on the Cortex-M33 Deepsleep mode combined with
peripheral clock gating. In Stop 3 mode, all clocks in the VCORE domain
are stopped.
The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled.
@@ -1005,7 +1055,7 @@
The switch to the VBAT supply is controlled by the power down reset
embedded in the Reset block.
- (+) After exiting reset, the USB Type-C “dead battery” behavior is enabled,
+ (+) After exiting reset, the USB Type-C (dead battery) behavior is enabled,
which may have a pull-down effect on CC1 and CC2 pins. It is
recommended to disable it in all cases, either to stop this pull-down
or to handover control to the UCPD (the UCPD must be initialized
@@ -1331,6 +1381,86 @@
CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
}
+#if defined (PWR_VOSR_USBPWREN)
+/**
+ * @brief Enable the internal USB HS transceiver supply.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_PWREx_EnableUSBHSTranceiverSupply(void)
+{
+ uint32_t vos;
+
+ /* Get the system applied voltage scaling range */
+ vos = HAL_PWREx_GetVoltageRange();
+
+ /* Check the system applied voltage scaling range */
+ if ((vos == PWR_REGULATOR_VOLTAGE_SCALE1) || (vos == PWR_REGULATOR_VOLTAGE_SCALE2))
+ {
+ SET_BIT(PWR->VOSR, (PWR_VOSR_USBPWREN | PWR_VOSR_USBBOOSTEN));
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the internal USB HS transceiver supply.
+ * @retval HAL status.
+ */
+void HAL_PWREx_DisableUSBHSTranceiverSupply(void)
+{
+ CLEAR_BIT(PWR->VOSR, (PWR_VOSR_USBPWREN | PWR_VOSR_USBBOOSTEN));
+}
+#endif /* defined (PWR_VOSR_USBPWREN) */
+
+#if defined (PWR_CR1_FORCE_USBPWR)
+/**
+ * @brief Enable OTG_HS PHY power during low power modes (Stop2, Stop3 and Standby).
+ * @retval None.
+ */
+void HAL_PWREx_EnableOTGHSPHYLowPowerRetention(void)
+{
+ /* Set FORCE_USBPWR bit */
+ SET_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR);
+}
+
+/**
+ * @brief Disable OTG_HS PHY power during low power modes (Stop2, Stop3 and Standby).
+ * @retval None.
+ */
+void HAL_PWREx_DisableOTGHSPHYLowPowerRetention(void)
+{
+ /* Clear FORCE_USBPWR bit */
+ CLEAR_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR);
+}
+#endif /* defined (PWR_CR1_FORCE_USBPWR) */
+
+#if defined (PWR_VOSR_VDD11USBDIS)
+/**
+ * @brief Enable the VDD11USB.
+ * @retval None.
+ */
+void HAL_PWREx_EnableVDD11USB(void)
+{
+ /* Clear VDD11USBDIS bit */
+ CLEAR_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS);
+}
+
+/**
+ * @brief Disable the VDD11USB.
+ * @retval None.
+ */
+void HAL_PWREx_DisableVDD11USB(void)
+{
+ /* Set VDD11USBDIS bit */
+ SET_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS);
+}
+#endif /* defined (PWR_VOSR_VDD11USBDIS) */
+
+#ifdef UCPD1
/**
* @brief Enable UCPD configuration memorization in Standby mode.
* @retval None.
@@ -1353,7 +1483,7 @@
/**
* @brief Enable dead battery behavior.
- * @note After exiting reset, the USB Type-C “dead battery” behavior is
+ * @note After exiting reset, the USB Type-C (dead battery) behavior is
* enabled, which may have a pull-down effect on CC1 and CC2 pins.
* It is recommended to disable it in all cases, either to stop this
* pull-down or to handover control to the UCPD (the UCPD must be
@@ -1367,7 +1497,7 @@
/**
* @brief Disable dead battery behavior.
- * @note After exiting reset, the USB Type-C “dead battery” behavior is
+ * @note After exiting reset, the USB Type-C (dead battery) behavior is
* enabled, which may have a pull-down effect on CC1 and CC2 pins.
* It is recommended to disable it in all cases, either to stop this
* pull-down or to handover control to the UCPD (the UCPD must be
@@ -1378,6 +1508,7 @@
{
SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
}
+#endif /* UCPD1 */
/**
* @brief Enable the Battery charging.
@@ -1540,10 +1671,12 @@
(+) Retained content RAMs in Stop modes are :
(++) SRAM1
(++) SRAM2
- (++) SRAM3
+ (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx,
+ STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices)
(++) SRAM4
(++) ICACHE
- (++) DMA2DRAM
+ (++) DMA2DRAM (available only for STM32U575xx, STM32U585xx, STM32U59xxx,
+ STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices)
(++) PKA32RAM
(++) DCACHE
(++) FMAC
@@ -1556,7 +1689,8 @@
(+) Retained content RAMs in Run modes are :
(++) SRAM1
(++) SRAM2
- (++) SRAM3
+ (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx,
+ STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices)
(++) SRAM4
[..]
@@ -1577,9 +1711,9 @@
* Stop 3 and Standby mode and its content is kept.
* @param SRAM2Pages : Specifies the SRAM2 pages.
* This parameter can be one of the following values :
- * @arg PWR_SRAM2_PAGE1_STANDBY_RETENTION : SRAM2 page 1 retention.
- * @arg PWR_SRAM2_PAGE2_STANDBY_RETENTION : SRAM2 page 2 retention.
- * @arg PWR_SRAM2_FULL_STANDBY_RETENTION : SRAM2 page 1 and page 2 retention.
+ * @arg PWR_SRAM2_PAGE1_STANDBY : SRAM2 page 1 retention.
+ * @arg PWR_SRAM2_PAGE2_STANDBY : SRAM2 page 2 retention.
+ * @arg PWR_SRAM2_FULL_STANDBY : SRAM2 page 1 and page 2 retention.
* @retval None.
*/
void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages)
@@ -1597,9 +1731,9 @@
* mode and its content is lost.
* @param SRAM2Pages : Specifies the SRAM2 pages.
* This parameter can be one of the following values :
- * @arg PWR_SRAM2_PAGE1_STANDBY_RETENTION : SRAM2 page 1 retention.
- * @arg PWR_SRAM2_PAGE2_STANDBY_RETENTION : SRAM2 page 2 retention.
- * @arg PWR_SRAM2_FULL_STANDBY_RETENTION : SRAM2 page 1 and page 2 retention.
+ * @arg PWR_SRAM2_PAGE1_STANDBY : SRAM2 page 1 retention.
+ * @arg PWR_SRAM2_PAGE2_STANDBY : SRAM2 page 2 retention.
+ * @arg PWR_SRAM2_FULL_STANDBY : SRAM2 page 1 and page 2 retention.
* @retval None.
*/
void HAL_PWREx_DisableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages)
@@ -1637,6 +1771,12 @@
dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID);
CLEAR_BIT(PWR->CR2, dummy);
+#if defined (PWR_CR4_SRAM1PDS4)
+ /* Calculate pages mask */
+ dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID)) >> 0x03U;
+ CLEAR_BIT(PWR->CR4, dummy);
+#endif /* defined (PWR_CR4_SRAM1PDS4) */
+
break;
}
@@ -1647,12 +1787,13 @@
assert_param(IS_PWR_SRAM2_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
- dummy = (RAMSelection & PWR_SRAM2_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ dummy = (RAMSelection & PWR_SRAM2_FULL_STOP) & ~SRAM_ID_MASK;
CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos));
break;
}
+#if defined (PWR_CR2_SRAM3PDS1)
/* SRAM 3 Stop retention */
case SRAM3_ID:
{
@@ -1664,8 +1805,16 @@
PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID);
CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos));
+#if defined (PWR_CR4_SRAM3PDS9)
+ /* Calculate pages mask */
+ dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID |
+ PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID)) >> 0x08U;
+ CLEAR_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM3PDS9_Pos));
+#endif /* defined (PWR_CR4_SRAM3PDS9) */
+
break;
}
+#endif /* PWR_CR2_SRAM3PDS1 */
/* SRAM 4 Stop retention */
case SRAM4_ID:
@@ -1674,7 +1823,7 @@
assert_param(IS_PWR_SRAM4_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
- dummy = (RAMSelection & PWR_SRAM4_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ dummy = (RAMSelection & PWR_SRAM4_FULL_STOP) & ~SRAM_ID_MASK;
CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM4PDS_Pos));
break;
@@ -1687,7 +1836,7 @@
assert_param(IS_PWR_ICACHE_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
- dummy = (RAMSelection & PWR_ICACHE_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ dummy = (RAMSelection & PWR_ICACHE_FULL_STOP) & ~SRAM_ID_MASK;
CLEAR_BIT(PWR->CR2, dummy << PWR_CR2_ICRAMPDS_Pos);
break;
@@ -1700,12 +1849,13 @@
assert_param(IS_PWR_DCACHE1_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
- dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP) & ~SRAM_ID_MASK;
CLEAR_BIT(PWR->CR2, dummy << PWR_CR2_DC1RAMPDS_Pos);
break;
}
+#if defined (PWR_CR2_DMA2DRAMPDS)
/* DMA2D RAM Stop retention */
case DMA2DRAM_ID:
{
@@ -1713,11 +1863,12 @@
assert_param(IS_PWR_DMA2DRAM_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
- dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP) & ~SRAM_ID_MASK;
CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DMA2DRAMPDS_Pos));
break;
}
+#endif /* PWR_CR2_DMA2DRAMPDS */
/* FMAC, FDCAN and USB RAM Stop retention */
case PERIPHRAM_ID:
@@ -1726,12 +1877,13 @@
assert_param(IS_PWR_PERIPHRAM_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
- dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP) & ~SRAM_ID_MASK;
CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_PRAMPDS_Pos));
break;
}
+#if defined (PWR_CR2_PKARAMPDS)
/* PKA32 RAM Stop retention */
case PKARAM_ID:
{
@@ -1739,11 +1891,102 @@
assert_param(IS_PWR_PKA32RAM_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
- dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP) & ~SRAM_ID_MASK;
CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_PKARAMPDS_Pos));
break;
}
+#endif /* PWR_CR2_PKARAMPDS */
+
+#if defined (PWR_CR2_DC2RAMPDS)
+ /* DCACHE2 RAM Stop retention */
+ case DCACHE2RAM_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_DCACHE2_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_DCACHE2_FULL_STOP) & ~SRAM_ID_MASK;
+ CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DC2RAMPDS_Pos));
+
+ break;
+ }
+#endif /* defined (PWR_CR2_DC2RAMPDS) */
+
+#if defined (PWR_CR2_GPRAMPDS)
+ /* LTDC and GFXMMU RAM Stop retention */
+ case GRAPHIPRAM_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_GRAPHICPRAM_FULL_STOP) & ~SRAM_ID_MASK;
+ CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_GPRAMPDS_Pos));
+
+ break;
+ }
+#endif /* defined (PWR_CR2_GPRAMPDS) */
+
+#if defined (PWR_CR2_DSIRAMPDS)
+ /* DSI RAM Stop retention */
+ case DSIRAM_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_DSIRAM_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_DSIRAM_FULL_STOP) & ~SRAM_ID_MASK;
+ CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DSIRAMPDS_Pos));
+
+ break;
+ }
+#endif /* defined (PWR_CR2_DSIRAMPDS) */
+
+#if defined (PWR_CR2_JPEGRAMPDS)
+ /* JPEG RAM Stop retention */
+ case JPEGRAM_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_JPEGRAM_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_JPEGRAM_FULL_STOP) & ~SRAM_ID_MASK;
+ CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_JPEGRAMPDS_Pos));
+
+ break;
+ }
+#endif /* defined (PWR_CR2_JPEGRAMPDS) */
+
+#if defined (PWR_CR4_SRAM5PDS1)
+ /* SRAM 5 Stop retention */
+ case SRAM5_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_SRAM5_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = ((RAMSelection & PWR_SRAM5_FULL_STOP) & ~SRAM_ID_MASK);
+ CLEAR_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM5PDS1_Pos));
+
+ break;
+ }
+#endif /* defined (PWR_CR4_SRAM5PDS1) */
+
+#if defined (PWR_CR5_SRAM6PDS1)
+ /* SRAM 6 Stop retention */
+ case SRAM6_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_SRAM6_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = ((RAMSelection & PWR_SRAM6_FULL_STOP) & ~SRAM_ID_MASK);
+ CLEAR_BIT(PWR->CR5, (dummy << PWR_CR5_SRAM6PDS1_Pos));
+
+ break;
+ }
+#endif /* defined (PWR_CR5_SRAM6PDS1) */
default:
{
@@ -1778,6 +2021,11 @@
/* Calculate pages mask */
dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID);
SET_BIT(PWR->CR2, dummy);
+#if defined (PWR_CR4_SRAM1PDS4)
+ /* Calculate pages mask */
+ dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID)) >> 0x03U;
+ SET_BIT(PWR->CR4, dummy);
+#endif /* defined (PWR_CR4_SRAM1PDS4) */
break;
}
@@ -1789,12 +2037,13 @@
assert_param(IS_PWR_SRAM2_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
- dummy = (RAMSelection & PWR_SRAM2_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ dummy = (RAMSelection & PWR_SRAM2_FULL_STOP) & ~SRAM_ID_MASK;
SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos));
break;
}
+#if defined (PWR_CR2_SRAM3PDS1)
/* SRAM 3 Stop retention */
case SRAM3_ID:
{
@@ -1806,8 +2055,16 @@
PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID);
SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos));
+#if defined (PWR_CR4_SRAM3PDS9)
+ /* Calculate pages mask */
+ dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID |
+ PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID)) >> 0x08U;
+ SET_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM3PDS9_Pos));
+#endif /* defined (PWR_CR4_SRAM3PDS9) */
+
break;
}
+#endif /* PWR_CR2_SRAM3PDS1 */
/* SRAM 4 Stop retention */
case SRAM4_ID:
@@ -1816,7 +2073,7 @@
assert_param(IS_PWR_SRAM4_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
- dummy = (RAMSelection & PWR_SRAM4_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ dummy = (RAMSelection & PWR_SRAM4_FULL_STOP) & ~SRAM_ID_MASK;
SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM4PDS_Pos));
break;
@@ -1829,7 +2086,7 @@
assert_param(IS_PWR_ICACHE_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
- dummy = (RAMSelection & PWR_ICACHE_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ dummy = (RAMSelection & PWR_ICACHE_FULL_STOP) & ~SRAM_ID_MASK;
SET_BIT(PWR->CR2, (dummy << PWR_CR2_ICRAMPDS_Pos));
break;
@@ -1842,12 +2099,13 @@
assert_param(IS_PWR_DCACHE1_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
- dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP) & ~SRAM_ID_MASK;
SET_BIT(PWR->CR2, (dummy << PWR_CR2_DC1RAMPDS_Pos));
break;
}
+#if defined (PWR_CR2_DMA2DRAMPDS)
/* DMA2D RAM Stop retention */
case DMA2DRAM_ID:
{
@@ -1855,11 +2113,12 @@
assert_param(IS_PWR_DMA2DRAM_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
- dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP) & ~SRAM_ID_MASK;
SET_BIT(PWR->CR2, (dummy << PWR_CR2_DMA2DRAMPDS_Pos));
break;
}
+#endif /* PWR_CR2_DMA2DRAMPDS */
/* FMAC, FDCAN and USB RAM Stop retention */
case PERIPHRAM_ID:
@@ -1868,12 +2127,13 @@
assert_param(IS_PWR_PERIPHRAM_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
- dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP) & ~SRAM_ID_MASK;
SET_BIT(PWR->CR2, (dummy << PWR_CR2_PRAMPDS_Pos));
break;
}
+#if defined (PWR_CR2_PKARAMPDS)
/* PKA32 RAM Stop retention */
case PKARAM_ID:
{
@@ -1881,11 +2141,102 @@
assert_param(IS_PWR_PKA32RAM_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
- dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP) & ~SRAM_ID_MASK;
SET_BIT(PWR->CR2, (dummy << PWR_CR2_PKARAMPDS_Pos));
break;
}
+#endif /* PWR_CR2_PKARAMPDS */
+
+#if defined (PWR_CR2_DC2RAMPDS)
+ /* DCACHE2 RAM Stop retention */
+ case DCACHE2RAM_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_DCACHE2_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_DCACHE2_FULL_STOP) & ~SRAM_ID_MASK;
+ SET_BIT(PWR->CR2, (dummy << PWR_CR2_DC2RAMPDS_Pos));
+
+ break;
+ }
+#endif /* defined (PWR_CR2_DC2RAMPDS) */
+
+#if defined (PWR_CR2_GPRAMPDS)
+ /* LTDC and GFXMMU RAM Stop retention */
+ case GRAPHIPRAM_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_GRAPHICPRAM_FULL_STOP) & ~SRAM_ID_MASK;
+ SET_BIT(PWR->CR2, (dummy << PWR_CR2_GPRAMPDS_Pos));
+
+ break;
+ }
+#endif /* defined (PWR_CR2_GPRAMPDS) */
+
+#if defined (PWR_CR2_DSIRAMPDS)
+ /* DSI RAM Stop retention */
+ case DSIRAM_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_DSIRAM_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_DSIRAM_FULL_STOP) & ~SRAM_ID_MASK;
+ SET_BIT(PWR->CR2, (dummy << PWR_CR2_DSIRAMPDS_Pos));
+
+ break;
+ }
+#endif /* defined (PWR_CR2_DSIRAMPDS) */
+
+#if defined (PWR_CR2_JPEGRAMPDS)
+ /* JPEG RAM Stop retention */
+ case JPEGRAM_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_JPEGRAM_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_JPEGRAM_FULL_STOP) & ~SRAM_ID_MASK;
+ SET_BIT(PWR->CR2, (dummy << PWR_CR2_JPEGRAMPDS_Pos));
+
+ break;
+ }
+#endif /* defined (PWR_CR2_JPEGRAMPDS) */
+
+#if defined (PWR_CR4_SRAM5PDS1)
+ /* SRAM 5 Stop retention */
+ case SRAM5_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_SRAM5_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = ((RAMSelection & PWR_SRAM5_FULL_STOP) & ~SRAM_ID_MASK);
+ SET_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM5PDS1_Pos));
+
+ break;
+ }
+#endif /* defined (PWR_CR4_SRAM5PDS1) */
+
+#if defined (PWR_CR5_SRAM6PDS1)
+ /* SRAM 6 Stop retention */
+ case SRAM6_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_SRAM6_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = ((RAMSelection & PWR_SRAM6_FULL_STOP) & ~SRAM_ID_MASK);
+ SET_BIT(PWR->CR5, (dummy << PWR_CR5_SRAM6PDS1_Pos));
+
+ break;
+ }
+#endif /* defined (PWR_CR5_SRAM6PDS1) */
default:
{
@@ -1899,10 +2250,17 @@
* @brief Enable RAMs full content retention in Run mode.
* @param RAMSelection : Specifies the SRAM content to be retained in Run mode.
* This parameter can be one or a combination of the following values :
- * @arg PWR_SRAM1_FULL_RUN_RETENTION : SRAM1 full content retention.
- * @arg PWR_SRAM2_FULL_RUN_RETENTION : SRAM2 full content retention.
- * @arg PWR_SRAM3_FULL_RUN_RETENTION : SRAM3 full content retention.
- * @arg PWR_SRAM4_FULL_RUN_RETENTION : SRAM4 full content retention.
+ * @arg PWR_SRAM1_FULL_RUN : SRAM1 full content retention.
+ * @arg PWR_SRAM2_FULL_RUN : SRAM2 full content retention.
+ * @arg PWR_SRAM3_FULL_RUN : SRAM3 full content retention (available only for STM32U575xx,
+ * STM32U585xx STM32U59xxx, STM32U5Axxx, STM32U5Fxxx
+ and STM32U5Gxxx devices).
+ * @arg PWR_SRAM4_FULL_RUN : SRAM4 full content retention.
+ * @arg PWR_SRAM5_FULL_RUN : SRAM5 full content retention (available only for
+ * STM32U59xxx, STM32U5Axxx, STM32U5Fxxx
+ * and STM32U5Gxxx devices).
+ * @arg PWR_SRAM6_FULL_RUN : SRAM6 full content retention (available only for
+ * STM32U5Fxxx and STM32U5Gxxx devices).
* @retval None.
*/
void HAL_PWREx_EnableRAMsContentRunRetention(uint32_t RAMSelection)
@@ -1918,10 +2276,17 @@
* @brief Disable RAMs full content retention in Run mode.
* @param RAMSelection : Specifies the SRAM content to be lost in Run mode.
* This parameter can be one or a combination of the following values :
- * @arg PWR_SRAM1_FULL_RUN_RETENTION : SRAM1 full content lost.
- * @arg PWR_SRAM2_FULL_RUN_RETENTION : SRAM2 full content lost.
- * @arg PWR_SRAM3_FULL_RUN_RETENTION : SRAM3 full content lost.
- * @arg PWR_SRAM4_FULL_RUN_RETENTION : SRAM4 full content lost.
+ * @arg PWR_SRAM1_FULL_RUN : SRAM1 full content lost.
+ * @arg PWR_SRAM2_FULL_RUN : SRAM2 full content lost.
+ * @arg PWR_SRAM3_FULL_RUN : SRAM3 full content lost (available only for STM32U575xx,
+ * STM32U585xx STM32U59xxx, STM32U5Axxx, STM32U5Fxxx
+ and STM32U5Gxxx devices).
+ * @arg PWR_SRAM4_FULL_RUN : SRAM4 full content lost.
+ * @arg PWR_SRAM5_FULL_RUN : SRAM5 full content retention (available only for
+ * STM32U59xxx, STM32U5Axxx, STM32U5Fxxx
+ * and STM32U5Gxxx devices).
+ * @arg PWR_SRAM6_FULL_RUN : SRAM6 full content retention (available only for
+ * STM32U5Fxxx and STM32U5Gxxx devices).
* @retval None.
*/
void HAL_PWREx_DisableRAMsContentRunRetention(uint32_t RAMSelection)
@@ -2035,15 +2400,17 @@
*
@verbatim
===============================================================================
- ##### Voltage monitoring Functions #####
+ ##### I/O Pull-Up Pull-Down Configuration Functions #####
===============================================================================
[..]
In Standby and Shutdown mode, pull up and pull down can be configured to
maintain an I/O in the selected state. If the APC bit in the PWR_APCR
register is set, the I/Os can be configured either with a pull-up through
- PWR_PUCRx registers (x=A,B,C,D,E,F,G,H,I), or with a pull-down through
- PWR_PDCRx registers (x=A,B,C,D,E,F,G,H,I)), or can be kept in analog state
+ PWR_PUCRx registers (x=A,B,C,D,E,F,G,H,I,J), or with a pull-down through
+ PWR_PDCRx registers (x=A,B,C,D,E,F,G,H,I,J)), or can be kept in analog state
if none of the PWR_PUCRx or PWR_PDCRx register is set.
+ (+) Port J is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx
+ and STM32U5Gxxx devices.
[..]
The pull-down configuration has highest priority over pull-up
@@ -2140,10 +2507,12 @@
CLEAR_BIT(PWR->PDCRE, GPIO_Pin);
break;
+#ifdef PWR_PUCRF_PU0
case PWR_GPIO_F: /* Apply Pull Up to GPIO port F */
SET_BIT(PWR->PUCRF, GPIO_Pin);
CLEAR_BIT(PWR->PDCRF, GPIO_Pin);
break;
+#endif /* PWR_PUCRF_PU0 */
case PWR_GPIO_G: /* Apply Pull Up to GPIO port G */
SET_BIT(PWR->PUCRG, GPIO_Pin);
@@ -2155,10 +2524,19 @@
CLEAR_BIT(PWR->PDCRH, GPIO_Pin);
break;
+#ifdef PWR_PUCRI_PU0
case PWR_GPIO_I: /* Apply Pull Up to GPIO port I */
SET_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
CLEAR_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
break;
+#endif /* PWR_PUCRI_PU0 */
+
+#if defined (PWR_PUCRJ_PU0)
+ case PWR_GPIO_J: /* Apply Pull Up to GPIO port J */
+ SET_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS));
+ CLEAR_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS));
+ break;
+#endif /* defined (PWR_PUCRJ_PU0) */
default:
return HAL_ERROR;
@@ -2211,9 +2589,11 @@
CLEAR_BIT(PWR->PUCRE, GPIO_Pin);
break;
+#ifdef PWR_PUCRF_PU0
case PWR_GPIO_F: /* Disable Pull Up for GPIO port F */
CLEAR_BIT(PWR->PUCRF, GPIO_Pin);
break;
+#endif /* PWR_PUCRF_PU0 */
case PWR_GPIO_G: /* Disable Pull Up for GPIO port G */
CLEAR_BIT(PWR->PUCRG, GPIO_Pin);
@@ -2223,9 +2603,17 @@
CLEAR_BIT(PWR->PUCRH, GPIO_Pin);
break;
+#ifdef PWR_PUCRI_PU0
case PWR_GPIO_I: /* Disable Pull Up for GPIO port I */
CLEAR_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
break;
+#endif /* PWR_PUCRI_PU0 */
+
+#if defined (PWR_PUCRJ_PU0)
+ case PWR_GPIO_J: /* Disable Pull Up for GPIO port J */
+ CLEAR_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS));
+ break;
+#endif /* defined (PWR_PUCRJ_PU0) */
default:
return HAL_ERROR;
@@ -2290,10 +2678,12 @@
CLEAR_BIT(PWR->PUCRE, GPIO_Pin);
break;
+#ifdef PWR_PUCRF_PU0
case PWR_GPIO_F: /* Apply Pull Down to GPIO port F */
SET_BIT(PWR->PDCRF, GPIO_Pin);
CLEAR_BIT(PWR->PUCRF, GPIO_Pin);
break;
+#endif /* PWR_PUCRF_PU0 */
case PWR_GPIO_G: /* Apply Pull Down to GPIO port G */
SET_BIT(PWR->PDCRG, GPIO_Pin);
@@ -2305,10 +2695,19 @@
CLEAR_BIT(PWR->PUCRH, GPIO_Pin);
break;
+#ifdef PWR_PUCRI_PU0
case PWR_GPIO_I: /* Apply Pull Down to GPIO port I */
SET_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
CLEAR_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
break;
+#endif /* PWR_PUCRI_PU0 */
+
+#if defined (PWR_PUCRJ_PU0)
+ case PWR_GPIO_J: /* Apply Pull Down to GPIO port J */
+ SET_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS));
+ CLEAR_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS));
+ break;
+#endif /* defined (PWR_PUCRJ_PU0) */
default:
return HAL_ERROR;
@@ -2361,9 +2760,11 @@
CLEAR_BIT(PWR->PDCRE, GPIO_Pin);
break;
+#ifdef PWR_PUCRF_PU0
case PWR_GPIO_F: /* Disable Pull Down for GPIO port F */
CLEAR_BIT(PWR->PDCRF, GPIO_Pin);
break;
+#endif /* PWR_PUCRF_PU0 */
case PWR_GPIO_G: /* Disable Pull Down for GPIO port G */
CLEAR_BIT(PWR->PDCRG, GPIO_Pin);
@@ -2373,9 +2774,17 @@
CLEAR_BIT(PWR->PDCRH, GPIO_Pin);
break;
+#ifdef PWR_PUCRI_PU0
case PWR_GPIO_I: /* Disable Pull Down for GPIO port I */
CLEAR_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
break;
+#endif /* PWR_PUCRI_PU0 */
+
+#if defined (PWR_PUCRJ_PU0)
+ case PWR_GPIO_J: /* Disable Pull Down for GPIO port J */
+ CLEAR_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS));
+ break;
+#endif /* defined (PWR_PUCRJ_PU0) */
default:
return HAL_ERROR;
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc.c
index 0c6d5db..edff155 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc.c
@@ -11,7 +11,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -44,7 +44,7 @@
(+) Configure the AHB and APB busses prescalers
(+) Enable the clock for the peripheral(s) to be used
(+) Configure the clock source(s) for peripherals which clocks are not
- derived from the System clock (SAIx, SYSTICK, RTC, ADC, USB OTG FS/SDMMC1/RNG)
+ derived from the System clock (SAIx, SYSTICK, RTC, ADC, USB OTG FS/USB FS/SDMMC1/RNG)
@endverbatim
******************************************************************************
@@ -70,6 +70,7 @@
* @{
*/
#define PLLDIVR_RESET_VALUE (0x01010280U)
+#define PLL_FRAC_WAIT_VALUE 1U /* PLL Fractional part waiting time before new latch enable : 1 ms */
/**
* @}
*/
@@ -84,6 +85,7 @@
((__HSE__) == RCC_HSE_BYPASS) || ((__HSE__) == RCC_HSE_BYPASS_DIGITAL))
#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
+ ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \
((__LSE__) == RCC_LSE_BYPASS))
#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
@@ -125,7 +127,7 @@
#define IS_RCC_PLLRGE_VALUE(VALUE) (((VALUE) == RCC_PLLVCIRANGE_0) || \
((VALUE) == RCC_PLLVCIRANGE_1))
-#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <= 8191U)
+#define IS_RCC_PLL_FRACN_VALUE(VALUE) ((VALUE) <= 8191U)
#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x1FU))
@@ -184,7 +186,8 @@
/** @defgroup RCC_Private_Constants RCC Private Constants
* @{
*/
-#define LSI_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
+#define LSI_TIMEOUT_VALUE 5UL /* 5 ms (LSI maximum timeout is LSI startup time + LSI_VALUE/128 when
+ LSI prediv is used) */
#define HSI48_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
#define SHSI_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
#define MSIK_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
@@ -246,7 +249,7 @@
the PLL as System clock source.
(+) MSI (Multiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.
- It can be used to generate the clock for the USB OTG FS (48 MHz).
+ It can be used to generate the clock for the USB FS or USB OTG FS (48 MHz).
The number of flash wait states is automatically adjusted when MSI range is updated with
HAL_RCC_OscConfig() and the MSI is used as System clock source.
@@ -260,14 +263,14 @@
(+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
(++) The first output is used to generate the high speed system clock (up to 80MHz).
- (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
+ (++) The second output is used to generate the clock for the USB FS or USB OTG FS (48 MHz),
the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
(++) The third output is used to generate an accurate clock to achieve
high-quality audio performance on SAI interface.
(+) PLL2 (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
(++) The first output is used to generate SAR ADC1 clock.
- (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
+ (++) The second output is used to generate the clock for the USB Fs or USB OTG FS (48 MHz),
the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
(++) The Third output is used to generate an accurate clock to achieve
high-quality audio performance on SAI interface.
@@ -305,7 +308,7 @@
divided by 2 to 31.
You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
to configure this clock.
- (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz
+ (+@) USB FS, USB OTG FS, SDMMC1 and RNG: USB OTG FS or USB FS requires a frequency equal to 48 MHz
to work correctly, while the SDMMC1 and RNG peripherals require a frequency
equal or lower than to 48 MHz. This clock is derived of the main PLL or PLL2
through PLLQ divider. You have to enable the peripheral clock and use
@@ -354,6 +357,7 @@
* - LSI, LSE and RTC clocks
* @retval HAL status
*/
+
HAL_StatusTypeDef HAL_RCC_DeInit(void)
{
uint32_t tickstart;
@@ -370,6 +374,7 @@
{
return HAL_ERROR;
}
+
}
tickstart = HAL_GetTick();
@@ -535,13 +540,15 @@
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct)
+HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruct)
{
uint32_t tickstart;
HAL_StatusTypeDef status;
uint32_t sysclk_source;
uint32_t pll_config;
FlagStatus pwrboosten = RESET;
+ uint32_t temp1_pllckcfg;
+ uint32_t temp2_pllckcfg;
/* Check Null pointer */
if (pRCC_OscInitStruct == NULL)
@@ -568,7 +575,7 @@
if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) ||
((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI)))
{
- if ((READ_BIT(RCC->CR, RCC_CR_MSISRDY) != 0U) && (pRCC_OscInitStruct->MSIState == RCC_MSI_OFF))
+ if (pRCC_OscInitStruct->MSIState == RCC_MSI_OFF)
{
return HAL_ERROR;
}
@@ -581,10 +588,14 @@
(HCLK) and the supply voltage of the device */
if (pRCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
{
- /* First increase number of wait states update if necessary */
- if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK)
+ /* Decrease number of wait states update if necessary */
+ /* Only possible when MSI is the System clock source */
+ if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI)
{
- return HAL_ERROR;
+ if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
}
/* Selects the Multiple Speed oscillator (MSI) clock range */
@@ -602,10 +613,12 @@
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \
(pRCC_OscInitStruct->MSIClockRange));
- /* Decrease number of wait states update if necessary */
- if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK)
+ if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI)
{
- return HAL_ERROR;
+ if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
}
}
@@ -672,7 +685,7 @@
if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) ||
((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
{
- if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (pRCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ if (pRCC_OscInitStruct->HSEState == RCC_HSE_OFF)
{
return HAL_ERROR;
}
@@ -723,7 +736,7 @@
((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
{
/* When HSI is used as system clock it will not be disabled */
- if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (pRCC_OscInitStruct->HSIState == RCC_HSI_OFF))
+ if (pRCC_OscInitStruct->HSIState == RCC_HSI_OFF)
{
return HAL_ERROR;
}
@@ -1149,6 +1162,8 @@
if ((pRCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
{
+ FlagStatus pwrclkchanged = RESET;
+
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
@@ -1168,7 +1183,7 @@
tickstart = HAL_GetTick();
- /* Wait till PLL is ready */
+ /* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
@@ -1177,8 +1192,12 @@
}
}
- /* Enable PWR CLK */
- __HAL_RCC_PWR_CLK_ENABLE();
+ /* Requires to enable write access to Backup Domain of necessary */
+ if (__HAL_RCC_PWR_IS_CLK_DISABLED())
+ {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
/*Disable EPOD to configure PLL1MBOOST*/
if (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) == PWR_VOSR_BOOSTEN)
@@ -1196,16 +1215,16 @@
pRCC_OscInitStruct->PLL.PLLQ,
pRCC_OscInitStruct->PLL.PLLR);
- assert_param(IS_RCC_PLLFRACN_VALUE(pRCC_OscInitStruct->PLL.PLLFRACN));
+ assert_param(IS_RCC_PLL_FRACN_VALUE(pRCC_OscInitStruct->PLL.PLLFRACN));
/* Disable PLL1FRACN */
- __HAL_RCC_PLLFRACN_DISABLE();
+ __HAL_RCC_PLL_FRACN_DISABLE();
/* Configure PLL PLL1FRACN */
- __HAL_RCC_PLLFRACN_CONFIG(pRCC_OscInitStruct->PLL.PLLFRACN);
+ __HAL_RCC_PLL_FRACN_CONFIG(pRCC_OscInitStruct->PLL.PLLFRACN);
/* Enable PLL1FRACN */
- __HAL_RCC_PLLFRACN_ENABLE();
+ __HAL_RCC_PLL_FRACN_ENABLE();
assert_param(IS_RCC_PLLRGE_VALUE(pRCC_OscInitStruct->PLL.PLLRGE));
@@ -1218,8 +1237,11 @@
SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN);
}
- /*Disable PWR clk */
- __HAL_RCC_PWR_CLK_DISABLE();
+ /* Restore clock configuration if changed */
+ if (pwrclkchanged == SET)
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
/* Enable PLL System Clock output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
@@ -1243,9 +1265,6 @@
/* Disable the main PLL */
__HAL_RCC_PLL_DISABLE();
- /* Disable main PLL outputs to save power if no PLLs on */
- __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL1_DIVP | RCC_PLL1_DIVQ | RCC_PLL1_DIVR);
-
tickstart = HAL_GetTick();
/* Wait till PLL is disabled */
@@ -1256,11 +1275,57 @@
return HAL_TIMEOUT;
}
}
+
+ /* Unselect main PLL clock source and disable main PLL outputs to save power */
+ RCC->PLL1CFGR &= ~(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1PEN | RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CFGR_PLL1REN);
+
}
}
else
{
- return HAL_ERROR;
+ /* Do not return HAL_ERROR if request repeats the current configuration */
+ temp1_pllckcfg = RCC->PLL1CFGR;
+ temp2_pllckcfg = RCC->PLL1DIVR;
+ if (((pRCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+ (READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1SRC) != pRCC_OscInitStruct->PLL.PLLSource) ||
+ ((READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1M) >> \
+ RCC_PLL1CFGR_PLL1M_Pos) != (pRCC_OscInitStruct->PLL.PLLM - 1U)) ||
+ (READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1MBOOST) != pRCC_OscInitStruct->PLL.PLLMBOOST) ||
+ (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1N) != (pRCC_OscInitStruct->PLL.PLLN - 1U)) ||
+ ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1P) >> \
+ RCC_PLL1DIVR_PLL1P_Pos) != (pRCC_OscInitStruct->PLL.PLLP - 1U)) ||
+ ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1Q) >> \
+ RCC_PLL1DIVR_PLL1Q_Pos) != (pRCC_OscInitStruct->PLL.PLLQ - 1U)) ||
+ ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1R) >> \
+ RCC_PLL1DIVR_PLL1R_Pos) != (pRCC_OscInitStruct->PLL.PLLR - 1U)))
+ {
+ return HAL_ERROR;
+ }
+
+ /* FRACN1 on-the-fly value update */
+ if ((READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> \
+ RCC_PLL1FRACR_PLL1FRACN_Pos) != (pRCC_OscInitStruct->PLL.PLLFRACN))
+ {
+ assert_param(IS_RCC_PLL_FRACN_VALUE(pRCC_OscInitStruct->PLL.PLLFRACN));
+
+ /* Disable PLL1FRACN. */
+ __HAL_RCC_PLL_FRACN_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait at least 2 CK_REF (PLL1 input source divided by M) period to make sure next latched value
+ will be taken into account. */
+ while ((HAL_GetTick() - tickstart) < PLL_FRAC_WAIT_VALUE)
+ {
+ }
+
+ /* Configure PLL PLL1FRACN */
+ __HAL_RCC_PLL_FRACN_CONFIG(pRCC_OscInitStruct->PLL.PLLFRACN);
+
+ /* Enable PLL1FRACN to latch the new value. */
+ __HAL_RCC_PLL_FRACN_ENABLE();
+ }
}
}
return HAL_OK;
@@ -1334,15 +1399,60 @@
}
}
+ /* Increasing the BUS frequency divider */
+ /*-------------------------- PCLK3 Configuration ---------------------------*/
+ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3)
+ {
+ if ((pRCC_ClkInitStruct->APB3CLKDivider) > (RCC->CFGR3 & RCC_CFGR3_PPRE3))
+ {
+ assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB3CLKDivider));
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, pRCC_ClkInitStruct->APB3CLKDivider);
+ }
+ }
+ /*-------------------------- PCLK2 Configuration ---------------------------*/
+ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ {
+ if ((pRCC_ClkInitStruct->APB2CLKDivider) > ((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4))
+ {
+ assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB2CLKDivider));
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4));
+ }
+ }
+
+ /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ if ((pRCC_ClkInitStruct->APB1CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE1))
+ {
+ assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB1CLKDivider));
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider);
+ }
+ }
+
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ if ((pRCC_ClkInitStruct->AHBCLKDivider) > (RCC->CFGR2 & RCC_CFGR2_HPRE))
+ {
+ assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider);
+ }
+ }
+
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
{
assert_param(IS_RCC_SYSCLKSOURCE(pRCC_ClkInitStruct->SYSCLKSource));
+ FlagStatus pwrclkchanged = RESET;
/* PLL is selected as System Clock Source */
if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
- __HAL_RCC_PWR_CLK_ENABLE();
+ if (__HAL_RCC_PWR_IS_CLK_DISABLED())
+ {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
tickstart = HAL_GetTick();
/* Check if EPOD is enabled */
if (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) != 0U)
@@ -1357,7 +1467,11 @@
}
}
- __HAL_RCC_PWR_CLK_DISABLE();
+ /* Restore clock configuration if changed */
+ if (pwrclkchanged == SET)
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
/* Check the PLL ready flag */
if (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U)
@@ -1445,32 +1559,15 @@
}
}
+ /* Decreasing the BUS frequency divider */
/*-------------------------- HCLK Configuration --------------------------*/
if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
- assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider);
- }
-
- /*-------------------------- PCLK1 Configuration ---------------------------*/
- if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- {
- assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB1CLKDivider));
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider);
- }
-
- /*-------------------------- PCLK2 Configuration ---------------------------*/
- if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- {
- assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB2CLKDivider));
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4));
- }
-
- /*-------------------------- PCLK3 Configuration ---------------------------*/
- if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3)
- {
- assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB3CLKDivider));
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, pRCC_ClkInitStruct->APB3CLKDivider);
+ if ((pRCC_ClkInitStruct->AHBCLKDivider) < (RCC->CFGR2 & RCC_CFGR2_HPRE))
+ {
+ assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider);
+ }
}
/* Decreasing the number of wait states because of lower CPU frequency */
@@ -1487,6 +1584,36 @@
}
}
+ /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ if ((pRCC_ClkInitStruct->APB1CLKDivider) < (RCC->CFGR2 & RCC_CFGR2_PPRE1))
+ {
+ assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB1CLKDivider));
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider);
+ }
+ }
+
+ /*-------------------------- PCLK2 Configuration ---------------------------*/
+ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ {
+ if ((pRCC_ClkInitStruct->APB2CLKDivider) < ((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4))
+ {
+ assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB2CLKDivider));
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4));
+ }
+ }
+
+ /*-------------------------- PCLK3 Configuration ---------------------------*/
+ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3)
+ {
+ if ((pRCC_ClkInitStruct->APB3CLKDivider) < (RCC->CFGR3 & RCC_CFGR3_PPRE3))
+ {
+ assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB3CLKDivider));
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, (pRCC_ClkInitStruct->APB3CLKDivider));
+ }
+ }
+
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos];
@@ -1530,7 +1657,7 @@
* @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLL1CLK main PLL clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
@@ -1661,34 +1788,27 @@
fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \
RCC_PLL1FRACR_PLL1FRACN_Pos));
- if (pllm != 0U)
+ switch (pllsource)
{
- switch (pllsource)
- {
- case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
- pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
- (fracn1 / (float_t)0x2000) + (float_t)1U);
- break;
+ case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
+ (fracn1 / (float_t)0x2000) + (float_t)1U);
+ break;
- case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
- pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
- (fracn1 / (float_t)0x2000) + (float_t)1U);
- break;
+ case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
+ (fracn1 / (float_t)0x2000) + (float_t)1U);
+ break;
- case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
- default:
- pllvco = ((float_t) msirange / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
- (fracn1 / (float_t)0x2000) + (float_t)1U);
- break;
- }
-
- pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U);
- sysclockfreq = (uint32_t)(float_t)((float_t)pllvco / (float_t)pllr);
+ case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
+ default:
+ pllvco = ((float_t) msirange / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
+ (fracn1 / (float_t)0x2000) + (float_t)1U);
+ break;
}
- else
- {
- sysclockfreq = 0;
- }
+
+ pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U);
+ sysclockfreq = (uint32_t)(float_t)((float_t)pllvco / (float_t)pllr);
}
return sysclockfreq;
@@ -1752,6 +1872,10 @@
*/
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct)
{
+ uint32_t regval;
+ uint32_t reg1val;
+ uint32_t reg2val;
+
/* Check the parameters */
assert_param(pRCC_OscInitStruct != (void *)NULL);
@@ -1759,104 +1883,62 @@
pRCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;
+ /* Get Control register */
+ regval = RCC->CR;
+
/* Get the HSE configuration -----------------------------------------------*/
- if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP)
- {
- pRCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
- }
- else if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT))
- {
- pRCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL;
- }
- else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
- {
- pRCC_OscInitStruct->HSEState = RCC_HSE_ON;
- }
- else
- {
- pRCC_OscInitStruct->HSEState = RCC_HSE_OFF;
- }
+ pRCC_OscInitStruct->HSEState = (regval & (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_HSEEXT));
/* Get the MSI configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_MSISON) == RCC_CR_MSISON)
- {
- pRCC_OscInitStruct->MSIState = RCC_MSI_ON;
- }
- else
- {
- pRCC_OscInitStruct->MSIState = RCC_MSI_OFF;
- }
+ pRCC_OscInitStruct->MSIState = regval & RCC_CR_MSISON;
- pRCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->CR & RCC_ICSCR1_MSISRANGE));
+ reg1val = RCC->ICSCR1;
+ reg2val = RCC->ICSCR2;
+
+ pRCC_OscInitStruct->MSIClockRange = (uint32_t)((reg1val & RCC_ICSCR1_MSISRANGE));
if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_12)
{
- pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM3) >> \
+ pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM3) >> \
RCC_ICSCR2_MSITRIM3_Pos);
}
else if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_8)
{
- pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM2) >> \
+ pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM2) >> \
RCC_ICSCR2_MSITRIM2_Pos);
}
else if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_4)
{
- pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM1) >> \
+ pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM1) >> \
RCC_ICSCR2_MSITRIM1_Pos);
}
else /*if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_0)*/
{
- pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM0) >> \
+ pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM0) >> \
RCC_ICSCR2_MSITRIM0_Pos);
}
- /* Get the HSI configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
- {
- pRCC_OscInitStruct->HSIState = RCC_HSI_ON;
- }
- else
- {
- pRCC_OscInitStruct->HSIState = RCC_HSI_OFF;
- }
+ /* Get the HSI configuration -----------------------------------------------*/
+ pRCC_OscInitStruct->HSIState = regval & RCC_CR_HSION;
pRCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR3 & RCC_ICSCR3_HSITRIM) >> RCC_ICSCR3_HSITRIM_Pos);
+ /* Get BDCR register */
+ regval = RCC->BDCR;
+
/* Get the LSE configuration -----------------------------------------------*/
- if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
- {
- pRCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
- }
- else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
- {
- pRCC_OscInitStruct->LSEState = RCC_LSE_ON;
- }
- else
- {
- pRCC_OscInitStruct->LSEState = RCC_LSE_OFF;
- }
+ pRCC_OscInitStruct->LSEState = (regval & (RCC_BDCR_LSEON | RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN));
/* Get the LSI configuration -----------------------------------------------*/
- if ((RCC->BDCR & RCC_BDCR_LSION) == RCC_BDCR_LSION)
- {
- pRCC_OscInitStruct->LSIState = RCC_LSI_ON;
- }
- else
- {
- pRCC_OscInitStruct->LSIState = RCC_LSI_OFF;
- }
+ pRCC_OscInitStruct->LSIState = regval & RCC_BDCR_LSION;
+
+ /* Get Control register */
+ regval = RCC->CR;
/* Get the HSI48 configuration ---------------------------------------------*/
- if ((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON)
- {
- pRCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
- }
- else
- {
- pRCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
- }
+ pRCC_OscInitStruct->HSI48State = regval & RCC_CR_HSI48ON;
/* Get the PLL configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_PLL1ON) == RCC_CR_PLL1ON)
+ if ((regval & RCC_CR_PLL1ON) == RCC_CR_PLL1ON)
{
pRCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
}
@@ -1864,17 +1946,21 @@
{
pRCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
}
- pRCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
- pRCC_OscInitStruct->PLL.PLLM = (uint32_t)(((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U);
- pRCC_OscInitStruct->PLL.PLLN = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1U);
- pRCC_OscInitStruct->PLL.PLLQ = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1U);
- pRCC_OscInitStruct->PLL.PLLR = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U);
- pRCC_OscInitStruct->PLL.PLLP = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U);
- pRCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1RGE));
+
+ reg1val = RCC->PLL1CFGR;
+ reg2val = RCC->PLL1DIVR;
+
+ pRCC_OscInitStruct->PLL.PLLSource = (uint32_t)(reg1val & RCC_PLL1CFGR_PLL1SRC);
+ pRCC_OscInitStruct->PLL.PLLM = (uint32_t)(((reg1val & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U);
+ pRCC_OscInitStruct->PLL.PLLN = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1U);
+ pRCC_OscInitStruct->PLL.PLLQ = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1U);
+ pRCC_OscInitStruct->PLL.PLLR = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U);
+ pRCC_OscInitStruct->PLL.PLLP = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U);
+ pRCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((reg1val & RCC_PLL1CFGR_PLL1RGE));
pRCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \
RCC_PLL1FRACR_PLL1FRACN_Pos));
- pRCC_OscInitStruct->PLL.PLLMBOOST = (uint32_t)(((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1MBOOST) >> \
- RCC_PLL1CFGR_PLL1MBOOST_Pos) + 1U);
+ pRCC_OscInitStruct->PLL.PLLMBOOST = (uint32_t)(((reg1val & RCC_PLL1CFGR_PLL1MBOOST) >> \
+ RCC_PLL1CFGR_PLL1MBOOST_Pos));
}
/**
@@ -2153,7 +2239,6 @@
else
{
if (msirange > RCC_MSIRANGE_2)
-
{
if (vos == PWR_REGULATOR_VOLTAGE_SCALE4)
{
@@ -2174,7 +2259,6 @@
else
{
if (msirange == RCC_MSIRANGE_1)
-
{
if (vos == PWR_REGULATOR_VOLTAGE_SCALE3)
{
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc_ex.c
index f28c27f..ab25e15 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc_ex.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rcc_ex.c
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -46,11 +46,15 @@
#define PLL2_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
#define PLL3_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
-#define LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
+/* Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. */
+#if defined (STM32U585xx) || defined (STM32U575xx)
+#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM23 /*!< External interrupt line 23 connected to the LSE CSS interrupt Line */
+#else
+#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM24 /*!< External interrupt line 24 connected to the LSE CSS interrupt Line */
+#endif /* STM32U585xx || STM32U575xx */
-#define LSCO_GPIO_PORT GPIOA
-
-#define LSCO_PIN GPIO_PIN_2
+/* Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. */
+#define RCC_EXTI_LINE_MSIPLLUNLCK EXTI_IMR1_IM23 /*!< External interrupt line 23 connected to the MSI PLL UNLOCK interrupt Line */
/**
* @}
@@ -80,11 +84,13 @@
((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \
((__SOURCE__) == RCC_USART1CLKSOURCE_LSE))
+#if defined(USART2)
#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \
((__SOURCE__) == RCC_USART2CLKSOURCE_LSE))
+#endif /* USART2 */
#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
@@ -104,6 +110,14 @@
((__SOURCE__) == RCC_UART5CLKSOURCE_HSI) || \
((__SOURCE__) == RCC_UART5CLKSOURCE_LSE))
+#if defined(USART6)
+#define IS_RCC_USART6CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_USART6CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_USART6CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART6CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_USART6CLKSOURCE_LSE))
+#endif /* USART6 */
+
#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK3) || \
((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
@@ -135,6 +149,22 @@
((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)|| \
((__SOURCE__) == RCC_I2C4CLKSOURCE_MSIK))
+#if defined(I2C5)
+#define IS_RCC_I2C5CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_I2C5CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_I2C5CLKSOURCE_SYSCLK)|| \
+ ((__SOURCE__) == RCC_I2C5CLKSOURCE_HSI)|| \
+ ((__SOURCE__) == RCC_I2C5CLKSOURCE_MSIK))
+#endif /* I2C5 */
+
+#if defined(I2C6)
+#define IS_RCC_I2C6CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_I2C6CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_I2C6CLKSOURCE_SYSCLK)|| \
+ ((__SOURCE__) == RCC_I2C6CLKSOURCE_HSI)|| \
+ ((__SOURCE__) == RCC_I2C6CLKSOURCE_MSIK))
+#endif /* I2C6 */
+
#define IS_RCC_SAI1CLK(__SOURCE__) \
(((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \
((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \
@@ -142,12 +172,14 @@
((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \
((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))
+#if defined(SAI2)
#define IS_RCC_SAI2CLK(__SOURCE__) \
(((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \
((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \
((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL1) || \
((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \
((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI))
+#endif /* SAI2 */
#define IS_RCC_LPTIM1CLK(__SOURCE__) \
(((__SOURCE__) == RCC_LPTIM1CLKSOURCE_MSIK) || \
@@ -181,9 +213,11 @@
((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48_DIV2) || \
((__SOURCE__) == RCC_RNGCLKSOURCE_HSI))
+#if defined(SAES)
#define IS_RCC_SAESCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_SAESCLKSOURCE_SHSI) || \
((__SOURCE__) == RCC_SAESCLKSOURCE_SHSI_DIV2))
+#endif /* SAES */
#define IS_RCC_ADCDACCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_ADCDACCLKSOURCE_HCLK) || \
@@ -213,11 +247,19 @@
((__SOURCE__) == RCC_OSPICLKSOURCE_PLL1) ||\
((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2))
-#define IS_RCC_CLK48CLKSOURCE(__SOURCE__)\
- (((__SOURCE__) == RCC_CLK48CLKSOURCE_HSI48)|| \
- ((__SOURCE__) == RCC_CLK48CLKSOURCE_PLL2) || \
- ((__SOURCE__) == RCC_CLK48CLKSOURCE_PLL1) || \
- ((__SOURCE__) == RCC_CLK48CLKSOURCE_MSIK))
+#if defined(HSPI1)
+#define IS_RCC_HSPICLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_HSPICLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL1) || \
+ ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL2) || \
+ ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL3))
+#endif /* HSPI1 */
+
+#define IS_RCC_ICLKCLKSOURCE(__SOURCE__)\
+ (((__SOURCE__) == RCC_ICLK_CLKSOURCE_HSI48)|| \
+ ((__SOURCE__) == RCC_ICLK_CLKSOURCE_PLL2) || \
+ ((__SOURCE__) == RCC_ICLK_CLKSOURCE_PLL1) || \
+ ((__SOURCE__) == RCC_ICLK_CLKSOURCE_MSIK))
#define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_SPI1CLKSOURCE_PCLK2) || \
@@ -245,6 +287,33 @@
((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
+
+#if defined(LTDC)
+
+#define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLL3) || \
+ ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLL2))
+
+#endif /* LTDC */
+
+#if defined(DSI)
+
+#define IS_RCC_DSICLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_DSICLKSOURCE_PLL3) || \
+ ((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY))
+
+#endif /* DSI */
+
+#if defined(USB_OTG_HS)
+
+#define IS_RCC_USBPHYCLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_USBPHYCLKSOURCE_HSE) || \
+ ((__SOURCE__) == RCC_USBPHYCLKSOURCE_HSE_DIV2) || \
+ ((__SOURCE__) == RCC_USBPHYCLKSOURCE_PLL1) || \
+ ((__SOURCE__) == RCC_USBPHYCLKSOURCE_PLL1_DIV2))
+
+#endif /* USB_OTG_HS */
+
#if defined(CRS)
#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
@@ -270,14 +339,18 @@
#endif /* CRS */
+/**
+ * @}
+ */
+
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup RCCEx_Private_Functions RCCEx Private Functions
* @{
*/
static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource);
-static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *Pll2);
-static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *Pll3);
+static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *Pll2);
+static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *Pll3);
/**
* @}
*/
@@ -317,36 +390,45 @@
* @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
* @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
* @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock
* @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C5 I2C5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C6 I2C6 peripheral clock
* @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock
* @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock (*)
* @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
* @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1,ADC4,DAC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1 ADC2 ADC4 DAC1 peripheral clock
* @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock
* @arg @ref RCC_PERIPHCLK_ADF1 ADF1 peripheral clock
* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
* @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
- * @arg @ref RCC_PERIPHCLK_CLK48 CLK48 peripheral clock
- * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ICLK ICLK peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC1 peripheral clock
* @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock
* @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock
* @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
* @arg @ref RCC_PERIPHCLK_OSPI OSPI peripheral clock
* @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock
* @arg @ref RCC_PERIPHCLK_DAC1 DAC1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_HSPI HSPI peripheral clock
+ * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USBPHY USBPHY peripheral clock
*
* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
* the RTC clock source: in this case the access to Backup domain is enabled.
*
* @retval HAL status
+ *
+ * (*) value not defined in all devices.
*/
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
{
uint32_t tmpregister;
uint32_t tickstart;
@@ -366,6 +448,7 @@
__HAL_RCC_USART1_CONFIG(pPeriphClkInit->Usart1ClockSelection);
}
+#if defined(USART2)
/*-------------------------- USART2 clock source configuration -------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
{
@@ -375,6 +458,7 @@
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(pPeriphClkInit->Usart2ClockSelection);
}
+#endif /* USART2 */
/*-------------------------- USART3 clock source configuration -------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
@@ -405,6 +489,17 @@
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(pPeriphClkInit->Uart5ClockSelection);
}
+#if defined(USART6)
+ /*-------------------------- USART6 clock source configuration -------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART6CLKSOURCE(pPeriphClkInit->Usart6ClockSelection));
+
+ /* Configure the USART6 clock source */
+ __HAL_RCC_USART6_CONFIG(pPeriphClkInit->Usart6ClockSelection);
+ }
+#endif /* USART6 */
/*-------------------------- LPUART1 clock source configuration ------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
@@ -456,6 +551,30 @@
__HAL_RCC_I2C4_CONFIG(pPeriphClkInit->I2c4ClockSelection);
}
+#if defined(I2C5)
+ /*-------------------------- I2C5 clock source configuration ---------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C5) == RCC_PERIPHCLK_I2C5)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C5CLKSOURCE(pPeriphClkInit->I2c5ClockSelection));
+
+ /* Configure the I2C5 clock source */
+ __HAL_RCC_I2C5_CONFIG(pPeriphClkInit->I2c5ClockSelection);
+ }
+#endif /* I2C5 */
+
+#if defined(I2C6)
+ /*-------------------------- I2C6 clock source configuration ---------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C6) == RCC_PERIPHCLK_I2C6)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C6CLKSOURCE(pPeriphClkInit->I2c6ClockSelection));
+
+ /* Configure the I2C6 clock source */
+ __HAL_RCC_I2C6_CONFIG(pPeriphClkInit->I2c6ClockSelection);
+ }
+#endif /* I2C6 */
+
/*-------------------------- LPTIM1 clock source configuration -------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
{
@@ -528,6 +647,7 @@
}
}
+#if defined(SAI2)
/*-------------------------- SAI2 clock source configuration ---------------------*/
if ((((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
{
@@ -577,6 +697,7 @@
status = ret;
}
}
+#endif /* SAI2 */
/*-------------------------- ADCDAC clock source configuration ----------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADCDAC) == RCC_PERIPHCLK_ADCDAC)
@@ -640,7 +761,6 @@
ret = HAL_ERROR;
break;
}
-
if (ret == HAL_OK)
{
/* Configure the MDF1 interface clock source */
@@ -658,7 +778,6 @@
{
/* Check the parameters */
assert_param(IS_RCC_ADF1CLKSOURCE(pPeriphClkInit->Adf1ClockSelection));
-
switch (pPeriphClkInit->Adf1ClockSelection)
{
case RCC_ADF1CLKSOURCE_PLL1:
@@ -679,7 +798,6 @@
ret = HAL_ERROR;
break;
}
-
if (ret == HAL_OK)
{
/* Configure the ADF1 interface clock source */
@@ -698,7 +816,6 @@
FlagStatus pwrclkchanged = RESET;
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(pPeriphClkInit->RTCClockSelection));
-
/* Enable Power Clock */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
{
@@ -777,25 +894,25 @@
}
}
- /*-------------------------------------- CK48 Configuration -----------------------------------*/
- if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
+ /*-------------------------------------- ICLK Configuration -----------------------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ICLK) == RCC_PERIPHCLK_ICLK)
{
/* Check the parameters */
- assert_param(IS_RCC_CLK48CLKSOURCE(pPeriphClkInit->Clk48ClockSelection));
+ assert_param(IS_RCC_ICLKCLKSOURCE(pPeriphClkInit->IclkClockSelection));
- switch (pPeriphClkInit->Clk48ClockSelection)
+ switch (pPeriphClkInit->IclkClockSelection)
{
- case RCC_CLK48CLKSOURCE_PLL2:
+ case RCC_ICLK_CLKSOURCE_PLL2:
/* PLL2 input clock, parameters M, N,P,Q & R configuration and clock output (PLL2ClockOut) */
ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
break;
- case RCC_CLK48CLKSOURCE_PLL1:
- /* Enable CLK48 Clock output generated from System PLL */
+ case RCC_ICLK_CLKSOURCE_PLL1:
+ /* Enable ICLK Clock output generated from System PLL */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
break;
- case RCC_CLK48CLKSOURCE_HSI48:
+ case RCC_ICLK_CLKSOURCE_HSI48:
break;
- case RCC_CLK48CLKSOURCE_MSIK:
+ case RCC_ICLK_CLKSOURCE_MSIK:
break;
default:
ret = HAL_ERROR;
@@ -804,7 +921,7 @@
if (ret == HAL_OK)
{
/* Configure the CLK48 source */
- __HAL_RCC_CLK48_CONFIG(pPeriphClkInit->Clk48ClockSelection);
+ __HAL_RCC_CLK48_CONFIG(pPeriphClkInit->IclkClockSelection);
}
else
{
@@ -836,7 +953,6 @@
ret = HAL_ERROR;
break;
}
-
if (ret == HAL_OK)
{
/* Set the source of RNG clock*/
@@ -849,6 +965,7 @@
}
}
+#if defined(SAES)
/*-------------------------- SAES clock source configuration ----------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAES) == RCC_PERIPHCLK_SAES)
{
@@ -858,6 +975,7 @@
/* Configure the SAES clock source */
__HAL_RCC_SAES_CONFIG(pPeriphClkInit->SaesClockSelection);
}
+#endif /* SAES */
/*-------------------------- SDMMC1/2 clock source configuration -------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == (RCC_PERIPHCLK_SDMMC))
@@ -918,13 +1036,71 @@
}
if (pPeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL2)
{
- /* Enable PLL2 Q CLK output */
- __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
+ /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
+ ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
}
- /* Configure the OctoSPI clock source */
- __HAL_RCC_OSPI_CONFIG(pPeriphClkInit->OspiClockSelection);
+ if (ret == HAL_OK)
+ {
+ /* Configure the OctoSPI clock source */
+ __HAL_RCC_OSPI_CONFIG(pPeriphClkInit->OspiClockSelection);
+ }
+ else
+ {
+ /* set overall return value */
+ status = ret;
+ }
}
+#if defined(HSPI1)
+ /*-------------------------- HSPIx kernel clock source configuration ----------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HSPI) == RCC_PERIPHCLK_HSPI)
+ {
+
+ /* Check the parameters */
+ assert_param(IS_RCC_HSPICLKSOURCE(pPeriphClkInit->HspiClockSelection));
+
+ switch (pPeriphClkInit->HspiClockSelection)
+ {
+ case RCC_HSPICLKSOURCE_SYSCLK: /* SYSCLK is used as clock source for HSPI kernel clock*/
+ /* HSPI kernel clock source config set later after clock selection check */
+ break;
+
+ case RCC_HSPICLKSOURCE_PLL1: /* PLL1 is used as clock source for HSPI kernel clock*/
+ /* Enable 48M2 Clock output generated from System PLL . */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ /* HSPI kernel clock source config set later after clock selection check */
+ break;
+
+ case RCC_HSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for HSPI kernel clock*/
+ /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
+ ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
+ /* HSPI kernel clock source config set later after clock selection check */
+ break;
+
+ case RCC_HSPICLKSOURCE_PLL3: /* PLL3 is used as clock source for HSPI kernel clock*/
+ /* PLL3 input clock, parameters M, N & R configuration and clock output (PLL3ClockOut) */
+ ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
+ /* HSPI kernel clock source config set later after clock selection check */
+ break;
+
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ if (ret == HAL_OK)
+ {
+ /* Set the source of HSPI kernel clock*/
+ __HAL_RCC_HSPI_CONFIG(pPeriphClkInit->HspiClockSelection);
+ }
+ else
+ {
+ /* set overall return value */
+ status = ret;
+ }
+ }
+#endif /* defined(HSPI1) */
+
/*-------------------------- FDCAN1 kernel clock source configuration -------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN1) == (RCC_PERIPHCLK_FDCAN1))
{
@@ -964,6 +1140,7 @@
/*-------------------------- DAC1 clock source configuration ----------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DAC1) == RCC_PERIPHCLK_DAC1)
{
+
/* Check the parameters */
assert_param(IS_RCC_DAC1CLKSOURCE(pPeriphClkInit->Dac1ClockSelection));
@@ -971,31 +1148,189 @@
__HAL_RCC_DAC1_CONFIG(pPeriphClkInit->Dac1ClockSelection);
}
+#if defined(LTDC)
+
+ /*-------------------------- LTDC clock source configuration ----------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
+ {
+
+ /* Check the parameters */
+ assert_param(IS_RCC_LTDCCLKSOURCE(pPeriphClkInit->LtdcClockSelection));
+
+ switch (pPeriphClkInit->LtdcClockSelection)
+ {
+ case RCC_LTDCCLKSOURCE_PLL2: /* PLL2 is used as clock source for LTDC clock*/
+ /* PLL2 input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
+ ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
+ /* LTDC clock source config set later after clock selection check */
+ break;
+
+ case RCC_LTDCCLKSOURCE_PLL3: /* PLL3 is used as clock source for LTDC clock*/
+ /* PLL3 input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
+ ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
+ /* LTDC clock source config set later after clock selection check */
+ break;
+
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ if (ret == HAL_OK)
+ {
+ /* Set the source of LTDC clock*/
+ __HAL_RCC_LTDC_CONFIG(pPeriphClkInit->LtdcClockSelection);
+ }
+ else
+ {
+ /* set overall return value */
+ status = ret;
+ }
+ }
+
+#endif /* defined(LTDC) */
+
+#if defined(DSI)
+
+ /*-------------------------- DSI clock source configuration ----------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
+ {
+
+ /* Check the parameters */
+ assert_param(IS_RCC_DSICLKSOURCE(pPeriphClkInit->DsiClockSelection));
+
+ if (pPeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLL3)
+ {
+ /* PLL3 is used as clock source for DSI clock*/
+ /* PLL3 input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
+ ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
+ }
+
+ if (ret == HAL_OK)
+ {
+ /* Set the source of DSI clock*/
+ __HAL_RCC_DSI_CONFIG(pPeriphClkInit->DsiClockSelection);
+ }
+ else
+ {
+ /* set overall return value */
+ status = ret;
+ }
+ }
+
+#endif /* defined(DSI) */
+
+#if defined(USB_OTG_HS)
+
+ /*-------------------------- USB PHY clock source configuration ----------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USBPHY) == RCC_PERIPHCLK_USBPHY)
+ {
+
+ /* Check the parameters */
+ assert_param(IS_RCC_USBPHYCLKSOURCE(pPeriphClkInit->UsbPhyClockSelection));
+
+ switch (pPeriphClkInit->UsbPhyClockSelection)
+ {
+ case RCC_USBPHYCLKSOURCE_HSE: /* HSE is used as clock source for USB PHY clock*/
+ case RCC_USBPHYCLKSOURCE_HSE_DIV2: /* HSE div 2 is used as clock source for USB PHY clock*/
+ /* USB-PHY clock source config set later after clock selection check */
+ break;
+
+ case RCC_USBPHYCLKSOURCE_PLL1: /* PLL1 P divider clock selected as USB PHY clock */
+ case RCC_USBPHYCLKSOURCE_PLL1_DIV2: /* PLL1 P divider clock div 2 selected as USB PHY clock */
+ /* Enable P Clock output generated from System PLL . */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
+ /* USB-PHY clock source config set later after clock selection check */
+ break;
+
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ if (ret == HAL_OK)
+ {
+ /* Set the source of USBPHY clock*/
+ __HAL_RCC_USBPHY_CONFIG(pPeriphClkInit->UsbPhyClockSelection);
+ }
+ else
+ {
+ /* set overall return value */
+ status = ret;
+ }
+ }
+
+#endif /* defined(USB_OTG_HS) */
+
return status;
}
+
+
/**
* @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
* @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* returns the configuration information for the Extended Peripherals
* clocks(USART1, USART2, USART3, UART4, UART5, LPUART, I2C1, I2C2, I2C3, LPTIM1, LPTIM2, SAI1, SAI2,
- * SAES, ADC1, ADC4, MDF1, MDF2, RTC, CLK48, SDMMC1, I2C4, SPI12, SPI3, OSPI, FDCAN1, DAC1).
+ * ADC1, ADC2, MDF1, MDF2, RTC, CLK48, SDMMC1, I2C4, SPI12, SPI3, OSPI, FDCAN1, DAC1).
* @retval None
*/
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
{
/* Set all possible values for the extended clock type parameter------------*/
+#if (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx))
+ pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \
+ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \
+ RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \
+ RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \
+ RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \
+ RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \
+ RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_USBPHY;
+#elif (defined(STM32U595xx) || defined(STM32U5A5xx))
+ pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \
+ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \
+ RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \
+ RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \
+ RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \
+ RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_USBPHY;
+#elif (defined(STM32U585xx) || defined(STM32U575xx))
pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \
RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \
- RCC_PERIPHCLK_SAES | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | \
RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | \
RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | \
RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1;
+#else
+ pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \
+ RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | \
+ RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | \
+ RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | \
+ RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ICLK | \
+ RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_I2C4 | \
+ RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \
+ RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1;
+#endif /* (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx)) */
+
+#if defined(SAES)
+ pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAES;
+#endif /* SAES */
+
/* Get the PLL2 Clock configuration -----------------------------------------------*/
pPeriphClkInit->PLL2.PLL2Source = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC) >> RCC_PLL2CFGR_PLL2SRC_Pos);
pPeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1U;
@@ -1021,8 +1356,10 @@
/* Get the USART1 clock source ---------------------------------------------*/
pPeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
+#if defined(USART2)
/* Get the USART2 clock source ---------------------------------------------*/
pPeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
+#endif /* USART2 */
/* Get the USART3 clock source ---------------------------------------------*/
pPeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
@@ -1036,6 +1373,11 @@
/* Get the LPUART1 clock source --------------------------------------------*/
pPeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
+#if defined(USART6)
+ /* Get the UART6 clock source ---------------------------------------------*/
+ pPeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
+#endif /* defined(USART6) */
+
/* Get the I2C1 clock source -----------------------------------------------*/
pPeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
@@ -1048,6 +1390,16 @@
/* Get the I2C4 clock source -----------------------------------------------*/
pPeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
+#if defined(I2C5)
+ /* Get the clock source ---------------------------------------------*/
+ pPeriphClkInit->I2c5ClockSelection = __HAL_RCC_GET_I2C5_SOURCE();
+#endif /* defined(I2C5) */
+
+#if defined(I2C6)
+ /* Get the clock source ---------------------------------------------*/
+ pPeriphClkInit->I2c6ClockSelection = __HAL_RCC_GET_I2C6_SOURCE();
+#endif /* defined(I2C6) */
+
/* Get the LPTIM1 clock source ---------------------------------------------*/
pPeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
@@ -1066,17 +1418,21 @@
/* Get the ADF1 clock source -----------------------------------------------*/
pPeriphClkInit->Adf1ClockSelection = __HAL_RCC_GET_ADF1_SOURCE();
+#if defined(SAES)
/* Get the SAES clock source -----------------------------------------------*/
pPeriphClkInit->SaesClockSelection = __HAL_RCC_GET_SAES_SOURCE();
+#endif /* SAES */
/* Get the SAI1 clock source -----------------------------------------------*/
pPeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
+#if defined(SAI2)
/* Get the SAI2 clock source -----------------------------------------------*/
pPeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
+#endif /* SAI2 */
/* Get the CLK48 clock source ----------------------------------------------*/
- pPeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+ pPeriphClkInit->IclkClockSelection = __HAL_RCC_GET_ICLK_SOURCE();
/* Get the SDMMC clock source ----------------------------------------------*/
pPeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE();
@@ -1104,6 +1460,26 @@
/* Get the RNG clock source ------------------------------------------------*/
pPeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
+
+#if defined(HSPI1)
+ /* Get the HSPI kernel clock source ------------------------------------------------*/
+ pPeriphClkInit->HspiClockSelection = __HAL_RCC_GET_HSPI_SOURCE();
+#endif /* defined(HSPI1) */
+
+#if defined(LTDC)
+ /* Get the LTDC clock source ------------------------------------------------*/
+ pPeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE();
+#endif /* defined(LTDC) */
+
+#if defined(DSI)
+ /* Get the DSI clock source ------------------------------------------------*/
+ pPeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE();
+#endif /* defined(DSI) */
+
+#if defined(USB_OTG_HS)
+ /* Get the USB PHY clock source ------------------------------------------------*/
+ pPeriphClkInit->UsbPhyClockSelection = __HAL_RCC_GET_USBPHY_SOURCE();
+#endif /* defined(USB_OTG_HS) */
}
/**
@@ -1133,73 +1509,64 @@
pll1n = (RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N);
pll1source = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U;
- pll1fracen = RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN;
+ pll1fracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos);
fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \
RCC_PLL1FRACR_PLL1FRACN_Pos));
- if (pll1m != 0U)
+ switch (pll1source)
{
- switch (pll1source)
- {
- case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
- pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
- (fracn1 / (float_t)0x2000) + (float_t)1);
- break;
- case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
- pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \
- ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1);
- break;
- case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
- pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
- (fracn1 / (float_t)0x2000) + (float_t)1);
- break;
- default:
- pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \
- ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1);
- break;
- }
+ case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
+ (fracn1 / (float_t)0x2000) + (float_t)1);
+ break;
+ case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
+ pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \
+ ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1);
+ break;
+ case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
+ (fracn1 / (float_t)0x2000) + (float_t)1);
+ break;
+ default:
+ pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \
+ ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1);
+ break;
+ }
- if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVP) != 0U)
- {
- PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \
- RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + \
- (float_t)1));
- }
- else
- {
- PLL1_Clocks->PLL1_P_Frequency = 0U;
- }
-
- if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVQ) != 0U)
- {
- PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \
- RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + \
- (float_t)1));
- }
- else
- {
- PLL1_Clocks->PLL1_Q_Frequency = 0U;
- }
-
- if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVR) != 0U)
- {
- PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \
- RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + \
- (float_t)1));
- }
- else
- {
- PLL1_Clocks->PLL1_R_Frequency = 0U;
- }
-
+ if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVP) != 0U)
+ {
+ PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \
+ RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + \
+ (float_t)1));
}
else
{
PLL1_Clocks->PLL1_P_Frequency = 0U;
+ }
+
+ if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVQ) != 0U)
+ {
+ PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \
+ RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + \
+ (float_t)1));
+ }
+ else
+ {
PLL1_Clocks->PLL1_Q_Frequency = 0U;
+ }
+
+ if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVR) != 0U)
+ {
+ PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \
+ RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + \
+ (float_t)1));
+ }
+ else
+ {
PLL1_Clocks->PLL1_R_Frequency = 0U;
}
+
}
/**
@@ -1231,69 +1598,60 @@
pll2n = (RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N);
pll2source = (RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC);
pll2m = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1U;
- pll2fracen = RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN;
+ pll2fracen = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN) >> RCC_PLL2CFGR_PLL2FRACEN_Pos);
fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \
RCC_PLL2FRACR_PLL2FRACN_Pos));
- if (pll2m != 0U)
+ switch (pll2source)
{
- switch (pll2source)
- {
- case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
- pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \
- (fracn2 / (float_t)0x2000) + (float_t)1);
- break;
+ case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \
+ (fracn2 / (float_t)0x2000) + (float_t)1);
+ break;
- case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
- pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll2m) * \
- ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1);
- break;
+ case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
+ pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll2m) * \
+ ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1);
+ break;
- case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
- pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \
- (fracn2 / (float_t)0x2000) + (float_t)1);
- break;
+ case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \
+ (fracn2 / (float_t)0x2000) + (float_t)1);
+ break;
- default:
- pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t) pll2m) \
- * ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1);
- break;
- }
- if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVP) != 0U)
- {
- PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \
- RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + \
- (float_t)1));
- }
- else
- {
- PLL2_Clocks->PLL2_P_Frequency = 0U;
- }
- if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVQ) != 0U)
- {
- PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \
- RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + \
- (float_t)1));
- }
- else
- {
- PLL2_Clocks->PLL2_Q_Frequency = 0U;
- }
- if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVR) != 0U)
- {
- PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \
- RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + \
- (float_t)1));
- }
- else
- {
- PLL2_Clocks->PLL2_R_Frequency = 0U;
- }
+ default:
+ pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t) pll2m) \
+ * ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1);
+ break;
+ }
+ if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVP) != 0U)
+ {
+ PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \
+ RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + \
+ (float_t)1));
}
else
{
PLL2_Clocks->PLL2_P_Frequency = 0U;
+ }
+ if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVQ) != 0U)
+ {
+ PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \
+ RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + \
+ (float_t)1));
+ }
+ else
+ {
PLL2_Clocks->PLL2_Q_Frequency = 0U;
+ }
+ if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVR) != 0U)
+ {
+ PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \
+ RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + \
+ (float_t)1));
+ }
+ else
+ {
PLL2_Clocks->PLL2_R_Frequency = 0U;
}
}
@@ -1329,75 +1687,66 @@
pll3n = (RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N);
pll3source = (RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC);
pll3m = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1U;
- pll3fracen = RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN;
+ pll3fracen = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN) >> RCC_PLL3CFGR_PLL3FRACEN_Pos);
fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \
RCC_PLL3FRACR_PLL3FRACN_Pos));
- if (pll3m != 0U)
+ switch (pll3source)
{
- switch (pll3source)
- {
- case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
- pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \
- (fracn3 / (float_t)0x2000) + (float_t)1);
+ case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \
+ (fracn3 / (float_t)0x2000) + (float_t)1);
- break;
- case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
- pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \
- ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1);
- break;
+ break;
+ case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
+ pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \
+ ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1);
+ break;
- case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
- pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \
- (fracn3 / (float_t)0x2000) + (float_t)1);
- break;
+ case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \
+ (fracn3 / (float_t)0x2000) + (float_t)1);
+ break;
- default:
- pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \
- ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1);
- break;
- }
+ default:
+ pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \
+ ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1);
+ break;
+ }
- if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVP) != 0U)
- {
- PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \
- RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + \
- (float_t)1));
- }
- else
- {
- PLL3_Clocks->PLL3_P_Frequency = 0U;
- }
-
- if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVQ) != 0U)
- {
- PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \
- RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + \
- (float_t)1));
- }
- else
- {
- PLL3_Clocks->PLL3_Q_Frequency = 0U;
- }
-
- if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVR) != 0U)
- {
- PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \
- RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + \
- (float_t)1));
- }
- else
- {
- PLL3_Clocks->PLL3_R_Frequency = 0U;
- }
-
+ if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVP) != 0U)
+ {
+ PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \
+ RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + \
+ (float_t)1));
}
else
{
PLL3_Clocks->PLL3_P_Frequency = 0U;
+ }
+
+ if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVQ) != 0U)
+ {
+ PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \
+ RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + \
+ (float_t)1));
+ }
+ else
+ {
PLL3_Clocks->PLL3_Q_Frequency = 0U;
+ }
+
+ if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVR) != 0U)
+ {
+ PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \
+ RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + \
+ (float_t)1));
+ }
+ else
+ {
PLL3_Clocks->PLL3_R_Frequency = 0U;
}
+
}
/**
@@ -1410,31 +1759,41 @@
* @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
* @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
* @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
- * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock
- * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock
* @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ICLK ICLK peripheral clock
+ * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock
* @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
* @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1,ADC4, DAC1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
- * @arg @ref RCC_PERIPHCLK_CLK48 CLK48 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock (*)
+ * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
* @arg @ref RCC_PERIPHCLK_SDMMC SDMMC peripheral clock
- * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock (*)
+ * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (*)
* @arg @ref RCC_PERIPHCLK_OSPI OSPI peripheral clock
- * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_HSPI HSPI peripheral clock (*)
+ * @arg @ref RCC_PERIPHCLK_I2C5 I2C5 peripheral clock (*)
+ * @arg @ref RCC_PERIPHCLK_I2C6 I2C6 peripheral clock (*)
+ * @arg @ref RCC_PERIPHCLK_USBPHY USB_OTG_HS peripheral clock (*)
+ * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1 ADC2 ADC4 DAC1 peripheral clock
* @arg @ref RCC_PERIPHCLK_DAC1 DAC1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADF1 ADF1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
* @retval Frequency in Hz
+ *
+ * (*) value not defined in all devices.
*/
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
{
PLL1_ClocksTypeDef pll1_clocks;
PLL2_ClocksTypeDef pll2_clocks;
@@ -1479,895 +1838,508 @@
frequency = 0U;
}
}
- else
+ else if (PeriphClk == RCC_PERIPHCLK_SAI1)
{
- /* Other external peripheral clock source than RTC */
- switch (PeriphClk)
+ srcclk = __HAL_RCC_GET_SAI1_SOURCE();
+
+ switch (srcclk)
{
- case RCC_PERIPHCLK_SAI1:
+ case RCC_SAI1CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */
- srcclk = __HAL_RCC_GET_SAI1_SOURCE();
-
- switch (srcclk)
- {
- case RCC_SAI1CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */
-
- HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
- frequency = pll1_clocks.PLL1_P_Frequency;
- break;
-
- case RCC_SAI1CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */
-
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- frequency = pll2_clocks.PLL2_P_Frequency;
- break;
-
- case RCC_SAI1CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */
-
- HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- frequency = pll3_clocks.PLL3_P_Frequency;
- break;
-
- case RCC_SAI1CLKSOURCE_PIN:
-
- frequency = EXTERNAL_SAI1_CLOCK_VALUE;
- break;
-
- case RCC_SAI1CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */
-
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- else
- {
- frequency = 0U;
- }
- break;
-
- default :
- {
- frequency = 0U;
- break;
- }
- }
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_P_Frequency;
break;
- case RCC_PERIPHCLK_SAI2:
+ case RCC_SAI1CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */
- srcclk = __HAL_RCC_GET_SAI2_SOURCE();
-
- switch (srcclk)
- {
- case RCC_SAI2CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */
-
- HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
- frequency = pll1_clocks.PLL1_P_Frequency;
- break;
-
- case RCC_SAI2CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */
-
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- frequency = pll2_clocks.PLL2_P_Frequency;
- break;
-
- case RCC_SAI2CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */
-
- HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- frequency = pll3_clocks.PLL3_P_Frequency;
- break;
-
- case RCC_SAI2CLKSOURCE_PIN:
-
- frequency = EXTERNAL_SAI1_CLOCK_VALUE;
- break;
-
- case RCC_SAI2CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */
-
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- else
- {
- frequency = 0U;
- }
- break;
-
- default :
-
- frequency = 0U;
- break;
-
- }
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ frequency = pll2_clocks.PLL2_P_Frequency;
break;
- case RCC_PERIPHCLK_SAES:
- /* Get the current SAES source */
- srcclk = __HAL_RCC_GET_SAES_SOURCE();
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI))
+ case RCC_SAI1CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */
+
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_P_Frequency;
+ break;
+
+ case RCC_SAI1CLKSOURCE_PIN:
+
+ frequency = EXTERNAL_SAI1_CLOCK_VALUE;
+ break;
+
+ case RCC_SAI1CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
{
frequency = HSI_VALUE;
}
- else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI_DIV2))
- {
- frequency = HSI_VALUE >> 1U;
- }
- /* Clock not enabled for SAES */
- else
- {
- frequency = 0U;
- }
- break;
-
- case RCC_PERIPHCLK_CLK48:
-
- srcclk = __HAL_RCC_GET_CLK48_SOURCE();
-
- switch (srcclk)
- {
- case RCC_CLK48CLKSOURCE_PLL1: /* PLL1Q */
-
- HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
- frequency = pll1_clocks.PLL1_Q_Frequency;
- break;
-
- case RCC_CLK48CLKSOURCE_PLL2: /* PLL2Q */
-
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- frequency = pll2_clocks.PLL2_Q_Frequency;
- break;
-
- case RCC_CLK48CLKSOURCE_HSI48: /* HSI48 */
-
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY))
- {
- frequency = HSI48_VALUE;
- }
- else
- {
- frequency = 0U;
- }
- break;
-
- case RCC_CLK48CLKSOURCE_MSIK: /* MSIK frequency range in HZ */
-
- frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
- break;
-
- default :
-
- frequency = 0U;
- break;
-
- }
- break;
-
- case RCC_PERIPHCLK_SDMMC:
- srcclk = __HAL_RCC_GET_SDMMC_SOURCE();
- if (srcclk == RCC_SDMMCCLKSOURCE_CLK48)
- {
- srcclk = __HAL_RCC_GET_CLK48_SOURCE();
-
- switch (srcclk)
- {
- case RCC_CLK48CLKSOURCE_PLL1: /* PLL1Q */
- {
- HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
- frequency = pll1_clocks.PLL1_Q_Frequency;
- break;
- }
- case RCC_CLK48CLKSOURCE_PLL2: /* PLL2Q */
- {
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- frequency = pll2_clocks.PLL2_Q_Frequency;
- break;
- }
- case RCC_CLK48CLKSOURCE_HSI48: /* HSI48 */
- {
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY))
- {
- frequency = HSI48_VALUE;
- }
- else
- {
- frequency = 0U;
- }
- break;
- }
- case RCC_CLK48CLKSOURCE_MSIK: /* MSIK frequency range in HZ */
- {
- frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
- break;
- }
- default :
- {
- frequency = 0U;
- break;
- }
- }
- break;
- }
- else if (srcclk == RCC_SDMMCCLKSOURCE_PLL1)
- {
- HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
- frequency = pll1_clocks.PLL1_P_Frequency;
- }
else
{
frequency = 0U;
}
break;
- case RCC_PERIPHCLK_USART1:
- /* Get the current USART1 source */
- srcclk = __HAL_RCC_GET_USART1_SOURCE();
+ default :
+ {
+ frequency = 0U;
+ break;
+ }
+ }
+ }
+#if defined(SAI2)
+ else if (PeriphClk == RCC_PERIPHCLK_SAI2)
+ {
+ srcclk = __HAL_RCC_GET_SAI2_SOURCE();
- if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
- {
- frequency = HAL_RCC_GetPCLK2Freq();
- }
- else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI))
+ switch (srcclk)
+ {
+ case RCC_SAI2CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */
+
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_P_Frequency;
+ break;
+
+ case RCC_SAI2CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */
+
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ frequency = pll2_clocks.PLL2_P_Frequency;
+ break;
+
+ case RCC_SAI2CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */
+
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_P_Frequency;
+ break;
+
+ case RCC_SAI2CLKSOURCE_PIN:
+
+ frequency = EXTERNAL_SAI1_CLOCK_VALUE;
+ break;
+
+ case RCC_SAI2CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
{
frequency = HSI_VALUE;
}
- else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE))
- {
- frequency = LSE_VALUE;
- }
- /* Clock not enabled for USART1 */
else
{
frequency = 0U;
}
break;
- case RCC_PERIPHCLK_USART2:
- /* Get the current USART2 source */
- srcclk = __HAL_RCC_GET_USART2_SOURCE();
+ default :
- if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
+ frequency = 0U;
+ break;
+ }
+ }
+#endif /* SAI2 */
+#if defined(SAES)
+ else if (PeriphClk == RCC_PERIPHCLK_SAES)
+ {
+ /* Get the current SAES source */
+ srcclk = __HAL_RCC_GET_SAES_SOURCE();
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI_DIV2))
+ {
+ frequency = HSI_VALUE >> 1U;
+ }
+ /* Clock not enabled for SAES */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+#endif /* SAES */
+ else if (PeriphClk == RCC_PERIPHCLK_ICLK)
+ {
+ srcclk = __HAL_RCC_GET_ICLK_SOURCE();
+
+ switch (srcclk)
+ {
+ case RCC_ICLK_CLKSOURCE_PLL1: /* PLL1Q */
+
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_Q_Frequency;
+ break;
+
+ case RCC_ICLK_CLKSOURCE_PLL2: /* PLL2Q */
+
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ frequency = pll2_clocks.PLL2_Q_Frequency;
+ break;
+
+ case RCC_ICLK_CLKSOURCE_HSI48: /* HSI48 */
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY))
{
- frequency = HAL_RCC_GetPCLK1Freq();
+ frequency = HSI48_VALUE;
}
- else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI))
- {
- frequency = HSI_VALUE;
- }
- else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE))
- {
- frequency = LSE_VALUE;
- }
- /* Clock not enabled for USART2 */
else
{
frequency = 0U;
}
break;
- case RCC_PERIPHCLK_USART3:
- /* Get the current USART3 source */
- srcclk = __HAL_RCC_GET_USART3_SOURCE();
+ case RCC_ICLK_CLKSOURCE_MSIK: /* MSIK frequency range in HZ */
- if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
- {
- frequency = HAL_RCC_GetPCLK1Freq();
- }
- else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI))
- {
- frequency = HSI_VALUE;
- }
- else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE))
- {
- frequency = LSE_VALUE;
- }
- /* Clock not enabled for USART3 */
- else
- {
- frequency = 0U;
- }
- break;
-
- case RCC_PERIPHCLK_UART4:
- /* Get the current UART4 source */
- srcclk = __HAL_RCC_GET_UART4_SOURCE();
-
- if (srcclk == RCC_UART4CLKSOURCE_PCLK1)
- {
- frequency = HAL_RCC_GetPCLK1Freq();
- }
- else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI))
- {
- frequency = HSI_VALUE;
- }
- else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE))
- {
- frequency = LSE_VALUE;
- }
- /* Clock not enabled for UART4 */
- else
- {
- frequency = 0U;
- }
- break;
-
- case RCC_PERIPHCLK_UART5:
- /* Get the current UART5 source */
- srcclk = __HAL_RCC_GET_UART5_SOURCE();
-
- if (srcclk == RCC_UART5CLKSOURCE_PCLK1)
- {
- frequency = HAL_RCC_GetPCLK1Freq();
- }
- else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI))
- {
- frequency = HSI_VALUE;
- }
- else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE))
- {
- frequency = LSE_VALUE;
- }
- /* Clock not enabled for UART5 */
- else
- {
- frequency = 0U;
- }
- break;
-
- case RCC_PERIPHCLK_LPUART1:
- /* Get the current LPUART1 source */
- srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
-
- if (srcclk == RCC_LPUART1CLKSOURCE_PCLK3)
- {
- frequency = HAL_RCC_GetPCLK3Freq();
- }
- else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI))
- {
- frequency = HSI_VALUE;
- }
- else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE))
- {
- frequency = LSE_VALUE;
- }
- else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_MSIK))
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
{
frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
}
- /* Clock not enabled for LPUART1 */
else
{
frequency = 0U;
}
break;
- case RCC_PERIPHCLK_ADCDAC:
+ default :
- srcclk = __HAL_RCC_GET_ADCDAC_SOURCE();
-
- if (srcclk == RCC_ADCDACCLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- else if (srcclk == RCC_ADCDACCLKSOURCE_PLL2)
- {
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- frequency = pll2_clocks.PLL2_R_Frequency;
- }
- else if (srcclk == RCC_ADCDACCLKSOURCE_HCLK)
- {
- frequency = HAL_RCC_GetHCLKFreq();
- break;
- }
- else if (srcclk == RCC_ADCDACCLKSOURCE_MSIK)
- {
- frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)];
- break;
- }
- else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSE))
- {
- frequency = HSE_VALUE;
- }
- else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSI))
- {
- frequency = HSI_VALUE;
- }
- /* Clock not enabled for ADC */
- else
- {
- frequency = 0U;
- }
+ frequency = 0U;
break;
+ }
+ }
+ else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
+ {
+ srcclk = __HAL_RCC_GET_SDMMC_SOURCE();
+ if (srcclk == RCC_SDMMCCLKSOURCE_CLK48)
+ {
+ srcclk = __HAL_RCC_GET_ICLK_SOURCE();
- case RCC_PERIPHCLK_MDF1:
- /* Get the current MDF1 source */
- srcclk = __HAL_RCC_GET_MDF1_SOURCE();
-
- switch (srcclk)
- {
- case RCC_MDF1CLKSOURCE_PLL1:
-
- HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
- frequency = pll1_clocks.PLL1_P_Frequency;
- break;
-
- case RCC_MDF1CLKSOURCE_PLL3:
-
- HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- frequency = pll3_clocks.PLL3_Q_Frequency;
- break;
-
- case RCC_MDF1CLKSOURCE_HCLK:
-
- frequency = HAL_RCC_GetHCLKFreq();
- break;
-
- case RCC_MDF1CLKSOURCE_PIN:
-
- frequency = EXTERNAL_SAI1_CLOCK_VALUE;
- break;
-
- case RCC_MDF1CLKSOURCE_MSIK:
-
- frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
- break;
-
- default:
-
- frequency = 0U;
- break;
-
- }
- break;
-
- case RCC_PERIPHCLK_ADF1:
- /* Get the current ADF1 source */
- srcclk = __HAL_RCC_GET_ADF1_SOURCE();
-
- switch (srcclk)
- {
- case RCC_ADF1CLKSOURCE_PLL1:
-
- HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
- frequency = pll1_clocks.PLL1_P_Frequency;
- break;
-
- case RCC_ADF1CLKSOURCE_PLL3:
-
- HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- frequency = pll3_clocks.PLL3_Q_Frequency;
- break;
-
- case RCC_ADF1CLKSOURCE_HCLK:
-
- frequency = HAL_RCC_GetHCLKFreq();
- break;
-
- case RCC_ADF1CLKSOURCE_PIN:
-
- frequency = EXTERNAL_SAI1_CLOCK_VALUE;
- break;
-
- case RCC_ADF1CLKSOURCE_MSIK:
-
- frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
- break;
-
- default:
-
- frequency = 0U;
- break;
- }
- break;
-
- case RCC_PERIPHCLK_I2C1:
- /* Get the current I2C1 source */
- srcclk = __HAL_RCC_GET_I2C1_SOURCE();
-
- if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
- {
- frequency = HAL_RCC_GetPCLK1Freq();
- }
- else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI))
- {
- frequency = HSI_VALUE;
- }
- /* Clock not enabled for I2C1 */
- else
- {
- frequency = 0U;
- }
- break;
-
- case RCC_PERIPHCLK_I2C2:
- /* Get the current I2C2 source */
- srcclk = __HAL_RCC_GET_I2C2_SOURCE();
-
- if (srcclk == RCC_I2C2CLKSOURCE_PCLK1)
- {
- frequency = HAL_RCC_GetPCLK1Freq();
- }
- else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI))
- {
- frequency = HSI_VALUE;
- }
- /* Clock not enabled for I2C2 */
- else
- {
- frequency = 0U;
- }
- break;
-
- case RCC_PERIPHCLK_I2C3:
- /* Get the current I2C3 source */
- srcclk = __HAL_RCC_GET_I2C3_SOURCE();
-
- switch (srcclk)
- {
- case RCC_I2C3CLKSOURCE_PCLK3:
- {
- frequency = HAL_RCC_GetPCLK3Freq();
- break;
- }
- case RCC_I2C3CLKSOURCE_HSI:
- {
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- else
- {
- frequency = 0U;
- }
- break;
- }
- case RCC_I2C3CLKSOURCE_SYSCLK:
- {
- frequency = HAL_RCC_GetSysClockFreq();
- break;
- }
- case RCC_I2C3CLKSOURCE_MSIK:
- {
- frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)];
- break;
- }
- default:
- {
- frequency = 0U;
- break;
- }
- }
- break;
-
- case RCC_PERIPHCLK_I2C4:
- /* Get the current I2C4 source */
- srcclk = __HAL_RCC_GET_I2C4_SOURCE();
-
- if (srcclk == RCC_I2C4CLKSOURCE_PCLK1)
- {
- frequency = HAL_RCC_GetPCLK1Freq();
- }
- else if (srcclk == RCC_I2C4CLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI))
- {
- frequency = HSI_VALUE;
- }
- /* Clock not enabled for I2C4 */
- else
- {
- frequency = 0U;
- }
- break;
-
- case RCC_PERIPHCLK_LPTIM34:
- /* Get the current LPTIM34 source */
- srcclk = __HAL_RCC_GET_LPTIM34_SOURCE();
-
- if (srcclk == RCC_LPTIM34CLKSOURCE_MSIK)
- {
- frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
- }
- else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSI))
- {
- frequency = LSI_VALUE;
- }
- else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_HSI))
- {
- frequency = HSI_VALUE;
- }
- else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSE))
- {
- frequency = LSE_VALUE;
- }
- /* Clock not enabled for LPTIM34 */
- else
- {
- frequency = 0U;
- }
- break;
-
- case RCC_PERIPHCLK_LPTIM1:
- /* Get the current LPTIM1 source */
- srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
-
- if (srcclk == RCC_LPTIM1CLKSOURCE_MSIK)
- {
- frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
- }
- else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI))
- {
- frequency = LSI_VALUE;
- }
- else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI))
- {
- frequency = HSI_VALUE;
- }
- else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE))
- {
- frequency = LSE_VALUE;
- }
- /* Clock not enabled for LPTIM1 */
- else
- {
- frequency = 0U;
- }
- break;
-
- case RCC_PERIPHCLK_LPTIM2:
- /* Get the current LPTIM2 source */
- srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
-
- if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1)
- {
- frequency = HAL_RCC_GetPCLK1Freq();
- }
- else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSI))
- {
- frequency = LSI_VALUE;
- }
- else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_HSI))
- {
- frequency = HSI_VALUE;
- }
- else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSE))
- {
- frequency = LSE_VALUE;
- }
- /* Clock not enabled for LPTIM2 */
- else
- {
- frequency = 0U;
- }
- break;
-
- case RCC_PERIPHCLK_FDCAN1:
- /* Get the current FDCAN1 kernel source */
- srcclk = __HAL_RCC_GET_FDCAN1_SOURCE();
-
- if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCAN1CLKSOURCE_HSE))
- {
- frequency = HSE_VALUE;
- }
- else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL1) /* PLL1 ? */
+ switch (srcclk)
+ {
+ case RCC_ICLK_CLKSOURCE_PLL1: /* PLL1Q */
{
HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
frequency = pll1_clocks.PLL1_Q_Frequency;
+ break;
}
- else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL2) /* PLL2 ? */
+ case RCC_ICLK_CLKSOURCE_PLL2: /* PLL2Q */
{
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- frequency = pll2_clocks.PLL2_P_Frequency;
+ frequency = pll2_clocks.PLL2_Q_Frequency;
+ break;
}
- /* Clock not enabled for FDCAN1 */
- else
+ case RCC_ICLK_CLKSOURCE_HSI48: /* HSI48 */
+ {
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY))
+ {
+ frequency = HSI48_VALUE;
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+ }
+ case RCC_ICLK_CLKSOURCE_MSIK: /* MSIK frequency range in HZ */
+ {
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+ }
+ default :
{
frequency = 0U;
+ break;
}
+ }
+ }
+ else if (srcclk == RCC_SDMMCCLKSOURCE_PLL1)
+ {
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_P_Frequency;
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ }
+ else if (PeriphClk == RCC_PERIPHCLK_USART1)
+ {
+ /* Get the current USART1 source */
+ srcclk = __HAL_RCC_GET_USART1_SOURCE();
+
+ if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
+ {
+ frequency = HAL_RCC_GetPCLK2Freq();
+ }
+ else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART1 */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+#if defined(USART2)
+ else if (PeriphClk == RCC_PERIPHCLK_USART2)
+ {
+ /* Get the current USART2 source */
+ srcclk = __HAL_RCC_GET_USART2_SOURCE();
+
+ if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART2 */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+#endif /* USART2 */
+ else if (PeriphClk == RCC_PERIPHCLK_USART3)
+ {
+ /* Get the current USART3 source */
+ srcclk = __HAL_RCC_GET_USART3_SOURCE();
+
+ if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART3 */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+ else if (PeriphClk == RCC_PERIPHCLK_UART4)
+ {
+ /* Get the current UART4 source */
+ srcclk = __HAL_RCC_GET_UART4_SOURCE();
+
+ if (srcclk == RCC_UART4CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for UART4 */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+ else if (PeriphClk == RCC_PERIPHCLK_UART5)
+ {
+ /* Get the current UART5 source */
+ srcclk = __HAL_RCC_GET_UART5_SOURCE();
+
+ if (srcclk == RCC_UART5CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for UART5 */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+#if defined(USART6)
+ else if (PeriphClk == RCC_PERIPHCLK_USART6)
+ {
+ /* Get the current USART6 source */
+ srcclk = __HAL_RCC_GET_USART6_SOURCE();
+
+ if (srcclk == RCC_USART6CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_USART6CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART6CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART6CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for UART5 */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+#endif /* USART6 */
+ else if (PeriphClk == RCC_PERIPHCLK_LPUART1)
+ {
+ /* Get the current LPUART1 source */
+ srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
+
+ if (srcclk == RCC_LPUART1CLKSOURCE_PCLK3)
+ {
+ frequency = HAL_RCC_GetPCLK3Freq();
+ }
+ else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_MSIK))
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ /* Clock not enabled for LPUART1 */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+ else if (PeriphClk == RCC_PERIPHCLK_ADCDAC)
+ {
+ srcclk = __HAL_RCC_GET_ADCDAC_SOURCE();
+
+ if (srcclk == RCC_ADCDACCLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if (srcclk == RCC_ADCDACCLKSOURCE_PLL2)
+ {
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ frequency = pll2_clocks.PLL2_R_Frequency;
+ }
+ else if (srcclk == RCC_ADCDACCLKSOURCE_HCLK)
+ {
+ frequency = HAL_RCC_GetHCLKFreq();
+ }
+ else if (srcclk == RCC_ADCDACCLKSOURCE_MSIK)
+ {
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSE))
+ {
+ frequency = HSE_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Clock not enabled for ADC */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+ else if (PeriphClk == RCC_PERIPHCLK_MDF1)
+ {
+ /* Get the current MDF1 source */
+ srcclk = __HAL_RCC_GET_MDF1_SOURCE();
+
+ switch (srcclk)
+ {
+ case RCC_MDF1CLKSOURCE_PLL1:
+
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_P_Frequency;
break;
- case RCC_PERIPHCLK_SPI1:
- /* Get the current SPI1 kernel source */
- srcclk = __HAL_RCC_GET_SPI1_SOURCE();
- switch (srcclk)
- {
- case RCC_SPI1CLKSOURCE_PCLK2:
+ case RCC_MDF1CLKSOURCE_PLL3:
- frequency = HAL_RCC_GetPCLK2Freq();
- break;
-
- case RCC_SPI1CLKSOURCE_SYSCLK:
-
- frequency = HAL_RCC_GetSysClockFreq();
- break;
-
- case RCC_SPI1CLKSOURCE_HSI:
-
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- else
- {
- frequency = 0U;
- }
- break;
-
- case RCC_SPI1CLKSOURCE_MSIK:
-
- frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
- break;
-
- default:
-
- frequency = 0U;
- break;
-
- }
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
break;
- case RCC_PERIPHCLK_SPI2:
- /* Get the current SPI2 kernel source */
- srcclk = __HAL_RCC_GET_SPI2_SOURCE();
- switch (srcclk)
- {
- case RCC_SPI2CLKSOURCE_PCLK1:
+ case RCC_MDF1CLKSOURCE_HCLK:
- frequency = HAL_RCC_GetPCLK1Freq();
- break;
-
- case RCC_SPI2CLKSOURCE_SYSCLK:
-
- frequency = HAL_RCC_GetSysClockFreq();
- break;
-
- case RCC_SPI2CLKSOURCE_HSI:
-
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- else
- {
- frequency = 0U;
- }
- break;
-
- case RCC_SPI2CLKSOURCE_MSIK:
-
- frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
- break;
-
- default:
-
- frequency = 0U;
- break;
-
- }
+ frequency = HAL_RCC_GetHCLKFreq();
break;
- case RCC_PERIPHCLK_SPI3:
- /* Get the current SPI3 kernel source */
- srcclk = __HAL_RCC_GET_SPI3_SOURCE();
- switch (srcclk)
- {
- case RCC_SPI3CLKSOURCE_PCLK3:
+ case RCC_MDF1CLKSOURCE_PIN:
- frequency = HAL_RCC_GetPCLK3Freq();
- break;
-
- case RCC_SPI3CLKSOURCE_SYSCLK:
-
- frequency = HAL_RCC_GetSysClockFreq();
- break;
-
- case RCC_SPI3CLKSOURCE_HSI:
-
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- else
- {
- frequency = 0U;
- }
- break;
-
- case RCC_SPI3CLKSOURCE_MSIK:
-
- frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
- break;
-
- default:
-
- frequency = 0U;
- break;
- }
+ frequency = EXTERNAL_SAI1_CLOCK_VALUE;
break;
- case RCC_PERIPHCLK_OSPI:
- /* Get the current OSPI kernel source */
- srcclk = __HAL_RCC_GET_OSPI_SOURCE();
+ case RCC_MDF1CLKSOURCE_MSIK:
- switch (srcclk)
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
{
- case RCC_OSPICLKSOURCE_PLL2:
-
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- frequency = pll2_clocks.PLL2_Q_Frequency;
- break;
-
- case RCC_OSPICLKSOURCE_PLL1:
-
- HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
- frequency = pll1_clocks.PLL1_Q_Frequency;
- break;
-
- case RCC_OSPICLKSOURCE_SYSCLK:
-
- frequency = HAL_RCC_GetSysClockFreq();
- break;
-
- case RCC_OSPICLKSOURCE_MSIK:
-
- frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
- break;
-
- default:
-
- frequency = 0U;
- break;
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
}
- break;
-
- case RCC_PERIPHCLK_DAC1:
- /* Get the current DAC1 kernel source */
- srcclk = __HAL_RCC_GET_DAC1_SOURCE();
- /* Check if LSE is ready and if DAC1 clock selection is LSE */
- if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSE))
- {
- frequency = LSE_VALUE;
- }
- /* Check if LSI is ready and if DAC1 clock selection is LSI */
- else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSI))
- {
- frequency = LSI_VALUE;
- }
- /* Clock not enabled for DAC1*/
else
{
frequency = 0U;
@@ -2375,16 +2347,729 @@
break;
default:
- frequency = 0U;
+
+ frequency = 0U;
break;
}
}
+ else if (PeriphClk == RCC_PERIPHCLK_ADF1)
+ {
+ /* Get the current ADF1 source */
+ srcclk = __HAL_RCC_GET_ADF1_SOURCE();
+
+ switch (srcclk)
+ {
+ case RCC_ADF1CLKSOURCE_PLL1:
+
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_P_Frequency;
+ break;
+
+ case RCC_ADF1CLKSOURCE_PLL3:
+
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
+ break;
+
+ case RCC_ADF1CLKSOURCE_HCLK:
+
+ frequency = HAL_RCC_GetHCLKFreq();
+ break;
+
+ case RCC_ADF1CLKSOURCE_PIN:
+
+ frequency = EXTERNAL_SAI1_CLOCK_VALUE;
+ break;
+
+ case RCC_ADF1CLKSOURCE_MSIK:
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ default:
+
+ frequency = 0U;
+ break;
+ }
+ }
+ else if (PeriphClk == RCC_PERIPHCLK_I2C1)
+ {
+ /* Get the current I2C1 source */
+ srcclk = __HAL_RCC_GET_I2C1_SOURCE();
+
+ if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C1CLKSOURCE_MSIK))
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ /* Clock not enabled for I2C1 */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+ else if (PeriphClk == RCC_PERIPHCLK_I2C2)
+ {
+ /* Get the current I2C2 source */
+ srcclk = __HAL_RCC_GET_I2C2_SOURCE();
+
+ if (srcclk == RCC_I2C2CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C2CLKSOURCE_MSIK))
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ /* Clock not enabled for I2C2 */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+ else if (PeriphClk == RCC_PERIPHCLK_I2C3)
+ {
+ /* Get the current I2C3 source */
+ srcclk = __HAL_RCC_GET_I2C3_SOURCE();
+
+ switch (srcclk)
+ {
+ case RCC_I2C3CLKSOURCE_PCLK3:
+ {
+ frequency = HAL_RCC_GetPCLK3Freq();
+ break;
+ }
+ case RCC_I2C3CLKSOURCE_HSI:
+ {
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+ {
+ frequency = HSI_VALUE;
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+ }
+ case RCC_I2C3CLKSOURCE_SYSCLK:
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ break;
+ }
+ case RCC_I2C3CLKSOURCE_MSIK:
+ {
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+ }
+ default:
+ {
+ frequency = 0U;
+ break;
+ }
+ }
+ }
+ else if (PeriphClk == RCC_PERIPHCLK_I2C4)
+ {
+ /* Get the current I2C4 source */
+ srcclk = __HAL_RCC_GET_I2C4_SOURCE();
+
+ if (srcclk == RCC_I2C4CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_I2C4CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C4CLKSOURCE_MSIK))
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ /* Clock not enabled for I2C4 */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+#if defined (I2C5)
+ else if (PeriphClk == RCC_PERIPHCLK_I2C5)
+ {
+ /* Get the current I2C5 source */
+ srcclk = __HAL_RCC_GET_I2C5_SOURCE();
+
+ if (srcclk == RCC_I2C5CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_I2C5CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C5CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C5CLKSOURCE_MSIK))
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ /* Clock not enabled for I2C5 */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+#endif /* I2C5 */
+#if defined (I2C6)
+ else if (PeriphClk == RCC_PERIPHCLK_I2C6)
+ {
+ /* Get the current I2C6 source */
+ srcclk = __HAL_RCC_GET_I2C6_SOURCE();
+
+ if (srcclk == RCC_I2C6CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_I2C6CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C6CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C6CLKSOURCE_MSIK))
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ /* Clock not enabled for I2C6 */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+#endif /* I2C6 */
+ else if (PeriphClk == RCC_PERIPHCLK_LPTIM34)
+ {
+ /* Get the current LPTIM34 source */
+ srcclk = __HAL_RCC_GET_LPTIM34_SOURCE();
+
+ if (srcclk == RCC_LPTIM34CLKSOURCE_MSIK)
+ {
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSI))
+ {
+ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV))
+ {
+ frequency = LSI_VALUE / 128U;
+ }
+ else
+ {
+ frequency = LSI_VALUE;
+ }
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for LPTIM34 */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+ else if (PeriphClk == RCC_PERIPHCLK_LPTIM1)
+ {
+ /* Get the current LPTIM1 source */
+ srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
+
+ if (srcclk == RCC_LPTIM1CLKSOURCE_MSIK)
+ {
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI))
+ {
+ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV))
+ {
+ frequency = LSI_VALUE / 128U;
+ }
+ else
+ {
+ frequency = LSI_VALUE;
+ }
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for LPTIM1 */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+ else if (PeriphClk == RCC_PERIPHCLK_LPTIM2)
+ {
+ /* Get the current LPTIM2 source */
+ srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
+
+ if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSI))
+ {
+ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV))
+ {
+ frequency = LSI_VALUE / 128U;
+ }
+ else
+ {
+ frequency = LSI_VALUE;
+ }
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for LPTIM2 */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+ else if (PeriphClk == RCC_PERIPHCLK_FDCAN1)
+ {
+ /* Get the current FDCAN1 kernel source */
+ srcclk = __HAL_RCC_GET_FDCAN1_SOURCE();
+
+ if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCAN1CLKSOURCE_HSE))
+ {
+ frequency = HSE_VALUE;
+ }
+ else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL1) /* PLL1 ? */
+ {
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_Q_Frequency;
+ }
+ else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL2) /* PLL2 ? */
+ {
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ frequency = pll2_clocks.PLL2_P_Frequency;
+ }
+ /* Clock not enabled for FDCAN1 */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+ else if (PeriphClk == RCC_PERIPHCLK_SPI1)
+ {
+ /* Get the current SPI1 kernel source */
+ srcclk = __HAL_RCC_GET_SPI1_SOURCE();
+ switch (srcclk)
+ {
+ case RCC_SPI1CLKSOURCE_PCLK2:
+
+ frequency = HAL_RCC_GetPCLK2Freq();
+ break;
+
+ case RCC_SPI1CLKSOURCE_SYSCLK:
+
+ frequency = HAL_RCC_GetSysClockFreq();
+ break;
+
+ case RCC_SPI1CLKSOURCE_HSI:
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+ {
+ frequency = HSI_VALUE;
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_SPI1CLKSOURCE_MSIK:
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ default:
+
+ frequency = 0U;
+ break;
+ }
+ }
+ else if (PeriphClk == RCC_PERIPHCLK_SPI2)
+ {
+ /* Get the current SPI2 kernel source */
+ srcclk = __HAL_RCC_GET_SPI2_SOURCE();
+ switch (srcclk)
+ {
+ case RCC_SPI2CLKSOURCE_PCLK1:
+
+ frequency = HAL_RCC_GetPCLK1Freq();
+ break;
+
+ case RCC_SPI2CLKSOURCE_SYSCLK:
+
+ frequency = HAL_RCC_GetSysClockFreq();
+ break;
+
+ case RCC_SPI2CLKSOURCE_HSI:
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+ {
+ frequency = HSI_VALUE;
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_SPI2CLKSOURCE_MSIK:
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ default:
+
+ frequency = 0U;
+ break;
+ }
+ }
+ else if (PeriphClk == RCC_PERIPHCLK_SPI3)
+ {
+ /* Get the current SPI3 kernel source */
+ srcclk = __HAL_RCC_GET_SPI3_SOURCE();
+ switch (srcclk)
+ {
+ case RCC_SPI3CLKSOURCE_PCLK3:
+
+ frequency = HAL_RCC_GetPCLK3Freq();
+ break;
+
+ case RCC_SPI3CLKSOURCE_SYSCLK:
+
+ frequency = HAL_RCC_GetSysClockFreq();
+ break;
+
+ case RCC_SPI3CLKSOURCE_HSI:
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+ {
+ frequency = HSI_VALUE;
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_SPI3CLKSOURCE_MSIK:
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ default:
+
+ frequency = 0U;
+ break;
+ }
+ }
+ else if (PeriphClk == RCC_PERIPHCLK_OSPI)
+ {
+ /* Get the current OSPI kernel source */
+ srcclk = __HAL_RCC_GET_OSPI_SOURCE();
+
+ switch (srcclk)
+ {
+ case RCC_OSPICLKSOURCE_PLL2:
+
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ frequency = pll2_clocks.PLL2_Q_Frequency;
+ break;
+
+ case RCC_OSPICLKSOURCE_PLL1:
+
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_Q_Frequency;
+ break;
+
+ case RCC_OSPICLKSOURCE_SYSCLK:
+
+ frequency = HAL_RCC_GetSysClockFreq();
+ break;
+
+ case RCC_OSPICLKSOURCE_MSIK:
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ default:
+
+ frequency = 0U;
+ break;
+ }
+ }
+#if defined(HSPI1)
+
+ else if (PeriphClk == RCC_PERIPHCLK_HSPI)
+ {
+ /* Get the current HSPI kernel source */
+ srcclk = __HAL_RCC_GET_HSPI_SOURCE();
+
+ switch (srcclk)
+ {
+ case RCC_HSPICLKSOURCE_SYSCLK:
+
+ frequency = HAL_RCC_GetSysClockFreq();
+ break;
+
+ case RCC_HSPICLKSOURCE_PLL1:
+
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_Q_Frequency;
+ break;
+
+ case RCC_HSPICLKSOURCE_PLL2:
+
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ frequency = pll2_clocks.PLL2_Q_Frequency;
+ break;
+ case RCC_HSPICLKSOURCE_PLL3:
+
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_R_Frequency;
+ break;
+
+ default:
+
+ frequency = 0U;
+ break;
+ }
+ }
+#endif /* defined(HSPI1) */
+ else if (PeriphClk == RCC_PERIPHCLK_DAC1)
+ {
+ /* Get the current DAC1 kernel source */
+ srcclk = __HAL_RCC_GET_DAC1_SOURCE();
+
+ /* Check if LSE is ready and if DAC1 clock selection is LSE */
+ if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Check if LSI is ready and if DAC1 clock selection is LSI */
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSI))
+ {
+ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV))
+ {
+ frequency = LSI_VALUE / 128U;
+ }
+ else
+ {
+ frequency = LSI_VALUE;
+ }
+ }
+ /* Clock not enabled for DAC1*/
+ else
+ {
+ frequency = 0U;
+ }
+
+ }
+ else if (PeriphClk == RCC_PERIPHCLK_RNG)
+ {
+ /* Get the current RNG kernel source */
+ srcclk = __HAL_RCC_GET_RNG_SOURCE();
+
+ /* Check if HSI48 is ready and if RNG clock selection is HSI48 */
+ if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48))
+ {
+ frequency = HSI48_VALUE;
+ }
+
+ /* Check if HSI48 is ready and if RNG clock selection is HSI48_DIV2 */
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48_DIV2))
+ {
+ frequency = HSI48_VALUE >> 1U ;
+ }
+
+ /* Check if HSI is ready and if RNG clock selection is HSI */
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Clock not enabled for RNG */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+#if defined(LTDC)
+ else if (PeriphClk == RCC_PERIPHCLK_LTDC)
+ {
+ /* Get the current LTDC kernel source */
+ srcclk = __HAL_RCC_GET_LTDC_SOURCE();
+
+ switch (srcclk)
+ {
+ case RCC_LTDCCLKSOURCE_PLL3: /* PLL3R is the clock source for LTDC */
+
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_R_Frequency;
+ break;
+
+ case RCC_LTDCCLKSOURCE_PLL2: /* PLL2R is the clock source for LTDC */
+
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ frequency = pll2_clocks.PLL2_R_Frequency;
+ break;
+
+ default:
+
+ frequency = 0U;
+ break;
+ }
+ }
+#endif /* defined(LTDC) */
+
+#if defined(USB_OTG_HS)
+
+ else if (PeriphClk == RCC_PERIPHCLK_USBPHY)
+ {
+ /* Get the current USB_OTG_HS kernel source */
+ srcclk = __HAL_RCC_GET_USBPHY_SOURCE();
+
+ if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_USBPHYCLKSOURCE_HSE))
+ {
+ frequency = HSE_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_USBPHYCLKSOURCE_HSE_DIV2))
+ {
+ frequency = HSE_VALUE >> 1U ;
+ }
+ else if (srcclk == RCC_USBPHYCLKSOURCE_PLL1) /* PLL1P */
+ {
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_P_Frequency;
+ }
+ else if (srcclk == RCC_USBPHYCLKSOURCE_PLL1_DIV2) /* PLL1P_DIV2 */
+ {
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = (pll1_clocks.PLL1_P_Frequency) / 2U;
+ }
+ /* Clock not enabled for USB_OTG_HS */
+ else
+ {
+ frequency = 0U;
+ }
+ }
+#endif /* defined(USB_OTG_HS) */
+
+ else
+ {
+ frequency = 0;
+ }
return (frequency);
}
-/**
- * @}
- */
/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
* @brief Extended Clock management functions
@@ -2407,7 +3092,7 @@
* contains the configuration information for the PLL2
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)
+HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(const RCC_PLL2InitTypeDef *PLL2Init)
{
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
@@ -2481,6 +3166,7 @@
}
}
}
+
return status;
}
@@ -2522,7 +3208,7 @@
* contains the configuration information for the PLL3
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *PLL3Init)
+HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(const RCC_PLL3InitTypeDef *PLL3Init)
{
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
@@ -2594,6 +3280,7 @@
}
}
}
+
return status;
}
@@ -2740,7 +3427,7 @@
* This parameter can be one of the following values:
* @arg @ref RCC_MSIRANGE_4 Range 4 around 4 MHz (reset value)
* @arg @ref RCC_MSIRANGE_5 Range 5 around 2 MHz
- * @arg @ref RCC_MSIRANGE_6 Range 6 around 1.5 MHz
+ * @arg @ref RCC_MSIRANGE_6 Range 6 around 1.33 MHz
* @arg @ref RCC_MSIRANGE_7 Range 7 around 1 MHz
* @arg @ref RCC_MSIRANGE_8 Range 8 around 3.072 MHz
* @retval None
@@ -2753,6 +3440,25 @@
}
/**
+ * @brief Configure the MSIK range after standby mode.
+ * @note After Standby its frequency can be selected between 5 possible values (1, 1.33, 2, 3.072 or 4 MHz).
+ * @param MSIKRange MSIK range
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MSIKRANGE_4 Range 4 around 4 MHz (reset value)
+ * @arg @ref RCC_MSIKRANGE_5 Range 5 around 2 MHz
+ * @arg @ref RCC_MSIKRANGE_6 Range 6 around 1.33 MHz
+ * @arg @ref RCC_MSIKRANGE_7 Range 7 around 1 MHz
+ * @arg @ref RCC_MSIKRANGE_8 Range 8 around 3.072 MHz
+ * @retval None
+ */
+void HAL_RCCEx_StandbyMSIKRangeConfig(uint32_t MSIKRange)
+{
+ assert_param(IS_RCC_MSIK_STANDBY_CLOCK_RANGE(MSIKRange));
+
+ __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(MSIKRange);
+}
+
+/**
* @brief Enable the LSE Clock Security System.
* @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
* with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
@@ -2775,14 +3481,56 @@
}
/**
+ * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
+ * @note LSE Clock Security System Interrupt is mapped on EXTI line
+ * Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices.
+ * @retval None
+ */
+void HAL_RCCEx_EnableLSECSS_IT(void)
+{
+ /* Enable LSE CSS */
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+
+ /* Enable IT on LSECSS EXTI Line */
+ SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS);
+ /* Enable the RCC LSECSS EXTI Interrupt Rising Edge */
+ SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS);
+}
+
+/**
* @brief Handle the RCC LSE Clock Security System interrupt request.
+ * @note LSECSS EXTI is not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices.
* @retval None
*/
void HAL_RCCEx_LSECSS_IRQHandler(void)
{
+ uint32_t falling_edge_flag;
+ uint32_t rising_edge_flag;
+
if (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) != 0U)
{
- /* RCC LSE Clock Security System interrupt user callback */
+ /* Read Falling Edge flag on LSECSS EXTI interrupt */
+ falling_edge_flag = READ_BIT(EXTI->FPR1, RCC_EXTI_LINE_LSECSS);
+
+ /* Read Rising Edge flag on LSECSS EXTI interrupt */
+ rising_edge_flag = READ_BIT(EXTI->RPR1, RCC_EXTI_LINE_LSECSS);
+
+ /* Check Rising/falling Edge flag on LSECSS EXTI interrupt */
+ if ((falling_edge_flag == RCC_EXTI_LINE_LSECSS) || \
+ (rising_edge_flag == RCC_EXTI_LINE_LSECSS))
+ {
+ if (rising_edge_flag == RCC_EXTI_LINE_LSECSS)
+ {
+ /* Clear the RCC LSECSS EXTI Rising Edge flag */
+ WRITE_REG(EXTI->RPR1, RCC_EXTI_LINE_LSECSS);
+ }
+ if (falling_edge_flag == RCC_EXTI_LINE_LSECSS)
+ {
+ /* Clear the RCC LSECSS EXTI Falling Edge flag */
+ WRITE_REG(EXTI->FPR1, RCC_EXTI_LINE_LSECSS);
+ }
+ }
+ /* RCC LSECSS interrupt user callback */
HAL_RCCEx_LSECSS_Callback();
}
}
@@ -2799,6 +3547,61 @@
}
/**
+ * @brief Enable the MSI PLL Unlock Interrupt & corresponding EXTI line.
+ * @note MSI PLL Unlock Interrupt is mapped on EXTI line
+ * Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices.
+ * @retval None
+ */
+void HAL_RCCEx_EnableMSIPLLUNLCK_IT(void)
+{
+ /* Enable IT on MSI PLL Unlock EXTI Line */
+ SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_MSIPLLUNLCK);
+ /* Enable the RCC MSI PLL UNLOCK EXTI Interrupt Rising Edge */
+ SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_MSIPLLUNLCK);
+}
+
+/**
+ * @brief Handle the RCC MSI PLL Unlock interrupt request.
+ * @note Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices.
+ * @retval None
+ */
+void HAL_RCCEx_MSIPLLUNLCK_IRQHandler(void)
+{
+ uint32_t rising_edge_flag = READ_BIT(EXTI->RPR1, RCC_EXTI_LINE_MSIPLLUNLCK);
+ uint32_t falling_edge_flag = READ_BIT(EXTI->FPR1, RCC_EXTI_LINE_MSIPLLUNLCK);
+
+ /* Check Rising/falling Edge flag on MSI PLL UNLOCK EXTI interrupt */
+ if ((rising_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK) || \
+ (falling_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK))
+ {
+ if (rising_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK)
+ {
+ /* Clear the RCC MSI PLL UNLOCK EXTI Rising Edge flag */
+ WRITE_REG(EXTI->RPR1, RCC_EXTI_LINE_MSIPLLUNLCK);
+ }
+ if (falling_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK)
+ {
+ /* Clear the RCC MSI PLL UNLOCK EXTI Falling Edge flag */
+ WRITE_REG(EXTI->FPR1, RCC_EXTI_LINE_MSIPLLUNLCK);
+ }
+ /* RCC MSI PLL Unlock interrupt user callback */
+ HAL_RCCEx_MSIPLLUNLCK_Callback();
+ }
+}
+
+/**
+ * @brief RCCEx RCC MSI PLL Unlock interrupt callback.
+ * @note Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices.
+ * @retval none
+ */
+__weak void HAL_RCCEx_MSIPLLUNLCK_Callback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the @ref HAL_RCCEx_MSIPLLUNLCK_Callback should be implemented in the user file
+ */
+}
+
+/**
* @brief Select the Low Speed clock source to output on LSCO pin (PA2).
* @param LSCOSource specifies the Low Speed clock source to output.
* This parameter can be one of the following values:
@@ -2808,23 +3611,12 @@
*/
void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
{
- GPIO_InitTypeDef gpio_initstruct;
FlagStatus pwrclkchanged = RESET;
FlagStatus backupchanged = RESET;
/* Check the parameters */
assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
- /* LSCO Pin Clock Enable */
- LSCO_CLK_ENABLE();
-
- /* Configure the LSCO pin in analog mode */
- gpio_initstruct.Pin = LSCO_PIN;
- gpio_initstruct.Mode = GPIO_MODE_ANALOG;
- gpio_initstruct.Speed = GPIO_SPEED_FREQ_HIGH;
- gpio_initstruct.Pull = GPIO_NOPULL;
- HAL_GPIO_Init(LSCO_GPIO_PORT, &gpio_initstruct);
-
/* Update LSCOSEL clock source in Backup Domain control register */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
{
@@ -2905,7 +3697,6 @@
{
CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
}
-
/**
* @}
*/
@@ -2931,7 +3722,7 @@
(+++) Default values can be set for frequency Error Measurement (reload and error limit)
and also HSI48 oscillator smooth trimming.
(+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
- directly reload value with target and sychronization frequencies values
+ directly reload value with target and synchronization frequencies values
(##) Call function HAL_RCCEx_CRSConfig which
(+++) Resets CRS registers to their default values.
(+++) Configures CRS registers with synchronization configuration
@@ -3370,11 +4161,11 @@
* @brief Configure the PLL2 VCI ranges, multiplication and division factors and enable it
* @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that
* contains the configuration parameters as well as VCI clock ranges.
- * @note PLL2 is temporary disable to apply new parameters
+ * @note PLL2 is temporary disabled to apply new parameters
*
* @retval HAL status
*/
-static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2)
+static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2)
{
uint32_t tickstart;
@@ -3442,13 +4233,13 @@
}
/**
- * @brief Configure the parameters N & P & optionally M of PLL3 and enable PLL3 output clock(s).
- * @param pll3 pointer to an RCC_PLL3InitTypeDef structure that
- * contains the configuration parameters N & P & optionally M as well as PLL3 output clock(s)
- * @note PLL3 is temporary disable to apply new parameters
+ * @brief Configure the PLL3 VCI ranges, multiplication and division factors and enable it
+ * @param pll3: Pointer to an RCC_PLL3InitTypeDef structure that
+ * contains the configuration parameters as well as VCI clock ranges.
+ * @note PLL3 is temporary disabled to apply new parameters
* @retval HAL status
*/
-static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3)
+static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3)
{
uint32_t tickstart;
assert_param(IS_RCC_PLLSOURCE(pll3->PLL3Source));
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng.c
index 6a033c4..b8546c5 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng.c
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -43,8 +43,8 @@
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_RNG_RegisterCallback() to register a user callback.
- Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks:
+ Use Function HAL_RNG_RegisterCallback() to register a user callback.
+ Function HAL_RNG_RegisterCallback() allows to register following callbacks:
(+) ErrorCallback : RNG Error Callback.
(+) MspInitCallback : RNG MspInit.
(+) MspDeInitCallback : RNG MspDeInit.
@@ -52,9 +52,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
- @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default
+ weak (overridden) function.
+ HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) ErrorCallback : RNG Error Callback.
@@ -63,16 +63,16 @@
[..]
For specific callback ReadyDataCallback, use dedicated register callbacks:
- respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback().
+ respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback().
[..]
- By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
- all callbacks are set to the corresponding weak (surcharged) functions:
- example @ref HAL_RNG_ErrorCallback().
+ By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
+ all callbacks are set to the corresponding weak (overridden) functions:
+ example HAL_RNG_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init()
- and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit()
+ reset to the legacy weak (overridden) functions in the HAL_RNG_Init()
+ and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
@@ -81,13 +81,13 @@
in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit()
- or @ref HAL_RNG_Init() function.
+ using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit()
+ or HAL_RNG_Init() function.
[..]
When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -201,7 +201,6 @@
/* Clock Error Detection Configuration when CONDRT bit is set to 1 */
MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST);
-
/* Writing bit CONDRST=0 */
CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
@@ -387,8 +386,6 @@
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hrng);
if (HAL_RNG_STATE_READY == hrng->State)
{
@@ -442,14 +439,12 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hrng);
return status;
}
/**
* @brief Unregister an RNG Callback
- * RNG callabck is redirected to the weak predefined callback
+ * RNG callback is redirected to the weak predefined callback
* @param hrng RNG handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -462,8 +457,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hrng);
if (HAL_RNG_STATE_READY == hrng->State)
{
@@ -517,8 +510,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hrng);
return status;
}
@@ -681,8 +672,9 @@
be used as it may not have enough entropy */
if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
{
- /* Update the error code */
+ /* Update the error code and status */
hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+ status = HAL_ERROR;
/* Clear bit DRDY */
CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY);
}
@@ -762,18 +754,19 @@
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
{
uint32_t rngclockerror = 0U;
+ uint32_t itflag = hrng->Instance->SR;
/* RNG clock error interrupt occurred */
- if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
+ if ((itflag & RNG_IT_CEI) == RNG_IT_CEI)
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
rngclockerror = 1U;
}
- else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+ else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI)
{
/* Check if Seed Error Current Status (SECS) is set */
- if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) == RESET)
+ if ((itflag & RNG_FLAG_SECS) != RNG_FLAG_SECS)
{
/* RNG IP performed the reset automatically (auto-reset) */
/* Clear bit SEIS */
@@ -813,7 +806,7 @@
}
/* Check RNG data ready interrupt occurred */
- if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
+ if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY)
{
/* Generate random number once, so disable the IT */
__HAL_RNG_DISABLE_IT(hrng);
@@ -845,7 +838,7 @@
* the configuration information for RNG.
* @retval random value
*/
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
+uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng)
{
return (hrng->RandomNumber);
}
@@ -912,7 +905,7 @@
* the configuration information for RNG.
* @retval HAL state
*/
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
+HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng)
{
return hrng->State;
}
@@ -922,7 +915,7 @@
* @param hrng: pointer to a RNG_HandleTypeDef structure.
* @retval RNG Error Code
*/
-uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
+uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng)
{
/* Return RNG Error Code */
return hrng->ErrorCode;
@@ -1032,3 +1025,4 @@
/**
* @}
*/
+
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng_ex.c
index cc78714..f5a7279 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng_ex.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rng_ex.c
@@ -11,7 +11,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -31,7 +31,7 @@
#if defined(RNG)
-/** @addtogroup RNGEx
+/** @addtogroup RNG_Ex
* @brief RNG Extended HAL module driver.
* @{
*/
@@ -42,7 +42,7 @@
/* Private defines -----------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Constants RNGEx Private Constants
+/** @addtogroup RNG_Ex_Private_Constants
* @{
*/
#define RNG_TIMEOUT_VALUE 2U
@@ -54,11 +54,11 @@
/* Private functions --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RNGEx_Exported_Functions
+/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions
* @{
*/
-/** @addtogroup RNGEx_Exported_Functions_Group1
+/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions
* @brief Configuration functions
*
@verbatim
@@ -78,12 +78,12 @@
* RNG_ConfigTypeDef.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
- * @param pConf: pointer to a RNG_ConfigTypeDef structure that contains
+ * @param pConf pointer to a RNG_ConfigTypeDef structure that contains
* the configuration information for RNG module
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
+HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf)
{
uint32_t tickstart;
uint32_t cr_value;
@@ -124,7 +124,7 @@
| (pConf->Config3 << RNG_CR_RNG_CONFIG3_Pos));
MODIFY_REG(hrng->Instance->CR, RNG_CR_NISTC | RNG_CR_CLKDIV | RNG_CR_RNG_CONFIG1
- | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3,
+ | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3 | RNG_CR_ARDIS,
(uint32_t)(RNG_CR_CONDRST | cr_value));
/* RNG health test control in accordance with NIST */
@@ -174,7 +174,7 @@
* RNG_ConfigTypeDef.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
- * @param pConf: pointer to a RNG_ConfigTypeDef structure that contains
+ * @param pConf pointer to a RNG_ConfigTypeDef structure that contains
* the configuration information for RNG module
* @retval HAL status
@@ -270,12 +270,12 @@
* @}
*/
-/** @addtogroup RNGEx_Exported_Functions_Group2
+/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function
* @brief Recover from seed error function
*
@verbatim
===============================================================================
- ##### Configuration and lock functions #####
+ ##### Recover from seed error function #####
===============================================================================
[..] This section provide function allowing to:
(+) Recover from a seed error
@@ -337,3 +337,4 @@
/**
* @}
*/
+
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc.c
index 062162f..7edd7be 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc.c
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -26,7 +26,7 @@
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
- *******************************************************************************
+ ******************************************************************************
@verbatim
===============================================================================
##### RTC Operating Condition #####
@@ -363,39 +363,50 @@
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Enter Initialization mode */
- status = RTC_EnterInitMode(hrtc);
- if (status == HAL_OK)
+ /* Check if the calendar has been not initialized */
+ if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U)
{
- /* Clear RTC_CR FMT, OSEL and POL Bits */
- CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE));
- /* Set RTC_CR register */
- SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity));
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Configure the RTC PRER */
- WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos)));
-
- /* Configure the Binary mode */
- MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU);
-
- /* Exit Initialization mode */
- status = RTC_ExitInitMode(hrtc);
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
if (status == HAL_OK)
{
- MODIFY_REG(RTC->CR, \
- RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \
- hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
- }
- }
+ /* Clear RTC_CR FMT, OSEL and POL Bits */
+ CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE));
+ /* Set RTC_CR register */
+ SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity));
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Configure the RTC PRER */
+ WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos)));
+
+ /* Configure the Binary mode */
+ MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU);
+
+ /* Exit Initialization mode */
+ status = RTC_ExitInitMode(hrtc);
+ if (status == HAL_OK)
+ {
+ MODIFY_REG(RTC->CR, \
+ RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \
+ hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ }
+ else
+ {
+ /* Calendar is already initialized */
+ /* Set flag to OK */
+ status = HAL_OK;
+ }
if (status == HAL_OK)
{
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
}
@@ -1057,7 +1068,7 @@
* @param hrtc RTC handle
* @retval None
*/
-void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc)
+void HAL_RTC_DST_Add1Hour(const RTC_HandleTypeDef *hrtc)
{
UNUSED(hrtc);
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
@@ -1071,7 +1082,7 @@
* @param hrtc RTC handle
* @retval None
*/
-void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc)
+void HAL_RTC_DST_Sub1Hour(const RTC_HandleTypeDef *hrtc)
{
UNUSED(hrtc);
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
@@ -1085,12 +1096,10 @@
* @param hrtc RTC handle
* @retval None
*/
-void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc)
+void HAL_RTC_DST_SetStoreOperation(const RTC_HandleTypeDef *hrtc)
{
UNUSED(hrtc);
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
SET_BIT(RTC->CR, RTC_CR_BKP);
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
/**
@@ -1098,12 +1107,10 @@
* @param hrtc RTC handle
* @retval None
*/
-void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc)
+void HAL_RTC_DST_ClearStoreOperation(const RTC_HandleTypeDef *hrtc)
{
UNUSED(hrtc);
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
CLEAR_BIT(RTC->CR, RTC_CR_BKP);
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
/**
@@ -1111,7 +1118,7 @@
* @param hrtc RTC handle
* @retval operation see RTC_StoreOperation_Definitions
*/
-uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc)
+uint32_t HAL_RTC_DST_ReadStoreOperation(const RTC_HandleTypeDef *hrtc)
{
UNUSED(hrtc);
return READ_BIT(RTC->CR, RTC_CR_BKP);
@@ -1142,20 +1149,21 @@
* @arg RTC_FORMAT_BCD: BCD format
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
uint32_t tmpreg;
UNUSED(hrtc);
- /* Get subseconds structure field from the corresponding register*/
+ /* Get subseconds structure field from the corresponding register */
sTime->SubSeconds = READ_REG(RTC->SSR);
+
if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) != RTC_BINARY_ONLY)
{
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
- /* Get SecondFraction structure field from the corresponding register field*/
+ /* Get SecondFraction structure field from the corresponding register field */
sTime->SecondFraction = (uint32_t)(READ_REG(RTC->PRER) & RTC_PRER_PREDIV_S);
/* Get the TR register */
@@ -1176,6 +1184,15 @@
sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
}
}
+ else
+ {
+ /* Initialize structure fields */
+ sTime->Hours = 0U;
+ sTime->Minutes = 0U;
+ sTime->Seconds = 0U;
+ sTime->TimeFormat = 0U;
+ sTime->SecondFraction = 0U;
+ }
return HAL_OK;
}
@@ -1274,7 +1291,7 @@
* @arg RTC_FORMAT_BCD: BCD format
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
uint32_t datetmpreg;
@@ -1446,8 +1463,6 @@
}
}
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Configure the Alarm register */
if (sAlarm->Alarm == RTC_ALARM_A)
@@ -1516,8 +1531,6 @@
SET_BIT(RTC->CR, RTC_CR_ALRBE);
}
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -1656,8 +1669,6 @@
}
}
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Configure the Alarm registers */
if (sAlarm->Alarm == RTC_ALARM_A)
@@ -1728,8 +1739,6 @@
}
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_READY;
@@ -1758,8 +1767,6 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* In case of interrupt mode is used, the interrupt source must disabled */
if (Alarm == RTC_ALARM_A)
@@ -1775,8 +1782,6 @@
CLEAR_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_SSCLR);
}
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_READY;
@@ -1800,7 +1805,8 @@
* @arg RTC_FORMAT_BCD: BCD format
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
+HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm,
+ uint32_t Format)
{
uint32_t tmpreg;
uint32_t subsecondtmpreg;
@@ -1868,7 +1874,7 @@
/* Get interrupt status */
uint32_t tmp = READ_REG(RTC->SMISR);
- if ((tmp & RTC_SMISR_ALRAMF) != 0u)
+ if ((tmp & RTC_SMISR_ALRAMF) != 0U)
{
/* Clear the AlarmA interrupt pending bit */
WRITE_REG(RTC->SCR, RTC_SCR_CALRAF);
@@ -1880,7 +1886,7 @@
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
}
- if ((tmp & RTC_SMISR_ALRBMF) != 0u)
+ if ((tmp & RTC_SMISR_ALRBMF) != 0U)
{
/* Clear the AlarmB interrupt pending bit */
WRITE_REG(RTC->SCR, RTC_SCR_CALRBF);
@@ -1961,8 +1967,11 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
uint32_t tickstart = HAL_GetTick();
while (READ_BIT(RTC->SR, RTC_SR_ALRAF) == 0U)
@@ -1971,8 +1980,15 @@
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RTC->SR, RTC_SR_ALRAF) == 0U)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ break;
+ }
}
}
}
@@ -1980,9 +1996,6 @@
/* Clear the Alarm interrupt pending bit */
WRITE_REG(RTC->SCR, RTC_SCR_CALRAF);
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
return HAL_OK;
}
@@ -2023,7 +2036,6 @@
{
uint32_t tickstart;
- UNUSED(hrtc);
/* Clear RSF flag */
CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF);
@@ -2034,7 +2046,17 @@
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U)
+ {
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ break;
+ }
}
}
@@ -2064,7 +2086,7 @@
* @param hrtc RTC handle
* @retval HAL state
*/
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc)
+HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc)
{
/* Return RTC handle state */
return hrtc->State;
@@ -2092,7 +2114,6 @@
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
- UNUSED(hrtc);
/* Check if the Initialization mode is set */
if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
{
@@ -2105,8 +2126,18 @@
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
- status = HAL_TIMEOUT;
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
+ {
+ status = HAL_TIMEOUT;
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ }
+ else
+ {
+ break;
+ }
}
}
}
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc_ex.c
index 8d450bb..83335c2 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc_ex.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_rtc_ex.c
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -186,14 +186,10 @@
/* Get the RTC_CR register and clear the bits to be configured */
CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE));
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Configure the Time Stamp TSEDGE and Enable bits */
SET_BIT(RTC->CR, (uint32_t)TimeStampEdge | RTC_CR_TSE);
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -237,8 +233,6 @@
/* Get the RTC_CR register and clear the bits to be configured */
CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE));
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Configure the Time Stamp TSEDGE before Enable bit to avoid unwanted TSF setting. */
SET_BIT(RTC->CR, (uint32_t)TimeStampEdge);
@@ -246,8 +240,6 @@
/* Enable timestamp and IT */
SET_BIT(RTC->CR, RTC_CR_TSE | RTC_CR_TSIE);
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_READY;
@@ -269,14 +261,10 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* In case of interrupt mode is used, the interrupt source must disabled */
CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE));
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_READY;
@@ -299,14 +287,10 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Configure the internal Time Stamp Enable bits */
SET_BIT(RTC->CR, RTC_CR_ITSE);
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -327,16 +311,13 @@
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Configure the internal Time Stamp Enable bits */
CLEAR_BIT(RTC->CR, RTC_CR_ITSE);
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_READY;
@@ -361,8 +342,9 @@
RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
{
uint32_t tmptime;
- uint32_t tmpdate;
+ uint32_t tmpdate;
+ /* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -404,41 +386,19 @@
return HAL_OK;
}
+/**
+ * @brief Handle TimeStamp interrupt request.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ /* Get the pending status of the TimeStamp Interrupt */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- * @brief Handle TimeStamp secure interrupt request.
- * @param hrtc RTC handle
- * @retval None
- */
-void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
-{
if (READ_BIT(RTC->SMISR, RTC_SMISR_TSMF) != 0U)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call TimeStampEvent registered Callback */
- hrtc->TimeStampEventCallback(hrtc);
#else
- HAL_RTCEx_TimeStampEventCallback(hrtc);
-#endif /*(USE_HAL_RTC_REGISTER_CALLBACKS == 1)*/
- /* Clearing flags after the Callback because the content of RTC_TSTR and RTC_TSDR are cleared when
- TSF bit is reset.*/
- WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSF);
- }
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-}
-
-#else /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/**
- * @brief Handle TimeStamp non-secure interrupt request.
- * @param hrtc RTC handle
- * @retval None
- */
-void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
-{
if (READ_BIT(RTC->MISR, RTC_MISR_TSMF) != 0U)
+#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
{
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
/* Call TimeStampEvent registered Callback */
@@ -447,14 +407,13 @@
HAL_RTCEx_TimeStampEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
/* Clearing flags after the Callback because the content of RTC_TSTR and RTC_TSDR are cleared when
- TSF bit is reset.*/
+ TSF bit is reset.*/
WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSF);
}
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
-#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @brief TimeStamp callback.
@@ -479,6 +438,9 @@
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
uint32_t tickstart = HAL_GetTick();
while (READ_BIT(RTC->SR, RTC_SR_TSF) == 0U)
@@ -488,9 +450,6 @@
/* Clear the TIMESTAMP OverRun Flag */
WRITE_REG(RTC->SCR, RTC_SCR_CTSOVF);
- /* Change TIMESTAMP state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
return HAL_ERROR;
}
@@ -498,15 +457,19 @@
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RTC->SR, RTC_SR_TSF) == 0U)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ break;
+ }
}
}
}
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
return HAL_OK;
}
@@ -546,10 +509,9 @@
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Clear WUTE in RTC_CR to disable the wakeup timer */
CLEAR_BIT(RTC->CR, RTC_CR_WUTE);
@@ -560,19 +522,27 @@
if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
{
tickstart = HAL_GetTick();
+
while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
+ {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ break;
+ }
}
}
}
@@ -586,9 +556,8 @@
/* Enable the Wakeup Timer */
SET_BIT(RTC->CR, RTC_CR_WUTE);
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
@@ -622,10 +591,9 @@
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Clear WUTE in RTC_CR to disable the wakeup timer */
CLEAR_BIT(RTC->CR, RTC_CR_WUTE);
@@ -643,15 +611,22 @@
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
+ {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ break;
+ }
}
}
}
@@ -665,9 +640,8 @@
/* Configure the Interrupt in the RTC_CR register and Enable the Wakeup Timer*/
SET_BIT(RTC->CR, (RTC_CR_WUTIE | RTC_CR_WUTE));
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
@@ -688,36 +662,44 @@
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Disable the Wakeup Timer */
/* In case of interrupt mode is used, the interrupt source must disabled */
CLEAR_BIT(RTC->CR, (RTC_CR_WUTE | RTC_CR_WUTIE));
tickstart = HAL_GetTick();
+
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
+ {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ break;
+ }
}
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
@@ -733,46 +715,25 @@
*/
uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
{
+ /* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
/* Get the counter value */
return (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT));
}
+/**
+ * @brief Handle Wake Up Timer interrupt request.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ /* Get the pending status of the Wake-Up Timer Interrupt */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- * @brief Handle Wake Up Timer secure interrupt request.
- * @param hrtc RTC handle
- * @retval None
- */
-void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
-{
- if ((RTC->SMISR & RTC_SMISR_WUTMF) != 0u)
- {
- /* Immediately clear flags */
- WRITE_REG(RTC->SCR, RTC_SCR_CWUTF);
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call wake up timer registered Callback */
- hrtc->WakeUpTimerEventCallback(hrtc);
+ if (READ_BIT(RTC->SMISR, RTC_SMISR_WUTMF) != 0U)
#else
- HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-}
-
-#else /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/**
- * @brief Handle Wake Up Timer non-secure interrupt request.
- * @param hrtc RTC handle
- * @retval None
- */
-void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
-{
- /* Get the pending status of the WAKEUPTIMER Interrupt */
if (READ_BIT(RTC->MISR, RTC_MISR_WUTMF) != 0U)
+#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
{
/* Clear the WAKEUPTIMER interrupt pending bit */
WRITE_REG(RTC->SCR, RTC_SCR_CWUTF);
@@ -789,7 +750,6 @@
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
-#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @brief Wake Up Timer callback.
@@ -806,7 +766,6 @@
*/
}
-
/**
* @brief Handle Wake Up Timer Polling.
* @param hrtc RTC handle
@@ -815,6 +774,9 @@
*/
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
uint32_t tickstart = HAL_GetTick();
while (READ_BIT(RTC->SR, RTC_SR_WUTF) == 0U)
@@ -823,8 +785,15 @@
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RTC->SR, RTC_SR_WUTF) == 0U)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ break;
+ }
}
}
}
@@ -870,8 +839,6 @@
* @{
*/
-
-
/**
* @brief Set the Smooth calibration parameters.
* @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
@@ -879,7 +846,7 @@
* SmoothCalibMinusPulsesValue must be equal to 0.
* @param hrtc RTC handle
* @param SmoothCalibPeriod Select the Smooth Calibration Period.
- * This parameter can be can be one of the following values :
+ * This parameter can be one of the following values :
* @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
* @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
* @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
@@ -904,23 +871,20 @@
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* check if a calibration is pending*/
- if (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U)
+ tickstart = HAL_GetTick();
+
+ /* check if a calibration is pending */
+ while (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U)
{
- tickstart = HAL_GetTick();
-
- /* check if a calibration is pending*/
- while (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U)
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U)
{
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_TIMEOUT;
@@ -930,8 +894,14 @@
return HAL_TIMEOUT;
}
+ else
+ {
+ break;
+ }
}
}
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Configure the Smooth calibration settings */
MODIFY_REG(RTC->CALR, (RTC_CALR_CALP | RTC_CALR_CALW8 | RTC_CALR_CALW16 | RTC_CALR_CALM),
@@ -966,6 +936,7 @@
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
/* Disable the write protection for RTC registers */
@@ -1009,30 +980,39 @@
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
tickstart = HAL_GetTick();
- /* Wait until the shift is completed*/
+ /* Wait until the shift is completed */
while (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) != 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) != 0U)
+ {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ break;
+ }
}
}
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
/* Check if the reference clock detection is disabled */
if (READ_BIT(RTC->CR, RTC_CR_REFCKON) == 0U)
{
@@ -1047,6 +1027,7 @@
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
/* Process Unlocked */
@@ -1099,10 +1080,9 @@
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Configure the RTC_CR register */
MODIFY_REG(RTC->CR, RTC_CR_COSEL, CalibOutput);
@@ -1110,8 +1090,6 @@
/* Enable calibration output */
SET_BIT(RTC->CR, RTC_CR_COE);
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -1132,16 +1110,13 @@
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Disable calibration output */
CLEAR_BIT(RTC->CR, RTC_CR_COE);
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -1164,6 +1139,7 @@
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
/* Disable the write protection for RTC registers */
@@ -1185,6 +1161,7 @@
if (status == HAL_OK)
{
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
@@ -1206,6 +1183,7 @@
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
/* Disable the write protection for RTC registers */
@@ -1227,6 +1205,7 @@
if (status == HAL_OK)
{
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
@@ -1248,16 +1227,13 @@
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Set the BYPSHAD bit */
SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -1280,16 +1256,13 @@
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Reset the BYPSHAD bit */
CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD);
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -1310,6 +1283,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance)
{
+ /* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
UNUSED(Instance);
/* This register is read-only only and is incremented by one when a write access is done to this
@@ -1330,6 +1304,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t Instance, uint32_t *Value)
{
+ /* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
UNUSED(Instance);
@@ -1350,17 +1325,15 @@
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Enable IT SSRU */
__HAL_RTC_SSRU_ENABLE_IT(hrtc, RTC_IT_SSRU);
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
@@ -1379,17 +1352,15 @@
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_SSRU_DISABLE_IT(hrtc, RTC_IT_TS);
+ __HAL_RTC_SSRU_DISABLE_IT(hrtc, RTC_IT_SSRU);
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
@@ -1398,7 +1369,6 @@
return HAL_OK;
}
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Handle SSR underflow interrupt request.
* @param hrtc RTC handle
@@ -1406,10 +1376,15 @@
*/
void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc)
{
- if ((RTC->SMISR & RTC_SMISR_SSRUMF) != 0u)
+ /* Get the pending status of the SSR Underflow Interrupt */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ if (READ_BIT(RTC->SMISR, RTC_SMISR_SSRUMF) != 0U)
+#else
+ if (READ_BIT(RTC->MISR, RTC_MISR_SSRUMF) != 0U)
+#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
{
- /* Immediately clear flags */
- RTC->SCR = RTC_SCR_CSSRUF;
+ /* Immediately clear SSR underflow flag */
+ WRITE_REG(RTC->SCR, RTC_SCR_CSSRUF);
/* SSRU callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@@ -1424,32 +1399,7 @@
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
-#else
-/**
- * @brief Handle SSR underflow interrupt request.
- * @param hrtc RTC handle
- * @retval None
- */
-void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc)
-{
- if ((RTC->MISR & RTC_MISR_SSRUMF) != 0u)
- {
- /* Immediately clear flags */
- RTC->SCR = RTC_SCR_CSSRUF;
- /* SSRU callback */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call SSRUEvent registered Callback */
- hrtc->SSRUEventCallback(hrtc);
-#else
- HAL_RTCEx_SSRUEventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @brief SSR underflow callback.
* @param hrtc RTC handle
@@ -1505,8 +1455,11 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
uint32_t tickstart = HAL_GetTick();
while (READ_BIT(RTC->SR, RTC_SR_ALRBF) == 0U)
@@ -1515,8 +1468,15 @@
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RTC->SR, RTC_SR_ALRBF) == 0U)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ break;
+ }
}
}
}
@@ -1524,9 +1484,6 @@
/* Clear the Alarm Flag */
WRITE_REG(RTC->SCR, RTC_SCR_CALRBF);
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
return HAL_OK;
}
@@ -1623,9 +1580,7 @@
/* Timestamp on tamper */
if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection)
{
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection);
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
/* Control register 1 */
@@ -1695,9 +1650,7 @@
/* Timestamp on tamper */
if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection)
{
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection);
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
/* Interrupt enable register */
@@ -1785,9 +1738,7 @@
CR = READ_REG(RTC->CR);
if ((CR & RTC_CR_TAMPTS) != (sAllTamper->TimeStampOnTamperDetection))
{
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sAllTamper->TimeStampOnTamperDetection);
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
CR1 = READ_REG(TAMP->CR1);
@@ -1824,7 +1775,7 @@
}
/* Configure ATOSELx[] in case of output sharing */
- ATCR2 |= sAllTamper->TampInput[i].Output << ((3u * i) + TAMP_ATCR2_ATOSEL1_Pos);
+ ATCR2 |= sAllTamper->TampInput[i].Output << ((3U * i) + TAMP_ATCR2_ATOSEL1_Pos);
if (i != sAllTamper->TampInput[i].Output)
{
@@ -1846,14 +1797,24 @@
WRITE_REG(TAMP->ATSEEDR, sAllTamper->Seed[i]);
}
- /* Wait till RTC SEEDF flag is set and if Time out is reached exit */
+ /* Wait till RTC SEEDF flag is cleared and if Time out is reached exit */
tickstart = HAL_GetTick();
- while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0u)
+ while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U)
+ {
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ break;
+ }
}
}
@@ -1907,14 +1868,24 @@
WRITE_REG(TAMP->ATSEEDR, pSeed[i]);
}
- /* Wait till RTC SEEDF flag is set and if Time out is reached exit */
+ /* Wait till RTC SEEDF flag is cleared and if Time out is reached exit */
tickstart = HAL_GetTick();
while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U)
+ {
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ break;
+ }
}
}
@@ -1930,6 +1901,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_SetBoothardwareKey(RTC_HandleTypeDef *hrtc)
{
+ /* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
WRITE_REG(TAMP->SECCFGR, TAMP_SECCFGR_BHKLOCK);
@@ -1987,7 +1959,9 @@
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout)
{
+ /* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
+
assert_param(IS_RTC_TAMPER(Tamper));
uint32_t tickstart = HAL_GetTick();
@@ -1999,7 +1973,15 @@
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(TAMP->SR, Tamper) != Tamper)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ break;
+ }
}
}
}
@@ -2030,11 +2012,11 @@
/* timestamp on internal tamper */
if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection)
{
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection);
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
}
+ /* No Erase Backup register enable for Internal Tamper */
if (sIntTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
{
/* Control register 3 */
@@ -2089,9 +2071,7 @@
/* timestamp on internal tamper */
if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection)
{
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection);
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
/* Interrupt enable register */
@@ -2121,7 +2101,9 @@
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper)
{
+ /* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
+
assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper));
/* Disable the selected Tamper pin */
@@ -2147,7 +2129,9 @@
*/
HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout)
{
+ /* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
+
assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper));
uint32_t tickstart = HAL_GetTick();
@@ -2159,7 +2143,15 @@
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(TAMP->SR, IntTamper) != IntTamper)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ break;
+ }
}
}
}
@@ -2170,22 +2162,19 @@
return HAL_OK;
}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/** @brief Handle Tamper secure interrupt request.
+/**
+ * @brief Handle Tamper interrupt request.
* @param hrtc RTC handle
* @retval None
*/
void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc)
{
- uint32_t tmp;
-
- /* Get secure interrupt status */
- tmp = READ_REG(TAMP->SMISR);
-
- /* Immediately clear flags */
- WRITE_REG(TAMP->SCR, tmp);
+ /* Get the pending status of the Tampers Interrupt */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ uint32_t tmp = READ_REG(TAMP->SMISR);
+#else
+ uint32_t tmp = READ_REG(TAMP->MISR);
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* Check Tamper1 status */
if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1)
@@ -2413,247 +2402,10 @@
HAL_RTCEx_InternalTamper13EventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
}
-}
-
-#else
-/**
- * @brief Handle Tamper non-secure interrupt request.
- * @param hrtc RTC handle
- * @retval None
- */
-void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc)
-{
- /* Get interrupt status */
- uint32_t tmp = READ_REG(TAMP->MISR);
-
- /* Immediately clear flags */
+ /* Clear flags after treatment to allow the potential tamper feature */
WRITE_REG(TAMP->SCR, tmp);
-
- /* Check Tamper1 status */
- if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Tamper 1 Event registered Callback */
- hrtc->Tamper1EventCallback(hrtc);
-#else
- /* Tamper1 callback */
- HAL_RTCEx_Tamper1EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
-
- /* Check Tamper2 status */
- if ((tmp & RTC_TAMPER_2) == RTC_TAMPER_2)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Tamper 2 Event registered Callback */
- hrtc->Tamper2EventCallback(hrtc);
-#else
- /* Tamper2 callback */
- HAL_RTCEx_Tamper2EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
-
- /* Check Tamper3 status */
- if ((tmp & RTC_TAMPER_3) == RTC_TAMPER_3)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Tamper 3 Event registered Callback */
- hrtc->Tamper3EventCallback(hrtc);
-#else
- /* Tamper3 callback */
- HAL_RTCEx_Tamper3EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
-
- /* Check Tamper4 status */
- if ((tmp & RTC_TAMPER_4) == RTC_TAMPER_4)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Tamper 4 Event registered Callback */
- hrtc->Tamper4EventCallback(hrtc);
-#else
- /* Tamper4 callback */
- HAL_RTCEx_Tamper4EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
-
- /* Check Tamper5 status */
- if ((tmp & RTC_TAMPER_5) == RTC_TAMPER_5)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Tamper 5 Event registered Callback */
- hrtc->Tamper5EventCallback(hrtc);
-#else
- /* Tamper5 callback */
- HAL_RTCEx_Tamper5EventCallback(hrtc);
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
- }
-
- /* Check Tamper6 status */
- if ((tmp & RTC_TAMPER_6) == RTC_TAMPER_6)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Tamper 6 Event registered Callback */
- hrtc->Tamper6EventCallback(hrtc);
-#else
- /* Tamper6 callback */
- HAL_RTCEx_Tamper6EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
-
- /* Check Tamper7 status */
- if ((tmp & RTC_TAMPER_7) == RTC_TAMPER_7)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Tamper 7 Event registered Callback */
- hrtc->Tamper7EventCallback(hrtc);
-#else
- /* Tamper7 callback */
- HAL_RTCEx_Tamper7EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
-
- /* Check Tamper8 status */
- if ((tmp & RTC_TAMPER_8) == RTC_TAMPER_8)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Tamper 8 Event registered Callback */
- hrtc->Tamper8EventCallback(hrtc);
-#else
- /* Tamper8 callback */
- HAL_RTCEx_Tamper8EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
-
- /* Check Internal Tamper1 status */
- if ((tmp & RTC_INT_TAMPER_1) == RTC_INT_TAMPER_1)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Internal Tamper 1 Event registered Callback */
- hrtc->InternalTamper1EventCallback(hrtc);
-#else
- /* Internal Tamper1 callback */
- HAL_RTCEx_InternalTamper1EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
-
- /* Check Internal Tamper2 status */
- if ((tmp & RTC_INT_TAMPER_2) == RTC_INT_TAMPER_2)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Internal Tamper 2 Event registered Callback */
- hrtc->InternalTamper2EventCallback(hrtc);
-#else
- /* Internal Tamper2 callback */
- HAL_RTCEx_InternalTamper2EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
-
- /* Check Internal Tamper3 status */
- if ((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Internal Tamper 3 Event registered Callback */
- hrtc->InternalTamper3EventCallback(hrtc);
-#else
- /* Internal Tamper3 callback */
- HAL_RTCEx_InternalTamper3EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
-
- /* Check Internal Tamper5 status */
- if ((tmp & RTC_INT_TAMPER_5) == RTC_INT_TAMPER_5)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Internal Tamper 5 Event registered Callback */
- hrtc->InternalTamper5EventCallback(hrtc);
-#else
- /* Internal Tamper5 callback */
- HAL_RTCEx_InternalTamper5EventCallback(hrtc);
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
- }
- /* Check Internal Tamper6 status */
- if ((tmp & RTC_INT_TAMPER_6) == RTC_INT_TAMPER_6)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Internal Tamper 6 Event registered Callback */
- hrtc->InternalTamper6EventCallback(hrtc);
-#else
- /* Internal Tamper6 callback */
- HAL_RTCEx_InternalTamper6EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
- /* Check Internal Tamper7 status */
- if ((tmp & RTC_INT_TAMPER_7) == RTC_INT_TAMPER_7)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Internal Tamper 7 Event registered Callback */
- hrtc->InternalTamper7EventCallback(hrtc);
-#else
- /* Internal Tamper7 callback */
- HAL_RTCEx_InternalTamper7EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
- /* Check Internal Tamper8 status */
- if ((tmp & RTC_INT_TAMPER_8) == RTC_INT_TAMPER_8)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Internal Tamper 8 Event registered Callback */
- hrtc->InternalTamper8EventCallback(hrtc);
-#else
- /* Internal Tamper8 callback */
- HAL_RTCEx_InternalTamper8EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
- /* Check Internal Tamper9 status */
- if ((tmp & RTC_INT_TAMPER_9) == RTC_INT_TAMPER_9)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Internal Tamper 9 Event registered Callback */
- hrtc->InternalTamper9EventCallback(hrtc);
-#else
- /* Internal Tamper9 callback */
- HAL_RTCEx_InternalTamper9EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
- /* Check Internal Tamper11 status */
- if ((tmp & RTC_INT_TAMPER_11) == RTC_INT_TAMPER_11)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Internal Tamper 11 Event registered Callback */
- hrtc->InternalTamper11EventCallback(hrtc);
-#else
- /* Internal Tamper11 callback */
- HAL_RTCEx_InternalTamper11EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
-
- /* Check Internal Tamper12 status */
- if ((tmp & RTC_INT_TAMPER_12) == RTC_INT_TAMPER_12)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Internal Tamper 12 Event registered Callback */
- hrtc->InternalTamper12EventCallback(hrtc);
-#else
- /* Internal Tamper12 callback */
- HAL_RTCEx_InternalTamper12EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
-
- /* Check Internal Tamper13 status */
- if ((tmp & RTC_INT_TAMPER_13) == RTC_INT_TAMPER_13)
- {
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- /* Call Internal Tamper 13 Event registered Callback */
- hrtc->InternalTamper13EventCallback(hrtc);
-#else
- /* Internal Tamper13 callback */
- HAL_RTCEx_InternalTamper13EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
- }
}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @brief Tamper 1 callback.
@@ -2670,7 +2422,6 @@
*/
}
-
/**
* @brief Tamper 2 callback.
* @param hrtc RTC handle
@@ -2956,7 +2707,7 @@
[..]
(+) Before calling any tamper or internal tamper function, you have to call first
HAL_RTC_Init() function.
- (+) In that ine you can select to output tamper event on RTC pin.
+ (+) In that one you can select to output tamper event on RTC pin.
[..]
This subsection provides functions allowing to
(+) Write a data in a specified RTC Backup data register
@@ -2978,7 +2729,9 @@
{
uint32_t tmp;
+ /* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
+
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
@@ -3001,6 +2754,7 @@
{
uint32_t tmp;
+ /* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
@@ -3114,6 +2868,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState)
{
+ /* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
/* Read registers */
uint32_t rtc_seccfgr = READ_REG(RTC->SECCFGR);
@@ -3123,7 +2878,7 @@
secureState->rtcSecureFull = READ_BIT(rtc_seccfgr, RTC_SECCFGR_SEC);
/* Warning, rtcNonSecureFeatures is only relevant if secureState->rtcSecureFull == RTC_SECURE_FULL_NO */
- secureState->rtcNonSecureFeatures = READ_BIT(rtc_seccfgr, RTC_NONSECURE_FEATURE_ALL);
+ secureState->rtcNonSecureFeatures = READ_BIT(rtc_seccfgr, RTC_NONSECURE_FEATURE_NONE);
/* TAMP */
secureState->tampSecureFull = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_TAMPSEC);
@@ -3150,6 +2905,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState)
{
+ /* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
assert_param(IS_RTC_SECURE_FULL(secureState->rtcSecureFull));
assert_param(IS_RTC_NONSECURE_FEATURES(secureState->rtcNonSecureFeatures));
@@ -3202,6 +2958,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeSet(RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState)
{
+ /* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
assert_param(IS_RTC_PRIVILEGE_FULL(privilegeState->rtcPrivilegeFull));
assert_param(IS_RTC_PRIVILEGE_FEATURES(privilegeState->rtcPrivilegeFeatures));
@@ -3243,12 +3000,14 @@
*/
HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
/* Read registers */
uint32_t rtc_privcfgr = READ_REG(RTC->PRIVCFGR);
uint32_t tamp_privcfgr = READ_REG(TAMP->PRIVCFGR);
uint32_t tamp_seccfgr = READ_REG(TAMP->SECCFGR);
- UNUSED(hrtc);
/* RTC privilege configuration */
privilegeState->rtcPrivilegeFull = READ_BIT(rtc_privcfgr, RTC_PRIVCFGR_PRIV);
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart.c
index ab26270..9eb4e1b 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart.c
@@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -88,8 +88,8 @@
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_UART_RegisterCallback() to register a user callback.
- Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:
+ Use Function HAL_UART_RegisterCallback() to register a user callback.
+ Function HAL_UART_RegisterCallback() allows to register following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
(+) TxCpltCallback : Tx Complete Callback.
(+) RxHalfCpltCallback : Rx Half Complete Callback.
@@ -107,9 +107,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
- @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
@@ -128,16 +128,16 @@
[..]
For specific callback RxEventCallback, use dedicated registration/reset functions:
- respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback().
+ respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback().
[..]
- By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
- all callbacks are set to the corresponding weak (surcharged) functions:
- examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
+ By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()
- and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()
+ reset to the legacy weak functions in the HAL_UART_Init()
+ and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
@@ -146,16 +146,17 @@
in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()
- or @ref HAL_UART_Init() function.
+ using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit()
+ or HAL_UART_Init() function.
[..]
When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -197,8 +198,9 @@
/** @addtogroup UART_Private_Functions
* @{
*/
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+#if defined(HAL_DMA_MODULE_ENABLED)
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
@@ -209,6 +211,7 @@
static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+#endif /* HAL_DMA_MODULE_ENABLED */
static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
@@ -348,17 +351,19 @@
__HAL_UART_DISABLE(huart);
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
{
return HAL_ERROR;
}
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- {
- UART_AdvFeatureConfig(huart);
- }
-
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
@@ -413,17 +418,19 @@
__HAL_UART_DISABLE(huart);
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
{
return HAL_ERROR;
}
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- {
- UART_AdvFeatureConfig(huart);
- }
-
/* In half-duplex mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN and IREN bits in the USART_CR3 register.*/
@@ -499,17 +506,19 @@
__HAL_UART_DISABLE(huart);
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
{
return HAL_ERROR;
}
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- {
- UART_AdvFeatureConfig(huart);
- }
-
/* In LIN mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN and IREN bits in the USART_CR3 register.*/
@@ -583,17 +592,19 @@
__HAL_UART_DISABLE(huart);
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
{
return HAL_ERROR;
}
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- {
- UART_AdvFeatureConfig(huart);
- }
-
/* In multiprocessor mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register. */
@@ -656,6 +667,7 @@
huart->gState = HAL_UART_STATE_RESET;
huart->RxState = HAL_UART_STATE_RESET;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
__HAL_UNLOCK(huart);
@@ -695,7 +707,10 @@
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User UART Callback
- * To be used instead of the weak predefined callback
+ * To be used to override the weak predefined callback
+ * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
+ * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register
+ * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
* @param huart uart handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -727,8 +742,6 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
if (huart->gState == HAL_UART_STATE_READY)
{
switch (CallbackID)
@@ -814,14 +827,15 @@
status = HAL_ERROR;
}
- __HAL_UNLOCK(huart);
-
return status;
}
/**
* @brief Unregister an UART Callback
* UART callaback is redirected to the weak predefined callback
+ * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
+ * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register
+ * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
* @param huart uart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -844,8 +858,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- __HAL_LOCK(huart);
-
if (HAL_UART_STATE_READY == huart->gState)
{
switch (CallbackID)
@@ -933,8 +945,6 @@
status = HAL_ERROR;
}
- __HAL_UNLOCK(huart);
-
return status;
}
@@ -1110,10 +1120,10 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint8_t *pdata8bits;
- uint16_t *pdata16bits;
+ const uint8_t *pdata8bits;
+ const uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
@@ -1124,8 +1134,14 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
+#if defined(USART_DMAREQUESTS_SW_WA)
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ }
+#endif /* USART_DMAREQUESTS_SW_WA */
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_BUSY_TX;
@@ -1139,7 +1155,7 @@
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
pdata8bits = NULL;
- pdata16bits = (uint16_t *) pData;
+ pdata16bits = (const uint16_t *) pData;
}
else
{
@@ -1147,12 +1163,13 @@
pdata16bits = NULL;
}
- __HAL_UNLOCK(huart);
-
while (huart->TxXferCount > 0U)
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
+
+ huart->gState = HAL_UART_STATE_READY;
+
return HAL_TIMEOUT;
}
if (pdata8bits == NULL)
@@ -1170,6 +1187,8 @@
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
+ huart->gState = HAL_UART_STATE_READY;
+
return HAL_TIMEOUT;
}
@@ -1214,8 +1233,14 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
+#if defined(USART_DMAREQUESTS_SW_WA)
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ }
+#endif /* USART_DMAREQUESTS_SW_WA */
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
@@ -1242,13 +1267,13 @@
pdata16bits = NULL;
}
- __HAL_UNLOCK(huart);
-
/* as long as data have to be received */
while (huart->RxXferCount > 0U)
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
+ huart->RxState = HAL_UART_STATE_READY;
+
return HAL_TIMEOUT;
}
if (pdata8bits == NULL)
@@ -1285,7 +1310,7 @@
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
@@ -1295,8 +1320,14 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
+#if defined(USART_DMAREQUESTS_SW_WA)
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ }
+#endif /* USART_DMAREQUESTS_SW_WA */
huart->pTxBuffPtr = pData;
huart->TxXferSize = Size;
huart->TxXferCount = Size;
@@ -1318,8 +1349,6 @@
huart->TxISR = UART_TxISR_8BIT_FIFOEN;
}
- __HAL_UNLOCK(huart);
-
/* Enable the TX FIFO threshold interrupt */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
}
@@ -1335,8 +1364,6 @@
huart->TxISR = UART_TxISR_8BIT;
}
- __HAL_UNLOCK(huart);
-
/* Enable the Transmit Data Register Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
}
@@ -1369,11 +1396,17 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+#if defined(USART_DMAREQUESTS_SW_WA)
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ }
+
+#endif /* USART_DMAREQUESTS_SW_WA */
if (!(IS_LPUART_INSTANCE(huart->Instance)))
{
/* Check that USART RTOEN bit is set */
@@ -1392,6 +1425,7 @@
}
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Send an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
@@ -1402,7 +1436,7 @@
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef status;
uint16_t nbByte = Size;
@@ -1415,8 +1449,6 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
huart->pTxBuffPtr = pData;
huart->TxXferSize = Size;
huart->TxXferCount = Size;
@@ -1480,8 +1512,6 @@
/* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA;
- __HAL_UNLOCK(huart);
-
/* Restore huart->gState to ready */
huart->gState = HAL_UART_STATE_READY;
@@ -1491,8 +1521,6 @@
/* Clear the TC flag in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
- __HAL_UNLOCK(huart);
-
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
@@ -1527,8 +1555,6 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
@@ -1560,27 +1586,55 @@
const HAL_UART_StateTypeDef gstate = huart->gState;
const HAL_UART_StateTypeDef rxstate = huart->RxState;
- __HAL_LOCK(huart);
-
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
(gstate == HAL_UART_STATE_BUSY_TX))
{
- /* Disable the UART DMA Tx request */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ /* Suspend the UART DMA Tx channel : use blocking DMA Suspend API (no callback) */
+ if (huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Suspend callback to Null.
+ No call back execution at end of DMA Suspend procedure */
+ huart->hdmatx->XferSuspendCallback = NULL;
+
+ if (HAL_DMAEx_Suspend(huart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
}
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
(rxstate == HAL_UART_STATE_BUSY_RX))
{
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ /* Suspend the UART DMA Rx channel : use blocking DMA Suspend API (no callback) */
+ if (huart->hdmarx != NULL)
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- /* Disable the UART DMA Rx request */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ /* Set the UART DMA Suspend callback to Null.
+ No call back execution at end of DMA Suspend procedure */
+ huart->hdmarx->XferSuspendCallback = NULL;
+
+ if (HAL_DMAEx_Suspend(huart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
}
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
@@ -1591,12 +1645,19 @@
*/
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
{
- __HAL_LOCK(huart);
-
if (huart->gState == HAL_UART_STATE_BUSY_TX)
{
- /* Enable the UART DMA Tx request */
- ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ /* Resume the UART DMA Tx channel */
+ if (huart->hdmatx != NULL)
+ {
+ if (HAL_DMAEx_Resume(huart->hdmatx) != HAL_OK)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_ERROR;
+ }
+ }
}
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
{
@@ -1604,14 +1665,24 @@
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ if (huart->Init.Parity != UART_PARITY_NONE)
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ }
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
- /* Enable the UART DMA Rx request */
- ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- }
+ /* Resume the UART DMA Rx channel */
+ if (huart->hdmarx != NULL)
+ {
+ if (HAL_DMAEx_Resume(huart->hdmarx) != HAL_OK)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
- __HAL_UNLOCK(huart);
+ return HAL_ERROR;
+ }
+ }
+ }
return HAL_OK;
}
@@ -1683,6 +1754,7 @@
return HAL_OK;
}
+#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @brief Abort ongoing transfers (blocking mode).
@@ -1709,11 +1781,15 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Tx request if enabled */
+#if defined(HAL_DMA_MODULE_ENABLED)
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
+#if !defined(USART_DMAREQUESTS_SW_WA)
+ /* Disable the UART DMA Tx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+#endif /* !USART_DMAREQUESTS_SW_WA */
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmatx != NULL)
{
@@ -1734,11 +1810,14 @@
}
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+#if !defined(USART_DMAREQUESTS_SW_WA)
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+#endif /* !USART_DMAREQUESTS_SW_WA */
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmarx != NULL)
{
@@ -1758,6 +1837,7 @@
}
}
}
+#endif /* HAL_DMA_MODULE_ENABLED */
/* Reset Tx and Rx transfer counters */
huart->TxXferCount = 0U;
@@ -1803,11 +1883,15 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
- /* Disable the UART DMA Tx request if enabled */
+#if defined(HAL_DMA_MODULE_ENABLED)
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
+#if !defined(USART_DMAREQUESTS_SW_WA)
+ /* Disable the UART DMA Tx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+#endif /* !USART_DMAREQUESTS_SW_WA */
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmatx != NULL)
{
@@ -1827,6 +1911,7 @@
}
}
}
+#endif /* HAL_DMA_MODULE_ENABLED */
/* Reset Tx transfer counter */
huart->TxXferCount = 0U;
@@ -1867,11 +1952,15 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Rx request if enabled */
+#if defined(HAL_DMA_MODULE_ENABLED)
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+#if !defined(USART_DMAREQUESTS_SW_WA)
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+#endif /* !USART_DMAREQUESTS_SW_WA */
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmarx != NULL)
{
@@ -1891,6 +1980,7 @@
}
}
}
+#endif /* HAL_DMA_MODULE_ENABLED */
/* Reset Rx transfer counter */
huart->RxXferCount = 0U;
@@ -1937,6 +2027,7 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
@@ -1968,12 +2059,14 @@
}
}
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
+#if !defined(USART_DMAREQUESTS_SW_WA)
/* Disable DMA Tx at UART level */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+#endif /* !USART_DMAREQUESTS_SW_WA */
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
if (huart->hdmatx != NULL)
{
@@ -1992,11 +2085,14 @@
}
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+#if !defined(USART_DMAREQUESTS_SW_WA)
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+#endif /* !USART_DMAREQUESTS_SW_WA */
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
if (huart->hdmarx != NULL)
{
@@ -2015,6 +2111,7 @@
}
}
}
+#endif /* HAL_DMA_MODULE_ENABLED */
/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
if (abortcplt == 1U)
@@ -2080,11 +2177,15 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
- /* Disable the UART DMA Tx request if enabled */
+#if defined(HAL_DMA_MODULE_ENABLED)
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
+#if !defined(USART_DMAREQUESTS_SW_WA)
+ /* Disable the UART DMA Tx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+#endif /* !USART_DMAREQUESTS_SW_WA */
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
if (huart->hdmatx != NULL)
{
@@ -2121,6 +2222,7 @@
}
}
else
+#endif /* HAL_DMA_MODULE_ENABLED */
{
/* Reset Tx transfer counter */
huart->TxXferCount = 0U;
@@ -2176,11 +2278,15 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Rx request if enabled */
+#if defined(HAL_DMA_MODULE_ENABLED)
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+#if !defined(USART_DMAREQUESTS_SW_WA)
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+#endif /* !USART_DMAREQUESTS_SW_WA */
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
if (huart->hdmarx != NULL)
{
@@ -2224,6 +2330,7 @@
}
}
else
+#endif /* HAL_DMA_MODULE_ENABLED */
{
/* Reset Rx transfer counter */
huart->RxXferCount = 0U;
@@ -2357,11 +2464,15 @@
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
- /* Disable the UART DMA Rx request if enabled */
+#if defined(HAL_DMA_MODULE_ENABLED)
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+#if !defined(USART_DMAREQUESTS_SW_WA)
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+#endif /* !USART_DMAREQUESTS_SW_WA */
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
{
@@ -2390,6 +2501,7 @@
}
}
else
+#endif /* HAL_DMA_MODULE_ENABLED */
{
/* Call user error callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -2427,6 +2539,7 @@
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Check if DMA mode is enabled in UART */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
@@ -2448,10 +2561,12 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+#if !defined(USART_DMAREQUESTS_SW_WA)
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+#endif /* !USART_DMAREQUESTS_SW_WA */
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
@@ -2461,6 +2576,11 @@
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
}
+
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Idle Event */
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
@@ -2473,6 +2593,7 @@
}
else
{
+#endif /* HAL_DMA_MODULE_ENABLED */
/* DMA mode not enabled */
/* Check received length : If all expected data are received, do nothing.
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
@@ -2494,6 +2615,11 @@
huart->RxISR = NULL;
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Idle Event */
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
@@ -2503,7 +2629,9 @@
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
return;
+#if defined(HAL_DMA_MODULE_ENABLED)
}
+#endif /* HAL_DMA_MODULE_ENABLED */
}
/* UART in mode Transmitter ------------------------------------------------*/
@@ -2960,7 +3088,7 @@
* the configuration information for the specified UART.
* @retval HAL state
*/
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart)
{
uint32_t temp1;
uint32_t temp2;
@@ -2976,7 +3104,7 @@
* the configuration information for the specified UART.
* @retval UART Error Code
*/
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart)
{
return huart->ErrorCode;
}
@@ -3130,7 +3258,7 @@
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
{
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
@@ -3150,10 +3278,10 @@
if (pclk != 0U)
{
/* USARTDIV must be greater than or equal to 0d16 */
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
{
- huart->Instance->BRR = usartdiv;
+ huart->Instance->BRR = (uint16_t)usartdiv;
}
else
{
@@ -3183,6 +3311,13 @@
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+ /* if required, configure RX/TX pins swap */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+ }
+
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
{
@@ -3204,13 +3339,6 @@
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
}
- /* if required, configure RX/TX pins swap */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
- }
-
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
{
@@ -3218,12 +3346,14 @@
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
}
+#endif /* HAL_DMA_MODULE_ENABLED */
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
@@ -3268,6 +3398,13 @@
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
{
+ /* Disable TXE interrupt for the interrupt process */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
/* Timeout occurred */
return HAL_TIMEOUT;
}
@@ -3279,6 +3416,15 @@
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ huart->RxState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
/* Timeout occurred */
return HAL_TIMEOUT;
}
@@ -3288,6 +3434,7 @@
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
__HAL_UNLOCK(huart);
@@ -3295,10 +3442,11 @@
}
/**
- * @brief Handle UART Communication Timeout.
+ * @brief This function handles UART Communication Timeout. It waits
+ * until a flag is no longer in the specified status.
* @param huart UART handle.
* @param Flag Specifies the UART flag to check
- * @param Status Flag status (SET or RESET)
+ * @param Status The actual Flag status (SET or RESET)
* @param Tickstart Tick start value
* @param Timeout Timeout duration
* @retval HAL status
@@ -3314,35 +3462,39 @@
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
- interrupts for the interrupt process */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
- USART_CR1_TXEIE_TXFNFIE));
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- __HAL_UNLOCK(huart);
return HAL_TIMEOUT;
}
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
{
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
+ {
+ /* Clear Overrun Error flag*/
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts if ongoing */
+ UART_EndRxTransfer(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_ORE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_ERROR;
+ }
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
- interrupts for the interrupt process */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
- USART_CR1_TXEIE_TXFNFIE));
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts if ongoing */
+ UART_EndRxTransfer(huart);
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
huart->ErrorCode = HAL_UART_ERROR_RTO;
/* Process Unlocked */
@@ -3396,10 +3548,11 @@
huart->RxISR = UART_RxISR_8BIT_FIFOEN;
}
- __HAL_UNLOCK(huart);
-
/* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ if (huart->Init.Parity != UART_PARITY_NONE)
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ }
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
}
else
@@ -3414,14 +3567,20 @@
huart->RxISR = UART_RxISR_8BIT;
}
- __HAL_UNLOCK(huart);
-
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ if (huart->Init.Parity != UART_PARITY_NONE)
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+ else
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
}
return HAL_OK;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Start Receive operation in DMA mode.
* @note This function could be called by all HAL UART API providing reception in DMA mode.
@@ -3500,18 +3659,18 @@
/* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA;
- __HAL_UNLOCK(huart);
-
/* Restore huart->RxState to ready */
huart->RxState = HAL_UART_STATE_READY;
return HAL_ERROR;
}
}
- __HAL_UNLOCK(huart);
/* Enable the UART Parity Error Interrupt */
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ if (huart->Init.Parity != UART_PARITY_NONE)
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ }
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
@@ -3538,6 +3697,7 @@
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
}
+#endif /* HAL_DMA_MODULE_ENABLED */
/**
@@ -3566,6 +3726,7 @@
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief DMA UART transmit process complete callback.
* @param hdma DMA handle.
@@ -3580,10 +3741,12 @@
{
huart->TxXferCount = 0U;
+#if !defined(USART_DMAREQUESTS_SW_WA)
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the UART CR3 register */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+#endif /* !USART_DMAREQUESTS_SW_WA */
/* Enable the UART Transmit Complete Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
}
@@ -3636,10 +3799,12 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+#if !defined(USART_DMAREQUESTS_SW_WA)
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+#endif /* !USART_DMAREQUESTS_SW_WA */
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
@@ -3650,6 +3815,10 @@
}
}
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : use Rx Event callback */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -3684,6 +3853,10 @@
{
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Half Transfer */
+ huart->RxEventType = HAL_UART_RXEVENT_HT;
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : use Rx Event callback */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -3942,6 +4115,7 @@
HAL_UART_AbortReceiveCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
+#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @brief TX interrupt handler for 7 or 8 bits data word length .
@@ -3981,7 +4155,7 @@
*/
static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
{
- uint16_t *tmp;
+ const uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
@@ -3996,7 +4170,7 @@
}
else
{
- tmp = (uint16_t *) huart->pTxBuffPtr;
+ tmp = (const uint16_t *) huart->pTxBuffPtr;
huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
huart->pTxBuffPtr += 2U;
huart->TxXferCount--;
@@ -4053,7 +4227,7 @@
*/
static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
{
- uint16_t *tmp;
+ const uint16_t *tmp;
uint16_t nb_tx_data;
/* Check that a Tx process is ongoing */
@@ -4073,7 +4247,7 @@
}
else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
{
- tmp = (uint16_t *) huart->pTxBuffPtr;
+ tmp = (const uint16_t *) huart->pTxBuffPtr;
huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
huart->pTxBuffPtr += 2U;
huart->TxXferCount--;
@@ -4144,6 +4318,19 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -4159,6 +4346,7 @@
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
}
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
@@ -4223,6 +4411,19 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -4238,6 +4439,7 @@
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
}
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
@@ -4353,6 +4555,19 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -4368,6 +4583,7 @@
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
}
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
@@ -4503,6 +4719,19 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -4518,6 +4747,7 @@
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
}
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
@@ -4576,3 +4806,4 @@
/**
* @}
*/
+
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart_ex.c
index 9ddf46c..a8395d4 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart_ex.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_uart_ex.c
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -38,6 +38,7 @@
configured prior starting RX/TX transfers.
@endverbatim
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -211,17 +212,19 @@
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
{
return HAL_ERROR;
}
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- {
- UART_AdvFeatureConfig(huart);
- }
-
/* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
@@ -703,11 +706,10 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
@@ -731,8 +733,6 @@
pdata16bits = NULL;
}
- __HAL_UNLOCK(huart);
-
/* Initialize output number of received elements */
*RxLen = 0U;
@@ -749,6 +749,7 @@
/* If Set, and data has already been received, this means Idle Event is valid : End reception */
if (*RxLen > 0U)
{
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
huart->RxState = HAL_UART_STATE_READY;
return HAL_OK;
@@ -814,7 +815,7 @@
*/
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef status;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
@@ -824,29 +825,24 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
/* Set Reception type to reception till IDLE Event*/
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
- status = UART_Start_Receive_IT(huart, pData, Size);
+ (void)UART_Start_Receive_IT(huart, pData, Size);
- /* Check Rx process has been successfully started */
- if (status == HAL_OK)
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
- }
- else
- {
- /* In case of errors already pending when reception is started,
- Interrupts may have already been raised and lead to reception abortion.
- (Overrun error for instance).
- In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
- status = HAL_ERROR;
- }
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ else
+ {
+ /* In case of errors already pending when reception is started,
+ Interrupts may have already been raised and lead to reception abortion.
+ (Overrun error for instance).
+ In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+ status = HAL_ERROR;
}
return status;
@@ -857,6 +853,7 @@
}
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Receive an amount of data in DMA mode till either the expected number
* of data is received or an IDLE event occurs.
@@ -886,10 +883,9 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
/* Set Reception type to reception till IDLE Event*/
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
status = UART_Start_Receive_DMA(huart, pData, Size);
@@ -918,6 +914,37 @@
return HAL_BUSY;
}
}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+ * @brief Provide Rx Event type that has lead to RxEvent callback execution.
+ * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress
+ * of reception process is provided to application through calls of Rx Event callback (either default one
+ * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event,
+ * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead
+ * to Rx Event callback execution.
+ * @note This function is expected to be called within the user implementation of Rx Event Callback,
+ * in order to provide the accurate value :
+ * In Interrupt Mode :
+ * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
+ * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
+ * received data is lower than expected one)
+ * In DMA Mode :
+ * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
+ * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received
+ * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
+ * received data is lower than expected one).
+ * In DMA mode, RxEvent callback could be called several times;
+ * When DMA is configured in Normal Mode, HT event does not stop Reception process;
+ * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process;
+ * @param huart UART handle.
+ * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
+ */
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart)
+{
+ /* Return Rx Event type value, as stored in UART handle */
+ return (huart->RxEventType);
+}
/**
* @brief Set autonomous mode Configuration.
@@ -925,7 +952,8 @@
* @param sConfig Autonomous mode structure parameters.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart, UART_AutonomousModeConfTypeDef *sConfig)
+HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart,
+ const UART_AutonomousModeConfTypeDef *sConfig)
{
uint32_t tmpreg;
@@ -987,7 +1015,8 @@
* @param sConfig Autonomous mode structure parameters.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(UART_HandleTypeDef *huart, UART_AutonomousModeConfTypeDef *sConfig)
+HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(const UART_HandleTypeDef *huart,
+ UART_AutonomousModeConfTypeDef *sConfig)
{
uint32_t tmpreg;
@@ -1114,3 +1143,4 @@
/**
* @}
*/
+
diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_ll_dlyb.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_ll_dlyb.c
index aa0bc97..ff5b4ea 100644
--- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_ll_dlyb.c
+++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_ll_dlyb.c
@@ -11,14 +11,15 @@
*
******************************************************************************
* @attention
- *
- * Copyright (c) 2021 STMicroelectronics.
+ *
+ * Copyright (c) 2021 - 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
+ *
******************************************************************************
@verbatim
==============================================================================
@@ -55,12 +56,12 @@
* @{
*/
-/** @defgroup DLYB DLYB
+/** @defgroup DLYB_LL DLYB
* @brief DLYB LL module driver.
* @{
*/
-#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_QSPI_MODULE_ENABLED)|| defined(HAL_OSPI_MODULE_ENABLED)
+#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_OSPI_MODULE_ENABLED) || defined(HAL_XSPI_MODULE_ENABLED)
/**
@cond 0
@@ -230,7 +231,7 @@
/**
* @}
*/
-#endif /* HAL_SD_MODULE_ENABLED || HAL_QSPI_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED */
+#endif /* HAL_SD_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED || HAL_XSPI_MODULE_ENABLED */
/**
* @}