RSE: FIH: Add option to use SW based delay
Currently FIH in RSE uses KMU to generate random delayes of
up to 32 cycles. Add an option RSE_ENABLE_SW_DELAY to always
use a SW based delay where waiting is performed actively by
the CPU instead of relying on KMU-based waiting.
Signed-off-by: Antonio de Angelis <antonio.deangelis@arm.com>
Change-Id: Id26973963414bb2205c7b65c351cc0ff846f1692
diff --git a/platform/ext/target/arm/rse/common/CMakeLists.txt b/platform/ext/target/arm/rse/common/CMakeLists.txt
index 0078844..1cfd7e4 100644
--- a/platform/ext/target/arm/rse/common/CMakeLists.txt
+++ b/platform/ext/target/arm/rse/common/CMakeLists.txt
@@ -498,6 +498,7 @@
target_compile_definitions(platform_bl1_1
PRIVATE
$<$<BOOL:${PLATFORM_PSA_ADAC_SECURE_DEBUG}>:PLATFORM_PSA_ADAC_SECURE_DEBUG>
+ $<$<BOOL:${RSE_ENABLE_FIH_SW_DELAY}>:RSE_ENABLE_FIH_SW_DELAY>
)
target_include_directories(platform_bl1_1_interface
diff --git a/platform/ext/target/arm/rse/common/bl1/rse_fih.c b/platform/ext/target/arm/rse/common/bl1/rse_fih.c
index 3536c0d..d8c8b2c 100644
--- a/platform/ext/target/arm/rse/common/bl1/rse_fih.c
+++ b/platform/ext/target/arm/rse/common/bl1/rse_fih.c
@@ -8,8 +8,12 @@
#include "fih.h"
#ifdef FIH_ENABLE_DELAY
+#ifndef RSE_ENABLE_FIH_SW_DELAY
#include "kmu_drv.h"
#include "device_definition.h"
+#else
+#include "bl1_random.h"
+#endif
#endif /* FIH_ENABLE_DELAY */
#ifdef TFM_FIH_PROFILE_ON
@@ -82,22 +86,36 @@
/* An infinite loop to suppress compiler warnings
* about the return of a noreturn function
*/
- while(1) {
- };
+ while(1) {}
}
#endif /* FIH_ENABLE_GLOBAL_FAIL */
#if defined(FIH_ENABLE_DELAY) && defined(FIH_ENABLE_DELAY_PLATFORM)
void fih_delay_init(void)
{
- /* Nothing to init, random delays through HW KMU */
+ /* Nothing to init */
return;
}
int fih_delay_platform(void)
{
+#ifndef RSE_ENABLE_FIH_SW_DELAY
kmu_random_delay(&KMU_DEV_S, KMU_DELAY_LIMIT_32_CYCLES);
- /* No SW based delay */
+#else
+ uint64_t random;
+ volatile uint32_t counter = 0;
+
+ if (bl1_random_generate_fast((uint8_t *)&random, sizeof(random))) {
+ FIH_PANIC;
+ }
+
+ /* Delays between 0 and 31 cycles to mimic the
+ * same delays allowed by the KMU configured above
+ */
+ while (counter < ((uint32_t)random) & 0x1F) {
+ counter++;
+ }
+#endif /* RSE_ENABLE_FIH_SW_DELAY */
return 1;
}
#endif /* FIH_ENABLE_DELAY && FIH_ENABLE_DELAY_PLATFORM */