diff --git a/config/check_config.cmake b/config/check_config.cmake
index 7fefce3..af0fae7 100644
--- a/config/check_config.cmake
+++ b/config/check_config.cmake
@@ -53,11 +53,11 @@
 
 ########################## FPU ################################################
 
-tfm_invalid_config(CONFIG_TFM_SPE_FP LESS 0 OR CONFIG_TFM_SPE_FP GREATER 2)
-tfm_invalid_config(NOT CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CONFIG_TFM_SPE_FP GREATER 0)
-tfm_invalid_config((NOT CONFIG_TFM_FP_ARCH) AND (CONFIG_TFM_SPE_FP GREATER 0))
-tfm_invalid_config((NOT TFM_PSA_API) AND (CONFIG_TFM_SPE_FP GREATER 0))
-tfm_invalid_config(CONFIG_TFM_SPE_FP STREQUAL "0" AND CONFIG_TFM_LAZY_STACKING_SPE)
+tfm_invalid_config(NOT (CONFIG_TFM_FP STREQUAL "soft" OR CONFIG_TFM_FP STREQUAL "hard"))
+tfm_invalid_config(NOT CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CONFIG_TFM_FP STREQUAL "hard")
+tfm_invalid_config((NOT CONFIG_TFM_FP_ARCH) AND CONFIG_TFM_FP STREQUAL "hard")
+tfm_invalid_config((NOT TFM_PSA_API) AND CONFIG_TFM_FP STREQUAL "hard")
+tfm_invalid_config(CONFIG_TFM_FP STREQUAL "soft" AND CONFIG_TFM_LAZY_STACKING)
 
 ########################## BL2 #################################################
 
@@ -108,3 +108,7 @@
 if(TFM_S_REG_TEST OR TFM_NS_REG_TEST)
     include(${TFM_TEST_PATH}/config/check_config.cmake)
 endif()
+
+###################### Compiler check for FP support ###########################
+
+include(config/cp_check.cmake)
diff --git a/config/config_default.cmake b/config/config_default.cmake
index a8a710f..d233475 100755
--- a/config/config_default.cmake
+++ b/config/config_default.cmake
@@ -52,8 +52,8 @@
 
 set(TFM_EXCEPTION_INFO_DUMP             OFF         CACHE BOOL      "On fatal errors in the secure firmware, capture info about the exception. Print the info if the SPM log level is sufficient.")
 
-set(CONFIG_TFM_SPE_FP                   0           CACHE STRING    "FP ABI type in SPE: 0-software, 1-hybird, 2-hardware")
-set(CONFIG_TFM_LAZY_STACKING_SPE        OFF         CACHE BOOL      "Disable lazy stacking from SPE")
+set(CONFIG_TFM_FP                       "soft"      CACHE STRING    "FP ABI type in SPE and NSPE: soft-Software ABI, hard-Hardware ABI")
+set(CONFIG_TFM_LAZY_STACKING            OFF         CACHE BOOL      "Enable/disable lazy stacking")
 
 ############################ Platform ##########################################
 
@@ -173,4 +173,4 @@
 
 ########################## FP #################################################
 
-set_property(CACHE CONFIG_TFM_SPE_FP PROPERTY STRINGS "0;1;2")
+set_property(CACHE CONFIG_TFM_FP PROPERTY STRINGS "soft;hard")
diff --git a/config/cp_check.cmake b/config/cp_check.cmake
new file mode 100644
index 0000000..8e4989a
--- /dev/null
+++ b/config/cp_check.cmake
@@ -0,0 +1,28 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2022, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+###################### Check compiler for FP vulnerability #####################
+
+# Check compiler with mitigation for the VLLDM instruction security vulnerability or not.
+# For more information, please check https://developer.arm.com/support/arm-security-updates/vlldm-instruction-security-vulnerability.
+if (CONFIG_TFM_FP STREQUAL "hard")
+    # Create test C file.
+    file(WRITE ${CMAKE_CURRENT_BINARY_DIR}/cvetest.c "int x;")
+    # Compile with mitigation -mfix-cmse-cve-2021-35465.
+    execute_process (
+        COMMAND ${CMAKE_C_COMPILER} -mfix-cmse-cve-2021-35465 -S ${CMAKE_CURRENT_BINARY_DIR}/cvetest.c -o ${CMAKE_CURRENT_BINARY_DIR}/cvetest.s
+        RESULT_VARIABLE ret
+        ERROR_VARIABLE err
+    )
+    file(REMOVE ${CMAKE_CURRENT_BINARY_DIR}/cvetest.c)
+    # Check result
+    if(NOT ret EQUAL 0)
+        message(FATAL_ERROR "To enable FPU usage in SPE and NSPE both, please use the compiler with '-mfix-cmse-cve-2021-35465' support")
+    else()
+        file(REMOVE ${CMAKE_CURRENT_BINARY_DIR}/cvetest.s)
+    endif()
+endif()
diff --git a/config/cp_config_default.cmake b/config/cp_config_default.cmake
index 842bc83..45e119e 100644
--- a/config/cp_config_default.cmake
+++ b/config/cp_config_default.cmake
@@ -1,5 +1,5 @@
 #-------------------------------------------------------------------------------
-# Copyright (c) 2021, Arm Limited. All rights reserved.
+# Copyright (c) 2022, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -12,6 +12,6 @@
     return()
 endif()
 
-if (CONFIG_TFM_SPE_FP STREQUAL "1" OR CONFIG_TFM_SPE_FP STREQUAL "2")
-    set(CONFIG_TFM_LAZY_STACKING_SPE     ON          CACHE BOOL      "Enable lazy stacking from SPE")
+if (CONFIG_TFM_FP STREQUAL "hard")
+    set(CONFIG_TFM_LAZY_STACKING         ON          CACHE BOOL      "Enable lazy stacking")
 endif()
diff --git a/interface/include/config_impl.h.template b/interface/include/config_impl.h.template
index bc29ac0..2a220ab 100644
--- a/interface/include/config_impl.h.template
+++ b/interface/include/config_impl.h.template
@@ -55,4 +55,8 @@
 #error "Invalid partition number input, check configurations."
 {% endif %}
 
+#if (CONFIG_TFM_FP > 0) && (CONFIG_TFM_SPM_BACKEND_SFN == 1)
+#error "FP is not supported for SFN model."
+#endif
+
 #endif /* __CONFIG_IMPL_H__ */
diff --git a/lib/ext/CMSIS_5/CMakeLists.txt b/lib/ext/CMSIS_5/CMakeLists.txt
index b25811a..2cde6c8 100644
--- a/lib/ext/CMSIS_5/CMakeLists.txt
+++ b/lib/ext/CMSIS_5/CMakeLists.txt
@@ -1,26 +1,30 @@
 #-------------------------------------------------------------------------------
-# Copyright (c) 2020, Arm Limited. All rights reserved.
+# Copyright (c) 2020-2022, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 #-------------------------------------------------------------------------------
 
 add_library(CMSIS_5_RTX_V8MMN STATIC IMPORTED GLOBAL)
+add_library(CMSIS_5_RTX_V8MMFN STATIC IMPORTED GLOBAL)
 add_library(CMSIS_5_RTX_V8MBN STATIC IMPORTED GLOBAL)
 add_library(CMSIS_5_RTX_CM3 STATIC IMPORTED GLOBAL)
 
 if ("${CMAKE_C_COMPILER_ID}" STREQUAL GNU)
     set_target_properties(CMSIS_5_RTX_V8MMN PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a)
+    set_target_properties(CMSIS_5_RTX_V8MMFN PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a)
     set_target_properties(CMSIS_5_RTX_V8MBN PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a)
     set_target_properties(CMSIS_5_RTX_CM3   PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/GCC/libRTX_CM3.a)
 elseif("${CMAKE_C_COMPILER_ID}" STREQUAL ARMClang)
     set_target_properties(CMSIS_5_RTX_V8MMN PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib)
+    set_target_properties(CMSIS_5_RTX_V8MMFN PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib)
     set_target_properties(CMSIS_5_RTX_V8MBN PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib)
     set_target_properties(CMSIS_5_RTX_CM3   PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/ARM/RTX_CM3.lib)
 elseif("${CMAKE_C_COMPILER_ID}" STREQUAL IAR)
     add_library(CMSIS_5_RTX_V81MMN STATIC IMPORTED GLOBAL)
     set_target_properties(CMSIS_5_RTX_V8MMN PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/IAR/RTX_V8MMN.a)
     set_target_properties(CMSIS_5_RTX_V81MMN PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/IAR/RTX_V81MMN.a)
+    set_target_properties(CMSIS_5_RTX_V8MMFN PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a)
     set_target_properties(CMSIS_5_RTX_V8MBN PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/IAR/RTX_V8MBN.a)
     set_target_properties(CMSIS_5_RTX_CM3   PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/IAR/RTX_CM3.a)
     target_link_libraries(CMSIS_5_RTX_V81MMN
@@ -36,6 +40,11 @@
         tfm_s_veneers
 )
 
+target_link_libraries(CMSIS_5_RTX_V8MMFN
+    INTERFACE
+        tfm_s_veneers
+)
+
 target_link_libraries(CMSIS_5_RTX_V8MBN
     INTERFACE
         tfm_s_veneers
diff --git a/platform/CMakeLists.txt b/platform/CMakeLists.txt
index 126e69d..c39585e 100755
--- a/platform/CMakeLists.txt
+++ b/platform/CMakeLists.txt
@@ -83,8 +83,10 @@
         TFM_SPM_LOG_LEVEL=${TFM_SPM_LOG_LEVEL}
         $<$<BOOL:${TFM_SPM_LOG_RAW_ENABLED}>:TFM_SPM_LOG_RAW_ENABLED>
         $<$<BOOL:${OTP_NV_COUNTERS_RAM_EMULATION}>:OTP_NV_COUNTERS_RAM_EMULATION>
-        CONFIG_TFM_SPE_FP=${CONFIG_TFM_SPE_FP}
-        $<$<BOOL:${CONFIG_TFM_LAZY_STACKING_SPE}>:CONFIG_TFM_LAZY_STACKING_SPE>
+        # CONFIG_TFM_FP
+        $<$<STREQUAL:${CONFIG_TFM_FP},hard>:CONFIG_TFM_FP=2>
+        $<$<STREQUAL:${CONFIG_TFM_FP},soft>:CONFIG_TFM_FP=0>
+        $<$<BOOL:${CONFIG_TFM_LAZY_STACKING}>:CONFIG_TFM_LAZY_STACKING>
     PRIVATE
         $<$<BOOL:${SYMMETRIC_INITIAL_ATTESTATION}>:SYMMETRIC_INITIAL_ATTESTATION>
         $<$<OR:$<VERSION_GREATER:${TFM_ISOLATION_LEVEL},1>,$<STREQUAL:"${TEST_PSA_API}","IPC">>:CONFIG_TFM_ENABLE_MEMORY_PROTECT>
@@ -118,10 +120,19 @@
 )
 
 target_compile_definitions(platform_ns
+    PUBLIC
+        # CONFIG_TFM_FP
+        $<$<STREQUAL:${CONFIG_TFM_FP},hard>:CONFIG_TFM_FP=2>
+        $<$<STREQUAL:${CONFIG_TFM_FP},soft>:CONFIG_TFM_FP=0>
     PRIVATE
         $<$<BOOL:${TEST_NS_SLIH_IRQ}>:TEST_NS_SLIH_IRQ>
 )
 
+target_compile_options(platform_ns
+    PUBLIC
+        ${COMPILER_CP_FLAG}
+)
+
 #========================= Platform BL2 =======================================#
 if(BL2)
     #TODO import policy
diff --git a/platform/ext/target/arm/musca_s1/CMakeLists.txt b/platform/ext/target/arm/musca_s1/CMakeLists.txt
index dde378e..4602e9e 100644
--- a/platform/ext/target/arm/musca_s1/CMakeLists.txt
+++ b/platform/ext/target/arm/musca_s1/CMakeLists.txt
@@ -1,5 +1,5 @@
 #-------------------------------------------------------------------------------
-# Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+# Copyright (c) 2020-2022, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -44,7 +44,16 @@
     )
     target_link_libraries(CMSIS_5_tfm_ns
         INTERFACE
-            CMSIS_5_RTX_V8MMN
+            $<$<STREQUAL:${CONFIG_TFM_FP},hard>:CMSIS_5_RTX_V8MMFN>
+            $<$<STREQUAL:${CONFIG_TFM_FP},soft>:CMSIS_5_RTX_V8MMN>
+    )
+    target_compile_options(tfm_ns
+        PUBLIC
+            ${COMPILER_CP_FLAG}
+    )
+    target_link_options(tfm_ns
+        PUBLIC
+            ${LINKER_CP_OPTION}
     )
 endif()
 
diff --git a/platform/include/tfm_plat_ns.h b/platform/include/tfm_plat_ns.h
index 3b689b4..1e35894 100644
--- a/platform/include/tfm_plat_ns.h
+++ b/platform/include/tfm_plat_ns.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -16,4 +16,11 @@
 
 int32_t tfm_ns_platform_init(void);
 
+/**
+ * \brief Coprocessor initialization.
+ *
+ * \return  ARM_DRIVER_OK if the initialization succeeds
+*/
+int32_t tfm_ns_cp_init(void);
+
 #endif /* __TFM_PLAT_NS_H__ */
diff --git a/secure_fw/spm/CMakeLists.txt b/secure_fw/spm/CMakeLists.txt
index cc5ddd6..4c67688 100755
--- a/secure_fw/spm/CMakeLists.txt
+++ b/secure_fw/spm/CMakeLists.txt
@@ -119,9 +119,11 @@
         $<$<AND:$<BOOL:${BL2}>,$<BOOL:${MCUBOOT_MEASURED_BOOT}>>:BOOT_DATA_AVAILABLE>
         $<$<BOOL:${TFM_EXCEPTION_INFO_DUMP}>:TFM_EXCEPTION_INFO_DUMP>
         $<$<BOOL:${TFM_NS_MANAGE_NSID}>:TFM_NS_MANAGE_NSID>
-        CONFIG_TFM_SPE_FP=${CONFIG_TFM_SPE_FP}
         $<$<BOOL:${CONFIG_TFM_SPM_BACKEND_IPC}>:CONFIG_TFM_SPM_BACKEND_IPC>
         $<$<BOOL:${CONFIG_TFM_SPM_BACKEND_SFN}>:CONFIG_TFM_SPM_BACKEND_SFN>
+        # CONFIG_TFM_FP
+        $<$<STREQUAL:${CONFIG_TFM_FP},hard>:CONFIG_TFM_FP=2>
+        $<$<STREQUAL:${CONFIG_TFM_FP},soft>:CONFIG_TFM_FP=0>
 )
 
 target_compile_options(tfm_spm
diff --git a/secure_fw/spm/cmsis_psa/arch/tfm_arch_v8m_main.c b/secure_fw/spm/cmsis_psa/arch/tfm_arch_v8m_main.c
index ab45cf4..cfc4e7e 100644
--- a/secure_fw/spm/cmsis_psa/arch/tfm_arch_v8m_main.c
+++ b/secure_fw/spm/cmsis_psa/arch/tfm_arch_v8m_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -18,7 +18,7 @@
 #include "tfm_secure_api.h"
 #include "tfm_svcalls.h"
 #include "utilities.h"
-#if defined(__FPU_USED) && (__FPU_USED == 1U) && (CONFIG_TFM_SPE_FP >= 1)
+#if defined(__FPU_USED) && (__FPU_USED == 1U) && (CONFIG_TFM_FP >= 1)
 #include "core_ext.h"
 #endif
 
@@ -264,47 +264,42 @@
 
 void tfm_arch_config_extensions(void)
 {
-#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-    /* Configure Secure access to the FPU only if the secure image is being
-     * built with the FPU in use. This avoids introducing extra interrupt
-     * latency when the FPU is not used by the SPE.
-     */
-#if defined(__FPU_USED) && (__FPU_USED == 1U)
-/* For secure uses FPU only */
-#if (CONFIG_TFM_SPE_FP >= 1)
+#if (CONFIG_TFM_FP >= 1)
 #ifdef __GNUC__
-    /* Enable Secure privileged and unprivilged access to the FP Extension */
+    /* Enable SPE privileged and unprivileged access to the FP Extension */
     SCB->CPACR |= (3U << 10U*2U)     /* enable CP10 full access */
                   | (3U << 11U*2U);  /* enable CP11 full access */
 #endif
 
-#ifdef CONFIG_TFM_LAZY_STACKING_SPE
-    /* Enable lazy stacking */
+#ifdef CONFIG_TFM_LAZY_STACKING
+    /* Enable lazy stacking. */
     FPU->FPCCR |= FPU_FPCCR_LSPEN_Msk;
 #else
-    /* Disable lazy stacking */
+    /* Disable lazy stacking. */
     FPU->FPCCR &= ~FPU_FPCCR_LSPEN_Msk;
 #endif
+
     /* If the SPE will ever use the floating-point registers for sensitive
      * data, then FPCCR.ASPEN, FPCCR.TS, FPCCR.CLRONRET and FPCCR.CLRONRETS
      * must be set at initialisation and not changed again afterwards.
+     * Let SPE decide the S/NS shared setting (LSPEN and CLRONRET) to avoid the
+     * possible side-path brought by flexibility.
      */
     FPU->FPCCR |= FPU_FPCCR_ASPEN_Msk
                   | FPU_FPCCR_TS_Msk
                   | FPU_FPCCR_CLRONRET_Msk
-                  | FPU_FPCCR_CLRONRETS_Msk;
+                  | FPU_FPCCR_CLRONRETS_Msk
+                  | FPU_FPCCR_LSPENS_Msk;
 
-    /* If FPU is used by secure only, prevent non-secure from modifying FPU’s
-     * power setting.
+    /* Permit Non-secure access to the Floating-point Extension.
+     * Note: It is still necessary to set CPACR_NS to enable the FP Extension
+     * in the NSPE. This configuration is left to NS privileged software.
      */
+    SCB->NSACR |= SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk;
+
+    /* Prevent non-secure from modifying FPU’s power setting. */
     SCnSCB->CPPWR |= SCnSCB_CPPWR_SUS11_Msk | SCnSCB_CPPWR_SUS10_Msk;
-
-    /* Disable Non-secure access to the Floating-point Extension.
-     */
-    SCB->NSACR &= ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk);
-#endif /* CONFIG_TFM_SPE_FP >= 1 */
-#endif /* __FPU_USED */
-#endif /* __FPU_PRESENT */
+#endif /* CONFIG_TFM_FP >= 1 */
 
 #if defined(__ARM_ARCH_8_1M_MAIN__)
     SCB->CCR |= SCB_CCR_TRD_Msk;
@@ -322,7 +317,7 @@
                   );
 }
 
-#if (CONFIG_TFM_SPE_FP >= 1)
+#if (CONFIG_TFM_FP >= 1)
 __attribute__((naked, noinline)) void tfm_arch_clear_fp_data(void)
 {
     __ASM volatile(
diff --git a/secure_fw/spm/cmsis_psa/main.c b/secure_fw/spm/cmsis_psa/main.c
index f707673..c0ed946 100644
--- a/secure_fw/spm/cmsis_psa/main.c
+++ b/secure_fw/spm/cmsis_psa/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2017-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -101,16 +101,9 @@
 
     SPMLOG_DBGMSGVAL("TF-M isolation level is: ", TFM_LVL);
 
-#if (CONFIG_TFM_SPE_FP == 0)
-    SPMLOG_INFMSG("TF-M FP mode: Software\r\n");
-#elif (CONFIG_TFM_SPE_FP == 1)
-    SPMLOG_INFMSG("TF-M FP mode: Hybird\r\n");
-#elif (CONFIG_TFM_SPE_FP == 2)
+#if (CONFIG_TFM_FP == 2)
     SPMLOG_INFMSG("TF-M FP mode: Hardware\r\n");
-#endif
-
-#if (CONFIG_TFM_SPE_FP >= 1)
-#ifdef CONFIG_TFM_LAZY_STACKING_SPE
+#ifdef CONFIG_TFM_LAZY_STACKING
     SPMLOG_INFMSG("Lazy stacking enabled\r\n");
 #else
     SPMLOG_INFMSG("Lazy stacking disabled\r\n");
@@ -151,7 +144,7 @@
      */
     tfm_arch_set_secure_exception_priorities();
 
-#if (CONFIG_TFM_SPE_FP >= 1)
+#if (CONFIG_TFM_FP >= 1)
     tfm_arch_clear_fp_data();
 #endif
 
diff --git a/secure_fw/spm/include/tfm_arch.h b/secure_fw/spm/include/tfm_arch.h
index c0b5276..dd28ea2 100644
--- a/secure_fw/spm/include/tfm_arch.h
+++ b/secure_fw/spm/include/tfm_arch.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -121,7 +121,7 @@
     __ISB();
 }
 
-#if (CONFIG_TFM_SPE_FP >= 1) && CONFIG_TFM_LAZY_STACKING_SPE
+#if (CONFIG_TFM_FP >= 1) && CONFIG_TFM_LAZY_STACKING
 #define ARCH_FLUSH_FP_CONTEXT()  __asm volatile("vmov  s0, s0 \n":::"memory")
 #else
 #define ARCH_FLUSH_FP_CONTEXT()
@@ -136,7 +136,7 @@
 /* Clear float point status. */
 void tfm_arch_clear_fp_status(void);
 
-#if (CONFIG_TFM_SPE_FP >= 1)
+#if (CONFIG_TFM_FP >= 1)
 /*
  * Clear float point data.
  */
diff --git a/toolchain_GNUARM.cmake b/toolchain_GNUARM.cmake
index 4a1e1b2..7645f58 100644
--- a/toolchain_GNUARM.cmake
+++ b/toolchain_GNUARM.cmake
@@ -104,8 +104,8 @@
     endif()
 
     if(GCC_VERSION VERSION_GREATER_EQUAL "8.0.0")
-        if (DEFINED CONFIG_TFM_SPE_FP)
-            if(CONFIG_TFM_SPE_FP STRGREATER 0)
+        if (DEFINED CONFIG_TFM_FP)
+            if(CONFIG_TFM_FP STREQUAL "hard")
                 string(APPEND CMAKE_SYSTEM_ARCH "+fp")
             endif()
         endif()
@@ -150,12 +150,9 @@
 
     set(BL2_COMPILER_CP_FLAG -mfloat-abi=soft)
 
-    if (CONFIG_TFM_SPE_FP STREQUAL "2")
+    if (CONFIG_TFM_FP STREQUAL "hard")
         set(COMPILER_CP_FLAG -mfloat-abi=hard -mfpu=${CONFIG_TFM_FP_ARCH})
         set(LINKER_CP_OPTION -mfloat-abi=hard -mfpu=${CONFIG_TFM_FP_ARCH})
-    elseif (CONFIG_TFM_SPE_FP STREQUAL "1")
-        set(COMPILER_CP_FLAG -mfloat-abi=softfp -mfpu=${CONFIG_TFM_FP_ARCH})
-        set(LINKER_CP_OPTION -mfloat-abi=softfp -mfpu=${CONFIG_TFM_FP_ARCH})
     else()
         set(COMPILER_CP_FLAG -mfloat-abi=soft)
         set(LINKER_CP_OPTION -mfloat-abi=soft)