Platform: Fix the Veneer SAU region for Arm platforms

Because the bits [4:0] of the SAU.LADDR are defined as 0x1F, the limit
address of SAU regions can not be written to the registers directly.
Otherwise, the region might include more than expected.

This patch fixes the veneer region limit addresses for Arm platforms.

Change-Id: I2692f3188a7bf982cc49b94329b2cb3f2c0f7618
Signed-off-by: Kevin Peng <kevin.peng@arm.com>
9 files changed