CC3XX: Update rom driver to CMSIS style
Change-Id: Ic73574cff7387041b540117f5df81bcf6e451532
Signed-off-by: Raef Coles <raef.coles@arm.com>
diff --git a/platform/ext/accelerator/cc312/bl1/cc312_rom_crypto.c b/platform/ext/accelerator/cc312/bl1/cc312_rom_crypto.c
index 935d87e..75b0d0e 100644
--- a/platform/ext/accelerator/cc312/bl1/cc312_rom_crypto.c
+++ b/platform/ext/accelerator/cc312/bl1/cc312_rom_crypto.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -11,12 +11,10 @@
#include <string.h>
#include "region_defs.h"
-#include "dx_reg_base_host.h"
+#include "device_definition.h"
#include "otp.h"
#include "fih.h"
-#include "cc3xx_aes.h"
-#include "cc3xx_hash.h"
-#include "cmsis_compiler.h"
+#include "cc3xx_drv.h"
#define KEY_DERIVATION_MAX_BUF_SIZE 128
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_aes.c b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_aes.c
index f55f115..667f10d 100644
--- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_aes.c
+++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_aes.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -7,19 +7,21 @@
#include "cc3xx_aes.h"
-#include "cc3xx_reg_defs.h"
+#include "cc3xx_dev.h"
#include "cc3xx_dma.h"
#include "cc3xx_lcs.h"
#include "cc3xx_engine_state.h"
#include "device_definition.h"
-static cc3xx_err_t cc3xx_aes_dumpiv(cc3xx_aes_mode_t mode, uint8_t *iv) {
+static cc3xx_err_t cc3xx_aes_dumpiv(cc3xx_aes_mode_t mode, uint8_t *iv)
+{
+ int32_t idx;
+
switch (mode) {
case CC3XX_AES_MODE_CTR:
- ((uint32_t*)iv)[3] = *CC3XX_REG_AES_AES_CTR_0_3;
- ((uint32_t*)iv)[2] = *CC3XX_REG_AES_AES_CTR_0_2;
- ((uint32_t*)iv)[1] = *CC3XX_REG_AES_AES_CTR_0_1;
- ((uint32_t*)iv)[0] = *CC3XX_REG_AES_AES_CTR_0_0;
+ for (idx = 3; idx >= 0; idx--) {
+ ((uint32_t*)iv)[idx] = P_CC3XX->aes.aes_ctr_0[idx];
+ }
break;
case CC3XX_AES_MODE_ECB:
return CC3XX_ERR_SUCCESS;
@@ -30,13 +32,15 @@
return CC3XX_ERR_SUCCESS;
}
-static cc3xx_err_t cc3xx_aes_loadiv(cc3xx_aes_mode_t mode, const uint8_t *iv) {
+static cc3xx_err_t cc3xx_aes_loadiv(cc3xx_aes_mode_t mode, const uint8_t *iv)
+{
+ int32_t idx;
+
switch (mode) {
case CC3XX_AES_MODE_CTR:
- *CC3XX_REG_AES_AES_CTR_0_3 = ((uint32_t*)iv)[3];
- *CC3XX_REG_AES_AES_CTR_0_2 = ((uint32_t*)iv)[2];
- *CC3XX_REG_AES_AES_CTR_0_1 = ((uint32_t*)iv)[1];
- *CC3XX_REG_AES_AES_CTR_0_0 = ((uint32_t*)iv)[0];
+ for (idx = 3; idx >= 0; idx--) {
+ P_CC3XX->aes.aes_ctr_0[idx] = ((uint32_t*)iv)[idx];
+ }
break;
case CC3XX_AES_MODE_ECB:
return CC3XX_ERR_SUCCESS;
@@ -53,8 +57,9 @@
cc3xx_aes_keysize_t key_size)
{
enum kmu_error_t kmu_err;
+ int32_t idx;
- if (*CC3XX_REG_AO_HOST_AO_LOCK_BITS & 0x1U) {
+ if (P_CC3XX->ao.host_ao_lock_bits & 0x1U) {
return CC3XX_ERR_INVALID_STATE;
}
@@ -90,16 +95,17 @@
} else {
switch (key_size) {
case CC3XX_AES_KEYSIZE_256:
- *CC3XX_REG_AES_AES_KEY_0_7 = ((uint32_t*)key)[7];
- *CC3XX_REG_AES_AES_KEY_0_6 = ((uint32_t*)key)[6];
+ for (idx = 7; idx >= 6; idx--) {
+ P_CC3XX->aes.aes_key_0[idx] = ((uint32_t*)key)[idx];
+ }
case CC3XX_AES_KEYSIZE_192:
- *CC3XX_REG_AES_AES_KEY_0_5 = ((uint32_t*)key)[5];
- *CC3XX_REG_AES_AES_KEY_0_4 = ((uint32_t*)key)[4];
+ for (idx = 5; idx >= 4; idx--) {
+ P_CC3XX->aes.aes_key_0[idx] = ((uint32_t*)key)[idx];
+ }
case CC3XX_AES_KEYSIZE_128:
- *CC3XX_REG_AES_AES_KEY_0_3 = ((uint32_t*)key)[3];
- *CC3XX_REG_AES_AES_KEY_0_2 = ((uint32_t*)key)[2];
- *CC3XX_REG_AES_AES_KEY_0_1 = ((uint32_t*)key)[1];
- *CC3XX_REG_AES_AES_KEY_0_0 = ((uint32_t*)key)[0];
+ for (idx = 3; idx >= 0; idx--) {
+ P_CC3XX->aes.aes_key_0[idx] = ((uint32_t*)key)[idx];
+ }
break;
default:
return CC3XX_ERR_NOT_IMPLEMENTED;
@@ -107,8 +113,8 @@
}
/* Set key size */
- *CC3XX_REG_AES_AES_CONTROL &= ~(0b11U << 12);
- *CC3XX_REG_AES_AES_CONTROL |= (key_size & 0b11U) << 12;
+ P_CC3XX->aes.aes_control &= ~(0b11U << 12);
+ P_CC3XX->aes.aes_control |= (key_size & 0b11U) << 12;
return CC3XX_ERR_SUCCESS;
}
@@ -132,22 +138,22 @@
}
break;
case CC3XX_AES_KEY_ID_KCP:
- if (*CC3XX_REG_AO_HOST_AO_LOCK_BITS & (0x1U << 3)) {
+ if (P_CC3XX->ao.host_ao_lock_bits & (0x1U << 3)) {
return CC3XX_ERR_INVALID_STATE;
}
break;
case CC3XX_AES_KEY_ID_KCE:
- if (*CC3XX_REG_AO_HOST_AO_LOCK_BITS & (0x1U << 4)) {
+ if (P_CC3XX->ao.host_ao_lock_bits & (0x1U << 4)) {
return CC3XX_ERR_INVALID_STATE;
}
break;
case CC3XX_AES_KEY_ID_KPICV:
- if (*CC3XX_REG_AO_HOST_AO_LOCK_BITS & (0x1U << 1)) {
+ if (P_CC3XX->ao.host_ao_lock_bits & (0x1U << 1)) {
return CC3XX_ERR_INVALID_STATE;
}
break;
case CC3XX_AES_KEY_ID_KCEICV:
- if (*CC3XX_REG_AO_HOST_AO_LOCK_BITS & (0x1U << 2)) {
+ if (P_CC3XX->ao.host_ao_lock_bits & (0x1U << 2)) {
return CC3XX_ERR_INVALID_STATE;
}
break;
@@ -165,10 +171,11 @@
cc3xx_aes_keysize_t key_size)
{
cc3xx_err_t err = CC3XX_ERR_SUCCESS;
+ int32_t idx;
if (key_id != CC3XX_AES_KEY_ID_USER_KEY) {
/* Check if the HOST_FATAL_ERROR mode is enabled */
- if (*CC3XX_REG_AO_HOST_AO_LOCK_BITS & 0x1U) {
+ if (P_CC3XX->ao.host_ao_lock_bits & 0x1U) {
return CC3XX_ERR_INVALID_STATE;
}
@@ -184,23 +191,24 @@
}
/* Select the required key */
- *CC3XX_REG_HOST_RGF_HOST_CRYPTOKEY_SEL = key_id;
+ P_CC3XX->host_rgf.host_cryptokey_sel = key_id;
/* Trigger the load into the key registers */
- *CC3XX_REG_AES_AES_SK = 0b1U;
+ P_CC3XX->aes.aes_sk = 0b1U;
} else {
switch (key_size) {
case CC3XX_AES_KEYSIZE_256:
- *CC3XX_REG_AES_AES_KEY_0_7 = ((uint32_t*)key)[7];
- *CC3XX_REG_AES_AES_KEY_0_6 = ((uint32_t*)key)[6];
+ for (idx = 7; idx >= 6; idx--) {
+ P_CC3XX->aes.aes_key_0[idx] = ((uint32_t*)key)[idx];
+ }
case CC3XX_AES_KEYSIZE_192:
- *CC3XX_REG_AES_AES_KEY_0_5 = ((uint32_t*)key)[5];
- *CC3XX_REG_AES_AES_KEY_0_4 = ((uint32_t*)key)[4];
+ for (idx = 5; idx >= 4; idx--) {
+ P_CC3XX->aes.aes_key_0[idx] = ((uint32_t*)key)[idx];
+ }
case CC3XX_AES_KEYSIZE_128:
- *CC3XX_REG_AES_AES_KEY_0_3 = ((uint32_t*)key)[3];
- *CC3XX_REG_AES_AES_KEY_0_2 = ((uint32_t*)key)[2];
- *CC3XX_REG_AES_AES_KEY_0_1 = ((uint32_t*)key)[1];
- *CC3XX_REG_AES_AES_KEY_0_0 = ((uint32_t*)key)[0];
+ for (idx = 3; idx >= 0; idx--) {
+ P_CC3XX->aes.aes_key_0[idx] = ((uint32_t*)key)[idx];
+ }
break;
default:
return CC3XX_ERR_NOT_IMPLEMENTED;
@@ -208,16 +216,16 @@
}
/* Set key size */
- *CC3XX_REG_AES_AES_CONTROL &= ~(0b11U << 12);
- *CC3XX_REG_AES_AES_CONTROL |= (key_size & 0b11U) << 12;
+ P_CC3XX->aes.aes_control &= ~(0b11U << 12);
+ P_CC3XX->aes.aes_control |= (key_size & 0b11U) << 12;
return CC3XX_ERR_SUCCESS;
}
#endif /* KMU_S */
cc3xx_err_t cc3xx_aes(cc3xx_aes_key_id_t key_id, const uint8_t *key,
- cc3xx_aes_keysize_t key_size, const uint8_t* in, size_t
- in_len, uint8_t* iv, uint8_t *out,
+ cc3xx_aes_keysize_t key_size, const uint8_t* in,
+ size_t in_len, uint8_t* iv, uint8_t *out,
cc3xx_aes_direction_t direction, cc3xx_aes_mode_t mode)
{
cc3xx_err_t err = CC3XX_ERR_SUCCESS;
@@ -230,27 +238,27 @@
}
/* Enable the aes engine clock */
- *CC3XX_REG_MISC_AES_CLK_ENABLE = 0x1U;
+ P_CC3XX->misc.aes_clk_enable = 0x1U;
/* Enable the DMA clock */
- *CC3XX_REG_MISC_DMA_CLK_ENABLE = 0x1U;
+ P_CC3XX->misc.dma_clk_enable = 0x1U;
/* Wait for the crypto engine to be ready */
- while (*CC3XX_REG_CC_CTL_CRYPTO_BUSY) {}
+ while (P_CC3XX->cc_ctl.crypto_busy) {}
/* Set the crypto engine to the AES engine */
- *CC3XX_REG_CC_CTL_CRYPTO_CTL = 0b00001U;
+ P_CC3XX->cc_ctl.crypto_ctl = 0b00001U;
/* Clear number of remaining bytes */
- *CC3XX_REG_AES_AES_REMAINING_BYTES = 0x0U;
+ P_CC3XX->aes.aes_remaining_bytes = 0x0U;
/* Set direction field of AES control register */
- *CC3XX_REG_AES_AES_CONTROL &= ~0b1U;
- *CC3XX_REG_AES_AES_CONTROL |= (direction & 0b1U);
+ P_CC3XX->aes.aes_control &= ~0b1U;
+ P_CC3XX->aes.aes_control |= (direction & 0b1U);
/* Set mode field of AES control register */
- *CC3XX_REG_AES_AES_CONTROL &= ~(0b111U << 2);
- *CC3XX_REG_AES_AES_CONTROL |= (mode & 0b111U) << 2;
+ P_CC3XX->aes.aes_control &= ~(0b111U << 2);
+ P_CC3XX->aes.aes_control |= (mode & 0b111U) << 2;
/* Set up the key */
err = cc3xx_aes_setkey(key_id, key, key_size);
@@ -278,13 +286,13 @@
out:
/* Set the crypto engine back to the default PASSTHROUGH engine */
- *CC3XX_REG_CC_CTL_CRYPTO_CTL = 0x0;
+ P_CC3XX->cc_ctl.crypto_ctl = 0x0;
/* Disable the hash engine clock */
- *CC3XX_REG_MISC_AES_CLK_ENABLE = 0x0U;
+ P_CC3XX->misc.aes_clk_enable = 0x0U;
/* Disable the DMA clock */
- *CC3XX_REG_MISC_DMA_CLK_ENABLE = 0x0U;
+ P_CC3XX->misc.dma_clk_enable = 0x0U;
return err;
}
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_aes.h b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_aes.h
index 37f5937..8a6b743 100644
--- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_aes.h
+++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_aes.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -45,9 +45,9 @@
} cc3xx_aes_key_id_t;
cc3xx_err_t cc3xx_aes(cc3xx_aes_key_id_t key_id, const uint8_t *key,
- cc3xx_aes_keysize_t key_size, const uint8_t* in, size_t
- in_len, uint8_t* iv, uint8_t *out,
- cc3xx_aes_direction_t direction, cc3xx_aes_mode_t mode);
+ cc3xx_aes_keysize_t key_size, const uint8_t* in,
+ size_t in_len, uint8_t* iv, uint8_t *out,
+ cc3xx_aes_direction_t direction, cc3xx_aes_mode_t mode);
#ifdef __cplusplus
}
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_config.h b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_config.h
index 5bd2e98..fb305d1 100644
--- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_config.h
+++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_config.h
@@ -1,10 +1,42 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
-#include "dx_reg_base_host.h"
+#ifndef CC3XX_CONFIG_H
+#define CC3XX_CONFIG_H
-#define CC3XX_BASE (DX_BASE_CC)
+#ifndef CC3XX_CONFIG_BASE_ADDRESS
+#include "platform_base_address.h"
+#endif /* CC3XX_CONFIG_BASE_ADDRESS */
+
+#ifndef CC3XX_CONFIG_BASE_ADDRESS
+#define CC3XX_CONFIG_BASE_ADDRESS (CC3XX_BASE_S)
+#endif /* CC3XX_CONFIG_BASE_ADDRESS */
+
+/* The number of times the TRNG will be re-read when it fails a statical test
+ * before an error is returned.
+ */
+#ifndef CC3XX_CONFIG_LOWLEVEL_RNG_MAX_ATTEMPTS
+#define CC3XX_CONFIG_LOWLEVEL_RNG_MAX_ATTEMPTS 16
+#endif /* CC3XX_CONFIG_LOWLEVEL_RNG_MAX_ATTEMPTS */
+
+/* This is the number of cycles between consecutive samples of the oscillator
+ * output. It needs to be set to a _reasonably_ large number, though It's
+ * unclear exactly what sort of number is reasonable. In general, if the
+ * statistical tests keep failing then increase it, if the RNG is too slow then
+ * decrease it. A sensible default is set here, and has worked correctly with a
+ * variety of cc3xx implementations.
+ */
+#ifndef CC3XX_CONFIG_LOWLEVEL_RNG_SUBSAMPLING_RATE
+#define CC3XX_CONFIG_LOWLEVEL_RNG_SUBSAMPLING_RATE 0x1337
+#endif /* !CC_RNG_SUBSAMPLING_RATE */
+
+/* Between 0 and 3 inclusive. 0 should be the fastest oscillator ring */
+#ifndef CC3XX_CONFIG_LOWLEVEL_RNG_RING_OSCILLATOR_ID
+#define CC3XX_CONFIG_LOWLEVEL_RNG_RING_OSCILLATOR_ID 0
+#endif /* !CC_RNG_RING_OSCILLATOR_ID */
+
+#endif /* CC3XX_CONFIG_H */
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_dev.h b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_dev.h
new file mode 100644
index 0000000..3b3cbaa
--- /dev/null
+++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_dev.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef CC3XX_DEV_H
+#define CC3XX_DEV_H
+
+#include <stdint.h>
+#include "cc3xx_config.h"
+#include "cc3xx_reg_defs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define P_CC3XX ((struct _cc3xx_reg_map_t * const)CC3XX_CONFIG_BASE_ADDRESS)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CC3XX_DEV_H */
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_dma.c b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_dma.c
index 54979f7..8a5ab92 100644
--- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_dma.c
+++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_dma.c
@@ -7,9 +7,7 @@
#include "cc3xx_dma.h"
-#include <string.h>
-
-#include "cc3xx_reg_defs.h"
+#include "cc3xx_dev.h"
#include "cc3xx_engine_state.h"
static cc3xx_dma_remap_region_t remap_regions[CC3XX_DMA_REMAP_REGION_AM] = {0};
@@ -42,6 +40,8 @@
cc3xx_err_t cc3xx_dma_tcm_cpusel(uint32_t cpuid)
{
remap_cpusel = cpuid;
+
+ return CC3XX_ERR_SUCCESS;
}
static uintptr_t remap_addr(uintptr_t addr)
@@ -73,13 +73,13 @@
}
/* Enable the DMA clock */
- *CC3XX_REG_MISC_DMA_CLK_ENABLE = 0x1U;
+ P_CC3XX->misc.dma_clk_enable = 0x1U;
/* Wait for the crypto engine to be ready */
- while (*CC3XX_REG_CC_CTL_CRYPTO_BUSY) {}
+ while (P_CC3XX->cc_ctl.crypto_busy) {}
/* Set the crypto engine to the PASSTHROUGH engine */
- *CC3XX_REG_CC_CTL_CRYPTO_CTL = 0b00000U;
+ P_CC3XX->cc_ctl.crypto_ctl = 0b00000U;
/* Set output target */
err = cc3xx_dma_set_output(dest, length);
@@ -92,7 +92,7 @@
out:
/* Disable the DMA clock */
- *CC3XX_REG_MISC_DMA_CLK_ENABLE = 0x0U;
+ P_CC3XX->misc.dma_clk_enable = 0x0U;
return err;
}
@@ -107,30 +107,30 @@
}
/* Mask a sensible set of the host interrupts */
- *CC3XX_REG_HOST_RGF_HOST_RGF_IMR = 0xFF0U;
+ P_CC3XX->host_rgf.host_rgf_imr = 0xFF0U;
/* Reset the AXI_ERROR and SYM_DMA_COMPLETED interrupts */
- *CC3XX_REG_HOST_RGF_HOST_RGF_ICR |= 0x900U;
+ P_CC3XX->host_rgf.host_rgf_icr |= 0x900U;
/* remap the address, particularly for TCMs */
remapped_buf = remap_addr((uintptr_t)buf);
/* Set the data source */
- *CC3XX_REG_DIN_SRC_LLI_WORD0 = remapped_buf;
+ P_CC3XX->din.src_lli_word0 = remapped_buf;
/* Writing the length triggers the DMA */
- *CC3XX_REG_DIN_SRC_LLI_WORD1 = length;
+ P_CC3XX->din.src_lli_word1 = length;
/* Wait for the DMA to complete (The SYM_DMA_COMPLETED interrupt to be
* asserted)
*/
- while (!(*CC3XX_REG_HOST_RGF_HOST_RGF_IRR & 0x800U)){
- if (*CC3XX_REG_HOST_RGF_HOST_RGF_IRR & 0x100U) {
+ while (!(P_CC3XX->host_rgf.host_rgf_irr & 0x800U)){
+ if (P_CC3XX->host_rgf.host_rgf_irr & 0x100U) {
return CC3XX_ERR_GENERIC_ERROR;
}
}
/* Reset the SYM_DMA_COMPLETED interrupt */
- *CC3XX_REG_HOST_RGF_HOST_RGF_ICR = 0x800U;
+ P_CC3XX->host_rgf.host_rgf_icr = 0x800U;
return CC3XX_ERR_SUCCESS;
}
@@ -143,9 +143,10 @@
remapped_buf = remap_addr((uintptr_t)buf);
/* Set the data target */
- *CC3XX_REG_DOUT_DST_LLI_WORD0 = remapped_buf;
+ P_CC3XX->dout.dst_lli_word0 = remapped_buf;
+
/* And the length */
- *CC3XX_REG_DOUT_DST_LLI_WORD1 = length;
+ P_CC3XX->dout.dst_lli_word1 = length;
return CC3XX_ERR_SUCCESS;
}
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_dma.h b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_dma.h
index 05b1e13..359f6ff 100644
--- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_dma.h
+++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_dma.h
@@ -12,6 +12,7 @@
#include <stdint.h>
#include <stddef.h>
+#include <string.h>
#ifndef CC3XX_DMA_REMAP_REGION_AM
#define CC3XX_DMA_REMAP_REGION_AM 4
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_drv.h b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_drv.h
new file mode 100644
index 0000000..c868aff
--- /dev/null
+++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_drv.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef CC3XX_DRV_H
+#define CC3XX_DRV_H
+
+#include "cc3xx_init.h"
+#include "cc3xx_rng.h"
+#include "cc3xx_aes.h"
+#include "cc3xx_hash.h"
+#include "cc3xx_lcs.h"
+#include "cc3xx_otp.h"
+#include "cc3xx_dma.h"
+
+#endif /* CC3XX_DRV_H */
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_hash.c b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_hash.c
index 48dab35..d9daf87 100644
--- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_hash.c
+++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_hash.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -7,8 +7,8 @@
#include "cc3xx_hash.h"
+#include "cc3xx_dev.h"
#include "cc3xx_error.h"
-#include "cc3xx_reg_defs.h"
#include "cc3xx_dma.h"
#include "cc3xx_engine_state.h"
@@ -35,7 +35,8 @@
return out;
}
-cc3xx_err_t cc3xx_hash_sha256_init() {
+cc3xx_err_t cc3xx_hash_sha256_init(void)
+{
if (cc3xx_engine_in_use) {
return CC3XX_ERR_ENGINE_IN_USE;
@@ -43,68 +44,70 @@
cc3xx_engine_in_use = true;
/* Enable the hash engine clock */
- *CC3XX_REG_MISC_HASH_CLK_ENABLE = 0x1U;
+ P_CC3XX->misc.hash_clk_enable = 0x1U;
/* Enable the DMA clock */
- *CC3XX_REG_MISC_DMA_CLK_ENABLE = 0x1U;
+ P_CC3XX->misc.dma_clk_enable = 0x1U;
/* Wait for the crypto engine to be ready */
- while (*CC3XX_REG_CC_CTL_CRYPTO_BUSY) {}
+ while (P_CC3XX->cc_ctl.crypto_busy) {}
/* Set the crypto engine to the HASH engine */
- *CC3XX_REG_CC_CTL_CRYPTO_CTL = 0b00111U;
+ P_CC3XX->cc_ctl.crypto_ctl = 0b00111U;
/* Select HASH mode, not MAC */
- *CC3XX_REG_HASH_HASH_SEL_AES_MAC = 0x0U;
+ P_CC3XX->hash.hash_sel_aes_mac = 0x0U;
/* Configure the hash engine to SHA256 */
- *CC3XX_REG_HASH_HASH_CONTROL = 0b0010U;
+ P_CC3XX->hash.hash_control = 0b0010U;
/* Enable padding */
- *CC3XX_REG_HASH_HASH_PAD_EN = 0x1U;
+ P_CC3XX->hash.hash_pad_en = 0x1U;
/* Disable auto-padding to allow multipart operations */
- *CC3XX_REG_HASH_AUTO_HW_PADDING = 0x0U;
+ P_CC3XX->hash.auto_hw_padding = 0x0U;
/* Set already processed length to 0 */
- *CC3XX_REG_HASH_HASH_CUR_LEN_0 = 0x0U;
- *CC3XX_REG_HASH_HASH_CUR_LEN_1 = 0x0U;
+ P_CC3XX->hash.hash_cur_len[0] = 0x0U;
+ P_CC3XX->hash.hash_cur_len[1] = 0x0U;
/* Set the registers to the magic initial values of sha256. CryptoCell
* hardware requires the writes to happen in reverse order
* (from H7 to H0).
*/
- *CC3XX_REG_HASH_HASH_H7 = 0x5be0cd19U;
- *CC3XX_REG_HASH_HASH_H6 = 0x1f83d9abU;
- *CC3XX_REG_HASH_HASH_H5 = 0x9b05688cU;
- *CC3XX_REG_HASH_HASH_H4 = 0x510e527fU;
- *CC3XX_REG_HASH_HASH_H3 = 0xa54ff53aU;
- *CC3XX_REG_HASH_HASH_H2 = 0x3c6ef372U;
- *CC3XX_REG_HASH_HASH_H1 = 0xbb67ae85U;
- *CC3XX_REG_HASH_HASH_H0 = 0x6a09e667U;
+ P_CC3XX->hash.hash_h[7] = 0x5be0cd19U;
+ P_CC3XX->hash.hash_h[6] = 0x1f83d9abU;
+ P_CC3XX->hash.hash_h[5] = 0x9b05688cU;
+ P_CC3XX->hash.hash_h[4] = 0x510e527fU;
+ P_CC3XX->hash.hash_h[3] = 0xa54ff53aU;
+ P_CC3XX->hash.hash_h[2] = 0x3c6ef372U;
+ P_CC3XX->hash.hash_h[1] = 0xbb67ae85U;
+ P_CC3XX->hash.hash_h[0] = 0x6a09e667U;
return CC3XX_ERR_SUCCESS;
}
-static void hash_uninit()
+static void hash_uninit(void)
{
/* Reset padding registers as required by the hardware */
- *CC3XX_REG_HASH_HASH_PAD_CFG = 0x0U;
- *CC3XX_REG_HASH_AUTO_HW_PADDING = 0x0U;
+ P_CC3XX->hash.hash_pad_cfg = 0x0U;
+ P_CC3XX->hash.auto_hw_padding = 0x0U;
/* Set the crypto engine back to the default PASSTHROUGH engine */
- *CC3XX_REG_CC_CTL_CRYPTO_CTL = 0x0U;
+ P_CC3XX->cc_ctl.crypto_ctl = 0x0U;
/* Disable the hash engine clock */
- *CC3XX_REG_MISC_HASH_CLK_ENABLE = 0x0U;
+ P_CC3XX->misc.hash_clk_enable = 0x0U;
/* Disable the DMA clock */
- *CC3XX_REG_MISC_DMA_CLK_ENABLE = 0x0U;
+ P_CC3XX->misc.dma_clk_enable = 0x0U;
cc3xx_engine_in_use = false;
}
-cc3xx_err_t cc3xx_hash_sha256_update(const uint8_t *buf, size_t length) {
+cc3xx_err_t cc3xx_hash_sha256_update(const uint8_t *buf,
+ size_t length)
+{
size_t current_processed_length = 0;
size_t partial_block_size_free = SHA256_BLOCK_SIZE - cc3xx_hash_partial_block_size;
size_t partial_block_size_increase = 0;
@@ -132,7 +135,7 @@
/* If the unprocessed data buffer is full then write it out */
if (cc3xx_hash_partial_block_size == SHA256_BLOCK_SIZE) {
err = cc3xx_dma_input_data(cc3xx_hash_partial_block_buf,
- cc3xx_hash_partial_block_size);
+ cc3xx_hash_partial_block_size);
if (err != CC3XX_ERR_SUCCESS) {
hash_uninit();
return err;
@@ -170,8 +173,12 @@
return CC3XX_ERR_SUCCESS;
}
-cc3xx_err_t cc3xx_hash_sha256_finish(uint8_t *res, size_t length) {
+cc3xx_err_t cc3xx_hash_sha256_finish(uint8_t *res,
+ size_t length)
+{
cc3xx_err_t err = CC3XX_ERR_SUCCESS;
+ uint32_t tmp_buf[SHA256_OUTPUT_SIZE / sizeof(uint32_t)];
+ uint32_t idx;
if (length < SHA256_OUTPUT_SIZE) {
hash_uninit();
@@ -180,9 +187,9 @@
/* Process the final block */
if (cc3xx_hash_partial_block_size > 0) {
- *CC3XX_REG_HASH_AUTO_HW_PADDING = 0x1U;
+ P_CC3XX->hash.auto_hw_padding = 0x1U;
err = cc3xx_dma_input_data(cc3xx_hash_partial_block_buf,
- cc3xx_hash_partial_block_size);
+ cc3xx_hash_partial_block_size);
if (err) {
hash_uninit();
return err;
@@ -191,19 +198,16 @@
}
/* Special-case for hardware padding when the length is 0 */
- if (*CC3XX_REG_HASH_HASH_CUR_LEN_0 == 0
- && *CC3XX_REG_HASH_HASH_CUR_LEN_1 == 0) {
- *CC3XX_REG_HASH_HASH_PAD_CFG = 0x4U;
+ if (P_CC3XX->hash.hash_cur_len[0] == 0
+ && P_CC3XX->hash.hash_cur_len[1] == 0) {
+ P_CC3XX->hash.hash_pad_cfg = 0x4U;
}
- ((uint32_t*)res)[0] = bswap_32(*CC3XX_REG_HASH_HASH_H0);
- ((uint32_t*)res)[1] = bswap_32(*CC3XX_REG_HASH_HASH_H1);
- ((uint32_t*)res)[2] = bswap_32(*CC3XX_REG_HASH_HASH_H2);
- ((uint32_t*)res)[3] = bswap_32(*CC3XX_REG_HASH_HASH_H3);
- ((uint32_t*)res)[4] = bswap_32(*CC3XX_REG_HASH_HASH_H4);
- ((uint32_t*)res)[5] = bswap_32(*CC3XX_REG_HASH_HASH_H5);
- ((uint32_t*)res)[6] = bswap_32(*CC3XX_REG_HASH_HASH_H6);
- ((uint32_t*)res)[7] = bswap_32(*CC3XX_REG_HASH_HASH_H7);
+ for (idx = 0; idx < 8; idx++) {
+ ((uint32_t*)res)[idx] = bswap_32(P_CC3XX->hash.hash_h[idx]);
+ }
+
+ memcpy(res, tmp_buf, sizeof(tmp_buf));
hash_uninit();
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_hash.h b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_hash.h
index 77205db..e36d112 100644
--- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_hash.h
+++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_hash.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -19,7 +19,7 @@
extern "C" {
#endif
-cc3xx_err_t cc3xx_hash_sha256_init();
+cc3xx_err_t cc3xx_hash_sha256_init(void);
cc3xx_err_t cc3xx_hash_sha256_update(const uint8_t *buf, size_t length);
cc3xx_err_t cc3xx_hash_sha256_finish(uint8_t *res, size_t length);
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_init.c b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_init.c
index a2e63c4..224dbd3 100644
--- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_init.c
+++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -7,22 +7,22 @@
#include "cc3xx_init.h"
-#include "cc3xx_reg_defs.h"
+#include "cc3xx_dev.h"
cc3xx_err_t cc3xx_init(void)
{
/* Configure entire system to litte endian */
- *CC3XX_REG_HOST_RGF_HOST_RGF_ENDIAN = 0x0U;
+ P_CC3XX->host_rgf.host_rgf_endian = 0x0U;
/* Disable the DFA countermeasures since they're unsupported, and lock the
* config option.
*/
- *CC3XX_REG_AO_HOST_AO_LOCK_BITS &= ~(0b1U << 7);
- *CC3XX_REG_AO_HOST_AO_LOCK_BITS |= 0b1U << 8;
- *CC3XX_REG_AES_AES_DFA_IS_ON = 0b0U;
+ P_CC3XX->ao.host_ao_lock_bits &= ~(0b1U << 7);
+ P_CC3XX->ao.host_ao_lock_bits |= 0b1U << 8;
+ P_CC3XX->aes.aes_dfa_is_on = 0b0U;
/* Set AHB to secure */
- *CC3XX_REG_AHB_AHBM_HNONSEC = 0b00U;
+ P_CC3XX->ahb.ahbm_hnonsec = 0b00U;
return CC3XX_ERR_SUCCESS;
}
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_init.h b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_init.h
index d9ddb87..d3149b7 100644
--- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_init.h
+++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_init.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -9,6 +9,7 @@
#define CC3XX_INIT_H
#include "cc3xx_error.h"
+#include "cc3xx_dev.h"
#include <stdint.h>
#include <stddef.h>
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_lcs.c b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_lcs.c
index 6315293..26cc0c3 100644
--- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_lcs.c
+++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_lcs.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -7,21 +7,22 @@
#include "cc3xx_lcs.h"
+#include "cc3xx_dev.h"
#include "cc3xx_lcs_defs.h"
-#include "cc3xx_reg_defs.h"
#include "cc3xx_error.h"
-cc3xx_err_t cc3xx_lcs_get(cc3xx_lcs_t* lcs){
+cc3xx_err_t cc3xx_lcs_get(cc3xx_lcs_t* lcs)
+{
uint32_t code = 0;
/* Wait until the NVM controller is idle */
- while (! (*CC3XX_REG_NVM_NVM_IS_IDLE & 0b1U)) {}
+ while (! (P_CC3XX->nvm.nvm_is_idle & 0b1U)) {}
- if (! (*CC3XX_REG_NVM_LCS_IS_VALID & 0b1U)) {
+ if (! (P_CC3XX->nvm.lcs_is_valid & 0b1U)) {
return CC3XX_ERR_INVALID_LCS;
}
- code = *CC3XX_REG_NVM_LCS_REG & 0b111U;
+ code = P_CC3XX->nvm.lcs_reg & 0b111U;
switch(code) {
case CC3XX_LCS_CM_CODE:
@@ -43,7 +44,8 @@
return CC3XX_ERR_SUCCESS;
}
-const char* cc3xx_lcs_get_name(cc3xx_lcs_t lcs) {
+const char* cc3xx_lcs_get_name(cc3xx_lcs_t lcs)
+{
switch(lcs) {
case cc3xx_lcs_cm:
return "LCS_CM";
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_otp.c b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_otp.c
index 1def398..ce1229c 100644
--- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_otp.c
+++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_otp.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -7,17 +7,19 @@
#include "cc3xx_otp.h"
-#include "cc3xx_reg_defs.h"
+#include "cc3xx_dev.h"
#include <stdint.h>
#include <stddef.h>
#include <string.h>
-void cc3xx_otp_wait_until_fuse_programming_complete(void) {
- while (! (*CC3XX_REG_NVM_AIB_FUSE_PROG_COMPLETED & 1)) {}
+static void cc3xx_otp_wait_until_fuse_programming_complete(void) {
+
+ while (! (P_CC3XX->nvm.aib_fuse_prog_completed & 1)) {}
}
-cc3xx_err_t cc3xx_otp_write(uint8_t *otp_addr, size_t size, const uint8_t *buf)
+cc3xx_err_t cc3xx_otp_write(uint8_t *otp_addr,
+ size_t size, const uint8_t *buf)
{
uint32_t* word_ptr;
uint32_t current_word;
@@ -74,7 +76,8 @@
return CC3XX_ERR_SUCCESS;
}
-cc3xx_err_t cc3xx_otp_read(const uint8_t *otp_addr, size_t size, uint8_t *buf)
+cc3xx_err_t cc3xx_otp_read(const uint8_t *otp_addr,
+ size_t size, uint8_t *buf)
{
uint32_t* word_ptr;
uint32_t word;
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_otp.h b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_otp.h
index 25e40c8..5dad454 100644
--- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_otp.h
+++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_otp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -9,7 +9,6 @@
#define CC3XX_OTP_H
#include "cc3xx_error.h"
-#include "cc3xx_otp_defs.h"
#include <stdint.h>
#include <stddef.h>
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_otp_defs.h b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_otp_defs.h
deleted file mode 100644
index a4818c7..0000000
--- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_otp_defs.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#ifndef CC3XX_OTP_DEFS_H
-#define CC3XX_OTP_DEFS_H
-
-#include "cc3xx_config.h"
-#include "cmsis_compiler.h"
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef CC3XX_OTP_BASE
-#define CC3XX_OTP_BASE (CC_BASE + 0x2000)
-#endif /* !CC_OTP_BASE */
-
-#ifndef CC3XX_OTP_GENERAL_PURPOSE_CUSTOM_VIEW
-#define CC3XX_OTP_GENERAL_PURPOSE_CUSTOM_VIEW __PACKED_UNION {};
-#endif /* CC3XX_OTP_GENERAL_PURPOSE_CUSTOM_VIEW */
-
-typedef __PACKED_STRUCT {
- uint32_t huk[0x8];
- uint32_t icv_provisioning_key[0x4];
- uint32_t icv_code_encryption_key[0x4];
- uint32_t icv_programmed_flags[0x1];
- __PACKED_UNION {
- uint32_t rot_public_key[0x8];
- __PACKED_STRUCT {
- uint32_t icv_rot_public_key[0x4];
- uint32_t oem_rot_public_key[0x4];
- };
- };
- uint32_t oem_provisioning_secret[0x4];
- uint32_t oem_code_encryption_key[0x4];
- uint32_t oem_programmed_flags[0x1];
- __PACKED_UNION {
- uint32_t nv_counter[0x5];
- __PACKED_STRUCT {
- uint32_t icv_nv_counter[0x2];
- uint32_t oem_nv_counter[0x3];
- };
- };
- uint32_t general_purpose_configuration_flags[0x4];
- uint32_t dcu_debug_lock_mask[0x4];
- __PACKED_UNION {
- uint32_t general_purpose_code_data[0x7d4];
- CC3XX_OTP_GENERAL_PURPOSE_CUSTOM_VIEW;
- };
-} cc3xx_otp_memory_t;
-
-#define CC3XX_OTP ((volatile cc3xx_otp_memory_t *) CC3XX_OTP_BASE)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* CC3XX_OTP_DEFS_H */
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_reg_defs.h b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_reg_defs.h
index 8b9c8c0ae..a716b5b 100644
--- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_reg_defs.h
+++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_reg_defs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -8,202 +8,582 @@
#ifndef CC3XX_REG_DEFS_H
#define CC3XX_REG_DEFS_H
-#include "cc3xx_config.h"
-
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
-typedef volatile uint32_t *cc3xx_reg_t;
+#ifndef __IM
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#endif /* __IM */
-#ifndef CC3XX_REG_BASE
-#define CC3XX_REG_BASE CC3XX_BASE
-#endif /* !CC3XX_REG_BASE */
+#ifndef __OM
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#endif /* __OM */
-/* RNG registers */
-#define CC3XX_REG_RNG_RNG_IMR (cc3xx_reg_t)(CC3XX_REG_BASE + 0x100U)
-#define CC3XX_REG_RNG_RNG_ISR (cc3xx_reg_t)(CC3XX_REG_BASE + 0x104U)
-#define CC3XX_REG_RNG_RNG_ICR (cc3xx_reg_t)(CC3XX_REG_BASE + 0x108U)
-#define CC3XX_REG_RNG_TRNG_CONFIG (cc3xx_reg_t)(CC3XX_REG_BASE + 0x10CU)
-#define CC3XX_REG_RNG_TRNG_VALID (cc3xx_reg_t)(CC3XX_REG_BASE + 0x110U)
-#define CC3XX_REG_RNG_EHR_DATA_0 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x114U)
-#define CC3XX_REG_RNG_EHR_DATA_1 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x118U)
-#define CC3XX_REG_RNG_EHR_DATA_2 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x11CU)
-#define CC3XX_REG_RNG_EHR_DATA_3 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x120U)
-#define CC3XX_REG_RNG_EHR_DATA_4 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x124U)
-#define CC3XX_REG_RNG_EHR_DATA_5 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x128U)
-#define CC3XX_REG_RNG_RND_SOURCE_ENABLE (cc3xx_reg_t)(CC3XX_REG_BASE + 0x12CU)
-#define CC3XX_REG_RNG_SAMPLE_CNT1 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x130U)
-#define CC3XX_REG_RNG_AUTOCORR_STATISTIC (cc3xx_reg_t)(CC3XX_REG_BASE + 0x134U)
-#define CC3XX_REG_RNG_TRNG_DEBUG_CONTROL (cc3xx_reg_t)(CC3XX_REG_BASE + 0x138U)
-#define CC3XX_REG_RNG_RNG_SW_RESET (cc3xx_reg_t)(CC3XX_REG_BASE + 0x140U)
-#define CC3XX_REG_RNG_RNG_DEBUG_EN_INPUT (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1B4U)
-#define CC3XX_REG_RNG_RNG_BUSY (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1B8U)
-#define CC3XX_REG_RNG_RST_BITS_COUNTER (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1BCU)
-#define CC3XX_REG_RNG_RNG_VERSION (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1C0U)
-#define CC3XX_REG_RNG_RNG_CLK_ENABLE (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1C4U)
-#define CC3XX_REG_RNG_RNG_DMA_ENABLE (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1C8U)
-#define CC3XX_REG_RNG_RNG_DMA_SRC_MASK (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1CCU)
-#define CC3XX_REG_RNG_RNG_DMA_SRAM_ADDR (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1D0U)
-#define CC3XX_REG_RNG_RNG_DMA_SAMPLES_NUM (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1D4U)
-#define CC3XX_REG_RNG_RNG_WATCHDOG_VAL (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1D8U)
-#define CC3XX_REG_RNG_RNG_DMA_STATUS (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1DCU)
+#ifndef __IOM
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+#endif /* __IOM */
-/* AES registers */
-#define CC3XX_REG_AES_AES_KEY_0_0 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x400U)
-#define CC3XX_REG_AES_AES_KEY_0_1 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x404U)
-#define CC3XX_REG_AES_AES_KEY_0_2 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x408U)
-#define CC3XX_REG_AES_AES_KEY_0_3 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x40CU)
-#define CC3XX_REG_AES_AES_KEY_0_4 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x410U)
-#define CC3XX_REG_AES_AES_KEY_0_5 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x414U)
-#define CC3XX_REG_AES_AES_KEY_0_6 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x418U)
-#define CC3XX_REG_AES_AES_KEY_0_7 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x41CU)
-#define CC3XX_REG_AES_AES_KEY_1_0 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x420U)
-#define CC3XX_REG_AES_AES_KEY_1_1 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x424U)
-#define CC3XX_REG_AES_AES_KEY_1_2 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x428U)
-#define CC3XX_REG_AES_AES_KEY_1_3 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x42CU)
-#define CC3XX_REG_AES_AES_KEY_1_4 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x430U)
-#define CC3XX_REG_AES_AES_KEY_1_5 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x434U)
-#define CC3XX_REG_AES_AES_KEY_1_6 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x438U)
-#define CC3XX_REG_AES_AES_KEY_1_7 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x43CU)
-#define CC3XX_REG_AES_AES_IV_0_0 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x440U)
-#define CC3XX_REG_AES_AES_IV_0_1 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x444U)
-#define CC3XX_REG_AES_AES_IV_0_2 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x448U)
-#define CC3XX_REG_AES_AES_IV_0_3 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x44CU)
-#define CC3XX_REG_AES_AES_IV_1_0 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x450U)
-#define CC3XX_REG_AES_AES_IV_1_1 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x454U)
-#define CC3XX_REG_AES_AES_IV_1_2 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x458U)
-#define CC3XX_REG_AES_AES_IV_1_3 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x45CU)
-#define CC3XX_REG_AES_AES_CTR_0_0 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x460U)
-#define CC3XX_REG_AES_AES_CTR_0_1 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x464U)
-#define CC3XX_REG_AES_AES_CTR_0_2 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x468U)
-#define CC3XX_REG_AES_AES_CTR_0_3 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x46CU)
-#define CC3XX_REG_AES_AES_BUSY (cc3xx_reg_t)(CC3XX_REG_BASE + 0x470U)
-#define CC3XX_REG_AES_AES_SK (cc3xx_reg_t)(CC3XX_REG_BASE + 0x478U)
-#define CC3XX_REG_AES_AES_CMAC_INIT (cc3xx_reg_t)(CC3XX_REG_BASE + 0x47CU)
-#define CC3XX_REG_AES_AES_SK1 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x4B4U)
-#define CC3XX_REG_AES_AES_REMAINING_BYTES (cc3xx_reg_t)(CC3XX_REG_BASE + 0x4BCU)
-#define CC3XX_REG_AES_AES_CONTROL (cc3xx_reg_t)(CC3XX_REG_BASE + 0x4C0U)
-#define CC3XX_REG_AES_AES_HW_FLAGS (cc3xx_reg_t)(CC3XX_REG_BASE + 0x4C8U)
-#define CC3XX_REG_AES_AES_CTR_NO_INCREMENT (cc3xx_reg_t)(CC3XX_REG_BASE + 0x4D8U)
-#define CC3XX_REG_AES_AES_DFA_IS_ON (cc3xx_reg_t)(CC3XX_REG_BASE + 0x4F0U)
-#define CC3XX_REG_AES_AES_DFA_ERR_STATUS (cc3xx_reg_t)(CC3XX_REG_BASE + 0x4F8U)
-#define CC3XX_REG_AES_AES_CMAC_SIZE0_KICK (cc3xx_reg_t)(CC3XX_REG_BASE + 0x524U)
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif /* __PACKED_STRUCT */
-/* HASH registers */
-#define CC3XX_REG_HASH_HASH_H0 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x640)
-#define CC3XX_REG_HASH_HASH_H1 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x644)
-#define CC3XX_REG_HASH_HASH_H2 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x648)
-#define CC3XX_REG_HASH_HASH_H3 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x64C)
-#define CC3XX_REG_HASH_HASH_H4 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x650)
-#define CC3XX_REG_HASH_HASH_H5 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x654)
-#define CC3XX_REG_HASH_HASH_H6 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x658)
-#define CC3XX_REG_HASH_HASH_H7 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x65C)
-#define CC3XX_REG_HASH_HASH_H8 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x660)
-#define CC3XX_REG_HASH_AUTO_HW_PADDING (cc3xx_reg_t)(CC3XX_REG_BASE + 0x684)
-#define CC3XX_REG_HASH_HASH_XOR_DIN (cc3xx_reg_t)(CC3XX_REG_BASE + 0x688)
-#define CC3XX_REG_HASH_LOAD_INIT_STATE (cc3xx_reg_t)(CC3XX_REG_BASE + 0x694)
-#define CC3XX_REG_HASH_HASH_SEL_AES_MAC (cc3xx_reg_t)(CC3XX_REG_BASE + 0x6A4)
-#define CC3XX_REG_HASH_HASH_VERSION (cc3xx_reg_t)(CC3XX_REG_BASE + 0x7B0)
-#define CC3XX_REG_HASH_HASH_CONTROL (cc3xx_reg_t)(CC3XX_REG_BASE + 0x7C0)
-#define CC3XX_REG_HASH_HASH_PAD_EN (cc3xx_reg_t)(CC3XX_REG_BASE + 0x7C4)
-#define CC3XX_REG_HASH_HASH_PAD_CFG (cc3xx_reg_t)(CC3XX_REG_BASE + 0x7C8)
-#define CC3XX_REG_HASH_HASH_CUR_LEN_0 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x7CC)
-#define CC3XX_REG_HASH_HASH_CUR_LEN_1 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x7D0)
-#define CC3XX_REG_HASH_HASH_PARAM (cc3xx_reg_t)(CC3XX_REG_BASE + 0x7DC)
+#ifndef __PACKED_UNION
+#define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif /* __PACKED_UNION */
-/* MISC registers */
-#define CC3XX_REG_MISC_AES_CLK_ENABLE (cc3xx_reg_t)(CC3XX_REG_BASE + 0x810)
-#define CC3XX_REG_MISC_HASH_CLK_ENABLE (cc3xx_reg_t)(CC3XX_REG_BASE + 0x818)
-#define CC3XX_REG_MISC_PKA_CLK_ENABLE (cc3xx_reg_t)(CC3XX_REG_BASE + 0x81C)
-#define CC3XX_REG_MISC_DMA_CLK_ENABLE (cc3xx_reg_t)(CC3XX_REG_BASE + 0x820)
-#define CC3XX_REG_MISC_CLK_STATUS (cc3xx_reg_t)(CC3XX_REG_BASE + 0x824)
-#define CC3XX_REG_MISC_CHACHA_CLK_ENABLE (cc3xx_reg_t)(CC3XX_REG_BASE + 0x858)
+#ifndef __ALIGNED
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#endif /* __ALIGNED */
-/* CC_CTL registers */
-#define CC3XX_REG_CC_CTL_CRYPTO_CTL (cc3xx_reg_t)(CC3XX_REG_BASE + 0x900)
-#define CC3XX_REG_CC_CTL_CRYPTO_BUSY (cc3xx_reg_t)(CC3XX_REG_BASE + 0x910)
-#define CC3XX_REG_CC_CTL_HASH_BUSY (cc3xx_reg_t)(CC3XX_REG_BASE + 0x91C)
-#define CC3XX_REG_CC_CTL_CONTEXT_ID (cc3xx_reg_t)(CC3XX_REG_BASE + 0x930)
+__PACKED_STRUCT __ALIGNED(4) _cc3xx_reg_map_t {
+ /* PKA block */
+ __PACKED_STRUCT {
+ __IOM uint32_t memory_map[32];
+ /*!< Offset: 0x0 (RW) */
+ __IOM uint32_t opcode;
+ /*!< Offset: 0x80 (RW) */
+ __IOM uint32_t n_np_t0_t1_addr;
+ /*!< Offset: 0x84 (RW) */
+ __IM uint32_t pka_status;
+ /*!< Offset: 0x88 (RO) */
+ __OM uint32_t pka_sw_reset;
+ /*!< Offset: 0x8C (WO) */
+ __IOM uint32_t pka_l[8];
+ /*!< Offset: 0x90 (RW) */
+ __IM uint32_t pka_pipe_rdy;
+ /*!< Offset: 0xB0 (RO) */
+ __IM uint32_t pka_done;
+ /*!< Offset: 0xB4 (RO) */
+ __IOM uint32_t pka_mon_select;
+ /*!< Offset: 0xB8 (RW) */
+ __IOM uint32_t pka_mongo_sel;
+ /*!< Offset: 0xBC (RW) */
+ __IOM uint32_t pka_ram_enc;
+ /*!< Offset: 0xC0 (RW) */
+ __IM uint32_t pka_version;
+ /*!< Offset: 0xC4 (RO) */
+ uint8_t _reserved_1[8];
+ /*!< Offset: 0xC8-0xCC Reserved */
+ __IM uint32_t pka_mon_read;
+ /*!< Offset: 0xD0 (RO) */
+ __OM uint32_t pka_sram_addr;
+ /*!< Offset: 0xD4 (WO) */
+ __OM uint32_t pka_sram_wdata;
+ /*!< Offset: 0xD8 (WO) */
+ __IOM uint32_t pka_sram_rdata;
+ /*!< Offset: 0xDC (RW) */
+ __OM uint32_t pka_sram_wr_clr;
+ /*!< Offset: 0xE0 (WO) */
+ __OM uint32_t pka_sram_raddr;
+ /*!< Offset: 0xE4 (WO) */
+ uint8_t _reserved_2[8];
+ /*!< Offset: 0xE8-0xEC Reserved */
+ __OM uint32_t pka_word_access;
+ /*!< Offset: 0xF0 (WO) */
+ uint8_t _reserved_3[4];
+ /*!< Offset: 0xF4 Reserved */
+ __OM uint32_t pka_buff_addr;
+ /*!< Offset: 0xF8 (WO) */
+ uint8_t _reserved_4[4];
+ /*!< Offset: 0xFC Reserved */
+ } pka;
-/* HOST_RGF registers */
-#define CC3XX_REG_HOST_RGF_HOST_RGF_IRR (cc3xx_reg_t)(CC3XX_REG_BASE + 0xA00)
-#define CC3XX_REG_HOST_RGF_HOST_RGF_IMR (cc3xx_reg_t)(CC3XX_REG_BASE + 0xA04)
-#define CC3XX_REG_HOST_RGF_HOST_RGF_ICR (cc3xx_reg_t)(CC3XX_REG_BASE + 0xA08)
-#define CC3XX_REG_HOST_RGF_HOST_RGF_ENDIAN (cc3xx_reg_t)(CC3XX_REG_BASE + 0xA0C)
-#define CC3XX_REG_HOST_RGF_HOST_RGF_SIGNATURE (cc3xx_reg_t)(CC3XX_REG_BASE + 0xA24)
-#define CC3XX_REG_HOST_RGF_HOST_BOOT (cc3xx_reg_t)(CC3XX_REG_BASE + 0xA28)
-#define CC3XX_REG_HOST_RGF_HOST_CRYPTOKEY_SEL (cc3xx_reg_t)(CC3XX_REG_BASE + 0xA38)
-#define CC3XX_REG_HOST_RGF_HOST_CORE_CLK_GATING_ENABLE (cc3xx_reg_t)(CC3XX_REG_BASE + 0xA78)
-#define CC3XX_REG_HOST_RGF_HOST_CC_IS_IDLE (cc3xx_reg_t)(CC3XX_REG_BASE + 0xA7C)
-#define CC3XX_REG_HOST_RGF_HOST_POWERDOWN (cc3xx_reg_t)(CC3XX_REG_BASE + 0xA80)
-#define CC3XX_REG_HOST_RGF_HOST_REMOVE_GHASH_ENGINE (cc3xx_reg_t)(CC3XX_REG_BASE + 0xA84)
-#define CC3XX_REG_HOST_RGF_HOST_REMOVE_CHACHA_ENGINE (cc3xx_reg_t)(CC3XX_REG_BASE + 0xA88)
+ /* RNG block */
+ __PACKED_STRUCT {
+ __IOM uint32_t rng_imr;
+ /*!< Offset: 0x100 (RW) */
+ __IM uint32_t rng_isr;
+ /*!< Offset: 0x104 (RO) */
+ __OM uint32_t rng_icr;
+ /*!< Offset: 0x108 (WO) */
+ __IOM uint32_t trng_config;
+ /*!< Offset: 0x10C (RW) */
+ __IM uint32_t trng_valid;
+ /*!< Offset: 0x110 (RO) */
+ __IM uint32_t ehr_data[6];
+ /*!< Offset: 0x114 (RO) */
+ __IOM uint32_t rnd_source_enable;
+ /*!< Offset: 0x12C (RW) */
+ __IOM uint32_t sample_cnt1;
+ /*!< Offset: 0x130 (RW) */
+ __IOM uint32_t autocorr_statistic;
+ /*!< Offset: 0x134 (RW) */
+ __IOM uint32_t trng_debug_control;
+ /*!< Offset: 0x138 (RW) */
+ uint8_t _reserved_0[4];
+ /*!< Offset: 0x13C Reserved */
+ __IOM uint32_t rng_sw_reset;
+ /*!< Offset: 0x140 (RW) */
+ uint8_t _reserved_1[112];
+ /*!< Offset: 0x144-0x1B0 Reserved */
+ __IM uint32_t rng_debug_en_input;
+ /*!< Offset: 0x1B4 (RO) */
+ __IM uint32_t rng_busy;
+ /*!< Offset: 0x1B8 (RO) */
+ __OM uint32_t rst_bits_counter;
+ /*!< Offset: 0x1BC (WO) */
+ __IM uint32_t rng_version;
+ /*!< Offset: 0x1C0 (RO) */
+ __OM uint32_t rng_clk_enable;
+ /*!< Offset: 0x1C4 (WO) */
+ __IOM uint32_t rng_dma_enable;
+ /*!< Offset: 0x1C8 (RW) */
+ __IOM uint32_t rng_dma_src_mask;
+ /*!< Offset: 0x1CC (RW) */
+ __IOM uint32_t rng_dma_sram_addr;
+ /*!< Offset: 0x1D0 (RW) */
+ __IOM uint32_t rng_dma_samples_num;
+ /*!< Offset: 0x1D4 (RW) */
+ __IOM uint32_t rng_watchdog_val;
+ /*!< Offset: 0x1D8 (RW) */
+ __IM uint32_t rng_dma_status;
+ /*!< Offset: 0x1DC (RO) */
+ uint8_t _reserved_2[416];
+ /*!< Offset: 0x1E0-0x380 Reserved */
+ } rng;
-/* AHB registers */
-#define CC3XX_REG_AHB_AHBM_SINGLES (cc3xx_reg_t)(CC3XX_REG_BASE + 0xB00)
-#define CC3XX_REG_AHB_AHBM_HPROT (cc3xx_reg_t)(CC3XX_REG_BASE + 0xB04)
-#define CC3XX_REG_AHB_AHBM_HMASTLOCK (cc3xx_reg_t)(CC3XX_REG_BASE + 0xB08)
-#define CC3XX_REG_AHB_AHBM_HNONSEC (cc3xx_reg_t)(CC3XX_REG_BASE + 0xB0C)
+ /* ChaCha block */
+ __PACKED_STRUCT {
+ __IOM uint32_t chacha_control_reg;
+ /*!< offset: 0x380 (RW) */
+ __IM uint32_t chacha_version;
+ /*!< offset: 0x384 (RO) */
+ __OM uint32_t chacha_key[8];
+ /*!< offset: 0x388 (WO) */
+ __IOM uint32_t chacha_iv[2];
+ /*!< offset: 0x3a8 (RW) */
+ __IM uint32_t chacha_busy;
+ /*!< offset: 0x3b0 (RO) */
+ __IM uint32_t chacha_hw_flags;
+ /*!< offset: 0x3b4 (RO) */
+ __IOM uint32_t chacha_block_cnt_lsb;
+ /*!< offset: 0x3b8 (RW) */
+ __IOM uint32_t chacha_block_cnt_msb;
+ /*!< offset: 0x3bc (RW) */
+ __OM uint32_t chacha_sw_reset;
+ /*!< offset: 0x3c0 (WO) */
+ __IM uint32_t chacha_for_poly_key[8];
+ /*!< offset: 0x3c4 (RO) */
+ __IOM uint32_t chacha_byte_word_order_cntl_reg;
+ /*!< Offset: 0x3E4 (RW) */
+ __IM uint32_t chacha_debug_reg;
+ /*!< offset: 0x3E8 (RO) */
+ uint8_t _reserved_0[20];
+ /*!< Offset: 0x3EC-0x3FC Reserved */
+ } chacha;
-/* DIN registers */
-#define CC3XX_REG_DIN_DIN_BUFFER (cc3xx_reg_t)(CC3XX_REG_BASE + 0xC00)
-#define CC3XX_REG_DIN_DIN_MEM_DMA_BUSY (cc3xx_reg_t)(CC3XX_REG_BASE + 0xC20)
-#define CC3XX_REG_DIN_SRC_LLI_WORD0 (cc3xx_reg_t)(CC3XX_REG_BASE + 0xC28)
-#define CC3XX_REG_DIN_SRC_LLI_WORD1 (cc3xx_reg_t)(CC3XX_REG_BASE + 0xC2C)
-#define CC3XX_REG_DIN_SRAM_SRC_ADDR (cc3xx_reg_t)(CC3XX_REG_BASE + 0xC30)
-#define CC3XX_REG_DIN_DIN_SRAM_BYTES_LEN (cc3xx_reg_t)(CC3XX_REG_BASE + 0xC34)
-#define CC3XX_REG_DIN_DIN_SRAM_DMA_BUSY (cc3xx_reg_t)(CC3XX_REG_BASE + 0xC38)
-#define CC3XX_REG_DIN_DIN_SRAM_ENDIANNESS (cc3xx_reg_t)(CC3XX_REG_BASE + 0xC3C)
-#define CC3XX_REG_DIN_DIN_CPU_DATA_SIZE (cc3xx_reg_t)(CC3XX_REG_BASE + 0xC48)
-#define CC3XX_REG_DIN_FIFO_IN_EMPTY (cc3xx_reg_t)(CC3XX_REG_BASE + 0xC50)
-#define CC3XX_REG_DIN_DIN_FIFO_RST_PNTR (cc3xx_reg_t)(CC3XX_REG_BASE + 0xC58)
+ /* AES block */
+ __PACKED_STRUCT {
+ __OM uint32_t aes_key_0[8];
+ /*!< Offset: 0x400 (WO) */
+ __OM uint32_t aes_key_1[8];
+ /*!< Offset: 0x420 (WO) */
+ __IOM uint32_t aes_iv_0[4];
+ /*!< Offset: 0x440 (RW) */
+ __IOM uint32_t aes_iv_1[4];
+ /*!< Offset: 0x450 (RW) */
+ __IOM uint32_t aes_ctr_0[4];
+ /*!< Offset: 0x460 (RW) */
+ __IM uint32_t aes_busy;
+ /*!< Offset: 0x470 (RO) */
+ uint8_t _reserved_0[4];
+ /*!< Offset: 0x474 Reserved */
+ __OM uint32_t aes_sk;
+ /*!< Offset: 0x478 (WO) */
+ __OM uint32_t aes_cmac_init;
+ /*!< Offset: 0x47C (WO) */
+ uint8_t _reserved_1[52];
+ /*!< Offset: 0x480-0x4B0 Reserved */
+ __OM uint32_t aes_sk1;
+ /*!< Offset: 0x4B4 (WO) */
+ uint8_t _reserved_2[4];
+ /*!< Offset: 0x4B8 Reserved */
+ __IOM uint32_t aes_remaining_bytes;
+ /*!< Offset: 0x4BC (RW) */
+ __IOM uint32_t aes_control;
+ /*!< Offset: 0x4C0 (RW) */
+ uint8_t _reserved_3[4];
+ /*!< Offset: 0x4C4 Reserved */
+ __IM uint32_t aes_hw_flags;
+ /*!< Offset: 0x4C8 (RO) */
+ uint8_t _reserved_4[12];
+ /*!< Offset: 0x4CC-0x4D4 Reserved */
+ __PACKED_UNION {
+ __IOM uint32_t aes_rbg_seed;
+ /*!< Offset: 0x4D8 (RW) */
+ __IOM uint32_t aes_ctr_no_increment;
+ /*!< Offset: 0x4D8 (RW) */
+ };
+ uint8_t _reserved_5[20];
+ /*!< Offset: 0x4DC-0x4EC Reserved */
+ __IOM uint32_t aes_dfa_is_on;
+ /*!< Offset: 0x4F0 (RW) */
+ uint8_t _reserved_6[4];
+ /*!< Offset: 0x4F4 Reserved */
+ __IM uint32_t aes_dfa_err_status;
+ /*!< Offset: 0x4F8 (RO) */
+ __IM uint32_t aes_rbg_seeding_rdy;
+ /*!< Offset: 0x4FC (RO) */
+ uint8_t _reserved_7[36];
+ /*!< Offset: 0x500-0x520 Reserved */
+ __OM uint32_t aes_cmac_size0_kick;
+ /*!< Offset: 0x524 (WO) */
+ uint8_t _reserved_8[28];
+ /*!< Offset: 0x528-0x540 Reserved */
+ __IOM uint32_t aes_dummy_rounds_enable;
+ /*!< Offset: 0x544 (RW) */
+ uint8_t _reserved_9[248];
+ /*!< Offset: 0x548-0x63C Reserved */
+ } aes;
-/* DOUT registers */
-#define CC3XX_REG_DOUT_DOUT_BUFFER (cc3xx_reg_t)(CC3XX_REG_BASE + 0xD00)
-#define CC3XX_REG_DOUT_DOUT_MEM_DMA_BUSY (cc3xx_reg_t)(CC3XX_REG_BASE + 0xD20)
-#define CC3XX_REG_DOUT_DST_LLI_WORD0 (cc3xx_reg_t)(CC3XX_REG_BASE + 0xD28)
-#define CC3XX_REG_DOUT_DST_LLI_WORD1 (cc3xx_reg_t)(CC3XX_REG_BASE + 0xD2C)
-#define CC3XX_REG_DOUT_SRAM_DEST_ADDR (cc3xx_reg_t)(CC3XX_REG_BASE + 0xD30)
-#define CC3XX_REG_DOUT_DOUT_SRAM_BYTES_LEN (cc3xx_reg_t)(CC3XX_REG_BASE + 0xD34)
-#define CC3XX_REG_DOUT_DOUT_SRAM_DMA_BUSY (cc3xx_reg_t)(CC3XX_REG_BASE + 0xD38)
-#define CC3XX_REG_DOUT_DOUT_SRAM_ENDIANNESS (cc3xx_reg_t)(CC3XX_REG_BASE + 0xD3C)
-#define CC3XX_REG_DOUT_READ_ALIGN_LAST (cc3xx_reg_t)(CC3XX_REG_BASE + 0xD44)
-#define CC3XX_REG_DOUT_DOUT_FIFO_EMPTY (cc3xx_reg_t)(CC3XX_REG_BASE + 0xD50)
+ /* Hash block */
+ __PACKED_STRUCT {
+ __IOM uint32_t hash_h[9];
+ /*!< Offset: 0x640 (RW) */
+ uint8_t _reserved_0[32];
+ /*!< Offset: 0x664-0x680 Reserved */
+ __OM uint32_t auto_hw_padding;
+ /*!< Offset: 0x684 (WO) */
+ __IOM uint32_t hash_xor_din;
+ /*!< Offset: 0x688 (RW) */
+ uint8_t _reserved_1[8];
+ /*!< Offset: 0x68C-0x690 Reserved */
+ __OM uint32_t load_init_state;
+ /*!< Offset: 0x694 (WO) */
+ uint8_t _reserved_2[12];
+ /*!< Offset: 0x698-0x6A0 Reserved */
+ __OM uint32_t hash_sel_aes_mac;
+ /*!< Offset: 0x6A4 (WO) */
+ uint8_t _reserved_3[264];
+ /*!< Offset: 0x6A8-0x6FC Reserved */
+ __IM uint32_t hash_version;
+ /*!< Offset: 0x7B0 (RO) */
+ uint8_t _reserved_4[12];
+ /*!< Offset: 0x7B4-0x7BC Reserved */
+ __IOM uint32_t hash_control;
+ /*!< Offset: 0x7C0 (RW) */
+ __IOM uint32_t hash_pad_en;
+ /*!< Offset: 0x7C4 (RW) */
+ __IOM uint32_t hash_pad_cfg;
+ /*!< Offset: 0x7C8 (RW) */
+ __IOM uint32_t hash_cur_len[2];
+ /*!< Offset: 0x7CC (RW) */
+ uint8_t _reserved_5[8];
+ /*!< Offset: 0x7D0-0x7D8 Reserved */
+ __IM uint32_t hash_param;
+ /*!< Offset: 0x7DC (RO) */
+ uint8_t _reserved_6[4];
+ /*!< Offset: 0x7E0 Reserved */
+ __OM uint32_t hash_aes_sw_reset;
+ /*!< Offset: 0x7E4 (WO) */
+ __IOM uint32_t hash_endianess;
+ /*!< Offset: 0x7E8 (RW) */
+ uint8_t _reserved_7[36];
+ /*!< Offset: 0x7E4-0x80C Reserved */
+ } hash;
-/* AO registers */
-#define CC3XX_REG_AO_HOST_DCU_EN0 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1E00)
-#define CC3XX_REG_AO_HOST_DCU_EN1 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1E04)
-#define CC3XX_REG_AO_HOST_DCU_EN2 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1E08)
-#define CC3XX_REG_AO_HOST_DCU_EN3 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1E0C)
-#define CC3XX_REG_AO_HOST_DCU_LOCK0 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1E10)
-#define CC3XX_REG_AO_HOST_DCU_LOCK1 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1E14)
-#define CC3XX_REG_AO_HOST_DCU_LOCK2 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1E18)
-#define CC3XX_REG_AO_HOST_DCU_LOCK3 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1E1C)
-#define CC3XX_REG_AO_AO_ICV_DCU_RESTRICTION_MASK0 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1E20)
-#define CC3XX_REG_AO_AO_ICV_DCU_RESTRICTION_MASK1 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1E24)
-#define CC3XX_REG_AO_AO_ICV_DCU_RESTRICTION_MASK2 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1E28)
-#define CC3XX_REG_AO_AO_ICV_DCU_RESTRICTION_MASK3 (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1E2C)
-#define CC3XX_REG_AO_AO_CC_SEC_DEBUG_RESET (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1E30)
-#define CC3XX_REG_AO_HOST_AO_LOCK_BITS (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1E34)
-#define CC3XX_REG_AO_AO_APB_FILTERING (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1E38)
-#define CC3XX_REG_AO_AO_CC_GPPC (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1E3C)
-#define CC3XX_REG_AO_HOST_RGF_CC_SW_RST (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1E40)
+ /* Misc Block */
+ __PACKED_STRUCT {
+ __IOM uint32_t aes_clk_enable;
+ /*!< Offset: 0x810 (RW) */
+ uint8_t _reserved_0[4];
+ /*!< Offset: 0x814 Reserved */
+ __IOM uint32_t hash_clk_enable;
+ /*!< Offset: 0x818 (RW) */
+ __IOM uint32_t pka_clk_enable;
+ /*!< Offset: 0x81C (RW) */
+ __IOM uint32_t dma_clk_enable;
+ /*!< Offset: 0x820 (RW) */
+ __IM uint32_t clk_status;
+ /*!< Offset: 0x824 (RO) */
+ uint8_t _reserved_1[48];
+ /*!< Offset: 0x828-0x854 Reserved */
+ __OM uint32_t chacha_clk_enable;
+ /*!< Offset: 0x858 (WO) */
+ uint8_t _reserved_2[164];
+ /*!< Offset: 0x85C-0x8FC Reserved */
+ } misc;
-/* NVM registers */
-#define CC3XX_REG_NVM_AIB_FUSE_PROG_COMPLETED (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1F04U)
-#define CC3XX_REG_NVM_NVM_DEBUG_STATUS (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1F08U)
-#define CC3XX_REG_NVM_LCS_IS_VALID (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1F0CU)
-#define CC3XX_REG_NVM_NVM_IS_IDLE (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1F10U)
-#define CC3XX_REG_NVM_LCS_REG (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1F14U)
-#define CC3XX_REG_NVM_HOST_SHADOW_KDR_REG (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1F18U)
-#define CC3XX_REG_NVM_HOST_SHADOW_KCP_REG (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1F1CU)
-#define CC3XX_REG_NVM_HOST_SHADOW_KCE_REG (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1F20U)
-#define CC3XX_REG_NVM_HOST_SHADOW_KPICV_REG (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1F24U)
-#define CC3XX_REG_NVM_HOST_SHADOW_KCEICV_REG (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1F28U)
-#define CC3XX_REG_NVM_OTP_ADDR_WIDTH_DEF (cc3xx_reg_t)(CC3XX_REG_BASE + 0x1F2CU)
+ /* CC_CTL Block */
+ __PACKED_STRUCT {
+ __OM uint32_t crypto_ctl;
+ /*!< Offset: 0x900 (WO) */
+ uint8_t _reserved_0[12];
+ /*!< Offset: 0x904-0x90C Reserved */
+ __IM uint32_t crypto_busy;
+ /*!< Offset: 0x910 (RO) */
+ uint8_t _reserved_1[8];
+ /*!< Offset: 0x914-0x918 Reserved */
+ __IM uint32_t hash_busy;
+ /*!< Offset: 0x91C (RO) */
+ uint8_t _reserved_2[16];
+ /*!< Offset: 0x920-0x92C Reserved */
+ __IOM uint32_t context_id;
+ /*!< Offset: 0x930 (RW) */
+ uint8_t _reserved_3[44];
+ /*!< Offset: 0x85C-0x8FC Reserved */
+ } cc_ctl;
+
+ /* GHash block */
+ __PACKED_STRUCT {
+ __OM uint32_t ghash_subkey_0[4];
+ /*!< Offset: 0x960 (WO) */
+ __IOM uint32_t ghash_iv_0[4];
+ /*!< Offset: 0x970 (RW) */
+ __IM uint32_t ghash_busy;
+ /*!< Offset: 0x980 (RO) */
+ __OM uint32_t ghash_init;
+ /*!< Offset: 0x984 (WO) */
+ uint8_t _reserved_0[120];
+ /*!< Offset: 0x988-0x9FC Reserved */
+ } ghash;
+
+ /* Host_RGF block */
+ __PACKED_STRUCT {
+ __IM uint32_t host_rgf_irr;
+ /*!< Offset: 0xA00 (RO) */
+ __IOM uint32_t host_rgf_imr;
+ /*!< Offset: 0xA04 (RW) */
+ __OM uint32_t host_rgf_icr;
+ /*!< Offset: 0xA08 (WO) */
+ __IOM uint32_t host_rgf_endian;
+ /*!< Offset: 0xA0C (RW) */
+ uint8_t _reserved_0[20];
+ /*!< Offset: 0xA10-0xA20 Reserved */
+ __IM uint32_t host_rgf_signature;
+ /*!< Offset: 0xA24 (RO) */
+ __IM uint32_t host_boot;
+ /*!< Offset: 0xA28 (RO) */
+ uint8_t _reserved_1[12];
+ /*!< Offset: 0xA2C-0xA34 Reserved */
+ __IOM uint32_t host_cryptokey_sel;
+ /*!< Offset: 0xA38 (RW) */
+ uint8_t _reserved_2[60];
+ /*!< Offset: 0xA3C-0xA78 Reserved */
+ __IOM uint32_t host_core_clk_gating_enable;
+ /*!< Offset: 0xA78 (RW) */
+ __IM uint32_t host_cc_is_idle;
+ /*!< Offset: 0xA7C (RO) */
+ __IOM uint32_t host_powerdown;
+ /*!< Offset: 0xA80 (RW) */
+ __IM uint32_t host_remove_ghash_engine;
+ /*!< Offset: 0xA84 (RO) */
+ __IM uint32_t host_remove_chacha_engine;
+ /*!< Offset: 0xA88 (RO) */
+ __IOM uint32_t host_sf_dynamic_cntl;
+ /*!< Offset: 0xA8C (RW) */
+ __IM uint32_t host_sf_ready;
+ /*!< Offset: 0xA90 (RO) */
+ uint8_t _reserved_3[108];
+ /*!< Offset: 0xA94-0xAFC Reserved */
+ } host_rgf;
+
+ /* AHB block */
+ __PACKED_STRUCT {
+ __IOM uint32_t ahbm_singles;
+ /*!< Offset: 0xB00 (RW) */
+ __IOM uint32_t ahbm_hprot;
+ /*!< Offset: 0xB04 (RW) */
+ __IOM uint32_t ahbm_hmastlock;
+ /*!< Offset: 0xB08 (RW) */
+ __IOM uint32_t ahbm_hnonsec;
+ /*!< Offset: 0xB0C (RW) */
+ uint8_t _reserved_0[240];
+ /*!< Offset: 0xB10-0xBF4 Reserved */
+ } ahb;
+
+ /* DIN block */
+ __PACKED_STRUCT {
+ __OM uint32_t din_buffer;
+ /*!< Offset: 0xC00 (WO) */
+ uint8_t _reserved_0[28];
+ /*!< Offset: 0xC04-0xC1C Reserved */
+ __IM uint32_t din_mem_dma_busy;
+ /*!< Offset: 0xC20 (RO) */
+ uint8_t _reserved_1[4];
+ /*!< Offset: 0xC24 Reserved */
+ __OM uint32_t src_lli_word0;
+ /*!< Offset: 0xC28 (WO) */
+ __OM uint32_t src_lli_word1;
+ /*!< Offset: 0xC2C (WO) */
+ __IOM uint32_t sram_src_addr;
+ /*!< Offset: 0xC30 (RW) */
+ __IOM uint32_t din_sram_bytes_len;
+ /*!< Offset: 0xC34 (RW) */
+ __IM uint32_t din_sram_dma_busy;
+ /*!< Offset: 0xC38 (RO) */
+ uint8_t _reserved_2[12];
+ /*!< Offset: 0xC3C-0xC44 Reserved */
+ __OM uint32_t din_cpu_data_size;
+ /*!< Offset: 0xC48 (WO) */
+ uint8_t _reserved_3[4];
+ /*!< Offset: 0xC4C Reserved */
+ __IM uint32_t fifo_in_empty;
+ /*!< Offset: 0xC50 (RO) */
+ uint8_t _reserved_4[4];
+ /*!< Offset: 0xC54 Reserved */
+ __OM uint32_t din_fifo_rst_pntr;
+ /*!< Offset: 0xC58 (WO) */
+ uint8_t _reserved_5[164];
+ /*!< Offset: 0xC5C-0xCFC Reserved */
+ } din;
+
+ /* DOUT block */
+ __PACKED_STRUCT {
+ __IM uint32_t dout_buffer;
+ /*!< Offset: 0xD00 (RO) */
+ uint8_t _reserved_0[28];
+ /*!< Offset: 0xD04-0xD1C Reserved */
+ __IM uint32_t dout_mem_dma_busy;
+ /*!< Offset: 0xD20 (RO) */
+ uint8_t _reserved_1[4];
+ /*!< Offset: 0xD24 Reserved */
+ __OM uint32_t dst_lli_word0;
+ /*!< Offset: 0xD28 (WO) */
+ __IOM uint32_t dst_lli_word1;
+ /*!< Offset: 0xD2C (RW) */
+ __IOM uint32_t sram_dest_addr;
+ /*!< Offset: 0xD30 (RW) */
+ __IOM uint32_t dout_sram_bytes_len;
+ /*!< Offset: 0xD34 (RW) */
+ __IM uint32_t dout_sram_dma_busy;
+ /*!< Offset: 0xD38 (RO) */
+ uint8_t _reserved_2[8];
+ /*!< Offset: 0xD3C-0xD40 Reserved */
+ __OM uint32_t read_align_last;
+ /*!< Offset: 0xD44 (WO) */
+ uint8_t _reserved_3[8];
+ /*!< Offset: 0xD48-0xD4C Reserved */
+ __IM uint32_t dout_fifo_empty;
+ /*!< Offset: 0xD50 (RO) */
+ uint8_t _reserved_4[172];
+ /*!< Offset: 0xD54-0xDFC Reserved */
+ } dout;
+
+ /* AO block */
+ __PACKED_STRUCT {
+ __IOM uint32_t host_dcu_en[4];
+ /*!< Offset: 0xE00 (RW) */
+ __IOM uint32_t host_dcu_lock[4];
+ /*!< Offset: 0xE10 (RW) */
+ __IM uint32_t ao_icv_dcu_restriction_mask[4];
+ /*!< Offset: 0xE20 (RO) */
+ __IM uint32_t ao_cc_sec_debug_reset;
+ /*!< Offset: 0xE30 (RO) */
+ __IOM uint32_t host_ao_lock_bits;
+ /*!< Offset: 0xE34 (RW) */
+ __IOM uint32_t ao_apb_filtering;
+ /*!< Offset: 0xE38 (RW) */
+ __IM uint32_t ao_cc_gppc;
+ /*!< Offset: 0xE3C (RO) */
+ __OM uint32_t host_rgf_cc_sw_rst;
+ /*!< Offset: 0xE40 (WO) */
+ __IM uint32_t dcu_debug_bits[4];
+ /*!< Offset: 0xE44 (RO) */
+ __IM uint32_t ao_permanent_disable_mask[4];
+ /*!< Offset: 0xE54 (RO) */
+ uint8_t _reserved_0[156];
+ /*!< Offset: 0xE58-0xEFC Reserved */
+ } ao;
+
+ /* Host_SRAM block */
+ __PACKED_STRUCT {
+ __IOM uint32_t sram_data;
+ /*!< Offset: 0x0F00 (RW) */
+ __OM uint32_t sram_addr;
+ /*!< Offset: 0x0F04 (WO) */
+ __IM uint32_t sram_data_ready;
+ /*!< Offset: 0x0F08 (RO) */
+ uint8_t _reserved_0[196];
+ /*!< Offset: 0xF08-0xFCC Reserved */
+ } host_sram;
+
+ /* ID_Registers block */
+ __PACKED_STRUCT {
+ __IM uint32_t peripheral_id_4;
+ /*!< Offset: 0xFD0 (RO) */
+ __IM uint32_t pidreserved0;
+ /*!< Offset: 0xFD4 (RO) */
+ __IM uint32_t pidreserved1;
+ /*!< Offset: 0xFD8 (RO) */
+ __IM uint32_t pidreserved2;
+ /*!< Offset: 0xFDC (RO) */
+ __IM uint32_t peripheral_id_0;
+ /*!< Offset: 0xFE0 (RO) */
+ __IM uint32_t peripheral_id_1;
+ /*!< Offset: 0xFE4 (RO) */
+ __IM uint32_t peripheral_id_2;
+ /*!< Offset: 0xFE8 (RO) */
+ __IM uint32_t peripheral_id_3;
+ /*!< Offset: 0xFEC (RO) */
+ __IM uint32_t component_id_0;
+ /*!< Offset: 0xFF0 (RO) */
+ __IM uint32_t component_id_1;
+ /*!< Offset: 0xFF4 (RO) */
+ uint8_t _reserved_0[3852];
+ /*!< Offset: 0xFF8-0x1F00 Reserved */
+ } id;
+
+ /* NVM block */
+ __PACKED_STRUCT {
+ __IM uint32_t aib_fuse_prog_completed;
+ /*!< Offset: 0x1F04 (RO) */
+ __IM uint32_t nvm_debug_status;
+ /*!< Offset: 0x1F08 (RO) */
+ __IM uint32_t lcs_is_valid;
+ /*!< Offset: 0x1F0C (RO) */
+ __IM uint32_t nvm_is_idle;
+ /*!< Offset: 0x1F10 (RO) */
+ __IM uint32_t lcs_reg;
+ /*!< Offset: 0x1F14 (RO) */
+ __OM uint32_t host_shadow_kdr_reg;
+ /*!< Offset: 0x1F18 (WO) */
+ __OM uint32_t host_shadow_kcp_reg;
+ /*!< Offset: 0x1F1C (WO) */
+ __OM uint32_t host_shadow_kce_reg;
+ /*!< Offset: 0x1F20 (WO) */
+ __OM uint32_t host_shadow_kpicv_reg;
+ /*!< Offset: 0x1F24 (WO) */
+ __OM uint32_t host_shadow_kceicv_reg;
+ /*!< Offset: 0x1F28 (WO) */
+ __IM uint32_t otp_addr_width_def;
+ /*!< Offset: 0x1F2C (RO) */
+ __IM uint32_t gp_param;
+ /*!< Offset: 0x1F30 (RO) */
+ uint8_t _reserved_0[204];
+ /*!< Offset: 0x1F34-0x1FFC Reserved */
+ } nvm;
+
+ __PACKED_STRUCT {
+ __IOM uint32_t huk[8];
+ __IOM uint32_t icv_provisioning_key[4];
+ __IOM uint32_t icv_code_encryption_key[4];
+ __IOM uint32_t icv_programmed_flags[1];
+ __PACKED_UNION {
+ __IOM uint32_t rot_public_key[8];
+ __PACKED_STRUCT {
+ __IOM uint32_t icv_rot_public_key[4];
+ __IOM uint32_t oem_rot_public_key[4];
+ };
+ };
+ __IOM uint32_t oem_provisioning_secret[4];
+ __IOM uint32_t oem_code_encryption_key[4];
+ __IOM uint32_t oem_programmed_flags[1];
+ __PACKED_UNION {
+ __IOM uint32_t nv_counter[5];
+ __PACKED_STRUCT {
+ __IOM uint32_t icv_nv_counter[2];
+ __IOM uint32_t oem_nv_counter[3];
+ };
+ };
+ __IOM uint32_t general_purpose_configuration_flags[1];
+ __IOM uint32_t dcu_debug_lock_mask[4];
+ __IOM uint32_t general_purpose_code_data[];
+ } otp;
+};
#ifdef __cplusplus
}
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_rng.c b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_rng.c
index 96c5383..cd93a75 100644
--- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_rng.c
+++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_rng.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -8,19 +8,20 @@
#include "cc3xx_rng.h"
#include "cc3xx_error.h"
-#include "cc3xx_reg_defs.h"
+#include "cc3xx_dev.h"
#include <stdint.h>
#include <stddef.h>
#include <string.h>
-cc3xx_err_t cc3xx_rng_init()
+cc3xx_err_t cc3xx_rng_init(void)
{
+
/* Enable clock */
- *CC3XX_REG_RNG_RNG_CLK_ENABLE = 0x1U;
+ P_CC3XX->rng.rng_clk_enable = 0x1U;
/* reset trng */
- *CC3XX_REG_RNG_RNG_SW_RESET = 0x1U;
+ P_CC3XX->rng.rng_sw_reset = 0x1U;
/* Apparently there's no way to tell that the reset has finished, so just do
* these things repeatedly until they succeed (and hence the reset has
@@ -28,41 +29,42 @@
*/
do {
/* Enable clock */
- *CC3XX_REG_RNG_RNG_CLK_ENABLE = 0x1U;
+ P_CC3XX->rng.rng_clk_enable = 0x1U;
/* Set subsampling ratio */
- *CC3XX_REG_RNG_SAMPLE_CNT1 = CC3XX_RNG_SUBSAMPLING_RATE;
+ P_CC3XX->rng.sample_cnt1 = CC3XX_CONFIG_LOWLEVEL_RNG_SUBSAMPLING_RATE;
- } while (*CC3XX_REG_RNG_SAMPLE_CNT1 != CC3XX_RNG_SUBSAMPLING_RATE);
+ } while (P_CC3XX->rng.sample_cnt1 != CC3XX_CONFIG_LOWLEVEL_RNG_SUBSAMPLING_RATE);
/* Temporarily disable the random source */
- *CC3XX_REG_RNG_RND_SOURCE_ENABLE = 0x0U;
+ P_CC3XX->rng.rnd_source_enable = 0x0U;
/* Clear the interrupts */
- *CC3XX_REG_RNG_RNG_ICR = 0x3FU;
+ P_CC3XX->rng.rng_icr = 0x3FU;
/* Mask all interrupts except EHR_VALID */
- *CC3XX_REG_RNG_RNG_IMR = 0x3EU;
+ P_CC3XX->rng.rng_imr = 0x3EU;
/* Select the oscillator ring (And set SOP_SEL to 0x1 as is mandatory) */
- *CC3XX_REG_RNG_TRNG_CONFIG = CC3XX_RNG_RING_OSCILLATOR_ID | (0x1U << 2);
+ P_CC3XX->rng.trng_config = CC3XX_CONFIG_LOWLEVEL_RNG_RING_OSCILLATOR_ID | (0x1U << 2);
/* Set debug control register to no bypasses */
- *CC3XX_REG_RNG_TRNG_DEBUG_CONTROL = 0x0U;
+ P_CC3XX->rng.trng_debug_control = 0x0U;
/* Enable the random source */
- *CC3XX_REG_RNG_RND_SOURCE_ENABLE = 0x1U;
+ P_CC3XX->rng.rnd_source_enable = 0x1U;
return CC3XX_ERR_SUCCESS;
}
-cc3xx_err_t cc3xx_rng_finish()
+cc3xx_err_t cc3xx_rng_finish(void)
{
+
/* Disable the random source */
- *CC3XX_REG_RNG_RND_SOURCE_ENABLE = 0x0U;
+ P_CC3XX->rng.rnd_source_enable = 0x0U;
/* Disable clock */
- *CC3XX_REG_RNG_RNG_CLK_ENABLE = 0x0U;
+ P_CC3XX->rng.rng_clk_enable = 0x0U;
return CC3XX_ERR_SUCCESS;
}
@@ -70,6 +72,7 @@
cc3xx_err_t cc3xx_rng_get_random(uint8_t* buf, size_t length)
{
uint32_t attempt_count = 0;
+ uint32_t idx;
/* The cc312 generates 192 bits of entropy, which is used as 24 bytes */
for (int byte_am = 0; byte_am < length; byte_am += 24) {
@@ -81,39 +84,36 @@
* failed.
*/
do {
- if (*CC3XX_REG_RNG_RNG_ISR & 0xEU) {
+ if (P_CC3XX->rng.rng_isr & 0xEU) {
/* At least one test has failed - the buffer contents aren't
* random.
*/
/* Reset EHR registers */
- *CC3XX_REG_RNG_RST_BITS_COUNTER = 0x1U;
+ P_CC3XX->rng.rst_bits_counter = 0x1U;
/* Clear the interrupt bits to restart generator */
- *CC3XX_REG_RNG_RNG_ICR = 0x3FU;
+ P_CC3XX->rng.rng_icr = 0x3FU;
attempt_count++;
}
- } while ((! (*CC3XX_REG_RNG_RNG_ISR & 0x1U))
- && attempt_count < CC3XX_RNG_MAX_ATTEMPTS);
+ } while ((! (P_CC3XX->rng.rng_isr & 0x1U))
+ && attempt_count < CC3XX_CONFIG_LOWLEVEL_RNG_MAX_ATTEMPTS);
- if (attempt_count == CC3XX_RNG_MAX_ATTEMPTS) {
+ if (attempt_count == CC3XX_CONFIG_LOWLEVEL_RNG_MAX_ATTEMPTS) {
cc3xx_rng_finish();
return CC3XX_ERR_GENERIC_ERROR;
}
- tmp_buf[0] = *CC3XX_REG_RNG_EHR_DATA_0;
- tmp_buf[1] = *CC3XX_REG_RNG_EHR_DATA_1;
- tmp_buf[2] = *CC3XX_REG_RNG_EHR_DATA_2;
- tmp_buf[3] = *CC3XX_REG_RNG_EHR_DATA_3;
- tmp_buf[4] = *CC3XX_REG_RNG_EHR_DATA_4;
- tmp_buf[5] = *CC3XX_REG_RNG_EHR_DATA_5;
+ for (idx = 0; idx < 6; idx++) {
+ tmp_buf[idx] = P_CC3XX->rng.ehr_data[idx];
+ }
/* Reset EHR register */
- *CC3XX_REG_RNG_RST_BITS_COUNTER = 0x1U;
+ P_CC3XX->rng.rst_bits_counter = 0x1U;
/* Clear the interrupt bits to restart generator */
- *CC3XX_REG_RNG_RNG_ICR = 0xFFFFFFFF;
+ P_CC3XX->rng.rng_icr = 0xFFFFFFFF;
copy_size = length > byte_am + 24 ? 24 : (length - byte_am);
memcpy(buf + byte_am, (uint8_t*)tmp_buf, copy_size);
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_rng.h b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_rng.h
index ff06d1b..a5e3113 100644
--- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_rng.h
+++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_rng.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -9,7 +9,6 @@
#define CC3XX_RNG_H
#include "cc3xx_error.h"
-#include "cc3xx_rng_defs.h"
#include <stdint.h>
#include <stddef.h>
@@ -18,9 +17,9 @@
extern "C" {
#endif
-cc3xx_err_t cc3xx_rng_init();
+cc3xx_err_t cc3xx_rng_init(void);
cc3xx_err_t cc3xx_rng_get_random(uint8_t* buf, size_t length);
-cc3xx_err_t cc3xx_rng_finish();
+cc3xx_err_t cc3xx_rng_finish(void);
#ifdef __cplusplus
}
diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_rng_defs.h b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_rng_defs.h
deleted file mode 100644
index 1dc1b23..0000000
--- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_rng_defs.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#ifndef CC3XX_RNG_DEFS_H
-#define CC3XX_RNG_DEFS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* The number of times the TRNG will be re-read when it fails a statical test
- * before an error is returned.
- */
-#ifndef CC3XX_RNG_MAX_ATTEMPTS
-#define CC3XX_RNG_MAX_ATTEMPTS 16
-#endif /* CC3XX_RNG_MAX_ATTEMPTS */
-
-/* This is the number of cycles between consecutive samples of the oscillator
- * output. It needs to be set to a _reasonably_ large number, though It's
- * unclear exactly what sort of number is reasonable. In general, if the
- * statistical tests keep failing then increase it, if the RNG is too slow then
- * decrease it. A sensible default is set here, and has worked correctly with a
- * variety of cc3xx implementations.
- */
-#ifndef CC3XX_RNG_SUBSAMPLING_RATE
-#define CC3XX_RNG_SUBSAMPLING_RATE 0x1337
-#endif /* !CC_RNG_SUBSAMPLING_RATE */
-
-/* Between 0 and 3 inclusive. 0 should be the fastest oscillator ring */
-#ifndef CC3XX_RNG_RING_OSCILLATOR_ID
-#define CC3XX_RNG_RING_OSCILLATOR_ID 0
-#endif /* !CC_RNG_RING_OSCILLATOR_ID */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* CC3XX_RNG_DEFS_H */
diff --git a/platform/ext/accelerator/cc312/cc312_rom_crypto_hw.c b/platform/ext/accelerator/cc312/cc312_rom_crypto_hw.c
index 60405b9..625905a 100644
--- a/platform/ext/accelerator/cc312/cc312_rom_crypto_hw.c
+++ b/platform/ext/accelerator/cc312/cc312_rom_crypto_hw.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -9,7 +9,8 @@
#include <stdint.h>
#include <stddef.h>
#include "region_defs.h"
-#include "cc3xx_init.h"
+#include "cc3xx_drv.h"
+#include "device_definition.h"
int crypto_hw_accelerator_init(void)
{
diff --git a/platform/ext/target/arm/rss/common/partition/platform_base_address.h b/platform/ext/target/arm/rss/common/partition/platform_base_address.h
index e86ff23..ed3da48 100644
--- a/platform/ext/target/arm/rss/common/partition/platform_base_address.h
+++ b/platform/ext/target/arm/rss/common/partition/platform_base_address.h
@@ -99,6 +99,7 @@
#define SIC_BASE_S 0x50140000 /* SIC Secure base address */
#define ATU_BASE_S 0x50150000 /* ATU Secure base address */
#define MPC_SIC_BASE_S 0x50151000 /* SIC Memory Protection Controller Secure base address */
+#define CC3XX_BASE_S 0x50154000 /* CryptoCell CC3XX Secure base address */
#define SYSCNTR_CNTRL_BASE_S 0x5015A000 /* System Counter Control Secure base address */
#define SYSCNTR_READ_BASE_S 0x5015B000 /* System Counter Read Secure base address */
#define MHU0_SENDER_BASE_S 0x50160000 /* Combined MHU 0 Sender Secure base address */