Platform: stm32l5xx: Set all NVIC interrupt target to NS
The STM32L5xx does not support NVIC in secure at the moment, just align
with other existing platforms that target all NVIC interrupt to NS.
Change-Id: I32c56ba36a88656df51969352876c45453ebcfee
Signed-off-by: Karl Zhang <karl.zhang@arm.com>
diff --git a/platform/ext/target/stm/stm32l5xx/boards/target_cfg.h b/platform/ext/target/stm/stm32l5xx/boards/target_cfg.h
index 07be8db..033753b 100644
--- a/platform/ext/target/stm/stm32l5xx/boards/target_cfg.h
+++ b/platform/ext/target/stm/stm32l5xx/boards/target_cfg.h
@@ -100,5 +100,9 @@
*/
enum tfm_plat_err_t enable_fault_handlers(void);
+/**
+ * \brief Set NVIC interrupt target state to NS.
+ */
+enum tfm_plat_err_t nvic_interrupt_target_state_cfg();
#endif /* __STM32L5XX_CFG_H__ */
diff --git a/platform/ext/target/stm/stm32l5xx/secure/spm_hal.c b/platform/ext/target/stm/stm32l5xx/secure/spm_hal.c
index 965f0fc..b0b3e6a 100644
--- a/platform/ext/target/stm/stm32l5xx/secure/spm_hal.c
+++ b/platform/ext/target/stm/stm32l5xx/secure/spm_hal.c
@@ -327,8 +327,7 @@
enum tfm_plat_err_t tfm_spm_hal_nvic_interrupt_target_state_cfg(void)
{
-/* return nvic_interrupt_target_state_cfg();*/
- return TFM_PLAT_ERR_SUCCESS;
+ return nvic_interrupt_target_state_cfg();
}
enum tfm_plat_err_t tfm_spm_hal_nvic_interrupt_enable(void)
diff --git a/platform/ext/target/stm/stm32l5xx/secure/target_cfg.c b/platform/ext/target/stm/stm32l5xx/secure/target_cfg.c
index efd039a..1f0ad61 100644
--- a/platform/ext/target/stm/stm32l5xx/secure/target_cfg.c
+++ b/platform/ext/target/stm/stm32l5xx/secure/target_cfg.c
@@ -73,13 +73,14 @@
}
/*----------------- NVIC interrupt target state to NS configuration ----------*/
-void nvic_interrupt_target_state_cfg()
+enum tfm_plat_err_t nvic_interrupt_target_state_cfg()
{
/* Target every interrupt to NS; unimplemented interrupts will be WI */
for (uint8_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++)
{
NVIC->ITNS[i] = 0xFFFFFFFF;
}
+ return TFM_PLAT_ERR_SUCCESS;
}
void system_reset_cfg(void)
{