Platform: Refactor the linker files
Remove the limitation between level 1 and other levels.
For TFM_LVL == 1, it moves the data of partition to its
own section. This does not affect other isolation levels.
Change-Id: Ie7e5dbf1b26255acb71de76574f1e201530423dc
Signed-off-by: Summer Qin <summer.qin@arm.com>
diff --git a/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct b/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct
index 6ecf8ce..e6cc33c 100644
--- a/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct
+++ b/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct
@@ -28,35 +28,6 @@
.ANY (+RO)
}
-#if TFM_LVL == 1
-
- /* Shared area between BL2 and runtime to exchange data */
- TFM_SHARED_DATA S_DATA_START ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
- }
-
- /* MSP */
- ARM_LIB_STACK_MSP S_DATA_START ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE {
- }
-
- /* PSP */
- ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE {
- }
-
- ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE {
- }
-
- ER_TFM_DATA +0 {
- .ANY (+RW +ZI)
- }
-
- TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x2000 {
- }
-
- TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
- }
-
-#else /* TFM_LVL == 1 */
-
/**** Unprivileged Secure code start here */
TFM_UNPRIV_CODE +0 ALIGN 32 {
tfm_spm_services.o (+RO)
@@ -187,6 +158,11 @@
.ANY (+RW +ZI)
}
+#if TFM_LVL == 1
+ TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x2000 {
+ }
+#endif /* TFM_LVL == 1 */
+
TFM_UNPRIV_DATA +0 ALIGN 32 {
tfm_spm_services.o (+RW +ZI)
dummy_crypto_keys.o (+RW +ZI)
@@ -318,8 +294,6 @@
TFM_APP_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
}
-#endif /* TFM_LVL == 1 */
-
/* This empty, zero long execution region is here to mark the limit address
* of the last execution region that is allocated in SRAM.
*/
diff --git a/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct.template b/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct.template
index 54880c8..c5a1581 100644
--- a/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct.template
+++ b/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct.template
@@ -28,35 +28,6 @@
.ANY (+RO)
}
-#if TFM_LVL == 1
-
- /* Shared area between BL2 and runtime to exchange data */
- TFM_SHARED_DATA S_DATA_START ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
- }
-
- /* MSP */
- ARM_LIB_STACK_MSP S_DATA_START ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE {
- }
-
- /* PSP */
- ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE {
- }
-
- ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE {
- }
-
- ER_TFM_DATA +0 {
- .ANY (+RW +ZI)
- }
-
- TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x2000 {
- }
-
- TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
- }
-
-#else /* TFM_LVL == 1 */
-
/**** Unprivileged Secure code start here */
TFM_UNPRIV_CODE +0 ALIGN 32 {
tfm_spm_services.o (+RO)
@@ -168,6 +139,11 @@
.ANY (+RW +ZI)
}
+#if TFM_LVL == 1
+ TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x2000 {
+ }
+#endif /* TFM_LVL == 1 */
+
TFM_UNPRIV_DATA +0 ALIGN 32 {
tfm_spm_services.o (+RW +ZI)
dummy_crypto_keys.o (+RW +ZI)
@@ -264,8 +240,6 @@
TFM_APP_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
}
-#endif /* TFM_LVL == 1 */
-
/* This empty, zero long execution region is here to mark the limit address
* of the last execution region that is allocated in SRAM.
*/
diff --git a/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld b/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld
index ebcdf0c..1b9bcdc 100644
--- a/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld
+++ b/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld
@@ -58,38 +58,17 @@
__vectors_end__ = .;
} > FLASH
-#if TFM_LVL == 1
.copy.table : ALIGN(4)
{
__copy_table_start__ = .;
LONG (LOADADDR(.TFM_DATA))
LONG (ADDR(.TFM_DATA))
LONG (SIZEOF(.TFM_DATA))
- __copy_table_end__ = .;
- } > FLASH
-
- .zero.table : ALIGN(4)
- {
- __zero_table_start__ = .;
- LONG (ADDR(.TFM_BSS))
- LONG (SIZEOF(.TFM_BSS))
- LONG (ADDR(.TFM_SECURE_STACK))
- LONG (SIZEOF(.TFM_SECURE_STACK))
- LONG (ADDR(.TFM_UNPRIV_SCRATCH))
- LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))
- __zero_table_end__ = .;
- } > FLASH
-
-#else /* TFM_LVL == 1 */
- .copy.table : ALIGN(4)
- {
- __copy_table_start__ = .;
- LONG (LOADADDR(.TFM_DATA))
- LONG (ADDR(.TFM_DATA))
- LONG (SIZEOF(.TFM_DATA))
+#if TFM_LVL != 1
LONG (LOADADDR(.TFM_UNPRIV_DATA))
LONG (ADDR(.TFM_UNPRIV_DATA))
LONG (SIZEOF(.TFM_UNPRIV_DATA))
+#endif /* TFM_LVL != 1 */
LONG (LOADADDR(.TFM_SP_STORAGE_DATA))
LONG (ADDR(.TFM_SP_STORAGE_DATA))
LONG (SIZEOF(.TFM_SP_STORAGE_DATA))
@@ -138,8 +117,13 @@
__zero_table_start__ = .;
LONG (ADDR(.TFM_BSS))
LONG (SIZEOF(.TFM_BSS))
+#if TFM_LVL == 1
+ LONG (ADDR(.TFM_SECURE_STACK))
+ LONG (SIZEOF(.TFM_SECURE_STACK))
+#else /* TFM_LVL == 1 */
LONG (ADDR(.TFM_UNPRIV_BSS))
LONG (SIZEOF(.TFM_UNPRIV_BSS))
+#endif /* TFM_LVL == 1 */
LONG (ADDR(.TFM_SP_STORAGE_BSS))
LONG (SIZEOF(.TFM_SP_STORAGE_BSS))
LONG (ADDR(.TFM_SP_STORAGE_STACK))
@@ -195,6 +179,7 @@
__zero_table_end__ = .;
} > FLASH
+#if TFM_LVL != 1
.TFM_UNPRIV_CODE : ALIGN(32)
{
*libc_nano*:*(.text*)
@@ -218,6 +203,7 @@
} > FLASH
Image$$TFM_UNPRIV_CODE$$RO$$Base = ADDR(.TFM_UNPRIV_CODE);
Image$$TFM_UNPRIV_CODE$$RO$$Limit = ADDR(.TFM_UNPRIV_CODE) + SIZEOF(.TFM_UNPRIV_CODE);
+#endif /* TFM_LVL != 1 */
/**** PSA RoT RO part (CODE + RODATA) start here */
Image$$TFM_PSA_CODE_START$$Base = .;
@@ -375,6 +361,7 @@
/**** APPLICATION RoT RO part (CODE + RODATA) end here */
Image$$TFM_APP_CODE_END$$Base = .;
+#if TFM_LVL != 1
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
@@ -387,7 +374,7 @@
} > FLASH
__exidx_end = .;
-#endif /* TFM_LVL == 1 */
+#endif /* TFM_LVL != 1 */
.ER_TFM_CODE : ALIGN(4)
{
@@ -447,13 +434,6 @@
Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);
Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);
- .TFM_UNPRIV_SCRATCH : ALIGN(32)
- {
- . += 0x400;
- } > RAM
- Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);
- Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);
-
.heap : ALIGN(8)
{
__end__ = .;
@@ -495,6 +475,7 @@
} > RAM
Image$$TFM_UNPRIV_DATA$$ZI$$Base = ADDR(.TFM_UNPRIV_BSS);
Image$$TFM_UNPRIV_DATA$$ZI$$Limit = ADDR(.TFM_UNPRIV_BSS) + SIZEOF(.TFM_UNPRIV_BSS);
+#endif /* TFM_LVL == 1 */
.TFM_UNPRIV_SCRATCH : ALIGN(32)
{
@@ -786,6 +767,7 @@
/**** APPLICATION RoT DATA end here */
Image$$TFM_APP_RW_STACK_END$$Base = .;
+#if TFM_LVL != 1
.TFM_SP_SECURE_TEST_PARTITION_DATA : ALIGN(32)
{
*libc_nano*:*(.data*)
@@ -814,7 +796,7 @@
. = ALIGN(32);
} > RAM
-#endif /* TFM_LVL == 1 */
+#endif /* TFM_LVL != 1 */
.TFM_DATA : ALIGN(4)
{
diff --git a/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld.template b/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld.template
index 725ff89..9c7f754 100644
--- a/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld.template
+++ b/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld.template
@@ -58,38 +58,17 @@
__vectors_end__ = .;
} > FLASH
-#if TFM_LVL == 1
.copy.table : ALIGN(4)
{
__copy_table_start__ = .;
LONG (LOADADDR(.TFM_DATA))
LONG (ADDR(.TFM_DATA))
LONG (SIZEOF(.TFM_DATA))
- __copy_table_end__ = .;
- } > FLASH
-
- .zero.table : ALIGN(4)
- {
- __zero_table_start__ = .;
- LONG (ADDR(.TFM_BSS))
- LONG (SIZEOF(.TFM_BSS))
- LONG (ADDR(.TFM_SECURE_STACK))
- LONG (SIZEOF(.TFM_SECURE_STACK))
- LONG (ADDR(.TFM_UNPRIV_SCRATCH))
- LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))
- __zero_table_end__ = .;
- } > FLASH
-
-#else /* TFM_LVL == 1 */
- .copy.table : ALIGN(4)
- {
- __copy_table_start__ = .;
- LONG (LOADADDR(.TFM_DATA))
- LONG (ADDR(.TFM_DATA))
- LONG (SIZEOF(.TFM_DATA))
+#if TFM_LVL != 1
LONG (LOADADDR(.TFM_UNPRIV_DATA))
LONG (ADDR(.TFM_UNPRIV_DATA))
LONG (SIZEOF(.TFM_UNPRIV_DATA))
+#endif /* TFM_LVL != 1 */
{% for manifest in manifests %}
{% if manifest.attr.conditional %}
#ifdef {{manifest.attr.conditional}}
@@ -109,8 +88,13 @@
__zero_table_start__ = .;
LONG (ADDR(.TFM_BSS))
LONG (SIZEOF(.TFM_BSS))
+#if TFM_LVL == 1
+ LONG (ADDR(.TFM_SECURE_STACK))
+ LONG (SIZEOF(.TFM_SECURE_STACK))
+#else /* TFM_LVL == 1 */
LONG (ADDR(.TFM_UNPRIV_BSS))
LONG (SIZEOF(.TFM_UNPRIV_BSS))
+#endif /* TFM_LVL == 1 */
{% for manifest in manifests %}
{% if manifest.attr.conditional %}
#ifdef {{manifest.attr.conditional}}
@@ -128,6 +112,7 @@
__zero_table_end__ = .;
} > FLASH
+#if TFM_LVL != 1
.TFM_UNPRIV_CODE : ALIGN(32)
{
*libc_nano*:*(.text*)
@@ -151,6 +136,7 @@
} > FLASH
Image$$TFM_UNPRIV_CODE$$RO$$Base = ADDR(.TFM_UNPRIV_CODE);
Image$$TFM_UNPRIV_CODE$$RO$$Limit = ADDR(.TFM_UNPRIV_CODE) + SIZEOF(.TFM_UNPRIV_CODE);
+#endif /* TFM_LVL != 1 */
/**** PSA RoT RO part (CODE + RODATA) start here */
Image$$TFM_PSA_CODE_START$$Base = .;
@@ -228,6 +214,7 @@
/**** APPLICATION RoT RO part (CODE + RODATA) end here */
Image$$TFM_APP_CODE_END$$Base = .;
+#if TFM_LVL != 1
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
@@ -240,7 +227,7 @@
} > FLASH
__exidx_end = .;
-#endif /* TFM_LVL == 1 */
+#endif /* TFM_LVL != 1 */
.ER_TFM_CODE : ALIGN(4)
{
@@ -300,13 +287,6 @@
Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);
Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);
- .TFM_UNPRIV_SCRATCH : ALIGN(32)
- {
- . += 0x400;
- } > RAM
- Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);
- Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);
-
.heap : ALIGN(8)
{
__end__ = .;
@@ -348,6 +328,7 @@
} > RAM
Image$$TFM_UNPRIV_DATA$$ZI$$Base = ADDR(.TFM_UNPRIV_BSS);
Image$$TFM_UNPRIV_DATA$$ZI$$Limit = ADDR(.TFM_UNPRIV_BSS) + SIZEOF(.TFM_UNPRIV_BSS);
+#endif /* TFM_LVL == 1 */
.TFM_UNPRIV_SCRATCH : ALIGN(32)
{
@@ -474,6 +455,7 @@
/**** APPLICATION RoT DATA end here */
Image$$TFM_APP_RW_STACK_END$$Base = .;
+#if TFM_LVL != 1
.TFM_SP_SECURE_TEST_PARTITION_DATA : ALIGN(32)
{
*libc_nano*:*(.data*)
@@ -502,7 +484,7 @@
. = ALIGN(32);
} > RAM
-#endif /* TFM_LVL == 1 */
+#endif /* TFM_LVL != 1 */
.TFM_DATA : ALIGN(4)
{
diff --git a/platform/ext/target/mps2/an521/armclang/mps2_an521_s.sct b/platform/ext/target/mps2/an521/armclang/mps2_an521_s.sct
index 2e03975..f293fcc 100644
--- a/platform/ext/target/mps2/an521/armclang/mps2_an521_s.sct
+++ b/platform/ext/target/mps2/an521/armclang/mps2_an521_s.sct
@@ -28,35 +28,6 @@
.ANY (+RO)
}
-#if TFM_LVL == 1
-
- /* Shared area between BL2 and runtime to exchange data */
- TFM_SHARED_DATA S_DATA_START ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
- }
-
- /* MSP */
- ARM_LIB_STACK_MSP S_DATA_START ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE {
- }
-
- /* PSP */
- ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE {
- }
-
- ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE {
- }
-
- ER_TFM_DATA +0 {
- .ANY (+RW +ZI)
- }
-
- TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x2000 {
- }
-
- TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
- }
-
-#else /* TFM_LVL == 1 */
-
/**** Unprivileged Secure code start here */
TFM_UNPRIV_CODE +0 ALIGN 32 {
tfm_spm_services.o (+RO)
@@ -185,6 +156,11 @@
.ANY (+RW +ZI)
}
+#if TFM_LVL == 1
+ TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x2000 {
+ }
+#endif /* TFM_LVL == 1 */
+
TFM_UNPRIV_DATA +0 ALIGN 32 {
tfm_spm_services.o (+RW +ZI)
dummy_crypto_keys.o (+RW +ZI)
@@ -313,7 +289,6 @@
*/
TFM_APP_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
}
-#endif /* TFM_LVL == 1 */
/* This empty, zero long execution region is here to mark the limit address
* of the last execution region that is allocated in SRAM.
diff --git a/platform/ext/target/mps2/an521/armclang/mps2_an521_s.sct.template b/platform/ext/target/mps2/an521/armclang/mps2_an521_s.sct.template
index a9bac1d..9a1e462 100644
--- a/platform/ext/target/mps2/an521/armclang/mps2_an521_s.sct.template
+++ b/platform/ext/target/mps2/an521/armclang/mps2_an521_s.sct.template
@@ -28,35 +28,6 @@
.ANY (+RO)
}
-#if TFM_LVL == 1
-
- /* Shared area between BL2 and runtime to exchange data */
- TFM_SHARED_DATA S_DATA_START ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
- }
-
- /* MSP */
- ARM_LIB_STACK_MSP S_DATA_START ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE {
- }
-
- /* PSP */
- ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE {
- }
-
- ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE {
- }
-
- ER_TFM_DATA +0 {
- .ANY (+RW +ZI)
- }
-
- TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x2000 {
- }
-
- TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
- }
-
-#else /* TFM_LVL == 1 */
-
/**** Unprivileged Secure code start here */
TFM_UNPRIV_CODE +0 ALIGN 32 {
tfm_spm_services.o (+RO)
@@ -166,6 +137,11 @@
.ANY (+RW +ZI)
}
+#if TFM_LVL == 1
+ TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x2000 {
+ }
+#endif /* TFM_LVL == 1 */
+
TFM_UNPRIV_DATA +0 ALIGN 32 {
tfm_spm_services.o (+RW +ZI)
dummy_crypto_keys.o (+RW +ZI)
@@ -259,7 +235,6 @@
*/
TFM_APP_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
}
-#endif /* TFM_LVL == 1 */
/* This empty, zero long execution region is here to mark the limit address
* of the last execution region that is allocated in SRAM.
diff --git a/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld b/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld
index a2efe1b..3fcef8f 100644
--- a/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld
+++ b/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld
@@ -58,38 +58,17 @@
__vectors_end__ = .;
} > FLASH
-#if TFM_LVL == 1
.copy.table : ALIGN(4)
{
__copy_table_start__ = .;
LONG (LOADADDR(.TFM_DATA))
LONG (ADDR(.TFM_DATA))
LONG (SIZEOF(.TFM_DATA))
- __copy_table_end__ = .;
- } > FLASH
-
- .zero.table : ALIGN(4)
- {
- __zero_table_start__ = .;
- LONG (ADDR(.TFM_BSS))
- LONG (SIZEOF(.TFM_BSS))
- LONG (ADDR(.TFM_SECURE_STACK))
- LONG (SIZEOF(.TFM_SECURE_STACK))
- LONG (ADDR(.TFM_UNPRIV_SCRATCH))
- LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))
- __zero_table_end__ = .;
- } > FLASH
-
-#else /* TFM_LVL == 1 */
- .copy.table : ALIGN(4)
- {
- __copy_table_start__ = .;
- LONG (LOADADDR(.TFM_DATA))
- LONG (ADDR(.TFM_DATA))
- LONG (SIZEOF(.TFM_DATA))
+#if TFM_LVL != 1
LONG (LOADADDR(.TFM_UNPRIV_DATA))
LONG (ADDR(.TFM_UNPRIV_DATA))
LONG (SIZEOF(.TFM_UNPRIV_DATA))
+#endif /* TFM_LVL != 1 */
LONG (LOADADDR(.TFM_SP_STORAGE_DATA))
LONG (ADDR(.TFM_SP_STORAGE_DATA))
LONG (SIZEOF(.TFM_SP_STORAGE_DATA))
@@ -138,8 +117,13 @@
__zero_table_start__ = .;
LONG (ADDR(.TFM_BSS))
LONG (SIZEOF(.TFM_BSS))
+#if TFM_LVL == 1
+ LONG (ADDR(.TFM_SECURE_STACK))
+ LONG (SIZEOF(.TFM_SECURE_STACK))
+#else /* TFM_LVL == 1 */
LONG (ADDR(.TFM_UNPRIV_BSS))
LONG (SIZEOF(.TFM_UNPRIV_BSS))
+#endif /* TFM_LVL == 1 */
LONG (ADDR(.TFM_SP_STORAGE_BSS))
LONG (SIZEOF(.TFM_SP_STORAGE_BSS))
LONG (ADDR(.TFM_SP_STORAGE_STACK))
@@ -195,6 +179,7 @@
__zero_table_end__ = .;
} > FLASH
+#if TFM_LVL != 1
.TFM_UNPRIV_CODE : ALIGN(32)
{
*libc_nano*:*(.text*)
@@ -218,6 +203,7 @@
} > FLASH
Image$$TFM_UNPRIV_CODE$$RO$$Base = ADDR(.TFM_UNPRIV_CODE);
Image$$TFM_UNPRIV_CODE$$RO$$Limit = ADDR(.TFM_UNPRIV_CODE) + SIZEOF(.TFM_UNPRIV_CODE);
+#endif /* TFM_LVL != 1 */
/**** PSA RoT RO part (CODE + RODATA) start here */
Image$$TFM_PSA_CODE_START$$Base = .;
@@ -375,6 +361,7 @@
/**** APPLICATION RoT RO part (CODE + RODATA) end here */
Image$$TFM_APP_CODE_END$$Base = .;
+#if TFM_LVL != 1
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
@@ -387,7 +374,7 @@
} > FLASH
__exidx_end = .;
-#endif /* TFM_LVL == 1 */
+#endif /* TFM_LVL != 1 */
.ER_TFM_CODE : ALIGN(4)
{
@@ -447,13 +434,6 @@
Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);
Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);
- .TFM_UNPRIV_SCRATCH : ALIGN(32)
- {
- . += 0x400;
- } > RAM
- Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);
- Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);
-
.heap : ALIGN(8)
{
__end__ = .;
@@ -495,6 +475,7 @@
} > RAM
Image$$TFM_UNPRIV_DATA$$ZI$$Base = ADDR(.TFM_UNPRIV_BSS);
Image$$TFM_UNPRIV_DATA$$ZI$$Limit = ADDR(.TFM_UNPRIV_BSS) + SIZEOF(.TFM_UNPRIV_BSS);
+#endif /* TFM_LVL == 1 */
.TFM_UNPRIV_SCRATCH : ALIGN(32)
{
@@ -786,6 +767,7 @@
/**** APPLICATION RoT DATA end here */
Image$$TFM_APP_RW_STACK_END$$Base = .;
+#if TFM_LVL != 1
.TFM_SP_SECURE_TEST_PARTITION_DATA : ALIGN(32)
{
*libc_nano*:*(.data*)
@@ -814,7 +796,7 @@
. = ALIGN(32);
} > RAM
-#endif /* TFM_LVL == 1 */
+#endif /* TFM_LVL != 1 */
.TFM_DATA : ALIGN(4)
{
diff --git a/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld.template b/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld.template
index 70d8c97..91c74de 100644
--- a/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld.template
+++ b/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld.template
@@ -58,38 +58,17 @@
__vectors_end__ = .;
} > FLASH
-#if TFM_LVL == 1
.copy.table : ALIGN(4)
{
__copy_table_start__ = .;
LONG (LOADADDR(.TFM_DATA))
LONG (ADDR(.TFM_DATA))
LONG (SIZEOF(.TFM_DATA))
- __copy_table_end__ = .;
- } > FLASH
-
- .zero.table : ALIGN(4)
- {
- __zero_table_start__ = .;
- LONG (ADDR(.TFM_BSS))
- LONG (SIZEOF(.TFM_BSS))
- LONG (ADDR(.TFM_SECURE_STACK))
- LONG (SIZEOF(.TFM_SECURE_STACK))
- LONG (ADDR(.TFM_UNPRIV_SCRATCH))
- LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))
- __zero_table_end__ = .;
- } > FLASH
-
-#else /* TFM_LVL == 1 */
- .copy.table : ALIGN(4)
- {
- __copy_table_start__ = .;
- LONG (LOADADDR(.TFM_DATA))
- LONG (ADDR(.TFM_DATA))
- LONG (SIZEOF(.TFM_DATA))
+#if TFM_LVL != 1
LONG (LOADADDR(.TFM_UNPRIV_DATA))
LONG (ADDR(.TFM_UNPRIV_DATA))
LONG (SIZEOF(.TFM_UNPRIV_DATA))
+#endif /* TFM_LVL != 1 */
{% for manifest in manifests %}
{% if manifest.attr.conditional %}
#ifdef {{manifest.attr.conditional}}
@@ -109,8 +88,13 @@
__zero_table_start__ = .;
LONG (ADDR(.TFM_BSS))
LONG (SIZEOF(.TFM_BSS))
+#if TFM_LVL == 1
+ LONG (ADDR(.TFM_SECURE_STACK))
+ LONG (SIZEOF(.TFM_SECURE_STACK))
+#else /* TFM_LVL == 1 */
LONG (ADDR(.TFM_UNPRIV_BSS))
LONG (SIZEOF(.TFM_UNPRIV_BSS))
+#endif /* TFM_LVL == 1 */
{% for manifest in manifests %}
{% if manifest.attr.conditional %}
#ifdef {{manifest.attr.conditional}}
@@ -128,6 +112,7 @@
__zero_table_end__ = .;
} > FLASH
+#if TFM_LVL != 1
.TFM_UNPRIV_CODE : ALIGN(32)
{
*libc_nano*:*(.text*)
@@ -151,6 +136,7 @@
} > FLASH
Image$$TFM_UNPRIV_CODE$$RO$$Base = ADDR(.TFM_UNPRIV_CODE);
Image$$TFM_UNPRIV_CODE$$RO$$Limit = ADDR(.TFM_UNPRIV_CODE) + SIZEOF(.TFM_UNPRIV_CODE);
+#endif /* TFM_LVL != 1 */
/**** PSA RoT RO part (CODE + RODATA) start here */
Image$$TFM_PSA_CODE_START$$Base = .;
@@ -228,6 +214,7 @@
/**** APPLICATION RoT RO part (CODE + RODATA) end here */
Image$$TFM_APP_CODE_END$$Base = .;
+#if TFM_LVL != 1
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
@@ -240,7 +227,7 @@
} > FLASH
__exidx_end = .;
-#endif /* TFM_LVL == 1 */
+#endif /* TFM_LVL != 1 */
.ER_TFM_CODE : ALIGN(4)
{
@@ -300,13 +287,6 @@
Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);
Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);
- .TFM_UNPRIV_SCRATCH : ALIGN(32)
- {
- . += 0x400;
- } > RAM
- Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);
- Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);
-
.heap : ALIGN(8)
{
__end__ = .;
@@ -348,6 +328,7 @@
} > RAM
Image$$TFM_UNPRIV_DATA$$ZI$$Base = ADDR(.TFM_UNPRIV_BSS);
Image$$TFM_UNPRIV_DATA$$ZI$$Limit = ADDR(.TFM_UNPRIV_BSS) + SIZEOF(.TFM_UNPRIV_BSS);
+#endif /* TFM_LVL == 1 */
.TFM_UNPRIV_SCRATCH : ALIGN(32)
{
@@ -474,6 +455,7 @@
/**** APPLICATION RoT DATA end here */
Image$$TFM_APP_RW_STACK_END$$Base = .;
+#if TFM_LVL != 1
.TFM_SP_SECURE_TEST_PARTITION_DATA : ALIGN(32)
{
*libc_nano*:*(.data*)
@@ -502,7 +484,7 @@
. = ALIGN(32);
} > RAM
-#endif /* TFM_LVL == 1 */
+#endif /* TFM_LVL != 1 */
.TFM_DATA : ALIGN(4)
{
diff --git a/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct b/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct
index a464efc..2aed64c 100644
--- a/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct
+++ b/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct
@@ -28,35 +28,6 @@
.ANY (+RO)
}
-#if TFM_LVL == 1
-
- /* Shared area between BL2 and runtime to exchange data */
- TFM_SHARED_DATA S_DATA_START ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
- }
-
- /* MSP */
- ARM_LIB_STACK_MSP S_DATA_START ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE {
- }
-
- /* PSP */
- ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE {
- }
-
- ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE {
- }
-
- ER_TFM_DATA +0 {
- .ANY (+RW +ZI)
- }
-
- TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x2000 {
- }
-
- TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
- }
-
-#else /* TFM_LVL == 1 */
-
/**** Unprivileged Secure code start here */
TFM_UNPRIV_CODE +0 ALIGN 32 {
tfm_spm_services.o (+RO)
@@ -185,6 +156,11 @@
.ANY (+RW +ZI)
}
+#if TFM_LVL == 1
+ TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x2000 {
+ }
+#endif /* TFM_LVL == 1 */
+
TFM_UNPRIV_DATA +0 ALIGN 32 {
tfm_spm_services.o (+RW +ZI)
dummy_crypto_keys.o (+RW +ZI)
@@ -313,7 +289,6 @@
*/
TFM_APP_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
}
-#endif /* TFM_LVL == 1 */
/* This empty, zero long execution region is here to mark the limit address
* of the last execution region that is allocated in SRAM.
diff --git a/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct.template b/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct.template
index c1b11c3..cb846f4 100644
--- a/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct.template
+++ b/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct.template
@@ -28,35 +28,6 @@
.ANY (+RO)
}
-#if TFM_LVL == 1
-
- /* Shared area between BL2 and runtime to exchange data */
- TFM_SHARED_DATA S_DATA_START ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
- }
-
- /* MSP */
- ARM_LIB_STACK_MSP S_DATA_START ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE {
- }
-
- /* PSP */
- ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE {
- }
-
- ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE {
- }
-
- ER_TFM_DATA +0 {
- .ANY (+RW +ZI)
- }
-
- TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x2000 {
- }
-
- TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
- }
-
-#else /* TFM_LVL == 1 */
-
/**** Unprivileged Secure code start here */
TFM_UNPRIV_CODE +0 ALIGN 32 {
tfm_spm_services.o (+RO)
@@ -166,6 +137,11 @@
.ANY (+RW +ZI)
}
+#if TFM_LVL == 1
+ TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x2000 {
+ }
+#endif /* TFM_LVL == 1 */
+
TFM_UNPRIV_DATA +0 ALIGN 32 {
tfm_spm_services.o (+RW +ZI)
dummy_crypto_keys.o (+RW +ZI)
@@ -259,7 +235,6 @@
*/
TFM_APP_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
}
-#endif /* TFM_LVL == 1 */
/* This empty, zero long execution region is here to mark the limit address
* of the last execution region that is allocated in SRAM.
diff --git a/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld
index c10d94b..a879345 100644
--- a/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld
+++ b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld
@@ -58,38 +58,17 @@
__vectors_end__ = .;
} > FLASH
-#if TFM_LVL == 1
.copy.table : ALIGN(4)
{
__copy_table_start__ = .;
LONG (LOADADDR(.TFM_DATA))
LONG (ADDR(.TFM_DATA))
LONG (SIZEOF(.TFM_DATA))
- __copy_table_end__ = .;
- } > FLASH
-
- .zero.table : ALIGN(4)
- {
- __zero_table_start__ = .;
- LONG (ADDR(.TFM_BSS))
- LONG (SIZEOF(.TFM_BSS))
- LONG (ADDR(.TFM_SECURE_STACK))
- LONG (SIZEOF(.TFM_SECURE_STACK))
- LONG (ADDR(.TFM_UNPRIV_SCRATCH))
- LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))
- __zero_table_end__ = .;
- } > FLASH
-
-#else /* TFM_LVL == 1 */
- .copy.table : ALIGN(4)
- {
- __copy_table_start__ = .;
- LONG (LOADADDR(.TFM_DATA))
- LONG (ADDR(.TFM_DATA))
- LONG (SIZEOF(.TFM_DATA))
+#if TFM_LVL != 1
LONG (LOADADDR(.TFM_UNPRIV_DATA))
LONG (ADDR(.TFM_UNPRIV_DATA))
LONG (SIZEOF(.TFM_UNPRIV_DATA))
+#endif
LONG (LOADADDR(.TFM_SP_STORAGE_DATA))
LONG (ADDR(.TFM_SP_STORAGE_DATA))
LONG (SIZEOF(.TFM_SP_STORAGE_DATA))
@@ -138,8 +117,13 @@
__zero_table_start__ = .;
LONG (ADDR(.TFM_BSS))
LONG (SIZEOF(.TFM_BSS))
+#if TFM_LVL == 1
+ LONG (ADDR(.TFM_SECURE_STACK))
+ LONG (SIZEOF(.TFM_SECURE_STACK))
+#else /* TFM_LVL == 1 */
LONG (ADDR(.TFM_UNPRIV_BSS))
LONG (SIZEOF(.TFM_UNPRIV_BSS))
+#endif /* TFM_LVL == 1 */
LONG (ADDR(.TFM_SP_STORAGE_BSS))
LONG (SIZEOF(.TFM_SP_STORAGE_BSS))
LONG (ADDR(.TFM_SP_STORAGE_STACK))
@@ -195,6 +179,7 @@
__zero_table_end__ = .;
} > FLASH
+#if TFM_LVL != 1
.TFM_UNPRIV_CODE : ALIGN(32)
{
*libc_nano*:*(.text*)
@@ -218,6 +203,7 @@
} > FLASH
Image$$TFM_UNPRIV_CODE$$RO$$Base = ADDR(.TFM_UNPRIV_CODE);
Image$$TFM_UNPRIV_CODE$$RO$$Limit = ADDR(.TFM_UNPRIV_CODE) + SIZEOF(.TFM_UNPRIV_CODE);
+#endif /* TFM_LVL != 1 */
.TFM_SP_STORAGE : ALIGN(32)
{
@@ -364,6 +350,7 @@
#endif /* TFM_PSA_API */
+#if TFM_LVL != 1
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
@@ -376,7 +363,7 @@
} > FLASH
__exidx_end = .;
-#endif /* TFM_LVL == 1 */
+#endif /* TFM_LVL != 1 */
.ER_TFM_CODE : ALIGN(4)
{
@@ -428,7 +415,6 @@
Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack);
#if TFM_LVL == 1
-
.TFM_SECURE_STACK : ALIGN(128)
{
. += 0x2000;
@@ -436,13 +422,6 @@
Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);
Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);
- .TFM_UNPRIV_SCRATCH : ALIGN(32)
- {
- . += 0x400;
- } > RAM
- Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);
- Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);
-
.heap : ALIGN(8)
{
__end__ = .;
@@ -484,6 +463,7 @@
} > RAM
Image$$TFM_UNPRIV_DATA$$ZI$$Base = ADDR(.TFM_UNPRIV_BSS);
Image$$TFM_UNPRIV_DATA$$ZI$$Limit = ADDR(.TFM_UNPRIV_BSS) + SIZEOF(.TFM_UNPRIV_BSS);
+#endif /* TFM_LVL == 1 */
.TFM_UNPRIV_SCRATCH : ALIGN(32)
{
@@ -764,6 +744,7 @@
#endif /* TFM_PSA_API */
+#if TFM_LVL != 1
.TFM_SP_SECURE_TEST_PARTITION_DATA : ALIGN(32)
{
*libc_nano*:*(.data*)
@@ -792,7 +773,7 @@
. = ALIGN(32);
} > RAM
-#endif /* TFM_LVL == 1 */
+#endif /* TFM_LVL != 1 */
.TFM_DATA : ALIGN(4)
{
diff --git a/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template
index 268894f..af74396 100644
--- a/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template
+++ b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template
@@ -58,38 +58,17 @@
__vectors_end__ = .;
} > FLASH
-#if TFM_LVL == 1
.copy.table : ALIGN(4)
{
__copy_table_start__ = .;
LONG (LOADADDR(.TFM_DATA))
LONG (ADDR(.TFM_DATA))
LONG (SIZEOF(.TFM_DATA))
- __copy_table_end__ = .;
- } > FLASH
-
- .zero.table : ALIGN(4)
- {
- __zero_table_start__ = .;
- LONG (ADDR(.TFM_BSS))
- LONG (SIZEOF(.TFM_BSS))
- LONG (ADDR(.TFM_SECURE_STACK))
- LONG (SIZEOF(.TFM_SECURE_STACK))
- LONG (ADDR(.TFM_UNPRIV_SCRATCH))
- LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))
- __zero_table_end__ = .;
- } > FLASH
-
-#else /* TFM_LVL == 1 */
- .copy.table : ALIGN(4)
- {
- __copy_table_start__ = .;
- LONG (LOADADDR(.TFM_DATA))
- LONG (ADDR(.TFM_DATA))
- LONG (SIZEOF(.TFM_DATA))
+#if TFM_LVL != 1
LONG (LOADADDR(.TFM_UNPRIV_DATA))
LONG (ADDR(.TFM_UNPRIV_DATA))
LONG (SIZEOF(.TFM_UNPRIV_DATA))
+#endif
{% for manifest in manifests %}
{% if manifest.attr.conditional %}
#ifdef {{manifest.attr.conditional}}
@@ -109,8 +88,13 @@
__zero_table_start__ = .;
LONG (ADDR(.TFM_BSS))
LONG (SIZEOF(.TFM_BSS))
+#if TFM_LVL == 1
+ LONG (ADDR(.TFM_SECURE_STACK))
+ LONG (SIZEOF(.TFM_SECURE_STACK))
+#else /* TFM_LVL == 1 */
LONG (ADDR(.TFM_UNPRIV_BSS))
LONG (SIZEOF(.TFM_UNPRIV_BSS))
+#endif /* TFM_LVL == 1 */
{% for manifest in manifests %}
{% if manifest.attr.conditional %}
#ifdef {{manifest.attr.conditional}}
@@ -128,6 +112,7 @@
__zero_table_end__ = .;
} > FLASH
+#if TFM_LVL != 1
.TFM_UNPRIV_CODE : ALIGN(32)
{
*libc_nano*:*(.text*)
@@ -151,6 +136,7 @@
} > FLASH
Image$$TFM_UNPRIV_CODE$$RO$$Base = ADDR(.TFM_UNPRIV_CODE);
Image$$TFM_UNPRIV_CODE$$RO$$Limit = ADDR(.TFM_UNPRIV_CODE) + SIZEOF(.TFM_UNPRIV_CODE);
+#endif /* TFM_LVL != 1 */
{% for manifest in manifests %}
{% if manifest.attr.conditional %}
@@ -183,6 +169,7 @@
{% endif %}
{% endfor %}
+#if TFM_LVL != 1
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
@@ -195,7 +182,7 @@
} > FLASH
__exidx_end = .;
-#endif /* TFM_LVL == 1 */
+#endif /* TFM_LVL != 1 */
.ER_TFM_CODE : ALIGN(4)
{
@@ -247,7 +234,6 @@
Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack);
#if TFM_LVL == 1
-
.TFM_SECURE_STACK : ALIGN(128)
{
. += 0x2000;
@@ -255,13 +241,6 @@
Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);
Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);
- .TFM_UNPRIV_SCRATCH : ALIGN(32)
- {
- . += 0x400;
- } > RAM
- Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);
- Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);
-
.heap : ALIGN(8)
{
__end__ = .;
@@ -303,6 +282,7 @@
} > RAM
Image$$TFM_UNPRIV_DATA$$ZI$$Base = ADDR(.TFM_UNPRIV_BSS);
Image$$TFM_UNPRIV_DATA$$ZI$$Limit = ADDR(.TFM_UNPRIV_BSS) + SIZEOF(.TFM_UNPRIV_BSS);
+#endif /* TFM_LVL == 1 */
.TFM_UNPRIV_SCRATCH : ALIGN(32)
{
@@ -363,6 +343,7 @@
{% endif %}
{% endfor %}
+#if TFM_LVL != 1
.TFM_SP_SECURE_TEST_PARTITION_DATA : ALIGN(32)
{
*libc_nano*:*(.data*)
@@ -391,7 +372,7 @@
. = ALIGN(32);
} > RAM
-#endif /* TFM_LVL == 1 */
+#endif /* TFM_LVL != 1 */
.TFM_DATA : ALIGN(4)
{
diff --git a/platform/ext/target/musca_b1/Device/Source/armclang/musca_s.sct b/platform/ext/target/musca_b1/Device/Source/armclang/musca_s.sct
index 757f1b4..d2da9e7 100644
--- a/platform/ext/target/musca_b1/Device/Source/armclang/musca_s.sct
+++ b/platform/ext/target/musca_b1/Device/Source/armclang/musca_s.sct
@@ -28,35 +28,6 @@
.ANY (+RO)
}
-#if TFM_LVL == 1
-
- /* Shared area between BL2 and runtime to exchange data */
- TFM_SHARED_DATA S_DATA_START ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
- }
-
- /* MSP */
- ARM_LIB_STACK_MSP S_DATA_START ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE {
- }
-
- /* PSP */
- ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE {
- }
-
- ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE {
- }
-
- ER_TFM_DATA +0 {
- .ANY (+RW +ZI)
- }
-
- TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x2000 {
- }
-
- TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
- }
-
-#else /* TFM_LVL == 1 */
-
/**** Unprivileged Secure code start here */
TFM_UNPRIV_CODE +0 ALIGN 32 {
tfm_spm_services.o (+RO)
@@ -185,6 +156,11 @@
.ANY (+RW +ZI)
}
+#if TFM_LVL == 1
+ TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x2000 {
+ }
+#endif /* TFM_LVL == 1 */
+
TFM_UNPRIV_DATA +0 ALIGN 32 {
tfm_spm_services.o (+RW +ZI)
dummy_crypto_keys.o (+RW +ZI)
@@ -313,7 +289,6 @@
*/
TFM_APP_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
}
-#endif /* TFM_LVL == 1 */
/* This empty, zero long execution region is here to mark the limit address
* of the last execution region that is allocated in SRAM.
diff --git a/platform/ext/target/musca_b1/Device/Source/armclang/musca_s.sct.template b/platform/ext/target/musca_b1/Device/Source/armclang/musca_s.sct.template
index 522cdea..56a5be2 100644
--- a/platform/ext/target/musca_b1/Device/Source/armclang/musca_s.sct.template
+++ b/platform/ext/target/musca_b1/Device/Source/armclang/musca_s.sct.template
@@ -28,35 +28,6 @@
.ANY (+RO)
}
-#if TFM_LVL == 1
-
- /* Shared area between BL2 and runtime to exchange data */
- TFM_SHARED_DATA S_DATA_START ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
- }
-
- /* MSP */
- ARM_LIB_STACK_MSP S_DATA_START ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE {
- }
-
- /* PSP */
- ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE {
- }
-
- ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE {
- }
-
- ER_TFM_DATA +0 {
- .ANY (+RW +ZI)
- }
-
- TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x2000 {
- }
-
- TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
- }
-
-#else /* TFM_LVL == 1 */
-
/**** Unprivileged Secure code start here */
TFM_UNPRIV_CODE +0 ALIGN 32 {
tfm_spm_services.o (+RO)
@@ -166,6 +137,11 @@
.ANY (+RW +ZI)
}
+#if TFM_LVL == 1
+ TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x2000 {
+ }
+#endif /* TFM_LVL == 1 */
+
TFM_UNPRIV_DATA +0 ALIGN 32 {
tfm_spm_services.o (+RW +ZI)
dummy_crypto_keys.o (+RW +ZI)
@@ -259,7 +235,6 @@
*/
TFM_APP_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
}
-#endif /* TFM_LVL == 1 */
/* This empty, zero long execution region is here to mark the limit address
* of the last execution region that is allocated in SRAM.
diff --git a/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld b/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld
index fae7086..e4cb9c1 100644
--- a/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld
+++ b/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld
@@ -58,38 +58,17 @@
__vectors_end__ = .;
} > FLASH
-#if TFM_LVL == 1
.copy.table : ALIGN(4)
{
__copy_table_start__ = .;
LONG (LOADADDR(.TFM_DATA))
LONG (ADDR(.TFM_DATA))
LONG (SIZEOF(.TFM_DATA))
- __copy_table_end__ = .;
- } > FLASH
-
- .zero.table : ALIGN(4)
- {
- __zero_table_start__ = .;
- LONG (ADDR(.TFM_BSS))
- LONG (SIZEOF(.TFM_BSS))
- LONG (ADDR(.TFM_SECURE_STACK))
- LONG (SIZEOF(.TFM_SECURE_STACK))
- LONG (ADDR(.TFM_UNPRIV_SCRATCH))
- LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))
- __zero_table_end__ = .;
- } > FLASH
-
-#else /* TFM_LVL == 1 */
- .copy.table : ALIGN(4)
- {
- __copy_table_start__ = .;
- LONG (LOADADDR(.TFM_DATA))
- LONG (ADDR(.TFM_DATA))
- LONG (SIZEOF(.TFM_DATA))
+#if TFM_LVL != 1
LONG (LOADADDR(.TFM_UNPRIV_DATA))
LONG (ADDR(.TFM_UNPRIV_DATA))
LONG (SIZEOF(.TFM_UNPRIV_DATA))
+#endif /* TFM_LVL != 1 */
LONG (LOADADDR(.TFM_SP_STORAGE_DATA))
LONG (ADDR(.TFM_SP_STORAGE_DATA))
LONG (SIZEOF(.TFM_SP_STORAGE_DATA))
@@ -138,8 +117,13 @@
__zero_table_start__ = .;
LONG (ADDR(.TFM_BSS))
LONG (SIZEOF(.TFM_BSS))
+#if TFM_LVL == 1
+ LONG (ADDR(.TFM_SECURE_STACK))
+ LONG (SIZEOF(.TFM_SECURE_STACK))
+#else /* TFM_LVL == 1 */
LONG (ADDR(.TFM_UNPRIV_BSS))
LONG (SIZEOF(.TFM_UNPRIV_BSS))
+#endif /* TFM_LVL == 1 */
LONG (ADDR(.TFM_SP_STORAGE_BSS))
LONG (SIZEOF(.TFM_SP_STORAGE_BSS))
LONG (ADDR(.TFM_SP_STORAGE_STACK))
@@ -195,6 +179,7 @@
__zero_table_end__ = .;
} > FLASH
+#if TFM_LVL != 1
.TFM_UNPRIV_CODE : ALIGN(32)
{
*libc_nano*:*(.text*)
@@ -218,6 +203,7 @@
} > FLASH
Image$$TFM_UNPRIV_CODE$$RO$$Base = ADDR(.TFM_UNPRIV_CODE);
Image$$TFM_UNPRIV_CODE$$RO$$Limit = ADDR(.TFM_UNPRIV_CODE) + SIZEOF(.TFM_UNPRIV_CODE);
+#endif /* TFM_LVL != 1 */
/**** PSA RoT (CODE + RODATA) start here */
Image$$TFM_PSA_CODE_START$$Base = .;
@@ -375,6 +361,7 @@
/**** APPLICATION RoT (CODE + RODATA) end here */
Image$$TFM_APP_CODE_END$$Base = .;
+#if TFM_LVL != 1
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
@@ -387,7 +374,7 @@
} > FLASH
__exidx_end = .;
-#endif /* TFM_LVL == 1 */
+#endif /* TFM_LVL != 1 */
.ER_TFM_CODE : ALIGN(4)
{
@@ -447,13 +434,6 @@
Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);
Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);
- .TFM_UNPRIV_SCRATCH : ALIGN(32)
- {
- . += 0x400;
- } > RAM
- Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);
- Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);
-
.heap : ALIGN(8)
{
__end__ = .;
@@ -495,6 +475,7 @@
} > RAM
Image$$TFM_UNPRIV_DATA$$ZI$$Base = ADDR(.TFM_UNPRIV_BSS);
Image$$TFM_UNPRIV_DATA$$ZI$$Limit = ADDR(.TFM_UNPRIV_BSS) + SIZEOF(.TFM_UNPRIV_BSS);
+#endif /* TFM_LVL == 1 */
.TFM_UNPRIV_SCRATCH : ALIGN(32)
{
@@ -786,6 +767,7 @@
/**** APP RoT DATA end here */
Image$$TFM_APP_RW_STACK_END$$Base = .;
+#if TFM_LVL != 1
.TFM_SP_SECURE_TEST_PARTITION_DATA : ALIGN(32)
{
*libc_nano*:*(.data*)
@@ -814,7 +796,7 @@
. = ALIGN(32);
} > RAM
-#endif /* TFM_LVL == 1 */
+#endif /* TFM_LVL != 1 */
.TFM_DATA : ALIGN(4)
{
diff --git a/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld.template b/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld.template
index d56c432..73e162a 100644
--- a/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld.template
+++ b/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld.template
@@ -58,38 +58,17 @@
__vectors_end__ = .;
} > FLASH
-#if TFM_LVL == 1
.copy.table : ALIGN(4)
{
__copy_table_start__ = .;
LONG (LOADADDR(.TFM_DATA))
LONG (ADDR(.TFM_DATA))
LONG (SIZEOF(.TFM_DATA))
- __copy_table_end__ = .;
- } > FLASH
-
- .zero.table : ALIGN(4)
- {
- __zero_table_start__ = .;
- LONG (ADDR(.TFM_BSS))
- LONG (SIZEOF(.TFM_BSS))
- LONG (ADDR(.TFM_SECURE_STACK))
- LONG (SIZEOF(.TFM_SECURE_STACK))
- LONG (ADDR(.TFM_UNPRIV_SCRATCH))
- LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))
- __zero_table_end__ = .;
- } > FLASH
-
-#else /* TFM_LVL == 1 */
- .copy.table : ALIGN(4)
- {
- __copy_table_start__ = .;
- LONG (LOADADDR(.TFM_DATA))
- LONG (ADDR(.TFM_DATA))
- LONG (SIZEOF(.TFM_DATA))
+#if TFM_LVL != 1
LONG (LOADADDR(.TFM_UNPRIV_DATA))
LONG (ADDR(.TFM_UNPRIV_DATA))
LONG (SIZEOF(.TFM_UNPRIV_DATA))
+#endif /* TFM_LVL != 1 */
{% for manifest in manifests %}
{% if manifest.attr.conditional %}
#ifdef {{manifest.attr.conditional}}
@@ -109,8 +88,13 @@
__zero_table_start__ = .;
LONG (ADDR(.TFM_BSS))
LONG (SIZEOF(.TFM_BSS))
+#if TFM_LVL == 1
+ LONG (ADDR(.TFM_SECURE_STACK))
+ LONG (SIZEOF(.TFM_SECURE_STACK))
+#else /* TFM_LVL == 1 */
LONG (ADDR(.TFM_UNPRIV_BSS))
LONG (SIZEOF(.TFM_UNPRIV_BSS))
+#endif /* TFM_LVL == 1 */
{% for manifest in manifests %}
{% if manifest.attr.conditional %}
#ifdef {{manifest.attr.conditional}}
@@ -128,6 +112,7 @@
__zero_table_end__ = .;
} > FLASH
+#if TFM_LVL != 1
.TFM_UNPRIV_CODE : ALIGN(32)
{
*libc_nano*:*(.text*)
@@ -151,6 +136,7 @@
} > FLASH
Image$$TFM_UNPRIV_CODE$$RO$$Base = ADDR(.TFM_UNPRIV_CODE);
Image$$TFM_UNPRIV_CODE$$RO$$Limit = ADDR(.TFM_UNPRIV_CODE) + SIZEOF(.TFM_UNPRIV_CODE);
+#endif /* TFM_LVL != 1 */
/**** PSA RoT (CODE + RODATA) start here */
Image$$TFM_PSA_CODE_START$$Base = .;
@@ -228,6 +214,7 @@
/**** APPLICATION RoT (CODE + RODATA) end here */
Image$$TFM_APP_CODE_END$$Base = .;
+#if TFM_LVL != 1
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
@@ -240,7 +227,7 @@
} > FLASH
__exidx_end = .;
-#endif /* TFM_LVL == 1 */
+#endif /* TFM_LVL != 1 */
.ER_TFM_CODE : ALIGN(4)
{
@@ -300,13 +287,6 @@
Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);
Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);
- .TFM_UNPRIV_SCRATCH : ALIGN(32)
- {
- . += 0x400;
- } > RAM
- Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);
- Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);
-
.heap : ALIGN(8)
{
__end__ = .;
@@ -348,6 +328,7 @@
} > RAM
Image$$TFM_UNPRIV_DATA$$ZI$$Base = ADDR(.TFM_UNPRIV_BSS);
Image$$TFM_UNPRIV_DATA$$ZI$$Limit = ADDR(.TFM_UNPRIV_BSS) + SIZEOF(.TFM_UNPRIV_BSS);
+#endif /* TFM_LVL == 1 */
.TFM_UNPRIV_SCRATCH : ALIGN(32)
{
@@ -474,6 +455,7 @@
/**** APP RoT DATA end here */
Image$$TFM_APP_RW_STACK_END$$Base = .;
+#if TFM_LVL != 1
.TFM_SP_SECURE_TEST_PARTITION_DATA : ALIGN(32)
{
*libc_nano*:*(.data*)
@@ -502,7 +484,7 @@
. = ALIGN(32);
} > RAM
-#endif /* TFM_LVL == 1 */
+#endif /* TFM_LVL != 1 */
.TFM_DATA : ALIGN(4)
{