Platform: Enable BL2 on LPC55S69
Add BL2 support and set 'BL2=ON' as default on LPC55S69.
Due to the amount of available on-chip flash memory, the following
limitations apply when BL2 is enabled:
- Build type 'Debug' cannot be selected,
- Regression tests cannot be run on the board without modifying the
flash layout (secondary image areas must be set to 0 and in parallel
the size of the primary regions must be increased in order for the
S and NS images to fit in the flash).
Change-Id: I6e9a40ba202e05c86d6f91cb85c0b13674682c56
Signed-off-by: David Vincze <david.vincze@linaro.org>
diff --git a/docs/getting_started/tfm_secure_boot.rst b/docs/getting_started/tfm_secure_boot.rst
index 6be5aaf..f9f4599 100644
--- a/docs/getting_started/tfm_secure_boot.rst
+++ b/docs/getting_started/tfm_secure_boot.rst
@@ -234,9 +234,9 @@
+---------------------+-----------------+---------------+----------+----------------+--------------+
| AN539 | Yes | Yes | Yes | Yes | No |
+---------------------+-----------------+---------------+----------+----------------+--------------+
-| FVP_SSE300_MPS2 | NO | Yes | Yes | Yes | No |
+| FVP_SSE300_MPS2 | No | Yes | Yes | Yes | No |
+---------------------+-----------------+---------------+----------+----------------+--------------+
-| LPC55S69 | No | No | No | No | No |
+| LPC55S69 | Yes | Yes | No | Yes | No |
+---------------------+-----------------+---------------+----------+----------------+--------------+
| Musca-A | No | No | No | No | Yes |
+---------------------+-----------------+---------------+----------+----------------+--------------+
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/CMakeLists.txt b/platform/ext/target/nxp/lpcxpresso55s69/CMakeLists.txt
index ad02905..97cfd9c 100644
--- a/platform/ext/target/nxp/lpcxpresso55s69/CMakeLists.txt
+++ b/platform/ext/target/nxp/lpcxpresso55s69/CMakeLists.txt
@@ -1,5 +1,6 @@
#-------------------------------------------------------------------------------
# Copyright (c) 2020, Arm Limited. All rights reserved.
+# Copyright (c) 2020, Linaro. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -8,6 +9,12 @@
cmake_policy(SET CMP0076 NEW)
set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR})
+string(TOLOWER "${CMAKE_BUILD_TYPE}" BUILD_TYPE_LOWER)
+if (BL2 AND ${BUILD_TYPE_LOWER} STREQUAL "debug")
+ Message(FATAL_ERROR "If BL2 is enabled, \"${CMAKE_BUILD_TYPE}\" build type cannot be selected as it is currently not \
+ supported on ${TFM_PLATFORM}. For more information please refer to the platform's README file.")
+endif()
+
#========================= Platform region defs ===============================#
target_include_directories(platform_region_defs
@@ -17,6 +24,7 @@
#========================= Platform common defs ===============================#
+# Specify the location of platform specific build dependencies.
target_sources(tfm_s
PRIVATE
$<$<C_COMPILER_ID:GNU>:${CMAKE_CURRENT_SOURCE_DIR}/Device/Source/armgcc/startup_LPC55S69_cm33_core0_s.S>
@@ -43,6 +51,16 @@
)
endif()
+if(BL2)
+ target_sources(bl2
+ PRIVATE
+ $<$<C_COMPILER_ID:GNU>:${CMAKE_CURRENT_SOURCE_DIR}/Device/Source/armgcc/startup_LPC55S69_cm33_core0_bl2.S>
+ )
+ target_add_scatter_file(bl2
+ $<$<C_COMPILER_ID:GNU>:${CMAKE_CURRENT_SOURCE_DIR}/Device/Source/armgcc/LPC55S69_cm33_core0_bl2.ld>
+ )
+endif()
+
#========================= Platform Secure ====================================#
target_include_directories(platform_s
@@ -169,3 +187,60 @@
$<$<BOOL:${TFM_PARTITION_PLATFORM}>:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c>
)
+#========================= Platform BL2 =======================================#
+if(BL2)
+
+ target_include_directories(platform_bl2
+ PUBLIC
+ partition
+ Device/Include
+ Native_Driver
+ Native_Driver/project_template/bl2
+ ${PLATFORM_DIR}/ext/target/nxp/common/Native_Driver/drivers
+ PRIVATE
+ .
+ Device/config
+ ${PLATFORM_DIR}/ext/target/nxp/common/Native_Driver
+ ${PLATFORM_DIR}/ext/target/nxp/common/Native_Driver/components/serial_manager
+ ${PLATFORM_DIR}/ext/target/nxp/common/Native_Driver/components/uart
+ ${PLATFORM_DIR}/ext/target/nxp/common/Native_Driver/utilities/debug_console
+ ${PLATFORM_DIR}/ext/target/nxp/common/Native_Driver/utilities/str
+ )
+ target_sources(platform_bl2
+ PRIVATE
+ boot_hal.c
+ Native_Driver/project_template/bl2/board.c
+ Native_Driver/project_template/bl2/clock_config.c
+ Native_Driver/project_template/bl2/pin_mux.c
+ Native_Driver/system_LPC55S69_cm33_core0.c
+ ../common/CMSIS_Driver/Driver_Flash.c
+ ../common/CMSIS_Driver/Driver_USART.c
+ ../common/Native_Driver/components/serial_manager/serial_manager.c
+ ../common/Native_Driver/components/serial_manager/serial_port_uart.c
+ ../common/Native_Driver/components/uart/usart_adapter.c
+ ../common/Native_Driver/drivers/fsl_casper.c
+ ../common/Native_Driver/drivers/fsl_clock.c
+ ../common/Native_Driver/drivers/fsl_common.c
+ ../common/Native_Driver/drivers/fsl_flexcomm.c
+ ../common/Native_Driver/drivers/fsl_hashcrypt.c
+ ../common/Native_Driver/drivers/fsl_iap.c
+ ../common/Native_Driver/drivers/fsl_power.c
+ ../common/Native_Driver/drivers/fsl_reset.c
+ ../common/Native_Driver/drivers/fsl_rng.c
+ ../common/Native_Driver/drivers/fsl_usart.c
+ ../common/Native_Driver/utilities/fsl_assert.c
+ ../common/Native_Driver/utilities/fsl_sbrk.c
+ ../common/Native_Driver/utilities/debug_console/fsl_debug_console.c
+ ../common/Native_Driver/utilities/str/fsl_str.c
+ )
+
+ # GNU ld has some strange behaviour to do with weak functions, and does not deal
+ # well with strong functions in static libraries overriding weak functions in
+ # object files. For this reason, the file hardware_init is linked directly to
+ # the s binary as an object file. This issue does not affect armclang, but the
+ # fix is compatible.
+ target_sources(bl2
+ PRIVATE
+ Native_Driver/project_template/bl2/hardware_init.c
+ )
+endif()
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/LPC55S69_cm33_core0_bl2.ld b/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/LPC55S69_cm33_core0_bl2.ld
new file mode 100644
index 0000000..fcc7ffa
--- /dev/null
+++ b/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/LPC55S69_cm33_core0_bl2.ld
@@ -0,0 +1,200 @@
+;/*
+; * Copyright (c) 2009-2020 Arm Limited
+; * Copyright (c) 2020 Linaro Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 gcc_arm.ld
+; */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "../../../partition/region_defs.h"
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = BL2_CODE_START, LENGTH = BL2_CODE_SIZE
+ RAM (rwx) : ORIGIN = BL2_DATA_START, LENGTH = BL2_DATA_SIZE
+}
+
+__heap_size__ = BL2_HEAP_SIZE;
+__msp_stack_size__ = BL2_MSP_STACK_SIZE;
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ /* Startup section is loaded to Flash and runs from Flash */
+ .startup :
+ {
+ KEEP(*(.vectors))
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ *startup_LPC55S69_cm33_core0_bl2.*
+ } > FLASH
+
+ .text :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * define etext2/data2_start/data2_end and
+ * define __STARTUP_COPY_MULTIPLE in startup_LPC55S69_cm33_core0_bl2.S */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (DEFINED(__etext2) ? __etext2 : 0)
+ LONG (DEFINED(__data2_start__) ? __data2_start__ : 0)
+ LONG (DEFINED(__data2_start__) ? __data2_end__ - __data2_start__ : 0)
+ __copy_table_end__ = .;
+ } > FLASH
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in
+ * startup_LPC55S69_cm33_core0_bl2.S */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0)
+ LONG (DEFINED(__bss2_start__) ? __bss2_end__ - __bss2_start__ : 0)
+ __zero_table_end__ = .;
+ } > FLASH
+
+ __etext = .;
+
+ .tfm_bl2_shared_data : ALIGN(32)
+ {
+ . += BOOT_TFM_SHARED_DATA_SIZE;
+ } > RAM
+ Image$$SHARED_DATA$$RW$$Base = ADDR(.tfm_bl2_shared_data);
+ Image$$SHARED_DATA$$RW$$Limit = ADDR(.tfm_bl2_shared_data) + SIZEOF(.tfm_bl2_shared_data);
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+ Image$$ER_DATA$$Base = ADDR(.data);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ bss_size = __bss_end__ - __bss_start__;
+
+ .msp_stack : ALIGN(32)
+ {
+ . += __msp_stack_size__;
+ } > RAM
+ Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack);
+ Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);
+
+ .heap : ALIGN(8)
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += __heap_size__;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > RAM
+ Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap);
+
+ PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit);
+}
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/startup_LPC55S69_cm33_core0_bl2.S b/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/startup_LPC55S69_cm33_core0_bl2.S
new file mode 100644
index 0000000..56a2a1d
--- /dev/null
+++ b/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/startup_LPC55S69_cm33_core0_bl2.S
@@ -0,0 +1,917 @@
+;/*
+; * Copyright (c) 2009-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
+; */
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler*/
+ .long HardFault_Handler /* Hard Fault Handler*/
+ .long MemManage_Handler /* MPU Fault Handler*/
+ .long BusFault_Handler /* Bus Fault Handler*/
+ .long UsageFault_Handler /* Usage Fault Handler*/
+ .long SecureFault_Handler /* Secure Fault Handler */
+ .long 0 /* Reserved*/
+ .long 0 /* Reserved*/
+ .long 0 /* Reserved*/
+ .long SVC_Handler /* SVCall Handler*/
+ .long DebugMon_Handler /* Debug Monitor Handler*/
+ .long 0 /* Reserved*/
+ .long PendSV_Handler /* PendSV Handler*/
+ .long SysTick_Handler /* SysTick Handler*/
+
+ /* External Interrupts */
+ .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */
+ .long DMA0_IRQHandler /* DMA0 controller */
+ .long GINT0_IRQHandler /* GPIO group 0 */
+ .long GINT1_IRQHandler /* GPIO group 1 */
+ .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */
+ .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */
+ .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */
+ .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */
+ .long UTICK0_IRQHandler /* Micro-tick Timer */
+ .long MRT0_IRQHandler /* Multi-rate timer */
+ .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */
+ .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */
+ .long SCT0_IRQHandler /* SCTimer/PWM */
+ .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */
+ .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
+ .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
+ .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
+ .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
+ .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
+ .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
+ .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
+ .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
+ .long ADC0_IRQHandler /* ADC0 */
+ .long Reserved39_IRQHandler /* Reserved interrupt */
+ .long ACMP_IRQHandler /* ACMP interrupts */
+ .long Reserved41_IRQHandler /* Reserved interrupt */
+ .long Reserved42_IRQHandler /* Reserved interrupt */
+ .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */
+ .long USB0_IRQHandler /* USB device */
+ .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */
+ .long Reserved46_IRQHandler /* Reserved interrupt */
+ .long MAILBOX_IRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */
+ .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */
+ .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */
+ .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */
+ .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */
+ .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */
+ .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */
+ .long OS_EVENT_IRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
+ .long Reserved55_IRQHandler /* Reserved interrupt */
+ .long Reserved56_IRQHandler /* Reserved interrupt */
+ .long Reserved57_IRQHandler /* Reserved interrupt */
+ .long SDIO_IRQHandler /* SD/MMC */
+ .long Reserved59_IRQHandler /* Reserved interrupt */
+ .long Reserved60_IRQHandler /* Reserved interrupt */
+ .long Reserved61_IRQHandler /* Reserved interrupt */
+ .long USB1_UTMI_IRQHandler /* USB1_UTMI */
+ .long USB1_IRQHandler /* USB1 interrupt */
+ .long USB1_NEEDCLK_IRQHandler /* USB1 activity */
+ .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */
+ .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */
+ .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */
+ .long PLU_IRQHandler /* PLU interrupt */
+ .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */
+ .long HASHCRYPT_IRQHandler /* HASHCRYPT interrupt */
+ .long CASER_IRQHandler /* CASPER interrupt */
+ .long PUF_IRQHandler /* PUF interrupt */
+ .long PQ_IRQHandler /* PQ interrupt */
+ .long DMA1_IRQHandler /* DMA1 interrupt */
+ .long LSPI_HS_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+ /* Only run on core 0 */
+ mov r0, #0x50000000
+ add r0, #0x0001F000
+ ldr r0, [r0]
+ cmp r0,#0
+not_the_core_to_run_on:
+ bne not_the_core_to_run_on
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ bl SystemInit
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak DefaultISR
+ .type DefaultISR, %function
+DefaultISR:
+ b DefaultISR
+ .size DefaultISR, . - DefaultISR
+
+ .align 1
+ .thumb_func
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ ldr r0,=NMI_Handler
+ bx r0
+ .size NMI_Handler, . - NMI_Handler
+
+ .align 1
+ .thumb_func
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ ldr r0,=HardFault_Handler
+ bx r0
+ .size HardFault_Handler, . - HardFault_Handler
+
+ .align 1
+ .thumb_func
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ ldr r0,=SVC_Handler
+ bx r0
+ .size SVC_Handler, . - SVC_Handler
+
+ .align 1
+ .thumb_func
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ ldr r0,=PendSV_Handler
+ bx r0
+ .size PendSV_Handler, . - PendSV_Handler
+
+ .align 1
+ .thumb_func
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ ldr r0,=SysTick_Handler
+ bx r0
+ .size SysTick_Handler, . - SysTick_Handler
+
+ .align 1
+ .thumb_func
+ .weak WDT_BOD_IRQHandler
+ .type WDT_BOD_IRQHandler, %function
+WDT_BOD_IRQHandler:
+ ldr r0,=WDT_BOD_DriverIRQHandler
+ bx r0
+ .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak DMA0_IRQHandler
+ .type DMA0_IRQHandler, %function
+DMA0_IRQHandler:
+ ldr r0,=DMA0_DriverIRQHandler
+ bx r0
+ .size DMA0_IRQHandler, . - DMA0_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak GINT0_IRQHandler
+ .type GINT0_IRQHandler, %function
+GINT0_IRQHandler:
+ ldr r0,=GINT0_DriverIRQHandler
+ bx r0
+ .size GINT0_IRQHandler, . - GINT0_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak GINT1_IRQHandler
+ .type GINT1_IRQHandler, %function
+GINT1_IRQHandler:
+ ldr r0,=GINT1_DriverIRQHandler
+ bx r0
+ .size GINT1_IRQHandler, . - GINT1_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak PIN_INT0_IRQHandler
+ .type PIN_INT0_IRQHandler, %function
+PIN_INT0_IRQHandler:
+ ldr r0,=PIN_INT0_DriverIRQHandler
+ bx r0
+ .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak PIN_INT1_IRQHandler
+ .type PIN_INT1_IRQHandler, %function
+PIN_INT1_IRQHandler:
+ ldr r0,=PIN_INT1_DriverIRQHandler
+ bx r0
+ .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak PIN_INT2_IRQHandler
+ .type PIN_INT2_IRQHandler, %function
+PIN_INT2_IRQHandler:
+ ldr r0,=PIN_INT2_DriverIRQHandler
+ bx r0
+ .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak PIN_INT3_IRQHandler
+ .type PIN_INT3_IRQHandler, %function
+PIN_INT3_IRQHandler:
+ ldr r0,=PIN_INT3_DriverIRQHandler
+ bx r0
+ .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak UTICK0_IRQHandler
+ .type UTICK0_IRQHandler, %function
+UTICK0_IRQHandler:
+ ldr r0,=UTICK0_DriverIRQHandler
+ bx r0
+ .size UTICK0_IRQHandler, . - UTICK0_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak MRT0_IRQHandler
+ .type MRT0_IRQHandler, %function
+MRT0_IRQHandler:
+ ldr r0,=MRT0_DriverIRQHandler
+ bx r0
+ .size MRT0_IRQHandler, . - MRT0_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak CTIMER0_IRQHandler
+ .type CTIMER0_IRQHandler, %function
+CTIMER0_IRQHandler:
+ ldr r0,=CTIMER0_DriverIRQHandler
+ bx r0
+ .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak CTIMER1_IRQHandler
+ .type CTIMER1_IRQHandler, %function
+CTIMER1_IRQHandler:
+ ldr r0,=CTIMER1_DriverIRQHandler
+ bx r0
+ .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak SCT0_IRQHandler
+ .type SCT0_IRQHandler, %function
+SCT0_IRQHandler:
+ ldr r0,=SCT0_DriverIRQHandler
+ bx r0
+ .size SCT0_IRQHandler, . - SCT0_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak CTIMER3_IRQHandler
+ .type CTIMER3_IRQHandler, %function
+CTIMER3_IRQHandler:
+ ldr r0,=CTIMER3_DriverIRQHandler
+ bx r0
+ .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak FLEXCOMM0_IRQHandler
+ .type FLEXCOMM0_IRQHandler, %function
+FLEXCOMM0_IRQHandler:
+ ldr r0,=FLEXCOMM0_DriverIRQHandler
+ bx r0
+ .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak FLEXCOMM1_IRQHandler
+ .type FLEXCOMM1_IRQHandler, %function
+FLEXCOMM1_IRQHandler:
+ ldr r0,=FLEXCOMM1_DriverIRQHandler
+ bx r0
+ .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak FLEXCOMM2_IRQHandler
+ .type FLEXCOMM2_IRQHandler, %function
+FLEXCOMM2_IRQHandler:
+ ldr r0,=FLEXCOMM2_DriverIRQHandler
+ bx r0
+ .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak FLEXCOMM3_IRQHandler
+ .type FLEXCOMM3_IRQHandler, %function
+FLEXCOMM3_IRQHandler:
+ ldr r0,=FLEXCOMM3_DriverIRQHandler
+ bx r0
+ .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak FLEXCOMM4_IRQHandler
+ .type FLEXCOMM4_IRQHandler, %function
+FLEXCOMM4_IRQHandler:
+ ldr r0,=FLEXCOMM4_DriverIRQHandler
+ bx r0
+ .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak FLEXCOMM5_IRQHandler
+ .type FLEXCOMM5_IRQHandler, %function
+FLEXCOMM5_IRQHandler:
+ ldr r0,=FLEXCOMM5_DriverIRQHandler
+ bx r0
+ .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak FLEXCOMM6_IRQHandler
+ .type FLEXCOMM6_IRQHandler, %function
+FLEXCOMM6_IRQHandler:
+ ldr r0,=FLEXCOMM6_DriverIRQHandler
+ bx r0
+ .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak FLEXCOMM7_IRQHandler
+ .type FLEXCOMM7_IRQHandler, %function
+FLEXCOMM7_IRQHandler:
+ ldr r0,=FLEXCOMM7_DriverIRQHandler
+ bx r0
+ .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak ADC0_IRQHandler
+ .type ADC0_IRQHandler, %function
+ADC0_IRQHandler:
+ ldr r0,=ADC0_DriverIRQHandler
+ bx r0
+ .size ADC0_IRQHandler, . - ADC0_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak Reserved39_IRQHandler
+ .type Reserved39_IRQHandler, %function
+Reserved39_IRQHandler:
+ ldr r0,=Reserved39_DriverIRQHandler
+ bx r0
+ .size Reserved39_IRQHandler, . - Reserved39_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak ACMP_IRQHandler
+ .type ACMP_IRQHandler, %function
+ACMP_IRQHandler:
+ ldr r0,=ACMP_DriverIRQHandler
+ bx r0
+ .size ACMP_IRQHandler, . - ACMP_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak Reserved41_IRQHandler
+ .type Reserved41_IRQHandler, %function
+Reserved41_IRQHandler:
+ ldr r0,=Reserved41_DriverIRQHandler
+ bx r0
+ .size Reserved41_IRQHandler, . - Reserved41_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak Reserved42_IRQHandler
+ .type Reserved42_IRQHandler, %function
+Reserved42_IRQHandler:
+ ldr r0,=Reserved42_DriverIRQHandler
+ bx r0
+ .size Reserved42_IRQHandler, . - Reserved42_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak USB0_NEEDCLK_IRQHandler
+ .type USB0_NEEDCLK_IRQHandler, %function
+USB0_NEEDCLK_IRQHandler:
+ ldr r0,=USB0_NEEDCLK_DriverIRQHandler
+ bx r0
+ .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak USB0_IRQHandler
+ .type USB0_IRQHandler, %function
+USB0_IRQHandler:
+ ldr r0,=USB0_DriverIRQHandler
+ bx r0
+ .size USB0_IRQHandler, . - USB0_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak RTC_IRQHandler
+ .type RTC_IRQHandler, %function
+RTC_IRQHandler:
+ ldr r0,=RTC_DriverIRQHandler
+ bx r0
+ .size RTC_IRQHandler, . - RTC_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak Reserved46_IRQHandler
+ .type Reserved46_IRQHandler, %function
+Reserved46_IRQHandler:
+ ldr r0,=Reserved46_DriverIRQHandler
+ bx r0
+ .size Reserved46_IRQHandler, . - Reserved46_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak MAILBOX_IRQHandler
+ .type MAILBOX_IRQHandler, %function
+MAILBOX_IRQHandler:
+ ldr r0,=MAILBOX_DriverIRQHandler
+ bx r0
+ .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak PIN_INT4_IRQHandler
+ .type PIN_INT4_IRQHandler, %function
+PIN_INT4_IRQHandler:
+ ldr r0,=PIN_INT4_DriverIRQHandler
+ bx r0
+ .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak PIN_INT5_IRQHandler
+ .type PIN_INT5_IRQHandler, %function
+PIN_INT5_IRQHandler:
+ ldr r0,=PIN_INT5_DriverIRQHandler
+ bx r0
+ .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak PIN_INT6_IRQHandler
+ .type PIN_INT6_IRQHandler, %function
+PIN_INT6_IRQHandler:
+ ldr r0,=PIN_INT6_DriverIRQHandler
+ bx r0
+ .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak PIN_INT7_IRQHandler
+ .type PIN_INT7_IRQHandler, %function
+PIN_INT7_IRQHandler:
+ ldr r0,=PIN_INT7_DriverIRQHandler
+ bx r0
+ .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak CTIMER2_IRQHandler
+ .type CTIMER2_IRQHandler, %function
+CTIMER2_IRQHandler:
+ ldr r0,=CTIMER2_DriverIRQHandler
+ bx r0
+ .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak CTIMER4_IRQHandler
+ .type CTIMER4_IRQHandler, %function
+CTIMER4_IRQHandler:
+ ldr r0,=CTIMER4_DriverIRQHandler
+ bx r0
+ .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak OS_EVENT_IRQHandler
+ .type OS_EVENT_IRQHandler, %function
+OS_EVENT_IRQHandler:
+ ldr r0,=OS_EVENT_DriverIRQHandler
+ bx r0
+ .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak Reserved55_IRQHandler
+ .type Reserved55_IRQHandler, %function
+Reserved55_IRQHandler:
+ ldr r0,=Reserved55_DriverIRQHandler
+ bx r0
+ .size Reserved55_IRQHandler, . - Reserved55_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak Reserved56_IRQHandler
+ .type Reserved56_IRQHandler, %function
+Reserved56_IRQHandler:
+ ldr r0,=Reserved56_DriverIRQHandler
+ bx r0
+ .size Reserved56_IRQHandler, . - Reserved56_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak Reserved57_IRQHandler
+ .type Reserved57_IRQHandler, %function
+Reserved57_IRQHandler:
+ ldr r0,=Reserved57_DriverIRQHandler
+ bx r0
+ .size Reserved57_IRQHandler, . - Reserved57_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak SDIO_IRQHandler
+ .type SDIO_IRQHandler, %function
+SDIO_IRQHandler:
+ ldr r0,=SDIO_DriverIRQHandler
+ bx r0
+ .size SDIO_IRQHandler, . - SDIO_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak Reserved59_IRQHandler
+ .type Reserved59_IRQHandler, %function
+Reserved59_IRQHandler:
+ ldr r0,=Reserved59_DriverIRQHandler
+ bx r0
+ .size Reserved59_IRQHandler, . - Reserved59_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak Reserved60_IRQHandler
+ .type Reserved60_IRQHandler, %function
+Reserved60_IRQHandler:
+ ldr r0,=Reserved60_DriverIRQHandler
+ bx r0
+ .size Reserved60_IRQHandler, . - Reserved60_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak Reserved61_IRQHandler
+ .type Reserved61_IRQHandler, %function
+Reserved61_IRQHandler:
+ ldr r0,=Reserved61_DriverIRQHandler
+ bx r0
+ .size Reserved61_IRQHandler, . - Reserved61_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak USB1_UTMI_IRQHandler
+ .type USB1_UTMI_IRQHandler, %function
+USB1_UTMI_IRQHandler:
+ ldr r0,=USB1_UTMI_DriverIRQHandler
+ bx r0
+ .size USB1_UTMI_IRQHandler, . - USB1_UTMI_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak USB1_IRQHandler
+ .type USB1_IRQHandler, %function
+USB1_IRQHandler:
+ ldr r0,=USB1_DriverIRQHandler
+ bx r0
+ .size USB1_IRQHandler, . - USB1_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak USB1_NEEDCLK_IRQHandler
+ .type USB1_NEEDCLK_IRQHandler, %function
+USB1_NEEDCLK_IRQHandler:
+ ldr r0,=USB1_NEEDCLK_DriverIRQHandler
+ bx r0
+ .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak SEC_HYPERVISOR_CALL_IRQHandler
+ .type SEC_HYPERVISOR_CALL_IRQHandler, %function
+SEC_HYPERVISOR_CALL_IRQHandler:
+ ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler
+ bx r0
+ .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak SEC_GPIO_INT0_IRQ0_IRQHandler
+ .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function
+SEC_GPIO_INT0_IRQ0_IRQHandler:
+ ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler
+ bx r0
+ .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak SEC_GPIO_INT0_IRQ1_IRQHandler
+ .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function
+SEC_GPIO_INT0_IRQ1_IRQHandler:
+ ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler
+ bx r0
+ .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak PLU_IRQHandler
+ .type PLU_IRQHandler, %function
+PLU_IRQHandler:
+ ldr r0,=PLU_DriverIRQHandler
+ bx r0
+ .size PLU_IRQHandler, . - PLU_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak SEC_VIO_IRQHandler
+ .type SEC_VIO_IRQHandler, %function
+SEC_VIO_IRQHandler:
+ ldr r0,=SEC_VIO_DriverIRQHandler
+ bx r0
+ .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak HASHCRYPT_IRQHandler
+ .type HASHCRYPT_IRQHandler, %function
+HASHCRYPT_IRQHandler:
+ ldr r0,=HASHCRYPT_DriverIRQHandler
+ bx r0
+ .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak CASER_IRQHandler
+ .type CASER_IRQHandler, %function
+CASER_IRQHandler:
+ ldr r0,=CASER_DriverIRQHandler
+ bx r0
+ .size CASER_IRQHandler, . - CASER_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak PUF_IRQHandler
+ .type PUF_IRQHandler, %function
+PUF_IRQHandler:
+ ldr r0,=PUF_DriverIRQHandler
+ bx r0
+ .size PUF_IRQHandler, . - PUF_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak PQ_IRQHandler
+ .type PQ_IRQHandler, %function
+PQ_IRQHandler:
+ ldr r0,=PQ_DriverIRQHandler
+ bx r0
+ .size PQ_IRQHandler, . - PQ_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak DMA1_IRQHandler
+ .type DMA1_IRQHandler, %function
+DMA1_IRQHandler:
+ ldr r0,=DMA1_DriverIRQHandler
+ bx r0
+ .size DMA1_IRQHandler, . - DMA1_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak LSPI_HS_IRQHandler
+ .type LSPI_HS_IRQHandler, %function
+LSPI_HS_IRQHandler:
+ ldr r0,=LSPI_HS_DriverIRQHandler
+ bx r0
+ .size LSPI_HS_IRQHandler, . - LSPI_HS_IRQHandler
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, DefaultISR
+ .endm
+/* Exception Handlers */
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SecureFault_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler WDT_BOD_DriverIRQHandler
+ def_irq_handler DMA0_DriverIRQHandler
+ def_irq_handler GINT0_DriverIRQHandler
+ def_irq_handler GINT1_DriverIRQHandler
+ def_irq_handler PIN_INT0_DriverIRQHandler
+ def_irq_handler PIN_INT1_DriverIRQHandler
+ def_irq_handler PIN_INT2_DriverIRQHandler
+ def_irq_handler PIN_INT3_DriverIRQHandler
+ def_irq_handler UTICK0_DriverIRQHandler
+ def_irq_handler MRT0_DriverIRQHandler
+ def_irq_handler CTIMER0_DriverIRQHandler
+ def_irq_handler CTIMER1_DriverIRQHandler
+ def_irq_handler SCT0_DriverIRQHandler
+ def_irq_handler CTIMER3_DriverIRQHandler
+ def_irq_handler FLEXCOMM0_DriverIRQHandler
+ def_irq_handler FLEXCOMM1_DriverIRQHandler
+ def_irq_handler FLEXCOMM2_DriverIRQHandler
+ def_irq_handler FLEXCOMM3_DriverIRQHandler
+ def_irq_handler FLEXCOMM4_DriverIRQHandler
+ def_irq_handler FLEXCOMM5_DriverIRQHandler
+ def_irq_handler FLEXCOMM6_DriverIRQHandler
+ def_irq_handler FLEXCOMM7_DriverIRQHandler
+ def_irq_handler ADC0_DriverIRQHandler
+ def_irq_handler Reserved39_DriverIRQHandler
+ def_irq_handler ACMP_DriverIRQHandler
+ def_irq_handler Reserved41_DriverIRQHandler
+ def_irq_handler Reserved42_DriverIRQHandler
+ def_irq_handler USB0_NEEDCLK_DriverIRQHandler
+ def_irq_handler USB0_DriverIRQHandler
+ def_irq_handler RTC_DriverIRQHandler
+ def_irq_handler Reserved46_DriverIRQHandler
+ def_irq_handler MAILBOX_DriverIRQHandler
+ def_irq_handler PIN_INT4_DriverIRQHandler
+ def_irq_handler PIN_INT5_DriverIRQHandler
+ def_irq_handler PIN_INT6_DriverIRQHandler
+ def_irq_handler PIN_INT7_DriverIRQHandler
+ def_irq_handler CTIMER2_DriverIRQHandler
+ def_irq_handler CTIMER4_DriverIRQHandler
+ def_irq_handler OS_EVENT_DriverIRQHandler
+ def_irq_handler Reserved55_DriverIRQHandler
+ def_irq_handler Reserved56_DriverIRQHandler
+ def_irq_handler Reserved57_DriverIRQHandler
+ def_irq_handler SDIO_DriverIRQHandler
+ def_irq_handler Reserved59_DriverIRQHandler
+ def_irq_handler Reserved60_DriverIRQHandler
+ def_irq_handler Reserved61_DriverIRQHandler
+ def_irq_handler USB1_UTMI_DriverIRQHandler
+ def_irq_handler USB1_DriverIRQHandler
+ def_irq_handler USB1_NEEDCLK_DriverIRQHandler
+ def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler
+ def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler
+ def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler
+ def_irq_handler PLU_DriverIRQHandler
+ def_irq_handler SEC_VIO_DriverIRQHandler
+ def_irq_handler HASHCRYPT_DriverIRQHandler
+ def_irq_handler CASER_DriverIRQHandler
+ def_irq_handler PUF_DriverIRQHandler
+ def_irq_handler PQ_DriverIRQHandler
+ def_irq_handler DMA1_DriverIRQHandler
+ def_irq_handler LSPI_HS_DriverIRQHandler
+
+ .end
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/app.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/app.h
new file mode 100644
index 0000000..ab675a5
--- /dev/null
+++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/app.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _APP_H_
+#define _APP_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+void BOARD_InitHardware(void);
+
+#endif /* _APP_H_ */
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/board.c b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/board.c
new file mode 100644
index 0000000..4b83689
--- /dev/null
+++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/board.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "board.h"
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+#include "fsl_i2c.h"
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+ CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+ RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);
+
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+
+void BOARD_InitDebugConsole_Core1(void)
+{
+ /* attach 12 MHz clock to FLEXCOMM1 (debug console) */
+ CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH_CORE1);
+
+ RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST_CORE1);
+
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ_CORE1;
+
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE_CORE1, BOARD_DEBUG_UART_BAUDRATE_CORE1, BOARD_DEBUG_UART_TYPE_CORE1,
+ uartClkSrcFreq);
+}
+
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
+{
+ i2c_master_config_t i2cConfig = {0};
+
+ I2C_MasterGetDefaultConfig(&i2cConfig);
+ I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
+}
+
+status_t BOARD_I2C_Send(I2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subaddressSize,
+ uint8_t *txBuff,
+ uint8_t txBuffSize)
+{
+ i2c_master_transfer_t masterXfer;
+
+ /* Prepare transfer structure. */
+ masterXfer.slaveAddress = deviceAddress;
+ masterXfer.direction = kI2C_Write;
+ masterXfer.subaddress = subAddress;
+ masterXfer.subaddressSize = subaddressSize;
+ masterXfer.data = txBuff;
+ masterXfer.dataSize = txBuffSize;
+ masterXfer.flags = kI2C_TransferDefaultFlag;
+
+ return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+status_t BOARD_I2C_Receive(I2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subaddressSize,
+ uint8_t *rxBuff,
+ uint8_t rxBuffSize)
+{
+ i2c_master_transfer_t masterXfer;
+
+ /* Prepare transfer structure. */
+ masterXfer.slaveAddress = deviceAddress;
+ masterXfer.subaddress = subAddress;
+ masterXfer.subaddressSize = subaddressSize;
+ masterXfer.data = rxBuff;
+ masterXfer.dataSize = rxBuffSize;
+ masterXfer.direction = kI2C_Read;
+ masterXfer.flags = kI2C_TransferDefaultFlag;
+
+ return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+void BOARD_Accel_I2C_Init(void)
+{
+ BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
+{
+ uint8_t data = (uint8_t)txBuff;
+
+ return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
+}
+
+status_t BOARD_Accel_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+ return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_Codec_I2C_Init(void)
+{
+ BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Codec_I2C_Send(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+ return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+ txBuffSize);
+}
+
+status_t BOARD_Codec_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+ return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+}
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/board.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/board.h
new file mode 100644
index 0000000..e69cdf7
--- /dev/null
+++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/board.h
@@ -0,0 +1,239 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_common.h"
+#include "fsl_reset.h"
+#include "fsl_gpio.h"
+#include "fsl_iocon.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "LPCXpresso55S69"
+
+/*! @brief The UART to use for debug messages. */
+/* TODO: rename UART to USART */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) USART0
+#define BOARD_DEBUG_UART_INSTANCE 0U
+#define BOARD_DEBUG_UART_CLK_FREQ 12000000U
+#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0
+#define BOARD_DEBUG_UART_RST kFC0_RST_SHIFT_RSTn
+#define BOARD_DEBUG_UART_CLKSRC kCLOCK_Flexcomm0
+#define BOARD_UART_IRQ_HANDLER FLEXCOMM0_IRQHandler
+#define BOARD_UART_IRQ FLEXCOMM0_IRQn
+
+#define BOARD_ACCEL_I2C_BASEADDR I2C4
+#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000
+
+#define BOARD_DEBUG_UART_TYPE_CORE1 kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR_CORE1 (uint32_t) USART1
+#define BOARD_DEBUG_UART_INSTANCE_CORE1 1U
+#define BOARD_DEBUG_UART_CLK_FREQ_CORE1 12000000U
+#define BOARD_DEBUG_UART_CLK_ATTACH_CORE1 kFRO12M_to_FLEXCOMM1
+#define BOARD_DEBUG_UART_RST_CORE1 kFC1_RST_SHIFT_RSTn
+#define BOARD_DEBUG_UART_CLKSRC_CORE1 kCLOCK_Flexcomm1
+#define BOARD_UART_IRQ_HANDLER_CORE1 FLEXCOMM1_IRQHandler
+#define BOARD_UART_IRQ_CORE1 FLEXCOMM1_IRQn
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE 115200U
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE_CORE1
+#define BOARD_DEBUG_UART_BAUDRATE_CORE1 115200U
+#endif /* BOARD_DEBUG_UART_BAUDRATE_CORE1 */
+
+#define BOARD_CODEC_I2C_BASEADDR I2C4
+#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000
+#define BOARD_CODEC_I2C_INSTANCE 4
+#ifndef BOARD_LED_RED_GPIO
+#define BOARD_LED_RED_GPIO GPIO
+#endif
+#define BOARD_LED_RED_GPIO_PORT 1U
+#ifndef BOARD_LED_RED_GPIO_PIN
+#define BOARD_LED_RED_GPIO_PIN 6U
+#endif
+
+#ifndef BOARD_LED_BLUE_GPIO
+#define BOARD_LED_BLUE_GPIO GPIO
+#endif
+#define BOARD_LED_BLUE_GPIO_PORT 1U
+#ifndef BOARD_LED_BLUE_GPIO_PIN
+#define BOARD_LED_BLUE_GPIO_PIN 4U
+#endif
+
+#ifndef BOARD_LED_GREEN_GPIO
+#define BOARD_LED_GREEN_GPIO GPIO
+#endif
+#define BOARD_LED_GREEN_GPIO_PORT 1U
+#ifndef BOARD_LED_GREEN_GPIO_PIN
+#define BOARD_LED_GREEN_GPIO_PIN 7U
+#endif
+
+#ifndef BOARD_SW1_GPIO
+#define BOARD_SW1_GPIO GPIO
+#endif
+#define BOARD_SW1_GPIO_PORT 0U
+#ifndef BOARD_SW1_GPIO_PIN
+#define BOARD_SW1_GPIO_PIN 5U
+#endif
+#define BOARD_SW1_NAME "SW1"
+#define BOARD_SW1_IRQ PIN_INT0_IRQn
+#define BOARD_SW1_IRQ_HANDLER PIN_INT0_IRQHandler
+
+#ifndef BOARD_SW2_GPIO
+#define BOARD_SW2_GPIO GPIO
+#endif
+#define BOARD_SW2_GPIO_PORT 1U
+#ifndef BOARD_SW2_GPIO_PIN
+#define BOARD_SW2_GPIO_PIN 18U
+#endif
+#define BOARD_SW2_NAME "SW2"
+#define BOARD_SW2_IRQ PIN_INT1_IRQn
+#define BOARD_SW2_IRQ_HANDLER PIN_INT1_IRQHandler
+#define BOARD_SW2_GPIO_PININT_INDEX 1
+
+#ifndef BOARD_SW3_GPIO
+#define BOARD_SW3_GPIO GPIO
+#endif
+#define BOARD_SW3_GPIO_PORT 1U
+#ifndef BOARD_SW3_GPIO_PIN
+#define BOARD_SW3_GPIO_PIN 9U
+#endif
+#define BOARD_SW3_NAME "SW3"
+#define BOARD_SW3_IRQ PIN_INT1_IRQn
+#define BOARD_SW3_IRQ_HANDLER PIN_INT1_IRQHandler
+#define BOARD_SW3_GPIO_PININT_INDEX 1
+
+/* Board led color mapping */
+#define LOGIC_LED_ON 0U
+#define LOGIC_LED_OFF 1U
+
+#define LED_RED_INIT(output) \
+ { \
+ IOCON_PinMuxSet(IOCON, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, IOCON_DIGITAL_EN); \
+ GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, \
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
+ }
+#define LED_RED_ON() \
+ GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+ 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED_RED_OFF() \
+ GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+ 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED1 \ \ \ \ \ \ \ \ \ \ \
+ */
+#define LED_RED_TOGGLE() \
+ GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+ 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED1 */
+
+#define LED_BLUE_INIT(output) \
+ { \
+ IOCON_PinMuxSet(IOCON, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, IOCON_DIGITAL_EN); \
+ GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
+ }
+#define LED_BLUE_ON() \
+ GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+ 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED_BLUE_OFF() \
+ GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+ 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_BLUE_TOGGLE() \
+ GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+ 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED1 */
+
+#define LED_GREEN_INIT(output) \
+ GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED1 */
+#define LED_GREEN_ON() \
+ GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+ 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED_GREEN_OFF() \
+ GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+ 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_GREEN_TOGGLE() \
+ GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+ 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED1 */
+
+/*! @brief The WIFI-QCA shield pin. */
+#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO
+#define BOARD_INITGT202SHIELD_PWRON_PORT 1U
+#define BOARD_INITGT202SHIELD_PWRON_PIN 8U
+
+#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO
+#define BOARD_INITGT202SHIELD_IRQ_PORT 1U
+#define BOARD_INITGT202SHIELD_IRQ_PIN 9U
+
+/*! @brief The WIFI-QCA shield pin. */
+#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO
+#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U
+#define BOARD_INITSILEX2401SHIELD_PWRON_PIN 7U
+
+#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO
+#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 0U
+#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 15U
+
+/*! @brief The WIFI-QCA shield pin. */
+#define BOARD_INITWIFI10CLICKSHIELD_PWRON_GPIO GPIO
+#define BOARD_INITWIFI10CLICKSHIELD_PWRON_PORT 1U
+#define BOARD_INITWIFI10CLICKSHIELD_PWRON_PIN 5U
+
+#define BOARD_INITWIFI10CLICKSHIELD_IRQ_GPIO GPIO
+#define BOARD_INITWIFI10CLICKSHIELD_IRQ_PORT 1U
+#define BOARD_INITWIFI10CLICKSHIELD_IRQ_GPIO_PIN 18U
+
+/* Display. */
+#define BOARD_LCD_DC_GPIO GPIO
+#define BOARD_LCD_DC_GPIO_PORT 1U
+#define BOARD_LCD_DC_GPIO_PIN 5U
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitDebugConsole_Core1(void);
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);
+status_t BOARD_I2C_Send(I2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subaddressSize,
+ uint8_t *txBuff,
+ uint8_t txBuffSize);
+status_t BOARD_I2C_Receive(I2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subaddressSize,
+ uint8_t *rxBuff,
+ uint8_t rxBuffSize);
+void BOARD_Accel_I2C_Init(void);
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
+status_t BOARD_Accel_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+void BOARD_Codec_I2C_Init(void);
+status_t BOARD_Codec_I2C_Send(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
+status_t BOARD_Codec_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/clock_config.c b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/clock_config.c
new file mode 100644
index 0000000..664c9cd
--- /dev/null
+++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/clock_config.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v7.0
+processor: LPC55S69
+package_id: LPC55S69JBD100
+mcu_data: ksdk2_0
+processor_version: 0.7.2
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockFROHF96M();
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+ /*!< Set up the clock sources */
+ /*!< Configure FRO192M */
+ /*!< Ensure FRO is on */
+ POWER_DisablePD(kPDRUNCFG_PD_FRO192M);
+ /*!< Set up FRO to the 12 MHz, just for sure */
+ CLOCK_SetupFROClocking(12000000U);
+ /*!< Switch to FRO 12MHz first to ensure we can change the clock */
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
+ /* Enable FRO HF(96MHz) output */
+ CLOCK_SetupFROClocking(96000000U);
+ /*!< Set FLASH wait states for core */
+ CLOCK_SetFLASHAccessCyclesForFreq(96000000U);
+ /*!< Set up dividers */
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);
+ /*!< Set up clock selectors - Attach clocks to the peripheries */
+ CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);
+ /* Enables the clock for the I/O controller.: Enable Clock. */
+ CLOCK_EnableClock(kCLOCK_Iocon);
+ /*< Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+#endif
+}
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/clock_config.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/clock_config.h
new file mode 100644
index 0000000..e7f1ec6
--- /dev/null
+++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/clock_config.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockPLL1_150M ********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL1_150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/hardware_init.c b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/hardware_init.c
new file mode 100644
index 0000000..5bed959
--- /dev/null
+++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/hardware_init.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+#include "pin_mux.h"
+#include "board.h"
+#include "clock_config.h"
+
+void BOARD_InitHardware(void)
+{
+ /* attach main clock divide to FLEXCOMM0 (debug console) */
+ CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+ BOARD_InitPins();
+
+ /* Flash operations (erase, blank check, program) and reading single word can only be performed for CPU frequencies
+ of up to 100 MHz. Cannot be performed for frequencies above 100 MHz. */
+ BOARD_BootClockFROHF96M();
+
+ BOARD_InitDebugConsole();
+}
+
+void SystemInitHook(void)
+{
+ BOARD_InitHardware();
+}
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/pin_mux.c b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/pin_mux.c
new file mode 100644
index 0000000..2a548e4
--- /dev/null
+++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/pin_mux.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v6.0
+processor: LPC55S69
+package_id: LPC55S69JBD100
+mcu_data: ksdk2_0
+processor_version: 0.0.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_iocon.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,
+ mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
+ - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,
+ slew_rate: standard, invert: disabled, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitPins(void)
+{
+ /* Enables the clock for the I/O controller.: Enable Clock. */
+ CLOCK_EnableClock(kCLOCK_Iocon);
+
+ const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
+ IOCON_PIO_FUNC1 |
+ /* No addition pin function */
+ IOCON_PIO_MODE_INACT |
+ /* Standard mode, output slew rate control is enabled */
+ IOCON_PIO_SLEW_STANDARD |
+ /* Input function is not inverted */
+ IOCON_PIO_INV_DI |
+ /* Enables digital function */
+ IOCON_PIO_DIGITAL_EN |
+ /* Open drain is disabled */
+ IOCON_PIO_OPENDRAIN_DI);
+ /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
+ IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config);
+
+ const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
+ IOCON_PIO_FUNC1 |
+ /* No addition pin function */
+ IOCON_PIO_MODE_INACT |
+ /* Standard mode, output slew rate control is enabled */
+ IOCON_PIO_SLEW_STANDARD |
+ /* Input function is not inverted */
+ IOCON_PIO_INV_DI |
+ /* Enables digital function */
+ IOCON_PIO_DIGITAL_EN |
+ /* Open drain is disabled */
+ IOCON_PIO_OPENDRAIN_DI);
+ /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
+ IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/pin_mux.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/pin_mux.h
new file mode 100644
index 0000000..ff9b963
--- /dev/null
+++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/project_template/bl2/pin_mux.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */
+#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/boot_hal.c b/platform/ext/target/nxp/lpcxpresso55s69/boot_hal.c
new file mode 100644
index 0000000..9e93972
--- /dev/null
+++ b/platform/ext/target/nxp/lpcxpresso55s69/boot_hal.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "cmsis.h"
+#include "region.h"
+#include "target_cfg.h"
+#include "boot_hal.h"
+#include "Driver_Flash.h"
+#include "flash_layout.h"
+
+/* Flash device name must be specified by target */
+extern ARM_DRIVER_FLASH FLASH_DEV_NAME;
+
+REGION_DECLARE(Image$$, ER_DATA, $$Base)[];
+REGION_DECLARE(Image$$, ARM_LIB_HEAP, $$ZI$$Limit)[];
+REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base);
+
+__attribute__((naked)) void boot_clear_bl2_ram_area(void)
+{
+ __ASM volatile(
+ "mov r0, #0 \n"
+ "subs %1, %1, %0 \n"
+ "Loop: \n"
+ "subs %1, #4 \n"
+ "itt ge \n"
+ "strge r0, [%0, %1] \n"
+ "bge Loop \n"
+ "bx lr \n"
+ :
+ : "r" (REGION_NAME(Image$$, ER_DATA, $$Base)),
+ "r" (REGION_NAME(Image$$, ARM_LIB_HEAP, $$ZI$$Limit))
+ : "r0", "memory"
+ );
+}
+
+int32_t boot_platform_init(void)
+{
+ int32_t result;
+
+ /* Initialize stack limit register */
+ uint32_t msp_stack_bottom =
+ (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base);
+
+ __set_MSPLIM(msp_stack_bottom);
+
+ result = FLASH_DEV_NAME.Initialize(NULL);
+ if (result != ARM_DRIVER_OK) {
+ return 1;
+ }
+
+ return 0;
+}
+
+void boot_platform_quit(struct boot_arm_vector_table *vt)
+{
+ /* Clang at O0, stores variables on the stack with SP relative addressing.
+ * When manually set the SP then the place of reset vector is lost.
+ * Static variables are stored in 'data' or 'bss' section, change of SP has
+ * no effect on them.
+ */
+ static struct boot_arm_vector_table *vt_cpy;
+ int32_t result;
+
+ result = FLASH_DEV_NAME.Uninitialize();
+ if (result != ARM_DRIVER_OK) {
+ while (1);
+ }
+
+ vt_cpy = vt;
+
+ __set_MSPLIM(0);
+ __set_MSP(vt->msp);
+ __DSB();
+ __ISB();
+
+ boot_jump_to_next_image(vt_cpy->reset);
+}
+
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/config.cmake b/platform/ext/target/nxp/lpcxpresso55s69/config.cmake
index fc34747..a81c8a1 100644
--- a/platform/ext/target/nxp/lpcxpresso55s69/config.cmake
+++ b/platform/ext/target/nxp/lpcxpresso55s69/config.cmake
@@ -4,5 +4,3 @@
# SPDX-License-Identifier: BSD-3-Clause
#
#-------------------------------------------------------------------------------
-
-set(BL2 OFF CACHE BOOL "Whether to build BL2" FORCE)
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/partition/flash_layout.h b/platform/ext/target/nxp/lpcxpresso55s69/partition/flash_layout.h
index 0e45d5d..18c37c1 100755
--- a/platform/ext/target/nxp/lpcxpresso55s69/partition/flash_layout.h
+++ b/platform/ext/target/nxp/lpcxpresso55s69/partition/flash_layout.h
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2018-2020 Arm Limited. All rights reserved.
* Copyright (c) 2020 Cypress Semiconductor Corporation. All rights reserved.
+ * Copyright (c) 2020 Linaro. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -18,16 +19,38 @@
#ifndef __FLASH_LAYOUT_H__
#define __FLASH_LAYOUT_H__
-/* Flash layout on LPC55S69 without BL2:
+/* Flash layout on LPC55S69 with BL2 (multiple image boot):
*
- * 0x0000_0000 Primary image area(576 kB):
- * 0x0000_0000 Secure image primary
- * 0x0005_0000 Non-secure image primary
- * 0x0009_0000 Secondary image area (0 KB):
- * 0x0009_0000 Protected Storage Area (16 KB)
- * 0x0009_4000 Internal Trusted Storage Area (8 KB)
- * 0x0009_6000 NV counters area (512 B)
- * 0x0006_6200 Unused
+ * 0x0000_0000 BL2 - MCUBoot (32 KB)
+ * 0x0000_8000 Secure image primary slot (160 KB)
+ * 0x0003_0000 Non-secure image primary slot (96 KB)
+ * 0x0004_8000 Secure image secondary slot (160 KB)
+ * 0x0007_0000 Non-secure image secondary slot (96 KB)
+ * 0x0008_8000 Protected Storage Area (8 KB)
+ * 0x0008_A000 Internal Trusted Storage Area (2 KB)
+ * 0x0008_A800 NV counters area (512 B)
+ * 0x0008_AA00 Unused (53.5 KB)
+ *
+ * Flash layout on LPC55S69 with BL2 (single image boot):
+ *
+ * 0x0000_0000 BL2 - MCUBoot (32 KB)
+ * 0x0000_8000 Primary image area (Secure + Non-secure images) (256 KB)
+ * 0x0004_8000 Secondary image area (Secure + Non-secure images) (256 KB)
+ * 0x0008_8000 Protected Storage Area (8 KB)
+ * 0x0008_A000 Internal Trusted Storage Area (2 KB)
+ * 0x0008_A800 NV counters area (512 B)
+ * 0x0008_AA00 Unused (53.5 KB)
+ *
+ * Flash layout on LPC55S69 without BL2:
+ *
+ * 0x0000_0000 Secure + Non-secure image area (512 KB):
+ * 0x0000_0000 Secure image (256 KB)
+ * 0x0004_0000 Non-secure image (256 KB)
+ * 0x0008_0000 Secondary image area (0 KB):
+ * 0x0008_0000 Protected Storage Area (16 KB)
+ * 0x0008_4000 Internal Trusted Storage Area (8 KB)
+ * 0x0008_6000 NV counters area (512 B)
+ * 0x0008_6200 Unused (71.5 KB)
*/
/* This header file is included from linker scatter file as well, where only a
@@ -38,21 +61,26 @@
*/
/* Size of a Secure and of a Non-secure image */
-#define FLASH_S_PARTITION_SIZE (0x40000) /* S partition: 256 kB*/
-#define FLASH_NS_PARTITION_SIZE (0x40000) /* NS partition: 256 kB*/
+#ifdef BL2
+#define FLASH_S_PARTITION_SIZE (0x28000) /* S partition: 160 KB */
+#define FLASH_NS_PARTITION_SIZE (0x18000) /* NS partition: 96 KB */
+#else
+#define FLASH_S_PARTITION_SIZE (0x40000) /* S partition: 256 KB*/
+#define FLASH_NS_PARTITION_SIZE (0x40000) /* NS partition: 256 KB*/
+#endif /* BL2 */
#define FLASH_MAX_PARTITION_SIZE ((FLASH_S_PARTITION_SIZE > \
FLASH_NS_PARTITION_SIZE) ? \
FLASH_S_PARTITION_SIZE : \
FLASH_NS_PARTITION_SIZE)
/* Sector size of the embedded flash hardware (erase/program) */
-#define FLASH_AREA_IMAGE_SECTOR_SIZE (512) /* 512 B. Flash memory program/erase operations have a page granularity. */
+#define FLASH_AREA_IMAGE_SECTOR_SIZE (512) /* 512 B. Flash memory program/erase operations have a page granularity. */
-/* FLASH size */
-#define FLASH_TOTAL_SIZE (0x00098000) /* 608 kB. The last 17 pages (10KB) are reserved on the 640KB flash. Sub-regiuon is 32KB, so avalble for application is 608KB. */
+/* Flash size, same as FLASH0_SIZE */
+#define FLASH_TOTAL_SIZE (0x00098000) /* 608 KB. The last 17 pages (10 KB) are reserved on the 640 KB flash. Sub-region is 32KB, so available for application is 608 KB. */
/* Flash layout info for BL2 bootloader */
-#define FLASH_BASE_ADDRESS (0x00000000)
+#define FLASH_BASE_ADDRESS (0x00000000)
#ifdef BL2
/* Offset and size definitions of the flash partitions that are handled by the
@@ -61,7 +89,7 @@
* swapping.
*/
#define FLASH_AREA_BL2_OFFSET (0x0)
-#define FLASH_AREA_BL2_SIZE (0x20000) /* 128 KB */
+#define FLASH_AREA_BL2_SIZE (0x8000) /* 32 KB */
#if !defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1)
/* Secure + Non-secure image primary slot */
@@ -74,8 +102,8 @@
#define FLASH_AREA_2_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE)
#define FLASH_AREA_2_SIZE (FLASH_S_PARTITION_SIZE + \
FLASH_NS_PARTITION_SIZE)
-/* Not used, only the Non-swapping firmware upgrade operation
- * is supported on Musca-B1.
+/* Not used (scratch area), the 'Swap' firmware upgrade operation is not
+ * supported on LPC55S69.
*/
#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_2_ID + 1)
#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE)
@@ -101,8 +129,8 @@
#define FLASH_AREA_3_ID (FLASH_AREA_2_ID + 1)
#define FLASH_AREA_3_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE)
#define FLASH_AREA_3_SIZE (FLASH_NS_PARTITION_SIZE)
-/* Not used, only the Non-swapping firmware upgrade operation
- * is supported on Musca-B1.
+/* Not used (scratch area), the 'Swap' firmware upgrade operation is not
+ * supported on LPC55S69.
*/
#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_3_ID + 1)
#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_3_OFFSET + FLASH_AREA_3_SIZE)
@@ -114,15 +142,14 @@
#error "Only MCUBOOT_IMAGE_NUMBER 1 and 2 are supported!"
#endif /* MCUBOOT_IMAGE_NUMBER */
-/* Not used, only the Non-swapping firmware upgrade operation
- * is supported on Musca-B1. The maximum number of status entries
- * supported by the bootloader.
+/* Not used, the 'Swap' firmware upgrade operation is not supported on LPC55S69.
+ * The maximum number of status entries supported by the bootloader.
*/
-#define MCUBOOT_STATUS_MAX_ENTRIES (0)
+#define MCUBOOT_STATUS_MAX_ENTRIES (0)
-#else
+#else /* NO BL2 */
-/* Secure + Non-secure image primary slot */
+/* Secure + Non-secure image slot */
#define FLASH_AREA_0_ID (1)
#define FLASH_AREA_0_OFFSET (0x0)
#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE + \
@@ -138,9 +165,9 @@
* FLASH_NV_COUNTERS_AREA_OFFSET point to offsets in flash, but reads and writes
* to these addresses are redirected to Code SRAM by Driver_Flash.c.
*/
-#define FLASH_PS_AREA_OFFSET (FLASH_AREA_SCRATCH_OFFSET + \
+#define FLASH_PS_AREA_OFFSET (FLASH_AREA_SCRATCH_OFFSET + \
FLASH_AREA_SCRATCH_SIZE)
-#define FLASH_PS_AREA_SIZE (0x2000) /* 8 KB */
+#define FLASH_PS_AREA_SIZE (0x2000) /* 8 KB */
/* Internal Trusted Storage (ITS) Service definitions */
#define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + \
@@ -222,7 +249,7 @@
/* NV Counters definitions */
#define TFM_NV_COUNTERS_AREA_ADDR FLASH_NV_COUNTERS_AREA_OFFSET
-#define TFM_NV_COUNTERS_AREA_SIZE FLASH_NV_COUNTERS_AREA_SIZE
+#define TFM_NV_COUNTERS_AREA_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE
#define TFM_NV_COUNTERS_SECTOR_ADDR FLASH_NV_COUNTERS_AREA_OFFSET
#define TFM_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE