Build: IAR support
- This patch contains IAR specific changes to a few source files,
mostly #pragmas to allow calling external functions from inline.
- Startup code and linker scripts
- cmake files
- cmsis file for the IAR compiler
Other targets are added in later commits
There are still lots of warnings generated for non-standard C, which
I plan to address in later updates
- Cleaned out some dead definitions in the common linker script in
preparation for psoc64 integration.
- Made sure that .rodata from tfm_its_secure_api.o is placed in
TFM_UNPRIV_CODE, which otherwised caused a memory management fault
in test TFM_ITS_TEST_2023 when compiled without optimization.
- Added dummy initializers to tfm_secure_irq_handlers.inc.template to
avoid illegal empty arrays.
- Reworked the iovec_args_t struct handling in tfm_func_api.c, which
was causing runtime errors when compiled with optimization.
According to the compiler developers the old implemetation is
illegal, you are not allowed to use the address of a scalar as an
address outside of that scalar.
- Added conditional around ".syntax unified" in tfm_nspm_ipc.c.
- Added "template" attribute for the IAR linker script in
tfm_generated_file_list.yaml.
- Cleaned up some indentation and tab/space issues
Change-Id: I8599d461f62194bc734e472a28d7111ba3b5046a
Signed-off-by: TTornblom <thomas.tornblom@iar.com>
diff --git a/CommonConfig.cmake b/CommonConfig.cmake
index aea576a..0763abc 100644
--- a/CommonConfig.cmake
+++ b/CommonConfig.cmake
@@ -17,7 +17,7 @@
if(NOT DEFINED COMPILER)
message(FATAL_ERROR "ERROR: COMPILER is not set in command line")
-elseif((NOT ${COMPILER} STREQUAL "ARMCLANG") AND (NOT ${COMPILER} STREQUAL "GNUARM"))
+elseif((NOT ${COMPILER} STREQUAL "ARMCLANG") AND (NOT ${COMPILER} STREQUAL "GNUARM") AND (NOT ${COMPILER} STREQUAL "IARARM"))
message(FATAL_ERROR "ERROR: Compiler \"${COMPILER}\" is not supported.")
endif()
@@ -82,7 +82,11 @@
# core acts as secure core in multi-core scenario.
# leave CMSE_FLAGS undefined
else()
- set (CMSE_FLAGS "-mcmse")
+ if(${COMPILER} STREQUAL "IARARM")
+ set (CMSE_FLAGS "--cmse")
+ else()
+ set (CMSE_FLAGS "-mcmse")
+ endif()
# Clear multi-core test setting
set (TFM_MULTI_CORE_TEST OFF)
@@ -126,6 +130,27 @@
#wchar, so the warning can be suppressed.
embedded_set_target_link_flags(TARGET ${tgt} FLAGS -Wl,-check-sections,-fatal-warnings,--gc-sections,--no-wchar-size-warning,--print-memory-usage --entry=Reset_Handler --specs=nano.specs)
endfunction()
+elseif(${COMPILER} STREQUAL "IARARM")
+ #Use any IARARM version found on PATH. Note: Only versions supported by the
+ #build system will work. A file cmake/Common/CompilerIARARMXY.cmake
+ #must be present with a matching version.
+ include("Common/FindIARARM")
+ include("Common/${IARARM_MODULE}")
+
+ set (COMMON_COMPILE_FLAGS -e --dlib_config=full --vla --silent -DNO_TYPEOF ${CMSE_FLAGS})
+ ##Shared compiler and linker settings.
+ function(config_setting_shared_compiler_flags tgt)
+ embedded_set_target_compile_flags(TARGET ${tgt} LANGUAGE C FLAGS ${COMMON_COMPILE_FLAGS} "-DImage$$= " "-DLoad$$LR$$= " "-D$$ZI$$Base=$$Base" "-D$$ZI$$Limit=$$Limit" "-D$$RO$$Base=$$Base" "-D$$RO$$Limit=$$Limit" "-D$$RW$$Base=$$Base" "-D$$RW$$Limit=$$Limit" "-D_DATA$$RW$$Base=_DATA$$Base" "-D_DATA$$RW$$Limit=_DATA$$Limit" "-D_DATA$$ZI$$Base=_DATA$$Base" "-D_DATA$$ZI$$Limit=_DATA$$Limit" "-D_STACK$$ZI$$Base=_STACK$$Base" "-D_STACK$$ZI$$Limit=_STACK$$Limit" )
+ endfunction()
+
+ ##Shared linker settings.
+ function(config_setting_shared_linker_flags tgt)
+ #--no-wchar-size-warning flag is added because TF-M sources are compiled
+ #with short wchars, however the standard library is compiled with normal
+ #wchar, and this generates linker time warnings. TF-M code does not use
+ #wchar, so the warning can be suppressed.
+ embedded_set_target_link_flags(TARGET ${tgt} FLAGS --silent --semihosting --redirect __write=__write_buffered)
+ endfunction()
endif()
#Create a string from the compile flags list, so that it can be used later
diff --git a/bl2/ext/mcuboot/bl2_main.c b/bl2/ext/mcuboot/bl2_main.c
index 62b93d9..391a996 100644
--- a/bl2/ext/mcuboot/bl2_main.c
+++ b/bl2/ext/mcuboot/bl2_main.c
@@ -71,10 +71,16 @@
* - There are secrets in the memory: KDF parameter, symmetric key,
* manufacturer sensitive code/data, etc.
*/
+#if defined(__ICCARM__)
+#pragma required = boot_clear_bl2_ram_area
+#endif
+
__attribute__((naked)) void boot_jump_to_next_image(uint32_t reset_handler_addr)
{
__ASM volatile(
+#if !defined(__ICCARM__)
".syntax unified \n"
+#endif
"mov r7, r0 \n"
"bl boot_clear_bl2_ram_area \n" /* Clear RAM before jump */
"movs r0, #0 \n" /* Clear registers: R0-R12, */
diff --git a/cmake/Common/CompilerDetermineASM.cmake b/cmake/Common/CompilerDetermineASM.cmake
index 7bef05d..e38bce5 100644
--- a/cmake/Common/CompilerDetermineASM.cmake
+++ b/cmake/Common/CompilerDetermineASM.cmake
@@ -1,5 +1,5 @@
#-------------------------------------------------------------------------------
-# Copyright (c) 2019, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2020, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -22,6 +22,8 @@
set(ARM_TOOLCHAIN_FILE "Compiler/ARMCC-ASM")
elseif (_ASM_COMPILER_NAME MATCHES "^.*gcc(\\.exe)?$")
set(ARM_TOOLCHAIN_FILE "Compiler/GNUARM-ASM")
+elseif (_ASM_COMPILER_NAME MATCHES "^.*iasmarm(\\.exe)?$")
+ set(ARM_TOOLCHAIN_FILE "Compiler/IARARM-ASM")
else()
message(FATAL_ERROR "ASM Compiler executable ${_ASM_COMPILER_NAME} is \
unknown. Please add needed settings to ${CMAKE_CURRENT_LIST_FILE}")
diff --git a/cmake/Common/CompilerDetermineC.cmake b/cmake/Common/CompilerDetermineC.cmake
index a429120..7d363d7 100644
--- a/cmake/Common/CompilerDetermineC.cmake
+++ b/cmake/Common/CompilerDetermineC.cmake
@@ -1,5 +1,5 @@
#-------------------------------------------------------------------------------
-# Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+# Copyright (c) 2017-2020, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -28,8 +28,8 @@
set(CMAKE_C_COMPILER_ID "GNUARM" CACHE INTERNAL "C compiler ID" FORCE)
set(ARM_TOOLCHAIN_FILE "Compiler/GNUARM-C")
elseif (_C_COMPILER_NAME MATCHES "^.*iccarm(\\.exe)?$")
- set(CMAKE_C_COMPILER_ID "IAR" CACHE INTERNAL "C compiler ID" FORCE)
- set(ARM_TOOLCHAIN_FILE "Compiler/IAR-C")
+ set(CMAKE_C_COMPILER_ID "IARARM" CACHE INTERNAL "C compiler ID" FORCE)
+ set(ARM_TOOLCHAIN_FILE "Compiler/IARARM-C")
else()
message(FATAL_ERROR "C Compiler executable ${_C_COMPILER_NAME} is unknown.\
Please add needed settings to ${CMAKE_CURRENT_LIST_FILE}")
diff --git a/cmake/Common/CompilerDetermineCXX.cmake b/cmake/Common/CompilerDetermineCXX.cmake
index 6d1f142..bf23367 100644
--- a/cmake/Common/CompilerDetermineCXX.cmake
+++ b/cmake/Common/CompilerDetermineCXX.cmake
@@ -1,5 +1,5 @@
#-------------------------------------------------------------------------------
-# Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+# Copyright (c) 2017-2020, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -27,8 +27,8 @@
set(CMAKE_CXX_COMPILER_ID "GNUARM" CACHE INTERNAL "C++ compiler ID" FORCE)
set(ARM_TOOLCHAIN_FILE "Compiler/GNUARM-CXX")
elseif (_CXX_COMPILER_NAME MATCHES "^.*iccarm(\\.exe)?$")
- set(CMAKE_CXX_COMPILER_ID "IAR" CACHE INTERNAL "C++ compiler ID" FORCE)
- set(ARM_TOOLCHAIN_FILE "Compiler/IAR-CXX")
+ set(CMAKE_CXX_COMPILER_ID "IARARM" CACHE INTERNAL "C++ compiler ID" FORCE)
+ set(ARM_TOOLCHAIN_FILE "Compiler/IARARM-CXX")
else()
message(FATAL_ERROR "C++ Compiler executable ${_C_COMPILER_NAME} is \
unknown. Please add needed settings to ${CMAKE_CURRENT_LIST_FILE}")
diff --git a/cmake/Common/CompilerIarArm842.cmake b/cmake/Common/CompilerIarArm842.cmake
new file mode 100644
index 0000000..7d5c422
--- /dev/null
+++ b/cmake/Common/CompilerIarArm842.cmake
@@ -0,0 +1,80 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2018-2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+#This file contains settings to specify how ICCARM shall be used
+
+#Include some dependencies
+Include(Common/CompilerIarArmCommon)
+Include(Common/Utils)
+
+check_iccarm_input_vars("8.42")
+
+if(NOT DEFINED ARM_CPU_ARCHITECTURE)
+ set(_NO_ARM_CPU_ARCHITECTURE true)
+elseif (${ARM_CPU_ARCHITECTURE} STREQUAL "ARMv8-M.BASE")
+ string_append_unique_item(STRING CMAKE_C_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M23")
+ string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M23")
+ string_append_unique_item(STRING CMAKE_ASM_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M23")
+ string_append_unique_item(STRING CMAKE_LINK_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M23")
+elseif(${ARM_CPU_ARCHITECTURE} STREQUAL "ARMv8-M.MAIN")
+ string_append_unique_item(STRING CMAKE_C_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M33.no_dsp")
+ string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M33.no_dsp")
+ string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M33.no_dsp")
+ string_append_unique_item(STRING CMAKE_LINK_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M33.no_dsp")
+elseif(${ARM_CPU_ARCHITECTURE} STREQUAL "ARMv7-M")
+ string_append_unique_item(STRING CMAKE_C_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M4")
+ string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M4")
+ string_append_unique_item(STRING CMAKE_ASM_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M4")
+ string_append_unique_item(STRING CMAKE_LINK_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M4")
+elseif(${ARM_CPU_ARCHITECTURE} STREQUAL "ARMv6-M")
+ string_append_unique_item(STRING CMAKE_C_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M0+")
+ string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M0+")
+ string_append_unique_item(STRING CMAKE_ASM_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M0+")
+ string_append_unique_item(STRING CMAKE_LINK_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M0+")
+else()
+ message(FATAL_ERROR "Unknown or unsupported ARM cpu architecture setting.")
+endif()
+
+#Prefer architecture definition over cpu type.
+if(NOT DEFINED ARM_CPU_ARCHITECTURE)
+ if(NOT DEFINED ARM_CPU_TYPE)
+ string_append_unique_item(_NO_ARM_CPU_TYPE true)
+ elseif(${ARM_CPU_TYPE} STREQUAL "Cortex-M3")
+ string_append_unique_item (CMAKE_C_FLAGS_CPU "--cpu Cortex-M3")
+ string_append_unique_item (CMAKE_CXX_FLAGS_CPU "--cpu Cortex-M3")
+ string_append_unique_item (CMAKE_ASM_FLAGS_CPU "--cpu Cortex-M3")
+ string_append_unique_item (CMAKE_LINK_FLAGS_CPU "--cpu Cortex-M3")
+ elseif(${ARM_CPU_TYPE} STREQUAL "Cortex-M33")
+ string_append_unique_item (CMAKE_C_FLAGS_CPU "--cpu Cortex-M33.no_dsp")
+ string_append_unique_item (CMAKE_CXX_FLAGS_CPU "--cpu Cortex-M33.no_dsp")
+ string_append_unique_item (CMAKE_ASM_FLAGS_CPU "--cpu Cortex-M33.no_dsp")
+ string_append_unique_item (CMAKE_LINK_FLAGS_CPU "--cpu Cortex-M3.no_dsp3")
+ elseif(${ARM_CPU_TYPE} STREQUAL "Cortex-M23")
+ string_append_unique_item (CMAKE_C_FLAGS_CPU "--cpu Cortex-M23")
+ string_append_unique_item (CMAKE_CXX_FLAGS_CPU "--cpu Cortex-M23")
+ string_append_unique_item (CMAKE_ASM_FLAGS_CPU "--cpu Cortex-M23")
+ string_append_unique_item (CMAKE_LINK_FLAGS_CPU "--cpu Cortex-M23")
+ elseif(${ARM_CPU_TYPE} STREQUAL "Cortex-M4")
+ string_append_unique_item (STRING CMAKE_C_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M4")
+ string_append_unique_item (STRING CMAKE_CXX_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M4")
+ string_append_unique_item (STRING CMAKE_ASM_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M4")
+ string_append_unique_item (STRING CMAKE_LINK_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M4")
+ set(ARM_CPU_ARCHITECTURE "ARMv7-M")
+ elseif (${ARM_CPU_TYPE} STREQUAL "Cortex-M0p")
+ string_append_unique_item (STRING CMAKE_C_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M0+")
+ string_append_unique_item (STRING CMAKE_CXX_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M0+")
+ string_append_unique_item (STRING CMAKE_ASM_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M0+")
+ string_append_unique_item (STRING CMAKE_LINK_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M0+")
+ set(ARM_CPU_ARCHITECTURE "ARMv6-M")
+ else()
+ message(FATAL_ERROR "Unknown ARM cpu setting.")
+ endif()
+endif()
+
+if (_NO_ARM_CPU_TYPE AND _NO_ARM_CPU_ARCHITECTURE)
+ message(FATAL_ERROR "Can not set CPU specific compiler flags: neither the ARM CPU type nor the architecture is set.")
+endif()
diff --git a/cmake/Common/CompilerIarArm850.cmake b/cmake/Common/CompilerIarArm850.cmake
new file mode 100644
index 0000000..bf40e64
--- /dev/null
+++ b/cmake/Common/CompilerIarArm850.cmake
@@ -0,0 +1,80 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2018-2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+#This file contains settings to specify how ICCARM shall be used
+
+#Include some dependencies
+Include(Common/CompilerIarArmCommon)
+Include(Common/Utils)
+
+check_iccarm_input_vars("8.50")
+
+if(NOT DEFINED ARM_CPU_ARCHITECTURE)
+ set(_NO_ARM_CPU_ARCHITECTURE true)
+elseif (${ARM_CPU_ARCHITECTURE} STREQUAL "ARMv8-M.BASE")
+ string_append_unique_item(STRING CMAKE_C_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M23")
+ string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M23")
+ string_append_unique_item(STRING CMAKE_ASM_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M23")
+ string_append_unique_item(STRING CMAKE_LINK_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M23")
+elseif(${ARM_CPU_ARCHITECTURE} STREQUAL "ARMv8-M.MAIN")
+ string_append_unique_item(STRING CMAKE_C_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M33.no_dsp")
+ string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M33.no_dsp")
+ string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M33.no_dsp")
+ string_append_unique_item(STRING CMAKE_LINK_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M33.no_dsp")
+elseif(${ARM_CPU_ARCHITECTURE} STREQUAL "ARMv7-M")
+ string_append_unique_item(STRING CMAKE_C_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M4")
+ string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M4")
+ string_append_unique_item(STRING CMAKE_ASM_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M4")
+ string_append_unique_item(STRING CMAKE_LINK_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M4")
+elseif(${ARM_CPU_ARCHITECTURE} STREQUAL "ARMv6-M")
+ string_append_unique_item(STRING CMAKE_C_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M0+")
+ string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M0+")
+ string_append_unique_item(STRING CMAKE_ASM_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M0+")
+ string_append_unique_item(STRING CMAKE_LINK_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M0+")
+else()
+ message(FATAL_ERROR "Unknown or unsupported ARM cpu architecture setting.")
+endif()
+
+#Prefer architecture definition over cpu type.
+if(NOT DEFINED ARM_CPU_ARCHITECTURE)
+ if(NOT DEFINED ARM_CPU_TYPE)
+ string_append_unique_item(_NO_ARM_CPU_TYPE true)
+ elseif(${ARM_CPU_TYPE} STREQUAL "Cortex-M3")
+ string_append_unique_item (CMAKE_C_FLAGS_CPU "--cpu Cortex-M3")
+ string_append_unique_item (CMAKE_CXX_FLAGS_CPU "--cpu Cortex-M3")
+ string_append_unique_item (CMAKE_ASM_FLAGS_CPU "--cpu Cortex-M3")
+ string_append_unique_item (CMAKE_LINK_FLAGS_CPU "--cpu Cortex-M3")
+ elseif(${ARM_CPU_TYPE} STREQUAL "Cortex-M33")
+ string_append_unique_item (CMAKE_C_FLAGS_CPU "--cpu Cortex-M33.no_dsp")
+ string_append_unique_item (CMAKE_CXX_FLAGS_CPU "--cpu Cortex-M33.no_dsp")
+ string_append_unique_item (CMAKE_ASM_FLAGS_CPU "--cpu Cortex-M33.no_dsp")
+ string_append_unique_item (CMAKE_LINK_FLAGS_CPU "--cpu Cortex-M3.no_dsp3")
+ elseif(${ARM_CPU_TYPE} STREQUAL "Cortex-M23")
+ string_append_unique_item (CMAKE_C_FLAGS_CPU "--cpu Cortex-M23")
+ string_append_unique_item (CMAKE_CXX_FLAGS_CPU "--cpu Cortex-M23")
+ string_append_unique_item (CMAKE_ASM_FLAGS_CPU "--cpu Cortex-M23")
+ string_append_unique_item (CMAKE_LINK_FLAGS_CPU "--cpu Cortex-M23")
+ elseif(${ARM_CPU_TYPE} STREQUAL "Cortex-M4")
+ string_append_unique_item (STRING CMAKE_C_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M4")
+ string_append_unique_item (STRING CMAKE_CXX_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M4")
+ string_append_unique_item (STRING CMAKE_ASM_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M4")
+ string_append_unique_item (STRING CMAKE_LINK_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M4")
+ set(ARM_CPU_ARCHITECTURE "ARMv7-M")
+ elseif (${ARM_CPU_TYPE} STREQUAL "Cortex-M0p")
+ string_append_unique_item (STRING CMAKE_C_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M0+")
+ string_append_unique_item (STRING CMAKE_CXX_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M0+")
+ string_append_unique_item (STRING CMAKE_ASM_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M0+")
+ string_append_unique_item (STRING CMAKE_LINK_FLAGS_CPU KEY "--cpu" VAL "--cpu Cortex-M0+")
+ set(ARM_CPU_ARCHITECTURE "ARMv6-M")
+ else()
+ message(FATAL_ERROR "Unknown ARM cpu setting.")
+ endif()
+endif()
+
+if (_NO_ARM_CPU_TYPE AND _NO_ARM_CPU_ARCHITECTURE)
+ message(FATAL_ERROR "Can not set CPU specific compiler flags: neither the ARM CPU type nor the architecture is set.")
+endif()
diff --git a/cmake/Common/CompilerIarArmCommon.cmake b/cmake/Common/CompilerIarArmCommon.cmake
new file mode 100644
index 0000000..78cbdd7
--- /dev/null
+++ b/cmake/Common/CompilerIarArmCommon.cmake
@@ -0,0 +1,275 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2017-2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+#This file contains settings to specify how IARARM shall be used
+
+function(check_iccarm_input_vars MY_VERSION)
+ #Specify where IARARM is
+ if (NOT DEFINED IARARM_PATH)
+ message(FATAL_ERROR "Please set IARARM_PATH to the root directory of the IARARM installation. e.g. set(IARARM_PATH \"C:/Program Files (x86)/IAR Systems/Embedded Workbench ${MY_VERSION}\")")
+ endif()
+
+ STRING(REGEX REPLACE "([0-9]+).([0-9]+).*" "\\1.\\2" _MY_MAJOR_MINOR "${MY_VERSION}")
+ STRING(REGEX REPLACE "([0-9]+).([0-9]+).*" "\\1.\\2" _IARARM_MAJOR_MINOR "${IARARM_VER}")
+
+ #Check iccarm version.
+ if (NOT "${_MY_MAJOR_MINOR}" VERSION_EQUAL "${_IARARM_MAJOR_MINOR}")
+ message(FATAL_ERROR "IARARM version (IARARM_VER=${IARARM_VER}) does not match ${MY_VERSION}")
+ endif()
+
+ if (NOT DEFINED ARM_CPU_ARCHITECTURE AND NOT DEFINED ARM_CPU_TYPE)
+ message(FATAL_ERROR "ARM_CPU_TYPE and ARM_CPU_ARCHITECTURE is not defined! Please include the CPU specific config file before this one.")
+ endif()
+
+endfunction()
+
+message(STATUS "Using IARARM compiler package v${IARARM_VER} from ${IARARM_PATH}")
+
+
+#Tell cmake which compiler we use
+if (EXISTS "c:/")
+ set (CMAKE_C_COMPILER "${IARARM_PATH}/bin/iccarm.exe")
+ set (CMAKE_CXX_COMPILER "${IARARM_PATH}/bin/iccarm.exe")
+ set (CMAKE_ASM_COMPILER "${IARARM_PATH}/bin/iasmarm.exe")
+else()
+ set (CMAKE_C_COMPILER "${IARARM_PATH}/bin/iccarm")
+ set (CMAKE_CXX_COMPILER "${IARARM_PATH}/bin/iccarm")
+ set (CMAKE_ASM_COMPILER "${IARARM_PATH}/bin/iasmarm")
+endif()
+
+if("CXX" IN_LIST languages)
+ set(CMAKE_CXX_COMPILER_ID "IARARM" CACHE INTERNAL "CXX compiler ID" FORCE)
+ include(Compiler/IARARM-CXX)
+endif()
+
+if("C" IN_LIST languages)
+ set(CMAKE_C_COMPILER_ID "IARARM" CACHE INTERNAL "C compiler ID" FORCE)
+ include(Compiler/IARARM-C)
+endif()
+
+function(compiler_get_preinclude_option_string INCLUDE RES)
+ set(${RES} "--preinclude ${INCLUDE}" PARENT_SCOPE)
+endfunction()
+
+function(compiler_set_preinclude_file)
+ #Option (on/off) arguments.
+ set( _OPTIONS_ARGS GLOBAL)
+ #Single option arguments.
+ set( _ONE_VALUE_ARGS INCLUDE)
+ #List arguments
+ set( _MULTI_VALUE_ARGS TARGETS FILES)
+ cmake_parse_arguments(_MY_PARAMS "${_OPTIONS_ARGS}" "${_ONE_VALUE_ARGS}" "${_MULTI_VALUE_ARGS}" ${ARGN} )
+ if(NOT DEFINED _MY_PARAMS)
+ message(FATAL_ERROR "compiler_set_preinclude_file: missing mandatory parameter INCLUDE.")
+ endif()
+ compiler_get_preinclude_option_string(${INCLUDE} _OPTION_STRING)
+ #If include is to be set globally, we ignore TARGETS and FILES
+ if(_MY_PARAMS_GLOBAL)
+ set_property(DIRECTORY ${CMAKE_SOURCE_DIR} APPEND PROPERTY COMPILE_OPTIONS "${_OPTION_STRING}")
+ else()
+ #If GLOBAL was not passed, then either TARGETS or FILES must be present
+ if(NOT DEFINED _MY_PARAM_TARGETS AND NOT DEFINED _MY_PARAM_FILES)
+ message(FATAL_ERROR "compiler_set_preinclude_file: missing mandatory parameter. Either TARGETS and/or FILES must be specified.")
+ endif()
+ #Iterate over targets. Note: call embedded_set_target_compile_flags to
+ #allow the target to be defined after this function call. This helps
+ #modularisation
+ foreach(_TGT IN_LISTS _MY_PARAM_TARGETS)
+ embedded_set_target_compile_flags(TARGET ${_TGT} LANGUAGE "C" FLAGS "${_OPTION_STRING}")
+ endforeach()
+ #Iterate over files
+ foreach(_FILE IN_LISTS _MY_PARAM_FILES)
+ set_property(FILE ${_FILE} APPEND PROPERTY COMPILE_OPTIONS "${_OPTION_STRING}")
+ endforeach()
+ endif()
+endfunction()
+
+function(compiler_set_linkercmdfile)
+ set( _OPTIONS_ARGS ) #Option (on/off) arguments.
+ set( _ONE_VALUE_ARGS TARGET PATH) #Single option arguments.
+ set( _MULTI_VALUE_ARGS DEFINES INCLUDES) #List arguments
+ cmake_parse_arguments(_MY_PARAMS "${_OPTIONS_ARGS}" "${_ONE_VALUE_ARGS}" "${_MULTI_VALUE_ARGS}" ${ARGN} )
+
+ #Check passed parameters
+ if(NOT _MY_PARAMS_TARGET)
+ message(FATAL_ERROR "compiler_set_linkercmdfile: mandatory parameter 'TARGET' is missing.")
+ endif()
+ if (NOT TARGET ${_MY_PARAMS_TARGET})
+ message(FATAL_ERROR "compiler_set_linkercmdfile: value of parameter 'TARGET' is invalid.")
+ endif()
+
+ if(NOT _MY_PARAMS_PATH)
+ message(FATAL_ERROR "compiler_set_linkercmdfile: mandatory parameter 'PATH' is missing.")
+ endif()
+ set(_FILE_PATH ${_MY_PARAMS_PATH})
+
+ #Create additional target if linker script needs to be pre-processed.
+ if (_MY_PARAMS_DEFINES OR _MY_PARAMS_INCLUDES)
+ #Name of pre-processed linker script file.
+ set(FINAL_LD_FILE_NAME "${CMAKE_CURRENT_BINARY_DIR}/${_MY_PARAMS_TARGET}.icf.i")
+ #Name of the target doing the pre-processing
+ set(LD_PP_TARGET_NAME "${_MY_PARAMS_TARGET}_ldpp")
+ compiler_preprocess_file(SRC ${_MY_PARAMS_PATH}
+ DST ${FINAL_LD_FILE_NAME}
+ TARGET_PREFIX ${_MY_PARAMS_TARGET}
+ BEFORE_TARGET ${_MY_PARAMS_TARGET}
+ DEFINES ${_MY_PARAMS_DEFINES}
+ INCLUDES ${_MY_PARAMS_INCLUDES})
+
+ #Tell cmake to delete the intermediate linker script when the clean rule is executed.
+ get_directory_property(_ADDITIONAL_MAKE_CLEAN_FILES DIRECTORY "./" ADDITIONAL_MAKE_CLEAN_FILES)
+ set_directory_properties(PROPERTY ADDITIONAL_MAKE_CLEAN_FILES "${_ADDITIONAL_MAKE_CLEAN_FILES} ${FINAL_LD_FILE_NAME}")
+ #Set the path to linker script point to the intermediate file.
+ set(_FILE_PATH ${FINAL_LD_FILE_NAME})
+ endif()
+
+ #Note: the space before the option is important!
+ set_property(TARGET ${_MY_PARAMS_TARGET} APPEND_STRING PROPERTY LINK_FLAGS " ${_FLAGS} --config=${_FILE_PATH}")
+ set_property(TARGET ${_MY_PARAMS_TARGET} APPEND PROPERTY LINK_DEPENDS ${_FILE_PATH})
+ #Tell cmake .map files shall be removed when project is cleaned (make clean)
+ get_filename_component(_TARGET_BASE_NAME ${_MY_PARAMS_TARGET} NAME_WE)
+ get_directory_property(_ADDITIONAL_MAKE_CLEAN_FILES DIRECTORY "./" ADDITIONAL_MAKE_CLEAN_FILES)
+ set_directory_properties(PROPERTY ADDITIONAL_MAKE_CLEAN_FILES "${_ADDITIONAL_MAKE_CLEAN_FILES} ${_TARGET_BASE_NAME}.map")
+endfunction()
+
+function(compiler_set_cmse_output TARGET FILE_PATH)
+ #Note: the space before the option is important!
+ set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " --import_cmse_lib_out=${FILE_PATH}")
+ #Tell cmake cmse output is a generated object file.
+ SET_SOURCE_FILES_PROPERTIES("${FILE_PATH}" PROPERTIES EXTERNAL_OBJECT true GENERATED true)
+ #Tell cmake cmse output shall be removed by clean target.
+ get_directory_property(_ADDITIONAL_MAKE_CLEAN_FILES DIRECTORY "./" ADDITIONAL_MAKE_CLEAN_FILES)
+ set_directory_properties(PROPERTY ADDITIONAL_MAKE_CLEAN_FILES "${_ADDITIONAL_MAKE_CLEAN_FILES} ${FILE_PATH}")
+endfunction()
+
+function(compiler_merge_library)
+ set( _OPTIONS_ARGS ) #Option (on/off) arguments.
+ set( _ONE_VALUE_ARGS DEST) #Single option arguments.
+ set( _MULTI_VALUE_ARGS LIBS) #List arguments
+ cmake_parse_arguments(_MY_PARAMS "${_OPTIONS_ARGS}" "${_ONE_VALUE_ARGS}" "${_MULTI_VALUE_ARGS}" ${ARGN} )
+
+ #Check passed parameters
+ if(NOT _MY_PARAMS_DEST)
+ message(FATAL_ERROR "compiler_merge_library: no destination target specified. Please see the DEST parameter.")
+ endif()
+ #Check if destination is a library
+ get_target_property(_tmp ${_MY_PARAMS_DEST} TYPE)
+ if(NOT "${_tmp}" STREQUAL "STATIC_LIBRARY")
+ message(FATAL_ERROR "compiler_merge_library: parameter DEST must be a static library target.")
+ endif()
+ set(_DEST ${_MY_PARAMS_DEST})
+
+ if(NOT _MY_PARAMS_LIBS)
+ message(FATAL_ERROR "compiler_merge_library: no source libraries specified. Please see the LIBS parameter.")
+ endif()
+ set(_LIBS ${_MY_PARAMS_LIBS})
+
+ ##Find the cmake script doing the merge.
+ find_file(_MERGE_SCRIPT "IARArMerge.cmake" PATHS ${CMAKE_MODULE_PATH} PATH_SUFFIXES Common NO_DEFAULT_PATH)
+
+ #Now add a custom command for each source library to our custom target to
+ #merge into the destination.
+ foreach(SRC_LIB ${_LIBS})
+ get_filename_component(_SRC_LIB_NAME "${SRC_LIB}" NAME)
+ add_custom_command(TARGET ${_DEST} POST_BUILD
+ COMMAND ${CMAKE_COMMAND} -DCMAKE_AR=${CMAKE_AR} -DSOURCE=${SRC_LIB} -DDESTINATION=$<TARGET_FILE:${_DEST}> -P ${_MERGE_SCRIPT}
+ COMMENT "\t\tmerging objects from ${_SRC_LIB_NAME}")
+ endforeach()
+endfunction()
+
+function(compiler_generate_binary_output TARGET)
+ add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_IARARM_IELFTOOL} ARGS --silent --bin $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin)
+endfunction()
+
+# Function for creating a new target that preprocesses a .c file
+#INPUTS:
+# SRC - (mandatory) - file to be preprocessed
+# DST - (mandatory) - output file for the preprocessing
+# TARGET_PREFIX - (optional) - prefix for the target that this function creates and which manages the preprocessing
+# BEFORE_TARGET - (optional) - target which is dependent on the preprocessing target in the below function
+# DEFINES - (optional) - additional command line switches from macro definitions for preprocessing
+# INCLUDES - (optional) - additional command line switches from include paths for preprocessing
+function(compiler_preprocess_file)
+ #Option (on/off) arguments.
+ set( _OPTIONS_ARGS)
+ #Single option arguments.
+ set( _ONE_VALUE_ARGS SRC DST TARGET_PREFIX BEFORE_TARGET)
+ #List arguments
+ set( _MULTI_VALUE_ARGS DEFINES INCLUDES)
+ cmake_parse_arguments(_MY_PARAMS "${_OPTIONS_ARGS}" "${_ONE_VALUE_ARGS}" "${_MULTI_VALUE_ARGS}" ${ARGN} )
+
+ #Check passed parameters
+ if(NOT DEFINED _MY_PARAMS_SRC)
+ message(FATAL_ERROR "compiler_preprocess_file: mandatory parameter 'SRC' is missing.")
+ endif()
+
+ if(NOT DEFINED _MY_PARAMS_DST)
+ message(FATAL_ERROR "compiler_preprocess_file: mandatory parameter 'DST' is missing.")
+ endif()
+
+ if(DEFINED _MY_PARAMS_BEFORE_TARGET)
+ if(NOT TARGET ${_MY_PARAMS_BEFORE_TARGET})
+ message(FATAL_ERROR "compiler_preprocess_file: optional parameter 'BEFORE_TARGET' is not target.")
+ endif()
+ endif()
+
+ #Compose additional command line switches from macro definitions.
+ set(_FLAGS "")
+ if (_MY_PARAMS_DEFINES)
+ foreach(_DEFINE IN LISTS _MY_PARAMS_DEFINES)
+ list(APPEND _FLAGS "-D${_DEFINE}")
+ endforeach()
+ endif()
+
+ #Compose additional command line switches from include paths.
+ if (_MY_PARAMS_INCLUDES)
+ foreach(_INCLUDE IN LISTS _MY_PARAMS_INCLUDES)
+ list(APPEND _FLAGS "-I${_INCLUDE}")
+ endforeach()
+ endif()
+
+ #The compiler flag might contain leading spaces which can fail the preprocess operation, these are removed
+ STRING(STRIP ${CMAKE_C_FLAGS_CPU} _MY_TEMP_CMAKE_C_FLAGS_CPU)
+ #If a string contains spaces, then it is inserted amongst quotation marks. Furthermore the compiler fails if it is
+ #called with multiple switches included in one quotation mark. If the extra spaces are replaced by semicolons,
+ #then the insertion will be advantageous for the compiler.
+ STRING(REPLACE " " ";" _MY_TEMP2_CMAKE_C_FLAGS_CPU ${_MY_TEMP_CMAKE_C_FLAGS_CPU})
+ set(_LOCAL_CMAKE_C_FLAGS_CPU "")
+ foreach(_C_FLAG IN LISTS _MY_TEMP2_CMAKE_C_FLAGS_CPU)
+ list(APPEND _LOCAL_CMAKE_C_FLAGS_CPU "${_C_FLAG}")
+ endforeach()
+
+ add_custom_command(OUTPUT ${_MY_PARAMS_DST}
+ COMMAND ${CMAKE_C_COMPILER} ${_LOCAL_CMAKE_C_FLAGS_CPU} ${_FLAGS} ${_MY_PARAMS_SRC} --silent --preprocess=ns ${_MY_PARAMS_DST}
+ DEPENDS ${_MY_PARAMS_SRC}
+ COMMENT "Preprocess the ${_MY_PARAMS_SRC} file"
+ )
+
+ set(_MY_TARGET_PREFIX "")
+ if(TARGET ${_MY_PARAMS_TARGET_PREFIX})
+ set(_MY_TARGET_PREFIX "${_MY_PARAMS_TARGET_PREFIX}")
+ endif()
+ #The preprocessing related target name is obtained by indexing the file's name that is to be preprocessed
+ get_filename_component(_MY_FILENAME_TO_BE_INDEXED ${_MY_PARAMS_SRC} NAME_WE)
+ foreach(_SUFFIX RANGE 1 100)
+ if (NOT TARGET ${_MY_TARGET_PREFIX}_pp_${_MY_FILENAME_TO_BE_INDEXED}_${_SUFFIX})
+ set(_PREPROCESS_TARGET_NAME "${_MY_TARGET_PREFIX}_pp_${_MY_FILENAME_TO_BE_INDEXED}_${_SUFFIX}")
+ break()
+ endif()
+ if (_SUFFIX EQUAL 100)
+ message(FATAL_ERROR "You have called 'compiler_preprocess_file' too many times (${_SUFFIX} function calls).")
+ endif()
+ endforeach()
+
+ #Make the original target depend on the new one.
+ if(TARGET ${_MY_PARAMS_BEFORE_TARGET})
+ add_custom_target(${_PREPROCESS_TARGET_NAME} DEPENDS ${_MY_PARAMS_DST})
+ add_dependencies(${_MY_PARAMS_BEFORE_TARGET} ${_PREPROCESS_TARGET_NAME})
+ else()
+ add_custom_target(${_PREPROCESS_TARGET_NAME} ALL DEPENDS ${_MY_PARAMS_DST})
+ endif()
+endfunction()
diff --git a/cmake/Common/FindIARARM.cmake b/cmake/Common/FindIARARM.cmake
new file mode 100644
index 0000000..4ace90b
--- /dev/null
+++ b/cmake/Common/FindIARARM.cmake
@@ -0,0 +1,118 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+#Find the location of the IAR C/C++ compiler.
+#
+# Find iccarm on the specified location or on the PATH and optionally validate its version.
+#
+#Inputs:
+# IARARM_PATH - (optional)- install path of iccarm compiler to use. If not set the
+# compiler on the PATH is used.
+# IARARM_VER - (optional)- version number. If set the module will validate the compiler version.
+#
+#outputs:
+# IARARM_PATH - will be set to the root directory of the compiler. Only set if undefined.
+# IARARM_VER - will be set to the version number found. Only set if undefined.
+# IARARM_MODULE - set to the name of the cmake module to be included for this iccarm version.
+#
+
+#Include some dependencies
+Include(Common/Utils)
+
+#Get the version of iccarm.
+#
+# Execute iccarm and extract its version number for its output.
+#
+#Exmaples:
+# Get the version reported by iccarm at location c:/foo/bin/iccarm to variable VER
+# get_iccarm_version(ICCARM "c:/foo/bin/iccarm" RES VER)
+#
+#INPUTS:
+# ICCARM - (mandatory) - iccarm executable
+# RES - (mandatory) - variable name to put result to
+#
+#OUTPUTS
+# The variable named after "RES" will be set to the version number matches
+#
+function(get_iccarm_version)
+ #Parse our arguments
+ set( _OPTIONS_ARGS ) #No option (on/off) arguments (e.g. IGNORE_CASE)
+ set( _ONE_VALUE_ARGS ICCARM RES) #Single option arguments (e.g. PATH "./foo/bar")
+ set( _MULTI_VALUE_ARGS ) #One list argument (e.g. LANGUAGES C ASM CXX)
+ cmake_parse_arguments(_MY_PARAMS "${_OPTIONS_ARGS}" "${_ONE_VALUE_ARGS}" "${_MULTI_VALUE_ARGS}" ${ARGN} )
+
+ #Check mandatory parameters
+ if(NOT _MY_PARAMS_RES)
+ message (FATAL_ERROR "get_iccarm_version(): Missing result parameter!")
+ endif()
+ set (_RES ${_MY_PARAMS_RES})
+
+ if(NOT _MY_PARAMS_ICCARM)
+ message (FATAL_ERROR "get_iccarm_version(): Missing ICCARM parameter!")
+ endif()
+ set (_ICCARM ${_MY_PARAMS_ICCARM})
+
+ #Call specified executable
+ execute_process(COMMAND "${_ICCARM}" --version
+ OUTPUT_VARIABLE _OUTPUT
+ ERROR_VARIABLE _OUTPUT
+ )
+ #Cut off version number. Just the numbers ignore anything after.
+ STRING(REGEX REPLACE "IAR.* Compiler V(([0-9]+\.)+[0-9]+).*" "\\1" _VER "${_OUTPUT}")
+
+ if (NOT _VER)
+ message (FATAL_ERROR "get_iccarm_version(): Failed to extract version number from iccarm output.")
+ endif()
+
+ set(${_RES} ${_VER} PARENT_SCOPE)
+endfunction()
+
+#If the install location needs to be found.
+if(NOT DEFINED IARARM_PATH)
+ #Set IARARM_PATH to default value.
+ set (IARARM_PATH "IARARM_PATH-NOTFOUND")
+
+ #First check if iccarm is on the PATH
+ #find_program puts() its output to the cmake cache. We don't want that, so we use a local variable, which
+ #is unset later.
+ find_program (
+ _IARARM_PATH
+ iccarm
+ PATHS env PATH
+ DOC "IARARM compiler location."
+ )
+
+ #Yes, check the version number if it is specified.
+ if(_IARARM_PATH STREQUAL "_IARARM_PATH-NOTFOUND")
+ message (FATAL_ERROR "iccarm install location is unset. Either put iccarm on the PATH or set IARARM_PATH.")
+ endif()
+
+ #Cut off executable name directory name to get install location.
+ STRING(REGEX REPLACE "(.*)/bin/iccarm.*" "\\1" IARARM_PATH "${_IARARM_PATH}")
+
+ #Remove unwanted junk from CMake cache.
+ unset(_IARARM_PATH CACHE)
+endif()
+
+get_iccarm_version(ICCARM "${IARARM_PATH}/bin/iccarm" RES _VER)
+
+#Check the version if needed
+if(NOT DEFINED IARARM_VER)
+ set(IARARM_VER ${_VER})
+endif()
+
+if(NOT "${IARARM_VER}" VERSION_EQUAL "${_VER}")
+ message (FATAL_ERROR "FindIARArm.cmake: iccarm compiler version ${_VER} does not match ${IARARM_VER}.")
+endif()
+
+STRING(REGEX REPLACE "([0-9]+)\.([0-9]+)(\.[0-9]+)*.*" "CompilerIarArm\\1\\2" IARARM_MODULE "${IARARM_VER}")
+
+message(STATUS "Version: ${IARARM_VER}/${IARARM_MODULE}")
+
+if(NOT EXISTS "${CMAKE_CURRENT_LIST_DIR}/${IARARM_MODULE}.cmake")
+ message(FATAL_ERROR "ERROR: Unsupported IARARM compiler version found on PATH.")
+endif()
diff --git a/cmake/Common/IARArMerge.cmake b/cmake/Common/IARArMerge.cmake
new file mode 100644
index 0000000..e9d19f9
--- /dev/null
+++ b/cmake/Common/IARArMerge.cmake
@@ -0,0 +1,117 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+#A cmake script to merge two archives using IAR iarchive.
+#
+# The script will first run iarchive to get the list of files in the source archive.
+# Then each file is:
+# -extracted
+# -added to the target archive
+# -deleted
+#
+# The loop is needed to avoid losing files with matching name in the source
+# archive.
+# The destination archive is updated in a way not to overwrite existing files
+# with matching names.
+#
+#Examples:
+# cmake -DCMAKE_AR=iarchive -DDESTINATION=new_lib.a -DSOURCE=/foo/bar/old_lib.a -P ./IARArMerge.cmake
+#
+#Parameters:
+# SOURCE - archive file to copy all members from
+# DESTINATION - archive file to copy members to. If file exists, then new
+# members are added without overwriting existing ones.
+# CMAKE_AR - GNU AR executable
+#
+
+#Execute AR and capture its output
+#
+# Script execution will stop with a fatal error if AR execution fails.
+#
+#Examples:
+# List content of archive:
+# run_ar(RESULT t /foo/bar/my_lib.a)
+# Add object file to archive
+# run_ar(RESULT q /foo/bar/my_lib.a new_obj.o)
+#
+#INPUTS:
+# RESULT - (mandatory) - name of variable to put result in
+# All remaining parameters will be command line options to AR
+#
+#OUTPUTS
+# RESULT - text output of AR command
+#
+function(run_ar OUTPUT )
+ execute_process(COMMAND ${CMAKE_AR} ${ARGN}
+ TIMEOUT 120
+ OUTPUT_VARIABLE _RES
+ RESULT_VARIABLE _STATUS_CODE
+ OUTPUT_STRIP_TRAILING_WHITESPACE)
+
+ if (STATUS_CODE GREATER 0)
+ message(FATAL_ERROR "ERROR: Failed to execute \"${CMAKE_AR} ${ARGN}\".")
+ endif()
+ set(${OUTPUT} ${_RES} PARENT_SCOPE)
+endfunction()
+
+#Delete a file
+#
+# Function to delete a file. No error will be reported if file is missing.
+# Script execution will stop with a fatal error if AR execution fails.
+#
+#Examples:
+# rm(/foo/bar/my_lib.a)
+#
+#INPUTS:
+# FILE - path to file to delete
+#
+#OUTPUTS
+# N/A
+#
+function(rm FILE)
+ execute_process(COMMAND ${CMAKE_COMMAND} -E remove ${FILE}
+ RESULT_VARIABLE _STATUS_CODE
+ TIMEOUT 120)
+ if (STATUS_CODE GREATER 0)
+ message(FATAL_ERROR "ERROR: Failed to execute \"${CMAKE_COMMAND} -E remove ${FILE}\".")
+ endif()
+endfunction()
+
+
+#############################################################################
+# Entry point
+#############################################################################
+#Verify input variables.
+
+if(NOT DEFINED SOURCE)
+ message(FATAL_ERROR "GNUArMerge.cmake: Variable SOURCE is not defined.")
+endif()
+
+if(NOT DEFINED DESTINATION)
+ message(FATAL_ERROR "GNUArMerge.cmake: Variable DESTINATION is not defined.")
+endif()
+
+if(NOT DEFINED CMAKE_AR)
+ message(FATAL_ERROR "GNUArMerge.cmake: Variable CMAKE_AR is not defined.")
+endif()
+
+
+#Get list of archive members
+run_ar("OBJ_LIST" -t ${SOURCE})
+
+#Convert AR output to cmake list
+string(REPLACE "\n" ";" OBJ_LIST ${OBJ_LIST})
+
+#Iterate over member list.
+foreach(OBJ ${OBJ_LIST})
+ #Extract member
+ run_ar("_DUMMY" -x ${SOURCE} ${OBJ})
+ #Add member to destination archive
+ run_ar("_DUMMY" -r ${DESTINATION} ${OBJ})
+ #Remove extracted member
+ rm("${OBJ}")
+endforeach()
diff --git a/cmake/Compiler/IARARM-ASM.cmake b/cmake/Compiler/IARARM-ASM.cmake
new file mode 100644
index 0000000..e13b881
--- /dev/null
+++ b/cmake/Compiler/IARARM-ASM.cmake
@@ -0,0 +1,11 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+include(Compiler/IARARM)
+set(CMAKE_ASM_SOURCE_FILE_EXTENSIONS s;S;asm)
+__compiler_iararm(ASM)
+
diff --git a/cmake/Compiler/IARARM-C.cmake b/cmake/Compiler/IARARM-C.cmake
new file mode 100644
index 0000000..bde93f9
--- /dev/null
+++ b/cmake/Compiler/IARARM-C.cmake
@@ -0,0 +1,9 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+include(Compiler/IARARM)
+__compiler_iararm(C)
diff --git a/cmake/Compiler/IARARM-CXX.cmake b/cmake/Compiler/IARARM-CXX.cmake
new file mode 100644
index 0000000..04ab85c
--- /dev/null
+++ b/cmake/Compiler/IARARM-CXX.cmake
@@ -0,0 +1,9 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+include(Compiler/IARARM)
+__compiler_iararm(CXX)
diff --git a/cmake/Compiler/IARARM.cmake b/cmake/Compiler/IARARM.cmake
new file mode 100644
index 0000000..5bb2a37
--- /dev/null
+++ b/cmake/Compiler/IARARM.cmake
@@ -0,0 +1,55 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+if(_IARARM_CMAKE_LOADED_TFM)
+ return()
+endif()
+set(_IARARM_CMAKE_LOADED_TFM TRUE)
+
+get_filename_component(_CMAKE_C_TOOLCHAIN_LOCATION "${CMAKE_C_COMPILER}" PATH)
+get_filename_component(_CMAKE_CXX_TOOLCHAIN_LOCATION "${CMAKE_CXX_COMPILER}" PATH)
+
+set(CMAKE_EXECUTABLE_SUFFIX ".axf")
+
+find_program(CMAKE_IARARM_LINKER ilinkarm HINTS "${_CMAKE_C_TOOLCHAIN_LOCATION}" "${_CMAKE_CXX_TOOLCHAIN_LOCATION}" )
+find_program(CMAKE_IARARM_AR iarchive HINTS "${_CMAKE_C_TOOLCHAIN_LOCATION}" "${_CMAKE_CXX_TOOLCHAIN_LOCATION}" )
+find_program(CMAKE_IARARM_IELFTOOL ielftool HINTS "${_CMAKE_C_TOOLCHAIN_LOCATION}" "${_CMAKE_CXX_TOOLCHAIN_LOCATION}" )
+
+set(CMAKE_LINKER "${CMAKE_IARARM_LINKER}" CACHE FILEPATH "The IAR linker" FORCE)
+mark_as_advanced(CMAKE_IARARM_LINKER)
+set(CMAKE_AR "${CMAKE_IARARM_AR}" CACHE FILEPATH "The IAR archiver" FORCE)
+mark_as_advanced(CMAKE_IARARM_AR)
+
+macro(__compiler_iararm lang)
+ if(NOT CMAKE_${lang}_FLAGS_SET)
+ set(CMAKE_${lang}_FLAGS_SET TRUE)
+ set(CMAKE_${lang}_RESPONSE_FILE_LINK_FLAG "-f ")
+ string(APPEND CMAKE_${lang}_FLAGS_INIT " ")
+
+ if (NOT ${lang} STREQUAL "ASM")
+ string(APPEND CMAKE_${lang}_FLAGS_DEBUG_INIT " --debug -On")
+ string(APPEND CMAKE_${lang}_FLAGS_MINSIZEREL_INIT " -Ohz -DNDEBUG")
+ string(APPEND CMAKE_${lang}_FLAGS_RELEASE_INIT " -Ohs -DNDEBUG")
+ string(APPEND CMAKE_${lang}_FLAGS_RELWITHDEBINFO_INIT " -Ohs --debug")
+ endif()
+
+ set(CMAKE_${lang}_OUTPUT_EXTENSION ".o")
+ set(CMAKE_${lang}_OUTPUT_EXTENSION_REPLACE 1)
+ set(CMAKE_STATIC_LIBRARY_PREFIX_${lang} "")
+ set(CMAKE_STATIC_LIBRARY_SUFFIX_${lang} ".a")
+
+ set(CMAKE_${lang}_USE_RESPONSE_FILE_FOR_OBJECTS 1)
+ set(CMAKE_${lang}_RESPONSE_FILE_LINK_FLAG "-f ")
+
+ set(CMAKE_${lang}_LINK_EXECUTABLE "<CMAKE_LINKER> <CMAKE_${lang}_LINK_FLAGS> <LINK_FLAGS> <LINK_LIBRARIES> <OBJECTS> -o <TARGET> --map <TARGET_BASE>.map")
+ set(CMAKE_${lang}_CREATE_STATIC_LIBRARY "<CMAKE_AR> --create <TARGET> <LINK_FLAGS> <OBJECTS>")
+ set(CMAKE_${lang}_CREATE_PREPROCESSED_SOURCE "<CMAKE_${lang}_COMPILER> <DEFINES> <INCLUDES> <FLAGS> --preprocess=n <PREPROCESSED_SOURCE> <SOURCE> ")
+ set(CMAKE_${lang}_CREATE_ASSEMBLY_SOURCE "<CMAKE_${lang}_COMPILER> <DEFINES> <INCLUDES> <FLAGS> <SOURCE> -la <ASSEMBLY_SOURCE>")
+
+ set(CMAKE_DEPFILE_FLAGS_${lang} "--dependencies=ins <DEPFILE>")
+ endif()
+endmacro()
diff --git a/platform/ext/cmsis/cmsis_iccarm.h b/platform/ext/cmsis/cmsis_iccarm.h
new file mode 100644
index 0000000..4020ad7
--- /dev/null
+++ b/platform/ext/cmsis/cmsis_iccarm.h
@@ -0,0 +1,964 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.1.1
+ * @date 30. July 2019
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2019 IAR Systems
+// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+ #if __ARM_ARCH == 6
+ #define __ARM_ARCH_6M__ 1
+ #elif __ARM_ARCH == 7
+ #if __ARM_FEATURE_DSP
+ #define __ARM_ARCH_7EM__ 1
+ #else
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #endif /* __ARM_ARCH */
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+ #define __ARM_ARCH_6M__ 1
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+ #define __ARM_ARCH_7M__ 1
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+ #define __ARM_ARCH_7EM__ 1
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #else
+ #error "Unknown target."
+ #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+ #define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+ #define __IAR_M0_FAMILY 1
+#else
+ #define __IAR_M0_FAMILY 0
+#endif
+
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #if __ICCARM_V8
+ #define __RESTRICT __restrict
+ #else
+ /* Needs IAR language extensions */
+ #define __RESTRICT restrict
+ #endif
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+ return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+ *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+ return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+ *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
+#endif
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+
+ #define __get_APSR() (__arm_rsr("APSR"))
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #define __get_IPSR() (__arm_rsr("IPSR"))
+ #define __get_MSP() (__arm_rsr("MSP"))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __get_MSPLIM() (0U)
+ #else
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+ #endif
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+ #define __get_PSP() (__arm_rsr("PSP"))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __get_PSPLIM() (0U)
+ #else
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+ #endif
+
+ #define __get_xPSR() (__arm_rsr("xPSR"))
+
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+ #endif
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+ #endif
+
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __TZ_get_PSPLIM_NS() (0U)
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+ #else
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #endif
+
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #if !__IAR_M0_FAMILY
+ #define __SSAT __iar_builtin_SSAT
+ #endif
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #if !__IAR_M0_FAMILY
+ #define __USAT __iar_builtin_USAT
+ #endif
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #if __ARM_MEDIA__
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+ #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz_not_active
+ #define __SSAT __cmsis_iar_ssat_not_active
+ #define __USAT __cmsis_iar_usat_not_active
+ #define __RBIT __cmsis_iar_rbit_not_active
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
+ #endif
+
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include <intrinsics.h>
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #undef __CLZ
+ #undef __SSAT
+ #undef __USAT
+ #undef __RBIT
+ #undef __get_APSR
+
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+ {
+ uint8_t sc = 31U;
+ uint32_t r = v;
+ for (v >>= 1U; v; v >>= 1U)
+ {
+ r <<= 1U;
+ r |= v & 1U;
+ sc--;
+ }
+ return (r << sc);
+ }
+
+ __STATIC_INLINE uint32_t __get_APSR(void)
+ {
+ uint32_t res;
+ __asm("MRS %0,APSR" : "=r" (res));
+ return res;
+ }
+
+ #endif
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #undef __get_FPSCR
+ #undef __set_FPSCR
+ #define __get_FPSCR() (0)
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+ #endif
+
+
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+ #if (__CORTEX_M >= 0x03)
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
+ return(result);
+ }
+
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
+ }
+
+
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+
+
+ #endif /* (__CORTEX_M >= 0x03) */
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+ __IAR_FT uint32_t __get_MSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_MSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __get_PSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_PSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
+ {
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
+ {
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
+ }
+
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+ {
+ __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+ {
+ __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+ {
+ __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+ }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+ {
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+ {
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+ {
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/platform/ext/common/iar/tfm_common_s.icf b/platform/ext/common/iar/tfm_common_s.icf
new file mode 100644
index 0000000..8acd451
--- /dev/null
+++ b/platform/ext/common/iar/tfm_common_s.icf
@@ -0,0 +1,738 @@
+/*
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * This file is derivative of ../armclang/tfm_common_s.sct.template
+ */
+
+/*********** WARNING: This is an auto-generated file. Do not edit! ***********/
+
+#include "region_defs.h"
+
+define memory mem with size = 4G;
+
+define region S_CODE_region = mem:[from S_CODE_START size S_CODE_SIZE];
+
+define region S_RAM_region = mem:[from S_DATA_START size S_DATA_SIZE];
+
+define block ER_TFM_CODE with fixed order, alignment = 8 {readonly section .intvec, readonly};
+
+define block TFM_UNPRIV_CODE with alignment = 32 {
+ ro object tfm_spm_services.o,
+ ro object platform_retarget_dev.o,
+ ro object device_definition.o,
+ section SFN,
+ ro section .rodata object tfm_its_secure_api.o,
+ ro object *7M_tl*.a,
+ ro object *libtfmsprt.a
+ };
+
+ /**** PSA RoT RO part (CODE + RODATA) start here */
+ /*
+ * This empty, zero long execution region is here to mark the start address
+ * of PSA RoT code.
+ */
+define block TFM_PSA_CODE_START with alignment = 32, size = 0 { };
+
+#ifdef TFM_PARTITION_SECURE_STORAGE
+define block TFM_SP_STORAGE_LINKER with alignment = 32 {
+ ro object *tfm_storage*,
+ section TFM_SP_STORAGE_ATTR_FN
+ };
+#endif /* TFM_PARTITION_SECURE_STORAGE */
+
+#ifdef TFM_PARTITION_INTERNAL_TRUSTED_STORAGE
+define block TFM_SP_ITS_LINKER with alignment = 32 {
+ ro object *tfm_internal_trusted_storage*,
+ section TFM_SP_ITS_ATTR_FN
+ };
+#endif /* TFM_PARTITION_INTERNAL_TRUSTED_STORAGE */
+
+#ifdef TFM_PARTITION_AUDIT_LOG
+define block TFM_SP_AUDIT_LOG_LINKER with alignment = 32 {
+ ro object *tfm_audit*,
+ section TFM_SP_AUDIT_LOG_ATTR_FN
+ };
+#endif /* TFM_PARTITION_AUDIT_LOG */
+
+#ifdef TFM_PARTITION_CRYPTO
+define block TFM_SP_CRYPTO_LINKER with alignment = 32 {
+ ro object *tfm_crypto*,
+ section TFM_SP_CRYPTO_ATTR_FN
+ };
+#endif /* TFM_PARTITION_CRYPTO */
+
+#ifdef TFM_PARTITION_PLATFORM
+define block TFM_SP_PLATFORM_LINKER with alignment = 32 {
+ ro object *tfm_platform*,
+ section TFM_SP_PLATFORM_ATTR_FN
+ };
+#endif /* TFM_PARTITION_PLATFORM */
+
+#ifdef TFM_PARTITION_INITIAL_ATTESTATION
+define block TFM_SP_INITIAL_ATTESTATION_LINKER with alignment = 32 {
+ ro object *tfm_attest*,
+ section TFM_SP_INITIAL_ATTESTATION_ATTR_FN
+ };
+#endif /* TFM_PARTITION_INITIAL_ATTESTATION */
+
+#ifdef TFM_PARTITION_TEST_CORE
+define block TFM_SP_CORE_TEST_LINKER with alignment = 32 {
+ ro object *tfm_ss_core_test.*,
+ section TFM_SP_CORE_TEST_ATTR_FN
+ };
+#endif /* TFM_PARTITION_TEST_CORE */
+
+#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
+define block TFM_SP_SECURE_TEST_PARTITION_LINKER with alignment = 32 {
+ ro object *tfm_secure_client_service.*,
+ ro object *test_framework*,
+ ro object *uart_stdout.*,
+ ro object *Driver_USART.*,
+ ro object *arm_uart_drv.*,
+ ro object *uart_pl011_drv.*,
+ ro object *uart_cmsdk_drv*,
+ ro object *secure_suites.*,
+ ro object *attestation_s_interface_testsuite.*,
+ section TFM_SP_SECURE_TEST_PARTITION_ATTR_FN
+ };
+#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
+
+#ifdef TFM_PARTITION_TEST_CORE_IPC
+define block TFM_SP_IPC_SERVICE_TEST_LINKER with alignment = 32 {
+ ro object *ipc_service_test.*,
+ section TFM_SP_IPC_SERVICE_TEST_ATTR_FN
+ };
+#endif /* TFM_PARTITION_TEST_CORE_IPC */
+
+#ifdef TFM_PARTITION_TEST_SST
+define block TFM_SP_SST_TEST_LINKER with alignment = 32 {
+ ro object *tfm_sst_test_service.*,
+ section TFM_SP_SST_TEST_ATTR_FN
+ };
+#endif /* TFM_PARTITION_TEST_SST */
+
+ /*
+ * This empty, zero long execution region is here to mark the end address
+ * of PSA RoT code.
+ */
+define block TFM_PSA_CODE_END with alignment = 32, size = 0 { };
+
+ /**** APPLICATION RoT RO part (CODE + RODATA) start here */
+ /*
+ * This empty, zero long execution region is here to mark the start address
+ * of APP RoT code.
+ */
+define block TFM_APP_CODE_START with alignment = 32, size = 0 { };
+
+#ifdef TFM_PARTITION_TEST_CORE
+define block TFM_SP_CORE_TEST_2_LINKER with alignment = 32 {
+ ro object *tfm_ss_core_test_2.*,
+ };
+#endif /* TFM_PARTITION_TEST_CORE */
+
+#ifdef TFM_PARTITION_TEST_CORE_IPC
+define block TFM_SP_IPC_CLIENT_TEST_LINKER with alignment = 32 {
+ ro object *ipc_client_test.*,
+ };
+#endif /* TFM_PARTITION_TEST_CORE_IPC */
+
+#ifdef TFM_ENABLE_IRQ_TEST
+define block TFM_IRQ_TEST_1_LINKER with alignment = 32 {
+ ro object *tfm_irq_test_service_1.*,
+ ro object *timer_cmsdk*,
+ };
+#endif /* TFM_ENABLE_IRQ_TEST */
+
+#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
+define block TFM_SP_SECURE_CLIENT_2_LINKER with alignment = 32 {
+ ro object *tfm_secure_client_2.*,
+ };
+#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
+
+#ifdef TFM_MULTI_CORE_TEST
+define block TFM_SP_MULTI_CORE_TEST_LINKER with alignment = 32 {
+ ro object *multi_core_test.*,
+ };
+#endif /* TFM_MULTI_CORE_TEST */
+
+ /*
+ * This empty, zero long execution region is here to mark the end address
+ * of APP RoT code.
+ */
+define block TFM_APP_CODE_END with alignment = 32, size = 0 { };
+
+ /**** Base address of secure data area */
+define block TFM_SECURE_DATA_START with size = 0 { };
+
+#if !TFM_MULTI_CORE_TOPOLOGY
+ /* Shared area between BL2 and runtime to exchange data */
+define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { };
+define block ARM_LIB_STACK_MSP with alignment = 32, size = S_MSP_STACK_SIZE { };
+define overlay STACK_DATA {block TFM_SHARED_DATA};
+define overlay STACK_DATA {block ARM_LIB_STACK_MSP};
+
+define block ARM_LIB_STACK with alignment = 32, size = S_PSP_STACK_SIZE { };
+#endif
+
+#if !defined(TFM_PSA_API)
+define block TFM_SECURE_STACK with size = 0x2000, alignment = 128 {};
+#endif /* !defined(TFM_PSA_API) */
+
+define block TFM_UNPRIV_DATA with alignment = 32 {
+ rw object tfm_spm_services.o,
+ rw object platform_retarget_dev.o,
+ rw object device_definition.o,
+ };
+
+define block TFM_APP_RW_STACK_START with alignment = 32, size = 0 { };
+
+#ifdef TFM_PARTITION_TEST_CORE
+define block TFM_SP_CORE_TEST_2_LINKER_DATA with alignment = 32 {
+ rw object *tfm_ss_core_test_2.*,
+ };
+
+#if defined (TFM_PSA_API)
+define block TFM_SP_CORE_TEST_2_LINKER_STACK with alignment = 128, size = 0x0280 { };
+#endif
+#endif /* TFM_PARTITION_TEST_CORE */
+
+#ifdef TFM_PARTITION_TEST_CORE_IPC
+define block TFM_SP_IPC_CLIENT_TEST_LINKER_DATA with alignment = 32 {
+ rw object *ipc_client_test.*,
+ };
+
+#if defined (TFM_PSA_API)
+define block TFM_SP_IPC_CLIENT_TEST_LINKER_STACK with alignment = 128, size = 0x0300 { };
+#endif
+#endif /* TFM_PARTITION_TEST_CORE_IPC */
+
+#ifdef TFM_ENABLE_IRQ_TEST
+define block TFM_IRQ_TEST_1_LINKER_DATA with alignment = 32 {
+ rw object *tfm_irq_test_service_1.*,
+ rw object *timer_cmsdk*,
+ };
+
+#if defined (TFM_PSA_API)
+define block TFM_IRQ_TEST_1_LINKER_STACK with alignment = 128, size = 0x0400 { };
+#endif
+#endif /* TFM_ENABLE_IRQ_TEST */
+
+#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
+define block TFM_SP_SECURE_CLIENT_2_LINKER_DATA with alignment = 32 {
+ rw object *tfm_secure_client_2.*,
+ };
+
+#if defined (TFM_PSA_API)
+define block TFM_SP_SECURE_CLIENT_2_LINKER_STACK with alignment = 128, size = 0x300 { };
+#endif
+#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
+
+#ifdef TFM_MULTI_CORE_TEST
+define block TFM_SP_MULTI_CORE_TEST_LINKER_DATA with alignment = 32 {
+ rw object *multi_core_test.*,
+ };
+
+#if defined (TFM_PSA_API)
+define block TFM_SP_MULTI_CORE_TEST_LINKER_STACK with alignment = 128, size = 0x0100 { };
+#endif
+#endif /* TFM_MULTI_CORE_TEST */
+
+
+ /*
+ * This empty, zero long execution region is here to mark the end address
+ * of APP RoT RW and Stack.
+ */
+define block TFM_APP_RW_STACK_END with alignment = 32, size = 0 { };
+
+#if TFM_MULTI_CORE_TOPOLOGY && defined(S_DATA_PRIV_START)
+ /**** Privileged data area base address specified by multi-core platform */
+define block TFM_SECURE_PRIV_DATA_BOUNDARY with size = 0 { };
+#endif
+
+#if TFM_MULTI_CORE_TOPOLOGY
+ /*
+ * Move BL2 shared area and MSP stack to the beginning of privileged data
+ * area in multi-core topology.
+ */
+ /* Shared area between BL2 and runtime to exchange data */
+define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { };
+
+ /* MSP */
+define block ARM_LIB_STACK_MSP with alignment = 32, size = S_MSP_STACK_SIZE { };
+
+define overlay STACK_DATA {block TFM_SHARED_DATA};
+define overlay STACK_DATA {block ARM_LIB_STACK_MSP};
+
+ /* PSP is privileged in multi-core topology */
+define block ARM_LIB_STACK with alignment = 32, size = S_PSP_STACK_SIZE { };
+#endif
+
+define block HEAP with alignment = 8, size = S_HEAP_SIZE { };
+define block ARM_LIB_HEAP with alignment = 8, size = S_HEAP_SIZE { };
+define overlay HEAP_OVL {block HEAP};
+define overlay HEAP_OVL {block ARM_LIB_HEAP};
+
+define block ER_TFM_DATA with alignment = 8 {readwrite};
+
+ /**** PSA RoT DATA start here */
+ /*
+ * This empty, zero long execution region is here to mark the start address
+ * of PSA RoT RW and Stack.
+ */
+define block TFM_PSA_RW_STACK_START with alignment = 32, size = 0 { };
+
+#ifdef TFM_PARTITION_SECURE_STORAGE
+define block TFM_SP_STORAGE_LINKER_DATA with alignment = 32 {
+ rw object *tfm_storage*,
+ };
+
+#if defined (TFM_PSA_API)
+define block TFM_SP_STORAGE_LINKER_STACK with alignment = 128, size = 0x600 { };
+#endif
+#endif /* TFM_PARTITION_SECURE_STORAGE */
+
+#ifdef TFM_PARTITION_INTERNAL_TRUSTED_STORAGE
+define block TFM_SP_ITS_LINKER_DATA with alignment = 32 {
+ rw object *tfm_internal_trusted_storage*,
+ };
+
+#if defined (TFM_PSA_API)
+define block TFM_SP_ITS_LINKER_STACK with alignment = 128, size = 0x500 { };
+#endif
+#endif /* TFM_PARTITION_INTERNAL_TRUSTED_STORAGE */
+
+#ifdef TFM_PARTITION_AUDIT_LOG
+define block TFM_SP_AUDIT_LOG_LINKER_DATA with alignment = 32 {
+ rw object *tfm_audit*,
+ };
+
+#if defined (TFM_PSA_API)
+define block TFM_SP_AUDIT_LOG_LINKER_STACK with alignment = 128, size = 0 { };
+#endif
+#endif /* TFM_PARTITION_AUDIT_LOG */
+
+#ifdef TFM_PARTITION_CRYPTO
+define block TFM_SP_CRYPTO_LINKER_DATA with alignment = 32 {
+ rw object *tfm_crypto*,
+ };
+
+#if defined (TFM_PSA_API)
+define block TFM_SP_CRYPTO_LINKER_STACK with alignment = 128, size = 0x2000 { };
+#endif
+#endif /* TFM_PARTITION_CRYPTO */
+
+#ifdef TFM_PARTITION_PLATFORM
+define block TFM_SP_PLATFORM_LINKER_DATA with alignment = 32 {
+ rw object *tfm_platform*,
+ };
+
+#if defined (TFM_PSA_API)
+define block TFM_SP_PLATFORM_LINKER_STACK with alignment = 128, size = 0x0400 { };
+#endif
+#endif /* TFM_PARTITION_PLATFORM */
+
+#ifdef TFM_PARTITION_INITIAL_ATTESTATION
+define block TFM_SP_INITIAL_ATTESTATION_LINKER_DATA with alignment = 32 {
+ rw object *tfm_attest*,
+ };
+
+#if defined (TFM_PSA_API)
+define block TFM_SP_INITIAL_ATTESTATION_LINKER_STACK with alignment = 128, size = 0x0A80 { };
+#endif
+#endif /* TFM_PARTITION_INITIAL_ATTESTATION */
+
+#ifdef TFM_PARTITION_TEST_CORE
+define block TFM_SP_CORE_TEST_LINKER_DATA with alignment = 32 {
+ rw object *tfm_ss_core_test.*,
+ };
+
+#if defined (TFM_PSA_API)
+define block TFM_SP_CORE_TEST_LINKER_STACK with alignment = 128, size = 0x0380 { };
+#endif
+#endif /* TFM_PARTITION_TEST_CORE */
+
+#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
+define block TFM_SP_SECURE_TEST_PARTITION_LINKER_DATA with alignment = 32 {
+ rw object *tfm_secure_client_service.*,
+ rw object *test_framework*,
+ rw object *uart_stdout.*,
+ rw object *Driver_USART.*,
+ rw object *arm_uart_drv.*,
+ rw object *uart_pl011_drv.*,
+ rw object *uart_cmsdk_drv*,
+ rw object *secure_suites.*,
+ rw object *attestation_s_interface_testsuite.*,
+ };
+
+#if defined (TFM_PSA_API)
+define block TFM_SP_SECURE_TEST_PARTITION_LINKER_STACK with alignment = 128, size = 0x0D00 { };
+#endif
+#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
+
+#ifdef TFM_PARTITION_TEST_CORE_IPC
+define block TFM_SP_IPC_SERVICE_TEST_LINKER_DATA with alignment = 32 {
+ rw object *ipc_service_test.*,
+ };
+
+#if defined (TFM_PSA_API)
+define block TFM_SP_IPC_SERVICE_TEST_LINKER_STACK with alignment = 128, size = 0x0220 { };
+#endif
+#endif /* TFM_PARTITION_TEST_CORE_IPC */
+
+#ifdef TFM_PARTITION_TEST_SST
+define block TFM_SP_SST_TEST_LINKER_DATA with alignment = 32 {
+ rw object *tfm_sst_test_service.*,
+ };
+
+#if defined (TFM_PSA_API)
+define block TFM_SP_SST_TEST_LINKER_STACK with alignment = 128, size = 0x500 { };
+#endif
+#endif /* TFM_PARTITION_TEST_SST */
+
+
+ /*
+ * This empty, zero long execution region is here to mark the end address
+ * of PSA RoT RW and Stack.
+ */
+define block TFM_PSA_RW_STACK_END with alignment = 32, size = 0x0 { };
+
+ /* This empty, zero long execution region is here to mark the limit address
+ * of the last execution region that is allocated in SRAM.
+ */
+define block SRAM_WATERMARK with size = 0 { };
+
+define block LR_CODE with fixed order {
+ block ER_TFM_CODE,
+ block TFM_UNPRIV_CODE,
+ block TFM_PSA_CODE_START,
+
+#ifdef TFM_PARTITION_SECURE_STORAGE
+ block TFM_SP_STORAGE_LINKER,
+#endif /* TFM_PARTITION_SECURE_STORAGE */
+#ifdef TFM_PARTITION_INTERNAL_TRUSTED_STORAGE
+ block TFM_SP_ITS_LINKER,
+#endif /* TFM_PARTITION_INTERNAL_TRUSTED_STORAGE */
+#ifdef TFM_PARTITION_AUDIT_LOG
+ block TFM_SP_AUDIT_LOG_LINKER,
+#endif /* TFM_PARTITION_AUDIT_LOG */
+#ifdef TFM_PARTITION_CRYPTO
+ block TFM_SP_CRYPTO_LINKER,
+#endif /* TFM_PARTITION_CRYPTO */
+#ifdef TFM_PARTITION_PLATFORM
+ block TFM_SP_PLATFORM_LINKER,
+#endif /* TFM_PARTITION_PLATFORM */
+#ifdef TFM_PARTITION_INITIAL_ATTESTATION
+ block TFM_SP_INITIAL_ATTESTATION_LINKER,
+#endif /* TFM_PARTITION_INITIAL_ATTESTATION */
+#ifdef TFM_PARTITION_TEST_CORE
+ block TFM_SP_CORE_TEST_LINKER,
+#endif /* TFM_PARTITION_TEST_CORE */
+#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
+ block TFM_SP_SECURE_TEST_PARTITION_LINKER,
+#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
+#ifdef TFM_PARTITION_TEST_CORE_IPC
+ block TFM_SP_IPC_SERVICE_TEST_LINKER,
+#endif /* TFM_PARTITION_TEST_CORE_IPC */
+#ifdef TFM_PARTITION_TEST_SST
+ block TFM_SP_SST_TEST_LINKER,
+#endif /* TFM_PARTITION_TEST_SST */
+
+ block TFM_PSA_CODE_END,
+
+/**** APPLICATION RoT RO part (CODE + RODATA) start here */
+ /*
+ * This empty, zero long execution region is here to mark the start address
+ * of APP RoT code.
+ */
+ block TFM_APP_CODE_START,
+#ifdef TFM_PARTITION_TEST_CORE
+ block TFM_SP_CORE_TEST_2_LINKER,
+#endif /* TFM_PARTITION_TEST_CORE */
+
+#ifdef TFM_PARTITION_TEST_CORE_IPC
+ block TFM_SP_IPC_CLIENT_TEST_LINKER,
+#endif /* TFM_PARTITION_TEST_CORE_IPC */
+
+#ifdef TFM_ENABLE_IRQ_TEST
+ block TFM_IRQ_TEST_1_LINKER,
+#endif /* TFM_ENABLE_IRQ_TEST */
+
+#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
+ block TFM_SP_SECURE_CLIENT_2_LINKER,
+#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
+
+#ifdef TFM_MULTI_CORE_TEST
+ block TFM_SP_MULTI_CORE_TEST_LINKER,
+#endif /* TFM_MULTI_CORE_TEST */
+
+ /*
+ * This empty, zero long execution region is here to mark the end address
+ * of APP RoT code.
+ */
+ block TFM_APP_CODE_END,
+ };
+
+do not initialize { section .noinit };
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy { section __DLIB_PERTHREAD };
+}
+
+place in S_CODE_region { block LR_CODE };
+
+define block DATA with fixed order {
+ /**** Base address of secure data area */
+ block TFM_SECURE_DATA_START,
+
+ /*
+ * MPU on Armv6-M/v7-M core in multi-core topology may require more strict
+ * alignment that MPU region base address must align with the MPU region
+ * size.
+ * As a result, in multi-core topology, to save memory resource and MPU
+ * regions, unprivileged data sections and privileged data sections are
+ * separated and gathered in unprivileged/privileged data area respectively.
+ * Keep BL2 shared data and MSP stack at the beginning of the secure data
+ * area in single Armv8-M topology, while move the two areas to the
+ * beginning of privileged data region in multi-core topology.
+ */
+#ifndef TFM_MULTI_CORE_TOPOLOGY
+ /* Shared area between BL2 and runtime to exchange data */
+ overlay STACK_DATA,
+ /* PSP is unprivileged in single-core topology */
+ block ARM_LIB_STACK,
+#endif
+
+#if !defined(TFM_PSA_API)
+ block TFM_SECURE_STACK,
+#endif /* !defined(TFM_PSA_API) */
+
+ block TFM_UNPRIV_DATA,
+
+ /**** APP RoT DATA start here */
+ /*
+ * This empty, zero long execution region is here to mark the start address
+ * of APP RoT RW and Stack.
+ */
+ block TFM_APP_RW_STACK_START,
+
+#ifdef TFM_PARTITION_TEST_CORE
+ block TFM_SP_CORE_TEST_2_LINKER_DATA,
+
+#if defined (TFM_PSA_API)
+ block TFM_SP_CORE_TEST_2_LINKER_STACK,
+#endif
+#endif /* TFM_PARTITION_TEST_CORE */
+
+#ifdef TFM_PARTITION_TEST_CORE_IPC
+ block TFM_SP_IPC_CLIENT_TEST_LINKER_DATA,
+
+#if defined (TFM_PSA_API)
+ block TFM_SP_IPC_CLIENT_TEST_LINKER_STACK,
+#endif
+#endif /* TFM_PARTITION_TEST_CORE_IPC */
+
+#ifdef TFM_ENABLE_IRQ_TEST
+ block TFM_IRQ_TEST_1_LINKER_DATA,
+
+#if defined (TFM_PSA_API)
+ block TFM_IRQ_TEST_1_LINKER_STACK,
+#endif
+#endif /* TFM_ENABLE_IRQ_TEST */
+
+#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
+ block TFM_SP_SECURE_CLIENT_2_LINKER_DATA,
+
+#if defined (TFM_PSA_API)
+ block TFM_SP_SECURE_CLIENT_2_LINKER_STACK,
+#endif
+#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
+
+#ifdef TFM_MULTI_CORE_TEST
+ block TFM_SP_MULTI_CORE_TEST_LINKER_DATA,
+
+#if defined (TFM_PSA_API)
+ block TFM_SP_MULTI_CORE_TEST_LINKER_STACK,
+#endif
+#endif /* TFM_MULTI_CORE_TEST */
+
+ /*
+ * This empty, zero long execution region is here to mark the end address
+ * of APP RoT RW and Stack.
+ */
+ block TFM_APP_RW_STACK_END,
+
+#ifdef TFM_MULTI_CORE_TOPOLOGY
+#ifdef S_DATA_PRIV_START
+ /**** Privileged data area base address specified by multi-core platform */
+ block TFM_SECURE_PRIV_DATA_BOUNDARY,
+ #endif
+
+ /*
+ * Move BL2 shared area and MSP stack to the beginning of privileged data
+ * area in multi-core topology.
+ */
+ /* Shared area between BL2 and runtime to exchange data */
+ overlay STACK_DATA,
+ /* PSP is privileged in multi-core topology */
+ block ARM_LIB_STACK,
+#endif
+
+ overlay HEAP_OVL,
+
+ block ER_TFM_DATA,
+
+ /**** PSA RoT DATA start here */
+ /*
+ * This empty, zero long execution region is here to mark the start address
+ * of PSA RoT RW and Stack.
+ */
+ block TFM_PSA_RW_STACK_START,
+
+#ifdef TFM_PARTITION_SECURE_STORAGE
+ block TFM_SP_STORAGE_LINKER_DATA,
+
+#if defined (TFM_PSA_API)
+ block TFM_SP_STORAGE_LINKER_STACK,
+#endif
+#endif /* TFM_PARTITION_SECURE_STORAGE */
+
+#ifdef TFM_PARTITION_INTERNAL_TRUSTED_STORAGE
+ block TFM_SP_ITS_LINKER_DATA,
+
+#if defined (TFM_PSA_API)
+ block TFM_SP_ITS_LINKER_STACK,
+#endif
+#endif /* TFM_PARTITION_INTERNAL_TRUSTED_STORAGE */
+
+#ifdef TFM_PARTITION_AUDIT_LOG
+ block TFM_SP_AUDIT_LOG_LINKER_DATA,
+
+#if defined (TFM_PSA_API)
+ block TFM_SP_AUDIT_LOG_LINKER_STACK,
+#endif
+#endif /* TFM_PARTITION_AUDIT_LOG */
+
+#ifdef TFM_PARTITION_CRYPTO
+ block TFM_SP_CRYPTO_LINKER_DATA,
+
+#if defined (TFM_PSA_API)
+ block TFM_SP_CRYPTO_LINKER_STACK,
+#endif
+#endif /* TFM_PARTITION_CRYPTO */
+
+#ifdef TFM_PARTITION_PLATFORM
+ block TFM_SP_PLATFORM_LINKER_DATA,
+
+#if defined (TFM_PSA_API)
+ block TFM_SP_PLATFORM_LINKER_STACK,
+#endif
+#endif /* TFM_PARTITION_PLATFORM */
+
+#ifdef TFM_PARTITION_INITIAL_ATTESTATION
+ block TFM_SP_INITIAL_ATTESTATION_LINKER_DATA,
+
+#if defined (TFM_PSA_API)
+ block TFM_SP_INITIAL_ATTESTATION_LINKER_STACK,
+#endif
+#endif /* TFM_PARTITION_INITIAL_ATTESTATION */
+
+#ifdef TFM_PARTITION_TEST_CORE
+ block TFM_SP_CORE_TEST_LINKER_DATA,
+
+#if defined (TFM_PSA_API)
+ block TFM_SP_CORE_TEST_LINKER_STACK,
+#endif
+#endif /* TFM_PARTITION_TEST_CORE */
+
+#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
+ block TFM_SP_SECURE_TEST_PARTITION_LINKER_DATA,
+
+#if defined (TFM_PSA_API)
+ block TFM_SP_SECURE_TEST_PARTITION_LINKER_STACK,
+#endif
+#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
+
+#ifdef TFM_PARTITION_TEST_CORE_IPC
+ block TFM_SP_IPC_SERVICE_TEST_LINKER_DATA,
+
+#if defined (TFM_PSA_API)
+ block TFM_SP_IPC_SERVICE_TEST_LINKER_STACK,
+#endif
+#endif /* TFM_PARTITION_TEST_CORE_IPC */
+
+#ifdef TFM_PARTITION_TEST_SST
+ block TFM_SP_SST_TEST_LINKER_DATA,
+
+#if defined (TFM_PSA_API)
+ block TFM_SP_SST_TEST_LINKER_STACK,
+#endif
+#endif /* TFM_PARTITION_TEST_SST */
+
+ /*
+ * This empty, zero long execution region is here to mark the end address
+ * of PSA RoT RW and Stack.
+ */
+ block TFM_PSA_RW_STACK_END,
+
+#if 0
+#if defined (S_RAM_CODE_START)
+ /* Executable code allocated in RAM */
+ TFM_RAM_CODE S_RAM_CODE_START {
+ * (.ramfunc)
+ }
+#endif
+#endif
+
+ /* This empty, zero long execution region is here to mark the limit address
+ * of the last execution region that is allocated in SRAM.
+ */
+ block SRAM_WATERMARK,
+
+ /* Make sure that the sections allocated in the SRAM does not exceed the
+ * size of the SRAM available.
+ */
+};
+
+#ifndef TFM_MULTI_CORE_TOPOLOGY
+ /*
+ * Place the CMSE Veneers (containing the SG instruction) in a separate
+ * 32 bytes aligned region so that the SAU can be programmed to
+ * just set this region as Non-Secure Callable.
+ */
+define block LR_VENEER with alignment = 0x20, size = CMSE_VENEER_REGION_SIZE {section Veneer$$CMSE};
+place at address CMSE_VENEER_REGION_START {block LR_VENEER};
+#endif
+
+ /* Reserved place for NS application.
+ * No code will be placed here, just address of this region is used in the
+ * secure code to configure certain HW components. This generates an empty
+ * execution region description warning during linking.
+ */
+define block LR_NS_PARTITION with size = NS_PARTITION_SIZE { };
+place at address NS_PARTITION_START { block LR_NS_PARTITION };
+
+#ifdef BL2
+ /* Reserved place for new image in case of firmware upgrade.
+ * No code will be placed here, just address of this region is used in the
+ * secure code to configure certain HW components. This generates an empty
+ * execution region description warning during linking.
+ */
+define block LR_SECONDARY_PARTITION with size = SECONDARY_PARTITION_SIZE { };
+place at address SECONDARY_PARTITION_START { block LR_SECONDARY_PARTITION };
+#endif /* BL2 */
+
+place in S_RAM_region { block DATA };
diff --git a/platform/ext/common/iar/tfm_common_s.icf.template b/platform/ext/common/iar/tfm_common_s.icf.template
new file mode 100644
index 0000000..288dccb
--- /dev/null
+++ b/platform/ext/common/iar/tfm_common_s.icf.template
@@ -0,0 +1,468 @@
+/*
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * This file is derivative of ../armclang/tfm_common_s.sct.template
+ */
+
+{{utilities.donotedit_warning}}
+
+#include "region_defs.h"
+
+define memory mem with size = 4G;
+
+define region S_CODE_region = mem:[from S_CODE_START size S_CODE_SIZE];
+
+define region S_RAM_region = mem:[from S_DATA_START size S_DATA_SIZE];
+
+define block ER_TFM_CODE with fixed order, alignment = 8 {readonly section .intvec, readonly};
+
+define block TFM_UNPRIV_CODE with alignment = 32 {
+ ro object tfm_spm_services.o,
+ ro object platform_retarget_dev.o,
+ ro object device_definition.o,
+ section SFN,
+ ro section .rodata object tfm_its_secure_api.o,
+ ro object *7M_tl*.a,
+ ro object *libtfmsprt.a
+ };
+
+ /**** PSA RoT RO part (CODE + RODATA) start here */
+ /*
+ * This empty, zero long execution region is here to mark the start address
+ * of PSA RoT code.
+ */
+define block TFM_PSA_CODE_START with alignment = 32, size = 0 { };
+
+{% for manifest in manifests %}
+ {% if manifest.manifest.type == 'PSA-ROT' %}
+ {% if manifest.attr.conditional %}
+#ifdef {{manifest.attr.conditional}}
+ {% endif %}
+define block {{manifest.manifest.name}}_LINKER with alignment = 32 {
+ {% if manifest.attr.linker_pattern.library_list %}
+ {% for pattern in manifest.attr.linker_pattern.library_list %}
+ ro object {{pattern}},
+ {% endfor %}
+ {% endif %}
+ {% if manifest.attr.linker_pattern.object_list %}
+ {% for pattern in manifest.attr.linker_pattern.object_list %}
+ ro object {{pattern}},
+ {% endfor %}
+ {% endif %}
+ section {{manifest.manifest.name}}_ATTR_FN
+ };
+ {% if manifest.attr.conditional %}
+#endif /* {{manifest.attr.conditional}} */
+ {% endif %}
+
+ {% endif %}
+{% endfor %}
+ /*
+ * This empty, zero long execution region is here to mark the end address
+ * of PSA RoT code.
+ */
+define block TFM_PSA_CODE_END with alignment = 32, size = 0 { };
+
+ /**** APPLICATION RoT RO part (CODE + RODATA) start here */
+ /*
+ * This empty, zero long execution region is here to mark the start address
+ * of APP RoT code.
+ */
+define block TFM_APP_CODE_START with alignment = 32, size = 0 { };
+
+{% for manifest in manifests %}
+ {% if manifest.manifest.type == 'APPLICATION-ROT' %}
+ {% if manifest.attr.conditional %}
+#ifdef {{manifest.attr.conditional}}
+ {% endif %}
+define block {{manifest.manifest.name}}_LINKER with alignment = 32 {
+ {% if manifest.attr.linker_pattern.library_list %}
+ {% for pattern in manifest.attr.linker_pattern.library_list %}
+ ro object {{pattern}},
+ {% endfor %}
+ {% endif %}
+ {% if manifest.attr.linker_pattern.object_list %}
+ {% for pattern in manifest.attr.linker_pattern.object_list %}
+ ro object {{pattern}},
+ {% endfor %}
+ {% endif %}
+ };
+ {% if manifest.attr.conditional %}
+#endif /* {{manifest.attr.conditional}} */
+ {% endif %}
+
+ {% endif %}
+{% endfor %}
+ /*
+ * This empty, zero long execution region is here to mark the end address
+ * of APP RoT code.
+ */
+define block TFM_APP_CODE_END with alignment = 32, size = 0 { };
+
+ /**** Base address of secure data area */
+define block TFM_SECURE_DATA_START with size = 0 { };
+
+#if !TFM_MULTI_CORE_TOPOLOGY
+ /* Shared area between BL2 and runtime to exchange data */
+define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { };
+define block ARM_LIB_STACK_MSP with alignment = 32, size = S_MSP_STACK_SIZE { };
+define overlay STACK_DATA {block TFM_SHARED_DATA};
+define overlay STACK_DATA {block ARM_LIB_STACK_MSP};
+
+define block ARM_LIB_STACK with alignment = 32, size = S_PSP_STACK_SIZE { };
+#endif
+
+#if !defined(TFM_PSA_API)
+define block TFM_SECURE_STACK with size = 0x2000, alignment = 128 {};
+#endif /* !defined(TFM_PSA_API) */
+
+define block TFM_UNPRIV_DATA with alignment = 32 {
+ rw object tfm_spm_services.o,
+ rw object platform_retarget_dev.o,
+ rw object device_definition.o,
+ };
+
+define block TFM_APP_RW_STACK_START with alignment = 32, size = 0 { };
+
+{% for manifest in manifests %}
+ {% if manifest.manifest.type == 'APPLICATION-ROT' %}
+ {% if manifest.attr.conditional %}
+#ifdef {{manifest.attr.conditional}}
+ {% endif %}
+define block {{manifest.manifest.name}}_LINKER_DATA with alignment = 32 {
+ {% if manifest.attr.linker_pattern.library_list %}
+ {% for pattern in manifest.attr.linker_pattern.library_list %}
+ rw object {{pattern}},
+ {% endfor %}
+ {% endif %}
+ {% if manifest.attr.linker_pattern.object_list %}
+ {% for pattern in manifest.attr.linker_pattern.object_list %}
+ rw object {{pattern}},
+ {% endfor %}
+ {% endif %}
+ };
+
+ {% if manifest.attr.tfm_partition_ipc %}
+#if defined (TFM_PSA_API)
+define block {{manifest.manifest.name}}_LINKER_STACK with alignment = 128, size = {{manifest.manifest.stack_size}} { };
+#endif
+ {% else %}
+#if defined (TFM_PSA_API)
+define block {{manifest.manifest.name}}_LINKER_STACK with alignment = 128 { };
+#endif
+ {% endif %}
+ {% if manifest.attr.conditional %}
+#endif /* {{manifest.attr.conditional}} */
+ {% endif %}
+
+ {% endif %}
+{% endfor %}
+
+ /*
+ * This empty, zero long execution region is here to mark the end address
+ * of APP RoT RW and Stack.
+ */
+define block TFM_APP_RW_STACK_END with alignment = 32, size = 0 { };
+
+#if TFM_MULTI_CORE_TOPOLOGY && defined(S_DATA_PRIV_START)
+ /**** Privileged data area base address specified by multi-core platform */
+define block TFM_SECURE_PRIV_DATA_BOUNDARY with size = 0 { };
+#endif
+
+#if TFM_MULTI_CORE_TOPOLOGY
+ /*
+ * Move BL2 shared area and MSP stack to the beginning of privileged data
+ * area in multi-core topology.
+ */
+ /* Shared area between BL2 and runtime to exchange data */
+define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { };
+
+ /* MSP */
+define block ARM_LIB_STACK_MSP with alignment = 32, size = S_MSP_STACK_SIZE { };
+
+define overlay STACK_DATA {block TFM_SHARED_DATA};
+define overlay STACK_DATA {block ARM_LIB_STACK_MSP};
+
+ /* PSP is privileged in multi-core topology */
+define block ARM_LIB_STACK with alignment = 32, size = S_PSP_STACK_SIZE { };
+#endif
+
+define block HEAP with alignment = 8, size = S_HEAP_SIZE { };
+define block ARM_LIB_HEAP with alignment = 8, size = S_HEAP_SIZE { };
+define overlay HEAP_OVL {block HEAP};
+define overlay HEAP_OVL {block ARM_LIB_HEAP};
+
+define block ER_TFM_DATA with alignment = 8 {readwrite};
+
+ /**** PSA RoT DATA start here */
+ /*
+ * This empty, zero long execution region is here to mark the start address
+ * of PSA RoT RW and Stack.
+ */
+define block TFM_PSA_RW_STACK_START with alignment = 32, size = 0 { };
+
+{% for manifest in manifests %}
+ {% if manifest.manifest.type == 'PSA-ROT' %}
+ {% if manifest.attr.conditional %}
+#ifdef {{manifest.attr.conditional}}
+ {% endif %}
+define block {{manifest.manifest.name}}_LINKER_DATA with alignment = 32 {
+ {% if manifest.attr.linker_pattern.library_list %}
+ {% for pattern in manifest.attr.linker_pattern.library_list %}
+ rw object {{pattern}},
+ {% endfor %}
+ {% endif %}
+ {% if manifest.attr.linker_pattern.object_list %}
+ {% for pattern in manifest.attr.linker_pattern.object_list %}
+ rw object {{pattern}},
+ {% endfor %}
+ {% endif %}
+ };
+
+ {% if manifest.attr.tfm_partition_ipc %}
+#if defined (TFM_PSA_API)
+define block {{manifest.manifest.name}}_LINKER_STACK with alignment = 128, size = {{manifest.manifest.stack_size}} { };
+#endif
+ {% else %}
+#if defined (TFM_PSA_API)
+define block {{manifest.manifest.name}}_LINKER_STACK with alignment = 128, size = 0 { };
+#endif
+ {% endif %}
+ {% if manifest.attr.conditional %}
+#endif /* {{manifest.attr.conditional}} */
+ {% endif %}
+
+ {% endif %}
+{% endfor %}
+
+ /*
+ * This empty, zero long execution region is here to mark the end address
+ * of PSA RoT RW and Stack.
+ */
+define block TFM_PSA_RW_STACK_END with alignment = 32, size = 0x0 { };
+
+ /* This empty, zero long execution region is here to mark the limit address
+ * of the last execution region that is allocated in SRAM.
+ */
+define block SRAM_WATERMARK with size = 0 { };
+
+define block LR_CODE with fixed order {
+ block ER_TFM_CODE,
+ block TFM_UNPRIV_CODE,
+ block TFM_PSA_CODE_START,
+
+{% for manifest in manifests %}
+ {% if manifest.manifest.type == 'PSA-ROT' %}
+ {% if manifest.attr.conditional %}
+#ifdef {{manifest.attr.conditional}}
+ {% endif %}
+ block {{manifest.manifest.name}}_LINKER,
+ {% if manifest.attr.conditional %}
+#endif /* {{manifest.attr.conditional}} */
+ {% endif %}
+ {% endif %}
+{% endfor %}
+
+ block TFM_PSA_CODE_END,
+
+/**** APPLICATION RoT RO part (CODE + RODATA) start here */
+ /*
+ * This empty, zero long execution region is here to mark the start address
+ * of APP RoT code.
+ */
+ block TFM_APP_CODE_START,
+{% for manifest in manifests %}
+ {% if manifest.manifest.type == 'APPLICATION-ROT' %}
+ {% if manifest.attr.conditional %}
+#ifdef {{manifest.attr.conditional}}
+ {% endif %}
+ block {{manifest.manifest.name}}_LINKER,
+ {% if manifest.attr.conditional %}
+#endif /* {{manifest.attr.conditional}} */
+ {% endif %}
+
+ {% endif %}
+{% endfor %}
+ /*
+ * This empty, zero long execution region is here to mark the end address
+ * of APP RoT code.
+ */
+ block TFM_APP_CODE_END,
+ };
+
+do not initialize { section .noinit };
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy { section __DLIB_PERTHREAD };
+}
+
+place in S_CODE_region { block LR_CODE };
+
+define block DATA with fixed order {
+ /**** Base address of secure data area */
+ block TFM_SECURE_DATA_START,
+
+ /*
+ * MPU on Armv6-M/v7-M core in multi-core topology may require more strict
+ * alignment that MPU region base address must align with the MPU region
+ * size.
+ * As a result, in multi-core topology, to save memory resource and MPU
+ * regions, unprivileged data sections and privileged data sections are
+ * separated and gathered in unprivileged/privileged data area respectively.
+ * Keep BL2 shared data and MSP stack at the beginning of the secure data
+ * area in single Armv8-M topology, while move the two areas to the
+ * beginning of privileged data region in multi-core topology.
+ */
+#ifndef TFM_MULTI_CORE_TOPOLOGY
+ /* Shared area between BL2 and runtime to exchange data */
+ overlay STACK_DATA,
+ /* PSP is unprivileged in single-core topology */
+ block ARM_LIB_STACK,
+#endif
+
+#if !defined(TFM_PSA_API)
+ block TFM_SECURE_STACK,
+#endif /* !defined(TFM_PSA_API) */
+
+ block TFM_UNPRIV_DATA,
+
+ /**** APP RoT DATA start here */
+ /*
+ * This empty, zero long execution region is here to mark the start address
+ * of APP RoT RW and Stack.
+ */
+ block TFM_APP_RW_STACK_START,
+
+{% for manifest in manifests %}
+ {% if manifest.manifest.type == 'APPLICATION-ROT' %}
+ {% if manifest.attr.conditional %}
+#ifdef {{manifest.attr.conditional}}
+ {% endif %}
+ block {{manifest.manifest.name}}_LINKER_DATA,
+
+#if defined (TFM_PSA_API)
+ block {{manifest.manifest.name}}_LINKER_STACK,
+#endif
+ {% if manifest.attr.conditional %}
+#endif /* {{manifest.attr.conditional}} */
+ {% endif %}
+
+ {% endif %}
+{% endfor %}
+ /*
+ * This empty, zero long execution region is here to mark the end address
+ * of APP RoT RW and Stack.
+ */
+ block TFM_APP_RW_STACK_END,
+
+#ifdef TFM_MULTI_CORE_TOPOLOGY
+#ifdef S_DATA_PRIV_START
+ /**** Privileged data area base address specified by multi-core platform */
+ block TFM_SECURE_PRIV_DATA_BOUNDARY,
+ #endif
+
+ /*
+ * Move BL2 shared area and MSP stack to the beginning of privileged data
+ * area in multi-core topology.
+ */
+ /* Shared area between BL2 and runtime to exchange data */
+ overlay STACK_DATA,
+ /* PSP is privileged in multi-core topology */
+ block ARM_LIB_STACK,
+#endif
+
+ overlay HEAP_OVL,
+
+ block ER_TFM_DATA,
+
+ /**** PSA RoT DATA start here */
+ /*
+ * This empty, zero long execution region is here to mark the start address
+ * of PSA RoT RW and Stack.
+ */
+ block TFM_PSA_RW_STACK_START,
+
+{% for manifest in manifests %}
+ {% if manifest.manifest.type == 'PSA-ROT' %}
+ {% if manifest.attr.conditional %}
+#ifdef {{manifest.attr.conditional}}
+ {% endif %}
+ block {{manifest.manifest.name}}_LINKER_DATA,
+
+#if defined (TFM_PSA_API)
+ block {{manifest.manifest.name}}_LINKER_STACK,
+#endif
+ {% if manifest.attr.conditional %}
+#endif /* {{manifest.attr.conditional}} */
+ {% endif %}
+
+ {% endif %}
+{% endfor %}
+ /*
+ * This empty, zero long execution region is here to mark the end address
+ * of PSA RoT RW and Stack.
+ */
+ block TFM_PSA_RW_STACK_END,
+
+#if 0
+#if defined (S_RAM_CODE_START)
+ /* Executable code allocated in RAM */
+ TFM_RAM_CODE S_RAM_CODE_START {
+ * (.ramfunc)
+ }
+#endif
+#endif
+
+ /* This empty, zero long execution region is here to mark the limit address
+ * of the last execution region that is allocated in SRAM.
+ */
+ block SRAM_WATERMARK,
+
+ /* Make sure that the sections allocated in the SRAM does not exceed the
+ * size of the SRAM available.
+ */
+};
+
+#ifndef TFM_MULTI_CORE_TOPOLOGY
+ /*
+ * Place the CMSE Veneers (containing the SG instruction) in a separate
+ * 32 bytes aligned region so that the SAU can be programmed to
+ * just set this region as Non-Secure Callable.
+ */
+define block LR_VENEER with alignment = 0x20, size = CMSE_VENEER_REGION_SIZE {section Veneer$$CMSE};
+place at address CMSE_VENEER_REGION_START {block LR_VENEER};
+#endif
+
+ /* Reserved place for NS application.
+ * No code will be placed here, just address of this region is used in the
+ * secure code to configure certain HW components. This generates an empty
+ * execution region description warning during linking.
+ */
+define block LR_NS_PARTITION with size = NS_PARTITION_SIZE { };
+place at address NS_PARTITION_START { block LR_NS_PARTITION };
+
+#ifdef BL2
+ /* Reserved place for new image in case of firmware upgrade.
+ * No code will be placed here, just address of this region is used in the
+ * secure code to configure certain HW components. This generates an empty
+ * execution region description warning during linking.
+ */
+define block LR_SECONDARY_PARTITION with size = SECONDARY_PARTITION_SIZE { };
+place at address SECONDARY_PARTITION_START { block LR_SECONDARY_PARTITION };
+#endif /* BL2 */
+
+place in S_RAM_region { block DATA };
diff --git a/platform/ext/musca_a.cmake b/platform/ext/musca_a.cmake
index d8422c5..ad7c423 100644
--- a/platform/ext/musca_a.cmake
+++ b/platform/ext/musca_a.cmake
@@ -29,6 +29,14 @@
# not all project defines CMSIS_5_DIR, only the ones that use it.
set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a")
endif()
+elseif(COMPILER STREQUAL "IARARM")
+ set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/common/iar/tfm_common_s.icf")
+ set (BL2_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/musca_a/Device/Source/iar/musca_bl2.icf")
+ set (NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/musca_a/Device/Source/iar/musca_ns.icf")
+ if (DEFINED CMSIS_5_DIR)
+ # not all project defines CMSIS_5_DIR, only the ones that use it.
+ set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a")
+ endif()
else()
message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
endif()
@@ -111,6 +119,10 @@
list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_bl2.S")
set_property(SOURCE "${ALL_SRC_ASM_S}" "${ALL_SRC_ASM_NS}" "${ALL_SRC_ASM_BL2}" APPEND
PROPERTY COMPILE_DEFINITIONS "__STARTUP_CLEAR_BSS_MULTIPLE" "__STARTUP_COPY_MULTIPLE")
+ elseif(CMAKE_C_COMPILER_ID STREQUAL "IARARM")
+ list(APPEND ALL_SRC_ASM_S "${PLATFORM_DIR}/target/musca_a/Device/Source/iar/startup_cmsdk_musca_s.s")
+ list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/musca_a/Device/Source/iar/startup_cmsdk_musca_ns.s")
+ list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/musca_a/Device/Source/iar/startup_cmsdk_musca_bl2.s")
else()
message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
endif()
diff --git a/platform/ext/target/musca_a/Device/Source/iar/musca_bl2.icf b/platform/ext/target/musca_a/Device/Source/iar/musca_bl2.icf
new file mode 100644
index 0000000..236033e
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/iar/musca_bl2.icf
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2020 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of ../armclang/musca_bl2.sct
+ */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+define memory mem with size = 4G;
+
+define region BL2_CODE_region = mem:[from BL2_CODE_START size BL2_CODE_SIZE];
+define region S_CODE_region = mem:[from S_CODE_START size S_CODE_SIZE];
+define region NS_CODE_region = mem:[from NS_CODE_START size NS_CODE_SIZE];
+
+define region BL2_RAM_region = mem:[from BL2_DATA_START size BL2_DATA_SIZE];
+define region S_RAM_region = mem:[from S_DATA_START size S_DATA_SIZE];
+define region NS_RAM_region = mem:[from NS_DATA_START size NS_DATA_SIZE];
+
+initialize by copy with packing = none { readonly, readwrite }
+ except{ section .rst_handler,
+ section .intvec,
+ ro object startup_cmsdk_musca_bl2.o*,
+ ro object system_core_init.o,
+ ro object cstartup_M.o,
+ ro object low_level_init.o,
+ ro object data_init.o,
+ ro object zero_init3.o,
+ ro object copy_init3.o,
+ ro object cmain.o};
+
+define block ER_CODE with fixed order, alignment = 8 {
+ section .intvec,
+ readonly
+ };
+
+define block ER_CODE_SRAM with fixed order, alignment = 8 {
+ rw section .text,
+ rw section .rodata
+ };
+place at address BL2_CODE_SRAM_BASE {block ER_CODE_SRAM};
+
+define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { };
+keep {block TFM_SHARED_DATA};
+
+define block ER_DATA with maximum size = BL2_DATA_SIZE, alignment = 32 {readwrite};
+ /* MSP */
+
+define block ARM_LIB_STACK with alignment = 32, size = BL2_MSP_STACK_SIZE { };
+define block HEAP with alignment = 8, size = BL2_HEAP_SIZE { };
+define block ARM_LIB_HEAP with alignment = 8, size = BL2_HEAP_SIZE { };
+define overlay HEAP_OVL {block HEAP};
+define overlay HEAP_OVL {block ARM_LIB_HEAP};
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+define block LR_CODE with fixed order {block ER_CODE};
+define block DATA with fixed order {block TFM_SHARED_DATA,
+ block ER_DATA,
+ block ARM_LIB_STACK,
+ overlay HEAP_OVL};
+
+place in BL2_CODE_region { block LR_CODE };
+place in BL2_RAM_region { block DATA};
diff --git a/platform/ext/target/musca_a/Device/Source/iar/musca_ns.icf b/platform/ext/target/musca_a/Device/Source/iar/musca_ns.icf
new file mode 100644
index 0000000..79907e8
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/iar/musca_ns.icf
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2020 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of ../armclang/musca_ns.sct
+ */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+define memory mem with size = 4G;
+
+define region S_CODE_region = mem:[from S_CODE_START size S_CODE_SIZE];
+define region NS_CODE_region = mem:[from NS_CODE_START size NS_CODE_SIZE];
+
+define region S_RAM_region = mem:[from S_DATA_START size S_DATA_SIZE];
+define region NS_RAM_region = mem:[from NS_DATA_START size NS_DATA_SIZE];
+
+define block ARM_LIB_STACK_MSP with alignment = 8, size = NS_MSP_STACK_SIZE { };
+define block ARM_LIB_STACK with alignment = 8, size = NS_PSP_STACK_SIZE { };
+define block HEAP with alignment = 8, size = NS_HEAP_SIZE { };
+define block ARM_LIB_HEAP with alignment = 8, size = NS_HEAP_SIZE { };
+define overlay HEAP_OVL {block HEAP};
+define overlay HEAP_OVL {block ARM_LIB_HEAP};
+
+define block ER_CODE with fixed order, alignment = 8 {
+ section .intvec,
+ readonly};
+
+define block ER_DATA with alignment = 8 {readwrite};
+
+do not initialize { section .noinit };
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+define block LR_CODE with fixed order {block ER_CODE};
+define block DATA with fixed order {block ER_DATA,
+ block ARM_LIB_STACK_MSP,
+ block ARM_LIB_STACK,
+ overlay HEAP_OVL};
+
+place in NS_CODE_region { block LR_CODE };
+place in NS_RAM_region { block DATA };
diff --git a/platform/ext/target/musca_a/Device/Source/iar/startup_cmsdk_musca_bl2.s b/platform/ext/target/musca_a/Device/Source/iar/startup_cmsdk_musca_bl2.s
new file mode 100644
index 0000000..47f4768
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/iar/startup_cmsdk_musca_bl2.s
@@ -0,0 +1,250 @@
+;/*
+; * Copyright (c) 2017-2020 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.01 startup_ARMv8MML.s
+; Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION ARM_LIB_STACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+ DATA
+
+
+__vector_table ;Core Interrupts
+ DCD sfe(ARM_LIB_STACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ;SSE-200 Interrupts
+ DCD NS_WATCHDOG_RESET_IRQHandler ; 0: Non-Secure Watchdog Reset Request Interrupt
+ DCD NS_WATCHDOG_IRQHandler ; 1: Non-Secure Watchdog Interrupt
+ DCD S32K_TIMER_IRQHandler ; 2: S32K Timer Interrupt
+ DCD TIMER0_IRQHandler ; 3: CMSDK Timer 0 Interrupt
+ DCD TIMER1_IRQHandler ; 4: CMSDK Timer 1 Interrupt
+ DCD DUALTIMER_IRQHandler ; 5: CMSDK Dual Timer Interrupt
+ DCD MHU0_IRQHandler ; 6: Message Handling Unit 0 Interrupt
+ DCD MHU1_IRQHandler ; 7: Message Handling Unit 1 Interrupt
+ DCD CRYPTOCELL_IRQHandler ; 8: CryptoCell-312 Interrupt
+ DCD MPC_Handler ; 9: Secure Combined MPC Interrupt
+ DCD PPC_Handler ; 10: Secure Combined PPC Interrupt
+ DCD S_MSC_COMBINED_IRQHandler ; 11: Secure Combined MSC Interrupt
+ DCD S_BRIDGE_ERR_IRQHandler ; 12: Secure Bridge Error Combined Interrupt
+ DCD I_CACHE_INV_ERR_IRQHandler ; 13: Intsruction Cache Invalidation Interrupt
+ DCD 0 ; 14: Reserved
+ DCD SYS_PPU_IRQHandler ; 15: System PPU Interrupt
+ DCD CPU0_PPU_IRQHandler ; 16: CPU0 PPU Interrupt
+ DCD CPU1_PPU_IRQHandler ; 17: CPU1 PPU Interrupt
+ DCD CPU0_DGB_PPU_IRQHandler ; 18: CPU0 Debug PPU Interrupt
+ DCD CPU1_DGB_PPU_IRQHandler ; 19: CPU1 Debug PPU Interrupt
+ DCD CRYPTOCELL_PPU_IRQHandler ; 20: CryptoCell PPU Interrupt
+ DCD 0 ; 21: Reserved
+ DCD RAM0_PPU_IRQHandler ; 22: RAM 0 PPU Interrupt
+ DCD RAM1_PPU_IRQHandler ; 23: RAM 1 PPU Interrupt
+ DCD RAM2_PPU_IRQHandler ; 24: RAM 2 PPU Interrupt
+ DCD RAM3_PPU_IRQHandler ; 25: RAM 3 PPU Interrupt
+ DCD DEBUG_PPU_IRQHandler ; 26: Debug PPU Interrupt
+ DCD 0 ; 27: Reserved
+ DCD CPU0_CTI_IRQHandler ; 28: CPU0 CTI Interrupt
+ DCD CPU1_CTI_IRQHandler ; 29: CPU1 CTI Interrupt
+ DCD 0 ; 30: Reserved
+ DCD 0 ; 31: Reserved
+ ;Expansion Interrupts
+ DCD 0 ; 32: Reserved
+ DCD GpTimer_IRQHandler ; 33: General Purpose Timer
+ DCD I2C0_IRQHandler ; 34: I2C0
+ DCD I2C1_IRQHandler ; 35: I2C1
+ DCD I2S_IRQHandler ; 36: I2S
+ DCD SPI_IRQHandler ; 37: SPI
+ DCD QSPI_IRQHandler ; 38: QSPI
+ DCD UARTRX0_Handler ; 39: UART0 receive FIFO interrupt
+ DCD UARTTX0_Handler ; 40: UART0 transmit FIFO interrupt
+ DCD UART0_RxTimeout_IRQHandler ; 41: UART0 receive timeout interrupt
+ DCD UART0_ModemStatus_IRQHandler ; 42: UART0 modem status interrupt
+ DCD UART0_Error_IRQHandler ; 43: UART0 error interrupt
+ DCD UART0_IRQHandler ; 44: UART0 interrupt
+ DCD UARTRX1_Handler ; 45: UART0 receive FIFO interrupt
+ DCD UARTTX1_Handler ; 46: UART0 transmit FIFO interrupt
+ DCD UART1_RxTimeout_IRQHandler ; 47: UART0 receive timeout interrupt
+ DCD UART1_ModemStatus_IRQHandler ; 48: UART0 modem status interrupt
+ DCD UART1_Error_IRQHandler ; 49: UART0 error interrupt
+ DCD UART1_IRQHandler ; 50: UART0 interrupt
+ DCD GPIO_0_IRQHandler ; 51: GPIO 0 interrupt
+ DCD GPIO_1_IRQHandler ; 52: GPIO 1 interrupt
+ DCD GPIO_2_IRQHandler ; 53: GPIO 2 interrupt
+ DCD GPIO_3_IRQHandler ; 54: GPIO 3 interrupt
+ DCD GPIO_4_IRQHandler ; 55: GPIO 4 interrupt
+ DCD GPIO_5_IRQHandler ; 56: GPIO 5 interrupt
+ DCD GPIO_6_IRQHandler ; 57: GPIO 6 interrupt
+ DCD GPIO_7_IRQHandler ; 58: GPIO 7 interrupt
+ DCD GPIO_8_IRQHandler ; 59: GPIO 8 interrupt
+ DCD GPIO_9_IRQHandler ; 60: GPIO 9 interrupt
+ DCD GPIO_10_IRQHandler ; 61: GPIO 10 interrupt
+ DCD GPIO_11_IRQHandler ; 62: GPIO 11 interrupt
+ DCD GPIO_12_IRQHandler ; 63: GPIO 12 interrupt
+ DCD GPIO_13_IRQHandler ; 64: GPIO 13 interrupt
+ DCD GPIO_14_IRQHandler ; 65: GPIO 14 interrupt
+ DCD GPIO_15_IRQHandler ; 66: GPIO 15 interrupt
+ DCD Combined_IRQHandler ; 67: Combined interrupt
+ DCD PVT_IRQHandler ; 68: PVT sensor interrupt
+ DCD 0 ; 69: Reserved
+ DCD PWM_0_IRQHandler ; 70: PWM0 interrupt
+ DCD RTC_IRQHandler ; 71: RTC interrupt
+ DCD GpTimer0_IRQHandler ; 72: General Purpose Timer0
+ DCD GpTimer1_IRQHandler ; 73: General Purpose Timer1
+ DCD PWM_1_IRQHandler ; 74: PWM1 interrupt
+ DCD PWM_2_IRQHandler ; 75: PWM2 interrupt
+ DCD IOMUX_IRQHandler ; 76: IOMUX interrupt
+
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ CPSID i ; Disable IRQs
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+End_Of_Main
+ B .
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+Default_Handler MACRO handler_name
+ PUBWEAK handler_name
+handler_name
+ B .
+ ENDM
+
+ Default_Handler NMI_Handler
+ Default_Handler HardFault_Handler
+ Default_Handler MemManage_Handler
+ Default_Handler BusFault_Handler
+ Default_Handler UsageFault_Handler
+ Default_Handler SecureFault_Handler
+ Default_Handler SVC_Handler
+ Default_Handler DebugMon_Handler
+ Default_Handler PendSV_Handler
+ Default_Handler SysTick_Handler
+
+ Default_Handler NS_WATCHDOG_RESET_IRQHandler
+ Default_Handler NS_WATCHDOG_IRQHandler
+ Default_Handler S32K_TIMER_IRQHandler
+ Default_Handler TIMER0_IRQHandler
+ Default_Handler TIMER1_IRQHandler
+ Default_Handler DUALTIMER_IRQHandler
+ Default_Handler MHU0_IRQHandler
+ Default_Handler MHU1_IRQHandler
+ Default_Handler CRYPTOCELL_IRQHandler
+ Default_Handler MPC_Handler
+ Default_Handler PPC_Handler
+ Default_Handler S_MSC_COMBINED_IRQHandler
+ Default_Handler S_BRIDGE_ERR_IRQHandler
+ Default_Handler I_CACHE_INV_ERR_IRQHandler
+ Default_Handler SYS_PPU_IRQHandler
+ Default_Handler CPU0_PPU_IRQHandler
+ Default_Handler CPU1_PPU_IRQHandler
+ Default_Handler CPU0_DGB_PPU_IRQHandler
+ Default_Handler CPU1_DGB_PPU_IRQHandler
+ Default_Handler CRYPTOCELL_PPU_IRQHandler
+ Default_Handler RAM0_PPU_IRQHandler
+ Default_Handler RAM1_PPU_IRQHandler
+ Default_Handler RAM2_PPU_IRQHandler
+ Default_Handler RAM3_PPU_IRQHandler
+ Default_Handler DEBUG_PPU_IRQHandler
+ Default_Handler CPU0_CTI_IRQHandler
+ Default_Handler CPU1_CTI_IRQHandler
+
+ Default_Handler GpTimer_IRQHandler
+ Default_Handler I2C0_IRQHandler
+ Default_Handler I2C1_IRQHandler
+ Default_Handler I2S_IRQHandler
+ Default_Handler SPI_IRQHandler
+ Default_Handler QSPI_IRQHandler
+ Default_Handler UARTRX0_Handler
+ Default_Handler UARTTX0_Handler
+ Default_Handler UART0_RxTimeout_IRQHandler
+ Default_Handler UART0_ModemStatus_IRQHandler
+ Default_Handler UART0_Error_IRQHandler
+ Default_Handler UART0_IRQHandler
+ Default_Handler UARTRX1_Handler
+ Default_Handler UARTTX1_Handler
+ Default_Handler UART1_RxTimeout_IRQHandler
+ Default_Handler UART1_ModemStatus_IRQHandler
+ Default_Handler UART1_Error_IRQHandler
+ Default_Handler UART1_IRQHandler
+ Default_Handler GPIO_0_IRQHandler
+ Default_Handler GPIO_1_IRQHandler
+ Default_Handler GPIO_2_IRQHandler
+ Default_Handler GPIO_3_IRQHandler
+ Default_Handler GPIO_4_IRQHandler
+ Default_Handler GPIO_5_IRQHandler
+ Default_Handler GPIO_6_IRQHandler
+ Default_Handler GPIO_7_IRQHandler
+ Default_Handler GPIO_8_IRQHandler
+ Default_Handler GPIO_9_IRQHandler
+ Default_Handler GPIO_10_IRQHandler
+ Default_Handler GPIO_11_IRQHandler
+ Default_Handler GPIO_12_IRQHandler
+ Default_Handler GPIO_13_IRQHandler
+ Default_Handler GPIO_14_IRQHandler
+ Default_Handler GPIO_15_IRQHandler
+ Default_Handler Combined_IRQHandler
+ Default_Handler PVT_IRQHandler
+ Default_Handler PWM_0_IRQHandler
+ Default_Handler RTC_IRQHandler
+ Default_Handler GpTimer0_IRQHandler
+ Default_Handler GpTimer1_IRQHandler
+ Default_Handler PWM_1_IRQHandler
+ Default_Handler PWM_2_IRQHandler
+ Default_Handler IOMUX_IRQHandler
+
+ END
diff --git a/platform/ext/target/musca_a/Device/Source/iar/startup_cmsdk_musca_ns.s b/platform/ext/target/musca_a/Device/Source/iar/startup_cmsdk_musca_ns.s
new file mode 100644
index 0000000..fbcc409
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/iar/startup_cmsdk_musca_ns.s
@@ -0,0 +1,247 @@
+;/*
+; * Copyright (c) 2017-2020 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+;
+; This file is derivative of CMSIS V5.01 startup_ARMv8MML.s
+; Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+; */
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3)
+ SECTION ARM_LIB_STACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table ;Core Interrupts
+ DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ;SSE-200 Interrupts
+ DCD NS_WATCHDOG_RESET_IRQHandler ; 0: Non-Secure Watchdog Reset Request Interrupt
+ DCD NS_WATCHDOG_IRQHandler ; 1: Non-Secure Watchdog Interrupt
+ DCD S32K_TIMER_IRQHandler ; 2: S32K Timer Interrupt
+ DCD TIMER0_IRQHandler ; 3: CMSDK Timer 0 Interrupt
+ DCD TIMER1_Handler ; 4: CMSDK Timer 1 Interrupt
+ DCD DUALTIMER_IRQHandler ; 5: CMSDK Dual Timer Interrupt
+ DCD MHU0_IRQHandler ; 6: Message Handling Unit 0 Interrupt
+ DCD MHU1_IRQHandler ; 7: Message Handling Unit 1 Interrupt
+ DCD CRYPTOCELL_IRQHandler ; 8: CryptoCell-312 Interrupt
+ DCD 0 ; 9: Reserved
+ DCD 0 ; 10: Reserved
+ DCD 0 ; 11: Reserved
+ DCD 0 ; 12: Reserved
+ DCD I_CACHE_INV_ERR_IRQHandler ; 13: Intsruction Cache Invalidation Interrupt
+ DCD 0 ; 14: Reserved
+ DCD SYS_PPU_IRQHandler ; 15: System PPU Interrupt
+ DCD CPU0_PPU_IRQHandler ; 16: CPU0 PPU Interrupt
+ DCD CPU1_PPU_IRQHandler ; 17: CPU1 PPU Interrupt
+ DCD CPU0_DGB_PPU_IRQHandler ; 18: CPU0 Debug PPU Interrupt
+ DCD CPU1_DGB_PPU_IRQHandler ; 19: CPU1 Debug PPU Interrupt
+ DCD CRYPTOCELL_PPU_IRQHandler ; 20: CryptoCell PPU Interrupt
+ DCD 0 ; 21: Reserved
+ DCD RAM0_PPU_IRQHandler ; 22: RAM 0 PPU Interrupt
+ DCD RAM1_PPU_IRQHandler ; 23: RAM 1 PPU Interrupt
+ DCD RAM2_PPU_IRQHandler ; 24: RAM 2 PPU Interrupt
+ DCD RAM3_PPU_IRQHandler ; 25: RAM 3 PPU Interrupt
+ DCD DEBUG_PPU_IRQHandler ; 26: Debug PPU Interrupt
+ DCD 0 ; 27: Reserved
+ DCD CPU0_CTI_IRQHandler ; 28: CPU0 CTI Interrupt
+ DCD CPU1_CTI_IRQHandler ; 29: CPU1 CTI Interrupt
+ DCD 0 ; 30: Reserved
+ DCD 0 ; 31: Reserved
+ ;Expansion Interrupts
+ DCD 0 ; 32: Reserved
+ DCD GpTimer_IRQHandler ; 33: General Purpose Timer
+ DCD I2C0_IRQHandler ; 34: I2C0
+ DCD I2C1_IRQHandler ; 35: I2C1
+ DCD I2S_IRQHandler ; 36: I2S
+ DCD SPI_IRQHandler ; 37: SPI
+ DCD QSPI_IRQHandler ; 38: QSPI
+ DCD UARTRX0_Handler ; 39: UART0 receive FIFO interrupt
+ DCD UARTTX0_Handler ; 40: UART0 transmit FIFO interrupt
+ DCD UART0_RxTimeout_IRQHandler ; 41: UART0 receive timeout interrupt
+ DCD UART0_ModemStatus_IRQHandler ; 42: UART0 modem status interrupt
+ DCD UART0_Error_IRQHandler ; 43: UART0 error interrupt
+ DCD UART0_IRQHandler ; 44: UART0 interrupt
+ DCD UARTRX1_Handler ; 45: UART0 receive FIFO interrupt
+ DCD UARTTX1_Handler ; 46: UART0 transmit FIFO interrupt
+ DCD UART1_RxTimeout_IRQHandler ; 47: UART0 receive timeout interrupt
+ DCD UART1_ModemStatus_IRQHandler ; 48: UART0 modem status interrupt
+ DCD UART1_Error_IRQHandler ; 49: UART0 error interrupt
+ DCD UART1_IRQHandler ; 50: UART0 interrupt
+ DCD GPIO_0_IRQHandler ; 51: GPIO 0 interrupt
+ DCD GPIO_1_IRQHandler ; 52: GPIO 1 interrupt
+ DCD GPIO_2_IRQHandler ; 53: GPIO 2 interrupt
+ DCD GPIO_3_IRQHandler ; 54: GPIO 3 interrupt
+ DCD GPIO_4_IRQHandler ; 55: GPIO 4 interrupt
+ DCD GPIO_5_IRQHandler ; 56: GPIO 5 interrupt
+ DCD GPIO_6_IRQHandler ; 57: GPIO 6 interrupt
+ DCD GPIO_7_IRQHandler ; 58: GPIO 7 interrupt
+ DCD GPIO_8_IRQHandler ; 59: GPIO 8 interrupt
+ DCD GPIO_9_IRQHandler ; 60: GPIO 9 interrupt
+ DCD GPIO_10_IRQHandler ; 61: GPIO 10 interrupt
+ DCD GPIO_11_IRQHandler ; 62: GPIO 11 interrupt
+ DCD GPIO_12_IRQHandler ; 63: GPIO 12 interrupt
+ DCD GPIO_13_IRQHandler ; 64: GPIO 13 interrupt
+ DCD GPIO_14_IRQHandler ; 65: GPIO 14 interrupt
+ DCD GPIO_15_IRQHandler ; 66: GPIO 15 interrupt
+ DCD Combined_IRQHandler ; 67: Combined interrupt
+ DCD PVT_IRQHandler ; 68: PVT sensor interrupt
+ DCD 0 ; 69: Reserved
+ DCD PWM_0_IRQHandler ; 70: PWM0 interrupt
+ DCD RTC_IRQHandler ; 71: RTC interrupt
+ DCD GpTimer0_IRQHandler ; 72: General Purpose Timer0
+ DCD GpTimer1_IRQHandler ; 73: General Purpose Timer1
+ DCD PWM_1_IRQHandler ; 74: PWM1 interrupt
+ DCD PWM_2_IRQHandler ; 75: PWM2 interrupt
+ DCD IOMUX_IRQHandler ; 76: IOMUX interrupt
+
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =sfe(ARM_LIB_STACK) ; End of ARM_LIB_STACK
+ MSR PSP, R0
+ MRS R0, CONTROL ; Get control value
+ ORR R0, R0, #1 ; Select switch to non privileged mode
+ ORR R0, R0, #2 ; Select switch to PSP
+ MSR CONTROL, R0
+ LDR R0, =__iar_program_start
+ BX R0
+End_Of_Main
+ B .
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+Default_Handler MACRO handler_name
+ PUBWEAK handler_name
+handler_name
+ B .
+ ENDM
+
+ Default_Handler NMI_Handler
+ Default_Handler HardFault_Handler
+ Default_Handler MemManage_Handler
+ Default_Handler BusFault_Handler
+ Default_Handler UsageFault_Handler
+ Default_Handler SVC_Handler
+ Default_Handler DebugMon_Handler
+ Default_Handler PendSV_Handler
+ Default_Handler SysTick_Handler
+
+ Default_Handler NS_WATCHDOG_RESET_IRQHandler
+ Default_Handler NS_WATCHDOG_IRQHandler
+ Default_Handler S32K_TIMER_IRQHandler
+ Default_Handler TIMER0_IRQHandler
+ Default_Handler TIMER1_Handler
+ Default_Handler DUALTIMER_IRQHandler
+ Default_Handler MHU0_IRQHandler
+ Default_Handler MHU1_IRQHandler
+ Default_Handler CRYPTOCELL_IRQHandler
+ Default_Handler I_CACHE_INV_ERR_IRQHandler
+ Default_Handler SYS_PPU_IRQHandler
+ Default_Handler CPU0_PPU_IRQHandler
+ Default_Handler CPU1_PPU_IRQHandler
+ Default_Handler CPU0_DGB_PPU_IRQHandler
+ Default_Handler CPU1_DGB_PPU_IRQHandler
+ Default_Handler CRYPTOCELL_PPU_IRQHandler
+ Default_Handler RAM0_PPU_IRQHandler
+ Default_Handler RAM1_PPU_IRQHandler
+ Default_Handler RAM2_PPU_IRQHandler
+ Default_Handler RAM3_PPU_IRQHandler
+ Default_Handler DEBUG_PPU_IRQHandler
+ Default_Handler CPU0_CTI_IRQHandler
+ Default_Handler CPU1_CTI_IRQHandler
+
+ Default_Handler GpTimer_IRQHandler
+ Default_Handler I2C0_IRQHandler
+ Default_Handler I2C1_IRQHandler
+ Default_Handler I2S_IRQHandler
+ Default_Handler SPI_IRQHandler
+ Default_Handler QSPI_IRQHandler
+ Default_Handler UARTRX0_Handler
+ Default_Handler UARTTX0_Handler
+ Default_Handler UART0_RxTimeout_IRQHandler
+ Default_Handler UART0_ModemStatus_IRQHandler
+ Default_Handler UART0_Error_IRQHandler
+ Default_Handler UART0_IRQHandler
+ Default_Handler UARTRX1_Handler
+ Default_Handler UARTTX1_Handler
+ Default_Handler UART1_RxTimeout_IRQHandler
+ Default_Handler UART1_ModemStatus_IRQHandler
+ Default_Handler UART1_Error_IRQHandler
+ Default_Handler UART1_IRQHandler
+ Default_Handler GPIO_0_IRQHandler
+ Default_Handler GPIO_1_IRQHandler
+ Default_Handler GPIO_2_IRQHandler
+ Default_Handler GPIO_3_IRQHandler
+ Default_Handler GPIO_4_IRQHandler
+ Default_Handler GPIO_5_IRQHandler
+ Default_Handler GPIO_6_IRQHandler
+ Default_Handler GPIO_7_IRQHandler
+ Default_Handler GPIO_8_IRQHandler
+ Default_Handler GPIO_9_IRQHandler
+ Default_Handler GPIO_10_IRQHandler
+ Default_Handler GPIO_11_IRQHandler
+ Default_Handler GPIO_12_IRQHandler
+ Default_Handler GPIO_13_IRQHandler
+ Default_Handler GPIO_14_IRQHandler
+ Default_Handler GPIO_15_IRQHandler
+ Default_Handler Combined_IRQHandler
+ Default_Handler PVT_IRQHandler
+ Default_Handler PWM_0_IRQHandler
+ Default_Handler RTC_IRQHandler
+ Default_Handler GpTimer0_IRQHandler
+ Default_Handler GpTimer1_IRQHandler
+ Default_Handler PWM_1_IRQHandler
+ Default_Handler PWM_2_IRQHandler
+ Default_Handler IOMUX_IRQHandler
+
+ END
diff --git a/platform/ext/target/musca_a/Device/Source/iar/startup_cmsdk_musca_s.s b/platform/ext/target/musca_a/Device/Source/iar/startup_cmsdk_musca_s.s
new file mode 100644
index 0000000..439eecf
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/iar/startup_cmsdk_musca_s.s
@@ -0,0 +1,256 @@
+;/*
+; * Copyright (c) 2017-2020 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.01 startup_ARMv8MML.s
+; Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3)
+ SECTION ARM_LIB_STACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table ;Core Interrupts
+ DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ;SSE-200 Interrupts
+ DCD NS_WATCHDOG_RESET_IRQHandler ; 0: Non-Secure Watchdog Reset Request Interrupt
+ DCD NS_WATCHDOG_IRQHandler ; 1: Non-Secure Watchdog Interrupt
+ DCD S32K_TIMER_IRQHandler ; 2: S32K Timer Interrupt
+ DCD TFM_TIMER0_IRQ_Handler ; 3: CMSDK Timer 0 Interrupt
+ DCD TIMER1_IRQHandler ; 4: CMSDK Timer 1 Interrupt
+ DCD DUALTIMER_IRQHandler ; 5: CMSDK Dual Timer Interrupt
+ DCD MHU0_IRQHandler ; 6: Message Handling Unit 0 Interrupt
+ DCD MHU1_IRQHandler ; 7: Message Handling Unit 1 Interrupt
+ DCD CRYPTOCELL_IRQHandler ; 8: CryptoCell-312 Interrupt
+ DCD MPC_Handler ; 9: Secure Combined MPC Interrupt
+ DCD PPC_Handler ; 10: Secure Combined PPC Interrupt
+ DCD S_MSC_COMBINED_IRQHandler ; 11: Secure Combined MSC Interrupt
+ DCD S_BRIDGE_ERR_IRQHandler ; 12: Secure Bridge Error Combined Interrupt
+ DCD I_CACHE_INV_ERR_IRQHandler ; 13: Intsruction Cache Invalidation Interrupt
+ DCD 0 ; 14: Reserved
+ DCD SYS_PPU_IRQHandler ; 15: System PPU Interrupt
+ DCD CPU0_PPU_IRQHandler ; 16: CPU0 PPU Interrupt
+ DCD CPU1_PPU_IRQHandler ; 17: CPU1 PPU Interrupt
+ DCD CPU0_DGB_PPU_IRQHandler ; 18: CPU0 Debug PPU Interrupt
+ DCD CPU1_DGB_PPU_IRQHandler ; 19: CPU1 Debug PPU Interrupt
+ DCD CRYPTOCELL_PPU_IRQHandler ; 20: CryptoCell PPU Interrupt
+ DCD 0 ; 21: Reserved
+ DCD RAM0_PPU_IRQHandler ; 22: RAM 0 PPU Interrupt
+ DCD RAM1_PPU_IRQHandler ; 23: RAM 1 PPU Interrupt
+ DCD RAM2_PPU_IRQHandler ; 24: RAM 2 PPU Interrupt
+ DCD RAM3_PPU_IRQHandler ; 25: RAM 3 PPU Interrupt
+ DCD DEBUG_PPU_IRQHandler ; 26: Debug PPU Interrupt
+ DCD 0 ; 27: Reserved
+ DCD CPU0_CTI_IRQHandler ; 28: CPU0 CTI Interrupt
+ DCD CPU1_CTI_IRQHandler ; 29: CPU1 CTI Interrupt
+ DCD 0 ; 30: Reserved
+ DCD 0 ; 31: Reserved
+ ;Expansion Interrupts
+ DCD 0 ; 32: Reserved
+ DCD GpTimer_IRQHandler ; 33: General Purpose Timer
+ DCD I2C0_IRQHandler ; 34: I2C0
+ DCD I2C1_IRQHandler ; 35: I2C1
+ DCD I2S_IRQHandler ; 36: I2S
+ DCD SPI_IRQHandler ; 37: SPI
+ DCD QSPI_IRQHandler ; 38: QSPI
+ DCD UARTRX0_Handler ; 39: UART0 receive FIFO interrupt
+ DCD UARTTX0_Handler ; 40: UART0 transmit FIFO interrupt
+ DCD UART0_RxTimeout_IRQHandler ; 41: UART0 receive timeout interrupt
+ DCD UART0_ModemStatus_IRQHandler ; 42: UART0 modem status interrupt
+ DCD UART0_Error_IRQHandler ; 43: UART0 error interrupt
+ DCD UART0_IRQHandler ; 44: UART0 interrupt
+ DCD UARTRX1_Handler ; 45: UART0 receive FIFO interrupt
+ DCD UARTTX1_Handler ; 46: UART0 transmit FIFO interrupt
+ DCD UART1_RxTimeout_IRQHandler ; 47: UART0 receive timeout interrupt
+ DCD UART1_ModemStatus_IRQHandler ; 48: UART0 modem status interrupt
+ DCD UART1_Error_IRQHandler ; 49: UART0 error interrupt
+ DCD UART1_IRQHandler ; 50: UART0 interrupt
+ DCD GPIO_0_IRQHandler ; 51: GPIO 0 interrupt
+ DCD GPIO_1_IRQHandler ; 52: GPIO 1 interrupt
+ DCD GPIO_2_IRQHandler ; 53: GPIO 2 interrupt
+ DCD GPIO_3_IRQHandler ; 54: GPIO 3 interrupt
+ DCD GPIO_4_IRQHandler ; 55: GPIO 4 interrupt
+ DCD GPIO_5_IRQHandler ; 56: GPIO 5 interrupt
+ DCD GPIO_6_IRQHandler ; 57: GPIO 6 interrupt
+ DCD GPIO_7_IRQHandler ; 58: GPIO 7 interrupt
+ DCD GPIO_8_IRQHandler ; 59: GPIO 8 interrupt
+ DCD GPIO_9_IRQHandler ; 60: GPIO 9 interrupt
+ DCD GPIO_10_IRQHandler ; 61: GPIO 10 interrupt
+ DCD GPIO_11_IRQHandler ; 62: GPIO 11 interrupt
+ DCD GPIO_12_IRQHandler ; 63: GPIO 12 interrupt
+ DCD GPIO_13_IRQHandler ; 64: GPIO 13 interrupt
+ DCD GPIO_14_IRQHandler ; 65: GPIO 14 interrupt
+ DCD GPIO_15_IRQHandler ; 66: GPIO 15 interrupt
+ DCD Combined_IRQHandler ; 67: Combined interrupt
+ DCD PVT_IRQHandler ; 68: PVT sensor interrupt
+ DCD 0 ; 69: Reserved
+ DCD PWM_0_IRQHandler ; 70: PWM0 interrupt
+ DCD RTC_IRQHandler ; 71: RTC interrupt
+ DCD GpTimer0_IRQHandler ; 72: General Purpose Timer0
+ DCD GpTimer1_IRQHandler ; 73: General Purpose Timer1
+ DCD PWM_1_IRQHandler ; 74: PWM1 interrupt
+ DCD PWM_2_IRQHandler ; 75: PWM2 interrupt
+ DCD IOMUX_IRQHandler ; 76: IOMUX interrupt
+
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ CPSID i ; Disable IRQs
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK
+ MSR PSP, R0
+ MRS R0, control ; Get control value
+ ORR R0, R0, #2 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =__iar_program_start
+ BX R0
+End_Of_Main
+ B .
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+Default_Handler MACRO handler_name
+ PUBWEAK handler_name
+handler_name
+ B .
+ ENDM
+
+ Default_Handler NMI_Handler
+ Default_Handler HardFault_Handler
+ Default_Handler MemManage_Handler
+ Default_Handler BusFault_Handler
+ Default_Handler UsageFault_Handler
+ Default_Handler SecureFault_Handler
+ Default_Handler SVC_Handler
+ Default_Handler DebugMon_Handler
+ Default_Handler PendSV_Handler
+ Default_Handler SysTick_Handler
+
+ Default_Handler NS_WATCHDOG_RESET_IRQHandler
+ Default_Handler NS_WATCHDOG_IRQHandler
+ Default_Handler S32K_TIMER_IRQHandler
+ Default_Handler TFM_TIMER0_IRQ_Handler
+ Default_Handler TIMER1_IRQHandler
+ Default_Handler DUALTIMER_IRQHandler
+ Default_Handler MHU0_IRQHandler
+ Default_Handler MHU1_IRQHandler
+ Default_Handler CRYPTOCELL_IRQHandler
+ Default_Handler MPC_Handler
+ Default_Handler PPC_Handler
+ Default_Handler S_MSC_COMBINED_IRQHandler
+ Default_Handler S_BRIDGE_ERR_IRQHandler
+ Default_Handler I_CACHE_INV_ERR_IRQHandler
+ Default_Handler SYS_PPU_IRQHandler
+ Default_Handler CPU0_PPU_IRQHandler
+ Default_Handler CPU1_PPU_IRQHandler
+ Default_Handler CPU0_DGB_PPU_IRQHandler
+ Default_Handler CPU1_DGB_PPU_IRQHandler
+ Default_Handler CRYPTOCELL_PPU_IRQHandler
+ Default_Handler RAM0_PPU_IRQHandler
+ Default_Handler RAM1_PPU_IRQHandler
+ Default_Handler RAM2_PPU_IRQHandler
+ Default_Handler RAM3_PPU_IRQHandler
+ Default_Handler DEBUG_PPU_IRQHandler
+ Default_Handler CPU0_CTI_IRQHandler
+ Default_Handler CPU1_CTI_IRQHandler
+
+ Default_Handler GpTimer_IRQHandler
+ Default_Handler I2C0_IRQHandler
+ Default_Handler I2C1_IRQHandler
+ Default_Handler I2S_IRQHandler
+ Default_Handler SPI_IRQHandler
+ Default_Handler QSPI_IRQHandler
+ Default_Handler UARTRX0_Handler
+ Default_Handler UARTTX0_Handler
+ Default_Handler UART0_RxTimeout_IRQHandler
+ Default_Handler UART0_ModemStatus_IRQHandler
+ Default_Handler UART0_Error_IRQHandler
+ Default_Handler UART0_IRQHandler
+ Default_Handler UARTRX1_Handler
+ Default_Handler UARTTX1_Handler
+ Default_Handler UART1_RxTimeout_IRQHandler
+ Default_Handler UART1_ModemStatus_IRQHandler
+ Default_Handler UART1_Error_IRQHandler
+ Default_Handler UART1_IRQHandler
+ Default_Handler GPIO_0_IRQHandler
+ Default_Handler GPIO_1_IRQHandler
+ Default_Handler GPIO_2_IRQHandler
+ Default_Handler GPIO_3_IRQHandler
+ Default_Handler GPIO_4_IRQHandler
+ Default_Handler GPIO_5_IRQHandler
+ Default_Handler GPIO_6_IRQHandler
+ Default_Handler GPIO_7_IRQHandler
+ Default_Handler GPIO_8_IRQHandler
+ Default_Handler GPIO_9_IRQHandler
+ Default_Handler GPIO_10_IRQHandler
+ Default_Handler GPIO_11_IRQHandler
+ Default_Handler GPIO_12_IRQHandler
+ Default_Handler GPIO_13_IRQHandler
+ Default_Handler GPIO_14_IRQHandler
+ Default_Handler GPIO_15_IRQHandler
+ Default_Handler Combined_IRQHandler
+ Default_Handler PVT_IRQHandler
+ Default_Handler PWM_0_IRQHandler
+ Default_Handler RTC_IRQHandler
+ Default_Handler GpTimer0_IRQHandler
+ Default_Handler GpTimer1_IRQHandler
+ Default_Handler PWM_1_IRQHandler
+ Default_Handler PWM_2_IRQHandler
+ Default_Handler IOMUX_IRQHandler
+
+ END
diff --git a/secure_fw/core/arch/tfm_arch_v8m_main.c b/secure_fw/core/arch/tfm_arch_v8m_main.c
index bf257e2..5b030cb 100644
--- a/secure_fw/core/arch/tfm_arch_v8m_main.c
+++ b/secure_fw/core/arch/tfm_arch_v8m_main.c
@@ -61,6 +61,10 @@
* thread SP/SP_LIMIT. R2 holds dummy data due to stack operation is 8 bytes
* aligned.
*/
+#if defined(__ICCARM__)
+#pragma required = tfm_pendsv_do_schedule
+#endif
+
__attribute__((naked)) void PendSV_Handler(void)
{
__ASM volatile(
@@ -181,6 +185,11 @@
}
}
+#if defined(__ICCARM__)
+uint32_t tfm_core_svc_handler(uint32_t *svc_args, uint32_t exc_return);
+#pragma required = tfm_core_svc_handler
+#endif
+
__attribute__((naked)) void SVC_Handler(void)
{
__ASM volatile(
@@ -228,7 +237,6 @@
__attribute__((naked, noinline)) void tfm_arch_clear_fp_status(void)
{
__ASM volatile(
- ".syntax unified \n"
"mrs r0, control \n"
"bics r0, r0, #4 \n"
"msr control, r0 \n"
diff --git a/secure_fw/core/ipc/tfm_secure_irq_handlers_ipc.inc b/secure_fw/core/ipc/tfm_secure_irq_handlers_ipc.inc
index 6b0cbf0..d44f7c6 100644
--- a/secure_fw/core/ipc/tfm_secure_irq_handlers_ipc.inc
+++ b/secure_fw/core/ipc/tfm_secure_irq_handlers_ipc.inc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -29,10 +29,11 @@
#ifdef TFM_ENABLE_IRQ_TEST
{ TFM_IRQ_TEST_1, SPM_CORE_IRQ_TEST_1_SIGNAL_TIMER_0_IRQ, TFM_TIMER0_IRQ, 64 },
#endif /* TFM_ENABLE_IRQ_TEST */
+ {0, 0, 0, 0} /* add dummy element to avoid non-standard empty array */
};
-const size_t tfm_core_irq_signals_count = sizeof(tfm_core_irq_signals) /
- sizeof(*tfm_core_irq_signals);
+const size_t tfm_core_irq_signals_count = (sizeof(tfm_core_irq_signals) /
+ sizeof(*tfm_core_irq_signals)) - 1; /* adjust for the dummy element */
/* Definitions of privileged IRQ handlers (if any) */
#ifdef TFM_ENABLE_IRQ_TEST
diff --git a/secure_fw/core/ipc/tfm_secure_irq_handlers_ipc.inc.template b/secure_fw/core/ipc/tfm_secure_irq_handlers_ipc.inc.template
index 0bf4415..5e9d44c 100644
--- a/secure_fw/core/ipc/tfm_secure_irq_handlers_ipc.inc.template
+++ b/secure_fw/core/ipc/tfm_secure_irq_handlers_ipc.inc.template
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -41,10 +41,11 @@
{% endif %}
{% endif %}
{% endfor %}
+ {0, 0, 0, 0} /* add dummy element to avoid non-standard empty array */
};
-const size_t tfm_core_irq_signals_count = sizeof(tfm_core_irq_signals) /
- sizeof(*tfm_core_irq_signals);
+const size_t tfm_core_irq_signals_count = (sizeof(tfm_core_irq_signals) /
+ sizeof(*tfm_core_irq_signals)) - 1; /* adjust for the dummy element */
/* Definitions of privileged IRQ handlers (if any) */
{% for manifest in manifests %}
diff --git a/secure_fw/core/tfm_nspm_ipc.c b/secure_fw/core/tfm_nspm_ipc.c
index 255ef25..2633e1b 100644
--- a/secure_fw/core/tfm_nspm_ipc.c
+++ b/secure_fw/core/tfm_nspm_ipc.c
@@ -89,7 +89,9 @@
void tfm_nspm_thread_entry(void)
{
__ASM volatile(
+#ifndef __ICCARM__
".syntax unified \n"
+#endif
"mov r4, r0 \n"
"movs r2, #1 \n" /* Clear Bit[0] for S to NS transition */
"bics r4, r2 \n"
diff --git a/secure_fw/core/tfm_secure_irq_handlers.inc b/secure_fw/core/tfm_secure_irq_handlers.inc
index 76116fe..0793403 100644
--- a/secure_fw/core/tfm_secure_irq_handlers.inc
+++ b/secure_fw/core/tfm_secure_irq_handlers.inc
@@ -29,10 +29,11 @@
#ifdef TFM_ENABLE_IRQ_TEST
{ TFM_IRQ_TEST_1, SPM_CORE_IRQ_TEST_1_SIGNAL_TIMER_0_IRQ, TFM_TIMER0_IRQ, 64 },
#endif /* TFM_ENABLE_IRQ_TEST */
+ {0, 0, (IRQn_Type) 0, 0} /* add dummy element to avoid non-standard empty array */
};
-const size_t tfm_core_irq_signals_count = sizeof(tfm_core_irq_signals) /
- sizeof(*tfm_core_irq_signals);
+const size_t tfm_core_irq_signals_count = (sizeof(tfm_core_irq_signals) /
+ sizeof(*tfm_core_irq_signals)) - 1; /* adjust for the dummy element */
extern void priv_irq_handler_main(uint32_t partition_id,
uint32_t unpriv_handler,
diff --git a/secure_fw/core/tfm_secure_irq_handlers.inc.template b/secure_fw/core/tfm_secure_irq_handlers.inc.template
index 872c4b0..3fabdc0 100644
--- a/secure_fw/core/tfm_secure_irq_handlers.inc.template
+++ b/secure_fw/core/tfm_secure_irq_handlers.inc.template
@@ -41,10 +41,11 @@
{% endif %}
{% endif %}
{% endfor %}
+ {0, 0, (IRQn_Type) 0, 0} /* add dummy element to avoid non-standard empty array */
};
-const size_t tfm_core_irq_signals_count = sizeof(tfm_core_irq_signals) /
- sizeof(*tfm_core_irq_signals);
+const size_t tfm_core_irq_signals_count = (sizeof(tfm_core_irq_signals) /
+ sizeof(*tfm_core_irq_signals)) - 1; /* adjust for the dummy element */
extern void priv_irq_handler_main(uint32_t partition_id,
uint32_t unpriv_handler,
diff --git a/secure_fw/spm/spm_func.c b/secure_fw/spm/spm_func.c
index ca11814..6b9c46b 100644
--- a/secure_fw/spm/spm_func.c
+++ b/secure_fw/spm/spm_func.c
@@ -302,9 +302,7 @@
static struct iovec_args_t *get_iovec_args_stack_address(uint32_t partition_idx)
{
/* Save the iovecs on the common stack. */
- return (struct iovec_args_t *)((uint8_t *)®ION_NAME(Image$$,
- TFM_SECURE_STACK, $$ZI$$Limit) -
- sizeof(struct iovec_args_t));
+ return ®ION_NAME(Image$$, TFM_SECURE_STACK, $$ZI$$Limit)[-1];
}
static enum tfm_status_e tfm_start_partition(
@@ -321,7 +319,6 @@
uint32_t partition_psp, partition_psplim;
uint32_t partition_state;
uint32_t caller_partition_state;
- uint32_t partition_flags;
struct tfm_state_context_t *svc_ctx;
uint32_t caller_partition_id;
int32_t client_id;
@@ -344,7 +341,6 @@
caller_part_data = tfm_spm_partition_get_runtime_data(caller_partition_idx);
partition_state = curr_part_data->partition_state;
caller_partition_state = caller_part_data->partition_state;
- partition_flags = tfm_spm_partition_get_flags(partition_idx);
caller_partition_id = tfm_spm_partition_get_partition_id(
caller_partition_idx);
@@ -361,8 +357,7 @@
* as stack by the partitions starts at a lower address
*/
partition_psp =
- (uint32_t)®ION_NAME(Image$$, TFM_SECURE_STACK, $$ZI$$Limit)-
- sizeof(struct iovec_args_t);
+ (uint32_t)®ION_NAME(Image$$, TFM_SECURE_STACK, $$ZI$$Limit)[-1];
partition_psplim =
(uint32_t)®ION_NAME(Image$$, TFM_SECURE_STACK, $$ZI$$Base);
@@ -472,7 +467,6 @@
uint32_t current_partition_idx =
tfm_spm_partition_get_running_partition_idx();
const struct spm_partition_runtime_data_t *curr_part_data, *ret_part_data;
- uint32_t current_partition_flags;
uint32_t return_partition_idx;
uint32_t return_partition_flags;
uint32_t psp = __get_PSP();
@@ -494,8 +488,6 @@
ret_part_data = tfm_spm_partition_get_runtime_data(return_partition_idx);
return_partition_flags = tfm_spm_partition_get_flags(return_partition_idx);
- current_partition_flags = tfm_spm_partition_get_flags(
- current_partition_idx);
tfm_secure_lock--;
@@ -509,14 +501,12 @@
(struct tfm_state_context_t *)ret_part_data->stack_ptr);
*excReturn = ret_part_data->lr;
__set_PSP(ret_part_data->stack_ptr);
- REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base)[];
+ REGION_DECLARE_T(Image$$, ARM_LIB_STACK, $$ZI$$Base, uint32_t)[];
uint32_t psp_stack_bottom =
(uint32_t)REGION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base);
tfm_arch_set_psplim(psp_stack_bottom);
- iovec_args = (struct iovec_args_t *)
- ((uint8_t *)®ION_NAME(Image$$, TFM_SECURE_STACK, $$ZI$$Limit) -
- sizeof(struct iovec_args_t));
+ iovec_args = ®ION_NAME(Image$$, TFM_SECURE_STACK, $$ZI$$Limit)[-1];
for (i = 0; i < curr_part_data->iovec_args.out_len; ++i) {
curr_part_data->orig_outvec[i].len = iovec_args->out_vec[i].len;
diff --git a/tools/tfm_generated_file_list.yaml b/tools/tfm_generated_file_list.yaml
index 0ec7198..5fd19d4 100644
--- a/tools/tfm_generated_file_list.yaml
+++ b/tools/tfm_generated_file_list.yaml
@@ -1,5 +1,5 @@
#-------------------------------------------------------------------------------
-# Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+# Copyright (c) 2018-2020, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -40,6 +40,12 @@
"output": "platform/ext/common/armclang/tfm_common_s.sct"
},
{
+ "name": "Common secure icf file",
+ "short_name": "tfm_common_s.icf",
+ "template": "platform/ext/common/iar/tfm_common_s.icf.template",
+ "output": "platform/ext/common/iar/tfm_common_s.icf"
+ },
+ {
"name": "Secure Veneers C file",
"short_name": "tfm_veneers_c",
"template": "secure_fw/ns_callable/tfm_veneers.c.template",