Platform: Update Musca-A with new file structure
This patch updates the Musca-A platform support files with a new file
structure and various other improvements.
Change-Id: Iac0c3aad97f89baf5db32ed331e54b8ed7fced63
Signed-off-by: Kevin Peng <kevin.peng@arm.com>
diff --git a/platform/ext/musca_a.cmake b/platform/ext/musca_a.cmake
index b82ab81..ac9d081 100644
--- a/platform/ext/musca_a.cmake
+++ b/platform/ext/musca_a.cmake
@@ -53,13 +53,13 @@
if (NOT DEFINED BUILD_CMSIS_CORE)
message(FATAL_ERROR "Configuration variable BUILD_CMSIS_CORE (true|false) is undefined!")
elseif(BUILD_CMSIS_CORE)
- list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/musca_a/Device/Source/system_cmsdk_musca.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/musca_a/Device/Source/system_core_init.c")
endif()
if (NOT DEFINED BUILD_RETARGET)
message(FATAL_ERROR "Configuration variable BUILD_RETARGET (true|false) is undefined!")
elseif(BUILD_RETARGET)
- list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/musca_a/Device/Source/platform_retarget_dev.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/musca_a/Device/Source/device_definition.c")
endif()
if (NOT DEFINED BUILD_UART_STDOUT)
@@ -158,7 +158,7 @@
if (NOT DEFINED BUILD_FLASH)
message(FATAL_ERROR "Configuration variable BUILD_FLASH (true|false) is undefined!")
elseif(BUILD_FLASH)
- list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/musca_a/CMSIS_Driver/Driver_Flash.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/musca_a/CMSIS_Driver/Driver_QSPI_Flash.c")
# As the SST area is going to be in RAM, it is required to set SST_CREATE_FLASH_LAYOUT
# to be sure the SST service knows that when it starts the SST area does not contain any
# valid SST flash layout and it needs to create one.
diff --git a/platform/ext/target/musca_a/CMSIS_Driver/Config/RTE_Device.h b/platform/ext/target/musca_a/CMSIS_Driver/Config/RTE_Device.h
index 67d33fc..fc74d19 100644
--- a/platform/ext/target/musca_a/CMSIS_Driver/Config/RTE_Device.h
+++ b/platform/ext/target/musca_a/CMSIS_Driver/Config/RTE_Device.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 Arm Limited
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -116,7 +116,7 @@
// <e> FLASH (Flash Memory) [Driver_FLASH0]
// <i> Configuration settings for Driver_FLASH0 in component ::Drivers:FLASH
-#define RTE_FLASH0 1
+#define RTE_QSPI_FLASH0 1
// </e> FLASH (Flash Memory) [Driver_FLASH0]
#endif /* __RTE_DEVICE_H */
diff --git a/platform/ext/target/musca_a/CMSIS_Driver/Config/cmsis_driver_config.h b/platform/ext/target/musca_a/CMSIS_Driver/Config/cmsis_driver_config.h
index 68fff4b..8ccd505 100644
--- a/platform/ext/target/musca_a/CMSIS_Driver/Config/cmsis_driver_config.h
+++ b/platform/ext/target/musca_a/CMSIS_Driver/Config/cmsis_driver_config.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019 Arm Limited
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -18,8 +18,8 @@
#define __CMSIS_DRIVER_CONFIG_H__
#include "device_cfg.h"
-#include "platform_retarget_dev.h"
-#include "platform_retarget_pins.h"
+#include "device_definition.h"
+#include "platform_description.h"
#include "RTE_Device.h"
#include "target_cfg.h"
diff --git a/platform/ext/target/musca_a/CMSIS_Driver/Driver_MPC.c b/platform/ext/target/musca_a/CMSIS_Driver/Driver_MPC.c
index af937c3..ca6f374 100644
--- a/platform/ext/target/musca_a/CMSIS_Driver/Driver_MPC.c
+++ b/platform/ext/target/musca_a/CMSIS_Driver/Driver_MPC.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018 Arm Limited
+ * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -15,7 +15,6 @@
*/
#include "Driver_MPC.h"
-#include "cmsis.h"
#include "cmsis_driver_config.h"
#include "RTE_Device.h"
@@ -751,6 +750,145 @@
};
#endif /* RTE_CODE_SRAM_MPC */
+#if (RTE_SSRAM1_MPC)
+/* Ranges controlled by this SSRAM1_MPC */
+static const struct mpc_sie200_memory_range_t MPC_SSRAM1_RANGE_S = {
+ .base = MPC_SSRAM1_RANGE_BASE_S,
+ .limit = MPC_SSRAM1_RANGE_LIMIT_S,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static const struct mpc_sie200_memory_range_t MPC_SSRAM1_RANGE_NS = {
+ .base = MPC_SSRAM1_RANGE_BASE_NS,
+ .limit = MPC_SSRAM1_RANGE_LIMIT_NS,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_SSRAM1_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t*
+ MPC_SSRAM1_RANGE_LIST[MPC_SSRAM1_RANGE_LIST_LEN] =
+ {&MPC_SSRAM1_RANGE_S, &MPC_SSRAM1_RANGE_NS};
+
+/* SSRAM1_MPC Driver wrapper functions */
+static int32_t SSRAM1_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_SSRAM1_DEV,
+ MPC_SSRAM1_RANGE_LIST,
+ MPC_SSRAM1_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM1_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t SSRAM1_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_SSRAM1_DEV, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM1_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_SSRAM1_DEV, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM1_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_SSRAM1_DEV, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM1_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_SSRAM1_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM1_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_SSRAM1_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM1_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_SSRAM1_DEV);
+
+ return error_trans(ret);
+}
+
+static void SSRAM1_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_SSRAM1_DEV);
+}
+
+
+static void SSRAM1_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_SSRAM1_DEV);
+}
+
+static uint32_t SSRAM1_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_SSRAM1_DEV);
+}
+
+static int32_t SSRAM1_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_SSRAM1_DEV);
+}
+
+/* SSRAM1_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_SRAM1_MPC;
+ARM_DRIVER_MPC Driver_SRAM1_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = SSRAM1_MPC_Initialize,
+ .Uninitialize = SSRAM1_MPC_Uninitialize,
+ .GetBlockSize = SSRAM1_MPC_GetBlockSize,
+ .GetCtrlConfig = SSRAM1_MPC_GetCtrlConfig,
+ .SetCtrlConfig = SSRAM1_MPC_SetCtrlConfig,
+ .ConfigRegion = SSRAM1_MPC_ConfigRegion,
+ .GetRegionConfig = SSRAM1_MPC_GetRegionConfig,
+ .EnableInterrupt = SSRAM1_MPC_EnableInterrupt,
+ .DisableInterrupt = SSRAM1_MPC_DisableInterrupt,
+ .ClearInterrupt = SSRAM1_MPC_ClearInterrupt,
+ .InterruptState = SSRAM1_MPC_InterruptState,
+ .LockDown = SSRAM1_MPC_LockDown,
+};
+#endif /* RTE_SSRAM1_MPC */
+
#if (RTE_SSRAM2_MPC)
/* Ranges controlled by this SSRAM2_MPC */
static const struct mpc_sie200_memory_range_t MPC_SSRAM2_RANGE_S = {
@@ -1027,7 +1165,6 @@
};
#endif /* RTE_SSRAM3_MPC */
-
#if (RTE_QSPI_MPC)
/* Ranges controlled by this QSPI_MPC */
static const struct mpc_sie200_memory_range_t MPC_QSPI_RANGE_S = {
diff --git a/platform/ext/target/musca_a/CMSIS_Driver/Driver_PPC.c b/platform/ext/target/musca_a/CMSIS_Driver/Driver_PPC.c
index 62f840f..efadb04 100644
--- a/platform/ext/target/musca_a/CMSIS_Driver/Driver_PPC.c
+++ b/platform/ext/target/musca_a/CMSIS_Driver/Driver_PPC.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018 Arm Limited
+ * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -16,7 +16,6 @@
#include "Driver_PPC.h"
-#include "cmsis.h"
#include "cmsis_driver_config.h"
#include "RTE_Device.h"
diff --git a/platform/ext/target/musca_a/CMSIS_Driver/Driver_Flash.c b/platform/ext/target/musca_a/CMSIS_Driver/Driver_QSPI_Flash.c
similarity index 98%
rename from platform/ext/target/musca_a/CMSIS_Driver/Driver_Flash.c
rename to platform/ext/target/musca_a/CMSIS_Driver/Driver_QSPI_Flash.c
index b7af48a..9a32afb 100644
--- a/platform/ext/target/musca_a/CMSIS_Driver/Driver_Flash.c
+++ b/platform/ext/target/musca_a/CMSIS_Driver/Driver_QSPI_Flash.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 Arm Limited
+ * Copyright (c) 2013-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -17,7 +17,6 @@
#include "Driver_Flash.h"
#include <stdbool.h>
-#include "cmsis.h"
#include "cmsis_driver_config.h"
#include "RTE_Device.h"
#include "flash_layout.h"
@@ -107,7 +106,7 @@
return ((param % flash_dev->data->program_unit) != 0) ? (false) : (true);
}
-#if (RTE_FLASH0)
+#if (RTE_QSPI_FLASH0)
static ARM_FLASH_INFO ARM_FLASH0_DEV_DATA = {
.sector_info = NULL, /* Uniform sector layout */
.sector_count = FLASH_TOTAL_SIZE / SUBSECTOR_4KB,
@@ -326,4 +325,4 @@
ARM_Flash_GetStatus,
ARM_Flash_GetInfo
};
-#endif /* RTE_FLASH0 */
+#endif /* RTE_QSPI_FLASH0 */
diff --git a/platform/ext/target/musca_a/CMSIS_Driver/Driver_USART.c b/platform/ext/target/musca_a/CMSIS_Driver/Driver_USART.c
index 866ea9e..b66b445 100644
--- a/platform/ext/target/musca_a/CMSIS_Driver/Driver_USART.c
+++ b/platform/ext/target/musca_a/CMSIS_Driver/Driver_USART.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2013-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -18,7 +18,6 @@
#include "Driver_USART.h"
-#include "cmsis.h"
#include "cmsis_driver_config.h"
#include "RTE_Device.h"
diff --git a/platform/ext/target/musca_a/Device/Config/device_cfg.h b/platform/ext/target/musca_a/Device/Config/device_cfg.h
index 55784cc..3520f10 100644
--- a/platform/ext/target/musca_a/Device/Config/device_cfg.h
+++ b/platform/ext/target/musca_a/Device/Config/device_cfg.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018 Arm Limited
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -75,4 +75,7 @@
#define MT25QL_S
#define MT25QL_NS
+/* Default UART baud rate */
+#define UART_DEFAULT_BAUD_RATE 115200
+
#endif /* __ARM_LTD_DEVICE_CFG_H__ */
diff --git a/platform/ext/target/musca_a/Device/Include/cmsis.h b/platform/ext/target/musca_a/Device/Include/cmsis.h
index b23b8a1..db9fe01 100644
--- a/platform/ext/target/musca_a/Device/Include/cmsis.h
+++ b/platform/ext/target/musca_a/Device/Include/cmsis.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -17,10 +17,94 @@
#ifndef __MUSCA_CMSIS_H__
#define __MUSCA_CMSIS_H__
-/* CMSIS wrapper for Musca board */
+/* Processor and Core Peripherals and configurations */
-#include "system_cmsdk_musca.h"
-#include "platform_regs.h" /* Platform registers */
-#include "platform_retarget.h" /* Peripherals base addresses */
+/* ========================================================================= */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ========================================================================= */
+
+/* ================ Start of section using anonymous unions ============== */
+#if defined (__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined (__ICCARM__)
+ #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+/* -- Configuration of the Cortex-M33 Processor and Core Peripherals -- */
+#ifdef DUAL_CORE
+/* Both cores are used */
+#define __CM33_REV 0x0001U /* Core revision r0p1 */
+#define __SAUREGION_PRESENT 1U /* SAU regions present */
+#define __MPU_PRESENT 1U /* MPU present */
+#define __VTOR_PRESENT 1U /* VTOR present */
+#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority
+ * Levels */
+#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick
+ * Config is used */
+
+#if defined CORE0
+#define __FPU_PRESENT 0U /* no FPU present */
+#define __DSP_PRESENT 0U /* no DSP extension present */
+#elif defined CORE1
+#define __FPU_PRESENT 1U /* FPU present */
+#define __DSP_PRESENT 1U /* DSP extension present */
+#else
+#error "Either CORE0 or CORE1 must be defined"
+#endif /* CORE0/1 */
+
+#else /* DUAL_CORE */
+
+/* Single core is used */
+/* ----- Configuration of the Cortex-M33 Processor and Core Peripherals --- */
+#define __CM33_REV 0x0001U /* Core revision r0p1 */
+#define __SAUREGION_PRESENT 1U /* SAU regions present */
+#define __MPU_PRESENT 1U /* MPU present */
+#define __VTOR_PRESENT 1U /* VTOR present */
+#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority
+ * Levels */
+#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick
+ * Config is used */
+#define __FPU_PRESENT 0U /* no FPU present */
+#define __DSP_PRESENT 0U /* no DSP extension present */
+#endif /* DUAL_CORE */
+
+#include "system_core_init.h"
+#include "platform_irq.h"
+#include <core_cm33.h> /*!< Arm Cortex-M33 processor and core peripherals */
+
+/* ============== End of section using anonymous unions =================== */
+#if defined (__CC_ARM)
+ #pragma pop
+#elif defined (__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning restore
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
#endif /*__MUSCA_CMSIS_H__ */
diff --git a/platform/ext/target/musca_a/Device/Include/platform_retarget_dev.h b/platform/ext/target/musca_a/Device/Include/device_definition.h
similarity index 63%
rename from platform/ext/target/musca_a/Device/Include/platform_retarget_dev.h
rename to platform/ext/target/musca_a/Device/Include/device_definition.h
index 03cf940..bccd2fb 100644
--- a/platform/ext/target/musca_a/Device/Include/platform_retarget_dev.h
+++ b/platform/ext/target/musca_a/Device/Include/device_definition.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018 Arm Limited
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -15,19 +15,23 @@
*/
/**
- * \file platform_retarget_dev.h
- * \brief The structure definitions in this file are exported based on the peripheral
- * definitions from device_cfg.h.
- * This retarget file is meant to be used as a helper for baremetal
+ * \file device_definition.h
+ * \brief The structure definitions in this file are exported based
+ * on the peripheral definitions from device_cfg.h.
+ * This file is meant to be used as a helper for baremetal
* applications and/or as an example of how to configure the generic
* driver structures.
*/
-#ifndef __ARM_LTD_MUSCA_A1_RETARGET_DEV_H__
-#define __ARM_LTD_MUSCA_A1_RETARGET_DEV_H__
+#ifndef __DEVICE_DEFINITION_H__
+#define __DEVICE_DEFINITION_H__
#include "device_cfg.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
/* ======= Peripheral configuration structure declarations ======= */
/* ARM SCC driver structures */
@@ -40,6 +44,16 @@
extern struct musca_a1_scc_dev_t MUSCA_A1_SCC_DEV_NS;
#endif
+/* ARM GPIO driver structures */
+#ifdef GPIO0_CMSDK_S
+#include "gpio_cmsdk_drv.h"
+extern struct gpio_cmsdk_dev_t GPIO0_CMSDK_DEV_S;
+#endif
+#ifdef GPIO0_CMSDK_NS
+#include "gpio_cmsdk_drv.h"
+extern struct gpio_cmsdk_dev_t GPIO0_CMSDK_DEV_NS;
+#endif
+
/* ARM MPC SIE 200 driver structures */
#ifdef MPC_ISRAM0_S
#include "mpc_sie200_drv.h"
@@ -74,6 +88,24 @@
extern struct mpc_sie200_dev_t MPC_QSPI_DEV_NS;
#endif
+/* ARM MHU driver structures */
+#ifdef ARM_MHU0_S
+#include "mhu_sse_200_drv.h"
+extern struct arm_mhu_sse_200_dev_t ARM_MHU0_DEV_S;
+#endif
+#ifdef ARM_MHU0_NS
+#include "mhu_sse_200_drv.h"
+extern struct arm_mhu_sse_200_dev_t ARM_MHU0_DEV_NS;
+#endif
+#ifdef ARM_MHU1_S
+#include "mhu_sse_200_drv.h"
+extern struct arm_mhu_sse_200_dev_t ARM_MHU1_DEV_S;
+#endif
+#ifdef ARM_MHU1_NS
+#include "mhu_sse_200_drv.h"
+extern struct arm_mhu_sse_200_dev_t ARM_MHU1_DEV_NS;
+#endif
+
/* ARM UART PL011 driver structures */
#ifdef UART0_PL011_S
#include "uart_pl011_drv.h"
@@ -92,6 +124,34 @@
extern struct uart_pl011_dev_t UART1_PL011_DEV_NS;
#endif
+/* I2C IP6510 driver structures */
+#ifdef I2C0_IP6510_S
+#include "i2c_ip6510_drv.h"
+extern struct i2c_ip6510_dev_t I2C0_IP6510_DEV_S;
+#endif
+#ifdef I2C0_IP6510_NS
+#include "i2c_ip6510_drv.h"
+extern struct i2c_ip6510_dev_t I2C0_IP6510_DEV_NS;
+#endif
+#ifdef I2C1_IP6510_S
+#include "i2c_ip6510_drv.h"
+extern struct i2c_ip6510_dev_t I2C1_IP6510_DEV_S;
+#endif
+#ifdef I2C1_IP6510_NS
+#include "i2c_ip6510_drv.h"
+extern struct i2c_ip6510_dev_t I2C1_IP6510_DEV_NS;
+#endif
+
+/* CMSDK Dualtimer driver structures */
+#ifdef CMSDK_DUALTIMER_S
+#include "dualtimer_cmsdk_drv.h"
+extern struct dualtimer_cmsdk_dev_t CMSDK_DUALTIMER_DEV_S;
+#endif
+#ifdef CMSDK_DUALTIMER_NS
+#include "dualtimer_cmsdk_drv.h"
+extern struct dualtimer_cmsdk_dev_t CMSDK_DUALTIMER_DEV_NS;
+#endif
+
/* CMSDK Timer driver structures */
#ifdef CMSDK_TIMER0_S
#include "timer_cmsdk_drv.h"
@@ -111,7 +171,38 @@
extern struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_NS;
#endif
-/* QSPI Flash Controller driver structures */
+/* General-Purpose Timer driver structures */
+#ifdef GP_TIMER_S
+#include "timer_gp_drv.h"
+extern struct timer_gp_dev_t GP_TIMER_DEV_S;
+#endif
+#ifdef GP_TIMER_NS
+#include "timer_gp_drv.h"
+extern struct timer_gp_dev_t GP_TIMER_DEV_NS;
+#endif
+
+/* RTC PL031 */
+#ifdef RTC_PL031_S
+#include "rtc_pl031_drv.h"
+extern struct rtc_pl031_dev_t RTC_PL031_DEV_S;
+#endif
+
+#ifdef RTC_PL031_NS
+#include "rtc_pl031_drv.h"
+extern struct rtc_pl031_dev_t RTC_PL031_DEV_NS;
+#endif
+
+/* Cadence SPI IP6524 driver structures */
+#ifdef SPI0_IP6524_S
+#include "spi_ip6524_drv.h"
+extern struct spi_ip6524_dev_t SPI0_DEV_S;
+#endif
+#ifdef SPI0_IP6524_NS
+#include "spi_ip6524_drv.h"
+extern struct spi_ip6524_dev_t SPI0_DEV_NS;
+#endif
+
+/* QSPI Flash Controller driver structures */
#ifdef QSPI_IP6514E_S
#include "qspi_ip6514e_drv.h"
extern struct qspi_ip6514e_dev_t QSPI_DEV_S;
@@ -182,12 +273,16 @@
/* MT25QL Flash memory library structures */
#if (defined(MT25QL_S) && defined(QSPI_IP6514E_S))
-#include "Libraries/mt25ql_flash_lib.h"
+#include "mt25ql_flash_lib.h"
extern struct mt25ql_dev_t MT25QL_DEV_S;
#endif
#if (defined(MT25QL_NS) && defined(QSPI_IP6514E_NS))
-#include "Libraries/mt25ql_flash_lib.h"
+#include "mt25ql_flash_lib.h"
extern struct mt25ql_dev_t MT25QL_DEV_NS;
#endif
-#endif /* __ARM_LTD_MUSCA_A1_RETARGET_DEV_H__ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DEVICE_DEFINITION_H__ */
diff --git a/platform/ext/target/musca_a/Device/Include/platform_base_address.h b/platform/ext/target/musca_a/Device/Include/platform_base_address.h
new file mode 100644
index 0000000..85b17c1
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Include/platform_base_address.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.01 Device\_Template_Vendor\Vendor\Device\Include\Device.h
+ */
+
+#ifndef __PLATFORM_BASE_ADDRESS_H__
+#define __PLATFORM_BASE_ADDRESS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Address Map ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+ * @{
+ */
+
+/* Non-Secure Peripheral and SRAM base address */
+#define MUSCA_CODE_SRAM_NS_BASE (0x00000000UL) /*!< (Non-Secure Code SRAM ) Base Address */
+#define MUSCA_QSPI_FLASH_NS_BASE (0x00200000UL) /*!< (Non-Secure QSPI FLASH ) Base Address */
+#define MUSCA_OTP_NS_BASE (0x0E000000UL) /*!< (Non-Secure OTP ) Base Address */
+#define MUSCA_SRAM_NS_BASE (0x20000000UL) /*!< (Non-Secure Internal SRAM ) Base Address */
+#define MUSCA_BASE_ELEMENT_NS_BASE (0x40000000UL) /*!< (Non-Secure Base Peripherals ) Base Address */
+#define MUSCA_CMSDK_TIMER0_NS_BASE (0x40000000UL) /*!< (Non-Secure CMSDK Timer0 ) Base Address */
+#define MUSCA_CMSDK_TIMER1_NS_BASE (0x40001000UL) /*!< (Non-Secure CMSDK Timer1 ) Base Address */
+#define MUSCA_CMSDK_DUALTIMER_NS_BASE (0x40002000UL) /*!< (Non-Secure CMSDK Dual Timer ) Base Address */
+#define MUSCA_MHU0_NS_BASE (0x40003000UL) /*!< (Non-Secure MHU0 ) Base Address */
+#define MUSCA_MHU1_NS_BASE (0x40004000UL) /*!< (Non-Secure MHU1 ) Base Address */
+#define MUSCA_CPU_ELEMENT_NS_BASE (0x40010000UL) /*!< (Non-Secure CPU Peripherals ) Base Address */
+#define MUSCA_SYSTEM_INFO_NS_BASE (0x40020000UL) /*!< (Non-Secure System Info ) Base Address */
+#define MUSCA_CMSDK_S32KTIMER_NS_BASE (0x4002F000UL) /*!< (Non-Secure CMSDK S32K Timer ) Base Address */
+#define MUSCA_NSPCTRL_NS_BASE (0x40080000UL) /*!< (Non-Secure Privilege Ctrl Blk) Base Address */
+#define MUSCA_CMSDK_WATCHDOG_NS_BASE (0x40081000UL) /*!< (Non-Secure CMSDK Watchdog ) Base Address */
+#define MUSCA_UART0_NS_BASE (0x40101000UL) /*!< (Non-Secure UART0 ) Base Address */
+#define MUSCA_UART1_NS_BASE (0x40102000UL) /*!< (Non-Secure UART1 ) Base Address */
+#define MUSCA_SPI0_NS_BASE (0x40103000UL) /*!< (Non-Secure SPI0 ) Base Address */
+#define MUSCA_I2C0_NS_BASE (0x40104000UL) /*!< (Non-Secure I2C0 ) Base Address */
+#define MUSCA_I2C1_NS_BASE (0x40105000UL) /*!< (Non-Secure I2C1 ) Base Address */
+#define MUSCA_I2S_NS_BASE (0x40106000UL) /*!< (Non-Secure I2S ) Base Address */
+#define MUSCA_PWM0_NS_BASE (0x40107000UL) /*!< (Non-Secure PWM0 ) Base Address */
+#define MUSCA_RTC_NS_BASE (0x40108000UL) /*!< (Non-Secure RTC ) Base Address */
+#define MUSCA_PVT_NS_BASE (0x40109000UL) /*!< (Non-Secure PVT sensors ) Base Address */
+#define MUSCA_QSPI_REG_NS_BASE (0x4010A000UL) /*!< (Non-Secure QSPI registers ) Base Address */
+#define MUSCA_TIMER_NS_BASE (0x4010B000UL) /*!< (Non-Secure Timer ) Base Address */
+#define MUSCA_SCC_NS_BASE (0x4010C000UL) /*!< (Non-Secure SCC ) Base Address */
+#define MUSCA_PWM1_NS_BASE (0x4010E000UL) /*!< (Non-Secure PWM1 ) Base Address */
+#define MUSCA_PWM2_NS_BASE (0x4010F000UL) /*!< (Non-Secure PWM2 ) Base Address */
+#define MUSCA_GPIO_NS_BASE (0x40110000UL) /*!< (Non-Secure GPIO ) Base Address */
+#define MUSCA_QSPI_MPC_NS_BASE (0x40120000UL) /*!< (Non-Secure QSPI MPC ) Base Address */
+#define MUSCA_CODE_SRAM_MPC_NS_BASE (0x40130000UL) /*!< (Non-Secure Code SRAM MPC ) Base Address */
+#define MUSCA_DEFAULT_SLAVE_NS_BASE (0x60000000UL) /*!< (Non-Secure Unused AHB ) Base Address */
+/* Secure Peripheral and SRAM base address */
+#define MUSCA_CODE_SRAM_S_BASE (0x10000000UL) /*!< (Secure Code SRAM ) Base Address */
+#define MUSCA_QSPI_FLASH_S_BASE (0x10200000UL) /*!< (Secure QSPI FLASH ) Base Address */
+#define MUSCA_OTP_S_BASE (0x1E000000UL) /*!< (Secure OTP ) Base Address */
+#define MUSCA_SRAM_S_BASE (0x30000000UL) /*!< (Secure Internal SRAM ) Base Address */
+#define MUSCA_BASE_ELEMENT_S_BASE (0x50000000UL) /*!< (Secure Base Peripherals ) Base Address */
+#define MUSCA_MHU0_S_BASE (0x50003000UL) /*!< (Secure MHU0 ) Base Address */
+#define MUSCA_MHU1_S_BASE (0x50004000UL) /*!< (Secure MHU1 ) Base Address */
+#define MUSCA_CPU_ELEMENT_S_BASE (0x50010000UL) /*!< (Secure CPU Peripherals ) Base Address */
+#define MUSCA_SYSTEM_INFO_S_BASE (0x50020000UL) /*!< (Secure System Info ) Base Address */
+#define MUSCA_SYSTEM_CTRL_S_BASE (0x50021000UL) /*!< (Secure System Control ) Base Address */
+#define MUSCA_CMSDK_S32KTIMER_S_BASE (0x5002F000UL) /*!< (Secure CMSDK S32K Timer ) Base Address */
+#define MUSCA_CMSDK_TIMER0_S_BASE (0x50000000UL) /*!< (Secure CMSDK Timer0 ) Base Address */
+#define MUSCA_CMSDK_TIMER1_S_BASE (0x50001000UL) /*!< (Secure CMSDK Timer1 ) Base Address */
+#define MUSCA_CMSDK_DUALTIMER_S_BASE (0x50002000UL) /*!< (Secure CMSDK Dual Timer ) Base Address */
+#define MUSCA_SPCTRL_S_BASE (0x50080000UL) /*!< (Secure Privilege Ctrl Blk) Base Address */
+#define MUSCA_CMSDK_WATCHDOG_S_BASE (0x50081000UL) /*!< (Secure CMSDK Watchdog ) Base Address */
+#define MUSCA_MPC_SRAM0_S_BASE (0x50083000UL) /*!< (Secure MPC SRAM Bank 0 ) Base Address */
+#define MUSCA_MPC_SRAM1_S_BASE (0x50084000UL) /*!< (Secure MPC SRAM Bank 1 ) Base Address */
+#define MUSCA_MPC_SRAM2_S_BASE (0x50085000UL) /*!< (Secure MPC SRAM Bank 2 ) Base Address */
+#define MUSCA_MPC_SRAM3_S_BASE (0x50086000UL) /*!< (Secure MPC SRAM Bank 3 ) Base Address */
+#define MUSCA_UART0_S_BASE (0x50101000UL) /*!< (Secure UART0 ) Base Address */
+#define MUSCA_UART1_S_BASE (0x50102000UL) /*!< (Secure UART1 ) Base Address */
+#define MUSCA_SPI0_S_BASE (0x50103000UL) /*!< (Secure SPI0 ) Base Address */
+#define MUSCA_I2C0_S_BASE (0x50104000UL) /*!< (Secure I2C0 ) Base Address */
+#define MUSCA_I2C1_S_BASE (0x50105000UL) /*!< (Secure I2C1 ) Base Address */
+#define MUSCA_I2S_S_BASE (0x50106000UL) /*!< (Secure I2S ) Base Address */
+#define MUSCA_PWM0_S_BASE (0x50107000UL) /*!< (Secure PWM0 ) Base Address */
+#define MUSCA_RTC_S_BASE (0x50108000UL) /*!< (Secure RTC ) Base Address */
+#define MUSCA_PVT_S_BASE (0x50109000UL) /*!< (Secure PVT sensors ) Base Address */
+#define MUSCA_QSPI_REG_S_BASE (0x5010A000UL) /*!< (Secure QSPI registers ) Base Address */
+#define MUSCA_TIMER_S_BASE (0x5010B000UL) /*!< (Secure Timer ) Base Address */
+#define MUSCA_SCC_S_BASE (0x5010C000UL) /*!< (Secure SCC ) Base Address */
+#define MUSCA_PWM1_S_BASE (0x5010E000UL) /*!< (Secure PWM1 ) Base Address */
+#define MUSCA_PWM2_S_BASE (0x5010F000UL) /*!< (Secure PWM2 ) Base Address */
+#define MUSCA_GPIO_S_BASE (0x50110000UL) /*!< (Secure GPIO ) Base Address */
+#define MUSCA_QSPI_MPC_S_BASE (0x50120000UL) /*!< (Secure QSPI MPC ) Base Address */
+#define MUSCA_CODE_SRAM_MPC_S_BASE (0x50130000UL) /*!< (Secure Code SRAM MPC ) Base Address */
+#define MUSCA_DEFAULT_SLAVE_S_BASE (0x70000000UL) /*!< (Secure Unused AHB ) Base Address */
+
+/* SRAM MPC ranges and limits */
+/* Internal memory */
+#define MPC_ISRAM0_RANGE_BASE_NS 0x20000000
+#define MPC_ISRAM0_RANGE_LIMIT_NS 0x20007FFF
+#define MPC_ISRAM0_RANGE_BASE_S 0x30000000
+#define MPC_ISRAM0_RANGE_LIMIT_S 0x30007FFF
+
+#define MPC_ISRAM1_RANGE_BASE_NS 0x20008000
+#define MPC_ISRAM1_RANGE_LIMIT_NS 0x2000FFFF
+#define MPC_ISRAM1_RANGE_BASE_S 0x30008000
+#define MPC_ISRAM1_RANGE_LIMIT_S 0x3000FFFF
+
+#define MPC_ISRAM2_RANGE_BASE_NS 0x20010000
+#define MPC_ISRAM2_RANGE_LIMIT_NS 0x20017FFF
+#define MPC_ISRAM2_RANGE_BASE_S 0x30010000
+#define MPC_ISRAM2_RANGE_LIMIT_S 0x30017FFF
+
+#define MPC_ISRAM3_RANGE_BASE_NS 0x20018000
+#define MPC_ISRAM3_RANGE_LIMIT_NS 0x2001FFFF
+#define MPC_ISRAM3_RANGE_BASE_S 0x30018000
+#define MPC_ISRAM3_RANGE_LIMIT_S 0x3001FFFF
+
+/* Code SRAM memory */
+#define MPC_CODE_SRAM_RANGE_BASE_NS (0x00000000)
+#define MPC_CODE_SRAM_RANGE_LIMIT_NS (0x00200000)
+#define MPC_CODE_SRAM_RANGE_BASE_S (0x10000000)
+#define MPC_CODE_SRAM_RANGE_LIMIT_S (0x10200000)
+
+/* QSPI Flash memory */
+#define MPC_QSPI_RANGE_BASE_NS (0x00200000)
+#define MPC_QSPI_RANGE_LIMIT_NS (0x00240000)
+#define MPC_QSPI_RANGE_BASE_S (0x10200000)
+#define MPC_QSPI_RANGE_LIMIT_S (0x10240000)
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLATFORM_BASE_ADDRESS_H__ */
diff --git a/platform/ext/target/musca_a/Device/Include/cmsis_cpu.h b/platform/ext/target/musca_a/Device/Include/platform_description.h
similarity index 66%
rename from platform/ext/target/musca_a/Device/Include/cmsis_cpu.h
rename to platform/ext/target/musca_a/Device/Include/platform_description.h
index b65df25..e5760c7 100644
--- a/platform/ext/target/musca_a/Device/Include/cmsis_cpu.h
+++ b/platform/ext/target/musca_a/Device/Include/platform_description.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 ARM Limited
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -14,10 +14,12 @@
* limitations under the License.
*/
-#ifndef __CMSIS_CPU_H__
-#define __CMSIS_CPU_H__
+#ifndef __PLATFORM_DESCRIPTION_H__
+#define __PLATFORM_DESCRIPTION_H__
-#include "system_core_musca.h"
-#include "core_cm33.h"
+#include "platform_base_address.h"
+#include "platform_pins.h"
+#include "platform_regs.h"
+#include "cmsis.h"
-#endif /* __CMSIS_CPU_H__ */
+#endif /* __PLATFORM_DESCRIPTION_H__ */
diff --git a/platform/ext/target/musca_a/Device/Include/platform_irq.h b/platform/ext/target/musca_a/Device/Include/platform_irq.h
new file mode 100644
index 0000000..886f037
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Include/platform_irq.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __PLATFORM_IRQ_H__
+#define __PLATFORM_IRQ_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ======================================================================= */
+/* ================== Interrupt Number Definition ===================== */
+/* ======================================================================= */
+
+
+typedef enum IRQn
+{
+/* =============== Core Specific Interrupt Numbers ====================== */
+ NonMaskableInt_IRQn = -14, /* -14 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* -13 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* -12 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* -11 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* -10 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* -9 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* -5 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* -4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* -2 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* -1 System Tick Interrupt */
+
+/* ============= Musca Specific SSE-200 Interrupt Numbers =============== */
+ NS_WATCHDOG_RESET_IRQn = 0, /* Non-Secure Watchdog Reset Request
+ * Interrupt */
+ NS_WATCHDOG_IRQn = 1, /* Non-Secure Watchdog Interrupt */
+ S32K_TIMER_IRQn = 2, /* S32K Timer Interrupt */
+ TIMER0_IRQn = 3, /* CMSDK Timer 0 Interrupt */
+ TIMER1_IRQn = 4, /* CMSDK Timer 1 Interrupt */
+ DUALTIMER_IRQn = 5, /* CMSDK Dual Timer Interrupt */
+ MHU0_IRQn = 6, /* Message Handling Unit 0 Interrupt */
+ MHU1_IRQn = 7, /* Message Handling Unit 1 Interrupt */
+ CRYPTOCELL_IRQn = 8, /* CryptoCell-312 Interrupt */
+ S_MPC_COMBINED_IRQn = 9, /* Secure Combined MPC Interrupt */
+ S_PPC_COMBINED_IRQn = 10, /* Secure Combined PPC Interrupt */
+ S_MSC_COMBINED_IRQn = 11, /* Secure Combined MSC Interrupt */
+ S_BRIDGE_ERR_IRQn = 12, /* Secure Bridge Error Combined
+ * Interrupt */
+ I_CACHE_INV_ERR_IRQn = 13, /* Instruction Cache Invalidation
+ * Interrupt */
+ /* Reserved = 14, Reserved */
+ SYS_PPU_IRQn = 15, /* System PPU Interrupt */
+ CPU0_PPU_IRQn = 16, /* CPU0 PPU Interrupt */
+ CPU1_PPU_IRQn = 17, /* CPU1 PPU Interrupt */
+ CPU0_DGB_PPU_IRQn = 18, /* CPU0 Debug PPU Interrupt */
+ CPU1_DGB_PPU_IRQn = 19, /* CPU1 Debug PPU Interrupt */
+ CRYPTOCELL_PPU_IRQn = 20, /* CryptoCell PPU Interrupt */
+ /* Reserved = 21, Reserved */
+ RAM0_PPU_IRQn = 22, /* RAM 0 PPU Interrupt */
+ RAM1_PPU_IRQn = 23, /* RAM 1 PPU Interrupt */
+ RAM2_PPU_IRQn = 24, /* RAM 2 PPU Interrupt */
+ RAM3_PPU_IRQn = 25, /* RAM 3 PPU Interrupt */
+ DEBUG_PPU_IRQn = 26, /* Debug PPU Interrupt */
+ /* Reserved = 27, Reserved */
+ CPU0_CTI_IRQn = 28, /* CPU0 CTI Interrupt */
+ CPU1_CTI_IRQn = 29, /* CPU1 CTI Interrupt */
+ /* Reserved = 30, Reserved */
+ /* Reserved = 31, Reserved */
+/* ============ Musca Specific Expansion Interrupt Numbers ============== */
+ /* None = 32, Not used. Tied to 0 */
+ GpTimer_IRQn = 33, /* General Purpose Timer Interrupt */
+ I2C0_IRQn = 34, /* I2C0 Interrupt */
+ I2C1_IRQn = 35, /* I2C1 Interrupt */
+ I2S_IRQn = 36, /* I2S Interrupt */
+ SPI_IRQn = 37, /* SPI Interrupt */
+ QSPI_IRQn = 38, /* QSPI Interrupt */
+ UART0_Rx_IRQn = 39, /* UART0 receive FIFO interrupt */
+ UART0_Tx_IRQn = 40, /* UART0 transmit FIFO interrupt */
+ UART0_RxTimeout_IRQn = 41, /* UART0 receive timeout interrupt */
+ UART0_ModemStatus_IRQn = 42, /* UART0 modem status interrupt */
+ UART0_Error_IRQn = 43, /* UART0 error interrupt */
+ UART0_IRQn = 44, /* UART0 interrupt */
+ UART1_Rx_IRQn = 45, /* UART1 receive FIFO interrupt */
+ UART1_Tx_IRQn = 46, /* UART1 transmit FIFO interrupt */
+ UART1_RxTimeout_IRQn = 47, /* UART1 receive timeout interrupt */
+ UART1_ModemStatus_IRQn = 48, /* UART1 modem status interrupt */
+ UART1_Error_IRQn = 49, /* UART1 error interrupt */
+ UART1_IRQn = 50, /* UART1 interrupt */
+ GPIO_0_IRQn = 51, /* GPIO 0 interrupt */
+ GPIO_1_IRQn = 52, /* GPIO 1 interrupt */
+ GPIO_2_IRQn = 53, /* GPIO 2 interrupt */
+ GPIO_3_IRQn = 54, /* GPIO 3 interrupt */
+ GPIO_4_IRQn = 55, /* GPIO 4 interrupt */
+ GPIO_5_IRQn = 56, /* GPIO 5 interrupt */
+ GPIO_6_IRQn = 57, /* GPIO 6 interrupt */
+ GPIO_7_IRQn = 58, /* GPIO 7 interrupt */
+ GPIO_8_IRQn = 59, /* GPIO 8 interrupt */
+ GPIO_9_IRQn = 60, /* GPIO 9 interrupt */
+ GPIO_10_IRQn = 61, /* GPIO 10 interrupt */
+ GPIO_11_IRQn = 62, /* GPIO 11 interrupt */
+ GPIO_12_IRQn = 63, /* GPIO 12 interrupt */
+ GPIO_13_IRQn = 64, /* GPIO 13 interrupt */
+ GPIO_14_IRQn = 65, /* GPIO 14 interrupt */
+ GPIO_15_IRQn = 66, /* GPIO 15 interrupt */
+ Combined_IRQn = 67, /* Combined interrupt */
+ PVT_IRQn = 68, /* PVT sensor interrupt */
+ /* Reserved = 69, Reserved */
+ PWM_0_IRQn = 70, /* PWM0 interrupt */
+ RTC_IRQn = 71, /* RTC interrupt */
+ GpTimer1_IRQn = 72, /* General Purpose Timer Alarm1
+ * Interrupt */
+ GpTimer0_IRQn = 73, /* General Purpose Timer Alarm0
+ * Interrupt */
+ PWM_1_IRQn = 74, /* PWM1 interrupt */
+ PWM_2_IRQn = 75, /* PWM2 interrupt */
+ IOMUX_IRQn = 76, /* IOMUX interrupt */
+} IRQn_Type;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLATFORM_IRQ_H__ */
diff --git a/platform/ext/target/musca_a/Device/Include/platform_retarget_pins.h b/platform/ext/target/musca_a/Device/Include/platform_pins.h
similarity index 81%
rename from platform/ext/target/musca_a/Device/Include/platform_retarget_pins.h
rename to platform/ext/target/musca_a/Device/Include/platform_pins.h
index fed5d66..5d1d927 100644
--- a/platform/ext/target/musca_a/Device/Include/platform_retarget_pins.h
+++ b/platform/ext/target/musca_a/Device/Include/platform_pins.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017 ARM Limited
+ * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -15,12 +15,12 @@
*/
/**
- * \file platform_retarget_pins.h
+ * \file platform_pins.h
* \brief This file defines all the pins for this platform.
*/
-#ifndef __ARM_LTD_MUSCA_RETARGET_PINS_H__
-#define __ARM_LTD_MUSCA_RETARGET_PINS_H__
+#ifndef __PLATFORM_PINS__
+#define __PLATFORM_PINS__
/* AHB GPIO pin names */
enum arm_gpio_pin_name_t {
@@ -42,4 +42,4 @@
AHB_GPIO0_15,
};
-#endif /* __ARM_LTD_MUSCA_RETARGET_PINS_H__ */
+#endif /* __PLATFORM_PINS__ */
diff --git a/platform/ext/target/musca_a/Device/Include/platform_regs.h b/platform/ext/target/musca_a/Device/Include/platform_regs.h
index fe76185..aef8d89 100644
--- a/platform/ext/target/musca_a/Device/Include/platform_regs.h
+++ b/platform/ext/target/musca_a/Device/Include/platform_regs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018 Arm Limited
+ * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -14,11 +14,11 @@
* limitations under the License.
*/
-#ifndef __ARM_LTD_MUSCA_REGS_H__
-#define __ARM_LTD_MUSCA_REGS_H__
+#ifndef __PLATFORM_REGS__
+#define __PLATFORM_REGS__
#include <stdint.h>
-#include "platform_retarget.h"
+#include "platform_base_address.h"
/* sysinfo memory mapped register access structure */
struct sysinfo_t {
@@ -261,8 +261,8 @@
volatile uint32_t pidr2; /* (R/W) Peripheral ID 2 */
volatile uint32_t pidr3; /* (R/W) Peripheral ID 3 */
volatile uint32_t cidr0; /* (R/W) Component ID 0 */
- volatile uint32_t cidr2; /* (R/W) Component ID 1 */
- volatile uint32_t cidr1; /* (R/W) Component ID 2 */
+ volatile uint32_t cidr1; /* (R/W) Component ID 1 */
+ volatile uint32_t cidr2; /* (R/W) Component ID 2 */
volatile uint32_t cidr3; /* (R/W) Component ID 3 */
};
@@ -302,4 +302,4 @@
/* End of ARM AHB PPCEXP3 peripherals definition */
-#endif /* __ARM_LTD_MUSCA_REGS_H__ */
+#endif /* __PLATFORM_REGS__ */
diff --git a/platform/ext/target/musca_a/Device/Include/platform_retarget.h b/platform/ext/target/musca_a/Device/Include/platform_retarget.h
deleted file mode 100644
index 87adfdc..0000000
--- a/platform/ext/target/musca_a/Device/Include/platform_retarget.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2017-2018 Arm Limited
- *
- * Licensed under the Apache License Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing software
- * distributed under the License is distributed on an "AS IS" BASIS
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * \file platform_retarget.h
- * \brief This file defines all the peripheral base addresses for Musca platform.
- */
-
-#ifndef __ARM_LTD_MUSCA_RETARGET_H__
-#define __ARM_LTD_MUSCA_RETARGET_H__
-
-#include "platform_regs.h" /* Platform registers */
-#include "system_cmsdk_musca.h"
-
-
-/* SRAM MPC ranges and limits */
-/* Internal memory */
-#define MPC_ISRAM0_RANGE_BASE_NS 0x20000000
-#define MPC_ISRAM0_RANGE_LIMIT_NS 0x20007FFF
-#define MPC_ISRAM0_RANGE_BASE_S 0x30000000
-#define MPC_ISRAM0_RANGE_LIMIT_S 0x30007FFF
-
-#define MPC_ISRAM1_RANGE_BASE_NS 0x20008000
-#define MPC_ISRAM1_RANGE_LIMIT_NS 0x2000FFFF
-#define MPC_ISRAM1_RANGE_BASE_S 0x30008000
-#define MPC_ISRAM1_RANGE_LIMIT_S 0x3000FFFF
-
-#define MPC_ISRAM2_RANGE_BASE_NS 0x20010000
-#define MPC_ISRAM2_RANGE_LIMIT_NS 0x20017FFF
-#define MPC_ISRAM2_RANGE_BASE_S 0x30010000
-#define MPC_ISRAM2_RANGE_LIMIT_S 0x30017FFF
-
-#define MPC_ISRAM3_RANGE_BASE_NS 0x20018000
-#define MPC_ISRAM3_RANGE_LIMIT_NS 0x2001FFFF
-#define MPC_ISRAM3_RANGE_BASE_S 0x30018000
-#define MPC_ISRAM3_RANGE_LIMIT_S 0x3001FFFF
-
-/* Code SRAM memory */
-#define MPC_CODE_SRAM_RANGE_BASE_NS (0x00000000)
-#define MPC_CODE_SRAM_RANGE_LIMIT_NS (0x00200000)
-#define MPC_CODE_SRAM_RANGE_BASE_S (0x10000000)
-#define MPC_CODE_SRAM_RANGE_LIMIT_S (0x10200000)
-
-/* QSPI Flash memory */
-#define MPC_QSPI_RANGE_BASE_NS (0x00200000)
-#define MPC_QSPI_RANGE_LIMIT_NS (0x00240000)
-#define MPC_QSPI_RANGE_BASE_S (0x10200000)
-#define MPC_QSPI_RANGE_LIMIT_S (0x10240000)
-
-#endif /* __ARM_LTD_MUSCA_RETARGET_H__ */
diff --git a/platform/ext/target/musca_a/Device/Include/system_cmsdk_musca.h b/platform/ext/target/musca_a/Device/Include/system_cmsdk_musca.h
deleted file mode 100644
index 1c9c419..0000000
--- a/platform/ext/target/musca_a/Device/Include/system_cmsdk_musca.h
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * Copyright (c) 2009-2018 Arm Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * This file is derivative of CMSIS V5.01 Device\_Template_Vendor\Vendor\Device\Include\Device.h
- * https://github.com/ARM-software/CMSIS_5/tree/5.0.1
- * Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
- */
-
-#ifndef SYSTEM_CMSDK_MUSCA_H
-#define SYSTEM_CMSDK_MUSCA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* =========================================================================================================================== */
-/* ================ Interrupt Number Definition ================ */
-/* =========================================================================================================================== */
-
-typedef enum IRQn
-{
-/* =========================================== Core Specific Interrupt Numbers ============================================= */
- NonMaskableInt_IRQn = -14, /* -14 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* -13 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /* -12 Memory Management Interrupt */
- BusFault_IRQn = -11, /* -11 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /* -10 Usage Fault Interrupt */
- SecureFault_IRQn = -9, /* -9 Secure Fault Interrupt */
- SVCall_IRQn = -5, /* -5 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /* -4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /* -2 Pend SV Interrupt */
- SysTick_IRQn = -1, /* -1 System Tick Interrupt */
-
-/* ======================================== Musca Specific SSE-200 Interrupt Numbers ====================================== */
- NS_WATCHDOG_RESET_IRQn = 0, /* Non-Secure Watchdog Reset Request Interrupt */
- NS_WATCHDOG_IRQn = 1, /* Non-Secure Watchdog Interrupt */
- S32K_TIMER_IRQn = 2, /* S32K Timer Interrupt */
- TIMER0_IRQn = 3, /* CMSDK Timer 0 Interrupt */
- TIMER1_IRQn = 4, /* CMSDK Timer 1 Interrupt */
- DUALTIMER_IRQn = 5, /* CMSDK Dual Timer Interrupt */
- MHU0_IRQn = 6, /* Message Handling Unit 0 Interrupt */
- MHU1_IRQn = 7, /* Message Handling Unit 1 Interrupt */
- CRYPTOCELL_IRQn = 8, /* CryptoCell-312 Interrupt */
- S_MPC_COMBINED_IRQn = 9, /* Secure Combined MPC Interrupt */
- S_PPC_COMBINED_IRQn = 10, /* Secure Combined PPC Interrupt */
- S_MSC_COMBINED_IRQn = 11, /* Secure Combined MSC Interrupt */
- S_BRIDGE_ERR_IRQn = 12, /* Secure Bridge Error Combined Interrupt */
- I_CACHE_INV_ERR_IRQn = 13, /* Instruction Cache Invalidation Interrupt */
- /* Reserved = 14, Reserved */
- SYS_PPU_IRQn = 15, /* System PPU Interrupt */
- CPU0_PPU_IRQn = 16, /* CPU0 PPU Interrupt */
- CPU1_PPU_IRQn = 17, /* CPU1 PPU Interrupt */
- CPU0_DGB_PPU_IRQn = 18, /* CPU0 Debug PPU Interrupt */
- CPU1_DGB_PPU_IRQn = 19, /* CPU1 Debug PPU Interrupt */
- CRYPTOCELL_PPU_IRQn = 20, /* CryptoCell PPU Interrupt */
- /* Reserved = 21, Reserved */
- RAM0_PPU_IRQn = 22, /* RAM 0 PPU Interrupt */
- RAM1_PPU_IRQn = 23, /* RAM 1 PPU Interrupt */
- RAM2_PPU_IRQn = 24, /* RAM 2 PPU Interrupt */
- RAM3_PPU_IRQn = 25, /* RAM 3 PPU Interrupt */
- DEBUG_PPU_IRQn = 26, /* Debug PPU Interrupt */
- /* Reserved = 27, Reserved */
- CPU0_CTI_IRQn = 28, /* CPU0 CTI Interrupt */
- CPU1_CTI_IRQn = 29, /* CPU1 CTI Interrupt */
- /* Reserved = 30, Reserved */
- /* Reserved = 31, Reserved */
-/* ========================================== Musca Specific Expansion Interrupt Numbers =================================== */
- /* None = 32, Not used. Tied to 0 */
- GpTimer_IRQn = 33, /* General Purpose Timer Interrupt */
- I2C0_IRQn = 34, /* I2C0 Interrupt */
- I2C1_IRQn = 35, /* I2C1 Interrupt */
- I2S_IRQn = 36, /* I2S Interrupt */
- SPI_IRQn = 37, /* SPI Interrupt */
- QSPI_IRQn = 38, /* QSPI Interrupt */
- UART0_Rx_IRQn = 39, /* UART0 receive FIFO interrupt */
- UART0_Tx_IRQn = 40, /* UART0 transmit FIFO interrupt */
- UART0_RxTimeout_IRQn = 41, /* UART0 receive timeout interrupt */
- UART0_ModemStatus_IRQn = 42, /* UART0 modem status interrupt */
- UART0_Error_IRQn = 43, /* UART0 error interrupt */
- UART0_IRQn = 44, /* UART0 interrupt */
- UART1_Rx_IRQn = 45, /* UART1 receive FIFO interrupt */
- UART1_Tx_IRQn = 46, /* UART1 transmit FIFO interrupt */
- UART1_RxTimeout_IRQn = 47, /* UART1 receive timeout interrupt */
- UART1_ModemStatus_IRQn = 48, /* UART1 modem status interrupt */
- UART1_Error_IRQn = 49, /* UART1 error interrupt */
- UART1_IRQn = 50, /* UART1 interrupt */
- GPIO_0_IRQn = 51, /* GPIO 0 interrupt */
- GPIO_1_IRQn = 52, /* GPIO 1 interrupt */
- GPIO_2_IRQn = 53, /* GPIO 2 interrupt */
- GPIO_3_IRQn = 54, /* GPIO 3 interrupt */
- GPIO_4_IRQn = 55, /* GPIO 4 interrupt */
- GPIO_5_IRQn = 56, /* GPIO 5 interrupt */
- GPIO_6_IRQn = 57, /* GPIO 6 interrupt */
- GPIO_7_IRQn = 58, /* GPIO 7 interrupt */
- GPIO_8_IRQn = 59, /* GPIO 8 interrupt */
- GPIO_9_IRQn = 60, /* GPIO 9 interrupt */
- GPIO_10_IRQn = 61, /* GPIO 10 interrupt */
- GPIO_11_IRQn = 62, /* GPIO 11 interrupt */
- GPIO_12_IRQn = 63, /* GPIO 12 interrupt */
- GPIO_13_IRQn = 64, /* GPIO 13 interrupt */
- GPIO_14_IRQn = 65, /* GPIO 14 interrupt */
- GPIO_15_IRQn = 66, /* GPIO 15 interrupt */
- Combined_IRQn = 67, /* Combined interrupt */
- PVT_IRQn = 68, /* PVT sensor interrupt */
- /* Reserved = 69, Reserved */
- PWM_0_IRQn = 70, /* PWM0 interrupt */
- RTC_IRQn = 71, /* RTC interrupt */
- GpTimer0_IRQn = 72, /* General Purpose Timer0 Interrupt */
- GpTimer1_IRQn = 73, /* General Purpose Timer1 Interrupt */
- PWM_1_IRQn = 74, /* PWM1 interrupt */
- PWM_2_IRQn = 75, /* PWM2 interrupt */
- IOMUX_IRQn = 76, /* IOMUX interrupt */
-} IRQn_Type;
-
-
-
-/* =========================================================================================================================== */
-/* ================ Processor and Core Peripheral Section ================ */
-/* =========================================================================================================================== */
-
-#include "system_core_musca.h"
-
-/** @} */ /* End of group Configuration_of_CMSIS */
-
-
-#include <core_cm33.h> /*!< ARM Cortex-M33 processor and core peripherals */
-#include "system_musca.h" /*!< Musca System */
-
-
-
-/* ======================================== Start of section using anonymous unions ======================================== */
-#if defined (__CC_ARM)
- #pragma push
- #pragma anon_unions
-#elif defined (__ICCARM__)
- #pragma language=extended
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang diagnostic push
- #pragma clang diagnostic ignored "-Wc11-extensions"
- #pragma clang diagnostic ignored "-Wreserved-id-macro"
-#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
-#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
-#elif defined (__TASKING__)
- #pragma warning 586
-#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
-#else
- #warning Not supported compiler type
-#endif
-
-
-/* =========================================================================================================================== */
-/* ================ Device Specific Peripheral Section ================ */
-/* =========================================================================================================================== */
-
-
-/** @addtogroup Device_Peripheral_peripherals
- * @{
- */
-
-/*@}*/ /* end of group <Device>_Peripherals */
-
-/* ========================================= End of section using anonymous unions ========================================= */
-#if defined (__CC_ARM)
- #pragma pop
-#elif defined (__ICCARM__)
- /* leave anonymous unions enabled */
-#elif (__ARMCC_VERSION >= 6010050)
- #pragma clang diagnostic pop
-#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
-#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
-#elif defined (__TASKING__)
- #pragma warning restore
-#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
-#else
- #warning Not supported compiler type
-#endif
-
-
-/* =========================================================================================================================== */
-/* ================ Device Specific Peripheral Address Map ================ */
-/* =========================================================================================================================== */
-
-
-/** @addtogroup Device_Peripheral_peripheralAddr
- * @{
- */
-
-/* Non-Secure Peripheral and SRAM base address */
-#define MUSCA_CODE_SRAM_NS_BASE (0x00000000UL) /*!< (Non-Secure Code SRAM ) Base Address */
-#define MUSCA_QSPI_FLASH_NS_BASE (0x00200000UL) /*!< (Non-Secure QSPI FLASH ) Base Address */
-#define MUSCA_OTP_NS_BASE (0x0E000000UL) /*!< (Non-Secure OTP ) Base Address */
-#define MUSCA_SRAM_NS_BASE (0x20000000UL) /*!< (Non-Secure Internal SRAM ) Base Address */
-#define MUSCA_BASE_ELEMENT_NS_BASE (0x40000000UL) /*!< (Non-Secure Base Peripherals ) Base Address */
-#define MUSCA_CMSDK_TIMER0_NS_BASE (0x40000000UL) /*!< (Non-Secure CMSDK Timer0 ) Base Address */
-#define MUSCA_CMSDK_TIMER1_NS_BASE (0x40001000UL) /*!< (Non-Secure CMSDK Timer1 ) Base Address */
-#define MUSCA_CMSDK_DUALTIMER_NS_BASE (0x40002000UL) /*!< (Non-Secure CMSDK Dual Timer ) Base Address */
-#define MUSCA_MHU0_NS_BASE (0x40003000UL) /*!< (Non-Secure MHU0 ) Base Address */
-#define MUSCA_MHU1_NS_BASE (0x40004000UL) /*!< (Non-Secure MHU1 ) Base Address */
-#define MUSCA_CPU_ELEMENT_NS_BASE (0x40010000UL) /*!< (Non-Secure CPU Peripherals ) Base Address */
-#define MUSCA_SYSTEM_INFO_NS_BASE (0x40020000UL) /*!< (Non-Secure System Info ) Base Address */
-#define MUSCA_CMSDK_S32KTIMER_NS_BASE (0x4002F000UL) /*!< (Non-Secure CMSDK S32K Timer ) Base Address */
-#define MUSCA_NSPCTRL_NS_BASE (0x40080000UL) /*!< (Non-Secure Privilege Ctrl Blk) Base Address */
-#define MUSCA_CMSDK_WATCHDOG_NS_BASE (0x40081000UL) /*!< (Non-Secure CMSDK Watchdog ) Base Address */
-#define MUSCA_UART0_NS_BASE (0x40101000UL) /*!< (Non-Secure UART0 ) Base Address */
-#define MUSCA_UART1_NS_BASE (0x40102000UL) /*!< (Non-Secure UART1 ) Base Address */
-#define MUSCA_SPI0_NS_BASE (0x40103000UL) /*!< (Non-Secure SPI0 ) Base Address */
-#define MUSCA_I2C0_NS_BASE (0x40104000UL) /*!< (Non-Secure I2C0 ) Base Address */
-#define MUSCA_I2C1_NS_BASE (0x40105000UL) /*!< (Non-Secure I2C1 ) Base Address */
-#define MUSCA_I2S_NS_BASE (0x40106000UL) /*!< (Non-Secure I2S ) Base Address */
-#define MUSCA_PWM0_NS_BASE (0x40107000UL) /*!< (Non-Secure PWM0 ) Base Address */
-#define MUSCA_RTC_NS_BASE (0x40108000UL) /*!< (Non-Secure RTC ) Base Address */
-#define MUSCA_PVT_NS_BASE (0x40109000UL) /*!< (Non-Secure PVT sensors ) Base Address */
-#define MUSCA_QSPI_REG_NS_BASE (0x4010A000UL) /*!< (Non-Secure QSPI registers ) Base Address */
-#define MUSCA_TIMER_NS_BASE (0x4010B000UL) /*!< (Non-Secure Timer ) Base Address */
-#define MUSCA_SCC_NS_BASE (0x4010C000UL) /*!< (Non-Secure SCC ) Base Address */
-#define MUSCA_PWM1_NS_BASE (0x4010E000UL) /*!< (Non-Secure PWM1 ) Base Address */
-#define MUSCA_PWM2_NS_BASE (0x4010F000UL) /*!< (Non-Secure PWM2 ) Base Address */
-#define MUSCA_GPIO_NS_BASE (0x40110000UL) /*!< (Non-Secure GPIO ) Base Address */
-#define MUSCA_QSPI_MPC_NS_BASE (0x40120000UL) /*!< (Non-Secure QSPI MPC ) Base Address */
-#define MUSCA_CODE_SRAM_MPC_NS_BASE (0x40130000UL) /*!< (Non-Secure Code SRAM MPC ) Base Address */
-#define MUSCA_DEFAULT_SLAVE_NS_BASE (0x60000000UL) /*!< (Non-Secure Unused AHB ) Base Address */
-/* Secure Peripheral and SRAM base address */
-#define MUSCA_CODE_SRAM_S_BASE (0x10000000UL) /*!< (Secure Code SRAM ) Base Address */
-#define MUSCA_QSPI_FLASH_S_BASE (0x10200000UL) /*!< (Secure QSPI FLASH ) Base Address */
-#define MUSCA_OTP_S_BASE (0x1E000000UL) /*!< (Secure OTP ) Base Address */
-#define MUSCA_SRAM_S_BASE (0x30000000UL) /*!< (Secure Internal SRAM ) Base Address */
-#define MUSCA_BASE_ELEMENT_S_BASE (0x50000000UL) /*!< (Secure Base Peripherals ) Base Address */
-#define MUSCA_MHU0_S_BASE (0x50003000UL) /*!< (Secure MHU0 ) Base Address */
-#define MUSCA_MHU1_S_BASE (0x50004000UL) /*!< (Secure MHU1 ) Base Address */
-#define MUSCA_CPU_ELEMENT_S_BASE (0x50010000UL) /*!< (Secure CPU Peripherals ) Base Address */
-#define MUSCA_SYSTEM_INFO_S_BASE (0x50020000UL) /*!< (Secure System Info ) Base Address */
-#define MUSCA_SYSTEM_CTRL_S_BASE (0x50021000UL) /*!< (Secure System Control ) Base Address */
-#define MUSCA_CMSDK_S32KTIMER_S_BASE (0x5002F000UL) /*!< (Secure CMSDK S32K Timer ) Base Address */
-#define MUSCA_CMSDK_TIMER0_S_BASE (0x50000000UL) /*!< (Secure CMSDK Timer0 ) Base Address */
-#define MUSCA_CMSDK_TIMER1_S_BASE (0x50001000UL) /*!< (Secure CMSDK Timer1 ) Base Address */
-#define MUSCA_CMSDK_DUALTIMER_S_BASE (0x50002000UL) /*!< (Secure CMSDK Dual Timer ) Base Address */
-#define MUSCA_SPCTRL_S_BASE (0x50080000UL) /*!< (Secure Privilege Ctrl Blk) Base Address */
-#define MUSCA_CMSDK_WATCHDOG_S_BASE (0x50081000UL) /*!< (Secure CMSDK Watchdog ) Base Address */
-#define MUSCA_MPC_SRAM0_S_BASE (0x50083000UL) /*!< (Secure MPC SRAM Bank 0 ) Base Address */
-#define MUSCA_MPC_SRAM1_S_BASE (0x50084000UL) /*!< (Secure MPC SRAM Bank 1 ) Base Address */
-#define MUSCA_MPC_SRAM2_S_BASE (0x50085000UL) /*!< (Secure MPC SRAM Bank 2 ) Base Address */
-#define MUSCA_MPC_SRAM3_S_BASE (0x50086000UL) /*!< (Secure MPC SRAM Bank 3 ) Base Address */
-#define MUSCA_UART0_S_BASE (0x50101000UL) /*!< (Secure UART0 ) Base Address */
-#define MUSCA_UART1_S_BASE (0x50102000UL) /*!< (Secure UART1 ) Base Address */
-#define MUSCA_SPI0_S_BASE (0x50103000UL) /*!< (Secure SPI0 ) Base Address */
-#define MUSCA_I2C0_S_BASE (0x50104000UL) /*!< (Secure I2C0 ) Base Address */
-#define MUSCA_I2C1_S_BASE (0x50105000UL) /*!< (Secure I2C1 ) Base Address */
-#define MUSCA_I2S_S_BASE (0x50106000UL) /*!< (Secure I2S ) Base Address */
-#define MUSCA_PWM0_S_BASE (0x50107000UL) /*!< (Secure PWM0 ) Base Address */
-#define MUSCA_RTC_S_BASE (0x50108000UL) /*!< (Secure RTC ) Base Address */
-#define MUSCA_PVT_S_BASE (0x50109000UL) /*!< (Secure PVT sensors ) Base Address */
-#define MUSCA_QSPI_REG_S_BASE (0x5010A000UL) /*!< (Secure QSPI registers ) Base Address */
-#define MUSCA_TIMER_S_BASE (0x5010B000UL) /*!< (Secure Timer ) Base Address */
-#define MUSCA_SCC_S_BASE (0x5010C000UL) /*!< (Secure SCC ) Base Address */
-#define MUSCA_PWM1_S_BASE (0x5010E000UL) /*!< (Secure PWM1 ) Base Address */
-#define MUSCA_PWM2_S_BASE (0x5010F000UL) /*!< (Secure PWM2 ) Base Address */
-#define MUSCA_GPIO_S_BASE (0x50110000UL) /*!< (Secure GPIO ) Base Address */
-#define MUSCA_QSPI_MPC_S_BASE (0x50120000UL) /*!< (Secure QSPI MPC ) Base Address */
-#define MUSCA_CODE_SRAM_MPC_S_BASE (0x50130000UL) /*!< (Secure Code SRAM MPC ) Base Address */
-#define MUSCA_DEFAULT_SLAVE_S_BASE (0x70000000UL) /*!< (Secure Unused AHB ) Base Address */
-
-
-/* Peripheral memory map */
-
-/** @} */ /* End of group Device_Peripheral_peripheralAddr */
-
-
-/* =========================================================================================================================== */
-/* ================ Peripheral declaration ================ */
-/* =========================================================================================================================== */
-
-
-/** @addtogroup Device_Peripheral_declaration
- * @{
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SYSTEM_CMSDK_MUSCA_H */
diff --git a/platform/ext/target/musca_a/Device/Include/system_musca.h b/platform/ext/target/musca_a/Device/Include/system_core_init.h
similarity index 89%
rename from platform/ext/target/musca_a/Device/Include/system_musca.h
rename to platform/ext/target/musca_a/Device/Include/system_core_init.h
index 8a6802a..71005db 100644
--- a/platform/ext/target/musca_a/Device/Include/system_musca.h
+++ b/platform/ext/target/musca_a/Device/Include/system_core_init.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -18,8 +18,10 @@
*
*/
-#ifndef SYSTEM_MUSCA_H
-#define SYSTEM_MUSCA_H
+#ifndef __SYSTEM_CORE_INIT_H__
+#define __SYSTEM_CORE_INIT_H__
+
+#include <stdint.h>
#ifdef __cplusplus
extern "C" {
@@ -51,4 +53,4 @@
}
#endif
-#endif /* SYSTEM_MUSCA_H */
+#endif /* __SYSTEM_CORE_INIT_H__ */
diff --git a/platform/ext/target/musca_a/Device/Include/system_core_musca.h b/platform/ext/target/musca_a/Device/Include/system_core_musca.h
deleted file mode 100644
index aac5b0d..0000000
--- a/platform/ext/target/musca_a/Device/Include/system_core_musca.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (c) 2018 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef SYSTEM_CORE_MUSCA_H
-#define SYSTEM_CORE_MUSCA_H
-
-#ifdef DUAL_CORE
-/* Both cores are used */
-/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
-#define __CM33_REV 0x0001U /* Core revision r0p1 */
-#define __SAUREGION_PRESENT 1U /* SAU regions present */
-#define __MPU_PRESENT 1U /* MPU present */
-#define __VTOR_PRESENT 1U /* VTOR present */
-#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
-
-#if defined CORE0
-#define __FPU_PRESENT 0U /* no FPU present */
-#define __DSP_PRESENT 0U /* no DSP extension present */
-#elif defined CORE1
-#define __FPU_PRESENT 1U /* FPU present */
-#define __DSP_PRESENT 1U /* DSP extension present */
-#else
-#error "Either CORE0 or CORE1 must be defined"
-#endif /* CORE0/1 */
-
-#else /* DUAL_CORE */
-
-/* Single core is used */
-/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
-#define __CM33_REV 0x0000U /* Core revision r0p1 */
-#define __SAUREGION_PRESENT 1U /* SAU regions present */
-#define __MPU_PRESENT 1U /* MPU present */
-#define __VTOR_PRESENT 1U /* VTOR present */
-#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 0U /* no FPU present */
-#define __DSP_PRESENT 0U /* no DSP extension present */
-#endif /* DUAL_CORE */
-
-#endif /* SYSTEM_CORE_MUSCA_H */
-
diff --git a/platform/ext/target/musca_a/Device/Source/armclang/musca_bl2.sct b/platform/ext/target/musca_a/Device/Source/armclang/musca_bl2.sct
index c954dc2..4e07ea9 100644
--- a/platform/ext/target/musca_a/Device/Source/armclang/musca_bl2.sct
+++ b/platform/ext/target/musca_a/Device/Source/armclang/musca_bl2.sct
@@ -1,7 +1,7 @@
#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
/*
- * Copyright (c) 2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -22,7 +22,7 @@
ER_CODE BL2_CODE_START {
startup_cmsdk_musca_bl2.o (RESET +First)
startup_cmsdk_musca_bl2.o (+RO)
- system_cmsdk_musca.o (+RO) ; SystemInit
+ system_core_init.o (+RO) ; SystemInit
*(InRoot$$Sections) ; ARM library sections
}
diff --git a/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct b/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct
index 442f1c1..3897ff7 100644
--- a/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct
+++ b/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct
@@ -1,7 +1,7 @@
#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
/*
- * Copyright (c) 2018-2019 Arm Limited
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -64,7 +64,7 @@
dummy_nv_counters.o (+RO)
dummy_boot_seed.o (+RO)
dummy_device_id.o (+RO)
- platform_retarget_dev.o (+RO)
+ device_definition.o (+RO)
*(SFN)
*armlib*
}
@@ -161,7 +161,7 @@
dummy_nv_counters.o (+RW +ZI)
dummy_boot_seed.o (+RW +ZI)
dummy_device_id.o (+RW +ZI)
- platform_retarget_dev.o (+RW +ZI)
+ device_definition.o (+RW +ZI)
}
TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
diff --git a/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct.template b/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct.template
index 07d3df9..1e89f41 100644
--- a/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct.template
+++ b/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct.template
@@ -1,7 +1,7 @@
#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
/*
- * Copyright (c) 2018-2019 Arm Limited
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -64,7 +64,7 @@
dummy_nv_counters.o (+RO)
dummy_boot_seed.o (+RO)
dummy_device_id.o (+RO)
- platform_retarget_dev.o (+RO)
+ device_definition.o (+RO)
*(SFN)
*armlib*
}
@@ -116,7 +116,7 @@
dummy_nv_counters.o (+RW +ZI)
dummy_boot_seed.o (+RW +ZI)
dummy_device_id.o (+RW +ZI)
- platform_retarget_dev.o (+RW +ZI)
+ device_definition.o (+RW +ZI)
}
TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
diff --git a/platform/ext/target/musca_a/Device/Source/platform_retarget_dev.c b/platform/ext/target/musca_a/Device/Source/device_definition.c
similarity index 70%
rename from platform/ext/target/musca_a/Device/Source/platform_retarget_dev.c
rename to platform/ext/target/musca_a/Device/Source/device_definition.c
index dc02ba7..4699af2 100644
--- a/platform/ext/target/musca_a/Device/Source/platform_retarget_dev.c
+++ b/platform/ext/target/musca_a/Device/Source/device_definition.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018 Arm Limited
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -15,17 +15,17 @@
*/
/**
- * \file platform_retarget_dev.c
+ * \file device_definition.c
* \brief This file defines exports the structures based on the peripheral
* definitions from device_cfg.h.
- * This retarget file is meant to be used as a helper for baremetal
+ * This file is meant to be used as a helper for baremetal
* applications and/or as an example of how to configure the generic
* driver structures.
*/
-#include "platform_retarget_dev.h"
-#include "platform_retarget.h"
-#include "system_cmsdk_musca.h"
+#include "device_cfg.h"
+#include "device_definition.h"
+#include "platform_base_address.h"
/* ======= Peripheral configuration structure definitions ======= */
/* MUSCA A1 SCC driver structures */
@@ -40,6 +40,18 @@
struct musca_a1_scc_dev_t MUSCA_A1_SCC_DEV_NS = {&(MUSCA_A1_SCC_DEV_CFG_NS)};
#endif
+/* CMSDK GPIO driver structures */
+#ifdef GPIO0_CMSDK_S
+static const struct gpio_cmsdk_dev_cfg_t GPIO0_CMSDK_DEV_CFG_S = {
+ .base = MUSCA_GPIO_S_BASE};
+struct gpio_cmsdk_dev_t GPIO0_CMSDK_DEV_S = {&(GPIO0_CMSDK_DEV_CFG_S)};
+#endif
+#ifdef GPIO0_CMSDK_NS
+static const struct gpio_cmsdk_dev_cfg_t GPIO0_CMSDK_DEV_CFG_NS = {
+ .base = MUSCA_GPIO_NS_BASE};
+struct gpio_cmsdk_dev_t GPIO0_CMSDK_DEV_NS = {&(GPIO0_CMSDK_DEV_CFG_NS)};
+#endif
+
/* ARM PPC SSE 200 driver structures */
#ifdef AHB_PPC0_S
static struct ppc_sse200_dev_cfg_t AHB_PPC0_DEV_CFG_S = {
@@ -300,6 +312,86 @@
&(MPC_QSPI_DEV_DATA_NS)};
#endif
+/* ARM MHU driver structures */
+#ifdef ARM_MHU0_S
+static const struct arm_mhu_sse_200_dev_cfg_t ARM_MHU0_DEV_CFG_S = {
+ .base = MUSCA_MHU0_S_BASE};
+struct arm_mhu_sse_200_dev_t ARM_MHU0_DEV_S = {&(ARM_MHU0_DEV_CFG_S)};
+#endif
+#ifdef ARM_MHU0_NS
+static const struct arm_mhu_sse_200_dev_cfg_t ARM_MHU0_DEV_CFG_NS = {
+ .base = MUSCA_MHU0_NS_BASE};
+struct arm_mhu_sse_200_dev_t ARM_MHU0_DEV_NS = {&(ARM_MHU0_DEV_CFG_NS)};
+#endif
+
+#ifdef ARM_MHU1_S
+static const struct arm_mhu_sse_200_dev_cfg_t ARM_MHU1_DEV_CFG_S = {
+ .base = MUSCA_MHU1_S_BASE};
+struct arm_mhu_sse_200_dev_t ARM_MHU1_DEV_S = {&(ARM_MHU1_DEV_CFG_S)};
+#endif
+#ifdef ARM_MHU1_NS
+static const struct arm_mhu_sse_200_dev_cfg_t ARM_MHU1_DEV_CFG_NS = {
+ .base = MUSCA_MHU1_NS_BASE};
+struct arm_mhu_sse_200_dev_t ARM_MHU1_DEV_NS = {&(ARM_MHU1_DEV_CFG_NS)};
+#endif
+
+/* I2C IP6510 driver structures */
+#ifdef I2C0_IP6510_S
+static const struct i2c_ip6510_dev_cfg_t I2C0_IP6510_DEV_CFG_S = {
+ .base = MUSCA_I2C0_S_BASE,
+ .default_mode = I2C_IP6510_MASTER_MODE,
+ .default_bus_speed = I2C_IP6510_SPEED_100KHZ};
+static struct i2c_ip6510_dev_data_t I2C0_IP6510_DEV_DATA_S = {
+ .state = 0,
+ .mode = 0,
+ .bus_speed = 0};
+struct i2c_ip6510_dev_t I2C0_IP6510_DEV_S = {
+ &(I2C0_IP6510_DEV_CFG_S),
+ &(I2C0_IP6510_DEV_DATA_S)};
+#endif
+
+#ifdef I2C0_IP6510_NS
+static const struct i2c_ip6510_dev_cfg_t I2C0_IP6510_DEV_CFG_NS = {
+ .base = MUSCA_I2C0_NS_BASE,
+ .default_mode = I2C_IP6510_MASTER_MODE,
+ .default_bus_speed = I2C_IP6510_SPEED_100KHZ};
+static struct i2c_ip6510_dev_data_t I2C0_IP6510_DEV_DATA_NS = {
+ .state = 0,
+ .mode = 0,
+ .bus_speed = 0};
+struct i2c_ip6510_dev_t I2C0_IP6510_DEV_NS = {
+ &(I2C0_IP6510_DEV_CFG_NS),
+ &(I2C0_IP6510_DEV_DATA_NS)};
+#endif
+
+#ifdef I2C1_IP6510_S
+static const struct i2c_ip6510_dev_cfg_t I2C1_IP6510_DEV_CFG_S = {
+ .base = MUSCA_I2C1_S_BASE,
+ .default_mode = I2C_IP6510_MASTER_MODE,
+ .default_bus_speed = I2C_IP6510_SPEED_100KHZ};
+static struct i2c_ip6510_dev_data_t I2C1_IP6510_DEV_DATA_S = {
+ .state = 0,
+ .mode = 0,
+ .bus_speed = 0};
+struct i2c_ip6510_dev_t I2C1_IP6510_DEV_S = {
+ &(I2C1_IP6510_DEV_CFG_S),
+ &(I2C1_IP6510_DEV_DATA_S)};
+#endif
+
+#ifdef I2C1_IP6510_NS
+static const struct i2c_ip6510_dev_cfg_t I2C1_IP6510_DEV_CFG_NS = {
+ .base = MUSCA_I2C1_NS_BASE,
+ .default_mode = I2C_IP6510_MASTER_MODE,
+ .default_bus_speed = I2C_IP6510_SPEED_100KHZ};
+static struct i2c_ip6510_dev_data_t I2C1_IP6510_DEV_DATA_NS = {
+ .state = 0,
+ .mode = 0,
+ .bus_speed = 0};
+struct i2c_ip6510_dev_t I2C1_IP6510_DEV_NS = {
+ &(I2C1_IP6510_DEV_CFG_NS),
+ &(I2C1_IP6510_DEV_DATA_NS)};
+#endif
+
/* CMSDK Timers driver structures */
#ifdef CMSDK_TIMER0_S
static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_S = {
@@ -335,11 +427,71 @@
&(CMSDK_TIMER1_DEV_DATA_NS)};
#endif
-/* ARM UART PL011 driver structures */
+/* CMSDK Dualtimer driver structures */
+#ifdef CMSDK_DUALTIMER_S
+static const struct dualtimer_cmsdk_dev_cfg_t CMSDK_DUALTIMER_DEV_CFG_S = {
+ .base = MUSCA_CMSDK_DUALTIMER_S_BASE};
+static struct dualtimer_cmsdk_dev_data_t CMSDK_DUALTIMER_DEV_DATA_S = {
+ .is_initialized = 0};
+
+struct dualtimer_cmsdk_dev_t CMSDK_DUALTIMER_DEV_S = {
+ &(CMSDK_DUALTIMER_DEV_CFG_S),
+ &(CMSDK_DUALTIMER_DEV_DATA_S)};
+#endif
+
+#ifdef CMSDK_DUALTIMER_NS
+static const struct dualtimer_cmsdk_dev_cfg_t CMSDK_DUALTIMER_DEV_CFG_NS = {
+ .base = MUSCA_CMSDK_DUALTIMER_NS_BASE};
+static struct dualtimer_cmsdk_dev_data_t CMSDK_DUALTIMER_DEV_DATA_NS = {
+ .is_initialized = 0};
+
+struct dualtimer_cmsdk_dev_t CMSDK_DUALTIMER_DEV_NS = {
+ &(CMSDK_DUALTIMER_DEV_CFG_NS),
+ &(CMSDK_DUALTIMER_DEV_DATA_NS)};
+#endif
+
+/* General-Purpose Timer driver structures */
+#ifdef GP_TIMER_S
+static const struct timer_gp_dev_cfg_t GP_TIMER_DEV_CFG_S = {
+ .base = MUSCA_TIMER_S_BASE};
+static struct timer_gp_dev_data_t GP_TIMER_DEV_DATA_S = {
+ .is_initialized = false,
+ .alarm0_init = 0,
+ .alarm1_init = 0};
+struct timer_gp_dev_t GP_TIMER_DEV_S = {
+ &(GP_TIMER_DEV_CFG_S),
+ &(GP_TIMER_DEV_DATA_S)};
+#endif
+
+#ifdef GP_TIMER_NS
+static const struct timer_gp_dev_cfg_t GP_TIMER_DEV_CFG_NS = {
+ .base = MUSCA_TIMER_NS_BASE};
+static struct timer_gp_dev_data_t GP_TIMER_DEV_DATA_NS = {
+ .is_initialized = false,
+ .alarm0_init = 0,
+ .alarm1_init = 0};
+struct timer_gp_dev_t GP_TIMER_DEV_NS = {
+ &(GP_TIMER_DEV_CFG_NS),
+ &(GP_TIMER_DEV_DATA_NS)};
+#endif
+
+/* PL031 Real-Time Clock structure */
+#ifdef RTC_PL031_S
+static const struct rtc_pl031_dev_cfg_t RTC_PL031_DEV_CFG_S = {
+ .base = MUSCA_RTC_S_BASE};
+struct rtc_pl031_dev_t RTC_PL031_DEV_S = {&(RTC_PL031_DEV_CFG_S)};
+#endif
+
+#ifdef RTC_PL031_NS
+static const struct rtc_pl031_dev_cfg_t RTC_PL031_DEV_CFG_NS = {
+ .base = MUSCA_RTC_NS_BASE};
+struct rtc_pl031_dev_t RTC_PL031_DEV_NS = {&(RTC_PL031_DEV_CFG_NS)};
+#endif
+
#ifdef UART0_PL011_S
static const struct uart_pl011_dev_cfg_t UART0_PL011_DEV_CFG_S = {
.base = MUSCA_UART0_S_BASE,
- .def_baudrate = 115200,
+ .def_baudrate = UART_DEFAULT_BAUD_RATE,
.def_wlen = UART_PL011_WLEN_8,
.def_parity = UART_PL011_PARITY_DISABLED,
.def_stopbit = UART_PL011_STOPBIT_1};
@@ -354,7 +506,7 @@
#ifdef UART0_PL011_NS
static const struct uart_pl011_dev_cfg_t UART0_PL011_DEV_CFG_NS = {
.base = MUSCA_UART0_NS_BASE,
- .def_baudrate = 115200,
+ .def_baudrate = UART_DEFAULT_BAUD_RATE,
.def_wlen = UART_PL011_WLEN_8,
.def_parity = UART_PL011_PARITY_DISABLED,
.def_stopbit = UART_PL011_STOPBIT_1};
@@ -369,7 +521,7 @@
#ifdef UART1_PL011_S
static const struct uart_pl011_dev_cfg_t UART1_PL011_DEV_CFG_S = {
.base = MUSCA_UART1_S_BASE,
- .def_baudrate = 115200,
+ .def_baudrate = UART_DEFAULT_BAUD_RATE,
.def_wlen = UART_PL011_WLEN_8,
.def_parity = UART_PL011_PARITY_DISABLED,
.def_stopbit = UART_PL011_STOPBIT_1};
@@ -384,7 +536,7 @@
#ifdef UART1_PL011_NS
static const struct uart_pl011_dev_cfg_t UART1_PL011_DEV_CFG_NS = {
.base = MUSCA_UART1_NS_BASE,
- .def_baudrate = 115200,
+ .def_baudrate = UART_DEFAULT_BAUD_RATE,
.def_wlen = UART_PL011_WLEN_8,
.def_parity = UART_PL011_PARITY_DISABLED,
.def_stopbit = UART_PL011_STOPBIT_1};
@@ -396,6 +548,25 @@
&(UART1_PL011_DEV_DATA_NS)};
#endif
+/* SPI IP6524 driver structures */
+#ifdef SPI0_IP6524_S
+static const struct spi_ip6524_dev_cfg_t SPI0_DEV_CFG_S = {
+ .base = MUSCA_SPI0_S_BASE};
+static struct spi_ip6524_dev_data_t SPI0_DEV_DATA_S = {
+ .state = 0};
+struct spi_ip6524_dev_t SPI0_DEV_S = {&(SPI0_DEV_CFG_S),
+ &(SPI0_DEV_DATA_S)};
+#endif
+
+#ifdef SPI0_IP6524_NS
+static const struct spi_ip6524_dev_cfg_t SPI0_DEV_CFG_NS = {
+ .base = MUSCA_SPI0_NS_BASE};
+static struct spi_ip6524_dev_data_t SPI0_DEV_DATA_NS = {
+ .state = 0};
+struct spi_ip6524_dev_t SPI0_DEV_NS = {&(SPI0_DEV_CFG_NS),
+ &(SPI0_DEV_DATA_NS)};
+#endif
+
/* QSPI IP6514E driver structures */
#ifdef QSPI_IP6514E_S
static const struct qspi_ip6514e_dev_cfg_t QSPI_DEV_CFG_S = {
@@ -445,7 +616,6 @@
* more.
*/
.size = 0x00800000U, /* 8 MiB */
- .func_state = MT25QL_FUNC_STATE_DEFAULT,
};
#endif
@@ -460,6 +630,5 @@
* more.
*/
.size = 0x00800000U, /* 8 MiB */
- .func_state = MT25QL_FUNC_STATE_DEFAULT,
};
#endif
diff --git a/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld
index 7fae0b2..7730f5e 100644
--- a/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld
+++ b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld
@@ -1,5 +1,5 @@
;/*
-; * Copyright (c) 2018-2019 Arm Limited
+; * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
; *
; * Licensed under the Apache License, Version 2.0 (the "License");
; * you may not use this file except in compliance with the License.
@@ -209,8 +209,8 @@
*dummy_boot_seed.o(.rodata*)
*dummy_device_id.o(.text*)
*dummy_device_id.o(.rodata*)
- *platform_retarget_dev.o(.text*)
- *platform_retarget_dev.o(.rodata*)
+ *device_definition.o(.text*)
+ *device_definition.o(.rodata*)
*(SFN)
*libgcc*:*(.text*)
*libgcc*:*(.rodata*)
@@ -460,7 +460,7 @@
*/dummy_nv_counters.o(.data*)
*/dummy_boot_seed.o(.data*)
*/dummy_device_id.o(.data*)
- */platform_retarget_dev.o(.data*)
+ */device_definition.o(.data*)
. = ALIGN(32);
} > RAM AT> FLASH
Image$$TFM_UNPRIV_RO_DATA$$RW$$Base = ADDR(.TFM_UNPRIV_RO_DATA);
@@ -469,13 +469,13 @@
.TFM_UNPRIV_RO_BSS : ALIGN(32)
{
*/tfm_spm_services.o(.bss*)
- */platform_retarget_dev.o(.bss*)
+ */device_definition.o(.bss*)
*/dummy_crypto_keys.o(.bss*)
*/dummy_nv_counters.o(.bss*)
*/dummy_boot_seed.o(.bss*)
*/dummy_device_id.o(.bss*)
*/tfm_spm_services.o(COMMON)
- */platform_retarget_dev.o(COMMON)
+ */device_definition.o(COMMON)
*/dummy_crypto_keys.o(COMMON)
*/dummy_nv_counters.o(COMMON)
*/dummy_boot_seed.o(COMMON)
diff --git a/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template
index 6ea61e0..47f3e12 100644
--- a/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template
+++ b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template
@@ -1,5 +1,5 @@
;/*
-; * Copyright (c) 2018-2019 Arm Limited
+; * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
; *
; * Licensed under the Apache License, Version 2.0 (the "License");
; * you may not use this file except in compliance with the License.
@@ -142,8 +142,8 @@
*dummy_boot_seed.o(.rodata*)
*dummy_device_id.o(.text*)
*dummy_device_id.o(.rodata*)
- *platform_retarget_dev.o(.text*)
- *platform_retarget_dev.o(.rodata*)
+ *device_definition.o(.text*)
+ *device_definition.o(.rodata*)
*(SFN)
*libgcc*:*(.text*)
*libgcc*:*(.rodata*)
@@ -279,7 +279,7 @@
*/dummy_nv_counters.o(.data*)
*/dummy_boot_seed.o(.data*)
*/dummy_device_id.o(.data*)
- */platform_retarget_dev.o(.data*)
+ */device_definition.o(.data*)
. = ALIGN(32);
} > RAM AT> FLASH
Image$$TFM_UNPRIV_RO_DATA$$RW$$Base = ADDR(.TFM_UNPRIV_RO_DATA);
@@ -288,13 +288,13 @@
.TFM_UNPRIV_RO_BSS : ALIGN(32)
{
*/tfm_spm_services.o(.bss*)
- */platform_retarget_dev.o(.bss*)
+ */device_definition.o(.bss*)
*/dummy_crypto_keys.o(.bss*)
*/dummy_nv_counters.o(.bss*)
*/dummy_boot_seed.o(.bss*)
*/dummy_device_id.o(.bss*)
*/tfm_spm_services.o(COMMON)
- */platform_retarget_dev.o(COMMON)
+ */device_definition.o(COMMON)
*/dummy_crypto_keys.o(COMMON)
*/dummy_nv_counters.o(COMMON)
*/dummy_boot_seed.o(COMMON)
diff --git a/platform/ext/target/musca_a/Device/Source/system_cmsdk_musca.c b/platform/ext/target/musca_a/Device/Source/system_core_init.c
similarity index 94%
rename from platform/ext/target/musca_a/Device/Source/system_cmsdk_musca.c
rename to platform/ext/target/musca_a/Device/Source/system_core_init.c
index 8d54569..517d6fe 100644
--- a/platform/ext/target/musca_a/Device/Source/system_cmsdk_musca.c
+++ b/platform/ext/target/musca_a/Device/Source/system_core_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2009-2018 Arm Limited
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -18,7 +18,9 @@
* Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
*/
-#include "system_cmsdk_musca.h"
+#include <stdint.h>
+#include "system_core_init.h"
+#include "platform_description.h"
/*----------------------------------------------------------------------------
Define clocks
diff --git a/platform/ext/target/musca_a/Native_Driver/mpc_sie200_drv.c b/platform/ext/target/musca_a/Native_Driver/mpc_sie200_drv.c
index fab3c60..00dfa86 100644
--- a/platform/ext/target/musca_a/Native_Driver/mpc_sie200_drv.c
+++ b/platform/ext/target/musca_a/Native_Driver/mpc_sie200_drv.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018 Arm Limited
+ * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -17,7 +17,7 @@
#include <stddef.h>
-#include "cmsis.h"
+#include "cmsis_compiler.h"
#define MPC_SIE200_BLK_CFG_OFFSET 5U
diff --git a/platform/ext/target/musca_a/Native_Driver/mpu_armv8m_drv.c b/platform/ext/target/musca_a/Native_Driver/mpu_armv8m_drv.c
index e540be2..e79b4d0 100644
--- a/platform/ext/target/musca_a/Native_Driver/mpu_armv8m_drv.c
+++ b/platform/ext/target/musca_a/Native_Driver/mpu_armv8m_drv.c
@@ -1,12 +1,12 @@
/*
- * Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#include "mpu_armv8m_drv.h"
-#include "cmsis_cpu.h"
+#include "cmsis.h"
/*
* FixMe:
diff --git a/platform/ext/target/musca_a/Native_Driver/mpu_armv8m_drv.h b/platform/ext/target/musca_a/Native_Driver/mpu_armv8m_drv.h
index 0abf7fd..d383568 100644
--- a/platform/ext/target/musca_a/Native_Driver/mpu_armv8m_drv.h
+++ b/platform/ext/target/musca_a/Native_Driver/mpu_armv8m_drv.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -10,7 +10,9 @@
#include <stdint.h>
-#include "cmsis.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
#define PRIVILEGED_DEFAULT_ENABLE 1
#define HARDFAULT_NMI_ENABLE 1
@@ -125,4 +127,8 @@
struct mpu_armv8m_dev_t *dev,
uint32_t region_nr);
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __MPU_ARMV8M_DRV_H__ */
diff --git a/platform/ext/target/musca_a/Native_Driver/ppc_sse200_drv.h b/platform/ext/target/musca_a/Native_Driver/ppc_sse200_drv.h
index 4071ee4..b6ce8c2 100644
--- a/platform/ext/target/musca_a/Native_Driver/ppc_sse200_drv.h
+++ b/platform/ext/target/musca_a/Native_Driver/ppc_sse200_drv.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018 Arm Limited
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -25,6 +25,10 @@
#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
/* Secure Privilege Control Block aka SPCTRL */
/* Non-Secure Privilege Control Block aka NSPCTRL */
@@ -187,4 +191,8 @@
*/
uint32_t ppc_sse200_irq_state(struct ppc_sse200_dev_t* dev);
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __PPC_SSE_200_DRV_H__ */
diff --git a/platform/ext/target/musca_a/partition/flash_layout.h b/platform/ext/target/musca_a/partition/flash_layout.h
index 3cceef6..8d3bc8f 100644
--- a/platform/ext/target/musca_a/partition/flash_layout.h
+++ b/platform/ext/target/musca_a/partition/flash_layout.h
@@ -41,9 +41,9 @@
/* This header file is included from linker scatter file as well, where only a
* limited C constructs are allowed. Therefore it is not possible to include
- * here the platform_retarget.h to access flash related defines. To resolve this
- * some of the values are redefined here with different names, these are marked
- * with comment.
+ * here the platform_base_address.h to access flash related defines. To resolve
+ * this some of the values are redefined here with different names, these are
+ * marked with comment.
*/
/* The size of a partition. This should be large enough to contain a S or NS
@@ -57,7 +57,9 @@
#define FLASH_TOTAL_SIZE (0x800000) /* 8MB */
/* Flash layout info for BL2 bootloader */
-#define FLASH_BASE_ADDRESS (0x10200000) /* same as FLASH0_BASE_S */
+#define FLASH_BASE_ADDRESS (0x10200000) /* same as
+ * MPC_QSPI_RANGE_BASE_S
+ */
/* Offset and size definitions of the flash partitions that are handled by the
* bootloader. The image swapping is done between IMAGE_0 and IMAGE_1, SCRATCH
diff --git a/platform/ext/target/musca_a/target_cfg.c b/platform/ext/target/musca_a/target_cfg.c
index fedcf12..b3d0300 100644
--- a/platform/ext/target/musca_a/target_cfg.c
+++ b/platform/ext/target/musca_a/target_cfg.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 Arm Limited
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -14,10 +14,10 @@
* limitations under the License.
*/
-#include "cmsis.h"
#include "target_cfg.h"
#include "Driver_MPC.h"
-#include "platform_retarget_dev.h"
+#include "platform_description.h"
+#include "device_definition.h"
#include "region_defs.h"
#include "tfm_secure_api.h"
diff --git a/platform/ext/target/musca_a/tfm_platform_system.c b/platform/ext/target/musca_a/tfm_platform_system.c
index 1e8a9ab..7cd0c84 100644
--- a/platform/ext/target/musca_a/tfm_platform_system.c
+++ b/platform/ext/target/musca_a/tfm_platform_system.c
@@ -1,12 +1,12 @@
/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#include "platform/include/tfm_platform_system.h"
-#include "cmsis.h"
+#include "platform_description.h"
void tfm_platform_hal_system_reset(void)
{