SPM: Unify exception priority setting code
The exception priority setting code is spread into multiple
places while there is no significant difference between them.
Unify them together into one architecture function.
Change-Id: Iac15aff32065394b44f5318c66fb331842ec3b34
Signed-off-by: Ken Liu <Ken.Liu@arm.com>
diff --git a/secure_fw/spm/include/tfm_arch.h b/secure_fw/spm/include/tfm_arch.h
index 74c0aba..988c575 100644
--- a/secure_fw/spm/include/tfm_arch.h
+++ b/secure_fw/spm/include/tfm_arch.h
@@ -46,33 +46,6 @@
SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
}
-#ifdef TFM_MULTI_CORE_TOPOLOGY
-__STATIC_INLINE void tfm_arch_set_pendsv_priority(void)
-{
- NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
-}
-#else
-__STATIC_INLINE void tfm_arch_set_pendsv_priority(void)
-{
- /*
- * Set secure PendSV priority to the lowest in SECURE state.
- *
- * IMPORTANT NOTE:
- *
- * Although the priority of the secure PendSV must be the lowest possible
- * among other interrupts in the Secure state, it must be ensured that
- * PendSV is not preempted nor masked by Non-Secure interrupts to ensure
- * the integrity of the Secure operation.
- * When AIRCR.PRIS is set, the Non-Secure execution can act on
- * FAULTMASK_NS, PRIMASK_NS or BASEPRI_NS register to boost its priority
- * number up to the value 0x80.
- * For this reason, set the priority of the PendSV interrupt to the next
- * priority level configurable on the platform, just below 0x80.
- */
- NVIC_SetPriority(PendSV_IRQn, (1 << (__NVIC_PRIO_BITS - 1)) - 1);
-}
-#endif /* TFM_MULTI_CORE_TOPOLOGY */
-
/**
* \brief Get Link Register
* \details Returns the value of the Link Register (LR)
@@ -114,14 +87,9 @@
uint32_t sp, uint32_t sp_limit);
/*
- * Prioritize Secure exceptions
+ * Set secure exceptions priority
*/
-void tfm_arch_prioritize_secure_exception(void);
-
-/*
- * Set the priority of fault exceptions
- */
-void tfm_arch_set_fault_priority(void);
+void tfm_arch_set_secure_exception_priorities(void);
/**
* \brief Configure coprocessors