FPU: Maintain the FPU test supported platforms
1. FPU interrupt protection tests need to set SCB.CCR.USERSETMPEND
as 1 to run on isolation level 2.
2. FPU interrupt protection tests known issues on Musca-s1 board
have not been fixed. It is not suggested to build and run FPU
test suites on Musca-S1 platform now.
3. Introduction about FPU supported platforms has been changed.
Signed-off-by: Jianliang Shen <jianliang.shen@arm.com>
Change-Id: Ie3185a0db7cc2ef7b0f7d4c0ecc22cc1eab0a7f9
diff --git a/docs/integration_guide/tfm_fpu_support.rst b/docs/integration_guide/tfm_fpu_support.rst
index 520146e..6ebf7ce 100644
--- a/docs/integration_guide/tfm_fpu_support.rst
+++ b/docs/integration_guide/tfm_fpu_support.rst
@@ -21,7 +21,7 @@
* Does not support use FPU in First-Level Interrupt Handling (FLIH) [6]_ at
current stage.
-Please refer to Arm musca S1 [7]_ platform as a reference implementation when
+Please refer to Arm AN521 or AN552 platform as a reference implementation when
you enable FP support on your platforms.
.. Note::
@@ -31,6 +31,11 @@
configurations described below.
.. Note::
+ FPU test issue has not been fixed yet on Musca-S1 [7]_. When running FPU
+ tests on Musca-S1, secure thread fails to trigger secure interrupt. FPU test
+ is disabled by default on Musca-S1 until the issue is fixed.
+
+.. Note::
``GNU Arm Embedded Toolchain 10.3-2021.10`` may have issue that reports
``'-mcpu=cortex-m55' conflicts with '-march=armv8.1-m.main'`` warning [8]_.
This issue has been fixed in the later version.