FPU: Maintain the FPU test supported platforms
1. FPU interrupt protection tests need to set SCB.CCR.USERSETMPEND
as 1 to run on isolation level 2.
2. FPU interrupt protection tests known issues on Musca-s1 board
have not been fixed. It is not suggested to build and run FPU
test suites on Musca-S1 platform now.
3. Introduction about FPU supported platforms has been changed.
Signed-off-by: Jianliang Shen <jianliang.shen@arm.com>
Change-Id: Ie3185a0db7cc2ef7b0f7d4c0ecc22cc1eab0a7f9
diff --git a/docs/integration_guide/tfm_fpu_support.rst b/docs/integration_guide/tfm_fpu_support.rst
index 520146e..6ebf7ce 100644
--- a/docs/integration_guide/tfm_fpu_support.rst
+++ b/docs/integration_guide/tfm_fpu_support.rst
@@ -21,7 +21,7 @@
* Does not support use FPU in First-Level Interrupt Handling (FLIH) [6]_ at
current stage.
-Please refer to Arm musca S1 [7]_ platform as a reference implementation when
+Please refer to Arm AN521 or AN552 platform as a reference implementation when
you enable FP support on your platforms.
.. Note::
@@ -31,6 +31,11 @@
configurations described below.
.. Note::
+ FPU test issue has not been fixed yet on Musca-S1 [7]_. When running FPU
+ tests on Musca-S1, secure thread fails to trigger secure interrupt. FPU test
+ is disabled by default on Musca-S1 until the issue is fixed.
+
+.. Note::
``GNU Arm Embedded Toolchain 10.3-2021.10`` may have issue that reports
``'-mcpu=cortex-m55' conflicts with '-march=armv8.1-m.main'`` warning [8]_.
This issue has been fixed in the later version.
diff --git a/platform/ext/target/arm/mps2/an521/tfm_hal_platform.c b/platform/ext/target/arm/mps2/an521/tfm_hal_platform.c
index 3e2eaf6..45a29ba 100644
--- a/platform/ext/target/arm/mps2/an521/tfm_hal_platform.c
+++ b/platform/ext/target/arm/mps2/an521/tfm_hal_platform.c
@@ -63,6 +63,13 @@
#if defined(TEST_NS_FPU)
/* Set IRQn in non-secure mode */
NVIC_SetTargetState(TFM_FPU_NS_TEST_IRQ);
+#if (TFM_LVL >= 2)
+ /* On isolation level 2, FPU test ARoT service runs in unprivileged mode.
+ * Set SCB.CCR.USERSETMPEND as 1 to enable FPU test service to access STIR
+ * register.
+ */
+ SCB->CCR |= SCB_CCR_USERSETMPEND_Msk;
+#endif
#endif
FIH_RET(fih_int_encode(TFM_HAL_SUCCESS));
diff --git a/platform/ext/target/arm/mps3/an552/tfm_hal_platform.c b/platform/ext/target/arm/mps3/an552/tfm_hal_platform.c
index 0eec442..ba5bacf 100644
--- a/platform/ext/target/arm/mps3/an552/tfm_hal_platform.c
+++ b/platform/ext/target/arm/mps3/an552/tfm_hal_platform.c
@@ -73,6 +73,13 @@
#if defined(TEST_NS_FPU)
/* Set IRQn in non-secure mode */
NVIC_SetTargetState(TFM_FPU_NS_TEST_IRQ);
+#if (TFM_LVL >= 2)
+ /* On isolation level 2, FPU test ARoT service runs in unprivileged mode.
+ * Set SCB.CCR.USERSETMPEND as 1 to enable FPU test service to access STIR
+ * register.
+ */
+ SCB->CCR |= SCB_CCR_USERSETMPEND_Msk;
+#endif
#endif
return TFM_HAL_SUCCESS;
diff --git a/platform/ext/target/arm/musca_s1/check_config.cmake b/platform/ext/target/arm/musca_s1/check_config.cmake
new file mode 100644
index 0000000..3e44a12
--- /dev/null
+++ b/platform/ext/target/arm/musca_s1/check_config.cmake
@@ -0,0 +1,10 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2022, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+if (TEST_S_FPU OR TEST_NS_FPU)
+ message(FATAL_ERROR "FPU tests are not supported on Musca-S1 platform.")
+endif()