Core: Initial implementation of sec IRQ handling
This commit makes possible for partitions to define IRQ handlers that
are executed in case of an interrupt is triggered, with the isolation
required by TFM_LVL settings.
Detailed changes:
- Add template files to generate code for configuring IRQs, and set
up IRQ handlers based on information provided in the partition's
manifest
- Add capability to Core to isolate the IRQ handlers
- Add documentation
Change-Id: I0e46b9a41fb4e20ca4c398acf5ce1d4027e8597f
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
diff --git a/platform/ext/target/mps2/an519/spm_hal.c b/platform/ext/target/mps2/an519/spm_hal.c
index e486e52..1c07116 100644
--- a/platform/ext/target/mps2/an519/spm_hal.c
+++ b/platform/ext/target/mps2/an519/spm_hal.c
@@ -6,6 +6,7 @@
*/
#include <stdio.h>
+#include "cmsis.h"
#include "platform/include/tfm_spm_hal.h"
#include "spm_api.h"
#include "spm_db.h"
@@ -398,3 +399,37 @@
uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS);
NVIC_SetPriority(irq_line, quantized_priority);
}
+
+void tfm_spm_hal_clear_pending_irq(int32_t irq_line)
+{
+ NVIC_ClearPendingIRQ(irq_line);
+}
+
+void tfm_spm_hal_enable_irq(int32_t irq_line)
+{
+ NVIC_EnableIRQ(irq_line);
+}
+
+void tfm_spm_hal_disable_irq(int32_t irq_line)
+{
+ NVIC_DisableIRQ(irq_line);
+}
+
+enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
+ int32_t irq_line,
+ enum irq_target_state_t target_state)
+{
+ uint32_t result;
+
+ if (target_state == TFM_IRQ_TARGET_STATE_SECURE) {
+ result = NVIC_ClearTargetState(irq_line);
+ } else {
+ result = NVIC_SetTargetState(irq_line);
+ }
+
+ if (result) {
+ return TFM_IRQ_TARGET_STATE_NON_SECURE;
+ } else {
+ return TFM_IRQ_TARGET_STATE_SECURE;
+ }
+}
diff --git a/platform/ext/target/mps2/an519/tfm_peripherals_def.h b/platform/ext/target/mps2/an519/tfm_peripherals_def.h
index 340a19c..b5f963c 100644
--- a/platform/ext/target/mps2/an519/tfm_peripherals_def.h
+++ b/platform/ext/target/mps2/an519/tfm_peripherals_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -8,6 +8,8 @@
#ifndef __TFM_PERIPHERALS_DEF_H__
#define __TFM_PERIPHERALS_DEF_H__
+#define TFM_TIMER0_IRQ (3)
+
struct tfm_spm_partition_platform_data_t;
extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart;
diff --git a/platform/ext/target/mps2/an521/spm_hal.c b/platform/ext/target/mps2/an521/spm_hal.c
index 193b2a3..bc91d41 100644
--- a/platform/ext/target/mps2/an521/spm_hal.c
+++ b/platform/ext/target/mps2/an521/spm_hal.c
@@ -6,6 +6,7 @@
*/
#include <stdio.h>
+#include "cmsis.h"
#include "platform/include/tfm_spm_hal.h"
#include "spm_api.h"
#include "spm_db.h"
@@ -398,3 +399,37 @@
uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS);
NVIC_SetPriority(irq_line, quantized_priority);
}
+
+void tfm_spm_hal_clear_pending_irq(int32_t irq_line)
+{
+ NVIC_ClearPendingIRQ(irq_line);
+}
+
+void tfm_spm_hal_enable_irq(int32_t irq_line)
+{
+ NVIC_EnableIRQ(irq_line);
+}
+
+void tfm_spm_hal_disable_irq(int32_t irq_line)
+{
+ NVIC_DisableIRQ(irq_line);
+}
+
+enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
+ int32_t irq_line,
+ enum irq_target_state_t target_state)
+{
+ uint32_t result;
+
+ if (target_state == TFM_IRQ_TARGET_STATE_SECURE) {
+ result = NVIC_ClearTargetState(irq_line);
+ } else {
+ result = NVIC_SetTargetState(irq_line);
+ }
+
+ if (result) {
+ return TFM_IRQ_TARGET_STATE_NON_SECURE;
+ } else {
+ return TFM_IRQ_TARGET_STATE_SECURE;
+ }
+}
diff --git a/platform/ext/target/mps2/an521/tfm_peripherals_def.h b/platform/ext/target/mps2/an521/tfm_peripherals_def.h
index 340a19c..b5f963c 100644
--- a/platform/ext/target/mps2/an521/tfm_peripherals_def.h
+++ b/platform/ext/target/mps2/an521/tfm_peripherals_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -8,6 +8,8 @@
#ifndef __TFM_PERIPHERALS_DEF_H__
#define __TFM_PERIPHERALS_DEF_H__
+#define TFM_TIMER0_IRQ (3)
+
struct tfm_spm_partition_platform_data_t;
extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart;
diff --git a/platform/ext/target/mps3/an524/spm_hal.c b/platform/ext/target/mps3/an524/spm_hal.c
index 0d1316d..361d332 100644
--- a/platform/ext/target/mps3/an524/spm_hal.c
+++ b/platform/ext/target/mps3/an524/spm_hal.c
@@ -6,6 +6,7 @@
*/
#include <stdio.h>
+#include "cmsis.h"
#include "tfm_spm_hal.h"
#include "tfm_platform_core_api.h"
#include "spm_db.h"
@@ -427,3 +428,37 @@
uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS);
NVIC_SetPriority(irq_line, quantized_priority);
}
+
+void tfm_spm_hal_clear_pending_irq(int32_t irq_line)
+{
+ NVIC_ClearPendingIRQ(irq_line);
+}
+
+void tfm_spm_hal_enable_irq(int32_t irq_line)
+{
+ NVIC_EnableIRQ(irq_line);
+}
+
+void tfm_spm_hal_disable_irq(int32_t irq_line)
+{
+ NVIC_DisableIRQ(irq_line);
+}
+
+enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
+ int32_t irq_line,
+ enum irq_target_state_t target_state)
+{
+ uint32_t result;
+
+ if (target_state == TFM_IRQ_TARGET_STATE_SECURE) {
+ result = NVIC_ClearTargetState(irq_line);
+ } else {
+ result = NVIC_SetTargetState(irq_line);
+ }
+
+ if (result) {
+ return TFM_IRQ_TARGET_STATE_NON_SECURE;
+ } else {
+ return TFM_IRQ_TARGET_STATE_SECURE;
+ }
+}
diff --git a/platform/ext/target/mps3/an524/tfm_peripherals_def.h b/platform/ext/target/mps3/an524/tfm_peripherals_def.h
index 7966756..e56cde2 100644
--- a/platform/ext/target/mps3/an524/tfm_peripherals_def.h
+++ b/platform/ext/target/mps3/an524/tfm_peripherals_def.h
@@ -12,6 +12,8 @@
extern "C" {
#endif
+#define TFM_TIMER0_IRQ (3)
+
struct tfm_spm_partition_platform_data_t;
extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart;
diff --git a/platform/ext/target/musca_a/spm_hal.c b/platform/ext/target/musca_a/spm_hal.c
index e658fc8..5637aaf 100644
--- a/platform/ext/target/musca_a/spm_hal.c
+++ b/platform/ext/target/musca_a/spm_hal.c
@@ -6,6 +6,7 @@
*/
#include <stdio.h>
+#include "cmsis.h"
#include "platform/include/tfm_spm_hal.h"
#include "spm_api.h"
#include "spm_db.h"
@@ -398,3 +399,37 @@
uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS);
NVIC_SetPriority(irq_line, quantized_priority);
}
+
+void tfm_spm_hal_clear_pending_irq(int32_t irq_line)
+{
+ NVIC_ClearPendingIRQ(irq_line);
+}
+
+void tfm_spm_hal_enable_irq(int32_t irq_line)
+{
+ NVIC_EnableIRQ(irq_line);
+}
+
+void tfm_spm_hal_disable_irq(int32_t irq_line)
+{
+ NVIC_DisableIRQ(irq_line);
+}
+
+enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
+ int32_t irq_line,
+ enum irq_target_state_t target_state)
+{
+ uint32_t result;
+
+ if (target_state == TFM_IRQ_TARGET_STATE_SECURE) {
+ result = NVIC_ClearTargetState(irq_line);
+ } else {
+ result = NVIC_SetTargetState(irq_line);
+ }
+
+ if (result) {
+ return TFM_IRQ_TARGET_STATE_NON_SECURE;
+ } else {
+ return TFM_IRQ_TARGET_STATE_SECURE;
+ }
+}
diff --git a/platform/ext/target/musca_a/tfm_peripherals_def.h b/platform/ext/target/musca_a/tfm_peripherals_def.h
index ab5f174..f47e756 100644
--- a/platform/ext/target/musca_a/tfm_peripherals_def.h
+++ b/platform/ext/target/musca_a/tfm_peripherals_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -8,6 +8,8 @@
#ifndef __TFM_PERIPHERALS_DEF_H__
#define __TFM_PERIPHERALS_DEF_H__
+#define TFM_TIMER0_IRQ (3)
+
struct tfm_spm_partition_platform_data_t;
extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart;
diff --git a/platform/ext/target/musca_b1/spm_hal.c b/platform/ext/target/musca_b1/spm_hal.c
index 1e350ca..84fc144 100644
--- a/platform/ext/target/musca_b1/spm_hal.c
+++ b/platform/ext/target/musca_b1/spm_hal.c
@@ -6,6 +6,7 @@
*/
#include <stdio.h>
+#include "cmsis.h"
#include "platform/include/tfm_spm_hal.h"
#include "spm_api.h"
#include "spm_db.h"
@@ -398,3 +399,37 @@
uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS);
NVIC_SetPriority(irq_line, quantized_priority);
}
+
+void tfm_spm_hal_clear_pending_irq(int32_t irq_line)
+{
+ NVIC_ClearPendingIRQ(irq_line);
+}
+
+void tfm_spm_hal_enable_irq(int32_t irq_line)
+{
+ NVIC_EnableIRQ(irq_line);
+}
+
+void tfm_spm_hal_disable_irq(int32_t irq_line)
+{
+ NVIC_DisableIRQ(irq_line);
+}
+
+enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
+ int32_t irq_line,
+ enum irq_target_state_t target_state)
+{
+ uint32_t result;
+
+ if (target_state == TFM_IRQ_TARGET_STATE_SECURE) {
+ result = NVIC_ClearTargetState(irq_line);
+ } else {
+ result = NVIC_SetTargetState(irq_line);
+ }
+
+ if (result) {
+ return TFM_IRQ_TARGET_STATE_NON_SECURE;
+ } else {
+ return TFM_IRQ_TARGET_STATE_SECURE;
+ }
+}
diff --git a/platform/ext/target/musca_b1/tfm_peripherals_def.h b/platform/ext/target/musca_b1/tfm_peripherals_def.h
index d9bcc1d..6663f8b 100644
--- a/platform/ext/target/musca_b1/tfm_peripherals_def.h
+++ b/platform/ext/target/musca_b1/tfm_peripherals_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -12,6 +12,8 @@
extern "C" {
#endif
+#define TFM_TIMER0_IRQ (3)
+
struct tfm_spm_partition_platform_data_t;
extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart;
diff --git a/platform/include/tfm_spm_hal.h b/platform/include/tfm_spm_hal.h
index 3458b17..cb54186 100644
--- a/platform/include/tfm_spm_hal.h
+++ b/platform/include/tfm_spm_hal.h
@@ -28,6 +28,11 @@
*/
struct tfm_spm_partition_platform_data_t;
+enum irq_target_state_t {
+ TFM_IRQ_TARGET_STATE_SECURE,
+ TFM_IRQ_TARGET_STATE_NON_SECURE,
+};
+
#if defined (TFM_PSA_API) || (TFM_LVL != 1)
/**
* \brief Holds SPM db fields that define the memory regions used by a
@@ -160,6 +165,42 @@
*/
void tfm_spm_hal_set_secure_irq_priority(int32_t irq_line, uint32_t priority);
+/**
+ * \brief Clears a pending IRQ
+ *
+ * \param[in] irq_line The IRQ to clear pending for.
+ */
+void tfm_spm_hal_clear_pending_irq(int32_t irq_line);
+
+/**
+ * \brief Enables an IRQ
+ *
+ * \param[in] irq_line The IRQ to be enabled.
+ */
+void tfm_spm_hal_enable_irq(int32_t irq_line);
+
+/**
+ * \brief Disables an IRQ
+ *
+ * \param[in] irq_line The IRQ to be disabled
+ */
+void tfm_spm_hal_disable_irq(int32_t irq_line);
+
+/**
+ * \brief Set the target state of an IRQ
+ *
+ * \param[in] irq_line The IRQ to set the priority for.
+ * \param[in] target_state Target state to ret for the IRQ.
+ *
+ * \return TFM_IRQ_TARGET_STATE_SECURE if interrupt is assigned
+ * to Secure
+ * TFM_IRQ_TARGET_STATE_NON_SECURE if interrupt is
+ * assigned to Non-Secure
+ */
+enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
+ int32_t irq_line,
+ enum irq_target_state_t target_state);
+
#if (TFM_LVL != 1) && !defined(TFM_PSA_API)
/**
* \brief Configure the sandbox for a partition.