Core: Explicitly set fault priorities
Change-Id: I49c825b56739e69f52c33d4b47036ada62455417
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
diff --git a/platform/ext/target/mps2/an519/target_cfg.c b/platform/ext/target/mps2/an519/target_cfg.c
index 0327ff0..4e44047 100644
--- a/platform/ext/target/mps2/an519/target_cfg.c
+++ b/platform/ext/target/mps2/an519/target_cfg.c
@@ -116,8 +116,9 @@
void enable_fault_handlers(void)
{
- /* Fault handles enable registers are not present in a baseline
- * implementation
+ /* Secure fault is not present in the Baseline implementation. */
+ /* Fault handler enable registers are not present in a Baseline
+ * implementation.
*/
}
diff --git a/platform/ext/target/mps2/an521/target_cfg.c b/platform/ext/target/mps2/an521/target_cfg.c
index 492187c..97191a5 100644
--- a/platform/ext/target/mps2/an521/target_cfg.c
+++ b/platform/ext/target/mps2/an521/target_cfg.c
@@ -116,6 +116,9 @@
void enable_fault_handlers(void)
{
+ /* Explicitly set secure fault priority to the highest */
+ NVIC_SetPriority(SecureFault_IRQn, 0);
+
/* Enables BUS, MEM, USG and Secure faults */
SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk
| SCB_SHCSR_BUSFAULTENA_Msk
diff --git a/platform/ext/target/musca_a/target_cfg.c b/platform/ext/target/musca_a/target_cfg.c
index 0cc31b9..f025b8b 100644
--- a/platform/ext/target/musca_a/target_cfg.c
+++ b/platform/ext/target/musca_a/target_cfg.c
@@ -93,6 +93,9 @@
void enable_fault_handlers(void)
{
+ /* Explicitly set secure fault priority to the highest */
+ NVIC_SetPriority(SecureFault_IRQn, 0);
+
/* Enables BUS, MEM, USG and Secure faults */
SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk
| SCB_SHCSR_BUSFAULTENA_Msk
diff --git a/platform/ext/target/musca_b1/target_cfg.c b/platform/ext/target/musca_b1/target_cfg.c
index 7175de2..7a4c15a 100644
--- a/platform/ext/target/musca_b1/target_cfg.c
+++ b/platform/ext/target/musca_b1/target_cfg.c
@@ -128,6 +128,9 @@
void enable_fault_handlers(void)
{
+ /* Explicitly set secure fault priority to the highest */
+ NVIC_SetPriority(SecureFault_IRQn, 0);
+
/* Enables BUS, MEM, USG and Secure faults */
SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk
| SCB_SHCSR_BUSFAULTENA_Msk
diff --git a/platform/include/tfm_spm_hal.h b/platform/include/tfm_spm_hal.h
index 3ce0b29..b8e654b 100644
--- a/platform/include/tfm_spm_hal.h
+++ b/platform/include/tfm_spm_hal.h
@@ -101,7 +101,9 @@
void tfm_spm_hal_init_debug(void);
/**
- * \brief Enables the fault handlers
+ * \brief Enables the fault handlers and sets priorities.
+ *
+ * Secure fault (if present) must have the highest possible priority
*/
void enable_fault_handlers(void);
diff --git a/secure_fw/core/tfm_core.c b/secure_fw/core/tfm_core.c
index dd65cd5..eb72be3 100644
--- a/secure_fw/core/tfm_core.c
+++ b/secure_fw/core/tfm_core.c
@@ -140,7 +140,8 @@
VECTKEY |
(AIRCR & ~SCB_AIRCR_VECTKEY_Msk);
- /* FixMe: Explicitly set secure fault and Secure SVC priority to highest */
+ /* Explicitly set Secure SVC priority to highest */
+ tfm_spm_hal_set_secure_irq_priority(SVCall_IRQn, 0);
/*
* Set secure PendSV priority to the lowest in SECURE state.