Platform: drivers and external components
This includes all the platform drivers required by Trusted Firmware M.
The 'ext' directory contains code for target support which has been
brought in from other project.
Change-Id: Iaf4659e1d9b2ad4c662a2e5566571657042b5f2e
Signed-off-by: Abhishek Pandit <abhishek.pandit@arm.com>
diff --git a/platform/ext/cmsis/cmsis_armclang.h b/platform/ext/cmsis/cmsis_armclang.h
new file mode 100644
index 0000000..c024ff0
--- /dev/null
+++ b/platform/ext/cmsis/cmsis_armclang.h
@@ -0,0 +1,1796 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file
+ * @version V5.0.3
+ * @date 27. March 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+//lint -esym(9058, IRQn) disable MISRA 2012 Rule 2.4 for IRQn
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h> /* Compatibility header for ARM Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+//lint -esym(9058, T_UINT32) disable MISRA 2012 Rule 2.4 for T_UINT32
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+//lint -esym(9058, T_UINT16_WRITE) disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+//lint -esym(9058, T_UINT16_READ) disable MISRA 2012 Rule 2.4 for T_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+//lint -esym(9058, T_UINT32_WRITE) disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+//lint -esym(9058, T_UINT32_READ) disable MISRA 2012 Rule 2.4 for T_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+ return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+/* #define __get_FPSCR __builtin_arm_get_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+/* #define __set_FPSCR __builtin_arm_set_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
+#else
+ (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF);
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF);
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF);
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __builtin_bswap32
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+ /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+ /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/platform/ext/cmsis/cmsis_compiler.h b/platform/ext/cmsis/cmsis_compiler.h
new file mode 100644
index 0000000..5a828c3
--- /dev/null
+++ b/platform/ext/cmsis/cmsis_compiler.h
@@ -0,0 +1,325 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.0.2
+ * @date 13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * ARM Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * ARM Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+
+ #include <cmsis_iar.h>
+
+ /* CMSIS compiler control architecture macros */
+ #if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
+ #ifndef __ARM_ARCH_6M__
+ #define __ARM_ARCH_6M__ 1
+ #endif
+ #elif (__CORE__ == __ARM7M__)
+ #ifndef __ARM_ARCH_7M__
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #elif (__CORE__ == __ARM7EM__)
+ #ifndef __ARM_ARCH_7EM__
+ #define __ARM_ARCH_7EM__ 1
+ #endif
+ #endif
+
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __noreturn
+ #endif
+ #ifndef __USED
+ #define __USED __root
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ __packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+
+ // Workaround for missing __CLZ intrinsic in
+ // various versions of the IAR compilers.
+ // __IAR_FEATURE_CLZ__ should be defined by
+ // the compiler that supports __CLZ internally.
+ #if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__))
+ __STATIC_INLINE uint32_t __CLZ(uint32_t data)
+ {
+ if (data == 0u) { return 32u; }
+
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while ((data & mask) == 0)
+ {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return (count);
+ }
+ #endif
+
+
+/*
+ * TI ARM Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include <cmsis_ccs.h>
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/platform/ext/cmsis/cmsis_version.h b/platform/ext/cmsis/cmsis_version.h
new file mode 100644
index 0000000..d458a6c
--- /dev/null
+++ b/platform/ext/cmsis/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.2
+ * @date 19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/platform/ext/cmsis/core_cm33.h b/platform/ext/cmsis/core_cm33.h
new file mode 100644
index 0000000..bcaff95
--- /dev/null
+++ b/platform/ext/cmsis/core_cm33.h
@@ -0,0 +1,2898 @@
+/**************************************************************************//**
+ * @file core_cm33.h
+ * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version V5.0.2
+ * @date 19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M33
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (33U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM33_REV
+ #define __CM33_REV 0x0000U
+ #warning "__CM33_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/platform/ext/driver/Driver_Common.h b/platform/ext/driver/Driver_Common.h
new file mode 100644
index 0000000..cdf44b3
--- /dev/null
+++ b/platform/ext/driver/Driver_Common.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date: 2. Jan 2014
+ * $Revision: V2.00
+ *
+ * Project: Common Driver definitions
+ */
+
+/* History:
+ * Version 2.00
+ * Changed prefix ARM_DRV -> ARM_DRIVER
+ * Added General return codes definitions
+ * Version 1.10
+ * Namespace prefix ARM_ added
+ * Version 1.00
+ * Initial release
+ */
+
+#ifndef __DRIVER_COMMON_H
+#define __DRIVER_COMMON_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
+
+/**
+\brief Driver Version
+*/
+typedef struct _ARM_DRIVER_VERSION {
+ uint16_t api; ///< API version
+ uint16_t drv; ///< Driver version
+} ARM_DRIVER_VERSION;
+
+/* General return codes */
+#define ARM_DRIVER_OK 0 ///< Operation succeeded
+#define ARM_DRIVER_ERROR -1 ///< Unspecified error
+#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy
+#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred
+#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported
+#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error
+#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors
+
+/**
+\brief General power states
+*/
+typedef enum _ARM_POWER_STATE {
+ ARM_POWER_OFF, ///< Power off: no operation possible
+ ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events
+ ARM_POWER_FULL ///< Power on: full operation at maximum performance
+} ARM_POWER_STATE;
+
+#endif /* __DRIVER_COMMON_H */
diff --git a/platform/ext/driver/Driver_MPC.h b/platform/ext/driver/Driver_MPC.h
new file mode 100644
index 0000000..c4fe825
--- /dev/null
+++ b/platform/ext/driver/Driver_MPC.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __DRIVER_MPC_H
+#define __DRIVER_MPC_H
+
+#include "Driver_Common.h"
+
+/* API version */
+#define ARM_MPC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)
+
+/* Error code returned by the driver functions */
+#define ARM_MPC_ERR_NOT_INIT (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< MPC not initialized */
+#define ARM_MPC_ERR_NOT_IN_RANGE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Address does not belong to a range controlled by the MPC */
+#define ARM_MPC_ERR_NOT_ALIGNED (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Address is not aligned on the block size of this MPC */
+#define ARM_MPC_ERR_INVALID_RANGE (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< The given address range to configure is invalid
+#define ARM_MPC_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< The given range cannot be accessed with the wanted security attributes */
+
+/* Security attribute used in various place of the API */
+typedef enum _ARM_MPC_SEC_ATTR {
+ ARM_MPC_ATTR_SECURE, ///< Secure attribute
+ ARM_MPC_ATTR_NONSECURE, ///< Non-secure attribute
+ /* Used when getting the configuration of a memory range and some blocks are
+ * secure whereas some other are non secure */
+ ARM_MPC_ATTR_MIXED, ///< Mixed attribute
+} ARM_MPC_SEC_ATTR;
+
+/* Function documentation */
+/**
+ \fn ARM_DRIVER_VERSION ARM_MPC_GetVersion (void)
+ \brief Get driver version.
+ \return \ref ARM_DRIVER_VERSION
+
+ \fn int32_t ARM_MPC_Initialize (void)
+ \brief Initialize MPC Interface.
+ \return Returns error code.
+
+ \fn int32_t ARM_MPC_Uninitialize (void)
+ \brief De-initialize MPC Interface. The controlled memory region
+ should not be accessed after a call to this function, as
+ it is allowed to configure everything to be secure (to
+ prevent information leak for example).
+ \return Returns error code.
+
+ \fn int32_t ARM_MPC_GetBlockSize (uint32_t* blk_size)
+ \brief Get the block size of the MPC. All regions must be aligned
+ on this block size (base address and limit+1 address).
+ \param[out] blk_size: The block size in bytes.
+ \return Returns error code.
+
+ \fn int32_t ARM_MPC_GetCtrlConfig (uint32_t* ctrl_val)
+ \brief Get some information on how the MPC IP is configured.
+ \param[out] ctrl_val: MPC control configuration
+ \return Returns error code.
+
+ \fn int32_t ARM_MPC_SetCtrlConfig (uint32_t ctrl)
+ \brief Set new control configuration for the MPC IP.
+ \param[in] ctrl: New control configuration.
+ \return Returns error code.
+
+ \fn int32_t ARM_MPC_ConfigRegion (uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+ \brief Configure a memory region (base and limit included).
+ Both base and limit addresses must belong to the same
+ memory range, and this range must be managed by this MPC.
+ Also, some ranges are only allowed to be configured as
+ secure/non-secure, because of hardware requirements
+ (security aliases), and only a relevant security attribute
+ is therefore allowed for such ranges.
+ \param[in] base: Base address of the region to configure. This
+ bound is included in the configured region.
+ This must be aligned on the block size of this MPC.
+ \param[in] limit: Limit address of the region to configure. This
+ bound is included in the configured region.
+ Limit+1 must be aligned on the block size of this MPC.
+ \param[in] attr: Wanted security attribute of the region.
+ \return Returns error code.
+
+ \fn int32_t ARM_MPC_GetRegionConfig (uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR *attr)
+ \brief Gets a memory region (base and limit included).
+ \param[in] base: Base address of the region to poll. This
+ bound is included. It does not need to be aligned
+ in any way.
+ \param[in] limit: Limit address of the region to poll. This
+ bound is included. (limit+1) does not need to be aligned
+ in any way.
+ \param[out] attr: Security attribute of the region.
+ If the region has mixed secure/non-secure,
+ a special value is returned (\ref ARM_MPC_SEC_ATTR).
+
+ In case base and limit+1 addresses are not aligned on
+ the block size, the enclosing region with base and
+ limit+1 aligned on block size will be queried.
+ In case of early termination of the function (error), the
+ security attribute will be set to ARM_MPC_ATTR_MIXED.
+ \return Returns error code.
+
+ \fn int32_t ARM_MPC_EnableInterrupt (void)
+ \brief Enable MPC interrupt.
+ \return Returns error code.
+
+ \fn void ARM_MPC_DisableInterrupt (void)
+ \brief Disable MPC interrupt.
+
+ \fn void ARM_MPC_ClearInterrupt (void)
+ \brief Clear MPC interrupt.
+
+ \fn uint32_t ARM_MPC_InterruptState (void)
+ \brief MPC interrupt state.
+ \return Returns 1 if the interrupt is active, 0 otherwise.
+
+ \fn int32_t ARM_MPC_LockDown (void)
+ \brief Lock down the MPC configuration.
+ \return Returns error code.
+*/
+
+/**
+ * \brief Access structure of the MPC Driver.
+ */
+typedef struct _ARM_DRIVER_MPC {
+ ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_MPC_GetVersion : Get driver version.
+ int32_t (*Initialize) (void); ///< Pointer to \ref ARM_MPC_Initialize : Initialize the MPC Interface.
+ int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_MPC_Uninitialize : De-initialize the MPC Interface.
+ int32_t (*GetBlockSize) (uint32_t* blk_size); ///< Pointer to \ref ARM_MPC_GetBlockSize : Get MPC block size
+ int32_t (*GetCtrlConfig) (uint32_t* ctrl_val); ///< Pointer to \ref ARM_MPC_GetCtrlConfig : Get the MPC control configuration flags.
+ int32_t (*SetCtrlConfig) (uint32_t ctrl); ///< Pointer to \ref ARM_MPC_SetCtrlConfig : Set the MPC control configuration flags.
+ int32_t (*ConfigRegion) (uintptr_t base, uintptr_t limit, ARM_MPC_SEC_ATTR attr); ///< Pointer to \ref ARM_MPC_ConfigRegion : Configure a region using the driver for the specific MPC.
+ int32_t (*GetRegionConfig) (uintptr_t base, uintptr_t limit, ARM_MPC_SEC_ATTR *attr); ///< Pointer to \ref ARM_MPC_GetRegionConfig : Get the configuration of a specific region on this MPC.
+ int32_t (*EnableInterrupt) (void); ///< Pointer to \ref ARM_MPC_EnableInterrupt : Enable MPC interrupt.
+ void (*DisableInterrupt) (void); ///< Pointer to \ref ARM_MPC_DisableInterrupt : Disable MPC interrupt.
+ void (*ClearInterrupt) (void); ///< Pointer to \ref ARM_MPC_ClearInterrupt : Clear MPC interrupt.
+ uint32_t (*InterruptState) (void); ///< Pointer to \ref ARM_MPC_InterruptState : MPC interrupt State.
+ int32_t (*LockDown) (void); ///< Pointer to \ref ARM_MPC_LockDown : Lock down the MPC configuration.
+} const ARM_DRIVER_MPC;
+
+#endif /* __DRIVER_MPC_H */
+
diff --git a/platform/ext/driver/Driver_PPC.h b/platform/ext/driver/Driver_PPC.h
new file mode 100644
index 0000000..e689b2e
--- /dev/null
+++ b/platform/ext/driver/Driver_PPC.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_PPC_DRV_H__
+#define __CMSIS_PPC_DRV_H__
+
+#include "Driver_Common.h"
+
+/* API version */
+#define ARM_PPC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)
+
+/* Security attribute used to configure the peripheral */
+typedef enum _ARM_PPC_SecAttr {
+ ARM_PPC_SECURE_ONLY, ///< Secure access
+ ARM_PPC_NONSECURE_ONLY, ///< Non-secure access
+} ARM_PPC_SecAttr;
+
+/* Privilege attribute used to configure the peripheral */
+typedef enum _ARM_PPC_PrivAttr {
+ ARM_PPC_PRIV_AND_NONPRIV, ///< Privilege and non-privilege access
+ ARM_PPC_PRIV_ONLY, ///< Privilege only access
+} ARM_PPC_PrivAttr;
+
+/* Function documentation */
+/**
+ \fn ARM_DRIVER_VERSION ARM_PPC_GetVersion (void)
+ \brief Get driver version.
+ \return \ref ARM_DRIVER_VERSION
+
+ \fn int32_t ARM_PPC_Initialize (void)
+ \brief Initialize PPC Interface.
+ \return Returns ARM error code.
+
+ \fn int32_t ARM_PPC_Uninitialize (void)
+ \brief De-initialize MPC Interface.
+ \return Returns ARM error code.
+
+ \fn int32_t ARM_PPC_ConfigPeriph (uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+ \brief Configures a peripheral controlled by the given PPC.
+ \param[in] periph: Peripheral position in SPCTRL and NSPCTRL registers.
+ \param[in] sec_attr: Secure attribute value.
+ \param[in] priv_attr: Privilege attrivute value.
+
+ Secure Privilege Control Block ( SPCTRL )
+ Non-Secure Privilege Control Block ( NSPCTRL )
+
+ \return Returns ARM error code.
+
+ \fn int32_t ARM_PPC_IsPeriphSecure (uint8_t periph)
+ \brief Check if the peripheral is configured to be secure.
+ \param[in] periph: Peripheral position in SPCTRL and NSPCTRL registers.
+
+ Secure Privilege Control Block ( SPCTRL )
+ Non-Secure Privilege Control Block ( NSPCTRL )
+
+ \return Returns 1 if the peripheral is configured as secure,
+ 0 for non-secure.
+
+ \fn uint32_t ARM_PPC_IsPeriphPrivOnly (uint8_t periph)
+ \brief Check if the peripheral is configured to be privilege only.
+ \param[in] periph: Peripheral position in SPCTRL and NSPCTRL registers.
+
+ Secure Privilege Control Block ( SPCTRL )
+ Non-Secure Privilege Control Block ( NSPCTRL )
+
+ \return Returns 1 if the peripheral is configured as privilege access
+ only, 0 for privilege and unprivilege access mode.
+
+ \fn int32_t ARM_PPC_EnableInterrupt (void)
+ \brief Enable PPC interrupt.
+ \return Returns ARM error code.
+
+ \fn void ARM_PPC_DisableInterrupt (void)
+ \brief Disable PPC interrupt.
+
+ \fn void ARM_PPC_ClearInterrupt (void)
+ \brief Clear PPC interrupt.
+
+ \fn int32_t ARM_PPC_InterruptState (void)
+ \brief PPC interrupt state.
+ \return Returns 1 if the interrupt is active, 0 otherwise.
+*/
+
+/**
+ * \brief Access structure of the MPC Driver.
+ */
+typedef struct _ARM_DRIVER_PPC {
+ ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_PPC_GetVersion : Get driver version.
+ int32_t (*Initialize) (void); ///< Pointer to \ref ARM_PPC_Initialize : Initialize the PPC Interface.
+ int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_PPC_Uninitialize : De-initialize the PPC Interface.
+ int32_t (*ConfigPeriph) (uint8_t periph, ARM_PPC_SecAttr sec_attr, ARM_PPC_PrivAttr priv_attr); ///< Pointer to \ref ARM_PPC_ConfigPeriph : Configure a peripheral controlled by the PPC.
+ uint32_t (*IsPeriphSecure) (uint8_t periph); ///< Pointer to \ref IsPeriphSecure : Check if the peripheral is configured to be secure.
+ uint32_t (*IsPeriphPrivOnly) (uint8_t periph); ///< Pointer to \ref IsPeriphPrivOnly : Check if the peripheral is configured to be privilege only.
+ int32_t (*EnableInterrupt) (void); ///< Pointer to \ref ARM_PPC_EnableInterrupt : Enable PPC interrupt.
+ void (*DisableInterrupt) (void); ///< Pointer to \ref ARM_PPC_DisableInterrupt : Disable PPC interrupt.
+ void (*ClearInterrupt) (void); ///< Pointer to \ref ARM_PPC_ClearInterrupt : Clear PPC interrupt.
+ uint32_t (*InterruptState) (void); ///< Pointer to \ref ARM_PPC_InterruptState : PPC interrupt State.
+} const ARM_DRIVER_PPC;
+
+#endif /* __CMSIS_PPC_DRV_H__ */
+
diff --git a/platform/ext/driver/Driver_USART.h b/platform/ext/driver/Driver_USART.h
new file mode 100644
index 0000000..237496b
--- /dev/null
+++ b/platform/ext/driver/Driver_USART.h
@@ -0,0 +1,341 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date: 2. Feb 2017
+ * $Revision: V2.3
+ *
+ * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter)
+ * Driver definitions
+ */
+
+/* History:
+ * Version 2.3
+ * ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile
+ * Version 2.2
+ * Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions
+ * Version 2.1
+ * Removed optional argument parameter from Signal Event
+ * Version 2.0
+ * New simplified driver:
+ * complexity moved to upper layer (especially data handling)
+ * more unified API for different communication interfaces
+ * renamed driver UART -> USART (Asynchronous & Synchronous)
+ * Added modes:
+ * Synchronous
+ * Single-wire
+ * IrDA
+ * Smart Card
+ * Changed prefix ARM_DRV -> ARM_DRIVER
+ * Version 1.10
+ * Namespace prefix ARM_ added
+ * Version 1.01
+ * Added events:
+ * ARM_UART_EVENT_TX_EMPTY, ARM_UART_EVENT_RX_TIMEOUT
+ * ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD
+ * Added functions: SetTxThreshold, SetRxThreshold
+ * Added "rx_timeout_event" to capabilities
+ * Version 1.00
+ * Initial release
+ */
+
+#ifndef DRIVER_USART_H_
+#define DRIVER_USART_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */
+
+
+/****** USART Control Codes *****/
+
+#define ARM_USART_CONTROL_Pos 0
+#define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos)
+
+/*----- USART Control Codes: Mode -----*/
+#define ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) ///< UART (Asynchronous); arg = Baudrate
+#define ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) ///< Synchronous Master (generates clock signal); arg = Baudrate
+#define ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) ///< Synchronous Slave (external clock signal)
+#define ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) ///< UART Single-wire (half-duplex); arg = Baudrate
+#define ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) ///< UART IrDA; arg = Baudrate
+#define ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) ///< UART Smart Card; arg = Baudrate
+
+/*----- USART Control Codes: Mode Parameters: Data Bits -----*/
+#define ARM_USART_DATA_BITS_Pos 8
+#define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos)
+#define ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) ///< 5 Data bits
+#define ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) ///< 6 Data bit
+#define ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) ///< 7 Data bits
+#define ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) ///< 8 Data bits (default)
+#define ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) ///< 9 Data bits
+
+/*----- USART Control Codes: Mode Parameters: Parity -----*/
+#define ARM_USART_PARITY_Pos 12
+#define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos)
+#define ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) ///< No Parity (default)
+#define ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) ///< Even Parity
+#define ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) ///< Odd Parity
+
+/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/
+#define ARM_USART_STOP_BITS_Pos 14
+#define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos)
+#define ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) ///< 1 Stop bit (default)
+#define ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) ///< 2 Stop bits
+#define ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) ///< 1.5 Stop bits
+#define ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) ///< 0.5 Stop bits
+
+/*----- USART Control Codes: Mode Parameters: Flow Control -----*/
+#define ARM_USART_FLOW_CONTROL_Pos 16
+#define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos)
+#define ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default)
+#define ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control
+#define ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control
+#define ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control
+
+/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/
+#define ARM_USART_CPOL_Pos 18
+#define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos)
+#define ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) ///< CPOL = 0 (default)
+#define ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) ///< CPOL = 1
+
+/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/
+#define ARM_USART_CPHA_Pos 19
+#define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos)
+#define ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) ///< CPHA = 0 (default)
+#define ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) ///< CPHA = 1
+
+
+/*----- USART Control Codes: Miscellaneous Controls -----*/
+#define ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) ///< Set default Transmit value (Synchronous Receive only); arg = value
+#define ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period
+#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Guard Time; arg = number of bit periods
+#define ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated
+#define ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) ///< Transmitter; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) ///< Receiver; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) ///< Continuous Break transmission; arg: 0=disabled, 1=enabled
+#define ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Send
+#define ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Receive
+#define ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Transfer
+
+
+
+/****** USART specific error codes *****/
+#define ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported
+#define ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified baudrate not supported
+#define ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported
+#define ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Parity not supported
+#define ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified number of Stop bits not supported
+#define ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Flow Control not supported
+#define ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock Polarity not supported
+#define ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Clock Phase not supported
+
+
+/**
+\brief USART Status
+*/
+typedef volatile struct _ARM_USART_STATUS {
+ uint32_t tx_busy : 1; ///< Transmitter busy flag
+ uint32_t rx_busy : 1; ///< Receiver busy flag
+ uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation)
+ uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation)
+ uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation)
+ uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation)
+ uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation)
+ uint32_t reserved : 25;
+} ARM_USART_STATUS;
+
+/**
+\brief USART Modem Control
+*/
+typedef enum _ARM_USART_MODEM_CONTROL {
+ ARM_USART_RTS_CLEAR, ///< Deactivate RTS
+ ARM_USART_RTS_SET, ///< Activate RTS
+ ARM_USART_DTR_CLEAR, ///< Deactivate DTR
+ ARM_USART_DTR_SET ///< Activate DTR
+} ARM_USART_MODEM_CONTROL;
+
+/**
+\brief USART Modem Status
+*/
+typedef volatile struct _ARM_USART_MODEM_STATUS {
+ uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive
+ uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive
+ uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive
+ uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive
+ uint32_t reserved : 28;
+} ARM_USART_MODEM_STATUS;
+
+
+/****** USART Event *****/
+#define ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed; however USART may still transmit data
+#define ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed
+#define ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) ///< Transfer completed
+#define ARM_USART_EVENT_TX_COMPLETE (1UL << 3) ///< Transmit completed (optional)
+#define ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) ///< Transmit data not available (Synchronous Slave)
+#define ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) ///< Receive data overflow
+#define ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) ///< Receive character timeout (optional)
+#define ARM_USART_EVENT_RX_BREAK (1UL << 7) ///< Break detected on receive
+#define ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) ///< Framing error detected on receive
+#define ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) ///< Parity error detected on receive
+#define ARM_USART_EVENT_CTS (1UL << 10) ///< CTS state changed (optional)
+#define ARM_USART_EVENT_DSR (1UL << 11) ///< DSR state changed (optional)
+#define ARM_USART_EVENT_DCD (1UL << 12) ///< DCD state changed (optional)
+#define ARM_USART_EVENT_RI (1UL << 13) ///< RI state changed (optional)
+
+
+// Function documentation
+/**
+ \fn ARM_DRIVER_VERSION ARM_USART_GetVersion (void)
+ \brief Get driver version.
+ \return \ref ARM_DRIVER_VERSION
+
+ \fn ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void)
+ \brief Get driver capabilities
+ \return \ref ARM_USART_CAPABILITIES
+
+ \fn int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event)
+ \brief Initialize USART Interface.
+ \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent
+ \return \ref execution_status
+
+ \fn int32_t ARM_USART_Uninitialize (void)
+ \brief De-initialize USART Interface.
+ \return \ref execution_status
+
+ \fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state)
+ \brief Control USART Interface Power.
+ \param[in] state Power state
+ \return \ref execution_status
+
+ \fn int32_t ARM_USART_Send (const void *data, uint32_t num)
+ \brief Start sending data to USART transmitter.
+ \param[in] data Pointer to buffer with data to send to USART transmitter
+ \param[in] num Number of data items to send
+ \return \ref execution_status
+
+ \fn int32_t ARM_USART_Receive (void *data, uint32_t num)
+ \brief Start receiving data from USART receiver.
+ \param[out] data Pointer to buffer for data to receive from USART receiver
+ \param[in] num Number of data items to receive
+ \return \ref execution_status
+
+ \fn int32_t ARM_USART_Transfer (const void *data_out,
+ void *data_in,
+ uint32_t num)
+ \brief Start sending/receiving data to/from USART transmitter/receiver.
+ \param[in] data_out Pointer to buffer with data to send to USART transmitter
+ \param[out] data_in Pointer to buffer for data to receive from USART receiver
+ \param[in] num Number of data items to transfer
+ \return \ref execution_status
+
+ \fn uint32_t ARM_USART_GetTxCount (void)
+ \brief Get transmitted data count.
+ \return number of data items transmitted
+
+ \fn uint32_t ARM_USART_GetRxCount (void)
+ \brief Get received data count.
+ \return number of data items received
+
+ \fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg)
+ \brief Control USART Interface.
+ \param[in] control Operation
+ \param[in] arg Argument of operation (optional)
+ \return common \ref execution_status and driver specific \ref usart_execution_status
+
+ \fn ARM_USART_STATUS ARM_USART_GetStatus (void)
+ \brief Get USART status.
+ \return USART status \ref ARM_USART_STATUS
+
+ \fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control)
+ \brief Set USART Modem Control line state.
+ \param[in] control \ref ARM_USART_MODEM_CONTROL
+ \return \ref execution_status
+
+ \fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void)
+ \brief Get USART Modem Status lines state.
+ \return modem status \ref ARM_USART_MODEM_STATUS
+
+ \fn void ARM_USART_SignalEvent (uint32_t event)
+ \brief Signal USART Events.
+ \param[in] event \ref USART_events notification mask
+ \return none
+*/
+
+typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event.
+
+
+/**
+\brief USART Device Driver Capabilities.
+*/
+typedef struct _ARM_USART_CAPABILITIES {
+ uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode
+ uint32_t synchronous_master : 1; ///< supports Synchronous Master mode
+ uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode
+ uint32_t single_wire : 1; ///< supports UART Single-wire mode
+ uint32_t irda : 1; ///< supports UART IrDA mode
+ uint32_t smart_card : 1; ///< supports UART Smart Card mode
+ uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available
+ uint32_t flow_control_rts : 1; ///< RTS Flow Control available
+ uint32_t flow_control_cts : 1; ///< CTS Flow Control available
+ uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE
+ uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
+ uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available
+ uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available
+ uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available
+ uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available
+ uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available
+ uint32_t ri : 1; ///< RI Line: 0=not available, 1=available
+ uint32_t event_cts : 1; ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS
+ uint32_t event_dsr : 1; ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR
+ uint32_t event_dcd : 1; ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD
+ uint32_t event_ri : 1; ///< Signal RI change event: \ref ARM_USART_EVENT_RI
+ uint32_t reserved : 11; ///< Reserved (must be zero)
+} ARM_USART_CAPABILITIES;
+
+
+/**
+\brief Access structure of the USART Driver.
+*/
+typedef struct _ARM_DRIVER_USART {
+ ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USART_GetVersion : Get driver version.
+ ARM_USART_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities.
+ int32_t (*Initialize) (ARM_USART_SignalEvent_t cb_event); ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface.
+ int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface.
+ int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power.
+ int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter.
+ int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver.
+ int32_t (*Transfer) (const void *data_out,
+ void *data_in,
+ uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART.
+ uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count.
+ uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count.
+ int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_USART_Control : Control USART Interface.
+ ARM_USART_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_USART_GetStatus : Get USART status.
+ int32_t (*SetModemControl) (ARM_USART_MODEM_CONTROL control); ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state.
+ ARM_USART_MODEM_STATUS (*GetModemStatus) (void); ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state.
+} const ARM_DRIVER_USART;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DRIVER_USART_H_ */
diff --git a/platform/ext/target/common/mbedtls_config.h b/platform/ext/target/common/mbedtls_config.h
new file mode 100644
index 0000000..db2d4dd
--- /dev/null
+++ b/platform/ext/target/common/mbedtls_config.h
@@ -0,0 +1,2682 @@
+/**
+ * \file config.h
+ *
+ * \brief Configuration options (set of defines)
+ *
+ * This set of compile-time options may be used to enable
+ * or disable features selectively, and reduce the global
+ * memory footprint.
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
+
+#ifndef MBEDTLS_CONFIG_H
+#define MBEDTLS_CONFIG_H
+
+#if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_DEPRECATE)
+#define _CRT_SECURE_NO_DEPRECATE 1
+#endif
+
+/**
+ * \name SECTION: System support
+ *
+ * This section sets system specific settings.
+ * \{
+ */
+
+/**
+ * \def MBEDTLS_HAVE_ASM
+ *
+ * The compiler has support for asm().
+ *
+ * Requires support for asm() in compiler.
+ *
+ * Used in:
+ * library/timing.c
+ * library/padlock.c
+ * include/mbedtls/bn_mul.h
+ *
+ * Comment to disable the use of assembly code.
+ */
+#define MBEDTLS_HAVE_ASM
+
+/**
+ * \def MBEDTLS_HAVE_SSE2
+ *
+ * CPU supports SSE2 instruction set.
+ *
+ * Uncomment if the CPU supports SSE2 (IA-32 specific).
+ */
+//#define MBEDTLS_HAVE_SSE2
+
+/**
+ * \def MBEDTLS_HAVE_TIME
+ *
+ * System has time.h and time().
+ * The time does not need to be correct, only time differences are used,
+ * by contrast with MBEDTLS_HAVE_TIME_DATE
+ *
+ * Defining MBEDTLS_HAVE_TIME allows you to specify MBEDTLS_PLATFORM_TIME_ALT,
+ * MBEDTLS_PLATFORM_TIME_MACRO, MBEDTLS_PLATFORM_TIME_TYPE_MACRO and
+ * MBEDTLS_PLATFORM_STD_TIME.
+ *
+ * Comment if your system does not support time functions
+ */
+#define MBEDTLS_HAVE_TIME
+
+/**
+ * \def MBEDTLS_HAVE_TIME_DATE
+ *
+ * System has time.h and time(), gmtime() and the clock is correct.
+ * The time needs to be correct (not necesarily very accurate, but at least
+ * the date should be correct). This is used to verify the validity period of
+ * X.509 certificates.
+ *
+ * Comment if your system does not have a correct clock.
+ */
+#define MBEDTLS_HAVE_TIME_DATE
+
+/**
+ * \def MBEDTLS_PLATFORM_MEMORY
+ *
+ * Enable the memory allocation layer.
+ *
+ * By default mbed TLS uses the system-provided calloc() and free().
+ * This allows different allocators (self-implemented or provided) to be
+ * provided to the platform abstraction layer.
+ *
+ * Enabling MBEDTLS_PLATFORM_MEMORY without the
+ * MBEDTLS_PLATFORM_{FREE,CALLOC}_MACROs will provide
+ * "mbedtls_platform_set_calloc_free()" allowing you to set an alternative calloc() and
+ * free() function pointer at runtime.
+ *
+ * Enabling MBEDTLS_PLATFORM_MEMORY and specifying
+ * MBEDTLS_PLATFORM_{CALLOC,FREE}_MACROs will allow you to specify the
+ * alternate function at compile time.
+ *
+ * Requires: MBEDTLS_PLATFORM_C
+ *
+ * Enable this layer to allow use of alternative memory allocators.
+ */
+#define MBEDTLS_PLATFORM_MEMORY
+
+/**
+ * \def MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
+ *
+ * Do not assign standard functions in the platform layer (e.g. calloc() to
+ * MBEDTLS_PLATFORM_STD_CALLOC and printf() to MBEDTLS_PLATFORM_STD_PRINTF)
+ *
+ * This makes sure there are no linking errors on platforms that do not support
+ * these functions. You will HAVE to provide alternatives, either at runtime
+ * via the platform_set_xxx() functions or at compile time by setting
+ * the MBEDTLS_PLATFORM_STD_XXX defines, or enabling a
+ * MBEDTLS_PLATFORM_XXX_MACRO.
+ *
+ * Requires: MBEDTLS_PLATFORM_C
+ *
+ * Uncomment to prevent default assignment of standard functions in the
+ * platform layer.
+ */
+//#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
+
+/**
+ * \def MBEDTLS_PLATFORM_EXIT_ALT
+ *
+ * MBEDTLS_PLATFORM_XXX_ALT: Uncomment a macro to let mbed TLS support the
+ * function in the platform abstraction layer.
+ *
+ * Example: In case you uncomment MBEDTLS_PLATFORM_PRINTF_ALT, mbed TLS will
+ * provide a function "mbedtls_platform_set_printf()" that allows you to set an
+ * alternative printf function pointer.
+ *
+ * All these define require MBEDTLS_PLATFORM_C to be defined!
+ *
+ * \note MBEDTLS_PLATFORM_SNPRINTF_ALT is required on Windows;
+ * it will be enabled automatically by check_config.h
+ *
+ * \warning MBEDTLS_PLATFORM_XXX_ALT cannot be defined at the same time as
+ * MBEDTLS_PLATFORM_XXX_MACRO!
+ *
+ * Requires: MBEDTLS_PLATFORM_TIME_ALT requires MBEDTLS_HAVE_TIME
+ *
+ * Uncomment a macro to enable alternate implementation of specific base
+ * platform function
+ */
+//#define MBEDTLS_PLATFORM_EXIT_ALT
+//#define MBEDTLS_PLATFORM_TIME_ALT
+//#define MBEDTLS_PLATFORM_FPRINTF_ALT
+//#define MBEDTLS_PLATFORM_PRINTF_ALT
+//#define MBEDTLS_PLATFORM_SNPRINTF_ALT
+//#define MBEDTLS_PLATFORM_NV_SEED_ALT
+
+/**
+ * \def MBEDTLS_DEPRECATED_WARNING
+ *
+ * Mark deprecated functions so that they generate a warning if used.
+ * Functions deprecated in one version will usually be removed in the next
+ * version. You can enable this to help you prepare the transition to a new
+ * major version by making sure your code is not using these functions.
+ *
+ * This only works with GCC and Clang. With other compilers, you may want to
+ * use MBEDTLS_DEPRECATED_REMOVED
+ *
+ * Uncomment to get warnings on using deprecated functions.
+ */
+//#define MBEDTLS_DEPRECATED_WARNING
+
+/**
+ * \def MBEDTLS_DEPRECATED_REMOVED
+ *
+ * Remove deprecated functions so that they generate an error if used.
+ * Functions deprecated in one version will usually be removed in the next
+ * version. You can enable this to help you prepare the transition to a new
+ * major version by making sure your code is not using these functions.
+ *
+ * Uncomment to get errors on using deprecated functions.
+ */
+//#define MBEDTLS_DEPRECATED_REMOVED
+
+/* \} name SECTION: System support */
+
+/**
+ * \name SECTION: mbed TLS feature support
+ *
+ * This section sets support for features that are or are not needed
+ * within the modules that are enabled.
+ * \{
+ */
+
+/**
+ * \def MBEDTLS_TIMING_ALT
+ *
+ * Uncomment to provide your own alternate implementation for mbedtls_timing_hardclock(),
+ * mbedtls_timing_get_timer(), mbedtls_set_alarm(), mbedtls_set/get_delay()
+ *
+ * Only works if you have MBEDTLS_TIMING_C enabled.
+ *
+ * You will need to provide a header "timing_alt.h" and an implementation at
+ * compile time.
+ */
+//#define MBEDTLS_TIMING_ALT
+
+/**
+ * \def MBEDTLS_AES_ALT
+ *
+ * MBEDTLS__MODULE_NAME__ALT: Uncomment a macro to let mbed TLS use your
+ * alternate core implementation of a symmetric crypto, an arithmetic or hash
+ * module (e.g. platform specific assembly optimized implementations). Keep
+ * in mind that the function prototypes should remain the same.
+ *
+ * This replaces the whole module. If you only want to replace one of the
+ * functions, use one of the MBEDTLS__FUNCTION_NAME__ALT flags.
+ *
+ * Example: In case you uncomment MBEDTLS_AES_ALT, mbed TLS will no longer
+ * provide the "struct mbedtls_aes_context" definition and omit the base
+ * function declarations and implementations. "aes_alt.h" will be included from
+ * "aes.h" to include the new function definitions.
+ *
+ * Uncomment a macro to enable alternate implementation of the corresponding
+ * module.
+ */
+//#define MBEDTLS_AES_ALT
+//#define MBEDTLS_ARC4_ALT
+//#define MBEDTLS_BLOWFISH_ALT
+//#define MBEDTLS_CAMELLIA_ALT
+//#define MBEDTLS_DES_ALT
+//#define MBEDTLS_XTEA_ALT
+//#define MBEDTLS_MD2_ALT
+//#define MBEDTLS_MD4_ALT
+//#define MBEDTLS_MD5_ALT
+//#define MBEDTLS_RIPEMD160_ALT
+//#define MBEDTLS_SHA1_ALT
+//#define MBEDTLS_SHA256_ALT
+//#define MBEDTLS_SHA512_ALT
+/*
+ * When replacing the elliptic curve module, pleace consider, that it is
+ * implemented with two .c files:
+ * - ecp.c
+ * - ecp_curves.c
+ * You can replace them very much like all the other MBEDTLS__MODULE_NAME__ALT
+ * macros as described above. The only difference is that you have to make sure
+ * that you provide functionality for both .c files.
+ */
+//#define MBEDTLS_ECP_ALT
+
+/**
+ * \def MBEDTLS_MD2_PROCESS_ALT
+ *
+ * MBEDTLS__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use you
+ * alternate core implementation of symmetric crypto or hash function. Keep in
+ * mind that function prototypes should remain the same.
+ *
+ * This replaces only one function. The header file from mbed TLS is still
+ * used, in contrast to the MBEDTLS__MODULE_NAME__ALT flags.
+ *
+ * Example: In case you uncomment MBEDTLS_SHA256_PROCESS_ALT, mbed TLS will
+ * no longer provide the mbedtls_sha1_process() function, but it will still provide
+ * the other function (using your mbedtls_sha1_process() function) and the definition
+ * of mbedtls_sha1_context, so your implementation of mbedtls_sha1_process must be compatible
+ * with this definition.
+ *
+ * Note: if you use the AES_xxx_ALT macros, then is is recommended to also set
+ * MBEDTLS_AES_ROM_TABLES in order to help the linker garbage-collect the AES
+ * tables.
+ *
+ * Uncomment a macro to enable alternate implementation of the corresponding
+ * function.
+ */
+//#define MBEDTLS_MD2_PROCESS_ALT
+//#define MBEDTLS_MD4_PROCESS_ALT
+//#define MBEDTLS_MD5_PROCESS_ALT
+//#define MBEDTLS_RIPEMD160_PROCESS_ALT
+//#define MBEDTLS_SHA1_PROCESS_ALT
+//#define MBEDTLS_SHA256_PROCESS_ALT
+//#define MBEDTLS_SHA512_PROCESS_ALT
+//#define MBEDTLS_DES_SETKEY_ALT
+//#define MBEDTLS_DES_CRYPT_ECB_ALT
+//#define MBEDTLS_DES3_CRYPT_ECB_ALT
+//#define MBEDTLS_AES_SETKEY_ENC_ALT
+//#define MBEDTLS_AES_SETKEY_DEC_ALT
+//#define MBEDTLS_AES_ENCRYPT_ALT
+//#define MBEDTLS_AES_DECRYPT_ALT
+
+/**
+ * \def MBEDTLS_ECP_INTERNAL_ALT
+ *
+ * Expose a part of the internal interface of the Elliptic Curve Point module.
+ *
+ * MBEDTLS_ECP__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use your
+ * alternative core implementation of elliptic curve arithmetic. Keep in mind
+ * that function prototypes should remain the same.
+ *
+ * This partially replaces one function. The header file from mbed TLS is still
+ * used, in contrast to the MBEDTLS_ECP_ALT flag. The original implementation
+ * is still present and it is used for group structures not supported by the
+ * alternative.
+ *
+ * Any of these options become available by defining MBEDTLS_ECP_INTERNAL_ALT
+ * and implementing the following functions:
+ * unsigned char mbedtls_internal_ecp_grp_capable(
+ * const mbedtls_ecp_group *grp )
+ * int mbedtls_internal_ecp_init( const mbedtls_ecp_group *grp )
+ * void mbedtls_internal_ecp_deinit( const mbedtls_ecp_group *grp )
+ * The mbedtls_internal_ecp_grp_capable function should return 1 if the
+ * replacement functions implement arithmetic for the given group and 0
+ * otherwise.
+ * The functions mbedtls_internal_ecp_init and mbedtls_internal_ecp_deinit are
+ * called before and after each point operation and provide an opportunity to
+ * implement optimized set up and tear down instructions.
+ *
+ * Example: In case you uncomment MBEDTLS_ECP_INTERNAL_ALT and
+ * MBEDTLS_ECP_DOUBLE_JAC_ALT, mbed TLS will still provide the ecp_double_jac
+ * function, but will use your mbedtls_internal_ecp_double_jac if the group is
+ * supported (your mbedtls_internal_ecp_grp_capable function returns 1 when
+ * receives it as an argument). If the group is not supported then the original
+ * implementation is used. The other functions and the definition of
+ * mbedtls_ecp_group and mbedtls_ecp_point will not change, so your
+ * implementation of mbedtls_internal_ecp_double_jac and
+ * mbedtls_internal_ecp_grp_capable must be compatible with this definition.
+ *
+ * Uncomment a macro to enable alternate implementation of the corresponding
+ * function.
+ */
+/* Required for all the functions in this section */
+//#define MBEDTLS_ECP_INTERNAL_ALT
+/* Support for Weierstrass curves with Jacobi representation */
+//#define MBEDTLS_ECP_RANDOMIZE_JAC_ALT
+//#define MBEDTLS_ECP_ADD_MIXED_ALT
+//#define MBEDTLS_ECP_DOUBLE_JAC_ALT
+//#define MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT
+//#define MBEDTLS_ECP_NORMALIZE_JAC_ALT
+/* Support for curves with Montgomery arithmetic */
+//#define MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT
+//#define MBEDTLS_ECP_RANDOMIZE_MXZ_ALT
+//#define MBEDTLS_ECP_NORMALIZE_MXZ_ALT
+
+/**
+ * \def MBEDTLS_TEST_NULL_ENTROPY
+ *
+ * Enables testing and use of mbed TLS without any configured entropy sources.
+ * This permits use of the library on platforms before an entropy source has
+ * been integrated (see for example the MBEDTLS_ENTROPY_HARDWARE_ALT or the
+ * MBEDTLS_ENTROPY_NV_SEED switches).
+ *
+ * WARNING! This switch MUST be disabled in production builds, and is suitable
+ * only for development.
+ * Enabling the switch negates any security provided by the library.
+ *
+ * Requires MBEDTLS_ENTROPY_C, MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+ *
+ */
+//#define MBEDTLS_TEST_NULL_ENTROPY
+
+/**
+ * \def MBEDTLS_ENTROPY_HARDWARE_ALT
+ *
+ * Uncomment this macro to let mbed TLS use your own implementation of a
+ * hardware entropy collector.
+ *
+ * Your function must be called \c mbedtls_hardware_poll(), have the same
+ * prototype as declared in entropy_poll.h, and accept NULL as first argument.
+ *
+ * Uncomment to use your own hardware entropy collector.
+ */
+//#define MBEDTLS_ENTROPY_HARDWARE_ALT
+
+/**
+ * \def MBEDTLS_AES_ROM_TABLES
+ *
+ * Store the AES tables in ROM.
+ *
+ * Uncomment this macro to store the AES tables in ROM.
+ */
+//#define MBEDTLS_AES_ROM_TABLES
+
+/**
+ * \def MBEDTLS_CAMELLIA_SMALL_MEMORY
+ *
+ * Use less ROM for the Camellia implementation (saves about 768 bytes).
+ *
+ * Uncomment this macro to use less memory for Camellia.
+ */
+//#define MBEDTLS_CAMELLIA_SMALL_MEMORY
+
+/**
+ * \def MBEDTLS_CIPHER_MODE_CBC
+ *
+ * Enable Cipher Block Chaining mode (CBC) for symmetric ciphers.
+ */
+#define MBEDTLS_CIPHER_MODE_CBC
+
+/**
+ * \def MBEDTLS_CIPHER_MODE_CFB
+ *
+ * Enable Cipher Feedback mode (CFB) for symmetric ciphers.
+ */
+#define MBEDTLS_CIPHER_MODE_CFB
+
+/**
+ * \def MBEDTLS_CIPHER_MODE_CTR
+ *
+ * Enable Counter Block Cipher mode (CTR) for symmetric ciphers.
+ */
+#define MBEDTLS_CIPHER_MODE_CTR
+
+/**
+ * \def MBEDTLS_CIPHER_NULL_CIPHER
+ *
+ * Enable NULL cipher.
+ * Warning: Only do so when you know what you are doing. This allows for
+ * encryption or channels without any security!
+ *
+ * Requires MBEDTLS_ENABLE_WEAK_CIPHERSUITES as well to enable
+ * the following ciphersuites:
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA
+ * MBEDTLS_TLS_RSA_WITH_NULL_SHA256
+ * MBEDTLS_TLS_RSA_WITH_NULL_SHA
+ * MBEDTLS_TLS_RSA_WITH_NULL_MD5
+ * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA
+ * MBEDTLS_TLS_PSK_WITH_NULL_SHA384
+ * MBEDTLS_TLS_PSK_WITH_NULL_SHA256
+ * MBEDTLS_TLS_PSK_WITH_NULL_SHA
+ *
+ * Uncomment this macro to enable the NULL cipher and ciphersuites
+ */
+//#define MBEDTLS_CIPHER_NULL_CIPHER
+
+/**
+ * \def MBEDTLS_CIPHER_PADDING_PKCS7
+ *
+ * MBEDTLS_CIPHER_PADDING_XXX: Uncomment or comment macros to add support for
+ * specific padding modes in the cipher layer with cipher modes that support
+ * padding (e.g. CBC)
+ *
+ * If you disable all padding modes, only full blocks can be used with CBC.
+ *
+ * Enable padding modes in the cipher layer.
+ */
+#define MBEDTLS_CIPHER_PADDING_PKCS7
+#define MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS
+#define MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN
+#define MBEDTLS_CIPHER_PADDING_ZEROS
+
+/**
+ * \def MBEDTLS_ENABLE_WEAK_CIPHERSUITES
+ *
+ * Enable weak ciphersuites in SSL / TLS.
+ * Warning: Only do so when you know what you are doing. This allows for
+ * channels with virtually no security at all!
+ *
+ * This enables the following ciphersuites:
+ * MBEDTLS_TLS_RSA_WITH_DES_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_DES_CBC_SHA
+ *
+ * Uncomment this macro to enable weak ciphersuites
+ */
+//#define MBEDTLS_ENABLE_WEAK_CIPHERSUITES
+
+/**
+ * \def MBEDTLS_REMOVE_ARC4_CIPHERSUITES
+ *
+ * Remove RC4 ciphersuites by default in SSL / TLS.
+ * This flag removes the ciphersuites based on RC4 from the default list as
+ * returned by mbedtls_ssl_list_ciphersuites(). However, it is still possible to
+ * enable (some of) them with mbedtls_ssl_conf_ciphersuites() by including them
+ * explicitly.
+ *
+ * Uncomment this macro to remove RC4 ciphersuites by default.
+ */
+#define MBEDTLS_REMOVE_ARC4_CIPHERSUITES
+
+/**
+ * \def MBEDTLS_ECP_DP_SECP192R1_ENABLED
+ *
+ * MBEDTLS_ECP_XXXX_ENABLED: Enables specific curves within the Elliptic Curve
+ * module. By default all supported curves are enabled.
+ *
+ * Comment macros to disable the curve and functions for it
+ */
+#define MBEDTLS_ECP_DP_SECP192R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP224R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP384R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP521R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP192K1_ENABLED
+#define MBEDTLS_ECP_DP_SECP224K1_ENABLED
+#define MBEDTLS_ECP_DP_SECP256K1_ENABLED
+#define MBEDTLS_ECP_DP_BP256R1_ENABLED
+#define MBEDTLS_ECP_DP_BP384R1_ENABLED
+#define MBEDTLS_ECP_DP_BP512R1_ENABLED
+#define MBEDTLS_ECP_DP_CURVE25519_ENABLED
+
+/**
+ * \def MBEDTLS_ECP_NIST_OPTIM
+ *
+ * Enable specific 'modulo p' routines for each NIST prime.
+ * Depending on the prime and architecture, makes operations 4 to 8 times
+ * faster on the corresponding curve.
+ *
+ * Comment this macro to disable NIST curves optimisation.
+ */
+#define MBEDTLS_ECP_NIST_OPTIM
+
+/**
+ * \def MBEDTLS_ECDSA_DETERMINISTIC
+ *
+ * Enable deterministic ECDSA (RFC 6979).
+ * Standard ECDSA is "fragile" in the sense that lack of entropy when signing
+ * may result in a compromise of the long-term signing key. This is avoided by
+ * the deterministic variant.
+ *
+ * Requires: MBEDTLS_HMAC_DRBG_C
+ *
+ * Comment this macro to disable deterministic ECDSA.
+ */
+#define MBEDTLS_ECDSA_DETERMINISTIC
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
+ *
+ * Enable the PSK based ciphersuite modes in SSL / TLS.
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_PSK_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
+ *
+ * Enable the DHE-PSK based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_DHM_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
+ *
+ * Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
+ *
+ * Enable the RSA-PSK based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ * MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
+ *
+ * Enable the RSA-only based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ * MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_RSA_WITH_RC4_128_MD5
+ */
+#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
+ *
+ * Enable the DHE-RSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_DHM_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ * MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
+ *
+ * Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ * MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
+ *
+ * Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_ECDSA_C, MBEDTLS_X509_CRT_PARSE_C,
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
+ *
+ * Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
+ *
+ * Enable the ECDH-RSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
+ *
+ * Enable the ECJPAKE based ciphersuite modes in SSL / TLS.
+ *
+ * \warning This is currently experimental. EC J-PAKE support is based on the
+ * Thread v1.0.0 specification; incompatible changes to the specification
+ * might still happen. For this reason, this is disabled by default.
+ *
+ * Requires: MBEDTLS_ECJPAKE_C
+ * MBEDTLS_SHA256_C
+ * MBEDTLS_ECP_DP_SECP256R1_ENABLED
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8
+ */
+//#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
+
+/**
+ * \def MBEDTLS_PK_PARSE_EC_EXTENDED
+ *
+ * Enhance support for reading EC keys using variants of SEC1 not allowed by
+ * RFC 5915 and RFC 5480.
+ *
+ * Currently this means parsing the SpecifiedECDomain choice of EC
+ * parameters (only known groups are supported, not arbitrary domains, to
+ * avoid validation issues).
+ *
+ * Disable if you only need to support RFC 5915 + 5480 key formats.
+ */
+#define MBEDTLS_PK_PARSE_EC_EXTENDED
+
+/**
+ * \def MBEDTLS_ERROR_STRERROR_DUMMY
+ *
+ * Enable a dummy error function to make use of mbedtls_strerror() in
+ * third party libraries easier when MBEDTLS_ERROR_C is disabled
+ * (no effect when MBEDTLS_ERROR_C is enabled).
+ *
+ * You can safely disable this if MBEDTLS_ERROR_C is enabled, or if you're
+ * not using mbedtls_strerror() or error_strerror() in your application.
+ *
+ * Disable if you run into name conflicts and want to really remove the
+ * mbedtls_strerror()
+ */
+#define MBEDTLS_ERROR_STRERROR_DUMMY
+
+/**
+ * \def MBEDTLS_GENPRIME
+ *
+ * Enable the prime-number generation code.
+ *
+ * Requires: MBEDTLS_BIGNUM_C
+ */
+#define MBEDTLS_GENPRIME
+
+/**
+ * \def MBEDTLS_FS_IO
+ *
+ * Enable functions that use the filesystem.
+ */
+//#define MBEDTLS_FS_IO
+
+/**
+ * \def MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+ *
+ * Do not add default entropy sources. These are the platform specific,
+ * mbedtls_timing_hardclock and HAVEGE based poll functions.
+ *
+ * This is useful to have more control over the added entropy sources in an
+ * application.
+ *
+ * Uncomment this macro to prevent loading of default entropy functions.
+ */
+//#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+
+/**
+ * \def MBEDTLS_NO_PLATFORM_ENTROPY
+ *
+ * Do not use built-in platform entropy functions.
+ * This is useful if your platform does not support
+ * standards like the /dev/urandom or Windows CryptoAPI.
+ *
+ * Uncomment this macro to disable the built-in platform entropy functions.
+ */
+#define MBEDTLS_NO_PLATFORM_ENTROPY
+
+/**
+ * \def MBEDTLS_ENTROPY_FORCE_SHA256
+ *
+ * Force the entropy accumulator to use a SHA-256 accumulator instead of the
+ * default SHA-512 based one (if both are available).
+ *
+ * Requires: MBEDTLS_SHA256_C
+ *
+ * On 32-bit systems SHA-256 can be much faster than SHA-512. Use this option
+ * if you have performance concerns.
+ *
+ * This option is only useful if both MBEDTLS_SHA256_C and
+ * MBEDTLS_SHA512_C are defined. Otherwise the available hash module is used.
+ */
+//#define MBEDTLS_ENTROPY_FORCE_SHA256
+
+/**
+ * \def MBEDTLS_ENTROPY_NV_SEED
+ *
+ * Enable the non-volatile (NV) seed file-based entropy source.
+ * (Also enables the NV seed read/write functions in the platform layer)
+ *
+ * This is crucial (if not required) on systems that do not have a
+ * cryptographic entropy source (in hardware or kernel) available.
+ *
+ * Requires: MBEDTLS_ENTROPY_C, MBEDTLS_PLATFORM_C
+ *
+ * \note The read/write functions that are used by the entropy source are
+ * determined in the platform layer, and can be modified at runtime and/or
+ * compile-time depending on the flags (MBEDTLS_PLATFORM_NV_SEED_*) used.
+ *
+ * \note If you use the default implementation functions that read a seedfile
+ * with regular fopen(), please make sure you make a seedfile with the
+ * proper name (defined in MBEDTLS_PLATFORM_STD_NV_SEED_FILE) and at
+ * least MBEDTLS_ENTROPY_BLOCK_SIZE bytes in size that can be read from
+ * and written to or you will get an entropy source error! The default
+ * implementation will only use the first MBEDTLS_ENTROPY_BLOCK_SIZE
+ * bytes from the file.
+ *
+ * \note The entropy collector will write to the seed file before entropy is
+ * given to an external source, to update it.
+ */
+//#define MBEDTLS_ENTROPY_NV_SEED
+
+/**
+ * \def MBEDTLS_MEMORY_DEBUG
+ *
+ * Enable debugging of buffer allocator memory issues. Automatically prints
+ * (to stderr) all (fatal) messages on memory allocation issues. Enables
+ * function for 'debug output' of allocated memory.
+ *
+ * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C
+ *
+ * Uncomment this macro to let the buffer allocator print out error messages.
+ */
+//#define MBEDTLS_MEMORY_DEBUG
+
+/**
+ * \def MBEDTLS_MEMORY_BACKTRACE
+ *
+ * Include backtrace information with each allocated block.
+ *
+ * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C
+ * GLIBC-compatible backtrace() an backtrace_symbols() support
+ *
+ * Uncomment this macro to include backtrace information
+ */
+//#define MBEDTLS_MEMORY_BACKTRACE
+
+/**
+ * \def MBEDTLS_PK_RSA_ALT_SUPPORT
+ *
+ * Support external private RSA keys (eg from a HSM) in the PK layer.
+ *
+ * Comment this macro to disable support for external private RSA keys.
+ */
+#define MBEDTLS_PK_RSA_ALT_SUPPORT
+
+/**
+ * \def MBEDTLS_PKCS1_V15
+ *
+ * Enable support for PKCS#1 v1.5 encoding.
+ *
+ * Requires: MBEDTLS_RSA_C
+ *
+ * This enables support for PKCS#1 v1.5 operations.
+ */
+#define MBEDTLS_PKCS1_V15
+
+/**
+ * \def MBEDTLS_PKCS1_V21
+ *
+ * Enable support for PKCS#1 v2.1 encoding.
+ *
+ * Requires: MBEDTLS_MD_C, MBEDTLS_RSA_C
+ *
+ * This enables support for RSAES-OAEP and RSASSA-PSS operations.
+ */
+#define MBEDTLS_PKCS1_V21
+
+/**
+ * \def MBEDTLS_RSA_NO_CRT
+ *
+ * Do not use the Chinese Remainder Theorem for the RSA private operation.
+ *
+ * Uncomment this macro to disable the use of CRT in RSA.
+ *
+ */
+//#define MBEDTLS_RSA_NO_CRT
+
+/**
+ * \def MBEDTLS_SELF_TEST
+ *
+ * Enable the checkup functions (*_self_test).
+ */
+#define MBEDTLS_SELF_TEST
+
+/**
+ * \def MBEDTLS_SHA256_SMALLER
+ *
+ * Enable an implementation of SHA-256 that has lower ROM footprint but also
+ * lower performance.
+ *
+ * The default implementation is meant to be a reasonnable compromise between
+ * performance and size. This version optimizes more aggressively for size at
+ * the expense of performance. Eg on Cortex-M4 it reduces the size of
+ * mbedtls_sha256_process() from ~2KB to ~0.5KB for a performance hit of about
+ * 30%.
+ *
+ * Uncomment to enable the smaller implementation of SHA256.
+ */
+//#define MBEDTLS_SHA256_SMALLER
+
+/**
+ * \def MBEDTLS_SSL_ALL_ALERT_MESSAGES
+ *
+ * Enable sending of alert messages in case of encountered errors as per RFC.
+ * If you choose not to send the alert messages, mbed TLS can still communicate
+ * with other servers, only debugging of failures is harder.
+ *
+ * The advantage of not sending alert messages, is that no information is given
+ * about reasons for failures thus preventing adversaries of gaining intel.
+ *
+ * Enable sending of all alert messages
+ */
+#define MBEDTLS_SSL_ALL_ALERT_MESSAGES
+
+/**
+ * \def MBEDTLS_SSL_DEBUG_ALL
+ *
+ * Enable the debug messages in SSL module for all issues.
+ * Debug messages have been disabled in some places to prevent timing
+ * attacks due to (unbalanced) debugging function calls.
+ *
+ * If you need all error reporting you should enable this during debugging,
+ * but remove this for production servers that should log as well.
+ *
+ * Uncomment this macro to report all debug messages on errors introducing
+ * a timing side-channel.
+ *
+ */
+//#define MBEDTLS_SSL_DEBUG_ALL
+
+/** \def MBEDTLS_SSL_ENCRYPT_THEN_MAC
+ *
+ * Enable support for Encrypt-then-MAC, RFC 7366.
+ *
+ * This allows peers that both support it to use a more robust protection for
+ * ciphersuites using CBC, providing deep resistance against timing attacks
+ * on the padding or underlying cipher.
+ *
+ * This only affects CBC ciphersuites, and is useless if none is defined.
+ *
+ * Requires: MBEDTLS_SSL_PROTO_TLS1 or
+ * MBEDTLS_SSL_PROTO_TLS1_1 or
+ * MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Comment this macro to disable support for Encrypt-then-MAC
+ */
+#define MBEDTLS_SSL_ENCRYPT_THEN_MAC
+
+/** \def MBEDTLS_SSL_EXTENDED_MASTER_SECRET
+ *
+ * Enable support for Extended Master Secret, aka Session Hash
+ * (draft-ietf-tls-session-hash-02).
+ *
+ * This was introduced as "the proper fix" to the Triple Handshake familiy of
+ * attacks, but it is recommended to always use it (even if you disable
+ * renegotiation), since it actually fixes a more fundamental issue in the
+ * original SSL/TLS design, and has implications beyond Triple Handshake.
+ *
+ * Requires: MBEDTLS_SSL_PROTO_TLS1 or
+ * MBEDTLS_SSL_PROTO_TLS1_1 or
+ * MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Comment this macro to disable support for Extended Master Secret.
+ */
+#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET
+
+/**
+ * \def MBEDTLS_SSL_FALLBACK_SCSV
+ *
+ * Enable support for FALLBACK_SCSV (draft-ietf-tls-downgrade-scsv-00).
+ *
+ * For servers, it is recommended to always enable this, unless you support
+ * only one version of TLS, or know for sure that none of your clients
+ * implements a fallback strategy.
+ *
+ * For clients, you only need this if you're using a fallback strategy, which
+ * is not recommended in the first place, unless you absolutely need it to
+ * interoperate with buggy (version-intolerant) servers.
+ *
+ * Comment this macro to disable support for FALLBACK_SCSV
+ */
+#define MBEDTLS_SSL_FALLBACK_SCSV
+
+/**
+ * \def MBEDTLS_SSL_HW_RECORD_ACCEL
+ *
+ * Enable hooking functions in SSL module for hardware acceleration of
+ * individual records.
+ *
+ * Uncomment this macro to enable hooking functions.
+ */
+//#define MBEDTLS_SSL_HW_RECORD_ACCEL
+
+/**
+ * \def MBEDTLS_SSL_CBC_RECORD_SPLITTING
+ *
+ * Enable 1/n-1 record splitting for CBC mode in SSLv3 and TLS 1.0.
+ *
+ * This is a countermeasure to the BEAST attack, which also minimizes the risk
+ * of interoperability issues compared to sending 0-length records.
+ *
+ * Comment this macro to disable 1/n-1 record splitting.
+ */
+#define MBEDTLS_SSL_CBC_RECORD_SPLITTING
+
+/**
+ * \def MBEDTLS_SSL_RENEGOTIATION
+ *
+ * Disable support for TLS renegotiation.
+ *
+ * The two main uses of renegotiation are (1) refresh keys on long-lived
+ * connections and (2) client authentication after the initial handshake.
+ * If you don't need renegotiation, it's probably better to disable it, since
+ * it has been associated with security issues in the past and is easy to
+ * misuse/misunderstand.
+ *
+ * Comment this to disable support for renegotiation.
+ */
+#define MBEDTLS_SSL_RENEGOTIATION
+
+/**
+ * \def MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
+ *
+ * Enable support for receiving and parsing SSLv2 Client Hello messages for the
+ * SSL Server module (MBEDTLS_SSL_SRV_C).
+ *
+ * Uncomment this macro to enable support for SSLv2 Client Hello messages.
+ */
+//#define MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
+
+/**
+ * \def MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE
+ *
+ * Pick the ciphersuite according to the client's preferences rather than ours
+ * in the SSL Server module (MBEDTLS_SSL_SRV_C).
+ *
+ * Uncomment this macro to respect client's ciphersuite order
+ */
+//#define MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE
+
+/**
+ * \def MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
+ *
+ * Enable support for RFC 6066 max_fragment_length extension in SSL.
+ *
+ * Comment this macro to disable support for the max_fragment_length extension
+ */
+#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
+
+/**
+ * \def MBEDTLS_SSL_PROTO_SSL3
+ *
+ * Enable support for SSL 3.0.
+ *
+ * Requires: MBEDTLS_MD5_C
+ * MBEDTLS_SHA1_C
+ *
+ * Comment this macro to disable support for SSL 3.0
+ */
+//#define MBEDTLS_SSL_PROTO_SSL3
+
+/**
+ * \def MBEDTLS_SSL_PROTO_TLS1
+ *
+ * Enable support for TLS 1.0.
+ *
+ * Requires: MBEDTLS_MD5_C
+ * MBEDTLS_SHA1_C
+ *
+ * Comment this macro to disable support for TLS 1.0
+ */
+#define MBEDTLS_SSL_PROTO_TLS1
+
+/**
+ * \def MBEDTLS_SSL_PROTO_TLS1_1
+ *
+ * Enable support for TLS 1.1 (and DTLS 1.0 if DTLS is enabled).
+ *
+ * Requires: MBEDTLS_MD5_C
+ * MBEDTLS_SHA1_C
+ *
+ * Comment this macro to disable support for TLS 1.1 / DTLS 1.0
+ */
+#define MBEDTLS_SSL_PROTO_TLS1_1
+
+/**
+ * \def MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Enable support for TLS 1.2 (and DTLS 1.2 if DTLS is enabled).
+ *
+ * Requires: MBEDTLS_SHA1_C or MBEDTLS_SHA256_C or MBEDTLS_SHA512_C
+ * (Depends on ciphersuites)
+ *
+ * Comment this macro to disable support for TLS 1.2 / DTLS 1.2
+ */
+#define MBEDTLS_SSL_PROTO_TLS1_2
+
+/**
+ * \def MBEDTLS_SSL_PROTO_DTLS
+ *
+ * Enable support for DTLS (all available versions).
+ *
+ * Enable this and MBEDTLS_SSL_PROTO_TLS1_1 to enable DTLS 1.0,
+ * and/or this and MBEDTLS_SSL_PROTO_TLS1_2 to enable DTLS 1.2.
+ *
+ * Requires: MBEDTLS_SSL_PROTO_TLS1_1
+ * or MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Comment this macro to disable support for DTLS
+ */
+#define MBEDTLS_SSL_PROTO_DTLS
+
+/**
+ * \def MBEDTLS_SSL_ALPN
+ *
+ * Enable support for RFC 7301 Application Layer Protocol Negotiation.
+ *
+ * Comment this macro to disable support for ALPN.
+ */
+#define MBEDTLS_SSL_ALPN
+
+/**
+ * \def MBEDTLS_SSL_DTLS_ANTI_REPLAY
+ *
+ * Enable support for the anti-replay mechanism in DTLS.
+ *
+ * Requires: MBEDTLS_SSL_TLS_C
+ * MBEDTLS_SSL_PROTO_DTLS
+ *
+ * \warning Disabling this is often a security risk!
+ * See mbedtls_ssl_conf_dtls_anti_replay() for details.
+ *
+ * Comment this to disable anti-replay in DTLS.
+ */
+#define MBEDTLS_SSL_DTLS_ANTI_REPLAY
+
+/**
+ * \def MBEDTLS_SSL_DTLS_HELLO_VERIFY
+ *
+ * Enable support for HelloVerifyRequest on DTLS servers.
+ *
+ * This feature is highly recommended to prevent DTLS servers being used as
+ * amplifiers in DoS attacks against other hosts. It should always be enabled
+ * unless you know for sure amplification cannot be a problem in the
+ * environment in which your server operates.
+ *
+ * \warning Disabling this can ba a security risk! (see above)
+ *
+ * Requires: MBEDTLS_SSL_PROTO_DTLS
+ *
+ * Comment this to disable support for HelloVerifyRequest.
+ */
+#define MBEDTLS_SSL_DTLS_HELLO_VERIFY
+
+/**
+ * \def MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE
+ *
+ * Enable server-side support for clients that reconnect from the same port.
+ *
+ * Some clients unexpectedly close the connection and try to reconnect using the
+ * same source port. This needs special support from the server to handle the
+ * new connection securely, as described in section 4.2.8 of RFC 6347. This
+ * flag enables that support.
+ *
+ * Requires: MBEDTLS_SSL_DTLS_HELLO_VERIFY
+ *
+ * Comment this to disable support for clients reusing the source port.
+ */
+#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE
+
+/**
+ * \def MBEDTLS_SSL_DTLS_BADMAC_LIMIT
+ *
+ * Enable support for a limit of records with bad MAC.
+ *
+ * See mbedtls_ssl_conf_dtls_badmac_limit().
+ *
+ * Requires: MBEDTLS_SSL_PROTO_DTLS
+ */
+#define MBEDTLS_SSL_DTLS_BADMAC_LIMIT
+
+/**
+ * \def MBEDTLS_SSL_SESSION_TICKETS
+ *
+ * Enable support for RFC 5077 session tickets in SSL.
+ * Client-side, provides full support for session tickets (maintainance of a
+ * session store remains the responsibility of the application, though).
+ * Server-side, you also need to provide callbacks for writing and parsing
+ * tickets, including authenticated encryption and key management. Example
+ * callbacks are provided by MBEDTLS_SSL_TICKET_C.
+ *
+ * Comment this macro to disable support for SSL session tickets
+ */
+#define MBEDTLS_SSL_SESSION_TICKETS
+
+/**
+ * \def MBEDTLS_SSL_EXPORT_KEYS
+ *
+ * Enable support for exporting key block and master secret.
+ * This is required for certain users of TLS, e.g. EAP-TLS.
+ *
+ * Comment this macro to disable support for key export
+ */
+#define MBEDTLS_SSL_EXPORT_KEYS
+
+/**
+ * \def MBEDTLS_SSL_SERVER_NAME_INDICATION
+ *
+ * Enable support for RFC 6066 server name indication (SNI) in SSL.
+ *
+ * Requires: MBEDTLS_X509_CRT_PARSE_C
+ *
+ * Comment this macro to disable support for server name indication in SSL
+ */
+#define MBEDTLS_SSL_SERVER_NAME_INDICATION
+
+/**
+ * \def MBEDTLS_SSL_TRUNCATED_HMAC
+ *
+ * Enable support for RFC 6066 truncated HMAC in SSL.
+ *
+ * Comment this macro to disable support for truncated HMAC in SSL
+ */
+#define MBEDTLS_SSL_TRUNCATED_HMAC
+
+/**
+ * \def MBEDTLS_THREADING_ALT
+ *
+ * Provide your own alternate threading implementation.
+ *
+ * Requires: MBEDTLS_THREADING_C
+ *
+ * Uncomment this to allow your own alternate threading implementation.
+ */
+//#define MBEDTLS_THREADING_ALT
+
+/**
+ * \def MBEDTLS_THREADING_PTHREAD
+ *
+ * Enable the pthread wrapper layer for the threading layer.
+ *
+ * Requires: MBEDTLS_THREADING_C
+ *
+ * Uncomment this to enable pthread mutexes.
+ */
+//#define MBEDTLS_THREADING_PTHREAD
+
+/**
+ * \def MBEDTLS_VERSION_FEATURES
+ *
+ * Allow run-time checking of compile-time enabled features. Thus allowing users
+ * to check at run-time if the library is for instance compiled with threading
+ * support via mbedtls_version_check_feature().
+ *
+ * Requires: MBEDTLS_VERSION_C
+ *
+ * Comment this to disable run-time checking and save ROM space
+ */
+#define MBEDTLS_VERSION_FEATURES
+
+/**
+ * \def MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
+ *
+ * If set, the X509 parser will not break-off when parsing an X509 certificate
+ * and encountering an extension in a v1 or v2 certificate.
+ *
+ * Uncomment to prevent an error.
+ */
+//#define MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
+
+/**
+ * \def MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
+ *
+ * If set, the X509 parser will not break-off when parsing an X509 certificate
+ * and encountering an unknown critical extension.
+ *
+ * \warning Depending on your PKI use, enabling this can be a security risk!
+ *
+ * Uncomment to prevent an error.
+ */
+//#define MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
+
+/**
+ * \def MBEDTLS_X509_CHECK_KEY_USAGE
+ *
+ * Enable verification of the keyUsage extension (CA and leaf certificates).
+ *
+ * Disabling this avoids problems with mis-issued and/or misused
+ * (intermediate) CA and leaf certificates.
+ *
+ * \warning Depending on your PKI use, disabling this can be a security risk!
+ *
+ * Comment to skip keyUsage checking for both CA and leaf certificates.
+ */
+#define MBEDTLS_X509_CHECK_KEY_USAGE
+
+/**
+ * \def MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
+ *
+ * Enable verification of the extendedKeyUsage extension (leaf certificates).
+ *
+ * Disabling this avoids problems with mis-issued and/or misused certificates.
+ *
+ * \warning Depending on your PKI use, disabling this can be a security risk!
+ *
+ * Comment to skip extendedKeyUsage checking for certificates.
+ */
+#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
+
+/**
+ * \def MBEDTLS_X509_RSASSA_PSS_SUPPORT
+ *
+ * Enable parsing and verification of X.509 certificates, CRLs and CSRS
+ * signed with RSASSA-PSS (aka PKCS#1 v2.1).
+ *
+ * Comment this macro to disallow using RSASSA-PSS in certificates.
+ */
+#define MBEDTLS_X509_RSASSA_PSS_SUPPORT
+
+/**
+ * \def MBEDTLS_ZLIB_SUPPORT
+ *
+ * If set, the SSL/TLS module uses ZLIB to support compression and
+ * decompression of packet data.
+ *
+ * \warning TLS-level compression MAY REDUCE SECURITY! See for example the
+ * CRIME attack. Before enabling this option, you should examine with care if
+ * CRIME or similar exploits may be a applicable to your use case.
+ *
+ * \note Currently compression can't be used with DTLS.
+ *
+ * Used in: library/ssl_tls.c
+ * library/ssl_cli.c
+ * library/ssl_srv.c
+ *
+ * This feature requires zlib library and headers to be present.
+ *
+ * Uncomment to enable use of ZLIB
+ */
+//#define MBEDTLS_ZLIB_SUPPORT
+/* \} name SECTION: mbed TLS feature support */
+
+/**
+ * \name SECTION: mbed TLS modules
+ *
+ * This section enables or disables entire modules in mbed TLS
+ * \{
+ */
+
+/**
+ * \def MBEDTLS_AESNI_C
+ *
+ * Enable AES-NI support on x86-64.
+ *
+ * Module: library/aesni.c
+ * Caller: library/aes.c
+ *
+ * Requires: MBEDTLS_HAVE_ASM
+ *
+ * This modules adds support for the AES-NI instructions on x86-64
+ */
+#define MBEDTLS_AESNI_C
+
+/**
+ * \def MBEDTLS_AES_C
+ *
+ * Enable the AES block cipher.
+ *
+ * Module: library/aes.c
+ * Caller: library/ssl_tls.c
+ * library/pem.c
+ * library/ctr_drbg.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA
+ *
+ * PEM_PARSE uses AES for decrypting encrypted keys.
+ */
+#define MBEDTLS_AES_C
+
+/**
+ * \def MBEDTLS_ARC4_C
+ *
+ * Enable the ARCFOUR stream cipher.
+ *
+ * Module: library/arc4.c
+ * Caller: library/ssl_tls.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_RSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_RSA_WITH_RC4_128_MD5
+ * MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_PSK_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_ARC4_C
+
+/**
+ * \def MBEDTLS_ASN1_PARSE_C
+ *
+ * Enable the generic ASN1 parser.
+ *
+ * Module: library/asn1.c
+ * Caller: library/x509.c
+ * library/dhm.c
+ * library/pkcs12.c
+ * library/pkcs5.c
+ * library/pkparse.c
+ */
+#define MBEDTLS_ASN1_PARSE_C
+
+/**
+ * \def MBEDTLS_ASN1_WRITE_C
+ *
+ * Enable the generic ASN1 writer.
+ *
+ * Module: library/asn1write.c
+ * Caller: library/ecdsa.c
+ * library/pkwrite.c
+ * library/x509_create.c
+ * library/x509write_crt.c
+ * library/x509write_csr.c
+ */
+#define MBEDTLS_ASN1_WRITE_C
+
+/**
+ * \def MBEDTLS_BASE64_C
+ *
+ * Enable the Base64 module.
+ *
+ * Module: library/base64.c
+ * Caller: library/pem.c
+ *
+ * This module is required for PEM support (required by X.509).
+ */
+#define MBEDTLS_BASE64_C
+
+/**
+ * \def MBEDTLS_BIGNUM_C
+ *
+ * Enable the multi-precision integer library.
+ *
+ * Module: library/bignum.c
+ * Caller: library/dhm.c
+ * library/ecp.c
+ * library/ecdsa.c
+ * library/rsa.c
+ * library/ssl_tls.c
+ *
+ * This module is required for RSA, DHM and ECC (ECDH, ECDSA) support.
+ */
+#define MBEDTLS_BIGNUM_C
+
+/**
+ * \def MBEDTLS_BLOWFISH_C
+ *
+ * Enable the Blowfish block cipher.
+ *
+ * Module: library/blowfish.c
+ */
+#define MBEDTLS_BLOWFISH_C
+
+/**
+ * \def MBEDTLS_CAMELLIA_C
+ *
+ * Enable the Camellia block cipher.
+ *
+ * Module: library/camellia.c
+ * Caller: library/ssl_tls.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ */
+#define MBEDTLS_CAMELLIA_C
+
+/**
+ * \def MBEDTLS_CCM_C
+ *
+ * Enable the Counter with CBC-MAC (CCM) mode for 128-bit block cipher.
+ *
+ * Module: library/ccm.c
+ *
+ * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C
+ *
+ * This module enables the AES-CCM ciphersuites, if other requisites are
+ * enabled as well.
+ */
+#define MBEDTLS_CCM_C
+
+/**
+ * \def MBEDTLS_CERTS_C
+ *
+ * Enable the test certificates.
+ *
+ * Module: library/certs.c
+ * Caller:
+ *
+ * This module is used for testing (ssl_client/server).
+ */
+#define MBEDTLS_CERTS_C
+
+/**
+ * \def MBEDTLS_CIPHER_C
+ *
+ * Enable the generic cipher layer.
+ *
+ * Module: library/cipher.c
+ * Caller: library/ssl_tls.c
+ *
+ * Uncomment to enable generic cipher wrappers.
+ */
+#define MBEDTLS_CIPHER_C
+
+/**
+ * \def MBEDTLS_CMAC_C
+ *
+ * Enable the CMAC (Cipher-based Message Authentication Code) mode for block
+ * ciphers.
+ *
+ * Module: library/cmac.c
+ *
+ * Requires: MBEDTLS_AES_C or MBEDTLS_DES_C
+ *
+ */
+//#define MBEDTLS_CMAC_C
+
+/**
+ * \def MBEDTLS_CTR_DRBG_C
+ *
+ * Enable the CTR_DRBG AES-256-based random generator.
+ *
+ * Module: library/ctr_drbg.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_AES_C
+ *
+ * This module provides the CTR_DRBG AES-256 random number generator.
+ */
+#define MBEDTLS_CTR_DRBG_C
+
+/**
+ * \def MBEDTLS_DEBUG_C
+ *
+ * Enable the debug functions.
+ *
+ * Module: library/debug.c
+ * Caller: library/ssl_cli.c
+ * library/ssl_srv.c
+ * library/ssl_tls.c
+ *
+ * This module provides debugging functions.
+ */
+#define MBEDTLS_DEBUG_C
+
+/**
+ * \def MBEDTLS_DES_C
+ *
+ * Enable the DES block cipher.
+ *
+ * Module: library/des.c
+ * Caller: library/pem.c
+ * library/ssl_tls.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA
+ *
+ * PEM_PARSE uses DES/3DES for decrypting encrypted keys.
+ */
+#define MBEDTLS_DES_C
+
+/**
+ * \def MBEDTLS_DHM_C
+ *
+ * Enable the Diffie-Hellman-Merkle module.
+ *
+ * Module: library/dhm.c
+ * Caller: library/ssl_cli.c
+ * library/ssl_srv.c
+ *
+ * This module is used by the following key exchanges:
+ * DHE-RSA, DHE-PSK
+ */
+#define MBEDTLS_DHM_C
+
+/**
+ * \def MBEDTLS_ECDH_C
+ *
+ * Enable the elliptic curve Diffie-Hellman library.
+ *
+ * Module: library/ecdh.c
+ * Caller: library/ssl_cli.c
+ * library/ssl_srv.c
+ *
+ * This module is used by the following key exchanges:
+ * ECDHE-ECDSA, ECDHE-RSA, DHE-PSK
+ *
+ * Requires: MBEDTLS_ECP_C
+ */
+#define MBEDTLS_ECDH_C
+
+/**
+ * \def MBEDTLS_ECDSA_C
+ *
+ * Enable the elliptic curve DSA library.
+ *
+ * Module: library/ecdsa.c
+ * Caller:
+ *
+ * This module is used by the following key exchanges:
+ * ECDHE-ECDSA
+ *
+ * Requires: MBEDTLS_ECP_C, MBEDTLS_ASN1_WRITE_C, MBEDTLS_ASN1_PARSE_C
+ */
+#define MBEDTLS_ECDSA_C
+
+/**
+ * \def MBEDTLS_ECJPAKE_C
+ *
+ * Enable the elliptic curve J-PAKE library.
+ *
+ * \warning This is currently experimental. EC J-PAKE support is based on the
+ * Thread v1.0.0 specification; incompatible changes to the specification
+ * might still happen. For this reason, this is disabled by default.
+ *
+ * Module: library/ecjpake.c
+ * Caller:
+ *
+ * This module is used by the following key exchanges:
+ * ECJPAKE
+ *
+ * Requires: MBEDTLS_ECP_C, MBEDTLS_MD_C
+ */
+//#define MBEDTLS_ECJPAKE_C
+
+/**
+ * \def MBEDTLS_ECP_C
+ *
+ * Enable the elliptic curve over GF(p) library.
+ *
+ * Module: library/ecp.c
+ * Caller: library/ecdh.c
+ * library/ecdsa.c
+ * library/ecjpake.c
+ *
+ * Requires: MBEDTLS_BIGNUM_C and at least one MBEDTLS_ECP_DP_XXX_ENABLED
+ */
+#define MBEDTLS_ECP_C
+
+/**
+ * \def MBEDTLS_ENTROPY_C
+ *
+ * Enable the platform-specific entropy code.
+ *
+ * Module: library/entropy.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SHA512_C or MBEDTLS_SHA256_C
+ *
+ * This module provides a generic entropy pool
+ */
+#define MBEDTLS_ENTROPY_C
+
+/**
+ * \def MBEDTLS_ERROR_C
+ *
+ * Enable error code to error string conversion.
+ *
+ * Module: library/error.c
+ * Caller:
+ *
+ * This module enables mbedtls_strerror().
+ */
+#define MBEDTLS_ERROR_C
+
+/**
+ * \def MBEDTLS_GCM_C
+ *
+ * Enable the Galois/Counter Mode (GCM) for AES.
+ *
+ * Module: library/gcm.c
+ *
+ * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C
+ *
+ * This module enables the AES-GCM and CAMELLIA-GCM ciphersuites, if other
+ * requisites are enabled as well.
+ */
+#define MBEDTLS_GCM_C
+
+/**
+ * \def MBEDTLS_HAVEGE_C
+ *
+ * Enable the HAVEGE random generator.
+ *
+ * Warning: the HAVEGE random generator is not suitable for virtualized
+ * environments
+ *
+ * Warning: the HAVEGE random generator is dependent on timing and specific
+ * processor traits. It is therefore not advised to use HAVEGE as
+ * your applications primary random generator or primary entropy pool
+ * input. As a secondary input to your entropy pool, it IS able add
+ * the (limited) extra entropy it provides.
+ *
+ * Module: library/havege.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_TIMING_C
+ *
+ * Uncomment to enable the HAVEGE random generator.
+ */
+//#define MBEDTLS_HAVEGE_C
+
+/**
+ * \def MBEDTLS_HMAC_DRBG_C
+ *
+ * Enable the HMAC_DRBG random generator.
+ *
+ * Module: library/hmac_drbg.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_MD_C
+ *
+ * Uncomment to enable the HMAC_DRBG random number geerator.
+ */
+#define MBEDTLS_HMAC_DRBG_C
+
+/**
+ * \def MBEDTLS_MD_C
+ *
+ * Enable the generic message digest layer.
+ *
+ * Module: library/md.c
+ * Caller:
+ *
+ * Uncomment to enable generic message digest wrappers.
+ */
+#define MBEDTLS_MD_C
+
+/**
+ * \def MBEDTLS_MD2_C
+ *
+ * Enable the MD2 hash algorithm.
+ *
+ * Module: library/md2.c
+ * Caller:
+ *
+ * Uncomment to enable support for (rare) MD2-signed X.509 certs.
+ */
+//#define MBEDTLS_MD2_C
+
+/**
+ * \def MBEDTLS_MD4_C
+ *
+ * Enable the MD4 hash algorithm.
+ *
+ * Module: library/md4.c
+ * Caller:
+ *
+ * Uncomment to enable support for (rare) MD4-signed X.509 certs.
+ */
+//#define MBEDTLS_MD4_C
+
+/**
+ * \def MBEDTLS_MD5_C
+ *
+ * Enable the MD5 hash algorithm.
+ *
+ * Module: library/md5.c
+ * Caller: library/md.c
+ * library/pem.c
+ * library/ssl_tls.c
+ *
+ * This module is required for SSL/TLS and X.509.
+ * PEM_PARSE uses MD5 for decrypting encrypted keys.
+ */
+#define MBEDTLS_MD5_C
+
+/**
+ * \def MBEDTLS_MEMORY_BUFFER_ALLOC_C
+ *
+ * Enable the buffer allocator implementation that makes use of a (stack)
+ * based buffer to 'allocate' dynamic memory. (replaces calloc() and free()
+ * calls)
+ *
+ * Module: library/memory_buffer_alloc.c
+ *
+ * Requires: MBEDTLS_PLATFORM_C
+ * MBEDTLS_PLATFORM_MEMORY (to use it within mbed TLS)
+ *
+ * Enable this module to enable the buffer memory allocator.
+ */
+#define MBEDTLS_MEMORY_BUFFER_ALLOC_C
+
+/**
+ * \def MBEDTLS_NET_C
+ *
+ * Enable the TCP and UDP over IPv6/IPv4 networking routines.
+ *
+ * \note This module only works on POSIX/Unix (including Linux, BSD and OS X)
+ * and Windows. For other platforms, you'll want to disable it, and write your
+ * own networking callbacks to be passed to \c mbedtls_ssl_set_bio().
+ *
+ * \note See also our Knowledge Base article about porting to a new
+ * environment:
+ * https://tls.mbed.org/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS
+ *
+ * Module: library/net_sockets.c
+ *
+ * This module provides networking routines.
+ */
+//#define MBEDTLS_NET_C
+
+/**
+ * \def MBEDTLS_OID_C
+ *
+ * Enable the OID database.
+ *
+ * Module: library/oid.c
+ * Caller: library/asn1write.c
+ * library/pkcs5.c
+ * library/pkparse.c
+ * library/pkwrite.c
+ * library/rsa.c
+ * library/x509.c
+ * library/x509_create.c
+ * library/x509_crl.c
+ * library/x509_crt.c
+ * library/x509_csr.c
+ * library/x509write_crt.c
+ * library/x509write_csr.c
+ *
+ * This modules translates between OIDs and internal values.
+ */
+#define MBEDTLS_OID_C
+
+/**
+ * \def MBEDTLS_PADLOCK_C
+ *
+ * Enable VIA Padlock support on x86.
+ *
+ * Module: library/padlock.c
+ * Caller: library/aes.c
+ *
+ * Requires: MBEDTLS_HAVE_ASM
+ *
+ * This modules adds support for the VIA PadLock on x86.
+ */
+#define MBEDTLS_PADLOCK_C
+
+/**
+ * \def MBEDTLS_PEM_PARSE_C
+ *
+ * Enable PEM decoding / parsing.
+ *
+ * Module: library/pem.c
+ * Caller: library/dhm.c
+ * library/pkparse.c
+ * library/x509_crl.c
+ * library/x509_crt.c
+ * library/x509_csr.c
+ *
+ * Requires: MBEDTLS_BASE64_C
+ *
+ * This modules adds support for decoding / parsing PEM files.
+ */
+#define MBEDTLS_PEM_PARSE_C
+
+/**
+ * \def MBEDTLS_PEM_WRITE_C
+ *
+ * Enable PEM encoding / writing.
+ *
+ * Module: library/pem.c
+ * Caller: library/pkwrite.c
+ * library/x509write_crt.c
+ * library/x509write_csr.c
+ *
+ * Requires: MBEDTLS_BASE64_C
+ *
+ * This modules adds support for encoding / writing PEM files.
+ */
+#define MBEDTLS_PEM_WRITE_C
+
+/**
+ * \def MBEDTLS_PK_C
+ *
+ * Enable the generic public (asymetric) key layer.
+ *
+ * Module: library/pk.c
+ * Caller: library/ssl_tls.c
+ * library/ssl_cli.c
+ * library/ssl_srv.c
+ *
+ * Requires: MBEDTLS_RSA_C or MBEDTLS_ECP_C
+ *
+ * Uncomment to enable generic public key wrappers.
+ */
+#define MBEDTLS_PK_C
+
+/**
+ * \def MBEDTLS_PK_PARSE_C
+ *
+ * Enable the generic public (asymetric) key parser.
+ *
+ * Module: library/pkparse.c
+ * Caller: library/x509_crt.c
+ * library/x509_csr.c
+ *
+ * Requires: MBEDTLS_PK_C
+ *
+ * Uncomment to enable generic public key parse functions.
+ */
+#define MBEDTLS_PK_PARSE_C
+
+/**
+ * \def MBEDTLS_PK_WRITE_C
+ *
+ * Enable the generic public (asymetric) key writer.
+ *
+ * Module: library/pkwrite.c
+ * Caller: library/x509write.c
+ *
+ * Requires: MBEDTLS_PK_C
+ *
+ * Uncomment to enable generic public key write functions.
+ */
+#define MBEDTLS_PK_WRITE_C
+
+/**
+ * \def MBEDTLS_PKCS5_C
+ *
+ * Enable PKCS#5 functions.
+ *
+ * Module: library/pkcs5.c
+ *
+ * Requires: MBEDTLS_MD_C
+ *
+ * This module adds support for the PKCS#5 functions.
+ */
+#define MBEDTLS_PKCS5_C
+
+/**
+ * \def MBEDTLS_PKCS11_C
+ *
+ * Enable wrapper for PKCS#11 smartcard support.
+ *
+ * Module: library/pkcs11.c
+ * Caller: library/pk.c
+ *
+ * Requires: MBEDTLS_PK_C
+ *
+ * This module enables SSL/TLS PKCS #11 smartcard support.
+ * Requires the presence of the PKCS#11 helper library (libpkcs11-helper)
+ */
+//#define MBEDTLS_PKCS11_C
+
+/**
+ * \def MBEDTLS_PKCS12_C
+ *
+ * Enable PKCS#12 PBE functions.
+ * Adds algorithms for parsing PKCS#8 encrypted private keys
+ *
+ * Module: library/pkcs12.c
+ * Caller: library/pkparse.c
+ *
+ * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_CIPHER_C, MBEDTLS_MD_C
+ * Can use: MBEDTLS_ARC4_C
+ *
+ * This module enables PKCS#12 functions.
+ */
+#define MBEDTLS_PKCS12_C
+
+/**
+ * \def MBEDTLS_PLATFORM_C
+ *
+ * Enable the platform abstraction layer that allows you to re-assign
+ * functions like calloc(), free(), snprintf(), printf(), fprintf(), exit().
+ *
+ * Enabling MBEDTLS_PLATFORM_C enables to use of MBEDTLS_PLATFORM_XXX_ALT
+ * or MBEDTLS_PLATFORM_XXX_MACRO directives, allowing the functions mentioned
+ * above to be specified at runtime or compile time respectively.
+ *
+ * \note This abstraction layer must be enabled on Windows (including MSYS2)
+ * as other module rely on it for a fixed snprintf implementation.
+ *
+ * Module: library/platform.c
+ * Caller: Most other .c files
+ *
+ * This module enables abstraction of common (libc) functions.
+ */
+#define MBEDTLS_PLATFORM_C
+
+/**
+ * \def MBEDTLS_RIPEMD160_C
+ *
+ * Enable the RIPEMD-160 hash algorithm.
+ *
+ * Module: library/ripemd160.c
+ * Caller: library/md.c
+ *
+ */
+#define MBEDTLS_RIPEMD160_C
+
+/**
+ * \def MBEDTLS_RSA_C
+ *
+ * Enable the RSA public-key cryptosystem.
+ *
+ * Module: library/rsa.c
+ * Caller: library/ssl_cli.c
+ * library/ssl_srv.c
+ * library/ssl_tls.c
+ * library/x509.c
+ *
+ * This module is used by the following key exchanges:
+ * RSA, DHE-RSA, ECDHE-RSA, RSA-PSK
+ *
+ * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C
+ */
+#define MBEDTLS_RSA_C
+
+/**
+ * \def MBEDTLS_SHA1_C
+ *
+ * Enable the SHA1 cryptographic hash algorithm.
+ *
+ * Module: library/sha1.c
+ * Caller: library/md.c
+ * library/ssl_cli.c
+ * library/ssl_srv.c
+ * library/ssl_tls.c
+ * library/x509write_crt.c
+ *
+ * This module is required for SSL/TLS up to version 1.1, for TLS 1.2
+ * depending on the handshake parameters, and for SHA1-signed certificates.
+ */
+#define MBEDTLS_SHA1_C
+
+/**
+ * \def MBEDTLS_SHA256_C
+ *
+ * Enable the SHA-224 and SHA-256 cryptographic hash algorithms.
+ *
+ * Module: library/sha256.c
+ * Caller: library/entropy.c
+ * library/md.c
+ * library/ssl_cli.c
+ * library/ssl_srv.c
+ * library/ssl_tls.c
+ *
+ * This module adds support for SHA-224 and SHA-256.
+ * This module is required for the SSL/TLS 1.2 PRF function.
+ */
+#define MBEDTLS_SHA256_C
+
+/**
+ * \def MBEDTLS_SHA512_C
+ *
+ * Enable the SHA-384 and SHA-512 cryptographic hash algorithms.
+ *
+ * Module: library/sha512.c
+ * Caller: library/entropy.c
+ * library/md.c
+ * library/ssl_cli.c
+ * library/ssl_srv.c
+ *
+ * This module adds support for SHA-384 and SHA-512.
+ */
+#define MBEDTLS_SHA512_C
+
+/**
+ * \def MBEDTLS_SSL_CACHE_C
+ *
+ * Enable simple SSL cache implementation.
+ *
+ * Module: library/ssl_cache.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SSL_CACHE_C
+ */
+#define MBEDTLS_SSL_CACHE_C
+
+/**
+ * \def MBEDTLS_SSL_COOKIE_C
+ *
+ * Enable basic implementation of DTLS cookies for hello verification.
+ *
+ * Module: library/ssl_cookie.c
+ * Caller:
+ */
+#define MBEDTLS_SSL_COOKIE_C
+
+/**
+ * \def MBEDTLS_SSL_TICKET_C
+ *
+ * Enable an implementation of TLS server-side callbacks for session tickets.
+ *
+ * Module: library/ssl_ticket.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_CIPHER_C
+ */
+#define MBEDTLS_SSL_TICKET_C
+
+/**
+ * \def MBEDTLS_SSL_CLI_C
+ *
+ * Enable the SSL/TLS client code.
+ *
+ * Module: library/ssl_cli.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SSL_TLS_C
+ *
+ * This module is required for SSL/TLS client support.
+ */
+#define MBEDTLS_SSL_CLI_C
+
+/**
+ * \def MBEDTLS_SSL_SRV_C
+ *
+ * Enable the SSL/TLS server code.
+ *
+ * Module: library/ssl_srv.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SSL_TLS_C
+ *
+ * This module is required for SSL/TLS server support.
+ */
+#define MBEDTLS_SSL_SRV_C
+
+/**
+ * \def MBEDTLS_SSL_TLS_C
+ *
+ * Enable the generic SSL/TLS code.
+ *
+ * Module: library/ssl_tls.c
+ * Caller: library/ssl_cli.c
+ * library/ssl_srv.c
+ *
+ * Requires: MBEDTLS_CIPHER_C, MBEDTLS_MD_C
+ * and at least one of the MBEDTLS_SSL_PROTO_XXX defines
+ *
+ * This module is required for SSL/TLS.
+ */
+#define MBEDTLS_SSL_TLS_C
+
+/**
+ * \def MBEDTLS_THREADING_C
+ *
+ * Enable the threading abstraction layer.
+ * By default mbed TLS assumes it is used in a non-threaded environment or that
+ * contexts are not shared between threads. If you do intend to use contexts
+ * between threads, you will need to enable this layer to prevent race
+ * conditions. See also our Knowledge Base article about threading:
+ * https://tls.mbed.org/kb/development/thread-safety-and-multi-threading
+ *
+ * Module: library/threading.c
+ *
+ * This allows different threading implementations (self-implemented or
+ * provided).
+ *
+ * You will have to enable either MBEDTLS_THREADING_ALT or
+ * MBEDTLS_THREADING_PTHREAD.
+ *
+ * Enable this layer to allow use of mutexes within mbed TLS
+ */
+//#define MBEDTLS_THREADING_C
+
+/**
+ * \def MBEDTLS_TIMING_C
+ *
+ * Enable the semi-portable timing interface.
+ *
+ * \note The provided implementation only works on POSIX/Unix (including Linux,
+ * BSD and OS X) and Windows. On other platforms, you can either disable that
+ * module and provide your own implementations of the callbacks needed by
+ * \c mbedtls_ssl_set_timer_cb() for DTLS, or leave it enabled and provide
+ * your own implementation of the whole module by setting
+ * \c MBEDTLS_TIMING_ALT in the current file.
+ *
+ * \note See also our Knowledge Base article about porting to a new
+ * environment:
+ * https://tls.mbed.org/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS
+ *
+ * Module: library/timing.c
+ * Caller: library/havege.c
+ *
+ * This module is used by the HAVEGE random number generator.
+ */
+//#define MBEDTLS_TIMING_C
+
+/**
+ * \def MBEDTLS_VERSION_C
+ *
+ * Enable run-time version information.
+ *
+ * Module: library/version.c
+ *
+ * This module provides run-time version information.
+ */
+#define MBEDTLS_VERSION_C
+
+/**
+ * \def MBEDTLS_X509_USE_C
+ *
+ * Enable X.509 core for using certificates.
+ *
+ * Module: library/x509.c
+ * Caller: library/x509_crl.c
+ * library/x509_crt.c
+ * library/x509_csr.c
+ *
+ * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_BIGNUM_C, MBEDTLS_OID_C,
+ * MBEDTLS_PK_PARSE_C
+ *
+ * This module is required for the X.509 parsing modules.
+ */
+#define MBEDTLS_X509_USE_C
+
+/**
+ * \def MBEDTLS_X509_CRT_PARSE_C
+ *
+ * Enable X.509 certificate parsing.
+ *
+ * Module: library/x509_crt.c
+ * Caller: library/ssl_cli.c
+ * library/ssl_srv.c
+ * library/ssl_tls.c
+ *
+ * Requires: MBEDTLS_X509_USE_C
+ *
+ * This module is required for X.509 certificate parsing.
+ */
+#define MBEDTLS_X509_CRT_PARSE_C
+
+/**
+ * \def MBEDTLS_X509_CRL_PARSE_C
+ *
+ * Enable X.509 CRL parsing.
+ *
+ * Module: library/x509_crl.c
+ * Caller: library/x509_crt.c
+ *
+ * Requires: MBEDTLS_X509_USE_C
+ *
+ * This module is required for X.509 CRL parsing.
+ */
+#define MBEDTLS_X509_CRL_PARSE_C
+
+/**
+ * \def MBEDTLS_X509_CSR_PARSE_C
+ *
+ * Enable X.509 Certificate Signing Request (CSR) parsing.
+ *
+ * Module: library/x509_csr.c
+ * Caller: library/x509_crt_write.c
+ *
+ * Requires: MBEDTLS_X509_USE_C
+ *
+ * This module is used for reading X.509 certificate request.
+ */
+#define MBEDTLS_X509_CSR_PARSE_C
+
+/**
+ * \def MBEDTLS_X509_CREATE_C
+ *
+ * Enable X.509 core for creating certificates.
+ *
+ * Module: library/x509_create.c
+ *
+ * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, MBEDTLS_PK_WRITE_C
+ *
+ * This module is the basis for creating X.509 certificates and CSRs.
+ */
+#define MBEDTLS_X509_CREATE_C
+
+/**
+ * \def MBEDTLS_X509_CRT_WRITE_C
+ *
+ * Enable creating X.509 certificates.
+ *
+ * Module: library/x509_crt_write.c
+ *
+ * Requires: MBEDTLS_X509_CREATE_C
+ *
+ * This module is required for X.509 certificate creation.
+ */
+#define MBEDTLS_X509_CRT_WRITE_C
+
+/**
+ * \def MBEDTLS_X509_CSR_WRITE_C
+ *
+ * Enable creating X.509 Certificate Signing Requests (CSR).
+ *
+ * Module: library/x509_csr_write.c
+ *
+ * Requires: MBEDTLS_X509_CREATE_C
+ *
+ * This module is required for X.509 certificate request writing.
+ */
+#define MBEDTLS_X509_CSR_WRITE_C
+
+/**
+ * \def MBEDTLS_XTEA_C
+ *
+ * Enable the XTEA block cipher.
+ *
+ * Module: library/xtea.c
+ * Caller:
+ */
+#define MBEDTLS_XTEA_C
+
+/* \} name SECTION: mbed TLS modules */
+
+/**
+ * \name SECTION: Module configuration options
+ *
+ * This section allows for the setting of module specific sizes and
+ * configuration options. The default values are already present in the
+ * relevant header files and should suffice for the regular use cases.
+ *
+ * Our advice is to enable options and change their values here
+ * only if you have a good reason and know the consequences.
+ *
+ * Please check the respective header file for documentation on these
+ * parameters (to prevent duplicate documentation).
+ * \{
+ */
+
+/* MPI / BIGNUM options */
+//#define MBEDTLS_MPI_WINDOW_SIZE 6 /**< Maximum windows size used. */
+//#define MBEDTLS_MPI_MAX_SIZE 1024 /**< Maximum number of bytes for usable MPIs. */
+
+/* CTR_DRBG options */
+//#define MBEDTLS_CTR_DRBG_ENTROPY_LEN 48 /**< Amount of entropy used per seed by default (48 with SHA-512, 32 with SHA-256) */
+//#define MBEDTLS_CTR_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */
+//#define MBEDTLS_CTR_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */
+//#define MBEDTLS_CTR_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */
+//#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */
+
+/* HMAC_DRBG options */
+//#define MBEDTLS_HMAC_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */
+//#define MBEDTLS_HMAC_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */
+//#define MBEDTLS_HMAC_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */
+//#define MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */
+
+/* ECP options */
+//#define MBEDTLS_ECP_MAX_BITS 521 /**< Maximum bit size of groups */
+//#define MBEDTLS_ECP_WINDOW_SIZE 6 /**< Maximum window size used */
+//#define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up */
+
+/* Entropy options */
+//#define MBEDTLS_ENTROPY_MAX_SOURCES 20 /**< Maximum number of sources supported */
+//#define MBEDTLS_ENTROPY_MAX_GATHER 128 /**< Maximum amount requested from entropy sources */
+//#define MBEDTLS_ENTROPY_MIN_HARDWARE 32 /**< Default minimum number of bytes required for the hardware entropy source mbedtls_hardware_poll() before entropy is released */
+
+/* Memory buffer allocator options */
+//#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 4 /**< Align on multiples of this value */
+
+/* Platform options */
+//#define MBEDTLS_PLATFORM_STD_MEM_HDR <stdlib.h> /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */
+//#define MBEDTLS_PLATFORM_STD_CALLOC calloc /**< Default allocator to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_FREE free /**< Default free to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_EXIT exit /**< Default exit to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */
+//#define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */
+/* Note: your snprintf must correclty zero-terminate the buffer! */
+//#define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< Default snprintf to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file to read/write with default implementation */
+
+/* To Use Function Macros MBEDTLS_PLATFORM_C must be enabled */
+/* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */
+//#define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_FREE_MACRO free /**< Default free macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_EXIT_MACRO exit /**< Default exit macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_TIME_MACRO time /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */
+//#define MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */
+//#define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf /**< Default fprintf macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be undefined */
+/* Note: your snprintf must correclty zero-terminate the buffer! */
+//#define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */
+//#define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */
+
+/* SSL Cache options */
+//#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */
+//#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */
+
+/* SSL options */
+//#define MBEDTLS_SSL_MAX_CONTENT_LEN 16384 /**< Maxium fragment length in bytes, determines the size of each of the two internal I/O buffers */
+//#define MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME 86400 /**< Lifetime of session tickets (if enabled) */
+//#define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 bits) */
+//#define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */
+
+/**
+ * Complete list of ciphersuites to use, in order of preference.
+ *
+ * \warning No dependency checking is done on that field! This option can only
+ * be used to restrict the set of available ciphersuites. It is your
+ * responsibility to make sure the needed modules are active.
+ *
+ * Use this to save a few hundred bytes of ROM (default ordering of all
+ * available ciphersuites) and a few to a few hundred bytes of RAM.
+ *
+ * The value below is only an example, not the default.
+ */
+//#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+
+/* X509 options */
+//#define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 /**< Maximum number of intermediate CAs in a verification chain. */
+//#define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in bytes including the null terminator character ('\0'). */
+
+/**
+ * Allow SHA-1 in the default TLS configuration for certificate signing.
+ * Without this build-time option, SHA-1 support must be activated explicitly
+ * through mbedtls_ssl_conf_cert_profile. Turning on this option is not
+ * recommended because of it is possible to generte SHA-1 collisions, however
+ * this may be safe for legacy infrastructure where additional controls apply.
+ */
+// #define MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_CERTIFICATES
+
+/**
+ * Allow SHA-1 in the default TLS configuration for TLS 1.2 handshake
+ * signature and ciphersuite selection. Without this build-time option, SHA-1
+ * support must be activated explicitly through mbedtls_ssl_conf_sig_hashes.
+ * The use of SHA-1 in TLS <= 1.1 and in HMAC-SHA-1 is always allowed by
+ * default. At the time of writing, there is no practical attack on the use
+ * of SHA-1 in handshake signatures, hence this option is turned on by default
+ * for compatibility with existing peers.
+ */
+#define MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_KEY_EXCHANGE
+
+/* \} name SECTION: Customisation configuration options */
+
+/* Target and application specific configurations */
+//#define YOTTA_CFG_MBEDTLS_TARGET_CONFIG_FILE "mbedtls/target_config.h"
+
+#if defined(TARGET_LIKE_MBED) && defined(YOTTA_CFG_MBEDTLS_TARGET_CONFIG_FILE)
+#include YOTTA_CFG_MBEDTLS_TARGET_CONFIG_FILE
+#endif
+
+/*
+ * Allow user to override any previous default.
+ *
+ * Use two macro names for that, as:
+ * - with yotta the prefix YOTTA_CFG_ is forced
+ * - without yotta is looks weird to have a YOTTA prefix.
+ */
+#if defined(YOTTA_CFG_MBEDTLS_USER_CONFIG_FILE)
+#include YOTTA_CFG_MBEDTLS_USER_CONFIG_FILE
+#elif defined(MBEDTLS_USER_CONFIG_FILE)
+#include MBEDTLS_USER_CONFIG_FILE
+#endif
+
+#endif /* MBEDTLS_CONFIG_H */
diff --git a/platform/ext/target/common/uart_stdout.c b/platform/ext/target/common/uart_stdout.c
new file mode 100644
index 0000000..3dd3b02
--- /dev/null
+++ b/platform/ext/target/common/uart_stdout.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apace License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apace.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "uart_stdout.h"
+
+#include <assert.h>
+#include <stdio.h>
+#include <string.h>
+#include "arm_uart_drv.h"
+#include "Driver_USART.h"
+
+#define ASSERT_HIGH(X) assert(X == ARM_DRIVER_OK)
+
+/* Imports USART driver */
+extern ARM_DRIVER_USART Driver_USART0;
+extern ARM_DRIVER_USART Driver_USART1;
+
+/* Struct FILE is implemented in stdio.h. Used to redirect printf to UART */
+FILE __stdout;
+
+/* Redirects printf to UART */
+__attribute__ ((weak)) int fputc(int ch, FILE *f) {
+ /* Send byte to USART */
+ uart_putc(ch);
+
+ /* Return character written */
+ return ch;
+}
+
+extern struct arm_uart_dev_t ARM_UART0_DEV_S, ARM_UART0_DEV_NS;
+extern struct arm_uart_dev_t ARM_UART1_DEV_S, ARM_UART1_DEV_NS;
+
+/* Generic driver to be configured and used */
+ARM_DRIVER_USART *Driver_USART = NULL;
+
+void uart_init(enum uart_channel uchan)
+{
+ int32_t ret = ARM_DRIVER_OK;
+
+ /* Add a configuration step for the UART channel to use, 0 or 1 */
+ switch(uchan) {
+ case UART0_CHANNEL:
+ /* UART0 is configured as a non-secure peripheral, so we wouldn't be
+ * able to access it using its secure alias. Ideally, we would want
+ * to use UART1 only from S side as it's a secure peripheral, but for
+ * simplicity, leave the option to use UART0 and use a workaround
+ */
+ memcpy(&ARM_UART0_DEV_S, &ARM_UART0_DEV_NS, sizeof(struct arm_uart_dev_t));
+ Driver_USART = &Driver_USART0;
+ break;
+ case UART1_CHANNEL:
+ Driver_USART = &Driver_USART1;
+ break;
+ default:
+ ret = ARM_DRIVER_ERROR;
+ }
+ ASSERT_HIGH(ret);
+
+ ret = Driver_USART->Initialize(NULL);
+ ASSERT_HIGH(ret);
+
+ ret = Driver_USART->Control(ARM_USART_MODE_ASYNCHRONOUS, 115200);
+ ASSERT_HIGH(ret);
+}
+
+void uart_putc(unsigned char c)
+{
+ int32_t ret = ARM_DRIVER_OK;
+
+ ret = Driver_USART->Send(&c, 1);
+ ASSERT_HIGH(ret);
+}
+
+unsigned char uart_getc(void)
+{
+ unsigned char c = 0;
+ int32_t ret = ARM_DRIVER_OK;
+
+ ret = Driver_USART->Receive(&c, 1);
+ ASSERT_HIGH(ret);
+
+ return c;
+}
diff --git a/platform/ext/target/common/uart_stdout.h b/platform/ext/target/common/uart_stdout.h
new file mode 100644
index 0000000..e9afe03
--- /dev/null
+++ b/platform/ext/target/common/uart_stdout.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __UART_STDOUT_H__
+#define __UART_STDOUT_H__
+
+#include <stdint.h>
+
+/**
+ * \brief UART channels that
+ * can be used from TFM
+ */
+enum uart_channel {
+ UART0_CHANNEL = 0,
+ UART1_CHANNEL,
+ UART_INVALID
+};
+
+/**
+ * \brief Initializes the UART.
+ *
+ * \param[in] uchan UART channel
+ * to use, 0 or 1.
+ */
+void uart_init(enum uart_channel uchan);
+
+/**
+ * \brief Puts a character in the UART.
+ *
+ * \param[in] ch Character to write.
+ */
+void uart_putc(unsigned char ch);
+
+/**
+ * \brief Gets a character from the UART.
+ *
+ * \return Character read from UART.
+ */
+unsigned char uart_getc(void);
+
+#endif /* __UART_STDOUT_H__ */
diff --git a/platform/ext/target/sse_200_mps2/cmsis_core/cmsis.h b/platform/ext/target/sse_200_mps2/cmsis_core/cmsis.h
new file mode 100644
index 0000000..f5dfea4
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/cmsis_core/cmsis.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MPS2_SSE_200_CMSIS_H__
+#define __MPS2_SSE_200_CMSIS_H__
+
+/* Corelink SSE 200 Core for MPS2 */
+#include "mps2_sse_200.h"
+
+#endif /*__MPS2_SSE_200_CMSIS_H__ */
diff --git a/platform/ext/target/sse_200_mps2/cmsis_core/mps2_sse_200.h b/platform/ext/target/sse_200_mps2/cmsis_core/mps2_sse_200.h
new file mode 100644
index 0000000..771fb95
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/cmsis_core/mps2_sse_200.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MPS2_SSE_200_H__
+#define __MPS2_SSE_200_H__
+
+#include "platform_irq.h" /* Platform IRQ numbers */
+
+/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
+#define __CM33_REV 0x0000U /* Core revision r0p1 */
+#define __MPU_PRESENT 1U /* MPU present */
+#define __SAUREGION_PRESENT 1U /* SAU regions present */
+#define __VTOR_PRESENT 1U /* VTOR present */
+#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 0U /* no FPU present */
+#define __DSP_PRESENT 0U /* no DSP extension present */
+
+#include <core_cm33.h> /* Processor and core peripherals */
+#include "system_cmsdk_mps2_sse_200.h" /* System Header */
+
+#include "platform_regs.h" /* Platform registers */
+#include "platform_retarget.h" /* Peripherals base addresses */
+
+#endif /* __MPS2_SSE_200_H__ */
diff --git a/platform/ext/target/sse_200_mps2/cmsis_core/platform_irq.h b/platform/ext/target/sse_200_mps2/cmsis_core/platform_irq.h
new file mode 100644
index 0000000..640f9fa
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/cmsis_core/platform_irq.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARM_LTD_SSE_200_IRQN_H__
+#define __ARM_LTD_SSE_200_IRQN_H__
+
+typedef enum _IRQn_Type {
+ NonMaskableInt_IRQn = -14, /* Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* Memory Management Interrupt */
+ BusFault_IRQn = -11, /* Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* Pend SV Interrupt */
+ SysTick_IRQn = -1, /* System Tick Interrupt */
+ NONSEC_WATCHDOG_RESET_IRQn = 0, /* Non-Secure Watchdog Reset
+ * Interrupt */
+ NONSEC_WATCHDOG_IRQn = 1, /* Non-Secure Watchdog Interrupt */
+ S32K_TIMER_IRQn = 2, /* S32K Timer Interrupt */
+ TIMER0_IRQn = 3, /* TIMER 0 Interrupt */
+ TIMER1_IRQn = 4, /* TIMER 1 Interrupt */
+ DUALTIMER_IRQn = 5, /* Dual Timer Interrupt */
+ MHU0_IRQn = 6, /* Message Handling Unit 0 */
+ MHU1_IRQn = 7, /* Message Handling Unit 1 */
+ MPC_IRQn = 9, /* MPC Combined (Secure) Interrupt */
+ PPC_IRQn = 10, /* PPC Combined (Secure) Interrupt */
+ MSC_IRQn = 11, /* MSC Combined (Secure) Interrput */
+ BRIDGE_ERROR_IRQn = 12, /* Bridge Error Combined
+ *(Secure) Interrupt */
+ INVALID_INSTR_CACHE_IRQn = 13, /* CPU Instruction Cache Invalidation
+ * Interrupt*/
+ SYS_PPU_IRQn = 15, /* SYS PPU */
+ CPU0_PPU_IRQn = 16, /* CPU0 PPU */
+ CPU1_PPU_IRQn = 17, /* CPU1 PPU */
+ CPU0_DBG_PPU_IRQn = 18, /* CPU0 DBG PPU */
+ CPU1_DBG_PPU_IRQn = 19, /* CPU1 DBG PPU */
+ CRYPT_PPU_IRQn = 20, /* CRYPT PPU */
+ RAM0_PPU_IRQn = 22, /* RAM0 PPU */
+ RAM1_PPU_IRQn = 23, /* RAM1 PPU */
+ RAM2_PPU_IRQn = 24, /* RAM2 PPU */
+ RAM3_PPU_IRQn = 25, /* RAM3 PPU */
+ DEBUG_PPU_IRQn = 26, /* DEBUG PPU */
+ CPU0_CTI_IRQn = 28, /* CPU0 CTI */
+ CPU1_CTI_IRQn = 29, /* CPU1 CTI */
+ CORDIOTXCOMB_IRQn = 30, /* CORDIO TX combined */
+ CORDIORXCOMB_IRQn = 31, /* CORDIO RX combined */
+ UARTRX0_IRQn = 32, /* UART 0 RX Interrupt */
+ UARTTX0_IRQn = 33, /* UART 0 TX Interrupt */
+ UARTRX1_IRQn = 34, /* UART 1 RX Interrupt */
+ UARTTX1_IRQn = 35, /* UART 1 TX Interrupt */
+ UARTRX2_IRQn = 36, /* UART 2 RX Interrupt */
+ UARTTX2_IRQn = 37, /* UART 2 TX Interrupt */
+ UARTRX3_IRQn = 38, /* UART 3 RX Interrupt */
+ UARTTX3_IRQn = 39, /* UART 3 TX Interrupt */
+ UARTRX4_IRQn = 40, /* UART 4 RX Interrupt */
+ UARTTX4_IRQn = 41, /* UART 4 TX Interrupt */
+ UART0_IRQn = 42, /* UART 0 combined Interrupt */
+ UART1_IRQn = 43, /* UART 1 combined Interrupt */
+ UART2_IRQn = 44, /* UART 2 combined Interrupt */
+ UART3_IRQn = 45, /* UART 3 combined Interrupt */
+ UART4_IRQn = 46, /* UART 4 combined Interrupt */
+ UARTOVF_IRQn = 47, /* UART Overflow (0, 1, 2, 3 & 4) */
+ ETHERNET_IRQn = 48, /* Ethernet Interrupt */
+ I2S_IRQn = 49, /* Audio I2S Interrupt */
+ TSC_IRQn = 50, /* Touch Screen Interrupt */
+ SPI0_IRQn = 51, /* SPI 0 Interrupt */
+ SPI1_IRQn = 52, /* SPI 1 Interrupt */
+ SPI2_IRQn = 53, /* SPI 2 Interrupt */
+ SPI3_IRQn = 54, /* SPI 3 Interrupt */
+ SPI4_IRQn = 55, /* SPI 4 Interrupt */
+ DMA0_ERROR_IRQn = 56, /* DMA 0 Error Interrupt */
+ DMA0_TC_IRQn = 57, /* DMA 0 Terminal Count Interrupt */
+ DMA0_IRQn = 58, /* DMA 0 Combined Interrupt */
+ DMA1_ERROR_IRQn = 59, /* DMA 1 Error Interrupt */
+ DMA1_TC_IRQn = 60, /* DMA 1 Terminal Count Interrupt */
+ DMA1_IRQn = 61, /* DMA 1 Combined Interrupt */
+ DMA2_ERROR_IRQn = 62, /* DMA 2 Error Interrupt */
+ DMA2_TC_IRQn = 63, /* DMA 2 Terminal Count Interrupt */
+ DMA2_IRQn = 64, /* DMA 2 Combined Interrupt */
+ DMA3_ERROR_IRQn = 65, /* DMA 3 Error Interrupt */
+ DMA3_TC_IRQn = 66, /* DMA 3 Terminal Count Interrupt */
+ DMA3_IRQn = 67, /* DMA 3 Combined Interrupt */
+ GPIO0_IRQn = 68, /* GPIO 0 Combined Interrupt */
+ GPIO1_IRQn = 69, /* GPIO 1 Combined Interrupt */
+ GPIO2_IRQn = 70, /* GPIO 2 Combined Interrupt */
+ GPIO3_IRQn = 71, /* GPIO 3 Combined Interrupt */
+ GPIO0_0_IRQn = 72, /* GPIO0 has 16 pins with IRQs */
+ GPIO0_1_IRQn = 73,
+ GPIO0_2_IRQn = 74,
+ GPIO0_3_IRQn = 75,
+ GPIO0_4_IRQn = 76,
+ GPIO0_5_IRQn = 77,
+ GPIO0_6_IRQn = 78,
+ GPIO0_7_IRQn = 79,
+ GPIO0_8_IRQn = 80,
+ GPIO0_9_IRQn = 81,
+ GPIO0_10_IRQn = 82,
+ GPIO0_11_IRQn = 83,
+ GPIO0_12_IRQn = 84,
+ GPIO0_13_IRQn = 85,
+ GPIO0_14_IRQn = 86,
+ GPIO0_15_IRQn = 87,
+ GPIO1_0_IRQn = 88, /* GPIO1 has 16 pins with IRQs */
+ GPIO1_1_IRQn = 89,
+ GPIO1_2_IRQn = 90,
+ GPIO1_3_IRQn = 91,
+ GPIO1_4_IRQn = 92,
+ GPIO1_5_IRQn = 93,
+ GPIO1_6_IRQn = 94,
+ GPIO1_7_IRQn = 95,
+ GPIO1_8_IRQn = 96,
+ GPIO1_9_IRQn = 97,
+ GPIO1_10_IRQn = 98,
+ GPIO1_11_IRQn = 99,
+ GPIO1_12_IRQn = 100,
+ GPIO1_13_IRQn = 101,
+ GPIO1_14_IRQn = 102,
+ GPIO1_15_IRQn = 103,
+ GPIO2_0_IRQn = 104, /* GPIO2 has 16 pins with IRQs */
+ GPIO2_1_IRQn = 105,
+ GPIO2_2_IRQn = 106,
+ GPIO2_3_IRQn = 107,
+ GPIO2_4_IRQn = 108,
+ GPIO2_5_IRQn = 109,
+ GPIO2_6_IRQn = 110,
+ GPIO2_7_IRQn = 111,
+ GPIO2_8_IRQn = 112,
+ GPIO2_9_IRQn = 113,
+ GPIO2_10_IRQn = 114,
+ GPIO2_11_IRQn = 115,
+ GPIO2_12_IRQn = 116,
+ GPIO2_13_IRQn = 117,
+ GPIO2_14_IRQn = 118,
+ GPIO2_15_IRQn = 119,
+ GPIO3_0_IRQn = 120, /* GPIO3 has 4 pins with IRQs */
+ GPIO3_1_IRQn = 121,
+ GPIO3_2_IRQn = 122,
+ GPIO3_3_IRQn = 123,
+}IRQn_Type;
+
+#endif /* __ARM_LTD_SSE_200_IRQN_H__ */
diff --git a/platform/ext/target/sse_200_mps2/cmsis_core/platform_regs.h b/platform/ext/target/sse_200_mps2/cmsis_core/platform_regs.h
new file mode 100644
index 0000000..0a96550
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/cmsis_core/platform_regs.h
@@ -0,0 +1,335 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARM_LTD_SSE_200_REGS_H__
+#define __ARM_LTD_SSE_200_REGS_H__
+
+#include <stdint.h>
+
+/* System information (SYSINFO) */
+#define CMSDK_SYSINFO_BASE_NS 0x40020000
+#define CMSDK_SYSINFO_BASE_S 0x50020000
+
+/* System info memory mapped register access structure */
+struct sysinfo_t {
+ volatile uint32_t sys_version; /* (R/ ) System version */
+ volatile uint32_t sys_config; /* (R/ ) System configuration */
+ volatile uint32_t reserved0[1008];
+ volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */
+ volatile uint32_t reserved1[3];
+ volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */
+ volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */
+ volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */
+ volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */
+ volatile uint32_t cidr0; /* (R/ ) Component ID 0 */
+ volatile uint32_t cidr1; /* (R/ ) Component ID 1 */
+ volatile uint32_t cidr2; /* (R/ ) Component ID 2 */
+ volatile uint32_t cidr3; /* (R/ ) Component ID 3 */
+};
+
+/* System Control (SYSCTRL) */
+#define CMSDK_SYSCTRL_BASE_S 0x50021000
+
+/* System control memory mapped register access structure */
+struct sysctrl_t {
+ volatile uint32_t secdbgstat; /* (R/ ) Secure Debug Configuration
+ * Status Register */
+ volatile uint32_t secdbgset; /* ( /W) Secure Debug Configuration
+ * Set Register */
+ volatile uint32_t secdbgclr; /* ( /W) Secure Debug Configuration
+ * Clear Register */
+ volatile uint32_t scsecctrl; /* (R/W) System Control Security
+ * Control Register */
+ volatile uint32_t fclk_div; /* (R/W) Fast Clock Divider
+ * Configuration Register */
+ volatile uint32_t sysclk_div; /* (R/W) System Clock Divider
+ * Configuration Register */
+ volatile uint32_t clockforce; /* (R/W) Clock Forces */
+ volatile uint32_t reserved0[57];
+ volatile uint32_t resetsyndrome; /* (R/W) Reset syndrome */
+ volatile uint32_t resetmask; /* (R/W) Reset MASK */
+ volatile uint32_t swreset; /* ( /W) Software Reset */
+ volatile uint32_t gretreg; /* (R/W) General Purpose Retention
+ * Register */
+ volatile uint32_t initsvtor0; /* (R/W) Initial Secure Reset Vector
+ * Register For CPU 0 */
+ volatile uint32_t initsvtor1; /* (R/W) Initial Secure Reset
+ * Vector Register For CPU 1*/
+ volatile uint32_t cpuwait; /* (R/W) CPU Boot wait control
+ * after reset */
+ volatile uint32_t nmi_enable; /* (R/W) NAMI Enable Register */
+ volatile uint32_t wicctrl; /* (R/W) CPU WIC Request and
+ * Acknowledgement */
+ volatile uint32_t ewctrl; /* (R/W) External Wakeup Control */
+ volatile uint32_t reserved1[54];
+ volatile uint32_t pdcm_pd_sys_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_SYS
+ * Power Domain Sensitivity.*/
+ volatile uint32_t reserved2[2]; /* Reserved */
+ volatile uint32_t pdcm_pd_sram0_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_SRAM0 Power
+ * Domain Sensitivity.*/
+ volatile uint32_t pdcm_pd_sram1_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_SRAM1 Power
+ * Domain Sensitivity.*/
+ volatile uint32_t pdcm_pd_sram2_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_SRAM2 Power
+ * Domain Sensitivity.*/
+ volatile uint32_t pdcm_pd_sram3_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_SRAM3 Power
+ * Domain Sensitivity.*/
+ volatile uint32_t reserved3[877]; /* Reserved */
+ volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */
+ volatile uint32_t reserved4[3];
+ volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */
+ volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */
+ volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */
+ volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */
+ volatile uint32_t cidr0; /* (R/ ) Component ID 0 */
+ volatile uint32_t cidr1; /* (R/ ) Component ID 1 */
+ volatile uint32_t cidr2; /* (R/ ) Component ID 2 */
+ volatile uint32_t cidr3; /* (R/ ) Component ID 3 */
+};
+
+/* Secure Privilege Control */
+#define CMSDK_SPCTRL_BASE_S 0x50080000
+#define CMSDK_SPCTRL ((struct spctrl_def*)CMSDK_SPCTRL_BASE_S)
+
+/* SPCTRL memory mapped register access structure */
+struct spctrl_def {
+ volatile uint32_t reserved[4];
+ volatile uint32_t secrespcfg;
+ volatile uint32_t nsccfg;
+ volatile uint32_t reserved2;
+ volatile uint32_t secmpcintstatus;
+ volatile uint32_t secppcintstat;
+ volatile uint32_t secppcintclr;
+ volatile uint32_t secppcinten;
+ volatile uint32_t reserved3;
+ volatile uint32_t secmscintstat;
+ volatile uint32_t secmscintclr;
+ volatile uint32_t secmscinten;
+ volatile uint32_t reserved4;
+ volatile uint32_t brgintstat;
+ volatile uint32_t brgintclr;
+ volatile uint32_t brginten;
+ volatile uint32_t reserved5;
+ volatile uint32_t ahbnsppc0;
+ volatile uint32_t reserved6[3];
+ volatile uint32_t ahbnsppcexp0;
+ volatile uint32_t ahbnsppcexp1;
+ volatile uint32_t ahbnsppcexp2;
+ volatile uint32_t ahbnsppcexp3;
+ volatile uint32_t apbnsppc0;
+ volatile uint32_t apbnsppc1;
+ volatile uint32_t reserved7[2];
+ volatile uint32_t apbnsppcexp0;
+ volatile uint32_t apbnsppcexp1;
+ volatile uint32_t apbnsppcexp2;
+ volatile uint32_t apbnsppcexp3;
+ volatile uint32_t ahbspppc0;
+ volatile uint32_t reserved8[3];
+ volatile uint32_t ahbspppcexp0;
+ volatile uint32_t ahbspppcexp1;
+ volatile uint32_t ahbspppcexp2;
+ volatile uint32_t ahbspppcexp3;
+ volatile uint32_t apbspppc0;
+ volatile uint32_t apbspppc1;
+ volatile uint32_t reserved9[2];
+ volatile uint32_t apbspppcexp0;
+ volatile uint32_t apbspppcexp1;
+ volatile uint32_t apbspppcexp2;
+ volatile uint32_t apbspppcexp3;
+ volatile uint32_t nsmscexp;
+ volatile uint32_t reserved10[959];
+ volatile uint32_t pid4;
+ volatile uint32_t pid5;
+ volatile uint32_t pid6;
+ volatile uint32_t pid7;
+ volatile uint32_t pid0;
+ volatile uint32_t pid1;
+ volatile uint32_t pid2;
+ volatile uint32_t pid3;
+ volatile uint32_t cid0;
+ volatile uint32_t cid1;
+ volatile uint32_t cid2;
+ volatile uint32_t cid3;
+};
+
+/* PPC interrupt position mask */
+#define CMSDK_APB_PPC0_INT_POS_MASK (1UL << 0)
+#define CMSDK_APB_PPC1_INT_POS_MASK (1UL << 1)
+#define CMSDK_APB_PPCEXP0_INT_POS_MASK (1UL << 4)
+#define CMSDK_APB_PPCEXP1_INT_POS_MASK (1UL << 5)
+#define CMSDK_APB_PPCEXP2_INT_POS_MASK (1UL << 6)
+#define CMSDK_APB_PPCEXP3_INT_POS_MASK (1UL << 7)
+#define CMSDK_AHB_PPC0_INT_POS_MASK (1UL << 16)
+#define CMSDK_AHB_PPCEXP0_INT_POS_MASK (1UL << 20)
+#define CMSDK_AHB_PPCEXP1_INT_POS_MASK (1UL << 21)
+#define CMSDK_AHB_PPCEXP2_INT_POS_MASK (1UL << 22)
+#define CMSDK_AHB_PPCEXP3_INT_POS_MASK (1UL << 23)
+
+/* Non-Secure Access slave PPCs register addresses */
+#define CMSDK_SPCTRL_AHB_NS_PPC0 (CMSDK_SPCTRL_BASE_S + 0x050)
+#define CMSDK_SPCTRL_AHB_NS_PPCEXP0 (CMSDK_SPCTRL_BASE_S + 0x060)
+#define CMSDK_SPCTRL_AHB_NS_PPCEXP1 (CMSDK_SPCTRL_BASE_S + 0x064)
+#define CMSDK_SPCTRL_AHB_NS_PPCEXP2 (CMSDK_SPCTRL_BASE_S + 0x068)
+#define CMSDK_SPCTRL_AHB_NS_PPCEXP3 (CMSDK_SPCTRL_BASE_S + 0x06C)
+#define CMSDK_SPCTRL_APB_NS_PPC0 (CMSDK_SPCTRL_BASE_S + 0x070)
+#define CMSDK_SPCTRL_APB_NS_PPC1 (CMSDK_SPCTRL_BASE_S + 0x074)
+#define CMSDK_SPCTRL_APB_NS_PPCEXP0 (CMSDK_SPCTRL_BASE_S + 0x080)
+#define CMSDK_SPCTRL_APB_NS_PPCEXP1 (CMSDK_SPCTRL_BASE_S + 0x084)
+#define CMSDK_SPCTRL_APB_NS_PPCEXP2 (CMSDK_SPCTRL_BASE_S + 0x088)
+#define CMSDK_SPCTRL_APB_NS_PPCEXP3 (CMSDK_SPCTRL_BASE_S + 0x08C)
+
+/* Secure Unprivileged (SP) Access slave PPCs register addresses */
+#define CMSDK_SPCTRL_AHB_PPC0_SP (CMSDK_SPCTRL_BASE_S + 0x090)
+#define CMSDK_SPCTRL_AHB_PPCEXP0_SP (CMSDK_SPCTRL_BASE_S + 0x0A0)
+#define CMSDK_SPCTRL_AHB_PPCEXP1_SP (CMSDK_SPCTRL_BASE_S + 0x0A4)
+#define CMSDK_SPCTRL_AHB_PPCEXP2_SP (CMSDK_SPCTRL_BASE_S + 0x0A8)
+#define CMSDK_SPCTRL_AHB_PPCEXP3_SP (CMSDK_SPCTRL_BASE_S + 0x0AC)
+#define CMSDK_SPCTRL_APB_PPC0_SP (CMSDK_SPCTRL_BASE_S + 0x0B0)
+#define CMSDK_SPCTRL_APB_PPC1_SP (CMSDK_SPCTRL_BASE_S + 0x0B4)
+#define CMSDK_SPCTRL_APB_PPCEXP0_SP (CMSDK_SPCTRL_BASE_S + 0x0C0)
+#define CMSDK_SPCTRL_APB_PPCEXP1_SP (CMSDK_SPCTRL_BASE_S + 0x0C4)
+#define CMSDK_SPCTRL_APB_PPCEXP2_SP (CMSDK_SPCTRL_BASE_S + 0x0C8)
+#define CMSDK_SPCTRL_APB_PPCEXP3_SP (CMSDK_SPCTRL_BASE_S + 0x0CC)
+
+/* Non-Secure Privilege Control */
+#define CMSDK_NSPCTRL_BASE_NS 0x40080000
+#define CMSDK_NSPCTRL ((struct nspctrl_def*)CMSDK_NSPCTRL_BASE_NS)
+
+/* NSPCTRL memory mapped register access structure */
+struct nspctrl_def {
+ volatile uint32_t reserved[36];
+ volatile uint32_t ahbnspppc0;
+ volatile uint32_t reserved3[3];
+ volatile uint32_t ahbnspppcexp0;
+ volatile uint32_t ahbnspppcexp1;
+ volatile uint32_t ahbnspppcexp2;
+ volatile uint32_t ahbnspppcexp3;
+ volatile uint32_t apbnspppc0;
+ volatile uint32_t apbnspppc1;
+ volatile uint32_t reserved4[2];
+ volatile uint32_t apbnspppcexp0;
+ volatile uint32_t apbnspppcexp1;
+ volatile uint32_t apbnspppcexp2;
+ volatile uint32_t apbnspppcexp3;
+ volatile uint32_t reserved5[960];
+ volatile uint32_t pidr4;
+ volatile uint32_t reserved7; /* pidr5 */
+ volatile uint32_t reserved8; /* pidr6 */
+ volatile uint32_t reserved9; /* pidr7 */
+ volatile uint32_t pidr0;
+ volatile uint32_t pidr1;
+ volatile uint32_t pidr2;
+ volatile uint32_t pidr3;
+ volatile uint32_t cidr0;
+ volatile uint32_t cidr1;
+ volatile uint32_t cidr2;
+ volatile uint32_t cidr3;
+};
+
+/* Non-Secure Unprivileged Access (NSP) Access slave PPCs register addresses */
+#define CMSDK_NSPCTRL_AHB_PPC0_NSP (CMSDK_NSPCTRL_BASE_NS + 0x090)
+#define CMSDK_NSPCTRL_AHB_PPCEXP0_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0A0)
+#define CMSDK_NSPCTRL_AHB_PPCEXP1_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0A4)
+#define CMSDK_NSPCTRL_AHB_PPCEXP2_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0A8)
+#define CMSDK_NSPCTRL_AHB_PPCEXP3_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0AC)
+#define CMSDK_NSPCTRL_APB_PPC0_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0B0)
+#define CMSDK_NSPCTRL_APB_PPC1_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0B4)
+#define CMSDK_NSPCTRL_APB_PPCEXP0_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0C0)
+#define CMSDK_NSPCTRL_APB_PPCEXP1_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0C4)
+#define CMSDK_NSPCTRL_APB_PPCEXP2_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0C8)
+#define CMSDK_NSPCTRL_APB_PPCEXP3_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0CC)
+
+/* ARM APB PPC0 peripherals definition */
+#define CMSDK_TIMER0_APB_PPC_POS 0U
+#define CMSDK_TIMER1_APB_PPC_POS 1U
+#define CMSDK_DTIMER_APB_PPC_POS 2U
+#define CMSDK_MHU0_APB_PPC_POS 3U
+#define CMSDK_MHU1_APB_PPC_POS 4U
+/* The bits 31:5 are reserved */
+/* End ARM APB PPC0 peripherals definition */
+
+/* ARM APB PPC1 peripherals definition */
+#define CMSDK_S32K_TIMER_PPC_POS 0U
+/* The bits 31:1 are reserved */
+/* End ARM APB PPC1 peripherals definition */
+
+/* ARM APB PPCEXP0 peripherals definition */
+#define CMSDK_SSRAM1_APB_PPC_POS 0U
+#define CMSDK_SSRAM2_APB_PPC_POS 1U
+#define CMSDK_SSRAM3_APB_PPC_POS 2U
+/* The bits 31:3 are reserved */
+/* End ARM APB PPCEXP0 peripherals definition */
+
+/* ARM APB PPCEXP1 peripherals definition */
+#define CMSDK_SPI0_APB_PPC_POS 0U
+#define CMSDK_SPI1_APB_PPC_POS 1U
+#define CMSDK_SPI2_APB_PPC_POS 2U
+#define CMSDK_SPI3_APB_PPC_POS 3U
+#define CMSDK_SPI4_APB_PPC_POS 4U
+#define CMSDK_UART0_APB_PPC_POS 5U
+#define CMSDK_UART1_APB_PPC_POS 6U
+#define CMSDK_UART2_APB_PPC_POS 7U
+#define CMSDK_UART3_APB_PPC_POS 8U
+#define CMSDK_UART4_APB_PPC_POS 9U
+#define CMSDK_I2C0_APB_PPC_POS 10U
+#define CMSDK_I2C1_APB_PPC_POS 11U
+#define CMSDK_I2C2_APB_PPC_POS 12U
+#define CMSDK_I2C3_APB_PPC_POS 13U
+/* The bits 31:14 are reserved */
+/* End ARM APB PPCEXP1 peripherals definition */
+
+/* ARM APB PPCEXP2 peripherals definition */
+#define CMSDK_FPGA_SCC_PPC_POS 0U
+#define CMSDK_FPGA_AUDIO_PPC_POS 1U
+#define CMSDK_FPGA_IO_PPC_POS 2U
+/* The bits 31:3 are reserved */
+/* End ARM APB PPCEXP2 peripherals definition */
+
+/* ARM APB PPCEXP3 peripherals definition */
+/* The bits 31:0 are reserved */
+/* End ARM APB PPCEXP3 peripherals definition */
+
+/* ARM AHB PPC0 peripherals definition */
+/* The bits 31:0 are reserved */
+/* End of ARM AHB PPC0 peripherals definition */
+
+/* ARM AHB PPCEXP0 peripherals definition */
+#define CMSDK_VGA_PPC_POS 0U
+#define CMSDK_GPIO0_PPC_POS 1U
+#define CMSDK_GPIO1_PPC_POS 2U
+#define CMSDK_GPIO2_PPC_POS 3U
+#define CMSDK_GPIO3_PPC_POS 4U
+/* The bits 31:5 are reserved */
+/* End of ARM AHB PPCEXP0 peripherals definition */
+
+/* ARM AHB PPCEXP1 peripherals definition */
+/* The bits 31:0 are reserved */
+/* End of ARM AHB PPCEXP1 peripherals definition */
+
+/* ARM AHB PPCEXP2 peripherals definition */
+/* The bits 31:0 are reserved */
+/* End of ARM AHB PPCEXP2 peripherals definition */
+
+/* ARM AHB PPCEXP3 peripherals definition */
+/* The bits 31:0 are reserved */
+
+/* End of ARM AHB PPCEXP3 peripherals definition */
+
+#endif /* __ARM_LTD_SSE_200_REGS_H__ */
diff --git a/platform/ext/target/sse_200_mps2/cmsis_core/system_cmsdk_mps2_sse_200.c b/platform/ext/target/sse_200_mps2/cmsis_core/system_cmsdk_mps2_sse_200.c
new file mode 100644
index 0000000..c815daa
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/cmsis_core/system_cmsdk_mps2_sse_200.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis.h"
+
+/*
+ * MPS2 SSE-200 has different frequencies for system core clock (20MHz) and
+ * peripherals clock (25MHz).
+ */
+#define XTAL (40000000UL)
+#define PERIPHERAL_XTAL (50000000UL)
+
+#define SYSTEM_CLOCK (XTAL/2)
+#define PERIPHERAL_CLOCK (PERIPHERAL_XTAL/2)
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t PeripheralClock = PERIPHERAL_CLOCK;
+
+/* System Core Clock update function */
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/* System initialization function */
+void SystemInit (void)
+{
+#if __DOMAIN_NS != 1U
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+#endif /* __DOMAIN_NS != 1U */
+
+ SystemCoreClock = SYSTEM_CLOCK;
+ PeripheralClock = PERIPHERAL_CLOCK;
+}
diff --git a/platform/ext/target/sse_200_mps2/cmsis_core/system_cmsdk_mps2_sse_200.h b/platform/ext/target/sse_200_mps2/cmsis_core/system_cmsdk_mps2_sse_200.h
new file mode 100644
index 0000000..bcdb1ed
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/cmsis_core/system_cmsdk_mps2_sse_200.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_CMSDK_MPS2_SSE_200_H__
+#define __SYSTEM_CMSDK_MPS2_SSE_200_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */
+
+/**
+ * \brief Initializes the system
+ */
+void SystemInit(void);
+
+/**
+ * \brief Restores system core clock
+ */
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_CMSDK_MPS2_SSE_200_H__ */
diff --git a/platform/ext/target/sse_200_mps2/dummy_crypto_keys.c b/platform/ext/target/sse_200_mps2/dummy_crypto_keys.c
new file mode 100644
index 0000000..05a3fca
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/dummy_crypto_keys.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform/include/plat_crypto_keys.h"
+
+#define TFM_KEY_LEN_BYTES 16
+
+static uint8_t sample_tfm_key[TFM_KEY_LEN_BYTES] =
+ {0x00, 0x001, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, \
+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F};
+
+enum tfm_plat_errno_t plat_get_crypto_huk(uint8_t* key, uint32_t size)
+{
+ /* FIXME: this function should be implemented by platform vendor. For the
+ * security of the storage system, it is critical to use a hardware unique
+ * key.
+ *
+ * SSE-200 does not have any available hardware unique key engine, so a
+ * software stub has been implemented in this case.
+ */
+ uint32_t i;
+ uint8_t* p_dst = key;
+ uint8_t* p_huk = sample_tfm_key;
+
+ if(size > TFM_KEY_LEN_BYTES) {
+ return TFM_PLAT_ERRNO_SYSTEM_ERR;
+ }
+
+ for (i = size; i > 0; i--) {
+ *((uint8_t*)p_dst) = *((uint8_t*)p_huk);
+ p_huk++;
+ p_dst++;
+ }
+
+ return TFM_PLAT_ERRNO_SUCCESS;
+}
+
diff --git a/platform/ext/target/sse_200_mps2/mps2/mps2_board/mps2_leds.c b/platform/ext/target/sse_200_mps2/mps2/mps2_board/mps2_leds.c
new file mode 100644
index 0000000..b86dfb2
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/mps2/mps2_board/mps2_leds.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mps2_leds.h"
+#include "smm_mps2.h"
+
+#define MPS2_FPGAIO_NBR_LEDS 2U /* Number of available MPS2 FPGAIO LEDs */
+#define MPS2_SCC_NBR_LEDS 8U /* Number of available MPS2 SCC LEDs */
+
+uint32_t mps2_get_nbr_leds(enum mps2_led_t led_type)
+{
+ switch(led_type) {
+ case MPS2_FPGAIO_LED:
+ return MPS2_FPGAIO_NBR_LEDS;
+ case MPS2_SCC_LED:
+ return MPS2_SCC_NBR_LEDS;
+ /* default: The default is not defined intentionally to force the
+ * compiler to check that all enumeration values are
+ * covered in the switch.*/
+ }
+}
+
+void mps2_set_leds(enum mps2_led_t led_type, uint32_t leds_val)
+{
+ switch(led_type) {
+ case MPS2_FPGAIO_LED:
+ MPS2_FPGAIO->LED = ((1U << (MPS2_FPGAIO_NBR_LEDS)) - 1U) & leds_val;
+ break;
+ case MPS2_SCC_LED:
+ MPS2_SCC->LEDS = ((1U << (MPS2_SCC_NBR_LEDS)) - 1U) & leds_val;
+ break;
+ /* default: The default is not defined intentionally to force the
+ * compiler to check that all enumeration values are
+ * covered in the switch.*/
+ }
+}
+
+void mps2_led_on(enum mps2_led_t led_type, enum mps2_led_name_t led_id)
+{
+ switch(led_type) {
+ case MPS2_FPGAIO_LED:
+ if (led_id < MPS2_FPGAIO_NBR_LEDS) {
+ MPS2_FPGAIO->LED |= (1U << led_id);
+ }
+ break;
+ case MPS2_SCC_LED:
+ if (led_id < MPS2_SCC_NBR_LEDS) {
+ MPS2_SCC->LEDS |= (1U << led_id);
+ }
+ break;
+ /* default: The default is not defined intentionally to force the
+ * compiler to check that all enumeration values are
+ * covered in the switch.*/
+ }
+}
+
+void mps2_led_off(enum mps2_led_t led_type, enum mps2_led_name_t led_id)
+{
+ switch(led_type) {
+ case MPS2_FPGAIO_LED:
+ if (led_id < MPS2_FPGAIO_NBR_LEDS) {
+ MPS2_FPGAIO->LED &= ~(1U << led_id);
+ }
+ break;
+ case MPS2_SCC_LED:
+ if (led_id < MPS2_SCC_NBR_LEDS) {
+ MPS2_SCC->LEDS &= ~(1U << led_id);
+ }
+ break;
+ /* default: The default is not defined intentionally to force the
+ * compiler to check that all enumeration values are
+ * covered in the switch.*/
+ }
+}
diff --git a/platform/ext/target/sse_200_mps2/mps2/mps2_board/mps2_leds.h b/platform/ext/target/sse_200_mps2/mps2/mps2_board/mps2_leds.h
new file mode 100644
index 0000000..5fca92c
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/mps2/mps2_board/mps2_leds.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MPS2_BOARD_LEDS_H__
+#define __MPS2_BOARD_LEDS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+enum mps2_led_t {
+ MPS2_FPGAIO_LED,
+ MPS2_SCC_LED
+};
+
+enum mps2_led_name_t {
+ MPS2_FPGAIO_USER_LED0,
+ MPS2_FPGAIO_USER_LED1,
+ MPS2_SCC_LED1,
+ MPS2_SCC_LED2,
+ MPS2_SCC_LED3,
+ MPS2_SCC_LED4,
+ MPS2_SCC_LED5,
+ MPS2_SCC_LED6,
+ MPS2_SCC_LED7,
+ MPS2_SCC_LED8
+};
+
+/**
+ * \brief Gets number of available FPGA LEDs.
+ *
+ * \param[in] led_type FPGA LEDs type (\ref mps2_led_t).
+ *
+ * \return Number of available LEDs.
+ */
+uint32_t mps2_get_nbr_leds(enum mps2_led_t led_type);
+
+/**
+ * \brief Sets FPGA LEDs state.
+ *
+ * \param[in] led_type FPGA LEDs type (\ref mps2_led_t).
+ * \param[in] leds_val FPGA LEDs value.
+*/
+void mps2_set_leds(enum mps2_led_t led_type, uint32_t leds_val);
+
+/**
+ * \brief Switchs on the given FPGA LED.
+ *
+ * \param[in] led_type FPGA LEDs type (\ref mps2_led_t).
+ * \param[in] led_id FPGA LED Id (\ref mps2_led_name_t).
+*/
+void mps2_led_on(enum mps2_led_t led_type, enum mps2_led_name_t led_id);
+
+/**
+ * \brief Switchs off the given FPGA LED.
+ *
+ * \param[in] led_type FPGA LEDs type (\ref mps2_led_t).
+ * \param[in] led_id FPGA LED Id (\ref mps2_led_name_t).
+*/
+void mps2_led_off(enum mps2_led_t led_type, enum mps2_led_name_t led_id);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __MPS2_BOARD_LEDS_H__ */
diff --git a/platform/ext/target/sse_200_mps2/mps2/mps2_board/mps2_time.c b/platform/ext/target/sse_200_mps2/mps2/mps2_board/mps2_time.c
new file mode 100644
index 0000000..661fb28
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/mps2/mps2_board/mps2_time.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mps2_time.h"
+#include "smm_mps2.h"
+
+#define TICKS_PER_US (SystemCoreClock / 1000000U)
+#define TICKS_PER_MS (SystemCoreClock / 1000U)
+
+uint32_t mps2_get_ticks(enum mps2_clk_t clk)
+{
+ switch (clk) {
+ case MPS2_CLK_1HZ:
+ return MPS2_FPGAIO->CLK1HZ;
+ case MPS2_CLK_100HZ:
+ return MPS2_FPGAIO->CLK100HZ;
+ case MPS2_CLK_25MHZ:
+ return MPS2_FPGAIO->COUNTER;
+ /* default: Compiler check */
+ }
+}
+
+void mps2_sleepms(uint32_t msec)
+{
+ uint32_t end;
+ uint32_t start;
+
+ start = MPS2_FPGAIO->COUNTER;
+ end = start + (msec * TICKS_PER_MS);
+
+ if (end >= start) {
+ while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end){};
+ } else {
+ while (MPS2_FPGAIO->COUNTER >= start){};
+ while (MPS2_FPGAIO->COUNTER < end){};
+ }
+}
+
+void mps2_sleepus(uint32_t usec)
+{
+ uint32_t end;
+ uint32_t start;
+
+ start = MPS2_FPGAIO->COUNTER;
+ end = start + (usec * TICKS_PER_US);
+
+ if (end >= start) {
+ while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end){};
+ } else {
+ while (MPS2_FPGAIO->COUNTER >= start){};
+ while (MPS2_FPGAIO->COUNTER < end){};
+ }
+}
+
+void mps2_sleeps(uint32_t sec)
+{
+ uint32_t end;
+ uint32_t start;
+
+ start = MPS2_FPGAIO->CLK1HZ;
+ end = start + sec;
+
+ if (end >= start) {
+ while (MPS2_FPGAIO->CLK1HZ >= start && MPS2_FPGAIO->CLK1HZ < end){};
+ } else {
+ while (MPS2_FPGAIO->CLK1HZ >= start){};
+ while (MPS2_FPGAIO->CLK1HZ < end){};
+ }
+}
diff --git a/platform/ext/target/sse_200_mps2/mps2/mps2_board/mps2_time.h b/platform/ext/target/sse_200_mps2/mps2/mps2_board/mps2_time.h
new file mode 100644
index 0000000..516c837
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/mps2/mps2_board/mps2_time.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MPS2_TIME_H__
+#define __MPS2_TIME_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Enum to define clocks in the system */
+enum mps2_clk_t {
+ MPS2_CLK_1HZ = 0, /*!< 1Hz ticker */
+ MPS2_CLK_100HZ, /*!< 100Hz ticker */
+ MPS2_CLK_25MHZ /*!< 25MHz ticker */
+};
+
+/**
+ * \brief Return number of ticks of a clock
+ *
+ * \param[in] clk Clock to get ticks from
+ *
+ * \return Value of the counter
+ */
+uint32_t mps2_get_ticks(enum mps2_clk_t clk);
+
+/**
+ * \brief Sleep function to delay milliseconds.
+ *
+ * \param[in] msec Time to sleep in msec
+ *
+ * \note Maximum measurable time with current implementation is 171s
+ */
+void mps2_sleepms(uint32_t msec);
+
+/**
+ * \brief Sleep function to delay microseconds.
+ *
+ * \param[in] usec Time to sleep in usec
+ *
+ * \note Maximum measurable time with current implementation is 171s
+ */
+void mps2_sleepus(uint32_t usec);
+
+/**
+ * \brief Sleep function to delay in seconds.
+ *
+ * \param[in] sec Time to sleep in seconds
+ */
+void mps2_sleeps(uint32_t sec);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __MPS2_TIME_H__ */
diff --git a/platform/ext/target/sse_200_mps2/mps2/mps2_board/smm_mps2.h b/platform/ext/target/sse_200_mps2/mps2/mps2_board/smm_mps2.h
new file mode 100644
index 0000000..8570c2a
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/mps2/mps2_board/smm_mps2.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SMM_MPS2_H__
+#define __SMM_MPS2_H__
+
+#include "cmsis.h" /* device specific header file */
+
+/* FPGAIO register map structure */
+struct arm_mps2_fpgaio_t {
+ volatile uint32_t LED; /* Offset: 0x000 (R/W) LED connections
+ * [31:2] : Reserved
+ * [1:0] : LEDs */
+ volatile uint32_t RESERVED1[1];
+ volatile uint32_t BUTTON; /* Offset: 0x008 (R/W) Buttons
+ * [31:2] : Reserved
+ * [1:0] : Buttons */
+ volatile uint32_t RESERVED2[1];
+ volatile uint32_t CLK1HZ; /* Offset: 0x010 (R/W) 1Hz up counter */
+ volatile uint32_t CLK100HZ; /* Offset: 0x014 (R/W) 100Hz up counter */
+ volatile uint32_t COUNTER; /* Offset: 0x018 (R/W) Cycle Up Counter
+ * Increments when
+ * 32bit prescale
+ * counter reach
+ * zero */
+ volatile uint32_t RESERVED3[1];
+ volatile uint32_t PRESCALE; /* Offset: 0x020 (R/W) Prescaler
+ * Bit[31:0] : reload
+ * value for prescale
+ * counter */
+ volatile uint32_t PSCNTR; /* Offset: 0x024 (R/W) 32bit Prescale
+ * counter. Current
+ * value of the
+ * prescaler counter.
+ *
+ * The Cycle Up Counter increment when the
+ * prescale down counter reach 0.
+ * The prescaler counter is reloaded with
+ * PRESCALE after reaching 0. */
+ volatile uint32_t RESERVED4[9];
+ volatile uint32_t MISC; /* Offset: 0x04C (R/W) Misc control
+ * [31:10] : Reserved
+ * [9] : SHIELD_1_SPI_nCS
+ * [8] : SHIELD_0_SPI_nCS
+ * [7] : ADC_SPI_nCS
+ * [6] : CLCD_BL_CTRL
+ * [5] : CLCD_RD
+ * [4] : CLCD_RS
+ * [3] : CLCD_RESET
+ * [2] : RESERVED
+ * [1] : SPI_nSS
+ * [0] : CLCD_CS */
+};
+
+/* SCC register map structure */
+struct arm_mps2_scc_t {
+ volatile uint32_t CFG_REG0; /* Offset: 0x000 (R/W) Remaps block RAM to
+ * ZBT
+ * [31:1] : Reserved
+ * [0] 1 : REMAP BlockRam to ZBT */
+ volatile uint32_t LEDS; /* Offset: 0x004 (R/W) Controls the MCC user
+ * LEDs
+ * [31:8] : Reserved
+ * [7:0] : MCC LEDs */
+ volatile uint32_t RESERVED0[1];
+ volatile uint32_t SWITCHES; /* Offset: 0x00C (R/ ) Denotes the state
+ * of the MCC user
+ * switches
+ * [31:8] : Reserved
+ * [7:0] : These bits indicate state
+ * of the MCC switches */
+ volatile uint32_t CFG_REG4; /* Offset: 0x010 (R/ ) Denotes the board
+ * revision
+ * [31:4] : Reserved
+ * [3:0] : Used by the MCC to pass
+ * PCB revision.
+ * 0 = A 1 = B */
+ volatile uint32_t RESERVED1[35];
+ volatile uint32_t SYS_CFGDATA_RTN; /* Offset: 0x0A0 (R/W) User data register
+ * [31:0] : Data */
+ volatile uint32_t SYS_CFGDATA_OUT; /* Offset: 0x0A4 (R/W) User data
+ * register
+ * [31:0] : Data */
+ volatile uint32_t SYS_CFGCTRL; /* Offset: 0x0A8 (R/W) Control register
+ * [31] : Start (generates
+ * interrupt on write
+ * to this bit)
+ * [30] : R/W access
+ * [29:26] : Reserved
+ * [25:20] : Function value
+ * [19:12] : Reserved
+ * [11:0] : Device (value of
+ * 0/1/2 for supported
+ * clocks) */
+ volatile uint32_t SYS_CFGSTAT; /* Offset: 0x0AC (R/W) Contains status
+ * information
+ * [31:2] : Reserved
+ * [1] : Error
+ * [0] : Complete */
+ volatile uint32_t RESERVED2[20];
+ volatile uint32_t SCC_DLL; /* Offset: 0x100 (R/W) DLL Lock Register
+ * [31:24] : DLL LOCK MASK[7:0]
+ * Indicate if the DLL
+ * locked is masked
+ * [23:16] : DLL LOCK MASK[7:0]
+ * Indicate if the DLLs
+ * are locked or
+ * unlocked
+ * [15:1] : Reserved
+ * [0] : This bit indicates
+ * if all enabled DLLs
+ * are locked */
+ volatile uint32_t RESERVED3[957];
+ volatile uint32_t SCC_AID; /* Offset: 0xFF8 (R/ ) SCC AID Register
+ * [31:24] : FPGA build number
+ * [23:20] : V2MMPS2 target
+ * board revision
+ * (A = 0, B = 1)
+ * [19:11] : Reserved
+ * [10] : if “1” SCC_SW
+ * register has been
+ * implemented
+ * [9] : if “1” SCC_LED
+ * register has been
+ * implemented
+ * [8] : if “1” DLL lock
+ * register has been
+ * implemented
+ * [7:0] : number of SCC
+ * configuration
+ * register */
+ volatile uint32_t SCC_ID; /* Offset: 0xFFC (R/ ) Contains
+ * information about
+ * the FPGA image
+ * [31:24] : Implementer ID:
+ * 0x41 = ARM
+ * [23:20] : Application note
+ * IP variant number
+ * [19:16] : IP Architecture:
+ * 0x4 =AHB
+ * [15:4] : Primary part number:
+ * 386 = AN386
+ * [3:0] : Application note IP
+ * revision number */
+};
+
+/* Peripheral memory map */
+#define MPS2_FPGAIO_BASE_NS 0x40302000 /* FPGAIO Base Address */
+#define MPS2_SCC_BASE_NS 0x40300000 /* SCC Base Address */
+
+/* Secure Peripheral memory map */
+#define MPS2_FPGAIO_BASE_S 0x50302000 /* FPGAIO Base Address */
+#define MPS2_SCC_BASE_S 0x50300000 /* SCC Base Address */
+
+/* Peripheral declaration */
+#define MPS2_FPGAIO ((struct arm_mps2_fpgaio_t*) MPS2_FPGAIO_BASE_NS)
+#define MPS2_SCC ((struct arm_mps2_scc_t*) MPS2_SCC_BASE_NS)
+
+/* Secure Peripheral declaration */
+#define SEC_MPS2_FPGAIO ((struct arm_mps2_fpgaio_t*) MPS2_FPGAIO_BASE_S)
+#define SEC_MPS2_SCC ((struct arm_mps2_scc_t*) MPS2_SCC_BASE_S)
+
+#endif /* __SMM_MPS2_H__ */
diff --git a/platform/ext/target/sse_200_mps2/sse_200/RTE_Device.h b/platform/ext/target/sse_200_mps2/sse_200/RTE_Device.h
new file mode 100644
index 0000000..723a5cd
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/RTE_Device.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+// <e> SPI (Serial Peripheral Interface) [Driver_SPI0]
+// <i> Configuration settings for Driver_SPI0 in component ::Drivers:SPI
+#define RTE_SPI0 1
+// </e> SPI (Serial Peripheral Interface) [Driver_SPI0]
+
+// <e> SPI (Serial Peripheral Interface) [Driver_SPI1]
+// <i> Configuration settings for Driver_SPI1 in component ::Drivers:SPI
+#define RTE_SPI1 1
+// </e> SPI (Serial Peripheral Interface) [Driver_SPI1]
+
+// <e> SPI (Serial Peripheral Interface) [Driver_SPI2]
+// <i> Configuration settings for Driver_SPI2 in component ::Drivers:SPI
+#define RTE_SPI2 1
+// </e> SPI (Serial Peripheral Interface) [Driver_SPI2]
+
+// <e> SPI (Serial Peripheral Interface) [Driver_SPI3]
+// <i> Configuration settings for Driver_SPI3 in component ::Drivers:SPI
+#define RTE_SPI3 1
+// </e> SPI (Serial Peripheral Interface) [Driver_SPI3]
+
+// <e> SPI (Serial Peripheral Interface) [Driver_SPI4]
+// <i> Configuration settings for Driver_SPI4 in component ::Drivers:SPI
+#define RTE_SPI4 1
+// </e> SPI (Serial Peripheral Interface) [Driver_SPI4]
+
+// <e> I2C (Inter-integrated Circuit Interface 2) [Driver_I2C0]
+// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
+#define RTE_I2C0 1
+// </e> I2C (Inter-integrated Circuit Interface 2) [Driver_I2C0]
+
+// <e> I2C (Inter-integrated Circuit Interface 2) [Driver_I2C1]
+// <i> Configuration settings for Driver_I2C1 in component ::Drivers:I2C
+#define RTE_I2C1 1
+// </e> I2C (Inter-integrated Circuit Interface 2) [Driver_I2C1]
+
+// <e> I2C (Inter-integrated Circuit Interface 2) [Driver_I2C2]
+// <i> Configuration settings for Driver_I2C2 in component ::Drivers:I2C
+#define RTE_I2C2 1
+// </e> I2C (Inter-integrated Circuit Interface 2) [Driver_I2C2]
+
+// <e> I2C (Inter-integrated Circuit Interface 2) [Driver_I2C3]
+// <i> Configuration settings for Driver_I2C3 in component ::Drivers:I2C
+#define RTE_I2C3 1
+// </e> I2C (Inter-integrated Circuit Interface 2) [Driver_I2C3]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
+// <i> Configuration settings for Driver_USART0 in component ::Drivers:USART
+#define RTE_USART0 1
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
+// <i> Configuration settings for Driver_USART1 in component ::Drivers:USART
+#define RTE_USART1 1
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART2]
+// <i> Configuration settings for Driver_USART2 in component ::Drivers:USART
+#define RTE_USART2 1
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART2]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART3]
+// <i> Configuration settings for Driver_USART3 in component ::Drivers:USART
+#define RTE_USART3 1
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART3]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART4]
+// <i> Configuration settings for Driver_USART4 in component ::Drivers:USART
+#define RTE_USART4 1
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART4]
+
+// <e> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
+// <i> Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC
+#define RTE_ISRAM0_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
+// <i> Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC
+#define RTE_ISRAM1_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_ISRAM2_MPC]
+// <i> Configuration settings for Driver_ISRAM2_MPC in component ::Drivers:MPC
+#define RTE_ISRAM2_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_ISRAM2_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_ISRAM3_MPC]
+// <i> Configuration settings for Driver_ISRAM3_MPC in component ::Drivers:MPC
+#define RTE_ISRAM3_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_ISRAM3_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_SRAM1_MPC]
+// <i> Configuration settings for Driver_SRAM1_MPC in component ::Drivers:MPC
+#define RTE_CODE_SRAM1_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_SRAM1_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_SRAM2_MPC]
+// <i> Configuration settings for Driver_SRAM2_MPC in component ::Drivers:MPC
+#define RTE_CODE_SRAM2_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_SRAM2_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_SRAM3_MPC]
+// <i> Configuration settings for Driver_SRAM3_MPC in component ::Drivers:MPC
+#define RTE_CODE_SRAM3_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_SRAM3_MPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP0]
+// <i> Configuration settings for Driver_AHB_PPCEXP0 in component ::Drivers:MPC
+#define RTE_AHB_PPCEXP0 1
+// </e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP1]
+// <i> Configuration settings for Driver_AHB_PPCEXP1 in component ::Drivers:MPC
+#define RTE_AHB_PPCEXP1 0
+// </e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP2]
+// <i> Configuration settings for Driver_AHB_PPCEXP2 in component ::Drivers:MPC
+#define RTE_AHB_PPCEXP2 0
+// </e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP2]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP3]
+// <i> Configuration settings for Driver_AHB_PPCEXP3 in component ::Drivers:MPC
+#define RTE_AHB_PPCEXP3 0
+// </e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP3]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPC0]
+// <i> Configuration settings for Driver_APB_PPC0 in component ::Drivers:MPC
+#define RTE_APB_PPC0 1
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPC0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPC1]
+// <i> Configuration settings for Driver_APB_PPC1 in component ::Drivers:MPC
+#define RTE_APB_PPC1 1
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPC1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP0]
+// <i> Configuration settings for Driver_APB_PPCEXP0 in component ::Drivers:MPC
+#define RTE_APB_PPCEXP0 1
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP1]
+// <i> Configuration settings for Driver_APB_PPCEXP1 in component ::Drivers:MPC
+#define RTE_APB_PPCEXP1 1
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP2]
+// <i> Configuration settings for Driver_APB_PPCEXP2 in component ::Drivers:MPC
+#define RTE_APB_PPCEXP2 1
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP2]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP3]
+// <i> Configuration settings for Driver_APB_PPCEXP3 in component ::Drivers:MPC
+#define RTE_APB_PPCEXP3 1
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP3]
+
+#endif /* __RTE_DEVICE_H */
diff --git a/platform/ext/target/sse_200_mps2/sse_200/armclang/sse_200_ns.sct b/platform/ext/target/sse_200_mps2/sse_200/armclang/sse_200_ns.sct
new file mode 100644
index 0000000..302945f
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/armclang/sse_200_ns.sct
@@ -0,0 +1,31 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
+
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "../partition/region_defs.h"
+
+LR_CODE NS_CODE_START {
+ ER_CODE NS_CODE_START NS_CODE_SIZE {
+ *.o (RESET +First)
+ .ANY (+RO)
+ }
+
+ ER_DATA NS_DATA_START NS_DATA_SIZE {
+ .ANY (+ZI +RW)
+ }
+}
+
diff --git a/platform/ext/target/sse_200_mps2/sse_200/armclang/sse_200_s.sct b/platform/ext/target/sse_200_mps2/sse_200/armclang/sse_200_s.sct
new file mode 100644
index 0000000..46c7ee8
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/armclang/sse_200_s.sct
@@ -0,0 +1,112 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
+
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "../partition/region_defs.h"
+
+LR_CODE S_CODE_START {
+
+ /**** This initial section contains common code for TEE */
+ ER_TFM_CODE S_CODE_START S_CODE_SIZE {
+ *.o (RESET +First)
+ .ANY (+RO)
+ }
+
+#if TFM_LVL == 1
+
+ ER_TFM_DATA S_DATA_START S_DATA_SIZE {
+ .ANY (+RW +ZI)
+ }
+
+ TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x4000 {
+ }
+
+ TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
+ }
+
+#else /* TFM_LVL == 1 */
+
+ /**** Unprivileged Secure code start here */
+ TFM_UNPRIV_CODE +0 ALIGN 32 {
+ tfm_unpriv_api.o (+RO)
+ platform_retarget_dev.o (+RO)
+ *(SFN)
+ }
+
+ TFM_SEC_FUNC_STORAGE +0 ALIGN 32 {
+ *tfm_storage* (+RO)
+ }
+
+#ifdef CORE_TEST_SERVICES
+ TFM_SEC_FUNC_CORE_TEST +0 ALIGN 32 {
+ *tfm_ss_core_test.* (+RO)
+ }
+
+ TFM_SEC_FUNC_CORE_TEST_2 +0 ALIGN 32 {
+ *tfm_ss_core_test_2.* (+RO)
+ }
+#endif /* CORE_TEST_SERVICES */
+
+ ER_TFM_DATA S_DATA_START S_DATA_SIZE {
+ .ANY (+RW +ZI)
+ }
+
+ TFM_UNPRIV_RO_DATA +0 ALIGN 32 {
+ tfm_unpriv_api.o (+RW +ZI)
+ platform_retarget_dev.o (+RW +ZI)
+ }
+
+ TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
+ }
+
+ TFM_SEC_FUNC_STORAGE_DATA +0 ALIGN 32 {
+ *tfm_storage* (+RW +ZI)
+ }
+
+ TFM_SEC_FUNC_STORAGE_STACK +0 ALIGN 128 EMPTY 0x2000 {
+ }
+
+#ifdef CORE_TEST_SERVICES
+ TFM_SEC_FUNC_CORE_TEST_DATA +0 ALIGN 32 {
+ tfm_ss_core_test.o (+RW +ZI)
+ }
+
+ TFM_SEC_FUNC_CORE_TEST_STACK +0 ALIGN 128 EMPTY 0x2000 {
+ }
+
+ TFM_SEC_FUNC_CORE_TEST_2_DATA +0 ALIGN 32 {
+ tfm_ss_core_test_2.o (+RW +ZI)
+ }
+
+ TFM_SEC_FUNC_CORE_TEST_2_STACK +0 ALIGN 128 EMPTY 0x2000 {
+ }
+#endif /* CORE_TEST_SERVICES */
+
+#endif /* TFM_LVL == 1 */
+
+}
+
+LR_VENEER CMSE_VENEER_REGION_START {
+ /*
+ * Place the CMSE Veneers (containing the SG instruction) in a separate
+ * 32 bytes aligned region so that the SAU can be programmed to
+ * just set this region as Non-Secure Callable.
+ */
+ ER_CODE_CMSE_VENEER CMSE_VENEER_REGION_START CMSE_VENEER_REGION_SIZE {
+ *(Veneer$$CMSE)
+ }
+}
diff --git a/platform/ext/target/sse_200_mps2/sse_200/armclang/startup_cmsdk_sse_200_ns.s b/platform/ext/target/sse_200_mps2/sse_200/armclang/startup_cmsdk_sse_200_ns.s
new file mode 100644
index 0000000..188188d
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/armclang/startup_cmsdk_sse_200_ns.s
@@ -0,0 +1,413 @@
+;/*
+; * Copyright (c) 2016 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.00 startup_ARMv8MML.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00001000
+MSP_STACK_SIZE EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_msp
+
+__initial_sp EQU __initial_msp - MSP_STACK_SIZE
+
+
+Heap_Size EQU 0x00001000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_msp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TIMER0_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD 0 ; Reserved - 6
+ DCD 0 ; Reserved - 7
+ DCD 0 ; Reserved - 8
+ DCD 0 ; Reserved - 9
+ DCD 0 ; Reserved - 10
+ DCD 0 ; Reserved - 11
+ DCD 0 ; Reserved - 12
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 0 combined Handler
+ DCD UART3_Handler ; 45 UART 1 combined Handler
+ DCD UART4_Handler ; 46 UART 0 combined Handler
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD SPI0_Handler ; 51 SPI 0 Handler
+ DCD SPI1_Handler ; 52 SPI 1 Handler
+ DCD SPI2_Handler ; 53 SPI 2 Handler
+ DCD SPI3_Handler ; 54 SPI 3 Handler
+ DCD SPI4_Handler ; 55 SPI 4 Handler
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72,
+ DCD GPIO0_1_Handler ; 73,
+ DCD GPIO0_2_Handler ; 74,
+ DCD GPIO0_3_Handler ; 75,
+ DCD GPIO0_4_Handler ; 76,
+ DCD GPIO0_5_Handler ; 77,
+ DCD GPIO0_6_Handler ; 78,
+ DCD GPIO0_7_Handler ; 79,
+ DCD GPIO0_8_Handler ; 80,
+ DCD GPIO0_9_Handler ; 81,
+ DCD GPIO0_10_Handler ; 82,
+ DCD GPIO0_11_Handler ; 83,
+ DCD GPIO0_12_Handler ; 84,
+ DCD GPIO0_13_Handler ; 85,
+ DCD GPIO0_14_Handler ; 86,
+ DCD GPIO0_15_Handler ; 87,
+ DCD GPIO1_0_Handler ; 88,
+ DCD GPIO1_1_Handler ; 89,
+ DCD GPIO1_2_Handler ; 90,
+ DCD GPIO1_3_Handler ; 91,
+ DCD GPIO1_4_Handler ; 92,
+ DCD GPIO1_5_Handler ; 93,
+ DCD GPIO1_6_Handler ; 94,
+ DCD GPIO1_7_Handler ; 95,
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ MRS R0, control ; Get control value
+ ORR R0, R0, #1 ; Select switch to unprivilage mode
+ ORR R0, R0, #2 ; Select switch to PSP, which will be set by __user_initial_stackheap
+ MSR control, R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; Core IoT Interrupts
+ EXPORT NONSEC_WATCHDOG_RESET_Handler [WEAK] ; - 0 Non-Secure Watchdog Reset Handler
+ EXPORT NONSEC_WATCHDOG_Handler [WEAK] ; - 1 Non-Secure Watchdog Handler
+ EXPORT S32K_TIMER_Handler [WEAK] ; - 2 S32K Timer Handler
+ EXPORT TIMER0_Handler [WEAK] ; - 3 TIMER 0 Handler
+ EXPORT TIMER1_Handler [WEAK] ; - 4 TIMER 1 Handler
+ EXPORT DUALTIMER_Handler [WEAK] ; - 5 Dual Timer Handler
+; External Interrupts
+ EXPORT UARTRX0_Handler [WEAK] ; 32 UART 0 RX Handler
+ EXPORT UARTTX0_Handler [WEAK] ; 33 UART 0 TX Handler
+ EXPORT UARTRX1_Handler [WEAK] ; 34 UART 1 RX Handler
+ EXPORT UARTTX1_Handler [WEAK] ; 35 UART 1 TX Handler
+ EXPORT UARTRX2_Handler [WEAK] ; 36 UART 2 RX Handler
+ EXPORT UARTTX2_Handler [WEAK] ; 37 UART 2 TX Handler
+ EXPORT UARTRX3_Handler [WEAK] ; 38 UART 3 RX Handler
+ EXPORT UARTTX3_Handler [WEAK] ; 39 UART 3 TX Handler
+ EXPORT UARTRX4_Handler [WEAK] ; 40 UART 4 RX Handler
+ EXPORT UARTTX4_Handler [WEAK] ; 41 UART 4 TX Handler
+ EXPORT UART0_Handler [WEAK] ; 42 UART 0 combined Handler
+ EXPORT UART1_Handler [WEAK] ; 43 UART 1 combined Handler
+ EXPORT UART2_Handler [WEAK] ; 44 UART 2 combined Handler
+ EXPORT UART3_Handler [WEAK] ; 45 UART 3 combined Handler
+ EXPORT UART4_Handler [WEAK] ; 46 UART 4 combined Handler
+ EXPORT UARTOVF_Handler [WEAK] ; 47 UART 0,1,2,3,4 Overflow Handler
+ EXPORT ETHERNET_Handler [WEAK] ; 48 Ethernet Handler
+ EXPORT I2S_Handler [WEAK] ; 49 I2S Handler
+ EXPORT TSC_Handler [WEAK] ; 50 Touch Screen Handler
+ EXPORT SPI0_Handler [WEAK] ; 51 SPI 0 Handler
+ EXPORT SPI1_Handler [WEAK] ; 52 SPI 1 Handler
+ EXPORT SPI2_Handler [WEAK] ; 53 SPI 2 Handler
+ EXPORT SPI3_Handler [WEAK] ; 54 SPI 3 Handler
+ EXPORT SPI4_Handler [WEAK] ; 55 SPI 4 Handler
+ EXPORT DMA0_ERROR_Handler [WEAK] ; 56 DMA 0 Error Handler
+ EXPORT DMA0_TC_Handler [WEAK] ; 57 DMA 0 Terminal Count Handler
+ EXPORT DMA0_Handler [WEAK] ; 58 DMA 0 Combined Handler
+ EXPORT DMA1_ERROR_Handler [WEAK] ; 59 DMA 1 Error Handler
+ EXPORT DMA1_TC_Handler [WEAK] ; 60 DMA 1 Terminal Count Handler
+ EXPORT DMA1_Handler [WEAK] ; 61 DMA 1 Combined Handler
+ EXPORT DMA2_ERROR_Handler [WEAK] ; 62 DMA 2 Error Handler
+ EXPORT DMA2_TC_Handler [WEAK] ; 63 DMA 2 Terminal Count Handler
+ EXPORT DMA2_Handler [WEAK] ; 64 DMA 2 Combined Handler
+ EXPORT DMA3_ERROR_Handler [WEAK] ; 65 DMA 3 Error Handler
+ EXPORT DMA3_TC_Handler [WEAK] ; 66 DMA 3 Terminal Count Handler
+ EXPORT DMA3_Handler [WEAK] ; 67 DMA 3 Combined Handler
+ EXPORT GPIO0_Handler [WEAK] ; 68 GPIO 0 Comboned Handler
+ EXPORT GPIO1_Handler [WEAK] ; 69 GPIO 1 Comboned Handler
+ EXPORT GPIO2_Handler [WEAK] ; 70 GPIO 2 Comboned Handler
+ EXPORT GPIO3_Handler [WEAK] ; 71 GPIO 3 Comboned Handler
+ EXPORT GPIO0_0_Handler [WEAK] ; 72 GPIO 1 has 16 individual Handlers
+ EXPORT GPIO0_1_Handler [WEAK] ; 73
+ EXPORT GPIO0_2_Handler [WEAK] ; 74
+ EXPORT GPIO0_3_Handler [WEAK] ; 75
+ EXPORT GPIO0_4_Handler [WEAK] ; 76
+ EXPORT GPIO0_5_Handler [WEAK] ; 77
+ EXPORT GPIO0_6_Handler [WEAK] ; 78
+ EXPORT GPIO0_7_Handler [WEAK] ; 79
+ EXPORT GPIO0_8_Handler [WEAK] ; 80
+ EXPORT GPIO0_9_Handler [WEAK] ; 81
+ EXPORT GPIO0_10_Handler [WEAK] ; 82
+ EXPORT GPIO0_11_Handler [WEAK] ; 83
+ EXPORT GPIO0_12_Handler [WEAK] ; 84
+ EXPORT GPIO0_13_Handler [WEAK] ; 85
+ EXPORT GPIO0_14_Handler [WEAK] ; 86
+ EXPORT GPIO0_15_Handler [WEAK] ; 87
+ EXPORT GPIO1_0_Handler [WEAK] ; 88 GPIO 1 has 8 individual Handlers
+ EXPORT GPIO1_1_Handler [WEAK] ; 89
+ EXPORT GPIO1_2_Handler [WEAK] ; 90
+ EXPORT GPIO1_3_Handler [WEAK] ; 91
+ EXPORT GPIO1_4_Handler [WEAK] ; 92
+ EXPORT GPIO1_5_Handler [WEAK] ; 93
+ EXPORT GPIO1_6_Handler [WEAK] ; 94
+ EXPORT GPIO1_7_Handler [WEAK] ; 95
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; - 2 S32K Timer Handler
+TIMER0_Handler ; - 3 TIMER 0 Handler
+TIMER1_Handler ; - 4 TIMER 1 Handler
+DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 51 SPI 0 Handler
+SPI1_Handler ; 52 SPI 1 Handler
+SPI2_Handler ; 53 SPI 2 Handler
+SPI3_Handler ; 54 SPI 3 Handler
+SPI4_Handler ; 55 SPI 4 Handler
+DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+DMA0_Handler ; 58 DMA 0 Combined Handler
+DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+DMA1_Handler ; 61 DMA 1 Combined Handler
+DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+DMA2_Handler ; 64 DMA 2 Combined Handler
+DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+DMA3_Handler ; 67 DMA 3 Combined Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
+GPIO0_1_Handler ; 73
+GPIO0_2_Handler ; 74
+GPIO0_3_Handler ; 75
+GPIO0_4_Handler ; 76
+GPIO0_5_Handler ; 77
+GPIO0_6_Handler ; 78
+GPIO0_7_Handler ; 79
+GPIO0_8_Handler ; 80
+GPIO0_9_Handler ; 81
+GPIO0_10_Handler ; 82
+GPIO0_11_Handler ; 83
+GPIO0_12_Handler ; 84
+GPIO0_13_Handler ; 85
+GPIO0_14_Handler ; 86
+GPIO0_15_Handler ; 87
+GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+GPIO1_1_Handler ; 89
+GPIO1_2_Handler ; 90
+GPIO1_3_Handler ; 91
+GPIO1_4_Handler ; 92
+GPIO1_5_Handler ; 93
+GPIO1_6_Handler ; 94
+GPIO1_7_Handler ; 95
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, = __initial_sp
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/platform/ext/target/sse_200_mps2/sse_200/armclang/startup_cmsdk_sse_200_s.s b/platform/ext/target/sse_200_mps2/sse_200/armclang/startup_cmsdk_sse_200_s.s
new file mode 100644
index 0000000..40d2347
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/armclang/startup_cmsdk_sse_200_s.s
@@ -0,0 +1,430 @@
+;/*
+; * Copyright (c) 2016 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.00 startup_ARMv8MML.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00001000
+MSP_STACK_SIZE EQU 0x00000800
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT Stack_Mem
+Stack_Mem SPACE Stack_Size
+__initial_msp
+__initial_sp EQU __initial_msp - MSP_STACK_SIZE
+
+
+Heap_Size EQU 0x00001000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_msp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TIMER0_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD 0 ; Reserved - 6
+ DCD 0 ; Reserved - 7
+ DCD 0 ; Reserved - 8
+ DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler
+ DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler
+ DCD 0 ; Reserved - 11
+ DCD 0 ; Reserved - 12
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 0 combined Handler
+ DCD UART3_Handler ; 45 UART 1 combined Handler
+ DCD UART4_Handler ; 46 UART 0 combined Handler
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD SPI0_Handler ; 51 SPI 0 Handler
+ DCD SPI1_Handler ; 52 SPI 1 Handler
+ DCD SPI2_Handler ; 53 SPI 2 Handler
+ DCD SPI3_Handler ; 54 SPI 3 Handler
+ DCD SPI4_Handler ; 55 SPI 4 Handler
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72,
+ DCD GPIO0_1_Handler ; 73,
+ DCD GPIO0_2_Handler ; 74,
+ DCD GPIO0_3_Handler ; 75,
+ DCD GPIO0_4_Handler ; 76,
+ DCD GPIO0_5_Handler ; 77,
+ DCD GPIO0_6_Handler ; 78,
+ DCD GPIO0_7_Handler ; 79,
+ DCD GPIO0_8_Handler ; 80,
+ DCD GPIO0_9_Handler ; 81,
+ DCD GPIO0_10_Handler ; 82,
+ DCD GPIO0_11_Handler ; 83,
+ DCD GPIO0_12_Handler ; 84,
+ DCD GPIO0_13_Handler ; 85,
+ DCD GPIO0_14_Handler ; 86,
+ DCD GPIO0_15_Handler ; 87,
+ DCD GPIO1_0_Handler ; 88,
+ DCD GPIO1_1_Handler ; 89,
+ DCD GPIO1_2_Handler ; 90,
+ DCD GPIO1_3_Handler ; 91,
+ DCD GPIO1_4_Handler ; 92,
+ DCD GPIO1_5_Handler ; 93,
+ DCD GPIO1_6_Handler ; 94,
+ DCD GPIO1_7_Handler ; 95,
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ MRS R0, control ; Get control value
+ ORR R0, R0, #2 ; Select switch to PSP, which will be set by __user_initial_stackheap
+ MSR control, R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+
+SecureFault_Handler\
+ PROC
+ EXPORT SecureFault_Handler [WEAK]
+ B .
+ ENDP
+
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ IMPORT SVCHandler_main
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+MPC_Handler PROC
+ EXPORT MPC_Handler [WEAK]
+ B .
+ ENDP
+PPC_Handler PROC
+ EXPORT PPC_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; Core IoT Interrupts
+ EXPORT NONSEC_WATCHDOG_RESET_Handler [WEAK] ; - 0 Non-Secure Watchdog Reset Handler
+ EXPORT NONSEC_WATCHDOG_Handler [WEAK] ; - 1 Non-Secure Watchdog Handler
+ EXPORT S32K_TIMER_Handler [WEAK] ; - 2 S32K Timer Handler
+ EXPORT TIMER0_Handler [WEAK] ; - 3 TIMER 0 Handler
+ EXPORT TIMER1_Handler [WEAK] ; - 4 TIMER 1 Handler
+ EXPORT DUALTIMER_Handler [WEAK] ; - 5 Dual Timer Handler
+; External Interrupts
+ EXPORT UARTRX0_Handler [WEAK] ; 32 UART 0 RX Handler
+ EXPORT UARTTX0_Handler [WEAK] ; 33 UART 0 TX Handler
+ EXPORT UARTRX1_Handler [WEAK] ; 34 UART 1 RX Handler
+ EXPORT UARTTX1_Handler [WEAK] ; 35 UART 1 TX Handler
+ EXPORT UARTRX2_Handler [WEAK] ; 36 UART 2 RX Handler
+ EXPORT UARTTX2_Handler [WEAK] ; 37 UART 2 TX Handler
+ EXPORT UARTRX3_Handler [WEAK] ; 38 UART 3 RX Handler
+ EXPORT UARTTX3_Handler [WEAK] ; 39 UART 3 TX Handler
+ EXPORT UARTRX4_Handler [WEAK] ; 40 UART 4 RX Handler
+ EXPORT UARTTX4_Handler [WEAK] ; 41 UART 4 TX Handler
+ EXPORT UART0_Handler [WEAK] ; 42 UART 0 combined Handler
+ EXPORT UART1_Handler [WEAK] ; 43 UART 1 combined Handler
+ EXPORT UART2_Handler [WEAK] ; 44 UART 2 combined Handler
+ EXPORT UART3_Handler [WEAK] ; 45 UART 3 combined Handler
+ EXPORT UART4_Handler [WEAK] ; 46 UART 4 combined Handler
+ EXPORT UARTOVF_Handler [WEAK] ; 47 UART 0,1,2,3,4 Overflow Handler
+ EXPORT ETHERNET_Handler [WEAK] ; 48 Ethernet Handler
+ EXPORT I2S_Handler [WEAK] ; 49 I2S Handler
+ EXPORT TSC_Handler [WEAK] ; 50 Touch Screen Handler
+ EXPORT SPI0_Handler [WEAK] ; 51 SPI 0 Handler
+ EXPORT SPI1_Handler [WEAK] ; 52 SPI 1 Handler
+ EXPORT SPI2_Handler [WEAK] ; 53 SPI 2 Handler
+ EXPORT SPI3_Handler [WEAK] ; 54 SPI 3 Handler
+ EXPORT SPI4_Handler [WEAK] ; 55 SPI 4 Handler
+ EXPORT DMA0_ERROR_Handler [WEAK] ; 56 DMA 0 Error Handler
+ EXPORT DMA0_TC_Handler [WEAK] ; 57 DMA 0 Terminal Count Handler
+ EXPORT DMA0_Handler [WEAK] ; 58 DMA 0 Combined Handler
+ EXPORT DMA1_ERROR_Handler [WEAK] ; 59 DMA 1 Error Handler
+ EXPORT DMA1_TC_Handler [WEAK] ; 60 DMA 1 Terminal Count Handler
+ EXPORT DMA1_Handler [WEAK] ; 61 DMA 1 Combined Handler
+ EXPORT DMA2_ERROR_Handler [WEAK] ; 62 DMA 2 Error Handler
+ EXPORT DMA2_TC_Handler [WEAK] ; 63 DMA 2 Terminal Count Handler
+ EXPORT DMA2_Handler [WEAK] ; 64 DMA 2 Combined Handler
+ EXPORT DMA3_ERROR_Handler [WEAK] ; 65 DMA 3 Error Handler
+ EXPORT DMA3_TC_Handler [WEAK] ; 66 DMA 3 Terminal Count Handler
+ EXPORT DMA3_Handler [WEAK] ; 67 DMA 3 Combined Handler
+ EXPORT GPIO0_Handler [WEAK] ; 68 GPIO 0 Comboned Handler
+ EXPORT GPIO1_Handler [WEAK] ; 69 GPIO 1 Comboned Handler
+ EXPORT GPIO2_Handler [WEAK] ; 70 GPIO 2 Comboned Handler
+ EXPORT GPIO3_Handler [WEAK] ; 71 GPIO 3 Comboned Handler
+ EXPORT GPIO0_0_Handler [WEAK] ; 72 GPIO 1 has 16 individual Handlers
+ EXPORT GPIO0_1_Handler [WEAK] ; 73
+ EXPORT GPIO0_2_Handler [WEAK] ; 74
+ EXPORT GPIO0_3_Handler [WEAK] ; 75
+ EXPORT GPIO0_4_Handler [WEAK] ; 76
+ EXPORT GPIO0_5_Handler [WEAK] ; 77
+ EXPORT GPIO0_6_Handler [WEAK] ; 78
+ EXPORT GPIO0_7_Handler [WEAK] ; 79
+ EXPORT GPIO0_8_Handler [WEAK] ; 80
+ EXPORT GPIO0_9_Handler [WEAK] ; 81
+ EXPORT GPIO0_10_Handler [WEAK] ; 82
+ EXPORT GPIO0_11_Handler [WEAK] ; 83
+ EXPORT GPIO0_12_Handler [WEAK] ; 84
+ EXPORT GPIO0_13_Handler [WEAK] ; 85
+ EXPORT GPIO0_14_Handler [WEAK] ; 86
+ EXPORT GPIO0_15_Handler [WEAK] ; 87
+ EXPORT GPIO1_0_Handler [WEAK] ; 88 GPIO 1 has 8 individual Handlers
+ EXPORT GPIO1_1_Handler [WEAK] ; 89
+ EXPORT GPIO1_2_Handler [WEAK] ; 90
+ EXPORT GPIO1_3_Handler [WEAK] ; 91
+ EXPORT GPIO1_4_Handler [WEAK] ; 92
+ EXPORT GPIO1_5_Handler [WEAK] ; 93
+ EXPORT GPIO1_6_Handler [WEAK] ; 94
+ EXPORT GPIO1_7_Handler [WEAK] ; 95
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; - 2 S32K Timer Handler
+TIMER0_Handler ; - 3 TIMER 0 Handler
+TIMER1_Handler ; - 4 TIMER 1 Handler
+DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 51 SPI 0 Handler
+SPI1_Handler ; 52 SPI 1 Handler
+SPI2_Handler ; 53 SPI 2 Handler
+SPI3_Handler ; 54 SPI 3 Handler
+SPI4_Handler ; 55 SPI 4 Handler
+DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+DMA0_Handler ; 58 DMA 0 Combined Handler
+DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+DMA1_Handler ; 61 DMA 1 Combined Handler
+DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+DMA2_Handler ; 64 DMA 2 Combined Handler
+DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+DMA3_Handler ; 67 DMA 3 Combined Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
+GPIO0_1_Handler ; 73
+GPIO0_2_Handler ; 74
+GPIO0_3_Handler ; 75
+GPIO0_4_Handler ; 76
+GPIO0_5_Handler ; 77
+GPIO0_6_Handler ; 78
+GPIO0_7_Handler ; 79
+GPIO0_8_Handler ; 80
+GPIO0_9_Handler ; 81
+GPIO0_10_Handler ; 82
+GPIO0_11_Handler ; 83
+GPIO0_12_Handler ; 84
+GPIO0_13_Handler ; 85
+GPIO0_14_Handler ; 86
+GPIO0_15_Handler ; 87
+GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+GPIO1_1_Handler ; 89
+GPIO1_2_Handler ; 90
+GPIO1_3_Handler ; 91
+GPIO1_4_Handler ; 92
+GPIO1_5_Handler ; 93
+GPIO1_6_Handler ; 94
+GPIO1_7_Handler ; 95
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, = __initial_sp
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/platform/ext/target/sse_200_mps2/sse_200/cmsis_drivers/Driver_MPC.c b/platform/ext/target/sse_200_mps2/sse_200/cmsis_drivers/Driver_MPC.c
new file mode 100644
index 0000000..b0e62dd
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/cmsis_drivers/Driver_MPC.c
@@ -0,0 +1,1017 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Driver_MPC.h"
+
+#include "cmsis.h"
+#include "platform_retarget_dev.h"
+#include "RTE_Device.h"
+
+/* driver version */
+#define ARM_MPC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+ ARM_MPC_API_VERSION,
+ ARM_MPC_DRV_VERSION
+};
+
+static ARM_DRIVER_VERSION ARM_MPC_GetVersion(void)
+{
+ return DriverVersion;
+}
+
+/*
+ * \brief Translates error codes from native API to CMSIS API.
+ *
+ * \param[in] err Error code to translate (\ref mpc_sie200_error_t).
+ *
+ * \return Returns CMSIS error code.
+ */
+static int32_t error_trans(enum mpc_sie200_error_t err)
+{
+ switch(err) {
+ case MPC_SIE200_ERR_NONE:
+ return ARM_DRIVER_OK;
+ case MPC_SIE200_INVALID_ARG:
+ return ARM_DRIVER_ERROR_PARAMETER;
+ case MPC_SIE200_NOT_INIT:
+ return ARM_MPC_ERR_NOT_INIT;
+ case MPC_SIE200_ERR_NOT_IN_RANGE:
+ return ARM_MPC_ERR_NOT_IN_RANGE;
+ case MPC_SIE200_ERR_NOT_ALIGNED:
+ return ARM_MPC_ERR_NOT_ALIGNED;
+ case MPC_SIE200_ERR_INVALID_RANGE:
+ return ARM_MPC_ERR_INVALID_RANGE;
+ case MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE:
+ return ARM_MPC_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE;
+ /* default: The default is not defined intentionally to force the
+ * compiler to check that all the enumeration values are
+ * covered in the switch.
+ */
+ }
+}
+
+#if (RTE_ISRAM0_MPC)
+/* Ranges controlled by this ISRAM0_MPC */
+static struct mpc_sie200_memory_range_t MPC_ISRAM0_RANGE_S = {
+ .base = MPC_ISRAM0_RANGE_BASE_S,
+ .limit = MPC_ISRAM0_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_ISRAM0_RANGE_NS = {
+ .base = MPC_ISRAM0_RANGE_BASE_NS,
+ .limit = MPC_ISRAM0_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_ISRAM0_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_ISRAM0_RANGE_LIST[MPC_ISRAM0_RANGE_LIST_LEN]=
+ {&MPC_ISRAM0_RANGE_S, &MPC_ISRAM0_RANGE_NS};
+
+/* ISRAM0_MPC Driver wrapper functions */
+static int32_t ISRAM0_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_ISRAM0_DEV_S,
+ MPC_ISRAM0_RANGE_LIST,
+ MPC_ISRAM0_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ISRAM0_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_ISRAM0_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_ISRAM0_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_ISRAM0_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_ISRAM0_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_ISRAM0_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_ISRAM0_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void ISRAM0_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_ISRAM0_DEV_S);
+}
+
+
+static void ISRAM0_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_ISRAM0_DEV_S);
+}
+
+static uint32_t ISRAM0_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_ISRAM0_DEV_S);
+}
+
+static int32_t ISRAM0_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_ISRAM0_DEV_S);
+}
+
+/* ISRAM0_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_ISRAM0_MPC;
+ARM_DRIVER_MPC Driver_ISRAM0_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = ISRAM0_MPC_Initialize,
+ .Uninitialize = ISRAM0_MPC_Uninitialize,
+ .GetBlockSize = ISRAM0_MPC_GetBlockSize,
+ .GetCtrlConfig = ISRAM0_MPC_GetCtrlConfig,
+ .SetCtrlConfig = ISRAM0_MPC_SetCtrlConfig,
+ .ConfigRegion = ISRAM0_MPC_ConfigRegion,
+ .GetRegionConfig = ISRAM0_MPC_GetRegionConfig,
+ .EnableInterrupt = ISRAM0_MPC_EnableInterrupt,
+ .DisableInterrupt = ISRAM0_MPC_DisableInterrupt,
+ .ClearInterrupt = ISRAM0_MPC_ClearInterrupt,
+ .InterruptState = ISRAM0_MPC_InterruptState,
+ .LockDown = ISRAM0_MPC_LockDown,
+};
+#endif /* RTE_ISRAM0_MPC */
+
+#if (RTE_ISRAM1_MPC)
+/* Ranges controlled by this ISRAM1_MPC */
+static struct mpc_sie200_memory_range_t MPC_ISRAM1_RANGE_S = {
+ .base = MPC_ISRAM1_RANGE_BASE_S,
+ .limit = MPC_ISRAM1_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_ISRAM1_RANGE_NS = {
+ .base = MPC_ISRAM1_RANGE_BASE_NS,
+ .limit = MPC_ISRAM1_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_ISRAM1_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_ISRAM1_RANGE_LIST[MPC_ISRAM1_RANGE_LIST_LEN]=
+ {&MPC_ISRAM1_RANGE_S, &MPC_ISRAM1_RANGE_NS};
+
+/* ISRAM1_MPC Driver wrapper functions */
+static int32_t ISRAM1_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_ISRAM1_DEV_S,
+ MPC_ISRAM1_RANGE_LIST,
+ MPC_ISRAM1_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ISRAM1_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_ISRAM1_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_ISRAM1_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_ISRAM1_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_ISRAM1_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_ISRAM1_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_ISRAM1_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void ISRAM1_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_ISRAM1_DEV_S);
+}
+
+
+static void ISRAM1_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_ISRAM1_DEV_S);
+}
+
+static uint32_t ISRAM1_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_ISRAM1_DEV_S);
+}
+
+static int32_t ISRAM1_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_ISRAM1_DEV_S);
+}
+
+/* ISRAM1_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_ISRAM1_MPC;
+ARM_DRIVER_MPC Driver_ISRAM1_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = ISRAM1_MPC_Initialize,
+ .Uninitialize = ISRAM1_MPC_Uninitialize,
+ .GetBlockSize = ISRAM1_MPC_GetBlockSize,
+ .GetCtrlConfig = ISRAM1_MPC_GetCtrlConfig,
+ .SetCtrlConfig = ISRAM1_MPC_SetCtrlConfig,
+ .ConfigRegion = ISRAM1_MPC_ConfigRegion,
+ .GetRegionConfig = ISRAM1_MPC_GetRegionConfig,
+ .EnableInterrupt = ISRAM1_MPC_EnableInterrupt,
+ .DisableInterrupt = ISRAM1_MPC_DisableInterrupt,
+ .ClearInterrupt = ISRAM1_MPC_ClearInterrupt,
+ .InterruptState = ISRAM1_MPC_InterruptState,
+ .LockDown = ISRAM1_MPC_LockDown,
+};
+#endif /* RTE_ISRAM1_MPC */
+
+#if (RTE_ISRAM2_MPC)
+/* Ranges controlled by this ISRAM2_MPC */
+static struct mpc_sie200_memory_range_t MPC_ISRAM2_RANGE_S = {
+ .base = MPC_ISRAM2_RANGE_BASE_S,
+ .limit = MPC_ISRAM2_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_ISRAM2_RANGE_NS = {
+ .base = MPC_ISRAM2_RANGE_BASE_NS,
+ .limit = MPC_ISRAM2_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_ISRAM2_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_ISRAM2_RANGE_LIST[MPC_ISRAM2_RANGE_LIST_LEN]=
+ {&MPC_ISRAM2_RANGE_S, &MPC_ISRAM2_RANGE_NS};
+
+/* ISRAM2_MPC Driver wrapper functions */
+static int32_t ISRAM2_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_ISRAM2_DEV_S,
+ MPC_ISRAM2_RANGE_LIST,
+ MPC_ISRAM2_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ISRAM2_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_ISRAM2_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_ISRAM2_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_ISRAM2_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_ISRAM2_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_ISRAM2_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_ISRAM2_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void ISRAM2_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_ISRAM2_DEV_S);
+}
+
+
+static void ISRAM2_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_ISRAM2_DEV_S);
+}
+
+static uint32_t ISRAM2_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_ISRAM2_DEV_S);
+}
+
+static int32_t ISRAM2_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_ISRAM2_DEV_S);
+}
+
+/* ISRAM2_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_ISRAM2_MPC;
+ARM_DRIVER_MPC Driver_ISRAM2_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = ISRAM2_MPC_Initialize,
+ .Uninitialize = ISRAM2_MPC_Uninitialize,
+ .GetBlockSize = ISRAM2_MPC_GetBlockSize,
+ .GetCtrlConfig = ISRAM2_MPC_GetCtrlConfig,
+ .SetCtrlConfig = ISRAM2_MPC_SetCtrlConfig,
+ .ConfigRegion = ISRAM2_MPC_ConfigRegion,
+ .GetRegionConfig = ISRAM2_MPC_GetRegionConfig,
+ .EnableInterrupt = ISRAM2_MPC_EnableInterrupt,
+ .DisableInterrupt = ISRAM2_MPC_DisableInterrupt,
+ .ClearInterrupt = ISRAM2_MPC_ClearInterrupt,
+ .InterruptState = ISRAM2_MPC_InterruptState,
+ .LockDown = ISRAM2_MPC_LockDown,
+};
+#endif /* RTE_ISRAM2_MPC */
+
+#if (RTE_ISRAM3_MPC)
+/* Ranges controlled by this ISRAM3_MPC */
+static struct mpc_sie200_memory_range_t MPC_ISRAM3_RANGE_S = {
+ .base = MPC_ISRAM3_RANGE_BASE_S,
+ .limit = MPC_ISRAM3_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_ISRAM3_RANGE_NS = {
+ .base = MPC_ISRAM3_RANGE_BASE_NS,
+ .limit = MPC_ISRAM3_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_ISRAM3_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_ISRAM3_RANGE_LIST[MPC_ISRAM3_RANGE_LIST_LEN]=
+ {&MPC_ISRAM3_RANGE_S, &MPC_ISRAM3_RANGE_NS};
+
+/* ISRAM3_MPC Driver wrapper functions */
+static int32_t ISRAM3_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_ISRAM3_DEV_S,
+ MPC_ISRAM3_RANGE_LIST,
+ MPC_ISRAM3_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ISRAM3_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_ISRAM3_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_ISRAM3_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_ISRAM3_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_ISRAM3_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_ISRAM3_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_ISRAM3_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void ISRAM3_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_ISRAM3_DEV_S);
+}
+
+
+static void ISRAM3_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_ISRAM3_DEV_S);
+}
+
+static uint32_t ISRAM3_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_ISRAM3_DEV_S);
+}
+
+static int32_t ISRAM3_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_ISRAM3_DEV_S);
+}
+
+/* ISRAM3_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_ISRAM3_MPC;
+ARM_DRIVER_MPC Driver_ISRAM3_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = ISRAM3_MPC_Initialize,
+ .Uninitialize = ISRAM3_MPC_Uninitialize,
+ .GetBlockSize = ISRAM3_MPC_GetBlockSize,
+ .GetCtrlConfig = ISRAM3_MPC_GetCtrlConfig,
+ .SetCtrlConfig = ISRAM3_MPC_SetCtrlConfig,
+ .ConfigRegion = ISRAM3_MPC_ConfigRegion,
+ .GetRegionConfig = ISRAM3_MPC_GetRegionConfig,
+ .EnableInterrupt = ISRAM3_MPC_EnableInterrupt,
+ .DisableInterrupt = ISRAM3_MPC_DisableInterrupt,
+ .ClearInterrupt = ISRAM3_MPC_ClearInterrupt,
+ .InterruptState = ISRAM3_MPC_InterruptState,
+ .LockDown = ISRAM3_MPC_LockDown,
+};
+#endif /* RTE_ISRAM3_MPC */
+
+#if (RTE_CODE_SRAM1_MPC)
+/* Ranges controlled by this SRAM1_MPC */
+static struct mpc_sie200_memory_range_t MPC_CODE_SRAM1_RANGE_S = {
+ .base = MPC_CODE_SRAM1_RANGE_BASE_S,
+ .limit = MPC_CODE_SRAM1_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_CODE_SRAM1_RANGE_NS = {
+ .base = MPC_CODE_SRAM1_RANGE_BASE_NS,
+ .limit = MPC_CODE_SRAM1_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_CODE_SRAM1_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_CODE_SRAM1_RANGE_LIST[MPC_CODE_SRAM1_RANGE_LIST_LEN]=
+ {&MPC_CODE_SRAM1_RANGE_S, &MPC_CODE_SRAM1_RANGE_NS};
+
+/* SRAM1_MPC Driver wrapper functions */
+static int32_t SRAM1_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_CODE_SRAM1_DEV_S,
+ MPC_CODE_SRAM1_RANGE_LIST,
+ MPC_CODE_SRAM1_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM1_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t SRAM1_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_CODE_SRAM1_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM1_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_CODE_SRAM1_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM1_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_CODE_SRAM1_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM1_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_CODE_SRAM1_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM1_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_CODE_SRAM1_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM1_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_CODE_SRAM1_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void SRAM1_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_CODE_SRAM1_DEV_S);
+}
+
+
+static void SRAM1_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_CODE_SRAM1_DEV_S);
+}
+
+static uint32_t SRAM1_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_CODE_SRAM1_DEV_S);
+}
+
+static int32_t SRAM1_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_CODE_SRAM1_DEV_S);
+}
+
+/* SRAM1_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_SRAM1_MPC;
+ARM_DRIVER_MPC Driver_SRAM1_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = SRAM1_MPC_Initialize,
+ .Uninitialize = SRAM1_MPC_Uninitialize,
+ .GetBlockSize = SRAM1_MPC_GetBlockSize,
+ .GetCtrlConfig = SRAM1_MPC_GetCtrlConfig,
+ .SetCtrlConfig = SRAM1_MPC_SetCtrlConfig,
+ .ConfigRegion = SRAM1_MPC_ConfigRegion,
+ .GetRegionConfig = SRAM1_MPC_GetRegionConfig,
+ .EnableInterrupt = SRAM1_MPC_EnableInterrupt,
+ .DisableInterrupt = SRAM1_MPC_DisableInterrupt,
+ .ClearInterrupt = SRAM1_MPC_ClearInterrupt,
+ .InterruptState = SRAM1_MPC_InterruptState,
+ .LockDown = SRAM1_MPC_LockDown,
+};
+#endif /* RTE_CODE_SRAM1_MPC */
+
+#if (RTE_CODE_SRAM2_MPC)
+/* Ranges controlled by this SRAM2_MPC */
+static struct mpc_sie200_memory_range_t MPC_CODE_SRAM2_RANGE_S = {
+ .base = MPC_CODE_SRAM2_RANGE_BASE_S,
+ .limit = MPC_CODE_SRAM2_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_CODE_SRAM2_RANGE_NS = {
+ .base = MPC_CODE_SRAM2_RANGE_BASE_NS,
+ .limit = MPC_CODE_SRAM2_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_CODE_SRAM2_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_CODE_SRAM2_RANGE_LIST[MPC_CODE_SRAM2_RANGE_LIST_LEN]=
+ {&MPC_CODE_SRAM2_RANGE_S, &MPC_CODE_SRAM2_RANGE_NS};
+
+/* SRAM2_MPC Driver wrapper functions */
+static int32_t SRAM2_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_CODE_SRAM2_DEV_S,
+ MPC_CODE_SRAM2_RANGE_LIST,
+ MPC_CODE_SRAM2_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM2_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t SRAM2_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_CODE_SRAM2_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM2_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_CODE_SRAM2_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM2_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_CODE_SRAM2_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM2_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_CODE_SRAM2_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM2_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_CODE_SRAM2_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM2_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_CODE_SRAM2_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void SRAM2_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_CODE_SRAM2_DEV_S);
+}
+
+
+static void SRAM2_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_CODE_SRAM2_DEV_S);
+}
+
+static uint32_t SRAM2_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_CODE_SRAM2_DEV_S);
+}
+
+static int32_t SRAM2_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_CODE_SRAM2_DEV_S);
+}
+
+/* SRAM2_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_SRAM2_MPC;
+ARM_DRIVER_MPC Driver_SRAM2_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = SRAM2_MPC_Initialize,
+ .Uninitialize = SRAM2_MPC_Uninitialize,
+ .GetBlockSize = SRAM2_MPC_GetBlockSize,
+ .GetCtrlConfig = SRAM2_MPC_GetCtrlConfig,
+ .SetCtrlConfig = SRAM2_MPC_SetCtrlConfig,
+ .ConfigRegion = SRAM2_MPC_ConfigRegion,
+ .GetRegionConfig = SRAM2_MPC_GetRegionConfig,
+ .EnableInterrupt = SRAM2_MPC_EnableInterrupt,
+ .DisableInterrupt = SRAM2_MPC_DisableInterrupt,
+ .ClearInterrupt = SRAM2_MPC_ClearInterrupt,
+ .InterruptState = SRAM2_MPC_InterruptState,
+ .LockDown = SRAM2_MPC_LockDown,
+};
+#endif /* RTE_CODE_SRAM2_MPC */
+
+#if (RTE_CODE_SRAM3_MPC)
+/* Ranges controlled by this SRAM3_MPC */
+static struct mpc_sie200_memory_range_t MPC_CODE_SRAM3_RANGE_S = {
+ .base = MPC_CODE_SRAM3_RANGE_BASE_S,
+ .limit = MPC_CODE_SRAM3_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_CODE_SRAM3_RANGE_NS = {
+ .base = MPC_CODE_SRAM3_RANGE_BASE_NS,
+ .limit = MPC_CODE_SRAM3_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_CODE_SRAM3_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_CODE_SRAM3_RANGE_LIST[MPC_CODE_SRAM3_RANGE_LIST_LEN]=
+ {&MPC_CODE_SRAM3_RANGE_S, &MPC_CODE_SRAM3_RANGE_NS};
+
+/* SRAM3_MPC Driver wrapper functions */
+static int32_t SRAM3_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_CODE_SRAM3_DEV_S,
+ MPC_CODE_SRAM3_RANGE_LIST,
+ MPC_CODE_SRAM3_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM3_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t SRAM3_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_CODE_SRAM3_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM3_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_CODE_SRAM3_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM3_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_CODE_SRAM3_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM3_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_CODE_SRAM3_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM3_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_CODE_SRAM3_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM3_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_CODE_SRAM3_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void SRAM3_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_CODE_SRAM3_DEV_S);
+}
+
+
+static void SRAM3_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_CODE_SRAM3_DEV_S);
+}
+
+static uint32_t SRAM3_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_CODE_SRAM3_DEV_S);
+}
+
+static int32_t SRAM3_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_CODE_SRAM3_DEV_S);
+}
+
+/* SRAM3_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_SRAM3_MPC;
+ARM_DRIVER_MPC Driver_SRAM3_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = SRAM3_MPC_Initialize,
+ .Uninitialize = SRAM3_MPC_Uninitialize,
+ .GetBlockSize = SRAM3_MPC_GetBlockSize,
+ .GetCtrlConfig = SRAM3_MPC_GetCtrlConfig,
+ .SetCtrlConfig = SRAM3_MPC_SetCtrlConfig,
+ .ConfigRegion = SRAM3_MPC_ConfigRegion,
+ .GetRegionConfig = SRAM3_MPC_GetRegionConfig,
+ .EnableInterrupt = SRAM3_MPC_EnableInterrupt,
+ .DisableInterrupt = SRAM3_MPC_DisableInterrupt,
+ .ClearInterrupt = SRAM3_MPC_ClearInterrupt,
+ .InterruptState = SRAM3_MPC_InterruptState,
+ .LockDown = SRAM3_MPC_LockDown,
+};
+#endif /* RTE_CODE_SRAM3_MPC */
diff --git a/platform/ext/target/sse_200_mps2/sse_200/cmsis_drivers/Driver_PPC.c b/platform/ext/target/sse_200_mps2/sse_200/cmsis_drivers/Driver_PPC.c
new file mode 100644
index 0000000..9787d05
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/cmsis_drivers/Driver_PPC.c
@@ -0,0 +1,883 @@
+/*
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Driver_PPC.h"
+
+#include "cmsis.h"
+#include "platform_retarget_dev.h"
+#include "RTE_Device.h"
+
+/* Driver version */
+#define ARM_PPC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+ ARM_PPC_API_VERSION,
+ ARM_PPC_DRV_VERSION
+};
+
+static ARM_DRIVER_VERSION ARM_PPC_GetVersion(void)
+{
+ return DriverVersion;
+}
+
+#if (RTE_AHB_PPCEXP0)
+/* AHB PPCEXP0 Driver wrapper functions */
+static int32_t AHB_PPCEXP0_Initialize(void)
+{
+ ppc_sse200_init(&AHB_PPCEXP0_DEV_S, AHB_PPC_EXP0);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP0_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP0_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&AHB_PPCEXP0_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t AHB_PPCEXP0_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&AHB_PPCEXP0_DEV_S, periph);
+}
+
+static uint32_t AHB_PPCEXP0_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP0_DEV_S, periph);
+}
+
+static int32_t AHB_PPCEXP0_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&AHB_PPCEXP0_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void AHB_PPCEXP0_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&AHB_PPCEXP0_DEV_S);
+}
+
+static void AHB_PPCEXP0_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&AHB_PPCEXP0_DEV_S);
+}
+
+static uint32_t AHB_PPCEXP0_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&AHB_PPCEXP0_DEV_S);
+}
+
+/* AHB PPCEXP0 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_AHB_PPCEXP0;
+ARM_DRIVER_PPC Driver_AHB_PPCEXP0 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = AHB_PPCEXP0_Initialize,
+ .Uninitialize = AHB_PPCEXP0_Uninitialize,
+ .ConfigPeriph = AHB_PPCEXP0_ConfigPeriph,
+ .IsPeriphSecure = AHB_PPCEXP0_IsPeriphSecure,
+ .IsPeriphPrivOnly = AHB_PPCEXP0_IsPeriphPrivOnly,
+ .EnableInterrupt = AHB_PPCEXP0_EnableInterrupt,
+ .DisableInterrupt = AHB_PPCEXP0_DisableInterrupt,
+ .ClearInterrupt = AHB_PPCEXP0_ClearInterrupt,
+ .InterruptState = AHB_PPCEXP0_InterruptState
+};
+#endif /* RTE_AHB_PPCEXP0 */
+
+#if (RTE_AHB_PPCEXP1)
+/* AHB PPCEXP1 Driver wrapper functions */
+static int32_t AHB_PPCEXP1_Initialize(void)
+{
+ ppc_sse200_init(&AHB_PPCEXP1_DEV_S, AHB_PPC_EXP1);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP1_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP1_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&AHB_PPCEXP1_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t AHB_PPCEXP1_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&AHB_PPCEXP1_DEV_S, periph);
+}
+
+static uint32_t AHB_PPCEXP1_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP1_DEV_S, periph);
+}
+
+static int32_t AHB_PPCEXP1_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&AHB_PPCEXP1_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void AHB_PPCEXP1_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&AHB_PPCEXP1_DEV_S);
+}
+
+static void AHB_PPCEXP1_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&AHB_PPCEXP1_DEV_S);
+}
+
+static uint32_t AHB_PPCEXP1_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&AHB_PPCEXP1_DEV_S);
+}
+
+/* AHB PPCEXP1 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_AHB_PPCEXP1;
+ARM_DRIVER_PPC Driver_AHB_PPCEXP1 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = AHB_PPCEXP1_Initialize,
+ .Uninitialize = AHB_PPCEXP1_Uninitialize,
+ .ConfigPeriph = AHB_PPCEXP1_ConfigPeriph,
+ .IsPeriphSecure = AHB_PPCEXP1_IsPeriphSecure,
+ .IsPeriphPrivOnly = AHB_PPCEXP1_IsPeriphPrivOnly,
+ .EnableInterrupt = AHB_PPCEXP1_EnableInterrupt,
+ .DisableInterrupt = AHB_PPCEXP1_DisableInterrupt,
+ .ClearInterrupt = AHB_PPCEXP1_ClearInterrupt,
+ .InterruptState = AHB_PPCEXP1_InterruptState
+};
+#endif /* RTE_AHB_PPCEXP1 */
+
+#if (RTE_AHB_PPCEXP2)
+/* AHB PPCEXP2 Driver wrapper functions */
+static int32_t AHB_PPCEXP2_Initialize(void)
+{
+ ppc_sse200_init(&AHB_PPCEXP2_DEV_S, AHB_PPC_EXP2);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP2_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP2_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&AHB_PPCEXP2_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t AHB_PPCEXP2_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&AHB_PPCEXP2_DEV_S, periph);
+}
+
+static uint32_t AHB_PPCEXP2_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP2_DEV_S, periph);
+}
+
+static int32_t AHB_PPCEXP2_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&AHB_PPCEXP2_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void AHB_PPCEXP2_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&AHB_PPCEXP2_DEV_S);
+}
+
+static void AHB_PPCEXP2_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&AHB_PPCEXP2_DEV_S);
+}
+
+static uint32_t AHB_PPCEXP2_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&AHB_PPCEXP2_DEV_S);
+}
+
+/* AHB PPCEXP2 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_AHB_PPCEXP2;
+ARM_DRIVER_PPC Driver_AHB_PPCEXP2 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = AHB_PPCEXP2_Initialize,
+ .Uninitialize = AHB_PPCEXP2_Uninitialize,
+ .ConfigPeriph = AHB_PPCEXP2_ConfigPeriph,
+ .IsPeriphSecure = AHB_PPCEXP2_IsPeriphSecure,
+ .IsPeriphPrivOnly = AHB_PPCEXP2_IsPeriphPrivOnly,
+ .EnableInterrupt = AHB_PPCEXP2_EnableInterrupt,
+ .DisableInterrupt = AHB_PPCEXP2_DisableInterrupt,
+ .ClearInterrupt = AHB_PPCEXP2_ClearInterrupt,
+ .InterruptState = AHB_PPCEXP2_InterruptState
+};
+#endif /* RTE_AHB_PPCEXP2 */
+
+#if (RTE_AHB_PPCEXP3)
+/* AHB PPCEXP3 Driver wrapper functions */
+static int32_t AHB_PPCEXP3_Initialize(void)
+{
+ ppc_sse200_init(&AHB_PPCEXP3_DEV_S, AHB_PPC_EXP3);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP3_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP3_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&AHB_PPCEXP3_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t AHB_PPCEXP3_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&AHB_PPCEXP3_DEV_S, periph);
+}
+
+static uint32_t AHB_PPCEXP3_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP3_DEV_S, periph);
+}
+
+static int32_t AHB_PPCEXP3_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&AHB_PPCEXP3_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void AHB_PPCEXP3_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&AHB_PPCEXP3_DEV_S);
+}
+
+static void AHB_PPCEXP3_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&AHB_PPCEXP3_DEV_S);
+}
+
+static uint32_t AHB_PPCEXP3_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&AHB_PPCEXP3_DEV_S);
+}
+
+/* AHB PPCEXP3 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_AHB_PPCEXP3;
+ARM_DRIVER_PPC Driver_AHB_PPCEXP3 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = AHB_PPCEXP3_Initialize,
+ .Uninitialize = AHB_PPCEXP3_Uninitialize,
+ .ConfigPeriph = AHB_PPCEXP3_ConfigPeriph,
+ .IsPeriphSecure = AHB_PPCEXP3_IsPeriphSecure,
+ .IsPeriphPrivOnly = AHB_PPCEXP3_IsPeriphPrivOnly,
+ .EnableInterrupt = AHB_PPCEXP3_EnableInterrupt,
+ .DisableInterrupt = AHB_PPCEXP3_DisableInterrupt,
+ .ClearInterrupt = AHB_PPCEXP3_ClearInterrupt,
+ .InterruptState = AHB_PPCEXP3_InterruptState
+};
+#endif /* RTE_AHB_PPCEXP3 */
+
+#if (RTE_APB_PPC0)
+/* APB PPC0 Driver wrapper functions */
+static int32_t APB_PPC0_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPC0_DEV_S, APB_PPC0);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPC0_Uninitialize(void)
+{
+ /* Nothing to be done*/
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPC0_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPC0_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPC0_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPC0_DEV_S, periph);
+}
+
+static uint32_t APB_PPC0_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPC0_DEV_S, periph);
+}
+
+static int32_t APB_PPC0_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPC0_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPC0_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPC0_DEV_S);
+}
+
+static void APB_PPC0_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPC0_DEV_S);
+}
+
+static uint32_t APB_PPC0_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPC0_DEV_S);
+}
+
+/* APB PPC0 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPC0;
+ARM_DRIVER_PPC Driver_APB_PPC0 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPC0_Initialize,
+ .Uninitialize = APB_PPC0_Uninitialize,
+ .ConfigPeriph = APB_PPC0_ConfigPeriph,
+ .IsPeriphSecure = APB_PPC0_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPC0_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPC0_EnableInterrupt,
+ .DisableInterrupt = APB_PPC0_DisableInterrupt,
+ .ClearInterrupt = APB_PPC0_ClearInterrupt,
+ .InterruptState = APB_PPC0_InterruptState
+};
+#endif /* RTE_APB_PPC0 */
+
+#if (RTE_APB_PPC1)
+/* APB PPC1 Driver wrapper functions */
+static int32_t APB_PPC1_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPC1_DEV_S, APB_PPC1);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPC1_Uninitialize(void)
+{
+ /* Nothing to be done*/
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPC1_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPC1_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPC1_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPC1_DEV_S, periph);
+}
+
+static uint32_t APB_PPC1_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPC1_DEV_S, periph);
+}
+static int32_t APB_PPC1_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPC1_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPC1_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPC1_DEV_S);
+}
+
+static void APB_PPC1_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPC1_DEV_S);
+}
+
+static uint32_t APB_PPC1_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPC1_DEV_S);
+}
+
+/* APB PPC1 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPC1;
+ARM_DRIVER_PPC Driver_APB_PPC1 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPC1_Initialize,
+ .Uninitialize = APB_PPC1_Uninitialize,
+ .ConfigPeriph = APB_PPC1_ConfigPeriph,
+ .IsPeriphSecure = APB_PPC1_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPC1_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPC1_EnableInterrupt,
+ .DisableInterrupt = APB_PPC1_DisableInterrupt,
+ .ClearInterrupt = APB_PPC1_ClearInterrupt,
+ .InterruptState = APB_PPC1_InterruptState
+};
+#endif /* RTE_APB_PPC1 */
+
+#if (RTE_APB_PPCEXP0)
+/* APB PPCEXP0 Driver wrapper functions */
+static int32_t APB_PPCEXP0_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPCEXP0_DEV_S, APB_PPC_EXP0);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP0_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP0_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPCEXP0_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPCEXP0_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPCEXP0_DEV_S, periph);
+}
+
+static uint32_t APB_PPCEXP0_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPCEXP0_DEV_S, periph);
+}
+
+static int32_t APB_PPCEXP0_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPCEXP0_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPCEXP0_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPCEXP0_DEV_S);
+}
+
+static void APB_PPCEXP0_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPCEXP0_DEV_S);
+}
+
+static uint32_t APB_PPCEXP0_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPCEXP0_DEV_S);
+}
+
+/* APB PPCEXP0 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP0;
+ARM_DRIVER_PPC Driver_APB_PPCEXP0 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPCEXP0_Initialize,
+ .Uninitialize = APB_PPCEXP0_Uninitialize,
+ .ConfigPeriph = APB_PPCEXP0_ConfigPeriph,
+ .IsPeriphSecure = APB_PPCEXP0_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPCEXP0_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPCEXP0_EnableInterrupt,
+ .DisableInterrupt = APB_PPCEXP0_DisableInterrupt,
+ .ClearInterrupt = APB_PPCEXP0_ClearInterrupt,
+ .InterruptState = APB_PPCEXP0_InterruptState
+};
+#endif /* RTE_APB_PPCEXP0 */
+
+#if (RTE_APB_PPCEXP1)
+/* APB PPCEXP1 Driver wrapper functions */
+static int32_t APB_PPCEXP1_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPCEXP1_DEV_S, APB_PPC_EXP1);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP1_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP1_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPCEXP1_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPCEXP1_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPCEXP1_DEV_S, periph);
+}
+
+static uint32_t APB_PPCEXP1_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPCEXP1_DEV_S, periph);
+}
+
+static int32_t APB_PPCEXP1_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPCEXP1_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPCEXP1_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPCEXP1_DEV_S);
+}
+
+static void APB_PPCEXP1_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPCEXP1_DEV_S);
+}
+
+static uint32_t APB_PPCEXP1_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPCEXP1_DEV_S);
+}
+
+/* APB PPCEXP1 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP1;
+ARM_DRIVER_PPC Driver_APB_PPCEXP1 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPCEXP1_Initialize,
+ .Uninitialize = APB_PPCEXP1_Uninitialize,
+ .ConfigPeriph = APB_PPCEXP1_ConfigPeriph,
+ .IsPeriphSecure = APB_PPCEXP1_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPCEXP1_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPCEXP1_EnableInterrupt,
+ .DisableInterrupt = APB_PPCEXP1_DisableInterrupt,
+ .ClearInterrupt = APB_PPCEXP1_ClearInterrupt,
+ .InterruptState = APB_PPCEXP1_InterruptState
+};
+#endif /* RTE_APB_PPCEXP1 */
+
+#if (RTE_APB_PPCEXP2)
+/* APB PPCEXP2 Driver wrapper functions */
+static int32_t APB_PPCEXP2_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPCEXP2_DEV_S, APB_PPC_EXP2);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP2_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP2_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPCEXP2_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPCEXP2_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPCEXP2_DEV_S, periph);
+}
+
+static uint32_t APB_PPCEXP2_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPCEXP2_DEV_S, periph);
+}
+
+static int32_t APB_PPCEXP2_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPCEXP2_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPCEXP2_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPCEXP2_DEV_S);
+}
+
+static void APB_PPCEXP2_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPCEXP2_DEV_S);
+}
+
+static uint32_t APB_PPCEXP2_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPCEXP2_DEV_S);
+}
+
+/* APB PPCEXP2 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP2;
+ARM_DRIVER_PPC Driver_APB_PPCEXP2 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPCEXP2_Initialize,
+ .Uninitialize = APB_PPCEXP2_Uninitialize,
+ .ConfigPeriph = APB_PPCEXP2_ConfigPeriph,
+ .IsPeriphSecure = APB_PPCEXP2_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPCEXP2_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPCEXP2_EnableInterrupt,
+ .DisableInterrupt = APB_PPCEXP2_DisableInterrupt,
+ .ClearInterrupt = APB_PPCEXP2_ClearInterrupt,
+ .InterruptState = APB_PPCEXP2_InterruptState
+};
+#endif /* RTE_APB_PPCEXP2 */
+
+#if (RTE_APB_PPCEXP3)
+/* APB PPCEXP3 Driver wrapper functions */
+static int32_t APB_PPCEXP3_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPCEXP3_DEV_S, APB_PPC_EXP3);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP3_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP3_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPCEXP3_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPCEXP3_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPCEXP3_DEV_S, periph);
+}
+
+static uint32_t APB_PPCEXP3_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPCEXP3_DEV_S, periph);
+}
+
+static int32_t APB_PPCEXP3_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPCEXP3_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPCEXP3_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPCEXP3_DEV_S);
+}
+
+static void APB_PPCEXP3_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPCEXP3_DEV_S);
+}
+
+static uint32_t APB_PPCEXP3_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPCEXP3_DEV_S);
+}
+
+/* APB PPCEXP3 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP3;
+ARM_DRIVER_PPC Driver_APB_PPCEXP3 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPCEXP3_Initialize,
+ .Uninitialize = APB_PPCEXP3_Uninitialize,
+ .ConfigPeriph = APB_PPCEXP3_ConfigPeriph,
+ .IsPeriphSecure = APB_PPCEXP3_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPCEXP3_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPCEXP3_EnableInterrupt,
+ .DisableInterrupt = APB_PPCEXP3_DisableInterrupt,
+ .ClearInterrupt = APB_PPCEXP3_ClearInterrupt,
+ .InterruptState = APB_PPCEXP3_InterruptState
+};
+#endif /* RTE_APB_PPCEXP3 */
diff --git a/platform/ext/target/sse_200_mps2/sse_200/cmsis_drivers/Driver_USART.c b/platform/ext/target/sse_200_mps2/sse_200/cmsis_drivers/Driver_USART.c
new file mode 100644
index 0000000..489708e
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/cmsis_drivers/Driver_USART.c
@@ -0,0 +1,719 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Driver_USART.h"
+
+#include "cmsis.h"
+#include "platform_retarget_dev.h"
+#include "RTE_Device.h"
+
+#ifndef ARG_UNUSED
+#define ARG_UNUSED(arg) (void)arg
+#endif
+
+/* Driver version */
+#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 2)
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+ ARM_USART_API_VERSION,
+ ARM_USART_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_USART_CAPABILITIES DriverCapabilities = {
+ 1, /* supports UART (Asynchronous) mode */
+ 0, /* supports Synchronous Master mode */
+ 0, /* supports Synchronous Slave mode */
+ 0, /* supports UART Single-wire mode */
+ 0, /* supports UART IrDA mode */
+ 0, /* supports UART Smart Card mode */
+ 0, /* Smart Card Clock generator available */
+ 0, /* RTS Flow Control available */
+ 0, /* CTS Flow Control available */
+ 0, /* Transmit completed event: \ref ARM_USARTx_EVENT_TX_COMPLETE */
+ 0, /* Signal receive character timeout event: \ref ARM_USARTx_EVENT_RX_TIMEOUT */
+ 0, /* RTS Line: 0=not available, 1=available */
+ 0, /* CTS Line: 0=not available, 1=available */
+ 0, /* DTR Line: 0=not available, 1=available */
+ 0, /* DSR Line: 0=not available, 1=available */
+ 0, /* DCD Line: 0=not available, 1=available */
+ 0, /* RI Line: 0=not available, 1=available */
+ 0, /* Signal CTS change event: \ref ARM_USARTx_EVENT_CTS */
+ 0, /* Signal DSR change event: \ref ARM_USARTx_EVENT_DSR */
+ 0, /* Signal DCD change event: \ref ARM_USARTx_EVENT_DCD */
+ 0, /* Signal RI change event: \ref ARM_USARTx_EVENT_RI */
+ 0 /* Reserved */
+};
+
+static ARM_DRIVER_VERSION ARM_USART_GetVersion(void)
+{
+ return DriverVersion;
+}
+
+static ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void)
+{
+ return DriverCapabilities;
+}
+
+typedef struct {
+ struct arm_uart_dev_t* dev; /* UART device structure */
+ uint32_t tx_nbr_bytes; /* Number of bytes transfered */
+ uint32_t rx_nbr_bytes; /* Number of bytes recevied */
+ ARM_USART_SignalEvent_t cb_event; /* Callback function for events */
+} UARTx_Resources;
+
+static int32_t ARM_USARTx_Initialize(UARTx_Resources* uart_dev)
+{
+ /* Initializes generic UART driver */
+ arm_uart_init(uart_dev->dev, PeripheralClock);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USARTx_PowerControl(UARTx_Resources* uart_dev,
+ ARM_POWER_STATE state)
+{
+ ARG_UNUSED(uart_dev);
+
+ switch (state) {
+ case ARM_POWER_OFF:
+ case ARM_POWER_LOW:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ case ARM_POWER_FULL:
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+ /* default: The default is not defined intentionally to force the
+ * compiler to check that all the enumeration values are
+ * covered in the switch.*/
+ }
+}
+
+static int32_t ARM_USARTx_Send(UARTx_Resources* uart_dev, const void *data,
+ uint32_t num)
+{
+ const uint8_t* p_data = (const uint8_t*)data;
+
+ if ((data == NULL) || (num == 0U)) {
+ /* Invalid parameters */
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ /* Resets previous TX counter */
+ uart_dev->tx_nbr_bytes = 0;
+
+ while(uart_dev->tx_nbr_bytes != num) {
+ /* Waits until UART is ready to transmit */
+ while(!arm_uart_tx_ready(uart_dev->dev)) {};
+
+ /* As UART is ready to transmit at this point, the write function can
+ * not return any transmit error */
+ (void)arm_uart_write(uart_dev->dev, *p_data);
+
+ uart_dev->tx_nbr_bytes++;
+ p_data++;
+ }
+
+ /* Waits until character is transmited */
+ while (!arm_uart_tx_ready(uart_dev->dev)){};
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USARTx_Receive(UARTx_Resources* uart_dev,
+ void *data, uint32_t num)
+{
+ uint8_t* p_data = (uint8_t*)data;
+
+ if ((data == NULL) || (num == 0U)) {
+ // Invalid parameters
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ /* Resets previous RX counter */
+ uart_dev->rx_nbr_bytes = 0;
+
+ while(uart_dev->rx_nbr_bytes != num) {
+ /* Waits until one character is received */
+ while (!arm_uart_rx_ready(uart_dev->dev)){};
+
+ /* As UART has received one byte, the read can not
+ * return any receive error at this point */
+ (void)arm_uart_read(uart_dev->dev, p_data);
+
+ uart_dev->rx_nbr_bytes++;
+ p_data++;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t ARM_USARTx_GetTxCount(UARTx_Resources* uart_dev)
+{
+ return uart_dev->tx_nbr_bytes;
+}
+
+static uint32_t ARM_USARTx_GetRxCount(UARTx_Resources* uart_dev)
+{
+ return uart_dev->rx_nbr_bytes;
+}
+
+static int32_t ARM_USARTx_Control(UARTx_Resources* uart_dev, uint32_t control,
+ uint32_t arg)
+{
+ switch (control & ARM_USART_CONTROL_Msk) {
+ case ARM_USART_MODE_ASYNCHRONOUS:
+ if(arm_uart_set_baudrate(uart_dev->dev, arg) != ARM_UART_ERR_NONE) {
+ return ARM_USART_ERROR_BAUDRATE;
+ }
+ break;
+ /* Unsupported command */
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ /* UART Data bits */
+ if(control & ARM_USART_DATA_BITS_Msk) {
+ /* Data bit is not configurable */
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ /* UART Parity */
+ if(control & ARM_USART_PARITY_Msk) {
+ /* Parity is not configurable */
+ return ARM_USART_ERROR_PARITY;
+ }
+
+ /* USART Stop bits */
+ if(control & ARM_USART_STOP_BITS_Msk) {
+ /* Stop bit is not configurable */
+ return ARM_USART_ERROR_STOP_BITS;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+#if (RTE_USART0)
+/* USART0 Driver wrapper functions */
+static UARTx_Resources USART0_DEV = {
+#if (__DOMAIN_NS == 1)
+ .dev = &ARM_UART0_DEV_NS,
+#else
+ .dev = &ARM_UART0_DEV_S,
+#endif
+ .tx_nbr_bytes = 0,
+ .rx_nbr_bytes = 0,
+ .cb_event = NULL,
+};
+
+static int32_t ARM_USART0_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+ USART0_DEV.cb_event = cb_event;
+
+ return ARM_USARTx_Initialize(&USART0_DEV);
+}
+
+static int32_t ARM_USART0_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART0_PowerControl(ARM_POWER_STATE state)
+{
+ return ARM_USARTx_PowerControl(&USART0_DEV, state);
+}
+
+static int32_t ARM_USART0_Send(const void *data, uint32_t num)
+{
+ return ARM_USARTx_Send(&USART0_DEV, data, num);
+}
+
+static int32_t ARM_USART0_Receive(void *data, uint32_t num)
+{
+ return ARM_USARTx_Receive(&USART0_DEV, data, num);
+}
+
+static int32_t ARM_USART0_Transfer(const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USART0_GetTxCount(void)
+{
+ return ARM_USARTx_GetTxCount(&USART0_DEV);
+}
+
+static uint32_t ARM_USART0_GetRxCount(void)
+{
+ return ARM_USARTx_GetRxCount(&USART0_DEV);
+}
+static int32_t ARM_USART0_Control(uint32_t control, uint32_t arg)
+{
+ return ARM_USARTx_Control(&USART0_DEV, control, arg);
+}
+
+static ARM_USART_STATUS ARM_USART0_GetStatus(void)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USART0_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USART0_GetModemStatus(void)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+extern ARM_DRIVER_USART Driver_USART0;
+ARM_DRIVER_USART Driver_USART0 = {
+ ARM_USART_GetVersion,
+ ARM_USART_GetCapabilities,
+ ARM_USART0_Initialize,
+ ARM_USART0_Uninitialize,
+ ARM_USART0_PowerControl,
+ ARM_USART0_Send,
+ ARM_USART0_Receive,
+ ARM_USART0_Transfer,
+ ARM_USART0_GetTxCount,
+ ARM_USART0_GetRxCount,
+ ARM_USART0_Control,
+ ARM_USART0_GetStatus,
+ ARM_USART0_SetModemControl,
+ ARM_USART0_GetModemStatus
+};
+#endif /* RTE_USART0 */
+
+#if (RTE_USART1)
+/* USART1 Driver wrapper functions */
+static UARTx_Resources USART1_DEV = {
+#if (__DOMAIN_NS == 1)
+ .dev = &ARM_UART1_DEV_NS,
+#else
+ .dev = &ARM_UART1_DEV_S,
+#endif
+ .tx_nbr_bytes = 0,
+ .rx_nbr_bytes = 0,
+ .cb_event = NULL,
+};
+
+static int32_t ARM_USART1_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+ USART1_DEV.cb_event = cb_event;
+
+ return ARM_USARTx_Initialize(&USART1_DEV);
+}
+
+static int32_t ARM_USART1_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART1_PowerControl(ARM_POWER_STATE state)
+{
+ return ARM_USARTx_PowerControl(&USART1_DEV, state);
+}
+
+static int32_t ARM_USART1_Send(const void *data, uint32_t num)
+{
+ return ARM_USARTx_Send(&USART1_DEV, data, num);
+}
+
+static int32_t ARM_USART1_Receive(void *data, uint32_t num)
+{
+ return ARM_USARTx_Receive(&USART1_DEV, data, num);
+}
+
+static int32_t ARM_USART1_Transfer(const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USART1_GetTxCount(void)
+{
+ return ARM_USARTx_GetTxCount(&USART1_DEV);
+}
+
+static uint32_t ARM_USART1_GetRxCount(void)
+{
+ return ARM_USARTx_GetRxCount(&USART1_DEV);
+}
+static int32_t ARM_USART1_Control(uint32_t control, uint32_t arg)
+{
+ return ARM_USARTx_Control(&USART1_DEV, control, arg);
+}
+
+static ARM_USART_STATUS ARM_USART1_GetStatus(void)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USART1_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USART1_GetModemStatus(void)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+extern ARM_DRIVER_USART Driver_USART1;
+ARM_DRIVER_USART Driver_USART1 = {
+ ARM_USART_GetVersion,
+ ARM_USART_GetCapabilities,
+ ARM_USART1_Initialize,
+ ARM_USART1_Uninitialize,
+ ARM_USART1_PowerControl,
+ ARM_USART1_Send,
+ ARM_USART1_Receive,
+ ARM_USART1_Transfer,
+ ARM_USART1_GetTxCount,
+ ARM_USART1_GetRxCount,
+ ARM_USART1_Control,
+ ARM_USART1_GetStatus,
+ ARM_USART1_SetModemControl,
+ ARM_USART1_GetModemStatus
+};
+#endif /* RTE_USART1 */
+
+#if (RTE_USART2)
+/* USART2 Driver wrapper functions */
+static UARTx_Resources USART2_DEV = {
+#if (__DOMAIN_NS == 1)
+ .dev = &ARM_UART2_DEV_NS,
+#else
+ .dev = &ARM_UART2_DEV_S,
+#endif
+ .tx_nbr_bytes = 0,
+ .rx_nbr_bytes = 0,
+ .cb_event = NULL,
+};
+
+static int32_t ARM_USART2_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+ USART2_DEV.cb_event = cb_event;
+
+ return ARM_USARTx_Initialize(&USART2_DEV);
+}
+
+static int32_t ARM_USART2_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART2_PowerControl(ARM_POWER_STATE state)
+{
+ return ARM_USARTx_PowerControl(&USART2_DEV, state);
+}
+
+static int32_t ARM_USART2_Send(const void *data, uint32_t num)
+{
+ return ARM_USARTx_Send(&USART2_DEV, data, num);
+}
+
+static int32_t ARM_USART2_Receive(void *data, uint32_t num)
+{
+ return ARM_USARTx_Receive(&USART2_DEV, data, num);
+}
+
+static int32_t ARM_USART2_Transfer(const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USART2_GetTxCount(void)
+{
+ return ARM_USARTx_GetTxCount(&USART2_DEV);
+}
+
+static uint32_t ARM_USART2_GetRxCount(void)
+{
+ return ARM_USARTx_GetRxCount(&USART2_DEV);
+}
+static int32_t ARM_USART2_Control(uint32_t control, uint32_t arg)
+{
+ return ARM_USARTx_Control(&USART2_DEV, control, arg);
+}
+
+static ARM_USART_STATUS ARM_USART2_GetStatus(void)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USART2_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USART2_GetModemStatus(void)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+extern ARM_DRIVER_USART Driver_USART2;
+ARM_DRIVER_USART Driver_USART2 = {
+ ARM_USART_GetVersion,
+ ARM_USART_GetCapabilities,
+ ARM_USART2_Initialize,
+ ARM_USART2_Uninitialize,
+ ARM_USART2_PowerControl,
+ ARM_USART2_Send,
+ ARM_USART2_Receive,
+ ARM_USART2_Transfer,
+ ARM_USART2_GetTxCount,
+ ARM_USART2_GetRxCount,
+ ARM_USART2_Control,
+ ARM_USART2_GetStatus,
+ ARM_USART2_SetModemControl,
+ ARM_USART2_GetModemStatus
+};
+#endif /* RTE_USART2 */
+
+#if (RTE_USART3)
+/* USART3 Driver wrapper functions */
+static UARTx_Resources USART3_DEV = {
+#if (__DOMAIN_NS == 1)
+ .dev = &ARM_UART3_DEV_NS,
+#else
+ .dev = &ARM_UART3_DEV_S,
+#endif
+ .tx_nbr_bytes = 0,
+ .rx_nbr_bytes = 0,
+ .cb_event = NULL,
+};
+
+static int32_t ARM_USART3_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+ USART3_DEV.cb_event = cb_event;
+
+ return ARM_USARTx_Initialize(&USART3_DEV);
+}
+
+static int32_t ARM_USART3_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART3_PowerControl(ARM_POWER_STATE state)
+{
+ return ARM_USARTx_PowerControl(&USART3_DEV, state);
+}
+
+static int32_t ARM_USART3_Send(const void *data, uint32_t num)
+{
+ return ARM_USARTx_Send(&USART3_DEV, data, num);
+}
+
+static int32_t ARM_USART3_Receive(void *data, uint32_t num)
+{
+ return ARM_USARTx_Receive(&USART3_DEV, data, num);
+}
+
+static int32_t ARM_USART3_Transfer(const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USART3_GetTxCount(void)
+{
+ return ARM_USARTx_GetTxCount(&USART3_DEV);
+}
+
+static uint32_t ARM_USART3_GetRxCount(void)
+{
+ return ARM_USARTx_GetRxCount(&USART3_DEV);
+}
+static int32_t ARM_USART3_Control(uint32_t control, uint32_t arg)
+{
+ return ARM_USARTx_Control(&USART3_DEV, control, arg);
+}
+
+static ARM_USART_STATUS ARM_USART3_GetStatus(void)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USART3_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USART3_GetModemStatus(void)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+extern ARM_DRIVER_USART Driver_USART3;
+ARM_DRIVER_USART Driver_USART3 = {
+ ARM_USART_GetVersion,
+ ARM_USART_GetCapabilities,
+ ARM_USART3_Initialize,
+ ARM_USART3_Uninitialize,
+ ARM_USART3_PowerControl,
+ ARM_USART3_Send,
+ ARM_USART3_Receive,
+ ARM_USART3_Transfer,
+ ARM_USART3_GetTxCount,
+ ARM_USART3_GetRxCount,
+ ARM_USART3_Control,
+ ARM_USART3_GetStatus,
+ ARM_USART3_SetModemControl,
+ ARM_USART3_GetModemStatus
+};
+#endif /* RTE_USART3 */
+
+#if (RTE_USART4)
+/* USART4 Driver wrapper functions */
+static UARTx_Resources USART4_DEV = {
+#if (__DOMAIN_NS == 1)
+ .dev = &ARM_UART4_DEV_NS,
+#else
+ .dev = &ARM_UART4_DEV_S,
+#endif
+ .tx_nbr_bytes = 0,
+ .rx_nbr_bytes = 0,
+ .cb_event = NULL,
+};
+
+static int32_t ARM_USART4_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+ USART4_DEV.cb_event = cb_event;
+
+ return ARM_USARTx_Initialize(&USART4_DEV);
+}
+
+static int32_t ARM_USART4_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART4_PowerControl(ARM_POWER_STATE state)
+{
+ return ARM_USARTx_PowerControl(&USART4_DEV, state);
+}
+
+static int32_t ARM_USART4_Send(const void *data, uint32_t num)
+{
+ return ARM_USARTx_Send(&USART4_DEV, data, num);
+}
+
+static int32_t ARM_USART4_Receive(void *data, uint32_t num)
+{
+ return ARM_USARTx_Receive(&USART4_DEV, data, num);
+}
+
+static int32_t ARM_USART4_Transfer(const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USART4_GetTxCount(void)
+{
+ return ARM_USARTx_GetTxCount(&USART4_DEV);
+}
+
+static uint32_t ARM_USART4_GetRxCount(void)
+{
+ return ARM_USARTx_GetRxCount(&USART4_DEV);
+}
+static int32_t ARM_USART4_Control(uint32_t control, uint32_t arg)
+{
+ return ARM_USARTx_Control(&USART4_DEV, control, arg);
+}
+
+static ARM_USART_STATUS ARM_USART4_GetStatus(void)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USART4_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USART4_GetModemStatus(void)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+extern ARM_DRIVER_USART Driver_USART4;
+ARM_DRIVER_USART Driver_USART4 = {
+ ARM_USART_GetVersion,
+ ARM_USART_GetCapabilities,
+ ARM_USART4_Initialize,
+ ARM_USART4_Uninitialize,
+ ARM_USART4_PowerControl,
+ ARM_USART4_Send,
+ ARM_USART4_Receive,
+ ARM_USART4_Transfer,
+ ARM_USART4_GetTxCount,
+ ARM_USART4_GetRxCount,
+ ARM_USART4_Control,
+ ARM_USART4_GetStatus,
+ ARM_USART4_SetModemControl,
+ ARM_USART4_GetModemStatus
+};
+#endif /* RTE_USART4 */
diff --git a/platform/ext/target/sse_200_mps2/sse_200/device_cfg.h b/platform/ext/target/sse_200_mps2/sse_200/device_cfg.h
new file mode 100644
index 0000000..62f19a0
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/device_cfg.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARM_LTD_DEVICE_CFG_H__
+#define __ARM_LTD_DEVICE_CFG_H__
+
+/**
+ * \file device_cfg.h
+ * \brief
+ * This is the default device configuration file with all peripherals
+ * defined and configured to be use via the secure and/or non-secure base
+ * address. This file is an example of how to define your own configuration
+ * file with the peripherals required for your application.
+ */
+
+/* ARM Memory Protection Controller (MPC) */
+#define MPC_ISRAM0_S
+#define MPC_ISRAM1_S
+#define MPC_ISRAM2_S
+#define MPC_ISRAM3_S
+#define MPC_CODE_SRAM1_S
+#define MPC_CODE_SRAM2_S
+#define MPC_CODE_SRAM3_S
+
+/* ARM Peripheral Protection Controllers (PPC) */
+#define AHB_PPCEXP0_S
+#define APB_PPC0_S
+#define APB_PPC1_S
+#define APB_PPCEXP0_S
+#define APB_PPCEXP1_S
+#define APB_PPCEXP2_S
+#define APB_PPCEXP3_S
+
+/* ARM UART */
+#define DEFAULT_UART_BAUDRATE 9600
+#define ARM_UART0_S
+#define ARM_UART0_NS
+#define ARM_UART1_S
+#define ARM_UART1_NS
+#define ARM_UART2_S
+#define ARM_UART2_NS
+#define ARM_UART3_S
+#define ARM_UART3_NS
+#define ARM_UART4_S
+#define ARM_UART4_NS
+
+/* CMSDK Timers */
+#define CMSDK_TIMER0_S
+#define CMSDK_TIMER0_NS
+#define CMSDK_TIMER1_S
+#define CMSDK_TIMER1_NS
+
+#endif /* __ARM_LTD_DEVICE_CFG_H__ */
diff --git a/platform/ext/target/sse_200_mps2/sse_200/native_drivers/arm_uart_drv.c b/platform/ext/target/sse_200_mps2/sse_200/native_drivers/arm_uart_drv.c
new file mode 100644
index 0000000..d61ae48
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/native_drivers/arm_uart_drv.c
@@ -0,0 +1,258 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_uart_drv.h"
+
+#include <stddef.h>
+
+/* UART register map structure */
+struct _arm_uart_reg_map_t {
+ volatile uint32_t data; /* Offset: 0x000 (R/W) data register */
+ volatile uint32_t state; /* Offset: 0x004 (R/W) status register */
+ volatile uint32_t ctrl; /* Offset: 0x008 (R/W) control register */
+ union {
+ volatile uint32_t intrstatus; /* Offset: 0x00c (R/ ) interrupt status
+ * register */
+ volatile uint32_t intrclear; /* Offset: 0x00c ( /W) interrupt clear
+ * register */
+ }intr_reg;
+ volatile uint32_t bauddiv; /* Offset: 0x010 (R/W) Baudrate divider
+ * register */
+};
+
+/* CTRL Register */
+#define ARM_UART_TX_EN (1ul << 0)
+#define ARM_UART_RX_EN (1ul << 1)
+#define ARM_UART_TX_INTR_EN (1ul << 2)
+#define ARM_UART_RX_INTR_EN (1ul << 3)
+
+/* STATE Register */
+#define ARM_UART_TX_BF (1ul << 0)
+#define ARM_UART_RX_BF (1ul << 1)
+
+/* INTSTATUS Register */
+#define ARM_UART_TX_INTR (1ul << 0)
+#define ARM_UART_RX_INTR (1ul << 1)
+
+/* UART state definitions */
+#define ARM_UART_INITIALIZED (1ul << 0)
+
+enum arm_uart_error_t arm_uart_init(struct arm_uart_dev_t* dev,
+ uint32_t system_clk)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+ if(system_clk == 0) {
+ return ARM_UART_ERR_INVALID_ARG;
+ }
+
+ /* Sets baudrate and system clock */
+ dev->data->system_clk = system_clk;
+ dev->data->baudrate = dev->cfg->default_baudrate;
+
+ /* Sets baudrate */
+ p_uart->bauddiv = (dev->data->system_clk / dev->cfg->default_baudrate);
+
+ /* Enables receiver and transmitter */
+ p_uart->ctrl = ARM_UART_RX_EN | ARM_UART_TX_EN;
+
+ dev->data->state = ARM_UART_INITIALIZED;
+
+ return ARM_UART_ERR_NONE;
+}
+
+enum arm_uart_error_t arm_uart_set_baudrate(struct arm_uart_dev_t* dev,
+ uint32_t baudrate)
+{
+ uint32_t bauddiv;
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(baudrate == 0) {
+ return ARM_UART_ERR_INVALID_BAUD;
+ }
+
+ if(!(dev->data->state & ARM_UART_INITIALIZED)) {
+ return ARM_UART_ERR_NOT_INIT;
+ }
+
+ /* Sets baudrate */
+ bauddiv = (dev->data->system_clk / baudrate);
+ dev->data->baudrate = baudrate;
+
+ /* Minimum bauddiv value */
+ if(bauddiv < 16) {
+ return ARM_UART_ERR_INVALID_BAUD;
+ }
+
+ p_uart->bauddiv = bauddiv;
+
+ return ARM_UART_ERR_NONE;
+}
+
+uint32_t arm_uart_get_baudrate(struct arm_uart_dev_t* dev)
+{
+ return dev->data->baudrate;
+}
+
+enum arm_uart_error_t arm_uart_set_clock(struct arm_uart_dev_t* dev,
+ uint32_t system_clk)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(system_clk == 0) {
+ return ARM_UART_ERR_INVALID_ARG;
+ }
+
+ if(!(dev->data->state & ARM_UART_INITIALIZED)) {
+ return ARM_UART_ERR_NOT_INIT;
+ }
+
+ /* Sets system clock */
+ dev->data->system_clk = system_clk;
+
+ /* Updates baudrate divider */
+ p_uart->bauddiv = (dev->data->system_clk / dev->data->baudrate);
+
+ /* Enables receiver and transmitter */
+ return ARM_UART_ERR_NONE;
+}
+
+enum arm_uart_error_t arm_uart_read(struct arm_uart_dev_t* dev, uint8_t* byte)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(!(p_uart->state & ARM_UART_RX_BF)) {
+ return ARM_UART_ERR_NOT_READY;
+ }
+
+ /* Reads data */
+ *byte = (uint8_t)p_uart->data;
+
+ return ARM_UART_ERR_NONE;
+}
+
+enum arm_uart_error_t arm_uart_write(struct arm_uart_dev_t* dev, uint8_t byte)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(p_uart->state & ARM_UART_TX_BF) {
+ return ARM_UART_ERR_NOT_READY;
+ }
+
+ /* Sends data */
+ p_uart->data = byte;
+
+ return ARM_UART_ERR_NONE;
+}
+
+enum arm_uart_error_t arm_uart_irq_tx_enable(struct arm_uart_dev_t* dev)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & ARM_UART_INITIALIZED)) {
+ return ARM_UART_ERR_NOT_INIT;
+ }
+
+ p_uart->ctrl |= ARM_UART_TX_INTR_EN;
+
+ return ARM_UART_ERR_NONE;
+}
+
+void arm_uart_irq_tx_disable(struct arm_uart_dev_t* dev)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(dev->data->state & ARM_UART_INITIALIZED ) {
+ p_uart->ctrl &= ~ARM_UART_TX_INTR_EN;
+ }
+}
+
+uint32_t arm_uart_tx_ready(struct arm_uart_dev_t* dev)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & ARM_UART_INITIALIZED)) {
+ return 0;
+ }
+
+ return !(p_uart->state & ARM_UART_TX_BF);
+}
+
+enum arm_uart_error_t arm_uart_irq_rx_enable(struct arm_uart_dev_t* dev)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & ARM_UART_INITIALIZED)) {
+ return ARM_UART_ERR_NOT_INIT;
+ }
+
+ p_uart->ctrl |= ARM_UART_RX_INTR_EN;
+
+ return ARM_UART_ERR_NONE;
+}
+
+void arm_uart_irq_rx_disable(struct arm_uart_dev_t* dev)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(dev->data->state & ARM_UART_INITIALIZED) {
+ p_uart->ctrl &= ~ARM_UART_RX_INTR_EN;
+ }
+}
+
+uint32_t arm_uart_rx_ready(struct arm_uart_dev_t* dev)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & ARM_UART_INITIALIZED)) {
+ return 0;
+ }
+
+ return (p_uart->state & ARM_UART_RX_BF);
+}
+
+void arm_uart_clear_interrupt(struct arm_uart_dev_t* dev,
+ enum arm_uart_irq_t irq)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(dev->data->state & ARM_UART_INITIALIZED) {
+ /* Clears pending interrupts */
+ switch(irq) {
+ case ARM_UART_IRQ_RX:
+ p_uart->intr_reg.intrclear = ARM_UART_RX_INTR;
+ break;
+ case ARM_UART_IRQ_TX:
+ p_uart->intr_reg.intrclear = ARM_UART_TX_INTR;
+ break;
+ case ARM_UART_IRQ_COMBINED:
+ p_uart->intr_reg.intrclear = (ARM_UART_RX_INTR | ARM_UART_TX_INTR);
+ break;
+ /* default: not defined to force all cases to be handled */
+ }
+ }
+}
diff --git a/platform/ext/target/sse_200_mps2/sse_200/native_drivers/arm_uart_drv.h b/platform/ext/target/sse_200_mps2/sse_200/native_drivers/arm_uart_drv.h
new file mode 100644
index 0000000..64d8200
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/native_drivers/arm_uart_drv.h
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file arm_uart_drv.h
+ * \brief Generic driver for ARM UART.
+ */
+
+#ifndef __ARM_UART_DRV_H__
+#define __ARM_UART_DRV_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ARM UART device configuration structure */
+struct arm_uart_dev_cfg_t {
+ const uint32_t base; /*!< UART base address */
+ const uint32_t default_baudrate; /*!< Default baudrate */
+};
+
+/* ARM UART device data structure */
+struct arm_uart_dev_data_t {
+ uint32_t state; /*!< Indicates if the uart driver
+ is initialized and enabled */
+ uint32_t system_clk; /*!< System clock */
+ uint32_t baudrate; /*!< Baudrate */
+};
+
+/* ARM UART device structure */
+struct arm_uart_dev_t {
+ const struct arm_uart_dev_cfg_t* const cfg; /*!< UART configuration */
+ struct arm_uart_dev_data_t* const data; /*!< UART data */
+};
+
+/* ARM UART enumeration types */
+enum arm_uart_error_t {
+ ARM_UART_ERR_NONE = 0, /*!< No error */
+ ARM_UART_ERR_INVALID_ARG, /*!< Error invalid input argument */
+ ARM_UART_ERR_INVALID_BAUD, /*!< Invalid baudrate */
+ ARM_UART_ERR_NOT_INIT, /*!< Error UART not initialized */
+ ARM_UART_ERR_NOT_READY, /*!< Error UART not ready */
+};
+
+enum arm_uart_irq_t {
+ ARM_UART_IRQ_RX, /*!< RX interrupt source */
+ ARM_UART_IRQ_TX, /*!< TX interrupt source */
+ ARM_UART_IRQ_COMBINED /*!< RX-TX combined interrupt source */
+};
+
+/**
+ * \brief Initializes UART. It uses the default baudrate to configure
+ * the peripheral at this point.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ * \param[in] system_clk System clock used by the device.
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_uart_error_t arm_uart_init(struct arm_uart_dev_t* dev,
+ uint32_t system_clk);
+
+/**
+ * \brief Sets the UART baudrate.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ * \param[in] baudrate New baudrate.
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_uart_error_t arm_uart_set_baudrate(struct arm_uart_dev_t* dev,
+ uint32_t baudrate);
+
+/**
+ * \brief Gets the UART baudrate.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ *
+ * \return Returns the UART baudrate.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t arm_uart_get_baudrate(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Sets system clock.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ * \param[in] system_clk System clock used by the device.
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_uart_error_t arm_uart_set_clock(struct arm_uart_dev_t* dev,
+ uint32_t system_clk);
+/**
+ * \brief Reads one byte from UART dev.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ * \param[in] byte Pointer to byte.
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note For better performance, this function doesn't check if dev and byte
+ * pointer are NULL, and if the driver is initialized.
+ */
+enum arm_uart_error_t arm_uart_read(struct arm_uart_dev_t* dev, uint8_t* byte);
+
+/**
+ * \brief Writes a byte to UART dev.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ * \param[in] byte Byte to write.
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note For better performance, this function doesn't check if dev is NULL and
+ * if the driver is initialized to have better performance.
+ */
+enum arm_uart_error_t arm_uart_write(struct arm_uart_dev_t* dev, uint8_t byte);
+
+/**
+ * \brief Enables TX interrupt.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_uart_error_t arm_uart_irq_tx_enable(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Disables TX interrupt.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void arm_uart_irq_tx_disable(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Verifies if Tx is ready to send more data.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ *
+ * \return 1 if TX is ready, 0 otherwise.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t arm_uart_tx_ready(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Enables RX interrupt.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_uart_error_t arm_uart_irq_rx_enable(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Disables RX interrupt
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void arm_uart_irq_rx_disable(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Verifies if Rx has data.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ *
+ * \return 1 if RX has data, 0 otherwise.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t arm_uart_rx_ready(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Clears UART interrupt.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ * \param[in] irq IRQ source to clean \ref arm_uart_irq_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void arm_uart_clear_interrupt(struct arm_uart_dev_t* dev,
+ enum arm_uart_irq_t irq);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __ARM_UART_DRV_H__ */
diff --git a/platform/ext/target/sse_200_mps2/sse_200/native_drivers/mpc_sie200_drv.c b/platform/ext/target/sse_200_mps2/sse_200/native_drivers/mpc_sie200_drv.c
new file mode 100644
index 0000000..e842681
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/native_drivers/mpc_sie200_drv.c
@@ -0,0 +1,656 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mpc_sie200_drv.h"
+
+#include <stddef.h>
+
+#include "cmsis.h"
+
+#define MPC_SIE200_BLK_CFG_OFFSET 5U
+
+#define MPC_SIE200_CTRL_SEC_RESP (1UL << 4UL) /* MPC fault triggers a
+ * bus error */
+#define MPC_SIE200_CTRL_AUTOINCREMENT (1UL << 8UL) /* BLK_IDX auto increment */
+#define MPC_SIE200_CTRL_SEC_LOCK_DOWN (1UL << 31UL) /* MPC Security lock down */
+
+/* ARM MPC interrupt */
+#define MPC_SIE200_INT_EN 1UL
+#define MPC_SIE200_INT_STAT 1UL
+
+/* ARM MPC state definitions */
+#define MPC_SIE200_INITIALIZED (1 << 0)
+
+/* Error code returned by the internal driver functions */
+enum mpc_sie200_intern_error_t{
+ MPC_SIE200_INTERN_ERR_NONE = MPC_SIE200_ERR_NONE,
+ MPC_SIE200_INTERN_ERR_NOT_IN_RANGE = MPC_SIE200_ERR_NOT_IN_RANGE,
+ MPC_SIE200_INTERN_ERR_NOT_ALIGNED = MPC_SIE200_ERR_NOT_ALIGNED,
+ MPC_SIE200_INTERN_ERR_INVALID_RANGE = MPC_SIE200_ERR_INVALID_RANGE,
+ MPC_INTERN_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE =
+ MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE,
+ /* Calculated block index
+ is higher than the maximum allowed by the MPC. It should never
+ happen unless the controlled ranges of the MPC are misconfigured
+ in the driver or if the IP has not enough LUTs to cover the
+ range, due to wrong reported block size for example.
+ */
+ MPC_SIE200_INTERN_ERR_BLK_IDX_TOO_HIGH = -1,
+
+};
+
+/* ARM MPC memory mapped register access structure */
+struct mpc_sie200_reg_map_t {
+ volatile uint32_t ctrl; /* (R/W) MPC Control */
+ volatile uint32_t reserved[3];/* Reserved */
+ volatile uint32_t blk_max; /* (R/ ) Maximum value of block based index */
+ volatile uint32_t blk_cfg; /* (R/ ) Block configuration */
+ volatile uint32_t blk_idx; /* (R/W) Index value for accessing block
+ * based look up table */
+ volatile uint32_t blk_lutn; /* (R/W) Block based gating
+ * Look Up Table (LUT) */
+ volatile uint32_t int_stat; /* (R/ ) Interrupt state */
+ volatile uint32_t int_clear; /* ( /W) Interrupt clear */
+ volatile uint32_t int_en; /* (R/W) Interrupt enable */
+ volatile uint32_t int_info1; /* (R/ ) Interrupt information 1 */
+ volatile uint32_t int_info2; /* (R/ ) Interrupt information 2 */
+ volatile uint32_t int_set; /* ( /W) Interrupt set. Debug purpose only */
+ volatile uint32_t reserved2[997]; /* Reserved */
+ volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */
+ volatile uint32_t pidr5; /* (R/ ) Peripheral ID 5 */
+ volatile uint32_t pidr6; /* (R/ ) Peripheral ID 6 */
+ volatile uint32_t pidr7; /* (R/ ) Peripheral ID 7 */
+ volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */
+ volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */
+ volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */
+ volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */
+ volatile uint32_t cidr0; /* (R/ ) Component ID 0 */
+ volatile uint32_t cidr1; /* (R/ ) Component ID 1 */
+ volatile uint32_t cidr2; /* (R/ ) Component ID 2 */
+ volatile uint32_t cidr3; /* (R/ ) Component ID 3 */
+};
+
+/*
+ * Checks if the address is controlled by the MPC and returns
+ * the range index in which it is contained.
+ *
+ * \param[in] dev MPC device to initalize \ref mpc_sie200_dev_t
+ * \param[in] addr Address to check if it is controlled by MPC.
+ * \param[out] addr_range Range index in which it is contained.
+ *
+ * \return True if the base is controller by the range list, false otherwise.
+ */
+static uint32_t is_ctrl_by_range_list(struct mpc_sie200_dev_t* dev, uint32_t addr,
+ const struct mpc_sie200_memory_range_t** addr_range)
+{
+ uint32_t i;
+ const struct mpc_sie200_memory_range_t* range;
+
+ for(i = 0; i < dev->data->nbr_of_ranges; i++) {
+ range = dev->data->range_list[i];
+ if(addr >= range->base && addr <= range->limit) {
+ *addr_range = range;
+ return 1;
+ }
+ }
+ return 0;
+}
+
+/*
+ * Gets the masks selecting the bits in the LUT of the MPC corresponding
+ * to the base address (included) up to the limit address (included)
+ *
+ * \param[in] mpc_dev The MPC device.
+ * \param[in] base Address in a range controlled by this MPC
+ * (included), aligned on block size.
+ * \param[in] limit Address in a range controlled by this MPC
+ * (included), aligned on block size.
+ * \param[out] range Memory range in which the base address and
+ * limit are.
+ * \param[out] first_word_idx Index of the first touched word in the LUT.
+ * \param[out] nr_words Number of words used in the LUT. If 1, only
+ * first_word_mask is valid and limit_word_mask
+ * must not be used.
+ * \param[out] first_word_mask First word mask in the LUT will be stored here.
+ * \param[out] limit_word_mask Limit word mask in the LUT will be stored here.
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_intern_error_t
+ */
+static enum mpc_sie200_intern_error_t get_lut_masks(
+ struct mpc_sie200_dev_t* dev,
+ const uint32_t base, const uint32_t limit,
+ const struct mpc_sie200_memory_range_t** range,
+ uint32_t *first_word_idx,
+ uint32_t *nr_words,
+ uint32_t *first_word_mask,
+ uint32_t *limit_word_mask)
+{
+ const struct mpc_sie200_memory_range_t* base_range;
+ uint32_t block_size;
+ uint32_t base_block_idx;
+ uint32_t base_word_idx;
+ uint32_t blk_max;
+ const struct mpc_sie200_memory_range_t* limit_range;
+ uint32_t limit_block_idx;
+ uint32_t limit_word_idx;
+ uint32_t mask;
+ uint32_t norm_base;
+ uint32_t norm_limit;
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ /*
+ * Check that the addresses are within the controlled regions
+ * of this MPC
+ */
+ if(!is_ctrl_by_range_list(dev, base, &base_range) ||
+ !is_ctrl_by_range_list(dev, limit, &limit_range)) {
+ return MPC_SIE200_INTERN_ERR_NOT_IN_RANGE;
+ }
+
+ /* Base and limit should be part of the same range */
+ if(base_range != limit_range) {
+ return MPC_SIE200_INTERN_ERR_INVALID_RANGE;
+ }
+ *range = base_range;
+
+ block_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET));
+
+ /* Base and limit+1 addresses must be aligned on the MPC block size */
+ if(base % block_size || (limit+1) % block_size) {
+ return MPC_SIE200_INTERN_ERR_NOT_ALIGNED;
+ }
+
+ /*
+ * Get a normalized address that is an offset from the beginning
+ * of the lowest range controlled by the MPC
+ */
+ norm_base = (base - base_range->base);
+ norm_limit = (limit - base_range->base);
+
+ /*
+ * Calculate block index and to which 32 bits word it belongs
+ */
+ limit_block_idx = norm_limit/block_size;
+ limit_word_idx = limit_block_idx/32;
+
+ base_block_idx = norm_base/block_size;
+ base_word_idx = base_block_idx/32;
+
+ if(base_block_idx > limit_block_idx) {
+ return MPC_SIE200_INTERN_ERR_INVALID_RANGE;
+ }
+
+ /* Transmit the information to the caller */
+ *nr_words = limit_word_idx - base_word_idx + 1;
+ *first_word_idx = base_word_idx;
+
+ /* Limit to the highest block that can be configured */
+ blk_max = p_mpc->blk_max;
+
+ if((limit_word_idx > blk_max) || (base_word_idx > blk_max)) {
+ return MPC_SIE200_INTERN_ERR_BLK_IDX_TOO_HIGH;
+ }
+
+ /*
+ * Create the mask for the first word to only select the limit N bits
+ */
+ *first_word_mask = ~((1 << (base_block_idx % 32)) - 1);
+
+ /*
+ * Create the mask for the limit word to select only the first M bits.
+ */
+ *limit_word_mask = (1 << ((limit_block_idx+1) % 32)) - 1;
+ /*
+ * If limit_word_mask is 0, it means that the limit touched block index is
+ * the limit in its word, so the limit word mask has all its bits selected
+ */
+ if(*limit_word_mask == 0) {
+ *limit_word_mask = 0xFFFFFFFF;
+ }
+
+ /*
+ * If the blocks to configure are all packed in one word, only
+ * touch this word.
+ * Code using the computed masks should test if this mask
+ * is non-zero, and if so, only use this one instead of the limit_word_mask
+ * and first_word_mask.
+ * As the only bits that are the same in both masks are the 1 that we want
+ * to select, just use XOR to extract them.
+ */
+ if(base_word_idx == limit_word_idx) {
+ mask = ~(*first_word_mask ^ *limit_word_mask);
+ *first_word_mask = mask;
+ *limit_word_mask = mask;
+ }
+
+ return MPC_SIE200_INTERN_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_init(struct mpc_sie200_dev_t* dev,
+ const struct mpc_sie200_memory_range_t** range_list,
+ uint8_t nbr_of_ranges)
+{
+ if((range_list == NULL) || (nbr_of_ranges == 0)) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ dev->data->range_list = range_list;
+ dev->data->nbr_of_ranges = nbr_of_ranges;
+ dev->data->state = MPC_SIE200_INITIALIZED;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_get_block_size(struct mpc_sie200_dev_t* dev,
+ uint32_t* blk_size)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ if(blk_size == 0) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ /* Calculate the block size in byte according to the manual */
+ *blk_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET));
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_config_region(struct mpc_sie200_dev_t* dev,
+ const uint32_t base,
+ const uint32_t limit,
+ enum mpc_sie200_sec_attr_t attr)
+{
+ enum mpc_sie200_intern_error_t error;
+ uint32_t first_word_idx;
+ uint32_t first_word_mask;
+ uint32_t i;
+ uint32_t limit_word_mask;
+ uint32_t limit_word_idx;
+ uint32_t nr_words;
+ const struct mpc_sie200_memory_range_t* range;
+ uint32_t word_value;
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ /* Sanity check to make sure the given range is within this MPCs range */
+ if ((dev->data->range_list[attr]->base > base) ||
+ (dev->data->range_list[attr]->limit < limit) ) {
+ return MPC_SIE200_ERR_NOT_IN_RANGE;
+ }
+
+ /* Get the bitmasks used to select the bits in the LUT */
+ error = get_lut_masks(dev, base, limit, &range, &first_word_idx, &nr_words,
+ &first_word_mask, &limit_word_mask);
+
+ limit_word_idx = first_word_idx + nr_words - 1;
+
+ if(error != MPC_SIE200_INTERN_ERR_NONE) {
+ /* Map internal error code lower than 0 to a generic errpr */
+ if(error < 0) {
+ return MPC_SIE200_ERR_INVALID_RANGE;
+ }
+ return (enum mpc_sie200_error_t)error;
+ }
+
+ /*
+ * The memory range should allow accesses in with the wanted security
+ * attribute if it requires special attribute for successfull accesses
+ */
+ if(range->attr != attr) {
+ return MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE;
+ }
+
+ /*
+ * Starts changing actual configuration so issue DMB to ensure every
+ * transaction has completed by now
+ */
+ __DMB();
+
+ /* Set the block index to the first word that will be updated */
+ p_mpc->blk_idx = first_word_idx;
+
+ /* If only one word needs to be touched in the LUT */
+ if(nr_words == 1) {
+ word_value = p_mpc->blk_lutn;
+ if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) {
+ word_value |= first_word_mask;
+ } else {
+ word_value &= ~first_word_mask;
+ }
+
+ /*
+ * Set the index again because full word read or write could have
+ * incremented it
+ */
+ p_mpc->blk_idx = first_word_idx;
+ p_mpc->blk_lutn = word_value;
+
+ /* Commit the configuration change */
+ __DSB();
+ __ISB();
+
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ /* First word */
+ word_value = p_mpc->blk_lutn;
+ if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) {
+ word_value |= first_word_mask;
+ } else {
+ word_value &= ~first_word_mask;
+ }
+ /*
+ * Set the index again because full word read or write could have
+ * incremented it
+ */
+ p_mpc->blk_idx = first_word_idx;
+ /* Partially configure the first word */
+ p_mpc->blk_lutn = word_value;
+
+ /* Fully configure the intermediate words if there are any */
+ for(i=first_word_idx+1; i<limit_word_idx; i++) {
+ p_mpc->blk_idx = i;
+ if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) {
+ p_mpc->blk_lutn = 0xFFFFFFFF;
+ } else {
+ p_mpc->blk_lutn = 0x00000000;
+ }
+ }
+
+ /* Partially configure the limit word */
+ p_mpc->blk_idx = limit_word_idx;
+ word_value = p_mpc->blk_lutn;
+ if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) {
+ word_value |= limit_word_mask;
+ } else {
+ word_value &= ~limit_word_mask;
+ }
+ p_mpc->blk_idx = limit_word_idx;
+ p_mpc->blk_lutn = word_value;
+
+ /* Commit the configuration change */
+ __DSB();
+ __ISB();
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_get_region_config(
+ struct mpc_sie200_dev_t* dev,
+ uint32_t base, uint32_t limit,
+ enum mpc_sie200_sec_attr_t* attr)
+{
+ enum mpc_sie200_sec_attr_t attr_prev;
+ uint32_t block_size;
+ uint32_t block_size_mask;
+ enum mpc_sie200_intern_error_t error;
+ uint32_t first_word_idx;
+ uint32_t first_word_mask;
+ uint32_t i;
+ uint32_t limit_word_idx;
+ uint32_t limit_word_mask;
+ uint32_t nr_words;
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+ const struct mpc_sie200_memory_range_t* range;
+ uint32_t word_value;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ if(attr == 0) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ /*
+ * Initialize the security attribute to mixed in case of early
+ * termination of this function. A caller that does not check the
+ * returned error will act as if it does not know anything about the
+ * region queried, which is the safest bet
+ */
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+
+ /*
+ * If the base and limit are not aligned, align them and make sure
+ * that the resulting region fully includes the original region
+ */
+ block_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET));
+
+ block_size_mask = block_size - 1;
+ base &= ~(block_size_mask);
+ limit &= ~(block_size_mask);
+ limit += block_size - 1; /* Round to the upper block address,
+ * and then remove one to get the preceding
+ * address.
+ */
+
+ /* Get the bitmasks used to select the bits in the LUT */
+ error = get_lut_masks(dev, base, limit, &range, &first_word_idx, &nr_words,
+ &first_word_mask, &limit_word_mask);
+
+ limit_word_idx = first_word_idx+nr_words - 1;
+
+ if(error != MPC_SIE200_INTERN_ERR_NONE) {
+ /* Map internal error code lower than 0 to generic error */
+ if(error < 0) {
+ return MPC_SIE200_ERR_INVALID_RANGE;
+ }
+ return (enum mpc_sie200_error_t)error;
+ }
+
+ /* Set the block index to the first word that will be updated */
+ p_mpc->blk_idx = first_word_idx;
+
+ /* If only one word needs to be touched in the LUT */
+ if(nr_words == 1) {
+ word_value = p_mpc->blk_lutn;
+ word_value &= first_word_mask;
+ if(word_value == 0) {
+ *attr = MPC_SIE200_SEC_ATTR_SECURE;
+ /*
+ * If there are differences between the mask and the word value,
+ * it means that the security attributes of blocks are mixed
+ */
+ } else if(word_value ^ first_word_mask) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ } else {
+ *attr = MPC_SIE200_SEC_ATTR_NONSECURE;
+ }
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ /* Get the partial configuration of the first word */
+ word_value = p_mpc->blk_lutn & first_word_mask;
+ if(word_value == 0x00000000) {
+ *attr = MPC_SIE200_SEC_ATTR_SECURE;
+ } else if(word_value ^ first_word_mask) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ /*
+ * Bail out as the security attribute will be the same regardless
+ * of the configuration of other blocks
+ */
+ return MPC_SIE200_ERR_NONE;
+ } else {
+ *attr = MPC_SIE200_SEC_ATTR_NONSECURE;
+ }
+ /*
+ * Store the current found attribute, to check that all the blocks indeed
+ * have the same security attribute.
+ */
+ attr_prev = *attr;
+
+ /* Get the configuration of the intermediate words if there are any */
+ for(i=first_word_idx+1; i<limit_word_idx; i++) {
+ p_mpc->blk_idx = i;
+ word_value = p_mpc->blk_lutn;
+ if(word_value == 0x00000000) {
+ *attr = MPC_SIE200_SEC_ATTR_SECURE;
+ } else if(word_value == 0xFFFFFFFF) {
+ *attr = MPC_SIE200_SEC_ATTR_NONSECURE;
+ } else {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ /* If the attribute is different than the one found before, bail out */
+ if(*attr != attr_prev) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ return MPC_SIE200_ERR_NONE;
+ }
+ attr_prev = *attr;
+ }
+
+ /* Get the partial configuration of the limit word */
+ p_mpc->blk_idx = limit_word_idx;
+ word_value = p_mpc->blk_lutn & limit_word_mask;
+ if(word_value == 0x00000000) {
+ *attr = MPC_SIE200_SEC_ATTR_SECURE;
+ } else if(word_value ^ first_word_mask) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ return MPC_SIE200_ERR_NONE;
+ } else {
+ *attr = MPC_SIE200_SEC_ATTR_NONSECURE;
+ }
+
+ if(*attr != attr_prev) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_get_ctrl(struct mpc_sie200_dev_t* dev,
+ uint32_t* ctrl_val)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ if(ctrl_val == 0) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ *ctrl_val = p_mpc->ctrl;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_set_ctrl(struct mpc_sie200_dev_t* dev,
+ uint32_t mpc_ctrl)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ p_mpc->ctrl = mpc_ctrl;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_get_sec_resp(struct mpc_sie200_dev_t* dev,
+ enum mpc_sie200_sec_resp_t* sec_rep)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ if(sec_rep == 0) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ if(p_mpc->ctrl & MPC_SIE200_CTRL_SEC_RESP) {
+ *sec_rep = MPC_SIE200_RESP_BUS_ERROR;
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ *sec_rep = MPC_SIE200_RESP_RAZ_WI;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_irq_enable(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ p_mpc->int_en |= MPC_SIE200_INT_EN;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+void mpc_sie200_irq_disable(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ p_mpc->int_en &= ~MPC_SIE200_INT_EN;
+}
+
+void mpc_sie200_clear_irq(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ p_mpc->int_clear = MPC_SIE200_INT_EN;
+}
+
+uint32_t mpc_sie200_irq_state(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ return (p_mpc->int_stat & MPC_SIE200_INT_STAT);
+}
+
+enum mpc_sie200_error_t mpc_sie200_lock_down(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ p_mpc->ctrl |= (MPC_SIE200_CTRL_AUTOINCREMENT
+ | MPC_SIE200_CTRL_SEC_LOCK_DOWN);
+
+ return MPC_SIE200_ERR_NONE;
+}
diff --git a/platform/ext/target/sse_200_mps2/sse_200/native_drivers/mpc_sie200_drv.h b/platform/ext/target/sse_200_mps2/sse_200/native_drivers/mpc_sie200_drv.h
new file mode 100644
index 0000000..02bd1d9
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/native_drivers/mpc_sie200_drv.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file mpc_sie200_drv.h
+ * \brief Generic driver for ARM SIE 200 Memory Protection
+ * Controllers (MPC).
+ */
+
+#ifndef __MPC_SIE_200_DRV_H__
+#define __MPC_SIE_200_DRV_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Error code returned by the driver functions */
+enum mpc_sie200_error_t {
+ MPC_SIE200_ERR_NONE, /*!< No error */
+ MPC_SIE200_INVALID_ARG, /*!< MPC invalid input arguments */
+ MPC_SIE200_NOT_INIT, /*!< MPC not initialized */
+ MPC_SIE200_ERR_NOT_IN_RANGE, /*!< Address does not belong to a range
+ * controlled by the MPC */
+ MPC_SIE200_ERR_NOT_ALIGNED, /*!< Address is not aligned on the block size
+ * of this MPC */
+ MPC_SIE200_ERR_INVALID_RANGE, /*!< The given address range to configure
+ * is invalid. This could be because:
+ * - The base and limit swapped
+ * - The base and limit addresses
+ * are in different ranges */
+ MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE, /*!< The given range cannot be
+ * accessed with the wanted
+ * security attributes */
+};
+
+/* Security attribute used in various place of the API */
+enum mpc_sie200_sec_attr_t {
+ MPC_SIE200_SEC_ATTR_SECURE, /*!< Secure attribute */
+ MPC_SIE200_SEC_ATTR_NONSECURE, /*!< Non-secure attribute */
+ /*!< Used when getting the configuration of a memory range and some blocks
+ * are secure whereas some other are non secure */
+ MPC_SIE200_SEC_ATTR_MIXED,
+};
+
+/* What can happen when trying to do an illegal memory access */
+enum mpc_sie200_sec_resp_t {
+ MPC_SIE200_RESP_RAZ_WI, /*!< Read As Zero, Write Ignored */
+ MPC_SIE200_RESP_BUS_ERROR /*!< Bus error */
+};
+
+/* Description of a memory range controlled by the MPC */
+struct mpc_sie200_memory_range_t {
+ const uint32_t base; /*!< Base address (included in the range) */
+ const uint32_t limit; /*!< Limit address (excluded in the range) */
+ const enum mpc_sie200_sec_attr_t attr; /*!< Optional security attribute
+ needed to be matched when
+ accessing this range.
+ For example, the non-secure
+ alias of a memory region can not
+ be accessed using secure access,
+ and configuring the MPC to
+ secure using that range will not
+ be permitted by the driver. */
+};
+
+/* ARM MPC SIE 200 device configuration structure */
+struct mpc_sie200_dev_cfg_t {
+ const uint32_t base; /*!< MPC base address */
+};
+
+/* ARM MPC SIE 200 device data structure */
+struct mpc_sie200_dev_data_t {
+ const struct mpc_sie200_memory_range_t** range_list; /*!< Array of pointers
+ to memory ranges
+ controlled by
+ the MPC */
+ uint8_t nbr_of_ranges; /*!< Number of memory ranges in the list */
+ uint8_t state; /*!< Indicates if the MPC driver
+ is initialized and enabled */
+ uint16_t reserved; /*!< 32 bits alignment */
+};
+
+/* ARM MPC SIE 200 device structure */
+struct mpc_sie200_dev_t {
+ const struct mpc_sie200_dev_cfg_t* const cfg; /*!< MPC configuration */
+ struct mpc_sie200_dev_data_t* const data; /*!< MPC data */
+};
+
+/**
+ * \brief Initializes a MPC device.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[in] range_list List of memory ranges controller by the MPC
+ * (\ref mpc_sie200_memory_range_t). This list can not
+ * freed after the initializations.
+ * \param[in] nbr_of_ranges Number of memory ranges
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_init(struct mpc_sie200_dev_t* dev,
+ const struct mpc_sie200_memory_range_t** range_list,
+ uint8_t nbr_of_ranges);
+
+/**
+ * \brief Gets MPC block size. All regions must be aligned on this block
+ * size (base address and limit+1 address).
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[out] blk_size MPC block size
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_get_block_size(struct mpc_sie200_dev_t* dev,
+ uint32_t* blk_size);
+
+/**
+ * \brief Configures a memory region (base and limit included).
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[in] base Base address of the region to poll. This bound is
+ * included. It does not need to be aligned in any way.
+ *
+ * \param[in] limit Limit address of the region to poll. This bound is
+ * included. (limit+1) does not need to be aligned
+ * in any way.
+ * \param[in] attr Security attribute of the region. If the region has mixed
+ * secure/non-secure, a special value is returned
+ * (\ref mpc_sie200_sec_attr_t).
+ *
+ * In case base and limit+1 addresses are not aligned on
+ * the block size, the enclosing region with base and
+ * limit+1 aligned on block size will be queried.
+ * In case of early termination of the function (error), the
+ * security attribute will be set to MPC_SIE200_ATTR_MIXED.
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_config_region(struct mpc_sie200_dev_t* dev,
+ const uint32_t base,
+ const uint32_t limit,
+ enum mpc_sie200_sec_attr_t attr);
+
+/**
+ * \brief Gets a memory region configuration(base and limit included).
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[in] base Base address of the region to get the configuration.
+ * \param[in] limit Limit address of the region to get the configuration.
+ * \param[out] attr Security attribute of the region
+ * \ref mpc_sie200_sec_attr_t
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_get_region_config(
+ struct mpc_sie200_dev_t* dev,
+ uint32_t base,
+ uint32_t limit,
+ enum mpc_sie200_sec_attr_t* attr);
+
+/**
+ * \brief Gets the MPC control value.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[out] ctrl_val Current MPC control value.
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_get_ctrl(struct mpc_sie200_dev_t* dev,
+ uint32_t* ctrl_val);
+
+/**
+ * \brief Sets the MPC control value.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[in] mpc_ctrl New MPC control value
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_set_ctrl(struct mpc_sie200_dev_t* dev,
+ uint32_t mpc_ctrl);
+
+/**
+ * \brief Gets the configured secure response.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[out] sec_rep Configured secure response (\ref mpc_sie200_sec_resp_t).
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_get_sec_resp(struct mpc_sie200_dev_t* dev,
+ enum mpc_sie200_sec_resp_t* sec_rep);
+
+/**
+ * \brief Enables MPC interrupt.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_irq_enable(struct mpc_sie200_dev_t* dev);
+
+/**
+ * \brief Disables MPC interrupt
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void mpc_sie200_irq_disable(struct mpc_sie200_dev_t* dev);
+
+/**
+ * \brief Clears MPC interrupt.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void mpc_sie200_clear_irq(struct mpc_sie200_dev_t* dev);
+
+/**
+ * \brief Returns the MPC interrupt state.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \return Returns 1 if the interrupt is active, 0 otherwise.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t mpc_sie200_irq_state(struct mpc_sie200_dev_t* dev);
+
+/**
+ * \brief Locks down the MPC configuration.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_lock_down(struct mpc_sie200_dev_t* dev);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __MPC_SIE_200_DRV_H__ */
diff --git a/platform/ext/target/sse_200_mps2/sse_200/native_drivers/ppc_sse200_drv.c b/platform/ext/target/sse_200_mps2/sse_200/native_drivers/ppc_sse200_drv.c
new file mode 100644
index 0000000..8db96e2
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/native_drivers/ppc_sse200_drv.c
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ppc_sse200_drv.h"
+
+/* SPCTRL PPCs control memory mapped registers access structure */
+struct arm_spctrl_ppc_sse200_t {
+ volatile uint32_t reserved[8];
+ volatile uint32_t secppcintstat; /* Secure PPC Interrupt Status */
+ volatile uint32_t secppcintclr; /* Secure PPC Interrupt Clear */
+ volatile uint32_t secppcinten; /* Secure PPC Interrupt Enable */
+ volatile uint32_t reserved1[9];
+ volatile uint32_t ahbnsppc0; /* Non-Secure Access AHB slave Peripheral
+ Protection Control #0 */
+ volatile uint32_t reserved2[3]; /* Reserved for Future Non-secure Access
+ AHB Slave Peripheral Protection
+ Control */
+ volatile uint32_t ahbnsppcexp0; /* Expansion 0 Non_Secure Access AHB
+ slave Peripheral Protection Control */
+ volatile uint32_t ahbnsppcexp1; /* Expansion 1 Non_Secure Access AHB
+ slave Peripheral Protection Control */
+ volatile uint32_t ahbnsppcexp2; /* Expansion 2 Non_Secure Access AHB
+ slave Peripheral Protection Control */
+ volatile uint32_t ahbnsppcexp3; /* Expansion 3 Non_Secure Access AHB
+ slave Peripheral Protection Control */
+ volatile uint32_t apbnsppc0; /* Non-Secure Access APB slave Peripheral
+ Protection Control 0 */
+ volatile uint32_t apbnsppc1; /* Non-Secure Access APB slave Peripheral
+ Protection Control 1 */
+ volatile uint32_t reserved3[2]; /* Non-Secure Access APB slave Peripheral
+ Protection Control [3:1] */
+ volatile uint32_t apbnsppcexp0; /* Expansion 0 Non_Secure Access APB
+ slave Peripheral Protection Control */
+ volatile uint32_t apbnsppcexp1; /* Expansion 1 Non_Secure Access APB
+ slave Peripheral Protection Control */
+ volatile uint32_t apbnsppcexp2; /* Expansion 2 Non_Secure Access APB
+ slave Peripheral Protection Control */
+ volatile uint32_t apbnsppcexp3; /* Expansion 3 Non_Secure Access APB
+ slave Peripheral Protection Control */
+ volatile uint32_t ahbspppc0; /* Secure Unprivileged Access AHB slave
+ Peripheral Protection Control 0 */
+ volatile uint32_t reserved4[3]; /* Reserved for Future Secure Unprivileged
+ Access AHB slave Peripheral Protection
+ Control */
+ volatile uint32_t ahbspppcexp0; /* Expansion 0 Secure Unprivileged Access
+ AHB slave Peripheral Protection
+ Control */
+ volatile uint32_t ahbspppcexp1; /* Expansion 1 Secure Unprivileged Access
+ AHB slave Peripheral Protection
+ Control */
+ volatile uint32_t ahbspppcexp2; /* Expansion 2 Secure Unprivileged Access
+ AHB slave Peripheral Protection
+ Control */
+ volatile uint32_t ahbspppcexp3; /* Expansion 3 Secure Unprivileged Access
+ AHB slave Peripheral Protection
+ Control */
+ volatile uint32_t apbspppc0; /* Secure Unprivileged Access APB slave
+ Peripheral 0 */
+ volatile uint32_t apbspppc1; /* Secure Unprivileged Access APB slave
+ Peripheral 1 */
+ volatile uint32_t reserved5[2]; /* Reserved for Future Secure Unprivileged
+ Access APB slave Peripheral Protection
+ Control */
+ volatile uint32_t apbspppcexp0; /* Expansion 0 Secure Unprivileged Access
+ APB slave Peripheral Protection
+ Control */
+ volatile uint32_t apbspppcexp1; /* Expansion 1 Secure Unprivileged Access
+ APB slave Peripheral Protection
+ Control */
+ volatile uint32_t apbspppcexp2; /* Expansion 2 Secure Unprivileged Access
+ APB slave Peripheral Protection
+ Control */
+ volatile uint32_t apbspppcexp3; /* Expansion 3 Secure Unprivileged Access
+ APB slave Peripheral Protection
+ Control */
+};
+
+/* NSPCTRL PPCs memory mapped register access structure */
+struct arm_nspctrl_ppc_sse200_t {
+ volatile uint32_t reserved[36];
+ volatile uint32_t ahbnspppc0;
+ volatile uint32_t reserved1[3];
+ volatile uint32_t ahbnspppcexp0;
+ volatile uint32_t ahbnspppcexp1;
+ volatile uint32_t ahbnspppcexp2;
+ volatile uint32_t ahbnspppcexp3;
+ volatile uint32_t apbnspppc0;
+ volatile uint32_t apbnspppc1;
+ volatile uint32_t reserved2[2];
+ volatile uint32_t apbnspppcexp0;
+ volatile uint32_t apbnspppcexp1;
+ volatile uint32_t apbnspppcexp2;
+ volatile uint32_t apbnspppcexp3;
+};
+
+/* PPC interrupt position mask */
+#define APB_PPC0_INT_POS_MASK (1UL << 0)
+#define APB_PPC1_INT_POS_MASK (1UL << 1)
+/* Reseved bits 2:3 */
+#define APB_PPCEXP0_INT_POS_MASK (1UL << 4)
+#define APB_PPCEXP1_INT_POS_MASK (1UL << 5)
+#define APB_PPCEXP2_INT_POS_MASK (1UL << 6)
+#define APB_PPCEXP3_INT_POS_MASK (1UL << 7)
+/* Reseved bits 8:15 */
+#define AHB_PPC0_INT_POS_MASK (1UL << 16)
+/* Reseved bits 17:19 */
+#define AHB_PPCEXP0_INT_POS_MASK (1UL << 20)
+#define AHB_PPCEXP1_INT_POS_MASK (1UL << 21)
+#define AHB_PPCEXP2_INT_POS_MASK (1UL << 22)
+#define AHB_PPCEXP3_INT_POS_MASK (1UL << 23)
+/* Reseved bits 24:31 */
+
+/* ARM PPC state definitions */
+#define PPC_SSE200_INITIALIZED (1 << 0)
+
+/* Default peripheral states */
+#define SECURE_AS_DEFAULT_PERIPHERAL_STATE 1
+#define PRIVILEGE_ONLY_AS_DEFAULT_PERIPHERAL_STATE 1
+
+void ppc_sse200_init(struct ppc_sse200_dev_t* dev,
+ enum ppc_sse200_name_t ppc_name)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+ struct arm_nspctrl_ppc_sse200_t* p_nspctrl =
+ (struct arm_nspctrl_ppc_sse200_t*)dev->cfg->nspctrl_base;
+
+ switch(ppc_name) {
+ case AHB_PPC0:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppc0;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppc0;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppc0;
+ dev->data->int_bit_mask = AHB_PPC0_INT_POS_MASK;
+ break;
+ case AHB_PPC_EXP0:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp0;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp0;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp0;
+ dev->data->int_bit_mask = AHB_PPCEXP0_INT_POS_MASK;
+ break;
+ case AHB_PPC_EXP1:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp1;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp1;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp1;
+ dev->data->int_bit_mask = AHB_PPCEXP1_INT_POS_MASK;
+ break;
+ case AHB_PPC_EXP2:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp2;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp2;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp2;
+ dev->data->int_bit_mask = AHB_PPCEXP2_INT_POS_MASK;
+ break;
+ case AHB_PPC_EXP3:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp3;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp3;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp3;
+ dev->data->int_bit_mask = AHB_PPCEXP3_INT_POS_MASK;
+ break;
+ case APB_PPC0:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppc0;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppc0;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppc0;
+ dev->data->int_bit_mask = APB_PPC0_INT_POS_MASK;
+ break;
+ case APB_PPC1:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppc1;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppc1;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppc1;
+ dev->data->int_bit_mask = APB_PPC1_INT_POS_MASK;
+ break;
+ case APB_PPC_EXP0:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp0;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppcexp0;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp0;
+ dev->data->int_bit_mask = APB_PPCEXP0_INT_POS_MASK;
+ break;
+ case APB_PPC_EXP1:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp1;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppcexp1;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp1;
+ dev->data->int_bit_mask = APB_PPCEXP1_INT_POS_MASK;
+ break;
+ case APB_PPC_EXP2:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp2;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppcexp2;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp2;
+ dev->data->int_bit_mask = APB_PPCEXP2_INT_POS_MASK;
+ break;
+ case APB_PPC_EXP3:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp3;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppcexp3;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp3;
+ dev->data->int_bit_mask = APB_PPCEXP3_INT_POS_MASK;
+ break;
+ /* default: The default is not defined intentionally to force the
+ * compiler to check that all enumeration values are
+ * covered in the switch.*/
+ }
+
+ dev->data->state = PPC_SSE200_INITIALIZED;
+}
+
+enum ppc_sse200_error_t ppc_sse200_config_peripheral(
+ struct ppc_sse200_dev_t* dev,
+ uint8_t periph,
+ enum ppc_sse200_sec_attr_t sec_attr,
+ enum ppc_sse200_priv_attr_t priv_attr)
+{
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return PPC_SSE200_NOT_INIT;
+ }
+
+ if(sec_attr == PPC_SSE200_SECURE_ONLY) {
+ /* Sets secure attribute */
+ *(dev->data->p_ns_ppc) &= ~(1U << periph);
+
+ /* Uses secure unprivileged access address (SPCTRL) to set privilege
+ * attribute */
+ if(priv_attr == PPC_SSE200_PRIV_ONLY) {
+ *(dev->data->p_sp_ppc) &= ~(1U << periph);
+ } else {
+ *(dev->data->p_sp_ppc) |= (1U << periph);
+ }
+ } else {
+ /* Sets secure attribute */
+ *(dev->data->p_ns_ppc) |= (1U << periph);
+
+ /* Uses non-secure unprivileged access address (NSPCTRL) to set
+ * privilege attribute */
+ if(priv_attr == PPC_SSE200_PRIV_ONLY) {
+ *(dev->data->p_nsp_ppc) &= ~(1U << periph);
+ } else {
+ *(dev->data->p_nsp_ppc) |= (1U << periph);
+ }
+ }
+
+ return PPC_SSE200_ERR_NONE;
+}
+
+uint32_t ppc_sse200_is_periph_secure(struct ppc_sse200_dev_t* dev,
+ uint8_t periph)
+{
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return SECURE_AS_DEFAULT_PERIPHERAL_STATE;
+ }
+
+ return ((*(dev->data->p_ns_ppc) & (1U << periph)) == 0);
+}
+
+uint32_t ppc_sse200_is_periph_priv_only(struct ppc_sse200_dev_t* dev,
+ uint8_t periph)
+{
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return PRIVILEGE_ONLY_AS_DEFAULT_PERIPHERAL_STATE;
+ }
+
+ if ((*(dev->data->p_ns_ppc) & (1U << periph)) == 0) {
+ /* Returns secure unprivileged access address (SPCTRL) */
+ return ((*(dev->data->p_sp_ppc) & (1U << periph)) == 0);
+ } else {
+ /* Returns non-secure unprivileged access address (NSPCTRL) */
+ return ((*(dev->data->p_nsp_ppc) & (1U << periph)) == 0);
+ }
+}
+
+enum ppc_sse200_error_t ppc_sse200_irq_enable(struct ppc_sse200_dev_t* dev)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return PPC_SSE200_NOT_INIT;
+ }
+
+ p_spctrl->secppcinten |= dev->data->int_bit_mask;
+
+ return PPC_SSE200_ERR_NONE;
+}
+
+void ppc_sse200_irq_disable(struct ppc_sse200_dev_t* dev)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+
+ if(dev->data->state == PPC_SSE200_INITIALIZED) {
+ p_spctrl->secppcinten &= ~(dev->data->int_bit_mask);
+ }
+}
+
+void ppc_sse200_clear_irq(struct ppc_sse200_dev_t* dev)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+
+ if(dev->data->state == PPC_SSE200_INITIALIZED) {
+ p_spctrl->secppcintclr = dev->data->int_bit_mask;
+ }
+}
+
+uint32_t ppc_sse200_irq_state(struct ppc_sse200_dev_t* dev)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return 0;
+ }
+
+ return ((p_spctrl->secppcintstat & dev->data->int_bit_mask) != 0);
+}
diff --git a/platform/ext/target/sse_200_mps2/sse_200/native_drivers/ppc_sse200_drv.h b/platform/ext/target/sse_200_mps2/sse_200/native_drivers/ppc_sse200_drv.h
new file mode 100644
index 0000000..c09650b
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/native_drivers/ppc_sse200_drv.h
@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file ppc_sse200_drv.h
+ * \brief Generic driver for ARM SEE 200 Peripheral Protection
+ * Controllers (PPC).
+ */
+
+#ifndef __PPC_SSE_200_DRV_H__
+#define __PPC_SSE_200_DRV_H__
+
+#include <stdint.h>
+
+/* Secure Privilege Control Block aka SPCTRL */
+/* Non-Secure Privilege Control Block aka NSPCTRL */
+
+/* ARM TrustZone PPC device configuration structure */
+struct ppc_sse200_dev_cfg_t {
+ uint32_t const spctrl_base; /*!< SPCTRL base address */
+ uint32_t const nspctrl_base; /*!< NSPCTRL base address */
+};
+
+/* ARM TrustZone PPC device data structure */
+struct ppc_sse200_dev_data_t {
+ volatile uint32_t* p_ns_ppc; /*!< Pointer to non-secure register */
+ volatile uint32_t* p_sp_ppc; /*!< Pointer to secure unprivileged
+ register */
+ volatile uint32_t* p_nsp_ppc; /*!< Pointer to non-secure unprivileged
+ register */
+ uint32_t int_bit_mask; /*!< Interrupt bit mask */
+ uint8_t state; /*!< Indicates if the PPC driver
+ is initialized */
+ uint8_t reserved[3]; /*!< 32 bits alignment */
+};
+
+/* ARM PPC device structure */
+struct ppc_sse200_dev_t {
+ const struct ppc_sse200_dev_cfg_t* const cfg; /*!< PPC configuration */
+ struct ppc_sse200_dev_data_t* const data; /*!< PPC data */
+};
+
+/* Security attribute used to configure the peripheral */
+enum ppc_sse200_sec_attr_t {
+ PPC_SSE200_SECURE_ONLY, /*! Secure access */
+ PPC_SSE200_NONSECURE_ONLY, /*! Non-secure access */
+};
+
+/* Privilege attribute used to configure the peripheral */
+enum ppc_sse200_priv_attr_t {
+ PPC_SSE200_PRIV_AND_NONPRIV, /*! Privilege and non-Privilege access */
+ PPC_SSE200_PRIV_ONLY, /*! Privilege only access */
+};
+
+/* ARM PPC error codes */
+enum ppc_sse200_error_t {
+ PPC_SSE200_ERR_NONE = 0, /*!< No error */
+ PPC_SSE200_NOT_INIT, /*!< PPC not initialized */
+};
+
+/* ARM PPC names */
+enum ppc_sse200_name_t {
+ AHB_PPC0 = 0, /*!< AHB PPC0 */
+ AHB_PPC_EXP0, /*!< Expansion 0 AHB PPC */
+ AHB_PPC_EXP1, /*!< Expansion 1 AHB PPC */
+ AHB_PPC_EXP2, /*!< Expansion 2 AHB PPC */
+ AHB_PPC_EXP3, /*!< Expansion 3 AHB PPC */
+ APB_PPC0, /*!< APB PPC0 */
+ APB_PPC1, /*!< APB PPC1 */
+ APB_PPC_EXP0, /*!< Expansion 0 APB PPC */
+ APB_PPC_EXP1, /*!< Expansion 1 APB PPC */
+ APB_PPC_EXP2, /*!< Expansion 2 APB PPC */
+ APB_PPC_EXP3 /*!< Expansion 3 APB PPC */
+};
+
+/**
+ * \brief Initialize the PPC device.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ * \param[in] ppc_name PPC name \ref ppc_sse200_name_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void ppc_sse200_init(struct ppc_sse200_dev_t* dev,
+ enum ppc_sse200_name_t ppc_name);
+
+/**
+ * \brief Configures the PPC device.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ * \param[in] periph Peripheral position in the PPC.
+ * \param[in] sec_attr Secure attribute value.
+ * \param[in] priv_attr Privilege attribute value.
+ *
+ * \return Returns error code as specified in \ref ppc_sse200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum ppc_sse200_error_t ppc_sse200_config_peripheral(
+ struct ppc_sse200_dev_t* dev,
+ uint8_t periph,
+ enum ppc_sse200_sec_attr_t sec_attr,
+ enum ppc_sse200_priv_attr_t priv_attr);
+/**
+ * \brief Checks if the peripheral is configured as secure or non-secure.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ * \param[in] periph Peripheral position in the PPC.
+ *
+ * \return Returns 1 for secure and 0 for non-secure.
+ * If the driver is not initalized the return value is 1 (secure) as
+ * it is the default system configuration.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t ppc_sse200_is_periph_secure(struct ppc_sse200_dev_t* dev,
+ uint8_t periph);
+
+/**
+ * \brief Checks if the peripheral is configured as Privilege only or
+ * Privilege and non-Privilege access mode.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ * \param[in] periph Peripheral position in the PPC.
+ *
+ * \return Returns 1 for Privilege only configuration and 0 for Privilege and
+ * non-Privilege access.
+ * If the driver is not initalized the return of this function is
+ * 1 (Privilege only) as it is the default system configuration.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t ppc_sse200_is_periph_priv_only(struct ppc_sse200_dev_t* dev,
+ uint8_t periph);
+/**
+ * \brief Enables PPC interrupt.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ *
+ * \return Returns error code as specified in \ref ppc_sse200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum ppc_sse200_error_t ppc_sse200_irq_enable(struct ppc_sse200_dev_t* dev);
+
+/**
+ * \brief Disables PPC interrupt.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void ppc_sse200_irq_disable(struct ppc_sse200_dev_t* dev);
+
+/**
+ * \brief Clears PPC interrupt.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void ppc_sse200_clear_irq(struct ppc_sse200_dev_t* dev);
+
+/**
+ * \brief Returns the PPC interrupt state.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ *
+ * \return Returns 1 if the interrupt is active and otherwise 0.
+ * If the driver is not initalized the return of this function is
+ * 0 (not active) as it is the default system configuration.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t ppc_sse200_irq_state(struct ppc_sse200_dev_t* dev);
+
+#endif /* __PPC_SSE_200_DRV_H__ */
diff --git a/platform/ext/target/sse_200_mps2/sse_200/native_drivers/timer_cmsdk/timer_cmsdk.c b/platform/ext/target/sse_200_mps2/sse_200/native_drivers/timer_cmsdk/timer_cmsdk.c
new file mode 100644
index 0000000..1037f2d
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/native_drivers/timer_cmsdk/timer_cmsdk.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file timer_cmsdk.c
+ * \brief Generic driver for CMSDK APB Timers.
+ * The timer is a 32-bit down-counter with the following features:
+ * - optional programmable external clock source
+ * - programmable interrupt source, triggered if counter reaches 0
+ * - automatic reload if counter reaches 0
+ */
+
+#include "timer_cmsdk.h"
+
+/** Setter bit manipulation macro */
+#define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX)))
+/** Clearing bit manipulation macro */
+#define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX)))
+/** Getter bit manipulation macro */
+#define GET_BIT(WORD, BIT_INDEX) (bool)(((WORD) & (1U << (BIT_INDEX))))
+
+/**
+ * \brief Timer register map structure
+ *
+ */
+struct cmsdk_timer_reg_map_t {
+ volatile uint32_t ctrl; /* Offset: 0x000 (R/W) control register */
+ volatile uint32_t value; /* Offset: 0x004 (R/W) current value register */
+ volatile uint32_t reload; /* Offset: 0x008 (R/W) reload value register */
+ union {
+ volatile uint32_t intstatus; /* Offset: 0x00C (R/ ) interrupt
+ * status register */
+ volatile uint32_t intclear; /* Offset: 0x00C ( /W) interrupt
+ * clear register */
+ }intreg;
+};
+
+/**
+ * \brief CTRL register bit definitions
+ *
+ */
+enum ctrl_reg_bits_t{
+ CTRL_REG_ENUM_ENABLE_INDEX = 0,
+ CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX = 1,
+ CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX = 2,
+ CTRL_REG_ENUM_IRQ_ENABLE_INDEX = 3
+};
+
+/**
+ * \brief INTSTATUS/INTCLEAR register bit definitions
+ *
+ */
+enum interrupt_reg_bits_t{
+ INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX = 0
+};
+
+void cmsdk_timer_init(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+
+ if (dev->data->is_initialized == 0) {
+ register_map->ctrl = 0;
+ register_map->reload = CMSDK_TIMER_DEFAULT_RELOAD;
+ dev->data->is_initialized = 1;
+ }
+}
+
+bool cmsdk_timer_is_initialized(const struct cmsdk_timer_dev_t* dev)
+{
+ return dev->data->is_initialized;
+}
+
+void cmsdk_timer_enable_external_input(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX);
+}
+
+void cmsdk_timer_disable_external_input(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX);
+}
+
+bool cmsdk_timer_is_external_input_enabled(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->ctrl,
+ CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX);
+}
+
+void cmsdk_timer_set_clock_to_internal(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX);
+}
+
+void cmsdk_timer_set_clock_to_external(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX);
+}
+
+bool cmsdk_timer_is_clock_external(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->ctrl,
+ CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX);
+}
+
+void cmsdk_timer_enable(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX);
+}
+
+void cmsdk_timer_disable(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX);
+}
+
+bool cmsdk_timer_is_enabled(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX);
+}
+
+void cmsdk_timer_enable_interrupt(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX);
+}
+
+void cmsdk_timer_disable_interrupt(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX);
+}
+
+bool cmsdk_timer_is_interrupt_enabled(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX);
+}
+
+bool cmsdk_timer_is_interrupt_active(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->intreg.intstatus,
+ INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX);
+}
+
+void cmsdk_timer_clear_interrupt(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->intreg.intclear,
+ INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX);
+}
+
+uint32_t cmsdk_timer_get_current_value(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return register_map->value;
+}
+
+void cmsdk_timer_set_reload_value(const struct cmsdk_timer_dev_t* dev,
+ uint32_t reload)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ register_map->reload = reload;
+}
+
+void cmsdk_timer_reset(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ register_map->value = register_map->reload;
+}
+
+uint32_t cmsdk_timer_get_reload_value(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return register_map->reload;
+}
+
+uint32_t cmsdk_timer_get_elapsed_value(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return register_map->reload - register_map->value;
+}
diff --git a/platform/ext/target/sse_200_mps2/sse_200/native_drivers/timer_cmsdk/timer_cmsdk.h b/platform/ext/target/sse_200_mps2/sse_200/native_drivers/timer_cmsdk/timer_cmsdk.h
new file mode 100644
index 0000000..52d9d5c
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/native_drivers/timer_cmsdk/timer_cmsdk.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file timer_cmsdk.h
+ * \brief Generic driver for CMSDK APB Timers.
+ * The timer is a 32-bit down-counter with the following features:
+ * - optional programmable external clock source
+ * - programmable interrupt source, triggered if counter reaches 0
+ * - automatic reload if counter reaches 0
+ */
+
+#ifndef __CMSDK_TIMER_DRV_H__
+#define __CMSDK_TIMER_DRV_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Maximum reload value */
+#define CMSDK_TIMER_MAX_RELOAD INT32_MAX /* max of 32-bit */
+#define CMSDK_TIMER_DEFAULT_RELOAD CMSDK_TIMER_MAX_RELOAD
+
+/** CMSDK timer device configuration structure */
+struct cmsdk_timer_dev_cfg_t {
+ const uintptr_t base; /*!< Timer base address */
+};
+
+/** CMSDK timer device data structure */
+struct cmsdk_timer_dev_data_t {
+ bool is_initialized; /*!< Indicates if the timer is initialized */
+};
+
+/* CMSDK timer device structure */
+struct cmsdk_timer_dev_t {
+ const struct cmsdk_timer_dev_cfg_t* const cfg; /*!< Timer configuration */
+ struct cmsdk_timer_dev_data_t* const data; /*!< Timer data */
+};
+
+/**
+ * \brief Initializes timer to a known default state, which is:
+ * - timer disabled
+ * - timer interrupt disabled
+ * - clock source set to internal
+ * - external input disabled
+ * - reload value maxed out
+ * Init should be called prior to any other process and
+ * it's the caller's responsibility to follow proper call order.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_init(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Checks if a timer is initialized.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return true if initialized, false otherwise
+ */
+bool cmsdk_timer_is_initialized(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Enables external input, which could be used as clock source
+ * by calling \ref cmsdk_timer_set_clock_to_external.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_enable_external_input(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Disables external input.
+ * Make sure if the timer is explicitly wanted to be stopped or set
+ * the clock source to internal by \ref cmsdk_timer_set_clock_to_internal.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_disable_external_input(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Checks if external input is enabled.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return true if enabled, false otherwise
+ */
+bool cmsdk_timer_is_external_input_enabled(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Sets the clock source to internal.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_set_clock_to_internal(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Sets the clock source to external.
+ * Make sure external input is enabled correspondingly
+ * by \ref cmsdk_timer_enable_external_input.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_set_clock_to_external(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Checks if clock source is external input.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return true if external, false if internal
+ */
+bool cmsdk_timer_is_clock_external(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Enables timer operation.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_enable(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Disables the given hardware timer.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_disable(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Checks if a timer is enabled.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return true if enabled, false otherwise
+ */
+bool cmsdk_timer_is_enabled(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Enables timer interrupt.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_enable_interrupt(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Disables timer interrupt.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_disable_interrupt(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Checks if a timer interrupt is enabled.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return true if enabled, false otherwise
+ */
+bool cmsdk_timer_is_interrupt_enabled(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Gets timer interrupt status
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * * \return true if active, false otherwise
+ */
+bool cmsdk_timer_is_interrupt_active(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Clears timer interrupt
+ * The interrupt request is held until it is cleared.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_clear_interrupt(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Reads timer current value.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return Timer value
+ */
+uint32_t cmsdk_timer_get_current_value(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Sets the reload value of the selected timer.
+ *
+ * New reload value takes effect when:
+ * - timer is restarted
+ * - on timer underflow
+ * - when cmsdk_timer_reset is called
+ *
+ * \note In r1p0 technical reference manual it's incorrectly stated
+ * writing the reload value automatically sets the current value also.
+ * r1p1 technical reference manual includes the fix.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ * \param[in] reload Timer reload value to set.
+ * This is the start value of the 32-bit down counter,
+ * which automatically reloaded if 0 is reached.
+ */
+void cmsdk_timer_set_reload_value(const struct cmsdk_timer_dev_t* dev,
+ uint32_t reload);
+
+/**
+ * \brief Resets the timer counter to the reload value instantly
+ * (i.e. without waiting for underflow).
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_reset(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Gets the reload value of the selected timer.
+ * This is the start value of the 32-bit down counter,
+ * which is automatically reloaded if 0 is reached by the counter.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return Reload value of the selected timer.
+ */
+uint32_t cmsdk_timer_get_reload_value(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Reads the number of ticks elapsed in the current cycle.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return Get elapsed number of ticks since last reload was set.
+ * Elapsed = (Reload value - Current value)
+ */
+uint32_t cmsdk_timer_get_elapsed_value(const struct cmsdk_timer_dev_t* dev);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __CMSDK_TIMER_DRV_H__ */
diff --git a/platform/ext/target/sse_200_mps2/sse_200/partition/region_defs.h b/platform/ext/target/sse_200_mps2/sse_200/partition/region_defs.h
new file mode 100644
index 0000000..afbf957
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/partition/region_defs.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __REGION_DEFS_H__
+#define __REGION_DEFS_H__
+
+#define TOTAL_ROM_SIZE (0x00400000) /* 4MB */
+#define TOTAL_RAM_SIZE (0x00200000) /* 2MB */
+
+/*
+ * MPC granularity is 128 KB on AN505 IoT Kit MPS2 FPGA image. Alignment
+ * of partitions is defined in accordance with this constraint.
+ */
+
+#define BL_PARTITION_SIZE (0x80000)
+
+/*Flash partitions on MPS2 AN505 with MCUboot:
+ *
+ * 0x0000_0000 MCUBoot
+ * 0x0008_0000 Secure image primary
+ * 0x0010_0000 Non-secure image primary
+ * 0x0018_0000 Secure image secondary
+ * 0x0020_0000 Non-secure image secondary
+ * 0x0028_0000 Scratch area
+ *
+ * Flash partitions on bare metal
+ * 0x0000_0000 Secure image
+ * 0x0010_0000 Non-secure image
+ */
+
+#ifdef MCUBOOT
+#define S_IMAGE_PRIMARY_PARTITION_OFFSET (0x80000)
+#else
+#define S_IMAGE_PRIMARY_PARTITION_OFFSET (0x0)
+#endif
+
+#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (0x100000)
+
+/*
+ * Boot partition structure if MCUboot is used:
+ * 0x0_0000 Bootloader header
+ * 0x0_0200 Image area
+ * 0x7_0000 Trailer
+ */
+/* IMAGE_AREA_SIZE is the space available for the software binary image.
+ * It is less than the PARTITION_SIZE because we reserve space
+ * for the image header and trailer introduced by the bootloader. */
+#ifdef MCUBOOT
+#define BL_HEADER_SIZE (0x200)
+#define BL_TRAILER_SIZE (0x10000)
+#else
+/* No header if no bootloader, but keep IMAGE_AREA_SIZE the same */
+#define BL_HEADER_SIZE (0x0)
+#define BL_TRAILER_SIZE (0x10200)
+#endif
+
+#define IMAGE_AREA_SIZE \
+ (BL_PARTITION_SIZE - BL_HEADER_SIZE - BL_TRAILER_SIZE)
+
+#define CMSE_VENEER_REGION_SIZE (0x00000080)
+
+/* Use SRAM1 memory to store Code data */
+#define S_ROM_ALIAS_BASE (0x10000000)
+#define NS_ROM_ALIAS_BASE (0x00000000)
+
+/* FIXME: Use SRAM2 memory to store RW data */
+#define S_RAM_ALIAS_BASE (0x38000000)
+#define NS_RAM_ALIAS_BASE (0x28000000)
+
+/* Alias definitions for secure and non-secure areas*/
+#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + x)
+#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + x)
+
+#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + x)
+#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + x)
+
+/* Secure regions */
+#define S_IMAGE_PRIMARY_AREA_OFFSET \
+ (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL_HEADER_SIZE)
+#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
+#define S_CODE_SIZE (IMAGE_AREA_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
+
+#define S_DATA_START (S_RAM_ALIAS(0x0))
+#define S_DATA_SIZE (TOTAL_RAM_SIZE/2)
+#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
+
+/* CMSE Veneers region */
+#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1)
+#define CMSE_VENEER_REGION_LIMIT (CMSE_VENEER_REGION_START + \
+ CMSE_VENEER_REGION_SIZE - 1)
+
+/* Non-secure regions */
+#define NS_IMAGE_PRIMARY_AREA_OFFSET \
+ (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL_HEADER_SIZE)
+#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET))
+#define NS_CODE_SIZE (IMAGE_AREA_SIZE)
+#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1)
+
+/* NS partition information is used for MPC configuration */
+#define NS_PARTITION_START \
+ (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET))
+
+#ifdef MCUBOOT
+/* Cover: non-secure primary + secure secondary + non-secure secondary area */
+#define NS_PARTITION_LIMIT \
+ (NS_PARTITION_START + 3 * BL_PARTITION_SIZE - 1)
+#else
+#define NS_PARTITION_LIMIT \
+ (NS_PARTITION_START + BL_PARTITION_SIZE - 1)
+#endif /* MCUBOOT */
+
+#define NS_DATA_START (NS_RAM_ALIAS(TOTAL_RAM_SIZE/2))
+#define NS_DATA_SIZE (TOTAL_RAM_SIZE/2)
+#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE -1)
+
+#endif /* __REGION_DEFS_H__ */
+
diff --git a/platform/ext/target/sse_200_mps2/sse_200/partition/region_limits.h b/platform/ext/target/sse_200_mps2/sse_200/partition/region_limits.h
new file mode 100644
index 0000000..ed6a0d3
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/partition/region_limits.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef REGION_LIMITS_H
+#define REGION_LIMITS_H
+
+#define TOTAL_ROM_SIZE (0x00400000) /* 4 MB */
+#define TOTAL_RAM_SIZE (0x00200000) /* 2 MB */
+
+/* Use SRAM1 memory to store Code data */
+#define S_ROM_ALIAS_BASE (0x10000000)
+#define NS_ROM_ALIAS_BASE (0x00000000)
+
+/* Use SRAM2 memory to store RW data as Internal RAM has issues in the FPGA */
+#define S_RAM_ALIAS_BASE (0x38000000)
+#define NS_RAM_ALIAS_BASE (0x28000000)
+
+#endif /*REGION_LIMITS_H*/
diff --git a/platform/ext/target/sse_200_mps2/sse_200/retarget/platform_retarget.h b/platform/ext/target/sse_200_mps2/sse_200/retarget/platform_retarget.h
new file mode 100644
index 0000000..c0141cb
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/retarget/platform_retarget.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_retarget.h
+ * \brief This file defines all the peripheral base addresses for MPS2/SSE-200 platform.
+ */
+
+#ifndef __ARM_LTD_SSE_200_RETARGET_H__
+#define __ARM_LTD_SSE_200_RETARGET_H__
+
+#include "platform_regs.h" /* Platform registers */
+#include "platform_irq.h" /* IRQ numbers */
+#include "platform_retarget_pins.h" /* Platform pin names */
+
+/* ======= Defines peripherals memory map addresses ======= */
+/* Non-secure memory map addresses */
+#define CMSDK_TIMER0_BASE_NS 0x40000000
+#define CMSDK_TIMER1_BASE_NS 0x40001000
+#define APB_DUALTIMER_BASE_NS 0x40002000
+#define MHU0_BASE_NS 0x40003000
+#define MHU1_BASE_NS 0x40004000
+#define S32K_TIMER_BASE_NS 0x4002F000
+#define S32K_WATCHDOG_BASE_NS 0x4002E000
+#define APB_WATCHDOG_BASE_NS 0x40081000
+#define GPIO0_BASE_NS 0x40100000
+#define GPIO1_BASE_NS 0x40101000
+#define GPIO2_BASE_NS 0x40102000
+#define GPIO3_BASE_NS 0x40103000
+#define UART0_BASE_NS 0x40200000
+#define UART1_BASE_NS 0x40201000
+#define UART2_BASE_NS 0x40202000
+#define UART3_BASE_NS 0x40203000
+#define UART4_BASE_NS 0x40204000
+#define I2C0_SBCON_BASE_NS 0x40207000 /* Touchscreen I2C Base Address */
+#define I2C1_SBCON_BASE_NS 0x40208000 /* Audio I2C Base Address */
+#define I2C2_SBCON_BASE_NS 0x4020C000 /* Shield 0 SBCon Base Address */
+#define I2C3_SBCON_BASE_NS 0x4020D000 /* Shield 1 SBCon Base Address */
+#define SSP0_BASE_NS 0x40206000 /* CLCD SSP PL022 Base Address */
+#define SSP1_BASE_NS 0x40205000 /* User SSP PL022 Base Address */
+#define SSP2_BASE_NS 0x40209000 /* ADC SPI PL022 Base Address */
+#define SSP3_BASE_NS 0x4020A000 /* Shield 0 SPI PL022 Base Address */
+#define SSP4_BASE_NS 0x4020B000 /* Shield 1 SPI PL022 Base Address */
+#define MPS2_IO_SCC_BASE_NS 0x40300000
+#define MPS2_IO_FPGAIO_BASE_NS 0x40302000
+
+/* Secure memory map addresses */
+#define CMSDK_TIMER0_BASE_S 0x50000000
+#define CMSDK_TIMER1_BASE_S 0x50001000
+#define APB_DUALTIMER_BASE_S 0x50002000
+#define MHU0_BASE_S 0x50003000
+#define MHU1_BASE_S 0x50004000
+#define S32K_TIMER_BASE_S 0x5002F000
+#define S32K_WATCHDOG_BASE_S 0x5002E000
+#define APB_WATCHDOG_BASE_S 0x50081000
+#define GPIO0_BASE_S 0x50100000
+#define GPIO1_BASE_S 0x50101000
+#define GPIO2_BASE_S 0x50102000
+#define GPIO3_BASE_S 0x50103000
+#define UART0_BASE_S 0x50200000
+#define UART1_BASE_S 0x50201000
+#define UART2_BASE_S 0x50202000
+#define UART3_BASE_S 0x50203000
+#define UART4_BASE_S 0x50204000
+#define I2C0_SBCON_BASE_S 0x50207000
+#define I2C1_SBCON_BASE_S 0x50208000
+#define I2C2_SBCON_BASE_S 0x5020C000
+#define I2C3_SBCON_BASE_S 0x5020D000
+#define SSP0_BASE_S 0x50206000
+#define SSP1_BASE_S 0x50205000
+#define SSP2_BASE_S 0x50209000
+#define SSP3_BASE_S 0x5020A000
+#define SSP4_BASE_S 0x5020B000
+#define MPS2_IO_SCC_BASE_S 0x50300000
+#define MPS2_IO_FPGAIO_BASE_S 0x50302000
+#define MPC_ISRAM0_BASE_S 0x50083000
+#define MPC_ISRAM1_BASE_S 0x50084000
+#define MPC_ISRAM2_BASE_S 0x50085000
+#define MPC_ISRAM3_BASE_S 0x50086000
+#define MPC_CODE_SRAM1_BASE_S 0x58007000
+#define MPC_CODE_SRAM2_BASE_S 0x58008000
+#define MPC_CODE_SRAM3_BASE_S 0x58009000
+
+/* SRAM MPC ranges and limits */
+/* Internal memory */
+#define MPC_ISRAM0_RANGE_BASE_NS 0x20000000
+#define MPC_ISRAM0_RANGE_LIMIT_NS 0x20007FFF
+#define MPC_ISRAM0_RANGE_BASE_S 0x30000000
+#define MPC_ISRAM0_RANGE_LIMIT_S 0x30007FFF
+
+#define MPC_ISRAM1_RANGE_BASE_NS 0x20008000
+#define MPC_ISRAM1_RANGE_LIMIT_NS 0x2000FFFF
+#define MPC_ISRAM1_RANGE_BASE_S 0x30008000
+#define MPC_ISRAM1_RANGE_LIMIT_S 0x3000FFFF
+
+#define MPC_ISRAM2_RANGE_BASE_NS 0x20010000
+#define MPC_ISRAM2_RANGE_LIMIT_NS 0x20017FFF
+#define MPC_ISRAM2_RANGE_BASE_S 0x30010000
+#define MPC_ISRAM2_RANGE_LIMIT_S 0x30017FFF
+
+#define MPC_ISRAM3_RANGE_BASE_NS 0x20018000
+#define MPC_ISRAM3_RANGE_LIMIT_NS 0x2001FFFF
+#define MPC_ISRAM3_RANGE_BASE_S 0x30018000
+#define MPC_ISRAM3_RANGE_LIMIT_S 0x3001FFFF
+
+/* External SSRAM memory */
+#define MPC_CODE_SRAM1_RANGE_BASE_NS 0x00000000
+#define MPC_CODE_SRAM1_RANGE_LIMIT_NS 0x003FFFFF
+#define MPC_CODE_SRAM1_RANGE_BASE_S 0x10000000
+#define MPC_CODE_SRAM1_RANGE_LIMIT_S 0x103FFFFF
+
+#define MPC_CODE_SRAM2_RANGE_BASE_NS 0x28000000
+#define MPC_CODE_SRAM2_RANGE_LIMIT_NS 0x281FFFFF
+#define MPC_CODE_SRAM2_RANGE_BASE_S 0x38000000
+#define MPC_CODE_SRAM2_RANGE_LIMIT_S 0x381FFFFF
+
+#define MPC_CODE_SRAM3_RANGE_BASE_NS 0x28200000
+#define MPC_CODE_SRAM3_RANGE_LIMIT_NS 0x283FFFFF
+#define MPC_CODE_SRAM3_RANGE_BASE_S 0x38200000
+#define MPC_CODE_SRAM3_RANGE_LIMIT_S 0x383FFFFF
+
+#endif /* __ARM_LTD_SSE_200_RETARGET_H__ */
diff --git a/platform/ext/target/sse_200_mps2/sse_200/retarget/platform_retarget_dev.c b/platform/ext/target/sse_200_mps2/sse_200/retarget/platform_retarget_dev.c
new file mode 100644
index 0000000..e7033c2
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/retarget/platform_retarget_dev.c
@@ -0,0 +1,427 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_retarget_dev.c
+ * \brief This file defines exports the structures based on the peripheral
+ * definitions from device_cfg.h.
+ * This retarget file is meant to be used as a helper for baremetal
+ * applications and/or as an example of how to configure the generic
+ * driver structures.
+ */
+
+#include "platform_retarget_dev.h"
+#include "platform_retarget.h"
+#include "system_cmsdk_mps2_sse_200.h"
+#include "mps2_time.h" /* Import mps2_sleepus function */
+
+/* ARM UART driver structures */
+#ifdef ARM_UART0_S
+static const struct arm_uart_dev_cfg_t ARM_UART0_DEV_CFG_S = {
+ .base = UART0_BASE_S,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART0_DEV_DATA_S = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART0_DEV_S = {&(ARM_UART0_DEV_CFG_S),
+ &(ARM_UART0_DEV_DATA_S)};
+#endif
+#ifdef ARM_UART0_NS
+static const struct arm_uart_dev_cfg_t ARM_UART0_DEV_CFG_NS = {
+ .base = UART0_BASE_NS,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART0_DEV_DATA_NS = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART0_DEV_NS = {&(ARM_UART0_DEV_CFG_NS),
+ &(ARM_UART0_DEV_DATA_NS)};
+#endif
+
+#ifdef ARM_UART1_S
+static const struct arm_uart_dev_cfg_t ARM_UART1_DEV_CFG_S = {
+ .base = UART1_BASE_S,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART1_DEV_DATA_S = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART1_DEV_S = {&(ARM_UART1_DEV_CFG_S),
+ &(ARM_UART1_DEV_DATA_S)};
+#endif
+#ifdef ARM_UART1_NS
+static const struct arm_uart_dev_cfg_t ARM_UART1_DEV_CFG_NS = {
+ .base = UART1_BASE_NS,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART1_DEV_DATA_NS = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART1_DEV_NS = {&(ARM_UART1_DEV_CFG_NS),
+ &(ARM_UART1_DEV_DATA_NS)};
+#endif
+
+#ifdef ARM_UART2_S
+static const struct arm_uart_dev_cfg_t ARM_UART2_DEV_CFG_S = {
+ .base = UART2_BASE_S,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART2_DEV_DATA_S = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART2_DEV_S = {&(ARM_UART2_DEV_CFG_S),
+ &(ARM_UART2_DEV_DATA_S)};
+#endif
+#ifdef ARM_UART2_NS
+static const struct arm_uart_dev_cfg_t ARM_UART2_DEV_CFG_NS = {
+ .base = UART2_BASE_NS,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART2_DEV_DATA_NS = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART2_DEV_NS = {&(ARM_UART2_DEV_CFG_NS),
+ &(ARM_UART2_DEV_DATA_NS)};
+#endif
+
+#ifdef ARM_UART3_S
+static const struct arm_uart_dev_cfg_t ARM_UART3_DEV_CFG_S = {
+ .base = UART3_BASE_S,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART3_DEV_DATA_S = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART3_DEV_S = {&(ARM_UART3_DEV_CFG_S),
+ &(ARM_UART3_DEV_DATA_S)};
+#endif
+#ifdef ARM_UART3_NS
+static const struct arm_uart_dev_cfg_t ARM_UART3_DEV_CFG_NS = {
+ .base = UART3_BASE_NS,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART3_DEV_DATA_NS = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART3_DEV_NS = {&(ARM_UART3_DEV_CFG_NS),
+ &(ARM_UART3_DEV_DATA_NS)};
+#endif
+
+#ifdef ARM_UART4_S
+static const struct arm_uart_dev_cfg_t ARM_UART4_DEV_CFG_S = {
+ .base = UART4_BASE_S,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART4_DEV_DATA_S = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART4_DEV_S = {&(ARM_UART4_DEV_CFG_S),
+ &(ARM_UART4_DEV_DATA_S)};
+#endif
+#ifdef ARM_UART4_NS
+static const struct arm_uart_dev_cfg_t ARM_UART4_DEV_CFG_NS = {
+ .base = UART4_BASE_NS,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART4_DEV_DATA_NS = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART4_DEV_NS = {&(ARM_UART4_DEV_CFG_NS),
+ &(ARM_UART4_DEV_DATA_NS)};
+#endif
+
+/* ARM PPC SIE 200 driver structures */
+#ifdef AHB_PPC0_S
+static struct ppc_sse200_dev_cfg_t AHB_PPC0_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t AHB_PPC0_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t AHB_PPC0_DEV_S = {
+ &AHB_PPC0_DEV_CFG_S, &AHB_PPC0_DEV_DATA_S };
+#endif
+
+#ifdef AHB_PPCEXP0_S
+static struct ppc_sse200_dev_cfg_t AHB_PPCEXP0_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t AHB_PPCEXP0_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t AHB_PPCEXP0_DEV_S = {
+ &AHB_PPCEXP0_DEV_CFG_S, &AHB_PPCEXP0_DEV_DATA_S };
+#endif
+
+#ifdef AHB_PPCEXP1_S
+static struct ppc_sse200_dev_cfg_t AHB_PPCEXP1_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t AHB_PPCEXP1_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sie200_dev_t AHB_PPCEXP1_DEV_S = {
+ &AHB_PPCEXP1_DEV_CFG_S, &AHB_PPCEXP1_DEV_DATA_S };
+#endif
+
+#ifdef AHB_PPCEXP2_S
+static struct ppc_sse200_dev_cfg_t AHB_PPCEXP2_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t AHB_PPCEXP2_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t AHB_PPCEXP2_DEV_S = {
+ &AHB_PPCEXP2_DEV_CFG_S, &AHB_PPCEXP2_DEV_DATA_S };
+#endif
+
+#ifdef AHB_PPCEXP3_S
+static struct ppc_sse200_dev_cfg_t AHB_PPCEXP3_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t AHB_PPCEXP3_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t AHB_PPCEXP3_DEV_S = {
+ &AHB_PPCEXP3_DEV_CFG_S, &AHB_PPCEXP3_DEV_DATA_S };
+#endif
+
+#ifdef APB_PPC0_S
+static struct ppc_sse200_dev_cfg_t APB_PPC0_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t APB_PPC0_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t APB_PPC0_DEV_S = {
+ &APB_PPC0_DEV_CFG_S, &APB_PPC0_DEV_DATA_S };
+#endif
+
+#ifdef APB_PPC1_S
+static struct ppc_sse200_dev_cfg_t APB_PPC1_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t APB_PPC1_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t APB_PPC1_DEV_S = {
+ &APB_PPC1_DEV_CFG_S, &APB_PPC1_DEV_DATA_S};
+#endif
+
+#ifdef APB_PPCEXP0_S
+static struct ppc_sse200_dev_cfg_t APB_PPCEXP0_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t APB_PPCEXP0_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t APB_PPCEXP0_DEV_S = {
+ &APB_PPCEXP0_DEV_CFG_S, &APB_PPCEXP0_DEV_DATA_S };
+#endif
+
+#ifdef APB_PPCEXP1_S
+static struct ppc_sse200_dev_cfg_t APB_PPCEXP1_DEV_CFG = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t APB_PPCEXP1_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t APB_PPCEXP1_DEV_S = {
+ &APB_PPCEXP1_DEV_CFG, &APB_PPCEXP1_DEV_DATA_S };
+#endif
+
+#ifdef APB_PPCEXP2_S
+static struct ppc_sse200_dev_cfg_t APB_PPCEXP2_DEV_CFG = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t APB_PPCEXP2_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t APB_PPCEXP2_DEV_S = {
+ &APB_PPCEXP2_DEV_CFG, &APB_PPCEXP2_DEV_DATA_S };
+#endif
+
+#ifdef APB_PPCEXP3_S
+static struct ppc_sse200_dev_cfg_t APB_PPCEXP3_DEV_CFG = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t APB_PPCEXP3_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t APB_PPCEXP3_DEV_S = {
+ &APB_PPCEXP3_DEV_CFG, &APB_PPCEXP3_DEV_DATA_S };
+#endif
+
+/* CMSDK Timer driver structures */
+#ifdef CMSDK_TIMER0_S
+static const struct cmsdk_timer_dev_cfg_t CMSDK_TIMER0_DEV_CFG_S = {
+ .base = CMSDK_TIMER0_BASE_S};
+static struct cmsdk_timer_dev_data_t CMSDK_TIMER0_DEV_DATA_S = {
+ .is_initialized = 0};
+struct cmsdk_timer_dev_t CMSDK_TIMER0_DEV_S = {&(CMSDK_TIMER0_DEV_CFG_S),
+ &(CMSDK_TIMER0_DEV_DATA_S)};
+#endif
+#ifdef CMSDK_TIMER0_NS
+static const struct cmsdk_timer_dev_cfg_t CMSDK_TIMER0_DEV_CFG_NS = {
+ .base = CMSDK_TIMER0_BASE_NS};
+static struct cmsdk_timer_dev_data_t CMSDK_TIMER0_DEV_DATA_NS = {
+ .is_initialized = 0};
+struct cmsdk_timer_dev_t CMSDK_TIMER0_DEV_NS = {&(CMSDK_TIMER0_DEV_CFG_NS),
+ &(CMSDK_TIMER0_DEV_DATA_NS)};
+#endif
+
+#ifdef CMSDK_TIMER1_S
+static const struct cmsdk_timer_dev_cfg_t CMSDK_TIMER1_DEV_CFG_S = {
+ .base = CMSDK_TIMER1_BASE_S};
+static struct cmsdk_timer_dev_data_t CMSDK_TIMER1_DEV_DATA_S = {
+ .is_initialized = 0};
+struct cmsdk_timer_dev_t CMSDK_TIMER1_DEV_S = {&(CMSDK_TIMER1_DEV_CFG_S),
+ &(CMSDK_TIMER1_DEV_DATA_S)};
+#endif
+#ifdef CMSDK_TIMER1_NS
+static const struct cmsdk_timer_dev_cfg_t CMSDK_TIMER1_DEV_CFG_NS = {
+ .base = CMSDK_TIMER1_BASE_NS};
+static struct cmsdk_timer_dev_data_t CMSDK_TIMER1_DEV_DATA_NS = {
+ .is_initialized = 0};
+struct cmsdk_timer_dev_t CMSDK_TIMER1_DEV_NS = {&(CMSDK_TIMER1_DEV_CFG_NS),
+ &(CMSDK_TIMER1_DEV_DATA_NS)};
+#endif
+
+/* ARM MPC SSE 200 driver structures */
+#ifdef MPC_ISRAM0_S
+static const struct mpc_sie200_dev_cfg_t MPC_ISRAM0_DEV_CFG_S = {
+ .base = MPC_ISRAM0_BASE_S};
+static struct mpc_sie200_dev_data_t MPC_ISRAM0_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_ISRAM0_DEV_S = {
+ &(MPC_ISRAM0_DEV_CFG_S),
+ &(MPC_ISRAM0_DEV_DATA_S)};
+#endif
+
+#ifdef MPC_ISRAM1_S
+static const struct mpc_sie200_dev_cfg_t MPC_ISRAM1_DEV_CFG_S = {
+ .base = MPC_ISRAM1_BASE_S};
+static struct mpc_sie200_dev_data_t MPC_ISRAM1_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_ISRAM1_DEV_S = {
+ &(MPC_ISRAM1_DEV_CFG_S),
+ &(MPC_ISRAM1_DEV_DATA_S)};
+#endif
+
+#ifdef MPC_ISRAM2_S
+static const struct mpc_sie200_dev_cfg_t MPC_ISRAM2_DEV_CFG_S = {
+ .base = MPC_ISRAM2_BASE_S};
+static struct mpc_sie200_dev_data_t MPC_ISRAM2_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_ISRAM2_DEV_S = {
+ &(MPC_ISRAM2_DEV_CFG_S),
+ &(MPC_ISRAM2_DEV_DATA_S)};
+#endif
+
+#ifdef MPC_ISRAM3_S
+static const struct mpc_sie200_dev_cfg_t MPC_ISRAM3_DEV_CFG_S = {
+ .base = MPC_ISRAM3_BASE_S};
+static struct mpc_sie200_dev_data_t MPC_ISRAM3_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_ISRAM3_DEV_S = {
+ &(MPC_ISRAM3_DEV_CFG_S),
+ &(MPC_ISRAM3_DEV_DATA_S)};
+#endif
+
+#ifdef MPC_CODE_SRAM1_S
+static const struct mpc_sie200_dev_cfg_t MPC_CODE_SRAM1_DEV_CFG_S = {
+ .base = MPC_CODE_SRAM1_BASE_S};
+static struct mpc_sie200_dev_data_t MPC_CODE_SRAM1_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_CODE_SRAM1_DEV_S = {
+ &(MPC_CODE_SRAM1_DEV_CFG_S),
+ &(MPC_CODE_SRAM1_DEV_DATA_S)};
+#endif
+
+#ifdef MPC_CODE_SRAM2_S
+static const struct mpc_sie200_dev_cfg_t MPC_CODE_SRAM2_DEV_CFG_S = {
+ .base = MPC_CODE_SRAM2_BASE_S};
+static struct mpc_sie200_dev_data_t MPC_CODE_SRAM2_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_CODE_SRAM2_DEV_S = {
+ &(MPC_CODE_SRAM2_DEV_CFG_S),
+ &(MPC_CODE_SRAM2_DEV_DATA_S)};
+#endif
+
+#ifdef MPC_CODE_SRAM3_S
+static const struct mpc_sie200_dev_cfg_t MPC_CODE_SRAM3_DEV_CFG_S = {
+ .base = MPC_CODE_SRAM3_BASE_S};
+static struct mpc_sie200_dev_data_t MPC_CODE_SRAM3_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_CODE_SRAM3_DEV_S = {
+ &(MPC_CODE_SRAM3_DEV_CFG_S),
+ &(MPC_CODE_SRAM3_DEV_DATA_S)};
+#endif
diff --git a/platform/ext/target/sse_200_mps2/sse_200/retarget/platform_retarget_dev.h b/platform/ext/target/sse_200_mps2/sse_200/retarget/platform_retarget_dev.h
new file mode 100644
index 0000000..8837558
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/retarget/platform_retarget_dev.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_retarget_dev.h
+ * \brief The structure definitions in this file are exported based on the peripheral
+ * definitions from device_cfg.h.
+ * This retarget file is meant to be used as a helper for baremetal
+ * applications and/or as an example of how to configure the generic
+ * driver structures.
+ */
+
+#ifndef __ARM_LTD_SSE_200_RETARGET_DEV_H__
+#define __ARM_LTD_SSE_200_RETARGET_DEV_H__
+
+#include "device_cfg.h"
+
+/* ======= Includes generic driver headers ======= */
+#include "mpc_sie200_drv.h"
+#include "ppc_sse200_drv.h"
+#include "arm_uart_drv.h"
+#include "timer_cmsdk/timer_cmsdk.h"
+
+/* ======= Defines peripheral configuration structures ======= */
+/* ARM UART driver structures */
+#ifdef ARM_UART0_S
+extern struct arm_uart_dev_t ARM_UART0_DEV_S;
+#endif
+#ifdef ARM_UART0_NS
+extern struct arm_uart_dev_t ARM_UART0_DEV_NS;
+#endif
+
+#ifdef ARM_UART1_S
+extern struct arm_uart_dev_t ARM_UART1_DEV_S;
+#endif
+#ifdef ARM_UART1_NS
+extern struct arm_uart_dev_t ARM_UART1_DEV_NS;
+#endif
+
+#ifdef ARM_UART2_S
+extern struct arm_uart_dev_t ARM_UART2_DEV_S;
+#endif
+#ifdef ARM_UART2_NS
+extern struct arm_uart_dev_t ARM_UART2_DEV_NS;
+#endif
+
+#ifdef ARM_UART3_S
+extern struct arm_uart_dev_t ARM_UART3_DEV_S;
+#endif
+#ifdef ARM_UART3_NS
+extern struct arm_uart_dev_t ARM_UART3_DEV_NS;
+#endif
+
+#ifdef ARM_UART4_S
+extern struct arm_uart_dev_t ARM_UART4_DEV_S;
+#endif
+#ifdef ARM_UART4_NS
+extern struct arm_uart_dev_t ARM_UART4_DEV_NS;
+#endif
+
+/* ARM PPC driver structures */
+#ifdef AHB_PPC0_S
+extern struct ppc_sse200_dev_t AHB_PPC0_DEV_S;
+#endif
+
+#ifdef AHB_PPCEXP0_S
+extern struct ppc_sse200_dev_t AHB_PPCEXP0_DEV_S;
+#endif
+
+#ifdef AHB_PPCEXP1_S
+extern struct ppc_sie200_dev_t AHB_PPCEXP1_DEV_S;
+#endif
+
+#ifdef AHB_PPCEXP2_S
+extern struct ppc_sse200_dev_t AHB_PPCEXP2_DEV_S;
+#endif
+
+#ifdef AHB_PPCEXP3_S
+extern struct ppc_sse200_dev_t AHB_PPCEXP3_DEV_S;
+#endif
+
+#ifdef APB_PPC0_S
+extern struct ppc_sse200_dev_t APB_PPC0_DEV_S;
+#endif
+
+#ifdef APB_PPC1_S
+extern struct ppc_sse200_dev_t APB_PPC1_DEV_S;
+#endif
+
+#ifdef APB_PPCEXP0_S
+extern struct ppc_sse200_dev_t APB_PPCEXP0_DEV_S;
+#endif
+
+#ifdef APB_PPCEXP1_S
+extern struct ppc_sse200_dev_t APB_PPCEXP1_DEV_S;
+#endif
+
+#ifdef APB_PPCEXP2_S
+extern struct ppc_sse200_dev_t APB_PPCEXP2_DEV_S;
+#endif
+
+#ifdef APB_PPCEXP3_S
+extern struct ppc_sse200_dev_t APB_PPCEXP3_DEV_S;
+#endif
+
+/* CMSDK Timer driver structures */
+#ifdef CMSDK_TIMER0_S
+extern struct cmsdk_timer_dev_t CMSDK_TIMER0_DEV_S;
+#endif
+#ifdef CMSDK_TIMER0_NS
+extern struct cmsdk_timer_dev_t CMSDK_TIMER0_DEV_NS;
+#endif
+
+#ifdef CMSDK_TIMER1_S
+extern struct cmsdk_timer_dev_t CMSDK_TIMER1_DEV_S;
+#endif
+#ifdef CMSDK_TIMER1_NS
+extern struct cmsdk_timer_dev_t CMSDK_TIMER1_DEV_NS;
+#endif
+
+/* ARM MPC SSE 200 driver structures */
+#ifdef MPC_ISRAM0_S
+extern struct mpc_sie200_dev_t MPC_ISRAM0_DEV_S;
+#endif
+
+#ifdef MPC_ISRAM1_S
+extern struct mpc_sie200_dev_t MPC_ISRAM1_DEV_S;
+#endif
+
+#ifdef MPC_ISRAM2_S
+extern struct mpc_sie200_dev_t MPC_ISRAM2_DEV_S;
+#endif
+
+#ifdef MPC_ISRAM3_S
+extern struct mpc_sie200_dev_t MPC_ISRAM3_DEV_S;
+#endif
+
+#ifdef MPC_CODE_SRAM1_S
+extern struct mpc_sie200_dev_t MPC_CODE_SRAM1_DEV_S;
+#endif
+
+#ifdef MPC_CODE_SRAM2_S
+extern struct mpc_sie200_dev_t MPC_CODE_SRAM2_DEV_S;
+#endif
+
+#ifdef MPC_CODE_SRAM3_S
+extern struct mpc_sie200_dev_t MPC_CODE_SRAM3_DEV_S;
+#endif
+
+#endif /* __ARM_LTD_SSE_200_RETARGET_DEV_H__ */
diff --git a/platform/ext/target/sse_200_mps2/sse_200/retarget/platform_retarget_pins.h b/platform/ext/target/sse_200_mps2/sse_200/retarget/platform_retarget_pins.h
new file mode 100644
index 0000000..6664877
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/retarget/platform_retarget_pins.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_retarget_pins.h
+ * \brief This file defines all the pins for this platform.
+ */
+
+#ifndef __ARM_LTD_SSE_200_RETARGET_PINS_H__
+#define __ARM_LTD_SSE_200_RETARGET_PINS_H__
+
+/* AHB GPIO pin names */
+enum arm_gpio_pin_name_t {
+ AHB_GPIO0_0 = 0U,
+ AHB_GPIO0_1 = 1U,
+ AHB_GPIO0_2 = 2U,
+ AHB_GPIO0_3 = 3U,
+ AHB_GPIO0_4 = 4U,
+ AHB_GPIO0_5 = 5U,
+ AHB_GPIO0_6 = 6U,
+ AHB_GPIO0_7 = 7U,
+ AHB_GPIO0_8 = 8U,
+ AHB_GPIO0_9 = 9U,
+ AHB_GPIO0_10 = 10U,
+ AHB_GPIO0_11 = 11U,
+ AHB_GPIO0_12 = 12U,
+ AHB_GPIO0_13 = 13U,
+ AHB_GPIO0_14 = 14U,
+ AHB_GPIO0_15 = 15U,
+ AHB_GPIO1_0 = 0U,
+ AHB_GPIO1_1 = 1U,
+ AHB_GPIO1_2 = 2U,
+ AHB_GPIO1_3 = 3U,
+ AHB_GPIO1_4 = 4U,
+ AHB_GPIO1_5 = 5U,
+ AHB_GPIO1_6 = 6U,
+ AHB_GPIO1_7 = 7U,
+ AHB_GPIO1_8 = 8U,
+ AHB_GPIO1_9 = 9U,
+ AHB_GPIO1_10 = 10U,
+ AHB_GPIO1_11 = 11U,
+ AHB_GPIO1_12 = 12U,
+ AHB_GPIO1_13 = 13U,
+ AHB_GPIO1_14 = 14U,
+ AHB_GPIO1_15 = 15U,
+ AHB_GPIO2_0 = 0U,
+ AHB_GPIO2_1 = 1U,
+ AHB_GPIO2_2 = 2U,
+ AHB_GPIO2_3 = 3U,
+ AHB_GPIO2_4 = 4U,
+ AHB_GPIO2_5 = 5U,
+ AHB_GPIO2_6 = 6U,
+ AHB_GPIO2_7 = 7U,
+ AHB_GPIO2_8 = 8U,
+ AHB_GPIO2_9 = 9U,
+ AHB_GPIO2_10 = 10U,
+ AHB_GPIO2_11 = 11U,
+ AHB_GPIO2_12 = 12U,
+ AHB_GPIO2_13 = 13U,
+ AHB_GPIO2_14 = 14U,
+ AHB_GPIO2_15 = 15U,
+ AHB_GPIO3_0 = 0U,
+ AHB_GPIO3_1 = 1U,
+ AHB_GPIO3_2 = 2U,
+ AHB_GPIO3_3 = 3U,
+};
+
+/* Pin definitions for the MPS2 Arduino adapter shields.
+ * Reference: Application Note AN502 */
+
+/*
+ * Shield buttons adaptor
+ * The user buttons on the shield are linked to the pins 5 and 6 of GPIO1.
+ */
+#define SHIELD_ADAPTOR_PB0 AHB_GPIO1_5
+#define SHIELD_ADAPTOR_PB1 AHB_GPIO1_6
+
+/* GPIO shield 0 definition */
+#define SH0_UART_RX AHB_GPIO0_0
+#define SH0_UART_TX AHB_GPIO0_4
+#define SH0_I2C_SCL AHB_GPIO0_5
+#define SH0_I2C_SDA AHB_GPIO0_15
+#define SH0_SPI_SCK AHB_GPIO0_11
+#define SH0_SPI_SS AHB_GPIO0_12
+#define SH0_SPI_MOSI AHB_GPIO0_13
+#define SH0_SPI_MISO AHB_GPIO0_14
+#define SH0_LED_RED AHB_GPIO0_6
+#define SH0_LED_GREEN AHB_GPIO0_10
+#define SH0_LED_BLUE AHB_GPIO0_9
+#define SH0_SPEAKER AHB_GPIO0_7
+#define SH0_LCD_CS SH0_SPI_SS
+#define SH0_LCD_A0 AHB_GPIO0_8
+#define SH0_LCD_RST SH0_SPI_MISO
+#define SH0_JT AHB_GPIO0_1
+
+/* GPIO shield 1 definition */
+#define SH1_UART_RX AHB_GPIO1_10
+#define SH1_UART_TX AHB_GPIO1_14
+#define SH1_I2C_SCL AHB_GPIO1_15
+#define SH1_I2C_SDA AHB_GPIO2_9
+#define SH1_SPI_SS AHB_GPIO2_6
+#define SH1_SPI_MOSI AHB_GPIO2_7
+#define SH1_SPI_MISO AHB_GPIO2_8
+#define SH1_SPI_SCK AHB_GPIO2_12
+#define SH1_LED_RED AHB_GPIO2_0
+#define SH1_LED_GREEN AHB_GPIO2_4
+#define SH1_LED_BLUE AHB_GPIO2_3
+#define SH1_SPEAKER AHB_GPIO2_1
+#define SH1_LCD_CS SH1_SPI_SS
+#define SH1_LCD_A0 AHB_GPIO2_2
+#define SH1_LCD_RST SH1_SPI_MISO
+#define SH1_JT AHB_GPIO1_11
+
+/* GPIO ADC SPI */
+#define ADC_SPI_SS AHB_GPIO1_0
+#define ADC_SPI_MOSI AHB_GPIO1_1
+#define ADC_SPI_MISO AHB_GPIO1_2
+#define ADC_SPI_SCK AHB_GPIO1_3
+
+/* GPIO BlueTooth/XBEE UART */
+#define BT_UART_RX AHB_GPIO1_7
+#define BT_UART_TX AHB_GPIO1_8
+#define BT_BOOT AHB_GPIO1_9
+
+#endif /* __ARM_LTD_SSE_200_RETARGET_PINS_H__ */
diff --git a/platform/ext/target/sse_200_mps2/target_cfg.c b/platform/ext/target/sse_200_mps2/target_cfg.c
new file mode 100644
index 0000000..65904d6
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/target_cfg.c
@@ -0,0 +1,292 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <arm_cmse.h>
+
+#include "cmsis.h"
+#include "target_cfg.h"
+#include "Driver_MPC.h"
+#include "platform_retarget_dev.h"
+#include "region_defs.h"
+#include "tfm_secure_api.h"
+
+/*
+ * This function pointer is meant to only hold non secure function pointers.
+ * It will be turned into a non-secure one (LSB cleared) before being called
+ * whatever happens anyway (unless cast to another function pointer type).
+ * Registers will be cleared before branching so that no information leaks
+ * from secure to non-secure world.
+ */
+typedef void __attribute__((cmse_nonsecure_call)) (*nsfptr_t) (void);
+
+/* Allows software, via SAU, to define the code region as a NSC */
+#define NSCCFG_CODENSC 1
+
+/* Import MPC driver */
+extern ARM_DRIVER_MPC Driver_SRAM1_MPC, Driver_SRAM2_MPC;
+
+/* Define Peripherals NS address range for the platform */
+#define PERIPHERALS_BASE_NS_START (0x40000000)
+#define PERIPHERALS_BASE_NS_END (0x4FFFFFFF)
+
+void configure_ns_code()
+{
+ /* SCB_NS.VTOR points to the Non-secure vector table base address */
+ SCB_NS->VTOR = (NS_CODE_START);
+
+ /* Setups Main stack pointer of the non-secure code */
+ uint32_t ns_msp = *((uint32_t*)(NS_CODE_START));
+ __TZ_set_MSP_NS(ns_msp);
+}
+
+void jump_to_ns_code()
+{
+ /* The entry contains address of the Reset_handler (CMSIS-CORE) function */
+ uint32_t entry_ptr = *((uint32_t*)(NS_CODE_START + 4));
+
+ /* Clears LSB of the function address to indicate the function-call
+ will perform the switch from secure to non-secure */
+ nsfptr_t ns_entry = (nsfptr_t) cmse_nsfptr_create(entry_ptr);
+
+ /* All changes made to memory will be effective after this point */
+ __DSB();
+ __ISB();
+
+ /* Calls the non-secure Reset_Handler to jump to the non-secure binary */
+ ns_entry();
+}
+
+void enable_fault_handlers(void)
+{
+ /* Enables BUS, MEM, USG and Secure faults */
+ SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk
+ | SCB_SHCSR_BUSFAULTENA_Msk
+ | SCB_SHCSR_MEMFAULTENA_Msk
+ | SCB_SHCSR_SECUREFAULTENA_Msk;
+
+ /* CFSR register setting to enable precise errors */
+ SCB->CFSR |= SCB_CFSR_PRECISERR_Msk;
+}
+
+/*------------------- NVIC interrupt target state to NS configuration ----------*/
+void nvic_interrupt_target_state_cfg()
+{
+ /* Target every interrupt to NS; unimplemented interrupts will be WI */
+ for (uint8_t i=0; i<sizeof(NVIC->ITNS)/sizeof(NVIC->ITNS[0]); i++) {
+ NVIC->ITNS[i] = 0xFFFFFFFF;
+ }
+
+ /* Make sure that MPC and PPC are targeted to S state */
+ NVIC_ClearTargetState(MPC_IRQn);
+ NVIC_ClearTargetState(PPC_IRQn);
+
+ /* UART1 is a secure peripheral, so its IRQs have to target S state */
+ NVIC_ClearTargetState(UARTRX1_IRQn);
+ NVIC_ClearTargetState(UARTTX1_IRQn);
+ NVIC_ClearTargetState(UART1_IRQn);
+}
+
+/*------------------- NVIC interrupt enabling for S peripherals ----------------*/
+void nvic_interrupt_enable()
+{
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+
+ /* MPC interrupt enabling */
+ Driver_SRAM1_MPC.EnableInterrupt();
+ Driver_SRAM2_MPC.EnableInterrupt();
+ NVIC_EnableIRQ(MPC_IRQn);
+
+ /* PPC interrupt enabling */
+ /* Clear pending PPC interrupts */
+ /* In the PPC configuration function, we have used the Non-Secure
+ * Privilege Control Block to grant unprivilged NS access to some
+ * peripherals used by NS. That triggers a PPC0 exception as that
+ * register is meant for NS privileged access only. Clear it here
+ */
+ spctrl->secppcintclr |= CMSDK_APB_PPC0_INT_POS_MASK;
+
+ /* Enable PPC interrupts for APB PPC */
+ spctrl->secppcinten |= CMSDK_APB_PPC0_INT_POS_MASK;
+ spctrl->secppcinten |= CMSDK_APB_PPC1_INT_POS_MASK;
+ spctrl->secppcinten |= CMSDK_APB_PPCEXP0_INT_POS_MASK;
+ spctrl->secppcinten |= CMSDK_APB_PPCEXP1_INT_POS_MASK;
+ spctrl->secppcinten |= CMSDK_APB_PPCEXP2_INT_POS_MASK;
+ spctrl->secppcinten |= CMSDK_APB_PPCEXP3_INT_POS_MASK;
+ NVIC_EnableIRQ(PPC_IRQn);
+}
+
+/*------------------- SAU/IDAU configuration functions -------------------------*/
+
+void sau_and_idau_cfg(void)
+{
+ /* Enables SAU */
+ TZ_SAU_Enable();
+
+ /* Configures SAU regions to be non-secure */
+ SAU->RNR = TFM_NS_REGION_CODE;
+ SAU->RBAR = (NS_PARTITION_START & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = (NS_PARTITION_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
+
+ SAU->RNR = TFM_NS_REGION_DATA;
+ SAU->RBAR = (NS_DATA_START & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = (NS_DATA_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
+
+ /* Configures veneers region to be non-secure callable */
+ SAU->RNR = TFM_NS_REGION_VENEER;
+ SAU->RBAR = (CMSE_VENEER_REGION_START & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = (CMSE_VENEER_REGION_LIMIT & SAU_RLAR_LADDR_Msk)
+ | SAU_RLAR_ENABLE_Msk
+ | SAU_RLAR_NSC_Msk;
+
+ /* Configure the peripherals space */
+ /* Only UART1 is configured as a secure peripheral */
+ SAU->RNR = TFM_NS_REGION_PERIPH_1;
+ SAU->RBAR = (PERIPHERALS_BASE_NS_START & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = ((UART1_BASE_NS-1) & SAU_RLAR_LADDR_Msk)
+ | SAU_RLAR_ENABLE_Msk;
+
+ /* The UART1 range is considered as a (secure) gap */
+
+ SAU->RNR = TFM_NS_REGION_PERIPH_2;
+ SAU->RBAR = (UART2_BASE_NS & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = (PERIPHERALS_BASE_NS_END & SAU_RLAR_LADDR_Msk)
+ | SAU_RLAR_ENABLE_Msk;
+
+ /* Allows SAU to define the code region as a NSC */
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ spctrl->nsccfg |= NSCCFG_CODENSC;
+}
+
+/*------------------- Memory configuration functions -------------------------*/
+
+void mpc_init_cfg(void)
+{
+ Driver_SRAM1_MPC.Initialize();
+ Driver_SRAM1_MPC.ConfigRegion(NS_PARTITION_START,
+ NS_PARTITION_LIMIT,
+ ARM_MPC_ATTR_NONSECURE);
+
+ Driver_SRAM2_MPC.Initialize();
+ Driver_SRAM2_MPC.ConfigRegion(NS_DATA_START, NS_DATA_LIMIT,
+ ARM_MPC_ATTR_NONSECURE);
+
+ /* Lock down the MPC configuration */
+ Driver_SRAM1_MPC.LockDown();
+ Driver_SRAM2_MPC.LockDown();
+
+ /* Add barriers to assure the MPC configuration is done before continue
+ * the execution. */
+ __DSB();
+ __ISB();
+}
+
+/*------------------- PPC configuration functions -------------------------*/
+
+void ppc_init_cfg(void)
+{
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ struct nspctrl_def* nspctrl = CMSDK_NSPCTRL;
+
+ /* Grant non-secure access to peripherals in the PPC0
+ * (timer0 and 1, dualtimer, watchdog, mhu 0 and 1) */
+ spctrl->apbnsppc0 |= (1U << CMSDK_TIMER0_APB_PPC_POS);
+ spctrl->apbnsppc0 |= (1U << CMSDK_TIMER1_APB_PPC_POS);
+ spctrl->apbnsppc0 |= (1U << CMSDK_DTIMER_APB_PPC_POS);
+ spctrl->apbnsppc0 |= (1U << CMSDK_MHU0_APB_PPC_POS);
+ spctrl->apbnsppc0 |= (1U << CMSDK_MHU1_APB_PPC_POS);
+ /* Grant non-secure access to S32K Timer in PPC1*/
+ spctrl->apbnsppc1 |= (1U << CMSDK_S32K_TIMER_PPC_POS);
+ /* Grant non-secure access for APB peripherals on EXP1 */
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_SPI0_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_SPI1_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_SPI2_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_SPI3_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_SPI4_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_UART0_APB_PPC_POS);
+ /* Do not do it for UART1 as it's a Secure peripheral */
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_UART2_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_UART3_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_UART4_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_I2C0_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_I2C1_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_I2C2_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_I2C3_APB_PPC_POS);
+ /* Grant non-secure access for APB peripherals on EXP2 */
+ spctrl->apbnsppcexp2 |= (1U << CMSDK_FPGA_SCC_PPC_POS);
+ spctrl->apbnsppcexp2 |= (1U << CMSDK_FPGA_AUDIO_PPC_POS);
+ spctrl->apbnsppcexp2 |= (1U << CMSDK_FPGA_IO_PPC_POS);
+ /* Grant non-secure access for AHB peripherals on PPC0 */
+ spctrl->ahbnsppc0 |= (1U << CMSDK_VGA_PPC_POS);
+ spctrl->ahbnsppc0 |= (1U << CMSDK_GPIO0_PPC_POS);
+ spctrl->ahbnsppc0 |= (1U << CMSDK_GPIO1_PPC_POS);
+ spctrl->ahbnsppc0 |= (1U << CMSDK_GPIO2_PPC_POS);
+ spctrl->ahbnsppc0 |= (1U << CMSDK_GPIO3_PPC_POS);
+
+ /* Grant non-secure access to all peripherals on AHB EXP:
+ * The SSE-200 doesn't have any peripheral connected to
+ * the AHB expansions. But the SIE-200 has peripherals,
+ * in particular the Ethernet driver on EXP1. Make sure
+ * that all possible peripherals are enabled by default
+ */
+ spctrl->ahbnsppcexp0 = 0xFFFFFFFF;
+ spctrl->ahbnsppcexp1 = 0xFFFFFFFF;
+ spctrl->ahbnsppcexp2 = 0xFFFFFFFF;
+ spctrl->ahbnsppcexp3 = 0xFFFFFFFF;
+
+ /* in NS, grant un-privileged for UART0 */
+ nspctrl->apbnspppcexp1 |= (1U << CMSDK_UART0_APB_PPC_POS);
+
+ /* in NS, grant un-privileged access for LEDs */
+ nspctrl->apbnspppcexp2 |= (1U << CMSDK_FPGA_SCC_PPC_POS);
+ nspctrl->apbnspppcexp2 |= (1U << CMSDK_FPGA_IO_PPC_POS);
+
+ /* Configure the response to a security violation as a
+ * bus error instead of RAZ/WI */
+ spctrl->secrespcfg |= 1U;
+}
+
+void ppc_configure_to_non_secure(enum ppc_bank_e bank, uint16_t pos)
+{
+ /* Clear NS flag for peripheral to prevent NS access */
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ ((uint32_t*)&(spctrl->ahbnsppc0))[bank] |= (1U << pos);
+}
+
+void ppc_configure_to_secure(enum ppc_bank_e bank, uint16_t pos)
+{
+ /* Clear NS flag for peripheral to prevent NS access */
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ ((uint32_t*)&(spctrl->ahbnsppc0))[bank] &= ~(1U << pos);
+}
+
+void ppc_en_secure_unpriv(enum ppc_bank_e bank, uint16_t pos)
+{
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ ((uint32_t*)&(spctrl->ahbspppc0))[bank] |= (1U << pos);
+}
+
+void ppc_clr_secure_unpriv(enum ppc_bank_e bank, uint16_t pos)
+{
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ ((uint32_t*)&(spctrl->ahbspppc0))[bank] &= ~(1U << pos);
+}
+
+void ppc_clear_irq(void)
+{
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ /* Clear APC PPC EXP2 IRQ */
+ spctrl->secppcintclr |= CMSDK_APB_PPCEXP2_INT_POS_MASK;
+}
diff --git a/platform/ext/target/sse_200_mps2/target_cfg.h b/platform/ext/target/sse_200_mps2/target_cfg.h
new file mode 100644
index 0000000..e41f7a2
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/target_cfg.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SSE200_TARGET_CFG_H__
+#define __SSE200_TARGET_CFG_H__
+
+enum ppc_bank_e
+{
+ PPC_SP_AHB_PPC0 = 0,
+ PPC_SP_RES0,
+ PPC_SP_RES1,
+ PPC_SP_RES2,
+ PPC_SP_AHB_PPC_EXP0,
+ PPC_SP_AHB_PPC_EXP1,
+ PPC_SP_AHB_PPC_EXP2,
+ PPC_SP_AHB_PPC_EXP3,
+ PPC_SP_APB_PPC0,
+ PPC_SP_APB_PPC1,
+ PPC_SP_RES3,
+ PPC_SP_RES4,
+ PPC_SP_APB_PPC_EXP0,
+ PPC_SP_APB_PPC_EXP1,
+ PPC_SP_APB_PPC_EXP2,
+ PPC_SP_APB_PPC_EXP3,
+};
+
+/**
+ * \brief Configures non-secure code.
+ */
+void configure_ns_code(void);
+
+/**
+ * \brief Jumps to non-secure code.
+ */
+void jump_to_ns_code(void);
+
+/**
+ * \brief Enables the fault handlers BusFault, UsageFault,
+ * MemManageFault and SecureFault.
+ */
+void enable_fault_handlers(void);
+
+/**
+ * \brief Configures all external interrupts to target the
+ * NS state, apart for the ones associated to secure
+ * peripherals (plus MPC and PPC)
+ */
+void nvic_interrupt_target_state_cfg();
+
+/**
+ * \brief This function enable the interrupts associated
+ * to the secure peripherals (plus MPC and PPC)
+ */
+void nvic_interrupt_enable();
+
+/**
+ * \brief Configures the Memory Protection Controller.
+ */
+void mpc_init_cfg(void);
+
+/**
+ * \brief Configures the Peripheral Protection Controller.
+ */
+void ppc_init_cfg(void);
+
+/**
+ * \brief Restict access to peripheral to secure
+ */
+void ppc_configure_to_secure(enum ppc_bank_e bank, uint16_t loc);
+
+/**
+ * \brief Allow non-secure access to peripheral
+ */
+void ppc_configure_to_non_secure(enum ppc_bank_e bank, uint16_t loc);
+
+/**
+ * \brief Enable secure unprivileged access to peripheral
+ */
+void ppc_en_secure_unpriv(enum ppc_bank_e bank, uint16_t pos);
+
+/**
+ * \brief Clear secure unprivileged access to peripheral
+ */
+void ppc_clr_secure_unpriv(enum ppc_bank_e bank, uint16_t pos);
+
+/**
+ * \brief Clears PPC interrupt.
+ */
+void ppc_clear_irq(void);
+
+/**
+ * \brief Configures SAU and IDAU.
+ */
+void sau_and_idau_cfg(void);
+
+
+#endif /* __SSE200_TARGET_CFG_H__ */