commit 0b572be0b231f649ea26659270b02e0e92146ef3
author Vishnu Banavath <vishnu.banavath@arm.com> Sat Mar 14 14:46:06 2020 +0000
committer Vishnu Banavath <vishnu.banavath@arm.com> Wed Jul 22 09:25:45 2020 +0100
tree a54870e6e7a1b3e8a96dab19af5f5a59c58a7a7a
parent dcc1ef71eebdaa02d03f304993e3f8327ba63758

Build: Compile the cc312 driver for Cortex-M0+ host processor

These change are made to provide an option to build
CC312 hardware crypto driver for cortex-m0plus host processor.

Change-Id: I614d8901aa55617aab72a9f83f0b8faa039a3f2a
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>

platform/ext/common/cc312/cc312.c

diff --git a/platform/ext/common/cc312/cc312.c b/platform/ext/common/cc312/cc312.c
index 503110f9..400260e 100644
--- a/platform/ext/common/cc312/cc312.c
+++ b/platform/ext/common/cc312/cc312.c
@@ -20,6 +20,8 @@
 #include "prod_hw_defs.h"
 #include "cc_otp_defs.h"
 
+#include "region_defs.h"
+
 #define CC312_NULL_CONTEXT "NO SALT!"
 
 CCRndContext_t*           CC312_pRndCtx         = NULL;
@@ -34,9 +36,16 @@
     CC_UNUSED_PARAM(buffType);
 
     *pBuffNs = DATA_BUFFER_IS_SECURE;
+#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
     if (cmse_check_address_range((void*)pDataBuffer, buffSize, CMSE_NONSECURE)) {
         *pBuffNs = DATA_BUFFER_IS_NONSECURE;
     }
+#else
+    if (pDataBuffer >= (uint8_t *)NS_DATA_START &&
+        (pDataBuffer + buffSize) <= (uint8_t *)NS_DATA_LIMIT) {
+        *pBuffNs = DATA_BUFFER_IS_NONSECURE;
+    }
+#endif
 
     return CC_OK;
 }