commit 4e51dd1b3eb6eddfd1cb878c694e74718158b43b
author Matthew Dalzell <matthew.dalzell@arm.com> Mon Mar 11 11:28:30 2024 +0000
committer Anton Komlev <Anton.Komlev@arm.com> Tue Mar 12 14:46:20 2024 +0100
tree 29d54c9a37528295e8d3f6317cc680e47cbdad64
parent 58b64e359727703cfd502a62f565298639e5367c

Aligning with CMSIS-6 update for profiling.

Removes usage of (deprecated) `CoreDebug` in favour of `DCB`.

Change-Id: I05ad7b686dc0faff22249c23db9c056373999ea2
Signed-off-by: Matthew Dalzell <matthew.dalzell@arm.com>

profiling/export/platform/tfm_hal_dwt_prof.c

diff --git a/profiling/export/platform/tfm_hal_dwt_prof.c b/profiling/export/platform/tfm_hal_dwt_prof.c
index 4f81100..f757fc0 100644
--- a/profiling/export/platform/tfm_hal_dwt_prof.c
+++ b/profiling/export/platform/tfm_hal_dwt_prof.c
@@ -10,7 +10,7 @@
 /* Initialize the timer/cycle counter hardware for profiling */
 void prof_hal_init(void)
 {
-    CoreDebug->DEMCR = CoreDebug_DEMCR_TRCENA_Msk; /* Enable DWT. */
+    DCB->DEMCR       = DCB_DEMCR_TRCENA_Msk; /* Enable DWT. */
     DWT->CTRL        = DWT_CTRL_CYCCNTENA_Msk;     /* Enable CYCCNT. */
     DWT->CYCCNT      = 0x0;                        /* Reset the processor cycle counter. */
 }