1. 3443a70 Fix MISRA C issues in BL1/BL2/BL31 by John Powell · 5 years ago
  2. c3e8b0b AArch32: Disable Secure Cycle Counter by Alexei Fedorov · 6 years ago
  3. c250cc3 SSBS: init SPSR register with default SSBS value by John Tsichritzis · 6 years ago
  4. e1abd56 arch: add some defines for generic timer registers by Yann Gautier · 6 years ago
  5. bd39370 Cortex-A53: Workarounds for 819472, 824069 and 827319 by Ambroise Vincent · 6 years ago
  6. ed4fc6f Disable processor Cycle Counting in Secure state by Antonio Nino Diaz · 6 years ago
  7. 29a2413 drivers: generic_delay_timer: Assert presence of Generic Timer by Antonio Nino Diaz · 7 years ago
  8. 2559b2c xlat v2: Dynamically detect need for CnP bit by Antonio Nino Diaz · 7 years ago
  9. 09d40e0 Sanitise includes across codebase by Antonio Nino Diaz · 7 years ago
  10. f5478de Reorganize architecture-dependent header files by Antonio Nino Diaz · 7 years ago[Renamed from include/lib/aarch32/arch.h]
  11. 3f99f7e Merge pull request #1731 from miyatsu/doc-fix-20181225 by Antonio Niño Díaz · 7 years ago