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Ghennadi Procopciuc7c362092024-06-12 07:38:52 +03001/*
2 * Copyright 2020-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#include <s32cc-clk-ids.h>
7#include <s32cc-clk-modules.h>
8#include <s32cc-clk-utils.h>
9
10/* Oscillators */
11static struct s32cc_osc fxosc =
12 S32CC_OSC_INIT(S32CC_FXOSC);
13static struct s32cc_clk fxosc_clk =
14 S32CC_MODULE_CLK(fxosc);
15
16static struct s32cc_osc firc =
17 S32CC_OSC_INIT(S32CC_FIRC);
18static struct s32cc_clk firc_clk =
19 S32CC_MODULE_CLK(firc);
20
21static struct s32cc_osc sirc =
22 S32CC_OSC_INIT(S32CC_SIRC);
23static struct s32cc_clk sirc_clk =
24 S32CC_MODULE_CLK(sirc);
25
Ghennadi Procopciuca8be7482024-06-12 09:53:18 +030026/* ARM PLL */
27static struct s32cc_clkmux arm_pll_mux =
28 S32CC_CLKMUX_INIT(S32CC_ARM_PLL, 0, 2,
29 S32CC_CLK_FIRC,
30 S32CC_CLK_FXOSC, 0, 0, 0);
31static struct s32cc_clk arm_pll_mux_clk =
32 S32CC_MODULE_CLK(arm_pll_mux);
33static struct s32cc_pll armpll =
34 S32CC_PLL_INIT(arm_pll_mux_clk, S32CC_ARM_PLL, 2);
35static struct s32cc_clk arm_pll_vco_clk =
36 S32CC_FREQ_MODULE_CLK(armpll, 1400 * MHZ, 2000 * MHZ);
37
38static struct s32cc_pll_out_div arm_pll_phi0_div =
39 S32CC_PLL_OUT_DIV_INIT(armpll, 0);
40static struct s32cc_clk arm_pll_phi0_clk =
41 S32CC_FREQ_MODULE_CLK(arm_pll_phi0_div, 0, GHZ);
42
43static struct s32cc_clk *s32cc_hw_clk_list[5] = {
Ghennadi Procopciuc7c362092024-06-12 07:38:52 +030044 /* Oscillators */
45 [S32CC_CLK_ID(S32CC_CLK_FIRC)] = &firc_clk,
46 [S32CC_CLK_ID(S32CC_CLK_SIRC)] = &sirc_clk,
47 [S32CC_CLK_ID(S32CC_CLK_FXOSC)] = &fxosc_clk,
Ghennadi Procopciuca8be7482024-06-12 09:53:18 +030048 /* ARM PLL */
49 [S32CC_CLK_ID(S32CC_CLK_ARM_PLL_PHI0)] = &arm_pll_phi0_clk,
Ghennadi Procopciuc7c362092024-06-12 07:38:52 +030050};
51
52static struct s32cc_clk_array s32cc_hw_clocks = {
53 .type_mask = S32CC_CLK_TYPE(S32CC_CLK_FIRC),
54 .clks = &s32cc_hw_clk_list[0],
55 .n_clks = ARRAY_SIZE(s32cc_hw_clk_list),
56};
57
Ghennadi Procopciuca8be7482024-06-12 09:53:18 +030058static struct s32cc_clk *s32cc_arch_clk_list[2] = {
59 /* ARM PLL */
60 [S32CC_CLK_ID(S32CC_CLK_ARM_PLL_MUX)] = &arm_pll_mux_clk,
61 [S32CC_CLK_ID(S32CC_CLK_ARM_PLL_VCO)] = &arm_pll_vco_clk,
62};
63
64static struct s32cc_clk_array s32cc_arch_clocks = {
65 .type_mask = S32CC_CLK_TYPE(S32CC_CLK_ARM_PLL_MUX),
66 .clks = &s32cc_arch_clk_list[0],
67 .n_clks = ARRAY_SIZE(s32cc_arch_clk_list),
68};
69
Ghennadi Procopciuc7c362092024-06-12 07:38:52 +030070struct s32cc_clk *s32cc_get_arch_clk(unsigned long id)
71{
Ghennadi Procopciuca8be7482024-06-12 09:53:18 +030072 static const struct s32cc_clk_array *clk_table[2] = {
Ghennadi Procopciuc7c362092024-06-12 07:38:52 +030073 &s32cc_hw_clocks,
Ghennadi Procopciuca8be7482024-06-12 09:53:18 +030074 &s32cc_arch_clocks,
Ghennadi Procopciuc7c362092024-06-12 07:38:52 +030075 };
76
77 return s32cc_get_clk_from_table(clk_table, ARRAY_SIZE(clk_table), id);
78}