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Sandrine Bailleux01b916b2014-07-17 16:06:39 +01001/*
Dan Handleyf8b0b222015-03-19 19:22:44 +00002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Sandrine Bailleux01b916b2014-07-17 16:06:39 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <bl_common.h>
Sandrine Bailleux23d39db2015-11-18 11:10:30 +000034#include <cortex_a53.h>
Sandrine Bailleux01b916b2014-07-17 16:06:39 +010035#include <cortex_a57.h>
Dan Handleyf8b0b222015-03-19 19:22:44 +000036#include <v2m_def.h>
Sandrine Bailleux01b916b2014-07-17 16:06:39 +010037#include "../juno_def.h"
38
Dan Handleyf8b0b222015-03-19 19:22:44 +000039
Sandrine Bailleux01b916b2014-07-17 16:06:39 +010040 .globl plat_reset_handler
David Wang371d4392015-10-22 13:30:50 +080041 .globl plat_arm_calc_core_pos
Sandrine Bailleux01b916b2014-07-17 16:06:39 +010042
Sandrine Bailleux23d39db2015-11-18 11:10:30 +000043#define JUNO_REVISION(rev) REV_JUNO_R##rev
44#define JUNO_HANDLER(rev) plat_reset_handler_juno_r##rev
45#define JUMP_TO_HANDLER_IF_JUNO_R(revision) \
46 jump_to_handler JUNO_REVISION(revision), JUNO_HANDLER(revision)
47
Sandrine Bailleux9454d312015-02-04 14:06:10 +000048 /* --------------------------------------------------------------------
Sandrine Bailleux23d39db2015-11-18 11:10:30 +000049 * Helper macro to jump to the given handler if the board revision
50 * matches.
51 * Expects the Juno board revision in x0.
52 * --------------------------------------------------------------------
53 */
54 .macro jump_to_handler _revision, _handler
55 cmp x0, #\_revision
56 b.eq \_handler
57 .endm
58
59 /* --------------------------------------------------------------------
60 * Helper macro that reads the part number of the current CPU and jumps
61 * to the given label if it matches the CPU MIDR provided.
Sandrine Bailleux01b916b2014-07-17 16:06:39 +010062 *
Sandrine Bailleux23d39db2015-11-18 11:10:30 +000063 * Clobbers x0.
64 * --------------------------------------------------------------------
65 */
66 .macro jump_if_cpu_midr _cpu_midr, _label
67 mrs x0, midr_el1
68 ubfx x0, x0, MIDR_PN_SHIFT, #12
69 cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
70 b.eq \_label
71 .endm
72
73 /* --------------------------------------------------------------------
74 * Platform reset handler for Juno R0.
75 *
76 * Juno R0 has the following topology:
77 * - Quad core Cortex-A53 processor cluster;
78 * - Dual core Cortex-A57 processor cluster.
79 *
80 * This handler does the following:
Sandrine Bailleux9454d312015-02-04 14:06:10 +000081 * - Implement workaround for defect id 831273 by enabling an event
82 * stream every 65536 cycles.
83 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
84 * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
Sandrine Bailleux23d39db2015-11-18 11:10:30 +000085 * --------------------------------------------------------------------
86 */
87func JUNO_HANDLER(0)
88 /* --------------------------------------------------------------------
89 * Enable the event stream every 65536 cycles
90 * --------------------------------------------------------------------
91 */
92 mov x0, #(0xf << EVNTI_SHIFT)
93 orr x0, x0, #EVNTEN_BIT
94 msr CNTKCTL_EL1, x0
95
96 /* --------------------------------------------------------------------
97 * Nothing else to do on Cortex-A53.
98 * --------------------------------------------------------------------
99 */
100 jump_if_cpu_midr CORTEX_A53_MIDR, 1f
101
102 /* --------------------------------------------------------------------
103 * Cortex-A57 specific settings
104 * --------------------------------------------------------------------
105 */
106 mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
107 (L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT))
108 msr L2CTLR_EL1, x0
1091:
110 isb
111 ret
112endfunc JUNO_HANDLER(0)
113
114 /* --------------------------------------------------------------------
115 * Platform reset handler for Juno R1.
Sandrine Bailleux9454d312015-02-04 14:06:10 +0000116 *
Sandrine Bailleux23d39db2015-11-18 11:10:30 +0000117 * Juno R1 has the following topology:
118 * - Quad core Cortex-A53 processor cluster;
119 * - Dual core Cortex-A57 processor cluster.
120 *
121 * This handler does the following:
Sandrine Bailleux9454d312015-02-04 14:06:10 +0000122 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
Sandrine Bailleux23d39db2015-11-18 11:10:30 +0000123 *
Sandrine Bailleux9454d312015-02-04 14:06:10 +0000124 * Note that:
125 * - The default value for the L2 Tag RAM latency for Cortex-A57 is
126 * suitable.
Sandrine Bailleux23d39db2015-11-18 11:10:30 +0000127 * - Defect #831273 doesn't affect Juno R1.
Sandrine Bailleux9454d312015-02-04 14:06:10 +0000128 * --------------------------------------------------------------------
Sandrine Bailleux01b916b2014-07-17 16:06:39 +0100129 */
Sandrine Bailleux23d39db2015-11-18 11:10:30 +0000130func JUNO_HANDLER(1)
Sandrine Bailleux9454d312015-02-04 14:06:10 +0000131 /* --------------------------------------------------------------------
Sandrine Bailleux23d39db2015-11-18 11:10:30 +0000132 * Nothing to do on Cortex-A53.
Sandrine Bailleux9454d312015-02-04 14:06:10 +0000133 * --------------------------------------------------------------------
134 */
Sandrine Bailleux23d39db2015-11-18 11:10:30 +0000135 jump_if_cpu_midr CORTEX_A57_MIDR, A57
Sandrine Bailleux9454d312015-02-04 14:06:10 +0000136 ret
137
138A57:
139 /* --------------------------------------------------------------------
140 * Cortex-A57 specific settings
141 * --------------------------------------------------------------------
142 */
Sandrine Bailleux23d39db2015-11-18 11:10:30 +0000143 mov x0, #(L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT)
Sandrine Bailleux01b916b2014-07-17 16:06:39 +0100144 msr L2CTLR_EL1, x0
Sandrine Bailleux01b916b2014-07-17 16:06:39 +0100145 isb
Sandrine Bailleux01b916b2014-07-17 16:06:39 +0100146 ret
Sandrine Bailleux23d39db2015-11-18 11:10:30 +0000147endfunc JUNO_HANDLER(1)
148
149 /* --------------------------------------------------------------------
150 * Platform reset handler for Juno R2.
151 *
152 * Juno R2 has the following topology:
153 * - Quad core Cortex-A53 processor cluster;
154 * - Dual core Cortex-A72 processor cluster.
155 *
156 * This handler does nothing.
157 * --------------------------------------------------------------------
158 */
159func JUNO_HANDLER(2)
160 ret
161endfunc JUNO_HANDLER(2)
162
163 /* --------------------------------------------------------------------
164 * void plat_reset_handler(void);
165 *
166 * Determine the Juno board revision and call the appropriate reset
167 * handler.
168 * --------------------------------------------------------------------
169 */
170func plat_reset_handler
171 /* Read the V2M SYS_ID register */
172 mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID)
173 ldr w1, [x0]
174 /* Extract board revision from the SYS_ID */
175 ubfx x0, x1, #V2M_SYS_ID_REV_SHIFT, #4
176
177 JUMP_TO_HANDLER_IF_JUNO_R(0)
178 JUMP_TO_HANDLER_IF_JUNO_R(1)
179 JUMP_TO_HANDLER_IF_JUNO_R(2)
180
181 /* Board revision is not supported */
182not_supported:
183 b not_supported
184
Kévin Petit8b779622015-03-24 14:03:57 +0000185endfunc plat_reset_handler
David Wang371d4392015-10-22 13:30:50 +0800186
187 /* -----------------------------------------------------
188 * unsigned int plat_arm_calc_core_pos(uint64_t mpidr)
189 * Helper function to calculate the core position.
190 * -----------------------------------------------------
191 */
192func plat_arm_calc_core_pos
193 b css_calc_core_pos_swap_cluster
194endfunc plat_arm_calc_core_pos