| // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) |
| /* |
| * Copyright (c) 2025, STMicroelectronics - All Rights Reserved |
| */ |
| |
| #include "stm32mp157c-ed1.dts" |
| |
| / { |
| model = "STMicroelectronics STM32MP157C eval daughter (SP_MIN)"; |
| }; |
| |
| &rcc { |
| st,clksrc = < |
| CLK_MPU_PLL1P |
| CLK_AXI_PLL2P |
| CLK_MCU_PLL3P |
| CLK_RTC_LSE |
| CLK_MCO1_DISABLED |
| CLK_MCO2_DISABLED |
| CLK_CKPER_HSE |
| CLK_FMC_ACLK |
| CLK_QSPI_ACLK |
| CLK_ETH_PLL4P |
| CLK_SDMMC12_PLL4P |
| CLK_DSI_DSIPLL |
| CLK_STGEN_HSE |
| CLK_USBPHY_HSE |
| CLK_SPI2S1_PLL3Q |
| CLK_SPI2S23_PLL3Q |
| CLK_SPI45_HSI |
| CLK_SPI6_HSI |
| CLK_I2C46_HSI |
| CLK_SDMMC3_PLL4P |
| CLK_USBO_USBPHY |
| CLK_ADC_CKPER |
| CLK_CEC_LSE |
| CLK_I2C12_HSI |
| CLK_I2C35_HSI |
| CLK_UART1_HSI |
| CLK_UART24_HSI |
| CLK_UART35_HSI |
| CLK_UART6_HSI |
| CLK_UART78_HSI |
| CLK_SPDIF_PLL4P |
| CLK_FDCAN_PLL4R |
| CLK_SAI1_PLL3Q |
| CLK_SAI2_PLL3Q |
| CLK_SAI3_PLL3Q |
| CLK_SAI4_PLL3Q |
| CLK_RNG1_CSI |
| CLK_RNG2_LSI |
| CLK_LPTIM1_PCLK1 |
| CLK_LPTIM23_PCLK3 |
| CLK_LPTIM45_LSE |
| >; |
| |
| st,clkdiv = < |
| DIV(DIV_MPU, 1) |
| DIV(DIV_AXI, 0) |
| DIV(DIV_MCU, 0) |
| DIV(DIV_APB1, 1) |
| DIV(DIV_APB2, 1) |
| DIV(DIV_APB3, 1) |
| DIV(DIV_APB4, 1) |
| DIV(DIV_APB5, 2) |
| DIV(DIV_MCO1, 0) |
| DIV(DIV_MCO2, 0) |
| >; |
| }; |