diff --git a/plat/imx/imx8ulp/imx8ulp_psci.c b/plat/imx/imx8ulp/imx8ulp_psci.c
index 78078d5..62cba2c 100644
--- a/plat/imx/imx8ulp/imx8ulp_psci.c
+++ b/plat/imx/imx8ulp/imx8ulp_psci.c
@@ -91,12 +91,17 @@
 	return 0;
 }
 
+static volatile uint32_t cgc1_nicclk;
 int imx_pwr_domain_on(u_register_t mpidr)
 {
 	unsigned int cpu = MPIDR_AFFLVL0_VAL(mpidr);
 
 	imx_pwr_set_cpu_entry(cpu, secure_entrypoint);
 
+	/* slow down the APD NIC bus clock */
+	cgc1_nicclk = mmio_read_32(IMX_CGC1_BASE + 0x34);
+	mmio_clrbits_32(IMX_CGC1_BASE + 0x34, GENMASK_32(29, 28));
+
 	mmio_write_32(IMX_CMC1_BASE + 0x18, 0x3f);
 	mmio_write_32(IMX_CMC1_BASE + 0x50 + 0x4 * cpu, 0);
 
@@ -111,6 +116,9 @@
 	imx_pwr_set_cpu_entry(0, IMX_ROM_ENTRY);
 	plat_gic_pcpu_init();
 	plat_gic_cpuif_enable();
+
+	/* set APD NIC back to orignally setting */
+	mmio_write_32(IMX_CGC1_BASE + 0x34, cgc1_nicclk);
 }
 
 int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint)