blob: 2432b8187d5d8b9ceb0fd49ef3e3602adf2fdf0f [file] [log] [blame]
/*
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <platform_def.h>
#define LIT_CAPACITY 239
#define MID_CAPACITY 686
#define BIG_CAPACITY 1024
#define INT_MBOX_RX 300
#define MHU_TX_ADDR 46040000 /* hex */
#define MHU_RX_ADDR 46140000 /* hex */
#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ 3750000
#if TARGET_FLAVOUR_FVP
#define DPU_ADDR 4000000000
#define DPU_IRQ 579
#elif TARGET_FLAVOUR_FPGA
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
#endif
#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"
#endif /* TARGET_FLAVOUR_FVP */
#include "tc-base.dtsi"