refactor(st-clock): driver size optimization
Re-ordering structures to avoid gaps and minimize data.
Reduce type of gate_refcounts[], uint8_t is enough.
Re-ordering structures to avoid gaps and minimize data.
Use an unsigned char to define a clock ops type.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: I6b793dc34abdd6ef013609fc0f122da5d1824a34
diff --git a/drivers/st/clk/clk-stm32-core.c b/drivers/st/clk/clk-stm32-core.c
index 1e0240e..e8bd85f 100644
--- a/drivers/st/clk/clk-stm32-core.c
+++ b/drivers/st/clk/clk-stm32-core.c
@@ -224,6 +224,15 @@
return NULL;
}
+static const struct stm32_clk_ops *_clk_get_ops(struct stm32_clk_priv *priv, int id)
+{
+ const struct clk_stm32 *clk = _clk_get(priv, id);
+
+ assert(clk->ops != NO_OPS);
+
+ return priv->ops_array[clk->ops];
+}
+
#define clk_div_mask(_width) GENMASK(((_width) - 1U), 0U)
static unsigned int _get_table_div(const struct clk_div_table *table,
@@ -377,7 +386,7 @@
int _clk_stm32_get_parent(struct stm32_clk_priv *priv, int clk_id)
{
- const struct clk_stm32 *clk = _clk_get(priv, clk_id);
+ const struct stm32_clk_ops *ops = _clk_get_ops(priv, clk_id);
const struct parent_cfg *parent;
uint16_t mux_id;
int sel;
@@ -394,8 +403,8 @@
mux_id &= MUX_PARENT_MASK;
parent = &priv->parents[mux_id];
- if (clk->ops->get_parent != NULL) {
- sel = clk->ops->get_parent(priv, clk_id);
+ if (ops->get_parent != NULL) {
+ sel = ops->get_parent(priv, clk_id);
} else {
sel = clk_mux_get_parent(priv, mux_id);
}
@@ -464,7 +473,7 @@
unsigned long _clk_stm32_get_rate(struct stm32_clk_priv *priv, int id)
{
- const struct clk_stm32 *clk = _clk_get(priv, id);
+ const struct stm32_clk_ops *ops = _clk_get_ops(priv, id);
int parent;
if ((unsigned int)id >= priv->num) {
@@ -476,14 +485,14 @@
return 0UL;
}
- if (clk->ops->recalc_rate != NULL) {
+ if (ops->recalc_rate != NULL) {
unsigned long prate = 0UL;
if (parent != CLK_IS_ROOT) {
prate = _clk_stm32_get_rate(priv, parent);
}
- return clk->ops->recalc_rate(priv, id, prate);
+ return ops->recalc_rate(priv, id, prate);
}
if (parent == CLK_IS_ROOT) {
@@ -520,10 +529,10 @@
int clk_stm32_enable_call_ops(struct stm32_clk_priv *priv, uint16_t id)
{
- const struct clk_stm32 *clk = _clk_get(priv, id);
+ const struct stm32_clk_ops *ops = _clk_get_ops(priv, id);
- if (clk->ops->enable != NULL) {
- clk->ops->enable(priv, id);
+ if (ops->enable != NULL) {
+ ops->enable(priv, id);
}
return 0;
@@ -550,7 +559,7 @@
priv->gate_refcounts[id]++;
- if (priv->gate_refcounts[id] == UINT_MAX) {
+ if (priv->gate_refcounts[id] == UINT8_MAX) {
ERROR("%s: %d max enable count !", __func__, id);
panic();
}
@@ -571,10 +580,10 @@
void clk_stm32_disable_call_ops(struct stm32_clk_priv *priv, uint16_t id)
{
- const struct clk_stm32 *clk = _clk_get(priv, id);
+ const struct stm32_clk_ops *ops = _clk_get_ops(priv, id);
- if (clk->ops->disable != NULL) {
- clk->ops->disable(priv, id);
+ if (ops->disable != NULL) {
+ ops->disable(priv, id);
}
}
@@ -619,10 +628,10 @@
bool _clk_stm32_is_enabled(struct stm32_clk_priv *priv, int id)
{
- const struct clk_stm32 *clk = _clk_get(priv, id);
+ const struct stm32_clk_ops *ops = _clk_get_ops(priv, id);
- if (clk->ops->is_enabled != NULL) {
- return clk->ops->is_enabled(priv, id);
+ if (ops->is_enabled != NULL) {
+ return ops->is_enabled(priv, id);
}
return priv->gate_refcounts[id];
@@ -1081,12 +1090,10 @@
priv->base = base;
for (i = 0U; i < priv->num; i++) {
- const struct clk_stm32 *clk = _clk_get(priv, i);
+ const struct stm32_clk_ops *ops = _clk_get_ops(priv, i);
- assert(clk->ops != NULL);
-
- if (clk->ops->init != NULL) {
- clk->ops->init(priv, i);
+ if (ops->init != NULL) {
+ ops->init(priv, i);
}
}