diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 0f1f92a..758d62b 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -317,6 +317,11 @@
    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
    it is still open.
 
+- ``ERRATA_A78_2712571``: This applies erratum 2712571 workaround to Cortex-A78
+   CPU, this erratum affects system configurations that do not use an ARM
+   interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1
+   and r1p2 and it is still open.
+
 -  ``ERRATA_A78_2742426``: This applies erratum 2742426 workaround to Cortex-A78
    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and
    it is still open.
@@ -347,6 +352,11 @@
   Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
   erratum is still open.
 
+- ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to
+  Cortex-A78 AE CPU. This erratum affects system configurations that do not use
+  an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and
+  r0p2. This erratum is still open.
+
 For Cortex-A78C, the following errata build flags are defined :
 
 - ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to
@@ -373,6 +383,11 @@
   Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
   erratum is still open.
 
+- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to
+  Cortex-A78C CPU, this erratum affects system configurations that do not use
+  an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2
+  and is still open.
+
 - ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to
   Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
   This erratum is still open.
@@ -488,6 +503,11 @@
    CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU.
    It is still open.
 
+- ``ERRATA_V1_2701953``: This applies erratum 2701953 workaround to Neoverse-V1
+   CPU, this erratum affects system configurations that do not use an ARM
+   interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1.
+   It has been fixed in r1p2.
+
 -  ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1
    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the
    CPU. It is still open.
@@ -500,6 +520,13 @@
    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the
    CPU. It is still open.
 
+For Neoverse V2, the following errata build flags are defined :
+
+-  ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2
+   CPU, this affects system configurations that do not use and ARM interconnect
+   IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed
+   in r0p2.
+
 For Cortex-A710, the following errata build flags are defined :
 
 -  ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
@@ -558,6 +585,11 @@
    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
    of the CPU and is fixed in r2p1.
 
+-  ``ERRATA_A710_2701952``: This applies erratum 2701952 workaround to Cortex-A710
+   CPU, and applies to system configurations that do not use and ARM
+   interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and
+   is still open.
+
 -  ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to
    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and
    r2p1 of the CPU and is still open.
@@ -610,6 +642,11 @@
    CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
    in r0p3.
 
+- ``ERRATA_N2_2728475``: This applies erratum 2728475 workaround to Neoverse-N2
+   CPU, this erratum affects system configurations that do not use and ARM
+   interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
+   It is fixed in r0p3.
+
 For Cortex-X2, the following errata build flags are defined :
 
 -  ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2
@@ -647,6 +684,11 @@
    CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU
    and is fixed in r2p1.
 
+- ``ERRATA_X2_2701952``: This applies erratum 2701952 workaround to Cortex-X2
+   CPU and affects system configurations that do not use an ARM interconnect IP.
+   This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is
+   still open.
+
 -  ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2
    CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
    CPU and is still open.
@@ -709,6 +751,13 @@
    Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2,
    r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3.
 
+For Cortex-A715, the following errata build flags are defined :
+
+-  ``ERRATA_A715_2701951``: This applies erratum 2701951 workaround to Cortex-A715
+   CPU and affects system configurations that do not use an ARM interconnect
+   IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed
+   in r1p2.
+
 DSU Errata Workarounds
 ----------------------