tree ae97bc6b20af02ae5839e8550a54df7fb45d99ea
parent 600a8f4157a0d8aed04d1423024c84cf3e19c1ca
parent 65739db28bf0c0d5d4daa8735a2935681f835634
author Madhukar Pappireddy <madhukar.pappireddy@arm.com> 1721310872 +0200
committer TrustedFirmware Code Review <review@review.trustedfirmware.org> 1721310872 +0200

Merge changes from topic "clk_fixed_divider" into integration

* changes:
  feat(nxp-clk): set rate for clock fixed divider
  feat(nxp-clk): add A53 clock objects
  feat(nxp-clk): set rate for PLL divider objects
  feat(nxp-clk): set rate for PLL objects