Merge changes from topic "feat_state_part4" into integration
* changes:
refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED
refactor(cpufeat): align FEAT_SEL2 to new feature handling
refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_TWED for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_PAN for FEAT_STATE_CHECKED
refactor(cpufeat): align FEAT_SB to new feature handling
refactor(cpufeat): use alternative encoding for "SB" barrier
refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED
fix(cpufeat): make stub enable functions "static inline"
fix(mpam): feat_detect: support major/minor
diff --git a/Makefile b/Makefile
index 530ce53..ca97fc2 100644
--- a/Makefile
+++ b/Makefile
@@ -1097,6 +1097,7 @@
ENABLE_AMU_FCONF \
AMU_RESTRICT_COUNTERS \
ENABLE_ASSERTIONS \
+ ENABLE_FEAT_SB \
ENABLE_PIE \
ENABLE_PMF \
ENABLE_PSCI_STAT \
@@ -1150,7 +1151,6 @@
COT_DESC_IN_DTB \
USE_SP804_TIMER \
PSA_FWU_SUPPORT \
- ENABLE_SYS_REG_TRACE_FOR_NS \
ENABLE_MPMM \
ENABLE_MPMM_FCONF \
SIMICS_BUILD \
@@ -1182,13 +1182,13 @@
ENABLE_FEAT_PAN \
ENABLE_FEAT_RNG \
ENABLE_FEAT_RNG_TRAP \
- ENABLE_FEAT_SB \
ENABLE_FEAT_SEL2 \
ENABLE_FEAT_TCR2 \
ENABLE_FEAT_VHE \
ENABLE_MPAM_FOR_LOWER_ELS \
ENABLE_RME \
ENABLE_SPE_FOR_NS \
+ ENABLE_SYS_REG_TRACE_FOR_NS \
ENABLE_TRF_FOR_NS \
FW_ENC_STATUS \
NR_OF_FW_BANKS \
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index 91406cf..006843e 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -120,7 +120,7 @@
BL31_SOURCES += lib/extensions/brbe/brbe.c
endif
-ifeq (${ENABLE_SYS_REG_TRACE_FOR_NS},1)
+ifneq (${ENABLE_SYS_REG_TRACE_FOR_NS},0)
BL31_SOURCES += lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c
endif
diff --git a/bl32/sp_min/sp_min.mk b/bl32/sp_min/sp_min.mk
index 2a6612a..e85e273 100644
--- a/bl32/sp_min/sp_min.mk
+++ b/bl32/sp_min/sp_min.mk
@@ -46,7 +46,7 @@
services/std_svc/trng/trng_entropy_pool.c
endif
-ifeq (${ENABLE_SYS_REG_TRACE_FOR_NS},1)
+ifneq (${ENABLE_SYS_REG_TRACE_FOR_NS},0)
BL32_SOURCES += lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c
endif
diff --git a/common/feat_detect.c b/common/feat_detect.c
index abb6d71..9218c07 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -60,36 +60,6 @@
}
}
-/******************************************
- * Feature : FEAT_SB (Speculation Barrier)
- *****************************************/
-static void read_feat_sb(void)
-{
-#if (ENABLE_FEAT_SB == FEAT_STATE_ALWAYS)
- feat_detect_panic(is_armv8_0_feat_sb_present(), "SB");
-#endif
-}
-
-/******************************************************
- * Feature : FEAT_CSV2_2 (Cache Speculation Variant 2)
- *****************************************************/
-static void read_feat_csv2_2(void)
-{
-#if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_ALWAYS)
- feat_detect_panic(is_armv8_0_feat_csv2_2_present(), "CSV2_2");
-#endif
-}
-
-/***********************************************
- * Feature : FEAT_PAN (Privileged Access Never)
- **********************************************/
-static void read_feat_pan(void)
-{
-#if (ENABLE_FEAT_PAN == FEAT_STATE_ALWAYS)
- feat_detect_panic(is_armv8_1_pan_present(), "PAN");
-#endif
-}
-
/*******************************************************************************
* Feature : FEAT_RAS (Reliability, Availability, and Serviceability Extension)
******************************************************************************/
@@ -120,28 +90,6 @@
#endif
}
-/**************************************************************
- * Feature : FEAT_NV2 (Enhanced Nested Virtualization Support)
- *************************************************************/
-static void read_feat_nv2(void)
-{
-#if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_ALWAYS)
- unsigned int nv = get_armv8_4_feat_nv_support();
-
- feat_detect_panic((nv == ID_AA64MMFR2_EL1_NV2_SUPPORTED), "NV2");
-#endif
-}
-
-/***********************************
- * Feature : FEAT_SEL2 (Secure EL2)
- **********************************/
-static void read_feat_sel2(void)
-{
-#if (ENABLE_FEAT_SEL2 == FEAT_STATE_ALWAYS)
- feat_detect_panic(is_armv8_4_sel2_present(), "SEL2");
-#endif
-}
-
/************************************************
* Feature : FEAT_MTE (Memory Tagging Extension)
***********************************************/
@@ -154,16 +102,6 @@
#endif
}
-/***********************************************
- * Feature : FEAT_RNG (Random Number Generator)
- **********************************************/
-static void read_feat_rng(void)
-{
-#if (ENABLE_FEAT_RNG == FEAT_STATE_ALWAYS)
- feat_detect_panic(is_armv8_5_rng_present(), "RNG");
-#endif
-}
-
/****************************************************
* Feature : FEAT_BTI (Branch Target Identification)
***************************************************/
@@ -184,29 +122,6 @@
#endif
}
-/*******************************************************
- * Feature : FEAT_ECV (Enhanced Counter Virtualization)
- ******************************************************/
-static void read_feat_ecv(void)
-{
-#if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS)
- unsigned int ecv = get_armv8_6_ecv_support();
-
- feat_detect_panic(((ecv == ID_AA64MMFR0_EL1_ECV_SUPPORTED) ||
- (ecv == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH)), "ECV");
-#endif
-}
-
-/***********************************************************
- * Feature : FEAT_TWED (Delayed Trapping of WFE Instruction)
- **********************************************************/
-static void read_feat_twed(void)
-{
-#if (ENABLE_FEAT_TWED == FEAT_STATE_ALWAYS)
- feat_detect_panic(is_armv8_6_twed_present(), "TWED");
-#endif
-}
-
/**************************************************
* Feature : FEAT_RME (Realm Management Extension)
*************************************************/
@@ -256,11 +171,12 @@
tainted = false;
/* v8.0 features */
- read_feat_sb();
- read_feat_csv2_2();
+ check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(), "SB", 1, 1);
+ check_feature(ENABLE_FEAT_CSV2_2, read_feat_csv2_id_field(),
+ "CSV2_2", 2, 3);
/* v8.1 features */
- read_feat_pan();
+ check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(), "PAN", 1, 3);
check_feature(ENABLE_FEAT_VHE, read_feat_vhe_id_field(), "VHE", 1, 1);
/* v8.2 features */
@@ -274,23 +190,26 @@
check_feature(ENABLE_FEAT_AMUv1, read_feat_amu_id_field(),
"AMUv1", 1, 2);
check_feature(ENABLE_MPAM_FOR_LOWER_ELS, read_feat_mpam_version(),
- "MPAM", 1, 1);
- read_feat_nv2();
- read_feat_sel2();
+ "MPAM", 1, 17);
+ check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(),
+ "NV2", 2, 2);
+ check_feature(ENABLE_FEAT_SEL2, read_feat_sel2_id_field(),
+ "SEL2", 1, 1);
check_feature(ENABLE_TRF_FOR_NS, read_feat_trf_id_field(),
"TRF", 1, 1);
/* v8.5 features */
read_feat_mte();
- read_feat_rng();
+ check_feature(ENABLE_FEAT_RNG, read_feat_rng_id_field(), "RNG", 1, 1);
read_feat_bti();
read_feat_rng_trap();
/* v8.6 features */
read_feat_amuv1p1();
check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(), "FGT", 1, 1);
- read_feat_ecv();
- read_feat_twed();
+ check_feature(ENABLE_FEAT_ECV, read_feat_ecv_id_field(), "ECV", 1, 2);
+ check_feature(ENABLE_FEAT_TWED, read_feat_twed_id_field(),
+ "TWED", 1, 1);
/* v8.7 features */
check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), "HCX", 1, 1);
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 9415871..0540b6d 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -327,12 +327,11 @@
Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from
Armv8.5 onwards.
-- ``ENABLE_FEAT_SB``: Numeric value to enable the ``FEAT_SB`` (Speculation
- Barrier) extension allowing access to ``sb`` instruction. ``FEAT_SB`` is an
- optional feature and defaults to ``0`` for pre-Armv8.5 CPUs but are mandatory
- for Armv8.5 or later CPUs. This flag can take values 0 to 2, to align with
- ``FEATURE_DETECTION`` mechanism. It is enabled from v8.5 and upwards and if
- needed could be overidden from platforms explicitly. Default value is ``0``.
+- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB``
+ (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and
+ defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or
+ later CPUs. It is enabled from v8.5 and upwards and if needed can be
+ overidden from platforms explicitly.
- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2)
extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4.
@@ -1079,10 +1078,11 @@
``FEATURE_DETECTION`` mechanism. The default is 0 and it is automatically
disabled when the target architecture is AArch32.
-- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Boolean option to enable trace system
+- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system
registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented
but unused). This feature is available if trace unit such as ETMv4.x, and
- ETE(extending ETM feature) is implemented. This flag is disabled by default.
+ ETE(extending ETM feature) is implemented. This flag can take the values
+ 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0.
- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers
access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused),
diff --git a/include/arch/aarch32/arch_features.h b/include/arch/aarch32/arch_features.h
index 12df6da..252b407 100644
--- a/include/arch/aarch32/arch_features.h
+++ b/include/arch/aarch32/arch_features.h
@@ -43,6 +43,24 @@
return read_feat_trf_id_field() != 0U;
}
+static inline unsigned int read_feat_coptrc_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_dfr0(), ID_DFR0_COPTRC);
+}
+
+static inline bool is_feat_sys_reg_trace_supported(void)
+{
+ if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_coptrc_id_field() != 0U;
+}
+
static inline bool is_feat_spe_supported(void)
{
/* FEAT_SPE is AArch64 only */
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 85546ec..8663ab8 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -119,6 +119,7 @@
#define MPAMVPM7_EL2 S3_4_C10_C6_7
#define MPAMVPMV_EL2 S3_4_C10_C4_1
#define TRFCR_EL2 S3_4_C1_C2_1
+#define VNCR_EL2 S3_4_C2_C2_0
#define PMSCR_EL2 S3_4_C9_C9_0
#define TFSR_EL2 S3_4_C5_C6_0
#define CONTEXTIDR_EL2 S3_4_C13_C0_1
@@ -1335,4 +1336,7 @@
#define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0)
#define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1)
+/* alternative system register encoding for the "sb" speculation barrier */
+#define SYSREG_SB S0_3_C3_C0_7
+
#endif /* ARCH_H */
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index f1a13d2..d3c6263 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -21,10 +21,22 @@
return true;
}
-static inline bool is_armv8_1_pan_present(void)
+static inline unsigned int read_feat_pan_id_field(void)
{
- return ((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_PAN_SHIFT) &
- ID_AA64MMFR1_EL1_PAN_MASK) != 0U;
+ return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN);
+}
+
+static inline bool is_feat_pan_supported(void)
+{
+ if (ENABLE_FEAT_PAN == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_FEAT_PAN == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_pan_id_field() != 0U;
}
static inline unsigned int read_feat_vhe_id_field(void)
@@ -101,16 +113,40 @@
ID_AA64PFR1_EL1_MTE_MASK);
}
-static inline bool is_armv8_4_sel2_present(void)
+static inline unsigned int read_feat_sel2_id_field(void)
{
- return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SEL2_SHIFT) &
- ID_AA64PFR0_SEL2_MASK) == 1ULL;
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2);
}
-static inline bool is_armv8_6_twed_present(void)
+static inline bool is_feat_sel2_supported(void)
{
- return (((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_TWED_SHIFT) &
- ID_AA64MMFR1_EL1_TWED_MASK) == ID_AA64MMFR1_EL1_TWED_SUPPORTED);
+ if (ENABLE_FEAT_SEL2 == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_FEAT_SEL2 == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_sel2_id_field() != 0U;
+}
+
+static inline unsigned int read_feat_twed_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_TWED);
+}
+
+static inline bool is_feat_twed_supported(void)
+{
+ if (ENABLE_FEAT_TWED == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_FEAT_TWED == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_twed_id_field() != 0U;
}
static unsigned int read_feat_fgt_id_field(void)
@@ -131,16 +167,53 @@
return read_feat_fgt_id_field() != 0U;
}
-static inline unsigned long int get_armv8_6_ecv_support(void)
+static unsigned int read_feat_ecv_id_field(void)
{
- return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_ECV_SHIFT) &
- ID_AA64MMFR0_EL1_ECV_MASK);
+ return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV);
}
-static inline bool is_armv8_5_rng_present(void)
+static inline bool is_feat_ecv_supported(void)
{
- return ((read_id_aa64isar0_el1() >> ID_AA64ISAR0_RNDR_SHIFT) &
- ID_AA64ISAR0_RNDR_MASK);
+ if (ENABLE_FEAT_ECV == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_ecv_id_field() != 0U;
+}
+
+static inline bool is_feat_ecv_v2_supported(void)
+{
+ if (ENABLE_FEAT_ECV == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_ecv_id_field() >= ID_AA64MMFR0_EL1_ECV_SELF_SYNCH;
+}
+
+static unsigned int read_feat_rng_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_RNDR);
+}
+
+static inline bool is_feat_rng_supported(void)
+{
+ if (ENABLE_FEAT_RNG == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_FEAT_RNG == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_rng_id_field() != 0U;
}
static unsigned int read_feat_tcrx_id_field(void)
@@ -256,19 +329,30 @@
/*********************************************************************************
* Function to identify the presence of FEAT_SB (Speculation Barrier Instruction)
********************************************************************************/
-static inline bool is_armv8_0_feat_sb_present(void)
+static inline unsigned int read_feat_sb_id_field(void)
{
- return (((read_id_aa64isar1_el1() >> ID_AA64ISAR1_SB_SHIFT) &
- ID_AA64ISAR1_SB_MASK) == ID_AA64ISAR1_SB_SUPPORTED);
+ return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB);
}
/*********************************************************************************
* Function to identify the presence of FEAT_CSV2_2 (Cache Speculation Variant 2)
********************************************************************************/
-static inline bool is_armv8_0_feat_csv2_2_present(void)
+static inline unsigned int read_feat_csv2_id_field(void)
{
- return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_CSV2_SHIFT) &
- ID_AA64PFR0_CSV2_MASK) == ID_AA64PFR0_CSV2_2_SUPPORTED);
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2);
+}
+
+static inline bool is_feat_csv2_2_supported(void)
+{
+ if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_csv2_id_field() >= ID_AA64PFR0_CSV2_2_SUPPORTED;
}
/**********************************************************************************
@@ -320,6 +404,24 @@
ID_AA64PFR0_DIT_MASK) == ID_AA64PFR0_DIT_SUPPORTED);
}
+static inline unsigned int read_feat_tracever_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEVER);
+}
+
+static inline bool is_feat_sys_reg_trace_supported(void)
+{
+ if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_tracever_id_field() != 0U;
+}
+
/*************************************************************************
* Function to identify the presence of FEAT_TRF (TraceLift)
************************************************************************/
@@ -345,10 +447,22 @@
* Function to identify the presence of FEAT_NV2 (Enhanced Nested Virtualization
* Support)
*******************************************************************************/
-static inline unsigned int get_armv8_4_feat_nv_support(void)
+static inline unsigned int read_feat_nv_id_field(void)
{
- return (((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_NV_SHIFT) &
- ID_AA64MMFR2_EL1_NV_MASK));
+ return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV);
+}
+
+static inline bool is_feat_nv2_supported(void)
+{
+ if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_nv_id_field() >= ID_AA64MMFR2_EL1_NV2_SUPPORTED;
}
/*******************************************************************************
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 6d115c7..04b64be 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -540,6 +540,8 @@
DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1)
DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el2, SCXTNUM_EL2)
+
/* Armv8.1 VHE Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(contextidr_el2, CONTEXTIDR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(ttbr1_el2, TTBR1_EL2)
@@ -571,6 +573,7 @@
/* Armv8.4 FEAT_TRF Register */
DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(vncr_el2, VNCR_EL2)
/* Armv8.5 MTE Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1)
@@ -590,6 +593,9 @@
DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr_el2, HFGRTR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr_el2, HFGWTR_EL2)
+/* ARMv8.6 FEAT_ECV Register */
+DEFINE_RENAME_SYSREG_RW_FUNCS(cntpoff_el2, CNTPOFF_EL2)
+
/* FEAT_HCX Register */
DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2)
diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S
index 66c39e5..b4dab085 100644
--- a/include/arch/aarch64/asm_macros.S
+++ b/include/arch/aarch64/asm_macros.S
@@ -215,12 +215,24 @@
.endm
/*
+ * The "sb" instruction was introduced later into the architecture,
+ * so not all toolchains understand it. Some deny its usage unless
+ * a supported processor is specified on the build command line.
+ * Use sb's system register encoding to work around this, we already
+ * guard the sb execution with a feature flag.
+ */
+
+ .macro sb_barrier_insn
+ msr SYSREG_SB, xzr
+ .endm
+
+ /*
* Macro for using speculation barrier instruction introduced by
* FEAT_SB, if it's enabled.
*/
.macro speculation_barrier
#if ENABLE_FEAT_SB
- sb
+ sb_barrier_insn
#else
dsb sy
isb
@@ -234,7 +246,7 @@
.macro exception_return
eret
#if ENABLE_FEAT_SB
- sb
+ sb_barrier_insn
#else
dsb nsh
isb
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index 9b50f33..e5e7e74 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -517,22 +517,10 @@
void el2_sysregs_context_save_mte(el2_sysregs_t *regs);
void el2_sysregs_context_restore_mte(el2_sysregs_t *regs);
#endif /* CTX_INCLUDE_MTE_REGS */
-#if ENABLE_FEAT_ECV
-void el2_sysregs_context_save_ecv(el2_sysregs_t *regs);
-void el2_sysregs_context_restore_ecv(el2_sysregs_t *regs);
-#endif /* ENABLE_FEAT_ECV */
#if RAS_EXTENSION
void el2_sysregs_context_save_ras(el2_sysregs_t *regs);
void el2_sysregs_context_restore_ras(el2_sysregs_t *regs);
#endif /* RAS_EXTENSION */
-#if CTX_INCLUDE_NEVE_REGS
-void el2_sysregs_context_save_nv2(el2_sysregs_t *regs);
-void el2_sysregs_context_restore_nv2(el2_sysregs_t *regs);
-#endif /* CTX_INCLUDE_NEVE_REGS */
-#if ENABLE_FEAT_CSV2_2
-void el2_sysregs_context_save_csv2(el2_sysregs_t *regs);
-void el2_sysregs_context_restore_csv2(el2_sysregs_t *regs);
-#endif /* ENABLE_FEAT_CSV2_2 */
#endif /* CTX_INCLUDE_EL2_REGS */
#if CTX_INCLUDE_FPREGS
diff --git a/include/lib/extensions/brbe.h b/include/lib/extensions/brbe.h
index aee208d..9ee2444 100644
--- a/include/lib/extensions/brbe.h
+++ b/include/lib/extensions/brbe.h
@@ -10,7 +10,7 @@
#if ENABLE_BRBE_FOR_NS
void brbe_enable(void);
#else
-void brbe_enable(void)
+static inline void brbe_enable(void)
{
}
#endif /* ENABLE_BRBE_FOR_NS */
diff --git a/include/lib/extensions/mpam.h b/include/lib/extensions/mpam.h
index 120a921..4327278 100644
--- a/include/lib/extensions/mpam.h
+++ b/include/lib/extensions/mpam.h
@@ -12,7 +12,7 @@
#if ENABLE_MPAM_FOR_LOWER_ELS
void mpam_enable(bool el2_unused);
#else
-void mpam_enable(bool el2_unused)
+static inline void mpam_enable(bool el2_unused)
{
}
#endif
diff --git a/include/lib/extensions/spe.h b/include/lib/extensions/spe.h
index d443f18..02fccae 100644
--- a/include/lib/extensions/spe.h
+++ b/include/lib/extensions/spe.h
@@ -13,10 +13,10 @@
void spe_enable(bool el2_unused);
void spe_disable(void);
#else
-void spe_enable(bool el2_unused)
+static inline void spe_enable(bool el2_unused)
{
}
-void spe_disable(void)
+static inline void spe_disable(void)
{
}
#endif
diff --git a/include/lib/extensions/sys_reg_trace.h b/include/lib/extensions/sys_reg_trace.h
index 74470fe..5915c55 100644
--- a/include/lib/extensions/sys_reg_trace.h
+++ b/include/lib/extensions/sys_reg_trace.h
@@ -9,10 +9,24 @@
#include <context.h>
+#if ENABLE_SYS_REG_TRACE_FOR_NS
#if __aarch64__
void sys_reg_trace_enable(cpu_context_t *context);
#else
void sys_reg_trace_enable(void);
#endif /* __aarch64__ */
+#else /* !ENABLE_SYS_REG_TRACE_FOR_NS */
+
+#if __aarch64__
+static inline void sys_reg_trace_enable(cpu_context_t *context)
+{
+}
+#else
+static inline void sys_reg_trace_enable(void)
+{
+}
+#endif /* __aarch64__ */
+#endif /* ENABLE_SYS_REG_TRACE_FOR_NS */
+
#endif /* SYS_REG_TRACE_H */
diff --git a/include/lib/extensions/trbe.h b/include/lib/extensions/trbe.h
index 0eff7c4..861a4ad 100644
--- a/include/lib/extensions/trbe.h
+++ b/include/lib/extensions/trbe.h
@@ -10,7 +10,7 @@
#if ENABLE_TRBE_FOR_NS
void trbe_enable(void);
#else
-void trbe_enable(void)
+static inline void trbe_enable(void)
{
}
#endif /* ENABLE_TRBE_FOR_NS */
diff --git a/include/lib/extensions/trf.h b/include/lib/extensions/trf.h
index a440abd..91a9615 100644
--- a/include/lib/extensions/trf.h
+++ b/include/lib/extensions/trf.h
@@ -10,7 +10,7 @@
#if ENABLE_TRF_FOR_NS
void trf_enable(void);
#else
-void trf_enable(void)
+static inline void trf_enable(void)
{
}
#endif /* ENABLE_TRF_FOR_NS */
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index e494a86..e7a0e58 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -140,9 +140,9 @@
amu_enable(el2_unused);
#endif
-#if ENABLE_SYS_REG_TRACE_FOR_NS
- sys_reg_trace_enable();
-#endif /* ENABLE_SYS_REG_TRACE_FOR_NS */
+ if (is_feat_sys_reg_trace_supported()) {
+ sys_reg_trace_enable();
+ }
if (is_feat_trf_supported()) {
trf_enable();
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index a5b64a5..013a505 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -17,22 +17,10 @@
.global el2_sysregs_context_save_mte
.global el2_sysregs_context_restore_mte
#endif /* CTX_INCLUDE_MTE_REGS */
-#if ENABLE_FEAT_ECV
- .global el2_sysregs_context_save_ecv
- .global el2_sysregs_context_restore_ecv
-#endif /* ENABLE_FEAT_ECV */
#if RAS_EXTENSION
.global el2_sysregs_context_save_ras
.global el2_sysregs_context_restore_ras
#endif /* RAS_EXTENSION */
-#if CTX_INCLUDE_NEVE_REGS
- .global el2_sysregs_context_save_nv2
- .global el2_sysregs_context_restore_nv2
-#endif /* CTX_INCLUDE_NEVE_REGS */
-#if ENABLE_FEAT_CSV2_2
- .global el2_sysregs_context_save_csv2
- .global el2_sysregs_context_restore_csv2
-#endif /* ENABLE_FEAT_CSV2_2 */
#endif /* CTX_INCLUDE_EL2_REGS */
.global el1_sysregs_context_save
@@ -222,20 +210,6 @@
endfunc el2_sysregs_context_restore_mte
#endif /* CTX_INCLUDE_MTE_REGS */
-#if ENABLE_FEAT_ECV
-func el2_sysregs_context_save_ecv
- mrs x11, CNTPOFF_EL2
- str x11, [x0, #CTX_CNTPOFF_EL2]
- ret
-endfunc el2_sysregs_context_save_ecv
-
-func el2_sysregs_context_restore_ecv
- ldr x11, [x0, #CTX_CNTPOFF_EL2]
- msr CNTPOFF_EL2, x11
- ret
-endfunc el2_sysregs_context_restore_ecv
-#endif /* ENABLE_FEAT_ECV */
-
#if RAS_EXTENSION
func el2_sysregs_context_save_ras
/*
@@ -260,46 +234,6 @@
endfunc el2_sysregs_context_restore_ras
#endif /* RAS_EXTENSION */
-#if CTX_INCLUDE_NEVE_REGS
-func el2_sysregs_context_save_nv2
- /*
- * VNCR_EL2 register is saved only when FEAT_NV2 is supported.
- */
- mrs x16, vncr_el2
- str x16, [x0, #CTX_VNCR_EL2]
- ret
-endfunc el2_sysregs_context_save_nv2
-
-func el2_sysregs_context_restore_nv2
- /*
- * VNCR_EL2 register is restored only when FEAT_NV2 is supported.
- */
- ldr x16, [x0, #CTX_VNCR_EL2]
- msr vncr_el2, x16
- ret
-endfunc el2_sysregs_context_restore_nv2
-#endif /* CTX_INCLUDE_NEVE_REGS */
-
-#if ENABLE_FEAT_CSV2_2
-func el2_sysregs_context_save_csv2
- /*
- * SCXTNUM_EL2 register is saved only when FEAT_CSV2_2 is supported.
- */
- mrs x13, scxtnum_el2
- str x13, [x0, #CTX_SCXTNUM_EL2]
- ret
-endfunc el2_sysregs_context_save_csv2
-
-func el2_sysregs_context_restore_csv2
- /*
- * SCXTNUM_EL2 register is restored only when FEAT_CSV2_2 is supported.
- */
- ldr x13, [x0, #CTX_SCXTNUM_EL2]
- msr scxtnum_el2, x13
- ret
-endfunc el2_sysregs_context_restore_csv2
-#endif /* ENABLE_FEAT_CSV2_2 */
-
#endif /* CTX_INCLUDE_EL2_REGS */
/* ------------------------------------------------------------------
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 20eb5f6..04b685f 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -134,7 +134,7 @@
#endif /* CTX_INCLUDE_MTE_REGS */
/* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */
- if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) {
+ if ((GET_EL(ep->spsr) == MODE_EL2) && is_feat_sel2_supported()) {
if (GET_RW(ep->spsr) != MODE_RW_64) {
ERROR("S-EL2 can not be used in AArch32\n.");
panic();
@@ -171,10 +171,10 @@
scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT;
-#if ENABLE_FEAT_CSV2_2
- /* Enable access to the SCXTNUM_ELx registers. */
- scr_el3 |= SCR_EnSCXT_BIT;
-#endif
+ if (is_feat_csv2_2_supported()) {
+ /* Enable access to the SCXTNUM_ELx registers. */
+ scr_el3 |= SCR_EnSCXT_BIT;
+ }
write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
}
@@ -227,10 +227,10 @@
scr_el3 |= SCR_TERR_BIT;
#endif
-#if ENABLE_FEAT_CSV2_2
- /* Enable access to the SCXTNUM_ELx registers. */
- scr_el3 |= SCR_EnSCXT_BIT;
-#endif
+ if (is_feat_csv2_2_supported()) {
+ /* Enable access to the SCXTNUM_ELx registers. */
+ scr_el3 |= SCR_EnSCXT_BIT;
+ }
#ifdef IMAGE_BL31
/*
@@ -380,22 +380,21 @@
scr_el3 |= SCR_FGTEN_BIT;
}
- if (get_armv8_6_ecv_support()
- == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) {
+ if (is_feat_ecv_supported()) {
scr_el3 |= SCR_ECVEN_BIT;
}
}
-#if ENABLE_FEAT_TWED
/* Enable WFE trap delay in SCR_EL3 if supported and configured */
- /* Set delay in SCR_EL3 */
- scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT);
- scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK)
- << SCR_TWEDEL_SHIFT);
+ if (is_feat_twed_supported()) {
+ /* Set delay in SCR_EL3 */
+ scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT);
+ scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK)
+ << SCR_TWEDEL_SHIFT);
- /* Enable WFE delay */
- scr_el3 |= SCR_TWEDEn_BIT;
-#endif /* ENABLE_FEAT_TWED */
+ /* Enable WFE delay */
+ scr_el3 |= SCR_TWEDEn_BIT;
+ }
/*
* Populate EL3 state so that we've the right context
@@ -510,9 +509,9 @@
brbe_enable();
}
-#if ENABLE_SYS_REG_TRACE_FOR_NS
- sys_reg_trace_enable(ctx);
-#endif /* ENABLE_SYS_REG_TRACE_FOR_NS */
+ if (is_feat_sys_reg_trace_supported()) {
+ sys_reg_trace_enable(ctx);
+ }
if (is_feat_trf_supported()) {
trf_enable();
@@ -957,9 +956,11 @@
el2_sysregs_context_save_fgt(el2_sysregs_ctx);
}
-#if ENABLE_FEAT_ECV
- el2_sysregs_context_save_ecv(el2_sysregs_ctx);
-#endif
+ if (is_feat_ecv_v2_supported()) {
+ write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2,
+ read_cntpoff_el2());
+ }
+
if (is_feat_vhe_supported()) {
write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2,
read_contextidr_el2());
@@ -969,15 +970,21 @@
#if RAS_EXTENSION
el2_sysregs_context_save_ras(el2_sysregs_ctx);
#endif
-#if CTX_INCLUDE_NEVE_REGS
- el2_sysregs_context_save_nv2(el2_sysregs_ctx);
-#endif
+
+ if (is_feat_nv2_supported()) {
+ write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2,
+ read_vncr_el2());
+ }
+
if (is_feat_trf_supported()) {
write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2());
}
-#if ENABLE_FEAT_CSV2_2
- el2_sysregs_context_save_csv2(el2_sysregs_ctx);
-#endif
+
+ if (is_feat_csv2_2_supported()) {
+ write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2,
+ read_scxtnum_el2());
+ }
+
if (is_feat_hcx_supported()) {
write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2());
}
@@ -1020,9 +1027,11 @@
el2_sysregs_context_restore_fgt(el2_sysregs_ctx);
}
-#if ENABLE_FEAT_ECV
- el2_sysregs_context_restore_ecv(el2_sysregs_ctx);
-#endif
+ if (is_feat_ecv_v2_supported()) {
+ write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx,
+ CTX_CNTPOFF_EL2));
+ }
+
if (is_feat_vhe_supported()) {
write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2));
write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2));
@@ -1030,15 +1039,19 @@
#if RAS_EXTENSION
el2_sysregs_context_restore_ras(el2_sysregs_ctx);
#endif
-#if CTX_INCLUDE_NEVE_REGS
- el2_sysregs_context_restore_nv2(el2_sysregs_ctx);
-#endif
+
+ if (is_feat_nv2_supported()) {
+ write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2));
+ }
if (is_feat_trf_supported()) {
write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2));
}
-#if ENABLE_FEAT_CSV2_2
- el2_sysregs_context_restore_csv2(el2_sysregs_ctx);
-#endif
+
+ if (is_feat_csv2_2_supported()) {
+ write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx,
+ CTX_SCXTNUM_EL2));
+ }
+
if (is_feat_hcx_supported()) {
write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2));
}
diff --git a/lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c b/lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c
index 89b8029..b3f44b7 100644
--- a/lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c
+++ b/lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c
@@ -10,27 +10,16 @@
#include <arch_helpers.h>
#include <lib/extensions/sys_reg_trace.h>
-static bool sys_reg_trace_supported(void)
-{
- uint32_t features;
-
- features = read_id_dfr0() >> ID_DFR0_COPTRC_SHIFT;
- return ((features & ID_DFR0_COPTRC_MASK) ==
- ID_DFR0_COPTRC_SUPPORTED);
-}
-
void sys_reg_trace_enable(void)
{
uint32_t val;
- if (sys_reg_trace_supported()) {
- /*
- * NSACR.NSTRCDIS = b0
- * enable NS system register access to implemented trace
- * registers.
- */
- val = read_nsacr();
- val &= ~NSTRCDIS_BIT;
- write_nsacr(val);
- }
+ /*
+ * NSACR.NSTRCDIS = b0
+ * enable NS system register access to implemented trace
+ * registers.
+ */
+ val = read_nsacr();
+ val &= ~NSTRCDIS_BIT;
+ write_nsacr(val);
}
diff --git a/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c b/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c
index 960d698..e61cb90 100644
--- a/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c
+++ b/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c
@@ -10,28 +10,17 @@
#include <arch_helpers.h>
#include <lib/extensions/sys_reg_trace.h>
-static bool sys_reg_trace_supported(void)
-{
- uint64_t features;
-
- features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEVER_SHIFT;
- return ((features & ID_AA64DFR0_TRACEVER_MASK) ==
- ID_AA64DFR0_TRACEVER_SUPPORTED);
-}
-
void sys_reg_trace_enable(cpu_context_t *ctx)
{
uint64_t val;
- if (sys_reg_trace_supported()) {
- /* Retrieve CPTR_EL3 value from the given context 'ctx',
- * and update CPTR_EL3.TTA bit to 0.
- * This function is called while switching context to NS to
- * allow system trace register access to NS-EL2 and NS-EL1
- * when NS-EL2 is implemented but not used.
- */
- val = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3);
- val &= ~TTA_BIT;
- write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, val);
- }
+ /* Retrieve CPTR_EL3 value from the given context 'ctx',
+ * and update CPTR_EL3.TTA bit to 0.
+ * This function is called while switching context to NS to
+ * allow system trace register access to NS-EL2 and NS-EL1
+ * when NS-EL2 is implemented but not used.
+ */
+ val = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3);
+ val &= ~TTA_BIT;
+ write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, val);
}
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 6d25def..1d96a2a 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -459,7 +459,7 @@
endif
# enable trace system registers access to NS by default
-ENABLE_SYS_REG_TRACE_FOR_NS := 1
+ENABLE_SYS_REG_TRACE_FOR_NS := 2
# enable trace filter control registers access to NS by default
ENABLE_TRF_FOR_NS := 2
@@ -469,6 +469,12 @@
ENABLE_FEAT_HCX := 2
ENABLE_FEAT_TCR2 := 2
+CTX_INCLUDE_NEVE_REGS := 2
+ENABLE_FEAT_CSV2_2 := 2
+ENABLE_FEAT_ECV := 2
+ENABLE_FEAT_PAN := 2
+ENABLE_FEAT_SEL2 := 2
+ENABLE_FEAT_TWED := 2
ENABLE_FEAT_VHE := 2
ENABLE_MPAM_FOR_LOWER_ELS := 2
diff --git a/plat/qemu/common/qemu_stack_protector.c b/plat/qemu/common/qemu_stack_protector.c
index 15ce3d6..d0b4a0f 100644
--- a/plat/qemu/common/qemu_stack_protector.c
+++ b/plat/qemu/common/qemu_stack_protector.c
@@ -14,12 +14,10 @@
u_register_t plat_get_stack_protector_canary(void)
{
-#if ENABLE_FEAT_RNG
/* Use the RNDR instruction if the CPU supports it */
- if (is_armv8_5_rng_present()) {
+ if (is_feat_rng_supported()) {
return read_rndr();
}
-#endif
/*
* Ideally, a random number should be returned above. If a random
diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index 13f61ca..c076aba 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk
@@ -301,6 +301,9 @@
ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
+# QEMU will use the RNDR instruction for the stack protector canary.
+ENABLE_FEAT_RNG := 2
+
# Later QEMU versions support SME and SVE.
ifneq (${ARCH},aarch32)
ENABLE_SVE_FOR_NS := 1
diff --git a/services/std_svc/sdei/sdei_intr_mgmt.c b/services/std_svc/sdei/sdei_intr_mgmt.c
index 9862e4f..3bdf4a2 100644
--- a/services/std_svc/sdei/sdei_intr_mgmt.c
+++ b/services/std_svc/sdei/sdei_intr_mgmt.c
@@ -274,7 +274,7 @@
(hcr_el2 & HCR_TGE_BIT) &&
(hcr_el2 & HCR_E2H_BIT);
- if (is_armv8_1_pan_present() &&
+ if (is_feat_pan_supported() &&
((client_el == MODE_EL1) ||
(client_el == MODE_EL2 && el_is_in_host)) &&
((client_el_sctlr & SCTLR_SPAN_BIT) == 0U)) {
diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
index e85109d..0e1899e 100644
--- a/services/std_svc/spmd/spmd_main.c
+++ b/services/std_svc/spmd/spmd_main.c
@@ -399,7 +399,7 @@
* Check if S-EL2 is supported on this system if S-EL2
* is required for SPM
*/
- if (!is_armv8_4_sel2_present()) {
+ if (!is_feat_sel2_supported()) {
WARN("SPM Core run time S-EL2 is not supported.\n");
return -EINVAL;
}