Merge changes I1fae91a5,I54793492,I703f0e6e into integration
* changes:
fix(cpus): workaround for Cortex-A710 erratum 1917258
fix(cpus): workaround for Cortex-A710 erratum 1916945
fix(cpus): workaround for Cortex-A710 erratum 1901946
diff --git a/.commitlintrc.js b/.commitlintrc.js
index 53e3a63..51493ea 100644
--- a/.commitlintrc.js
+++ b/.commitlintrc.js
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -67,6 +67,6 @@
"type-enum": [2, "always", types], /* Error */
"scope-case": [2, "always", "lower-case"], /* Error */
- "scope-enum": [1, "always", scopes] /* Warning */
+ "scope-enum": [2, "always", scopes] /* Error */
},
};
diff --git a/Makefile b/Makefile
index 530e6e0..cbf0a8a 100644
--- a/Makefile
+++ b/Makefile
@@ -546,31 +546,6 @@
BL_COMMON_SOURCES += lib/extensions/pauth/pauth.c
endif
-####################################################
-# Enable required options for Memory Stack Tagging.
-####################################################
-
-# Currently, these options are enabled only for clang and armclang compiler.
-ifeq (${SUPPORT_STACK_MEMTAG},yes)
- ifdef mem_tag_arch_support
- # Check for armclang and clang compilers
- ifneq ($(filter %-clang,$($(ARCH)-cc-id)),)
- # Add "memtag" architecture feature modifier if not specified
- ifeq ( ,$(findstring memtag,$(arch-features)))
- arch-features := $(arch-features)+memtag
- endif # memtag
- ifeq ($($(ARCH)-cc-id),arm-clang)
- TF_CFLAGS += -mmemtag-stack
- else ifeq ($($(ARCH)-cc-id),llvm-clang)
- TF_CFLAGS += -fsanitize=memtag
- endif # armclang
- endif
- else
- $(error "Error: stack memory tagging is not supported for \
- architecture ${ARCH},armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a")
- endif #(mem_tag_arch_support)
-endif #(SUPPORT_STACK_MEMTAG)
-
################################################################################
# RME dependent flags configuration, Enable optional features for RME.
################################################################################
@@ -1027,6 +1002,9 @@
ifneq (${ENABLE_FEAT_MOPS},0)
$(error "ENABLE_FEAT_MOPS cannot be used with ARCH=aarch32")
endif
+ ifneq (${ENABLE_FEAT_GCIE},0)
+ $(error "ENABLE_FEAT_GCIE cannot be used with ARCH=aarch32")
+ endif
endif #(ARCH=aarch32)
ifneq (${ENABLE_FEAT_FPMR},0)
@@ -1263,6 +1241,7 @@
ENABLE_RUNTIME_INSTRUMENTATION \
ENABLE_SME_FOR_SWD \
ENABLE_SVE_FOR_SWD \
+ ENABLE_FEAT_GCIE \
ENABLE_FEAT_RAS \
FFH_SUPPORT \
ERROR_DEPRECATED \
@@ -1550,6 +1529,7 @@
ENABLE_FEAT_D128 \
ENABLE_FEAT_GCS \
ENABLE_FEAT_MOPS \
+ ENABLE_FEAT_GCIE \
ENABLE_FEAT_MTE2 \
FEATURE_DETECTION \
TWED_DELAY \
@@ -1861,7 +1841,8 @@
doc:
$(s)echo " BUILD DOCUMENTATION"
- $(q)${MAKE} --no-print-directory -C ${DOCS_PATH} html
+ $(if $(host-poetry),$(q)poetry -q install --with docs --no-root)
+ $(q)$(if $(host-poetry),poetry run )${MAKE} --no-print-directory -C ${DOCS_PATH} html
enctool: ${ENCTOOL}
diff --git a/changelog.yaml b/changelog.yaml
index e5d43d9..f2f821e 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -621,6 +621,12 @@
scope: stm32mp2
subsections:
+ - title: STM32MP21
+ scope: stm32mp21
+
+ - title: STM32MP23
+ scope: stm32mp23
+
- title: STM32MP25
scope: stm32mp25
@@ -990,6 +996,9 @@
scope: gic
subsections:
+ - title: GICv5
+ scope: gicv5
+
- title: GICv3
scope: gicv3
@@ -1175,6 +1184,9 @@
- title: Clock
scope: nxp-clk
+ - title: uSDHC
+ scope: nxp-mmc
+
- title: Renesas
scope: renesas-drivers
@@ -1352,6 +1364,12 @@
scope: stm32mp2-fdts
subsections:
+ - title: STM32MP21
+ scope: stm32mp21-fdts
+
+ - title: STM32MP23
+ scope: stm32mp23-fdts
+
- title: STM32MP25
scope: stm32mp25-fdts
diff --git a/common/feat_detect.c b/common/feat_detect.c
index 2d80b42..fa817d9 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -279,6 +279,11 @@
return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_D128_SHIFT,
ID_AA64MMFR3_EL1_D128_MASK);
}
+static unsigned int read_feat_gcie_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_GCIE_SHIFT,
+ ID_AA64PFR2_EL1_GCIE_MASK);
+}
static unsigned int read_feat_fpmr_id_field(void)
{
@@ -425,6 +430,8 @@
/* v9.3 features */
check_feature(ENABLE_FEAT_D128, read_feat_d128_id_field(),
"D128", 1, 1);
+ check_feature(ENABLE_FEAT_GCIE, read_feat_gcie_id_field(),
+ "GCIE", 1, 1);
/* v9.4 features */
check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), "GCS", 1, 1);
diff --git a/docs/about/features.rst b/docs/about/features.rst
index f15144a..78f5ff3 100644
--- a/docs/about/features.rst
+++ b/docs/about/features.rst
@@ -128,6 +128,7 @@
in a platform:
- RSE comms driver ``drivers/arm/rse``
+- GICv5 driver ``drivers/arm/gicv5`` via ``USE_GIC_DRIVER=5``
Still to come
-------------
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 8b0ab4b..e11f8c0 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -1061,6 +1061,12 @@
please note that this workaround results in increased DSU power consumption
on idle.
+- ``ERRATA_DSU_2900952``: This applies errata 2900952 workaround for the
+ affected DSU-120 configurations. This erratum applies to some r2p0
+ implementations and is fixed in r2p1. The affected r2p0 implementations
+ are determined by reading the IMP_CLUSTERREVIDR_EL1[1] register bit
+ and making sure it's clear.
+
CPU Specific optimizations
--------------------------
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 1b3568e..e80f3d1 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -481,6 +481,11 @@
the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism.
Default value is ``0``.
+ - ``ENABLE_FEAT_GCIE``: Boolean value to enable support for the GICv5 CPU
+ interface (see ``USE_GIC_DRIVER`` for the IRI). GICv5 and GICv3 are mutually
+ exclusive, so the ``ENABLE_FEAT`` mechanism is currently not supported.
+ Default value is ``0``.
+
- ``ENABLE_FEAT_THE``: Numeric value to enable support for FEAT_THE
(Translation Hardening Extension) at EL2 and below, setting the bit
SCR_EL3.RCWMASKEn in EL3 to allow access to RCWMASK_EL1 and RCWSMASK_EL1
@@ -1196,11 +1201,6 @@
cluster platforms). If this option is enabled, then warm boot path
enables D-caches immediately after enabling MMU. This option defaults to 0.
-- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory
- tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The
- default value of this flag is ``no``. Note this option must be enabled only
- for ARM architecture greater than Armv8.5-A.
-
- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT``
speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``.
The default value of this flag is ``0``.
@@ -1313,6 +1313,7 @@
- ``3``: use the GICv3 driver. See the next section on how to further configure
it. Use this option for GICv4 implementations.
+ - ``5``: use the EXPERIMENTAL GICv5 driver. Requires ``ENABLE_FEAT_GCIE=1``.
For GIC driver versions other than ``1``, deciding when to save and restore GIC
context on a power domain state transition, as well as any GIC actions outside
diff --git a/docs/getting_started/docs-build.rst b/docs/getting_started/docs-build.rst
index 54e29dd..e11da77 100644
--- a/docs/getting_started/docs-build.rst
+++ b/docs/getting_started/docs-build.rst
@@ -42,7 +42,7 @@
.. code:: shell
- poetry run make doc
+ make doc
Output from the build process will be placed in: ``docs/build/html``.
@@ -55,7 +55,7 @@
.. code:: shell
- poetry run make -C docs help
+ make -C docs help
To build the documentation in PDF format, additionally ensure that the following
packages are installed:
@@ -80,9 +80,10 @@
Building rendered documentation from Poetry's virtual environment
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-The command ``poetry run`` used in the steps above executes the input command
-from inside the project's virtual environment. The easiest way to activate this
-virtual environment is with the ``poetry shell`` command.
+If Poetry is installed, the ``doc`` target wraps its build steps with ``poetry
+run``, which runs the specified command within the project's virtual
+environment. The easiest way to activate this environment manually is by using
+the ``poetry shell`` command.
Running ``poetry shell`` from the directory containing this project, activates
the same virtual environment. This creates a sub-shell through which you can
@@ -91,7 +92,7 @@
.. code:: shell
poetry shell
- make doc
+ make -C docs html
Type ``exit`` to deactivate the virtual environment and exit this new shell. For
other use cases, please see the official `Poetry`_ documentation.
@@ -121,7 +122,7 @@
--------------
-*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2025, Arm Limited. All rights reserved.*
.. _Sphinx: http://www.sphinx-doc.org/en/master/
.. _Poetry: https://python-poetry.org/docs/
diff --git a/docs/plat/arm/fvp/fvp-build-options.rst b/docs/plat/arm/fvp/fvp-build-options.rst
index 79dc0dc..3d87494 100644
--- a/docs/plat/arm/fvp/fvp-build-options.rst
+++ b/docs/plat/arm/fvp/fvp-build-options.rst
@@ -27,6 +27,7 @@
- ``FVP_GICV2`` : The GICv2 only driver is selected
- ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
+ - ``FVP_GICV5`` : The GICv5 only driver is selected
- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for
@@ -41,6 +42,9 @@
HW_CONFIG blob instead of the DTS file. This option is useful to override
the default HW_CONFIG selected by the build system.
+- ``FVP_HW_CONFIG_ADDR`` : Specify the memory address in which to load the
+ HW_CONFIG. The default value is ``0x82000000``.
+
- ``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of
inactive/fused CPU cores as read-only. The default value of this option
is ``0``, which means the redistributor pages of all CPU cores are marked
diff --git a/docs/plat/arm/fvp/fvp-specific-configs.rst b/docs/plat/arm/fvp/fvp-specific-configs.rst
index 0f51e4b..9608969 100644
--- a/docs/plat/arm/fvp/fvp-specific-configs.rst
+++ b/docs/plat/arm/fvp/fvp-specific-configs.rst
@@ -241,6 +241,34 @@
(Default) For use with Foundation FVP with Base memory map configuration
and Linux GICv3 support.
+GICv5 Support
+^^^^^^^^^^^^^
+
+GICv5 support in TF-A is currently **experimental** and provided only for early
+development and testing purposes. A simplified build configuration is available
+to allow booting the Linux kernel as a BL33 payload on the FVP platform.
+
+Key notes:
+
+- The support is **not production-ready** and is intended to assist with
+ upstream kernel development and validation.
+- The device tree bindings are **not finalized**; support has been validated
+ only with a **custom device tree**.
+- Use this configuration at your own discretion, understanding that the design
+ and register usage may change in future revisions.
+
+This configuration is **temporary** and may be removed once full GICv5 support
+is integrated upstream.
+
+.. code:: shell
+
+ make PLAT=fvp DEBUG=1 \
+ CTX_INCLUDE_AARCH32_REGS=0 \
+ FVP_USE_GIC_DRIVER=FVP_GICV5 \
+ ARM_LINUX_KERNEL_AS_BL33=1 \
+ PRELOADED_BL33_BASE=0x84000000 \
+ FVP_HW_CONFIG_DTS=<PROVIDE_YOUR_OWN_DT> \
+
--------------
*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
diff --git a/docs/plat/st/stm32mp2.rst b/docs/plat/st/stm32mp2.rst
index 87bb6a5..e64b989 100644
--- a/docs/plat/st/stm32mp2.rst
+++ b/docs/plat/st/stm32mp2.rst
@@ -12,6 +12,43 @@
STM32MP2 Versions
-----------------
+Here are the variants for STM32MP2:
+- STM32MP21
+- STM32MP23
+- STM32MP25
+
+STM32MP21 Versions
+~~~~~~~~~~~~~~~~~~
+The STM32MP21 series is available in 3 different lines which are pin-to-pin compatible:
+
+- STM32MP215: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD - CSI - LTDC
+- STM32MP213: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
+- STM32MP211: Single Cortex-A35 + Cortex-M33 - 1x Ethernet
+
+Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
+
+- A Basic + Cortex-A35 @ 1.2GHz
+- C Secure Boot + HW Crypto + Cortex-A35 @ 1.2GHz
+- D Basic + Cortex-A35 @ 1.5GHz
+- F Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz
+
+STM32MP23 Versions
+~~~~~~~~~~~~~~~~~~
+The STM32MP23 series is available in 3 different lines which are pin-to-pin compatible:
+
+- STM32MP235: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD - H264 - 3D GPU - AI / NN - LVDS / DSI
+- STM32MP233: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
+- STM32MP231: Single Cortex-A35 + Cortex-M33 - 1x Ethernet
+
+Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
+
+- A Basic + Cortex-A35 @ 1.2GHz
+- C Secure Boot + HW Crypto + Cortex-A35 @ 1.2GHz
+- D Basic + Cortex-A35 @ 1.5GHz
+- F Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz
+
+STM32MP25 Versions
+~~~~~~~~~~~~~~~~~~
The STM32MP25 series is available in 4 different lines which are pin-to-pin compatible:
- STM32MP257: Dual Cortex-A35 cores, Cortex-M33 core - 3x Ethernet (2+1 switch) - 3x CAN FD – H264 - 3D GPU – AI / NN - LVDS
@@ -70,6 +107,10 @@
- | ``STM32MP_DDR_FIP_IO_STORAGE``: to store DDR firmware in FIP.
| Default: 1
+- | ``STM32MP21``: to select STM32MP21 variant configuration.
+ | Default: 0
+- | ``STM32MP23``: to select STM32MP23 variant configuration.
+ | Default: 0
- | ``STM32MP25``: to select STM32MP25 variant configuration.
| Default: 1
@@ -154,4 +195,4 @@
.. _STM32MP2 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP25_microprocessor#Part_number_codification
.. _STMicroelectronics DDR PHY github: https://github.com/STMicroelectronics/stm32-ddr-phy-binary
-*Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved*
+*Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved*
diff --git a/docs/process/commit-style.rst b/docs/process/commit-style.rst
index c287599..97b4b44 100644
--- a/docs/process/commit-style.rst
+++ b/docs/process/commit-style.rst
@@ -36,6 +36,9 @@
[optional footer(s)]
+Note that the type, the scope and the first letter of the description (also
+called subject by the commitlint checker) must be lower case.
+
The following example commit message demonstrates the use of the
``refactor`` type and the ``amu`` scope:
@@ -144,7 +147,7 @@
--------------
-*Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.*
.. _Conventional Commits: https://www.conventionalcommits.org/en/v1.0.0
.. _Gerrit Change-Ids documentation: https://review.trustedfirmware.org/Documentation/user-changeid.html
diff --git a/drivers/arm/gic/gic.mk b/drivers/arm/gic/gic.mk
index ad30984..8b28f21 100644
--- a/drivers/arm/gic/gic.mk
+++ b/drivers/arm/gic/gic.mk
@@ -4,7 +4,7 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-GIC_REVISIONS_ := 1 2 3
+GIC_REVISIONS_ := 1 2 3 5
ifeq ($(filter $(USE_GIC_DRIVER),$(GIC_REVISIONS_)),)
$(error USE_GIC_DRIVER can only be one of $(GIC_REVISIONS_))
endif
@@ -19,6 +19,18 @@
GIC_SOURCES := ${GICV3_SOURCES} \
drivers/arm/gic/v3/gicv3_base.c \
plat/common/plat_gicv3.c
+else ifeq (${USE_GIC_DRIVER},5)
+ifneq (${ENABLE_FEAT_GCIE},1)
+$(error USE_GIC_DRIVER=5 requires ENABLE_FEAT_GCIE=1)
+endif
+$(warning GICv5 support is experimental!)
+GIC_SOURCES := drivers/arm/gicv5/gicv5_iri.c \
+ plat/common/plat_gicv5.c
+endif
+
+ifneq (${ENABLE_FEAT_GCIE},0)
+GIC_SOURCES += drivers/arm/gicv5/gicv5_cpuif.c \
+ drivers/arm/gicv5/gicv5_main.c
endif
ifeq ($(ARCH),aarch64)
diff --git a/drivers/arm/gicv5/gicv5_cpuif.c b/drivers/arm/gicv5/gicv5_cpuif.c
new file mode 100644
index 0000000..eb17206
--- /dev/null
+++ b/drivers/arm/gicv5/gicv5_cpuif.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/gic.h>
+#include <drivers/arm/gicv5.h>
+
+void gic_cpuif_enable(unsigned int cpu_idx)
+{
+}
+
+void gic_cpuif_disable(unsigned int cpu_idx)
+{
+}
+
+void gic_pcpu_init(unsigned int cpu_idx)
+{
+ gicv5_enable_ppis();
+}
+
+void gic_pcpu_off(unsigned int cpu_idx)
+{
+}
+
diff --git a/drivers/arm/gicv5/gicv5_iri.c b/drivers/arm/gicv5/gicv5_iri.c
new file mode 100644
index 0000000..049f3f0
--- /dev/null
+++ b/drivers/arm/gicv5/gicv5_iri.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <cdefs.h>
+#include <drivers/arm/gic.h>
+#include <drivers/arm/gicv5.h>
+
+#if USE_GIC_DRIVER != 5
+#error "This file should only be used with USE_GIC_DRIVER=5"
+#endif
+
+void __init gic_init(unsigned int cpu_idx)
+{
+ gicv5_driver_init();
+}
+
+void gic_save(void)
+{
+}
+
+void gic_resume(void)
+{
+}
diff --git a/drivers/arm/gicv5/gicv5_main.c b/drivers/arm/gicv5/gicv5_main.c
new file mode 100644
index 0000000..803a96d
--- /dev/null
+++ b/drivers/arm/gicv5/gicv5_main.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <cdefs.h>
+
+#include <arch.h>
+#include <arch_features.h>
+#include <arch_helpers.h>
+
+#include <bl31/interrupt_mgmt.h>
+#include <common/debug.h>
+#include <drivers/arm/gicv5.h>
+
+/*
+ * Check for a bad platform configuration.
+ * Not expected to be called on release builds.
+ */
+static inline bool probe_component(uintptr_t base_addr, uint8_t component)
+{
+ uint32_t aidr = read_iri_aidr(base_addr);
+
+ if (EXTRACT(IRI_AIDR_COMPONENT, aidr) != component) {
+ ERROR("GICv5 frame belongs to wrong component\n");
+ return false;
+ }
+
+ if (EXTRACT(IRI_AIDR_ARCH_MAJOR, aidr) != IRI_AIDR_ARCH_MAJOR_V5) {
+ ERROR("Bad GICv5 major version\n");
+ return false;
+ }
+
+ /* there was a bump in architecture and we've not updated the driver */
+ assert(EXTRACT(IRI_AIDR_ARCH_MINOR, aidr) == IRI_AIDR_ARCH_MINOR_P0);
+
+ return true;
+}
+
+static inline bool iwb_domain_supported(uint32_t idr0, uint8_t domain)
+{
+ return (EXTRACT(IWB_IDR0_DOMAINS, idr0) & (1U << domain)) != 0U;
+}
+
+static void iwb_configure_domainr(uintptr_t base_addr, struct gicv5_wire_props wire)
+{
+ uint32_t reg_offset = (wire.id % 16U) * 2U;
+ uint32_t reg_index = wire.id / 16U;
+ uint32_t val = read_iwb_wdomainr(base_addr, reg_index) &
+ ~(IWB_WDOMAINR_DOMAINX_MASK << reg_offset);
+
+ write_iwb_wdomainr(base_addr, reg_index, val | wire.domain << reg_offset);
+}
+
+static void iwb_configure_wtmr(uintptr_t base_addr, struct gicv5_wire_props wire)
+{
+ uint32_t reg_offset = wire.id % 32U;
+ uint32_t reg_index = wire.id / 32U;
+ uint32_t val = read_iwb_wtmr(base_addr, reg_index) & ~(1U << reg_offset);
+
+ write_iwb_wtmr(base_addr, reg_index, val | wire.tm << reg_offset);
+}
+
+static void iwb_enable(const struct gicv5_iwb *config)
+{
+ uintptr_t base_addr = config->config_frame;
+ uint32_t idr0;
+ uint16_t num_regs;
+
+ assert(probe_component(base_addr, IRI_AIDR_COMPONENT_IWB));
+
+ idr0 = read_iwb_idr0(base_addr);
+ num_regs = EXTRACT(IWB_IDR0_IWRANGE, idr0) + 1U;
+
+ /* initialise all wires as disabled */
+ for (int i = 0U; i < num_regs; i++) {
+ write_iwb_wenabler(base_addr, i, 0U);
+ }
+
+ /* default all wires to the NS domain */
+ for (int i = 0U; i < num_regs * 2; i++) {
+ write_iwb_wdomainr(base_addr, i, 0x55555555);
+ }
+
+ for (uint32_t i = 0U; i < config->num_wires; i++) {
+ assert(iwb_domain_supported(idr0, config->wires[i].domain));
+ assert(config->wires[i].id <= num_regs * 32);
+
+ iwb_configure_domainr(base_addr, config->wires[i]);
+ iwb_configure_wtmr(base_addr, config->wires[i]);
+ }
+
+ write_iwb_cr0(base_addr, IWB_CR0_IWBEN_BIT);
+ WAIT_FOR_IDLE_IWB_WENABLE_STATUSR(base_addr);
+ WAIT_FOR_IDLE_IWB_WDOMAIN_STATUSR(base_addr);
+ WAIT_FOR_IDLE_IWB_CR0(base_addr);
+}
+
+static void irs_configure_wire(uintptr_t base_addr, uint32_t wire, uint8_t domain)
+{
+ write_irs_spi_selr(base_addr, wire);
+ WAIT_FOR_VIDLE_IRS_SPI_STATUSR(base_addr);
+
+ write_irs_spi_domainr(base_addr, domain);
+ WAIT_FOR_VIDLE_IRS_SPI_STATUSR(base_addr);
+}
+
+static void irs_enable(const struct gicv5_irs *config)
+{
+ uint32_t spi_base, spi_range;
+ uintptr_t base_addr = config->el3_config_frame;
+
+ spi_base = EXTRACT(IRS_IDR7_SPI_BASE, read_irs_idr7(base_addr));
+ spi_range = EXTRACT(IRS_IDR6_SPI_IRS_RANGE, read_irs_idr6(base_addr));
+
+ assert(probe_component(base_addr, IRI_AIDR_COMPONENT_IRS));
+
+ if (spi_range == 0U) {
+ assert(config->num_spis == 0U);
+ }
+
+ /* default all wires to the NS domain */
+ for (uint32_t i = spi_base; i < spi_base + spi_range; i++) {
+ irs_configure_wire(base_addr, i, INTDMN_NS);
+ }
+
+ for (uint32_t i = 0U; i < config->num_spis; i++) {
+ assert((config->spis[i].id >= spi_base) &&
+ (config->spis[i].id < spi_base + spi_range));
+
+ irs_configure_wire(base_addr, config->spis[i].id, config->spis[i].domain);
+
+ /* don't (can't) configure TM of wires for other domains */
+ if (config->spis[i].domain == INTDMN_EL3) {
+ write_irs_spi_cfgr(base_addr, config->spis[i].tm);
+ WAIT_FOR_VIDLE_IRS_SPI_STATUSR(base_addr);
+ }
+ }
+}
+
+void __init gicv5_driver_init(void)
+{
+ for (size_t i = 0U; i < plat_gicv5_driver_data.num_iwbs; i++) {
+ iwb_enable(&plat_gicv5_driver_data.iwbs[i]);
+ }
+
+ for (size_t i = 0U; i < plat_gicv5_driver_data.num_irss; i++) {
+ irs_enable(&plat_gicv5_driver_data.irss[i]);
+ }
+}
+
+/*
+ * There exists a theoretical configuration where FEAT_RME is enabled
+ * without using TrustZone (i.e., no Secure world present). Currently,
+ * there is no reliable mechanism to detect this scenario at runtime.
+ *
+ * TODO: Add support for this configuration in the future if required.
+ */
+bool gicv5_has_interrupt_type(unsigned int type)
+{
+ switch (type) {
+ case INTR_TYPE_EL3:
+ case INTR_TYPE_S_EL1:
+ case INTR_TYPE_NS:
+ return true;
+ case INTR_TYPE_RL:
+ return is_feat_rme_supported();
+ default:
+ return false;
+ }
+}
+
+uint8_t gicv5_get_pending_interrupt_type(void)
+{
+ /* there is no pending interrupt expected */
+ return INTR_TYPE_INVAL;
+}
+
+/* TODO: these will probably end up contexted. Make Linux work for now */
+void gicv5_enable_ppis(void)
+{
+ uint64_t domainr = 0U;
+
+ /* the only ones described in the device tree at the moment */
+ write_icc_ppi_domainr(domainr, PPI_PMUIRQ, INTDMN_NS);
+ write_icc_ppi_domainr(domainr, PPI_GICMNT, INTDMN_NS);
+ write_icc_ppi_domainr(domainr, PPI_CNTHP, INTDMN_NS);
+ write_icc_ppi_domainr(domainr, PPI_CNTV, INTDMN_NS);
+ write_icc_ppi_domainr(domainr, PPI_CNTPS, INTDMN_NS);
+ write_icc_ppi_domainr(domainr, PPI_CNTP, INTDMN_NS);
+
+ write_icc_ppi_domainr0_el3(domainr);
+}
diff --git a/drivers/imx/usdhc/imx_usdhc.c b/drivers/imx/usdhc/imx_usdhc.c
index 49dfc07..f6a27dc 100644
--- a/drivers/imx/usdhc/imx_usdhc.c
+++ b/drivers/imx/usdhc/imx_usdhc.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright 2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,9 +15,22 @@
#include <drivers/delay_timer.h>
#include <drivers/mmc.h>
#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
#include <imx_usdhc.h>
+/* These masks represent the commands which involve a data transfer. */
+#define ADTC_MASK_SD (BIT_32(6U) | BIT_32(17U) | BIT_32(18U) |\
+ BIT_32(24U) | BIT_32(25U))
+#define ADTC_MASK_ACMD (BIT_64(51U))
+
+struct imx_usdhc_device_data {
+ uint32_t addr;
+ uint32_t blk_size;
+ uint32_t blks;
+ bool valid;
+};
+
static void imx_usdhc_initialize(void);
static int imx_usdhc_send_cmd(struct mmc_cmd *cmd);
static int imx_usdhc_set_ios(unsigned int clk, unsigned int width);
@@ -34,27 +48,85 @@
};
static imx_usdhc_params_t imx_usdhc_params;
+static struct imx_usdhc_device_data imx_usdhc_data;
+
+static bool imx_usdhc_is_buf_valid(void)
+{
+ return imx_usdhc_data.valid;
+}
+
+static bool imx_usdhc_is_buf_multiblk(void)
+{
+ return imx_usdhc_data.blks > 1U;
+}
+
+static void imx_usdhc_inval_buf_data(void)
+{
+ imx_usdhc_data.valid = false;
+}
+
+static int imx_usdhc_save_buf_data(uintptr_t buf, size_t size)
+{
+ uint32_t block_size;
+ uint64_t blks;
+
+ if (size <= MMC_BLOCK_SIZE) {
+ block_size = (uint32_t)size;
+ } else {
+ block_size = MMC_BLOCK_SIZE;
+ }
+
+ if (buf > UINT32_MAX) {
+ return -EOVERFLOW;
+ }
+
+ imx_usdhc_data.addr = (uint32_t)buf;
+ imx_usdhc_data.blk_size = block_size;
+ blks = size / block_size;
+ imx_usdhc_data.blks = (uint32_t)blks;
+
+ imx_usdhc_data.valid = true;
+
+ return 0;
+}
+
+static void imx_usdhc_write_buf_data(void)
+{
+ uintptr_t reg_base = imx_usdhc_params.reg_base;
+ uint32_t addr, blks, blk_size;
+
+ addr = imx_usdhc_data.addr;
+ blks = imx_usdhc_data.blks;
+ blk_size = imx_usdhc_data.blk_size;
+
+ mmio_write_32(reg_base + DSADDR, addr);
+ mmio_write_32(reg_base + BLKATT, BLKATT_BLKCNT(blks) |
+ BLKATT_BLKSIZE(blk_size));
+}
#define IMX7_MMC_SRC_CLK_RATE (200 * 1000 * 1000)
-static void imx_usdhc_set_clk(int clk)
+static void imx_usdhc_set_clk(unsigned int clk)
{
- int div = 1;
- int pre_div = 1;
unsigned int sdhc_clk = IMX7_MMC_SRC_CLK_RATE;
uintptr_t reg_base = imx_usdhc_params.reg_base;
+ unsigned int pre_div = 1U, div = 1U;
assert(clk > 0);
while (sdhc_clk / (16 * pre_div) > clk && pre_div < 256)
pre_div *= 2;
- while (sdhc_clk / div > clk && div < 16)
+ while (((sdhc_clk / (div * pre_div)) > clk) && (div < 16U)) {
div++;
+ }
pre_div >>= 1;
div -= 1;
clk = (pre_div << 8) | (div << 4);
+ while ((mmio_read_32(reg_base + PSTATE) & PSTATE_SDSTB) == 0U) {
+ }
+
mmio_clrbits32(reg_base + VENDSPEC, VENDSPEC_CARD_CLKEN);
mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk);
udelay(10000);
@@ -107,15 +179,85 @@
#define FSL_CMD_RETRIES 1000
+static bool is_data_transfer_to_card(const struct mmc_cmd *cmd)
+{
+ unsigned int cmd_idx = cmd->cmd_idx;
+
+ return (cmd_idx == MMC_CMD(24)) || (cmd_idx == MMC_CMD(25));
+}
+
+static bool is_data_transfer_cmd(const struct mmc_cmd *cmd)
+{
+ uintptr_t reg_base = imx_usdhc_params.reg_base;
+ unsigned int cmd_idx = cmd->cmd_idx;
+ uint32_t xfer_type;
+
+ xfer_type = mmio_read_32(reg_base + XFERTYPE);
+
+ if (XFERTYPE_GET_CMD(xfer_type) == MMC_CMD(55)) {
+ return (ADTC_MASK_ACMD & BIT_64(cmd_idx)) != 0ULL;
+ }
+
+ if ((ADTC_MASK_SD & BIT_32(cmd->cmd_idx)) != 0U) {
+ return true;
+ }
+
+ return false;
+}
+
+static int get_xfr_type(const struct mmc_cmd *cmd, bool data, uint32_t *xfertype)
+{
+ *xfertype = XFERTYPE_CMD(cmd->cmd_idx);
+
+ switch (cmd->resp_type) {
+ case MMC_RESPONSE_R2:
+ *xfertype |= XFERTYPE_RSPTYP_136;
+ *xfertype |= XFERTYPE_CCCEN;
+ break;
+ case MMC_RESPONSE_R4:
+ *xfertype |= XFERTYPE_RSPTYP_48;
+ break;
+ case MMC_RESPONSE_R6:
+ *xfertype |= XFERTYPE_RSPTYP_48;
+ *xfertype |= XFERTYPE_CICEN;
+ *xfertype |= XFERTYPE_CCCEN;
+ break;
+ case MMC_RESPONSE_R1B:
+ *xfertype |= XFERTYPE_RSPTYP_48_BUSY;
+ *xfertype |= XFERTYPE_CICEN;
+ *xfertype |= XFERTYPE_CCCEN;
+ break;
+ default:
+ ERROR("Invalid CMD response: %u\n", cmd->resp_type);
+ return -EINVAL;
+ }
+
+ if (data) {
+ *xfertype |= XFERTYPE_DPSEL;
+ }
+
+ return 0;
+}
+
static int imx_usdhc_send_cmd(struct mmc_cmd *cmd)
{
uintptr_t reg_base = imx_usdhc_params.reg_base;
- unsigned int xfertype = 0, mixctl = 0, multiple = 0, data = 0, err = 0;
unsigned int state, flags = INTSTATEN_CC | INTSTATEN_CTOE;
+ unsigned int mixctl = 0;
unsigned int cmd_retries = 0;
+ uint32_t xfertype;
+ bool data;
+ int err = 0;
assert(cmd);
+ data = is_data_transfer_cmd(cmd);
+
+ err = get_xfr_type(cmd, data, &xfertype);
+ if (err != 0) {
+ return err;
+ }
+
/* clear all irq status */
mmio_write_32(reg_base + INTSTAT, 0xffffffff);
@@ -128,56 +270,23 @@
;
mmio_write_32(reg_base + INTSIGEN, 0);
- udelay(1000);
-
- switch (cmd->cmd_idx) {
- case MMC_CMD(12):
- xfertype |= XFERTYPE_CMDTYP_ABORT;
- break;
- case MMC_CMD(18):
- multiple = 1;
- /* for read op */
- /* fallthrough */
- case MMC_CMD(17):
- case MMC_CMD(8):
- mixctl |= MIXCTRL_DTDSEL;
- data = 1;
- break;
- case MMC_CMD(25):
- multiple = 1;
- /* for data op flag */
- /* fallthrough */
- case MMC_CMD(24):
- data = 1;
- break;
- default:
- break;
- }
-
- if (multiple) {
- mixctl |= MIXCTRL_MSBSEL;
- mixctl |= MIXCTRL_BCEN;
- }
if (data) {
- xfertype |= XFERTYPE_DPSEL;
mixctl |= MIXCTRL_DMAEN;
}
- if (cmd->resp_type & MMC_RSP_48 && cmd->resp_type != MMC_RESPONSE_R2)
- xfertype |= XFERTYPE_RSPTYP_48;
- else if (cmd->resp_type & MMC_RSP_136)
- xfertype |= XFERTYPE_RSPTYP_136;
- else if (cmd->resp_type & MMC_RSP_BUSY)
- xfertype |= XFERTYPE_RSPTYP_48_BUSY;
+ if (!is_data_transfer_to_card(cmd)) {
+ mixctl |= MIXCTRL_DTDSEL;
+ }
- if (cmd->resp_type & MMC_RSP_CMD_IDX)
- xfertype |= XFERTYPE_CICEN;
+ if ((cmd->cmd_idx != MMC_CMD(55)) && imx_usdhc_is_buf_valid()) {
+ if (imx_usdhc_is_buf_multiblk()) {
+ mixctl |= MIXCTRL_MSBSEL | MIXCTRL_BCEN;
+ }
- if (cmd->resp_type & MMC_RSP_CRC)
- xfertype |= XFERTYPE_CCCEN;
-
- xfertype |= XFERTYPE_CMD(cmd->cmd_idx);
+ imx_usdhc_write_buf_data();
+ imx_usdhc_inval_buf_data();
+ }
/* Send the command */
mmio_write_32(reg_base + CMDARG, cmd->cmd_arg);
@@ -269,17 +378,13 @@
static int imx_usdhc_prepare(int lba, uintptr_t buf, size_t size)
{
- uintptr_t reg_base = imx_usdhc_params.reg_base;
-
- mmio_write_32(reg_base + DSADDR, buf);
- mmio_write_32(reg_base + BLKATT,
- (size / MMC_BLOCK_SIZE) << 16 | MMC_BLOCK_SIZE);
-
- return 0;
+ flush_dcache_range(buf, size);
+ return imx_usdhc_save_buf_data(buf, size);
}
static int imx_usdhc_read(int lba, uintptr_t buf, size_t size)
{
+ inv_dcache_range(buf, size);
return 0;
}
@@ -291,13 +396,24 @@
void imx_usdhc_init(imx_usdhc_params_t *params,
struct mmc_device_info *mmc_dev_info)
{
+ int ret __maybe_unused;
+
assert((params != 0) &&
((params->reg_base & MMC_BLOCK_MASK) == 0) &&
- (params->clk_rate > 0) &&
((params->bus_width == MMC_BUS_WIDTH_1) ||
(params->bus_width == MMC_BUS_WIDTH_4) ||
(params->bus_width == MMC_BUS_WIDTH_8)));
+#if PLAT_XLAT_TABLES_DYNAMIC
+ ret = mmap_add_dynamic_region(params->reg_base, params->reg_base,
+ PAGE_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE);
+ if (ret != 0) {
+ ERROR("Failed to map the uSDHC registers\n");
+ panic();
+ }
+#endif
+
memcpy(&imx_usdhc_params, params, sizeof(imx_usdhc_params_t));
mmc_init(&imx_usdhc_ops, params->clk_rate, params->bus_width,
params->flags, mmc_dev_info);
diff --git a/drivers/imx/usdhc/imx_usdhc.h b/drivers/imx/usdhc/imx_usdhc.h
index e063316..bb0ef01 100644
--- a/drivers/imx/usdhc/imx_usdhc.h
+++ b/drivers/imx/usdhc/imx_usdhc.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright 2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,8 +12,8 @@
typedef struct imx_usdhc_params {
uintptr_t reg_base;
- int clk_rate;
- int bus_width;
+ unsigned int clk_rate;
+ unsigned int bus_width;
unsigned int flags;
} imx_usdhc_params_t;
@@ -20,115 +21,119 @@
struct mmc_device_info *mmc_dev_info);
/* iMX MMC registers definition */
-#define DSADDR 0x000
-#define BLKATT 0x004
-#define CMDARG 0x008
-#define CMDRSP0 0x010
-#define CMDRSP1 0x014
-#define CMDRSP2 0x018
-#define CMDRSP3 0x01c
+#define DSADDR 0x000U
+#define BLKATT 0x004U
+#define BLKATT_BLKCNT(x) (((x) << 16U) & GENMASK_32(31U, 16U))
+#define BLKATT_BLKSIZE(x) ((x) & GENMASK_32(12U, 0U))
+#define CMDARG 0x008U
+#define CMDRSP0 0x010U
+#define CMDRSP1 0x014U
+#define CMDRSP2 0x018U
+#define CMDRSP3 0x01cU
-#define XFERTYPE 0x00c
-#define XFERTYPE_CMD(x) (((x) & 0x3f) << 24)
-#define XFERTYPE_CMDTYP_ABORT (3 << 22)
-#define XFERTYPE_DPSEL BIT(21)
-#define XFERTYPE_CICEN BIT(20)
-#define XFERTYPE_CCCEN BIT(19)
-#define XFERTYPE_RSPTYP_136 BIT(16)
-#define XFERTYPE_RSPTYP_48 BIT(17)
-#define XFERTYPE_RSPTYP_48_BUSY (BIT(16) | BIT(17))
+#define XFERTYPE 0x00cU
+#define XFERTYPE_CMD(x) (((x) & 0x3fU) << 24U)
+#define XFERTYPE_GET_CMD(x) (((x) & GENMASK_32(29U, 24U)) >> 24U)
+#define XFERTYPE_CMDTYP_ABORT (3U << 22U)
+#define XFERTYPE_DPSEL BIT_32(21U)
+#define XFERTYPE_CICEN BIT_32(20U)
+#define XFERTYPE_CCCEN BIT_32(19U)
+#define XFERTYPE_RSPTYP_136 BIT_32(16U)
+#define XFERTYPE_RSPTYP_48 BIT_32(17U)
+#define XFERTYPE_RSPTYP_48_BUSY (BIT_32(16U) | BIT_32(17U))
-#define PSTATE 0x024
-#define PSTATE_DAT0 BIT(24)
-#define PSTATE_DLA BIT(2)
-#define PSTATE_CDIHB BIT(1)
-#define PSTATE_CIHB BIT(0)
+#define PSTATE 0x024U
+#define PSTATE_DAT0 BIT_32(24U)
+#define PSTATE_SDSTB BIT_32(3U)
+#define PSTATE_DLA BIT_32(2U)
+#define PSTATE_CDIHB BIT_32(1U)
+#define PSTATE_CIHB BIT_32(0U)
-#define PROTCTRL 0x028
-#define PROTCTRL_LE BIT(5)
-#define PROTCTRL_WIDTH_4 BIT(1)
-#define PROTCTRL_WIDTH_8 BIT(2)
-#define PROTCTRL_WIDTH_MASK 0x6
+#define PROTCTRL 0x028U
+#define PROTCTRL_LE BIT_32(5U)
+#define PROTCTRL_WIDTH_4 BIT_32(1U)
+#define PROTCTRL_WIDTH_8 BIT_32(2U)
+#define PROTCTRL_WIDTH_MASK 0x6U
-#define SYSCTRL 0x02c
-#define SYSCTRL_RSTD BIT(26)
-#define SYSCTRL_RSTC BIT(25)
-#define SYSCTRL_RSTA BIT(24)
-#define SYSCTRL_CLOCK_MASK 0x0000fff0
-#define SYSCTRL_TIMEOUT_MASK 0x000f0000
-#define SYSCTRL_TIMEOUT(x) ((0xf & (x)) << 16)
+#define SYSCTRL 0x02cU
+#define SYSCTRL_RSTD BIT_32(26U)
+#define SYSCTRL_RSTC BIT_32(25U)
+#define SYSCTRL_RSTA BIT_32(24U)
+#define SYSCTRL_CLOCK_MASK GENMASK_32(15U, 4U)
+#define SYSCTRL_TIMEOUT_MASK GENMASK_32(19U, 16U)
+#define SYSCTRL_TIMEOUT(x) ((0xfU & (x)) << 16U)
-#define INTSTAT 0x030
-#define INTSTAT_DMAE BIT(28)
-#define INTSTAT_DEBE BIT(22)
-#define INTSTAT_DCE BIT(21)
-#define INTSTAT_DTOE BIT(20)
-#define INTSTAT_CIE BIT(19)
-#define INTSTAT_CEBE BIT(18)
-#define INTSTAT_CCE BIT(17)
-#define INTSTAT_DINT BIT(3)
-#define INTSTAT_BGE BIT(2)
-#define INTSTAT_TC BIT(1)
-#define INTSTAT_CC BIT(0)
+#define INTSTAT 0x030U
+#define INTSTAT_DMAE BIT_32(28U)
+#define INTSTAT_DEBE BIT_32(22U)
+#define INTSTAT_DCE BIT_32(21U)
+#define INTSTAT_DTOE BIT_32(20U)
+#define INTSTAT_CIE BIT_32(19U)
+#define INTSTAT_CEBE BIT_32(18U)
+#define INTSTAT_CCE BIT_32(17U)
+#define INTSTAT_DINT BIT_32(3U)
+#define INTSTAT_BGE BIT_32(2U)
+#define INTSTAT_TC BIT_32(1U)
+#define INTSTAT_CC BIT_32(0U)
#define CMD_ERR (INTSTAT_CIE | INTSTAT_CEBE | INTSTAT_CCE)
#define DATA_ERR (INTSTAT_DMAE | INTSTAT_DEBE | INTSTAT_DCE | \
INTSTAT_DTOE)
#define DATA_COMPLETE (INTSTAT_DINT | INTSTAT_TC)
-#define INTSTATEN 0x034
-#define INTSTATEN_DEBE BIT(22)
-#define INTSTATEN_DCE BIT(21)
-#define INTSTATEN_DTOE BIT(20)
-#define INTSTATEN_CIE BIT(19)
-#define INTSTATEN_CEBE BIT(18)
-#define INTSTATEN_CCE BIT(17)
-#define INTSTATEN_CTOE BIT(16)
-#define INTSTATEN_CINT BIT(8)
-#define INTSTATEN_BRR BIT(5)
-#define INTSTATEN_BWR BIT(4)
-#define INTSTATEN_DINT BIT(3)
-#define INTSTATEN_TC BIT(1)
-#define INTSTATEN_CC BIT(0)
+#define INTSTATEN 0x034U
+#define INTSTATEN_DEBE BIT_32(22U)
+#define INTSTATEN_DCE BIT_32(21U)
+#define INTSTATEN_DTOE BIT_32(20U)
+#define INTSTATEN_CIE BIT_32(19U)
+#define INTSTATEN_CEBE BIT_32(18U)
+#define INTSTATEN_CCE BIT_32(17U)
+#define INTSTATEN_CTOE BIT_32(16U)
+#define INTSTATEN_CINT BIT_32(8U)
+#define INTSTATEN_BRR BIT_32(5U)
+#define INTSTATEN_BWR BIT_32(4U)
+#define INTSTATEN_DINT BIT_32(3U)
+#define INTSTATEN_TC BIT_32(1U)
+#define INTSTATEN_CC BIT_32(0U)
#define EMMC_INTSTATEN_BITS (INTSTATEN_CC | INTSTATEN_TC | INTSTATEN_DINT | \
INTSTATEN_BWR | INTSTATEN_BRR | INTSTATEN_CINT | \
INTSTATEN_CTOE | INTSTATEN_CCE | INTSTATEN_CEBE | \
INTSTATEN_CIE | INTSTATEN_DTOE | INTSTATEN_DCE | \
INTSTATEN_DEBE)
-#define INTSIGEN 0x038
+#define INTSIGEN 0x038U
-#define WATERMARKLEV 0x044
-#define WMKLV_RD_MASK 0xff
-#define WMKLV_WR_MASK 0x00ff0000
+#define WATERMARKLEV 0x044U
+#define WMKLV_RD_MASK GENMASK_32(7U, 0U)
+#define WMKLV_WR_MASK GENMASK_32(23U, 16U)
#define WMKLV_MASK (WMKLV_RD_MASK | WMKLV_WR_MASK)
-#define MIXCTRL 0x048
-#define MIXCTRL_MSBSEL BIT(5)
-#define MIXCTRL_DTDSEL BIT(4)
-#define MIXCTRL_DDREN BIT(3)
-#define MIXCTRL_AC12EN BIT(2)
-#define MIXCTRL_BCEN BIT(1)
-#define MIXCTRL_DMAEN BIT(0)
-#define MIXCTRL_DATMASK 0x7f
+#define MIXCTRL 0x048U
+#define MIXCTRL_MSBSEL BIT_32(5U)
+#define MIXCTRL_DTDSEL BIT_32(4U)
+#define MIXCTRL_DDREN BIT_32(3U)
+#define MIXCTRL_AC12EN BIT_32(2U)
+#define MIXCTRL_BCEN BIT_32(1U)
+#define MIXCTRL_DMAEN BIT_32(0U)
+#define MIXCTRL_DATMASK 0x7fU
-#define DLLCTRL 0x060
+#define DLLCTRL 0x060U
-#define CLKTUNECTRLSTS 0x068
+#define CLKTUNECTRLSTS 0x068U
-#define VENDSPEC 0x0c0
-#define VENDSPEC_RSRV1 BIT(29)
-#define VENDSPEC_CARD_CLKEN BIT(14)
-#define VENDSPEC_PER_CLKEN BIT(13)
-#define VENDSPEC_AHB_CLKEN BIT(12)
-#define VENDSPEC_IPG_CLKEN BIT(11)
-#define VENDSPEC_AC12_CHKBUSY BIT(3)
-#define VENDSPEC_EXTDMA BIT(0)
+#define VENDSPEC 0x0c0U
+#define VENDSPEC_RSRV1 BIT_32(29U)
+#define VENDSPEC_CARD_CLKEN BIT_32(14U)
+#define VENDSPEC_PER_CLKEN BIT_32(13U)
+#define VENDSPEC_AHB_CLKEN BIT_32(12U)
+#define VENDSPEC_IPG_CLKEN BIT_32(11U)
+#define VENDSPEC_AC12_CHKBUSY BIT_32(3U)
+#define VENDSPEC_EXTDMA BIT_32(0U)
#define VENDSPEC_INIT (VENDSPEC_RSRV1 | VENDSPEC_CARD_CLKEN | \
VENDSPEC_PER_CLKEN | VENDSPEC_AHB_CLKEN | \
VENDSPEC_IPG_CLKEN | VENDSPEC_AC12_CHKBUSY | \
VENDSPEC_EXTDMA)
-#define MMCBOOT 0x0c4
+#define MMCBOOT 0x0c4U
#define mmio_clrsetbits32(addr, clear, set) mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set))
#define mmio_clrbits32(addr, clear) mmio_write_32(addr, mmio_read_32(addr) & ~(clear))
diff --git a/drivers/st/clk/clk-stm32mp2.c b/drivers/st/clk/clk-stm32mp2.c
index 12839f1..1266e00 100644
--- a/drivers/st/clk/clk-stm32mp2.c
+++ b/drivers/st/clk/clk-stm32mp2.c
@@ -105,7 +105,9 @@
_SPDIFSYMB,
_CK_PLL1,
_CK_PLL2,
+#if !STM32MP21
_CK_PLL3,
+#endif /* !STM32MP21 */
_CK_PLL4,
_CK_PLL5,
_CK_PLL6,
@@ -180,6 +182,9 @@
_CK_ICN_APB2,
_CK_ICN_APB3,
_CK_ICN_APB4,
+#if STM32MP21
+ _CK_ICN_APB5,
+#endif /* STM32MP21 */
_CK_ICN_APBDBG,
_CK_BKPSRAM,
_CK_BSEC,
@@ -200,51 +205,82 @@
_CK_GPIOG,
_CK_GPIOH,
_CK_GPIOI,
+#if !STM32MP21
_CK_GPIOJ,
_CK_GPIOK,
+#endif /* !STM32MP21 */
_CK_GPIOZ,
+#if STM32MP21
+ _CK_HASH1,
+ _CK_HASH2,
+#else /* STM32MP21 */
_CK_HASH,
+#endif /* STM32MP21 */
_CK_I2C1,
_CK_I2C2,
+#if !STM32MP23
_CK_I2C3,
+#endif /* !STM32MP23 */
+#if STM32MP25
_CK_I2C4,
_CK_I2C5,
_CK_I2C6,
+#endif /* STM32MP25 */
+#if !STM32MP21
_CK_I2C7,
_CK_I2C8,
+#endif /* !STM32MP21 */
_CK_IWDG1,
_CK_IWDG2,
_CK_OSPI1,
+#if !STM32MP21
_CK_OSPI2,
_CK_OSPIIOM,
+#endif /* !STM32MP21 */
_CK_PKA,
_CK_RETRAM,
+#if STM32MP21
+ _CK_RNG1,
+ _CK_RNG2,
+#else /* STM32MP21 */
_CK_RNG,
+#endif /* STM32MP21 */
_CK_RTC,
_CK_SAES,
_CK_SDMMC1,
_CK_SDMMC2,
_CK_SRAM1,
+#if !STM32MP21
_CK_SRAM2,
+#endif /* !STM32MP21 */
_CK_STGEN,
_CK_SYSCPU1,
_CK_SYSRAM,
_CK_UART4,
_CK_UART5,
_CK_UART7,
+#if STM32MP25
_CK_UART8,
_CK_UART9,
+#endif /* STM32MP25 */
_CK_USART1,
_CK_USART2,
_CK_USART3,
_CK_USART6,
+#if STM32MP21
+ _CK_USBHEHCI,
+ _CK_USBHOHCI,
+#else /* STM32MP21 */
_CK_USB2EHCI,
_CK_USB2OHCI,
+#endif /* STM32MP21 */
_CK_USB2PHY1,
_CK_USB2PHY2,
+#if !STM32MP21
_CK_USB3DR,
_CK_USB3PCIEPHY,
_CK_USBTC,
+#endif /* !STM32MP21 */
CK_LAST
};
@@ -271,6 +307,7 @@
_CK_FLEXGEN_58, _CK_HSE
};
+#if !STM32MP21
static const uint16_t usb3pciphy_src[] = {
_CK_FLEXGEN_34, _CK_HSE
};
@@ -278,6 +315,7 @@
static const uint16_t d3per_src[] = {
_CK_MSI, _CK_LSI, _CK_LSE
};
+#endif /* !STM32MP21 */
#define MUX_CONF(id, src, _offset, _shift, _witdh)[id] = {\
.id_parents = src,\
@@ -290,7 +328,7 @@
},\
}
-static const struct parent_cfg parent_mp25[] = {
+static const struct parent_cfg parent_mp2[] = {
MUX_CONF(MUX_MUXSEL0, muxsel_src, RCC_MUXSELCFGR, 0, 2),
MUX_CONF(MUX_MUXSEL1, muxsel_src, RCC_MUXSELCFGR, 4, 2),
MUX_CONF(MUX_MUXSEL2, muxsel_src, RCC_MUXSELCFGR, 8, 2),
@@ -303,8 +341,10 @@
MUX_CONF(MUX_RTC, rtc_src, RCC_BDCR, 16, 2),
MUX_CONF(MUX_USB2PHY1, usb2phy1_src, RCC_USB2PHY1CFGR, 15, 1),
MUX_CONF(MUX_USB2PHY2, usb2phy2_src, RCC_USB2PHY2CFGR, 15, 1),
+#if !STM32MP21
MUX_CONF(MUX_USB3PCIEPHY, usb3pciphy_src, RCC_USB3PCIEPHYCFGR, 15, 1),
MUX_CONF(MUX_D3PER, d3per_src, RCC_D3DCR, 16, 2),
+#endif /* !STM32MP21 */
};
/* GATES */
@@ -324,15 +364,26 @@
GATE_SYSRAM,
GATE_RETRAM,
GATE_SRAM1,
+#if !STM32MP21
GATE_SRAM2,
+#endif /* !STM32MP21 */
GATE_DDRPHYC,
GATE_SYSCPU1,
GATE_CRC,
+#if !STM32MP21
GATE_OSPIIOM,
+#endif /* !STM32MP21 */
GATE_BKPSRAM,
+#if STM32MP21
+ GATE_HASH1,
+ GATE_HASH2,
+ GATE_RNG1,
+ GATE_RNG2,
+#else /* STM32MP21 */
GATE_HASH,
GATE_RNG,
+#endif /* STM32MP21 */
GATE_CRYP1,
GATE_CRYP2,
GATE_SAES,
@@ -347,18 +398,27 @@
GATE_GPIOG,
GATE_GPIOH,
GATE_GPIOI,
+#if !STM32MP21
GATE_GPIOJ,
GATE_GPIOK,
+#endif /* !STM32MP21 */
GATE_GPIOZ,
GATE_RTC,
GATE_DDRCP,
/* WARNING 2 CLOCKS FOR ONE GATE */
+#if STM32MP21
+ GATE_USBHOHCI,
+ GATE_USBHEHCI,
+#else /* STM32MP21 */
GATE_USB2OHCI,
GATE_USB2EHCI,
+#endif /* STM32MP21 */
+#if !STM32MP21
GATE_USB3DR,
+#endif /* !STM32MP21 */
GATE_BSEC,
GATE_IWDG1,
@@ -373,22 +433,34 @@
GATE_UART5,
GATE_I2C1,
GATE_I2C2,
+#if !STM32MP23
GATE_I2C3,
+#endif /* !STM32MP23 */
+#if STM32MP25
GATE_I2C5,
GATE_I2C4,
GATE_I2C6,
+#endif /* STM32MP25 */
+#if !STM32MP21
GATE_I2C7,
+#endif /* !STM32MP21 */
GATE_USART1,
GATE_USART6,
GATE_UART7,
+#if STM32MP25
GATE_UART8,
GATE_UART9,
+#endif /* STM32MP25 */
GATE_STGEN,
+#if !STM32MP21
GATE_USB3PCIEPHY,
GATE_USBTC,
GATE_I2C8,
+#endif /* !STM32MP21 */
GATE_OSPI1,
+#if !STM32MP21
GATE_OSPI2,
+#endif /* !STM32MP21 */
GATE_FMC,
GATE_SDMMC1,
GATE_SDMMC2,
@@ -403,30 +475,57 @@
.set_clr = (_offset_clr),\
}
-static const struct gate_cfg gates_mp25[LAST_GATE] = {
+static const struct gate_cfg gates_mp2[LAST_GATE] = {
GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0),
+#if STM32MP21
+ GATE_CFG(GATE_LSI, RCC_LSICR, 0, 0),
+#else /* STM32MP21 */
GATE_CFG(GATE_LSI, RCC_BDCR, 9, 0),
+#endif /* STM32MP21 */
GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0),
GATE_CFG(GATE_HSI, RCC_OCENSETR, 0, 1),
GATE_CFG(GATE_HSE, RCC_OCENSETR, 8, 1),
+#if STM32MP21
+ GATE_CFG(GATE_MSI, RCC_OCENSETR, 2, 0),
+#else /* STM32MP21 */
GATE_CFG(GATE_MSI, RCC_D3DCR, 0, 0),
+#endif /* STM32MP21 */
+#if STM32MP21
+ GATE_CFG(GATE_LSI_RDY, RCC_LSICR, 1, 0),
+#else /* STM32MP21 */
GATE_CFG(GATE_LSI_RDY, RCC_BDCR, 10, 0),
+#endif /* STM32MP21 */
GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0),
+#if STM32MP21
+ GATE_CFG(GATE_MSI_RDY, RCC_OCRDYR, 2, 0),
+#else /* STM32MP21 */
GATE_CFG(GATE_MSI_RDY, RCC_D3DCR, 2, 0),
+#endif /* STM32MP21 */
GATE_CFG(GATE_HSE_RDY, RCC_OCRDYR, 8, 0),
GATE_CFG(GATE_HSI_RDY, RCC_OCRDYR, 0, 0),
GATE_CFG(GATE_SYSRAM, RCC_SYSRAMCFGR, 1, 0),
GATE_CFG(GATE_RETRAM, RCC_RETRAMCFGR, 1, 0),
GATE_CFG(GATE_SRAM1, RCC_SRAM1CFGR, 1, 0),
+#if !STM32MP21
GATE_CFG(GATE_SRAM2, RCC_SRAM2CFGR, 1, 0),
+#endif /* !STM32MP21 */
GATE_CFG(GATE_DDRPHYC, RCC_DDRPHYCAPBCFGR, 1, 0),
GATE_CFG(GATE_SYSCPU1, RCC_SYSCPU1CFGR, 1, 0),
GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0),
+#if !STM32MP21
GATE_CFG(GATE_OSPIIOM, RCC_OSPIIOMCFGR, 1, 0),
+#endif /* !STM32MP21 */
GATE_CFG(GATE_BKPSRAM, RCC_BKPSRAMCFGR, 1, 0),
+#if STM32MP21
+ GATE_CFG(GATE_HASH1, RCC_HASH1CFGR, 1, 0),
+ GATE_CFG(GATE_HASH2, RCC_HASH2CFGR, 1, 0),
+ GATE_CFG(GATE_RNG1, RCC_RNG1CFGR, 1, 0),
+ GATE_CFG(GATE_RNG2, RCC_RNG2CFGR, 1, 0),
+#else /* STM32MP21 */
GATE_CFG(GATE_HASH, RCC_HASHCFGR, 1, 0),
GATE_CFG(GATE_RNG, RCC_RNGCFGR, 1, 0),
+#endif /* STM32MP21 */
GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0),
GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0),
GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0),
@@ -440,16 +539,23 @@
GATE_CFG(GATE_GPIOG, RCC_GPIOGCFGR, 1, 0),
GATE_CFG(GATE_GPIOH, RCC_GPIOHCFGR, 1, 0),
GATE_CFG(GATE_GPIOI, RCC_GPIOICFGR, 1, 0),
+#if !STM32MP21
GATE_CFG(GATE_GPIOJ, RCC_GPIOJCFGR, 1, 0),
GATE_CFG(GATE_GPIOK, RCC_GPIOKCFGR, 1, 0),
+#endif /* !STM32MP21 */
GATE_CFG(GATE_GPIOZ, RCC_GPIOZCFGR, 1, 0),
GATE_CFG(GATE_RTC, RCC_RTCCFGR, 1, 0),
GATE_CFG(GATE_DDRCP, RCC_DDRCPCFGR, 1, 0),
/* WARNING 2 CLOCKS FOR ONE GATE */
+#if STM32MP21
+ GATE_CFG(GATE_USBHOHCI, RCC_USBHCFGR, 1, 0),
+ GATE_CFG(GATE_USBHEHCI, RCC_USBHCFGR, 1, 0),
+#else /* STM32MP21 */
GATE_CFG(GATE_USB2OHCI, RCC_USB2CFGR, 1, 0),
GATE_CFG(GATE_USB2EHCI, RCC_USB2CFGR, 1, 0),
GATE_CFG(GATE_USB3DR, RCC_USB3DRCFGR, 1, 0),
+#endif /* STM32MP21 */
GATE_CFG(GATE_BSEC, RCC_BSECCFGR, 1, 0),
GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0),
GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0),
@@ -461,22 +567,34 @@
GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0),
GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0),
GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0),
+#if !STM32MP23
GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0),
+#endif /* !STM32MP23 */
+#if STM32MP25
GATE_CFG(GATE_I2C5, RCC_I2C5CFGR, 1, 0),
GATE_CFG(GATE_I2C4, RCC_I2C4CFGR, 1, 0),
GATE_CFG(GATE_I2C6, RCC_I2C6CFGR, 1, 0),
+#endif /* STM32MP25 */
+#if !STM32MP21
GATE_CFG(GATE_I2C7, RCC_I2C7CFGR, 1, 0),
+#endif /* !STM32MP21 */
GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0),
GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0),
GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0),
+#if STM32MP25
GATE_CFG(GATE_UART8, RCC_UART8CFGR, 1, 0),
GATE_CFG(GATE_UART9, RCC_UART9CFGR, 1, 0),
+#endif /* STM32MP25 */
GATE_CFG(GATE_STGEN, RCC_STGENCFGR, 1, 0),
+#if !STM32MP21
GATE_CFG(GATE_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 1, 0),
GATE_CFG(GATE_USBTC, RCC_USBTCCFGR, 1, 0),
GATE_CFG(GATE_I2C8, RCC_I2C8CFGR, 1, 0),
+#endif /* !STM32MP21 */
GATE_CFG(GATE_OSPI1, RCC_OSPI1CFGR, 1, 0),
+#if !STM32MP21
GATE_CFG(GATE_OSPI2, RCC_OSPI2CFGR, 1, 0),
+#endif /* !STM32MP21 */
GATE_CFG(GATE_FMC, RCC_FMCCFGR, 1, 0),
GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0),
GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0),
@@ -499,11 +617,14 @@
.bitrdy = _bitrdy,\
}
-static const struct div_cfg dividers_mp25[] = {
+static const struct div_cfg dividers_mp2[] = {
DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 31),
DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 31),
DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 31),
DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 31),
+#if STM32MP21
+ DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 0, apb_div_table, 31),
+#endif /* STM32MP21 */
DIV_CFG(DIV_APBDBG, RCC_APBDBGDIVR, 0, 3, 0, apb_div_table, 31),
DIV_CFG(DIV_LSMCU, RCC_LSMCUDIVR, 0, 1, 0, NULL, 31),
DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, 0),
@@ -520,7 +641,7 @@
NB_OSCILLATOR
};
-static struct clk_oscillator_data stm32mp25_osc_data[] = {
+static struct clk_oscillator_data stm32mp2_osc_data[] = {
OSCILLATOR(OSC_HSI, _CK_HSI, "clk-hsi", GATE_HSI, GATE_HSI_RDY,
NULL, NULL, NULL),
@@ -551,7 +672,7 @@
static const char *clk_stm32_get_oscillator_name(enum stm32_osc id)
{
if (id < NB_OSCILLATOR) {
- return stm32mp25_osc_data[id].name;
+ return stm32mp2_osc_data[id].name;
}
return NULL;
@@ -590,10 +711,12 @@
.reg_pllxcfgr1 = (_reg),\
}
-static const struct stm32_clk_pll stm32mp25_clk_pll[_PLL_NB] = {
+static const struct stm32_clk_pll stm32mp2_clk_pll[_PLL_NB] = {
CLK_PLL_CFG(_PLL1, _CK_PLL1, A35_SS_CHGCLKREQ),
CLK_PLL_CFG(_PLL2, _CK_PLL2, RCC_PLL2CFGR1),
+#if !STM32MP21
CLK_PLL_CFG(_PLL3, _CK_PLL3, RCC_PLL3CFGR1),
+#endif /* !STM32MP21 */
CLK_PLL_CFG(_PLL4, _CK_PLL4, RCC_PLL4CFGR1),
CLK_PLL_CFG(_PLL5, _CK_PLL5, RCC_PLL5CFGR1),
CLK_PLL_CFG(_PLL6, _CK_PLL6, RCC_PLL6CFGR1),
@@ -603,7 +726,7 @@
static const struct stm32_clk_pll *clk_stm32_pll_data(unsigned int idx)
{
- return &stm32mp25_clk_pll[idx];
+ return &stm32mp2_clk_pll[idx];
}
static unsigned long clk_get_pll_fvco(struct stm32_clk_priv *priv,
@@ -958,6 +1081,7 @@
#define RCC_16_MHZ UL(16000000)
#ifdef IMAGE_BL2
+#if !STM32MP21
static int clk_stm32_osc_msi_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate,
unsigned long prate)
{
@@ -982,12 +1106,16 @@
return ret;
}
+#endif /* !STM32MP21 */
#endif /* IMAGE_BL2 */
static unsigned long clk_stm32_osc_msi_recalc_rate(struct stm32_clk_priv *priv,
int id __unused,
unsigned long prate __unused)
{
+#if STM32MP21
+ return RCC_16_MHZ;
+#else /* STM32MP21 */
uintptr_t address = priv->base + RCC_BDCR;
if ((mmio_read_32(address) & RCC_BDCR_MSIFREQSEL) == 0U) {
@@ -995,6 +1123,7 @@
} else {
return RCC_16_MHZ;
}
+#endif /* STM32MP21 */
}
static const struct stm32_clk_ops clk_stm32_osc_msi_ops = {
@@ -1039,10 +1168,10 @@
STM32_OSC_MSI_OPS,
STM32_RTC_OPS,
- MP25_LAST_OPS
+ MP2_LAST_OPS
};
-static const struct stm32_clk_ops *ops_array_mp25[MP25_LAST_OPS] = {
+static const struct stm32_clk_ops *ops_array_mp2[MP2_LAST_OPS] = {
[NO_OPS] = NULL,
[FIXED_FACTOR_OPS] = &clk_fixed_factor_ops,
[GATE_OPS] = &clk_gate_ops,
@@ -1061,7 +1190,7 @@
[STM32_RTC_OPS] = &clk_stm32_rtc_ops
};
-static const struct clk_stm32 stm32mp25_clk[CK_LAST] = {
+static const struct clk_stm32 stm32mp2_clk[CK_LAST] = {
CLK_FIXED_RATE(_CK_0_MHZ, _NO_ID, RCC_0_MHZ),
/* ROOT CLOCKS */
@@ -1081,7 +1210,9 @@
CLK_PLL1(_CK_PLL1, PLL1_CK, MUX(MUX_MUXSEL5), _PLL1, 0),
CLK_PLL(_CK_PLL2, PLL2_CK, MUX(MUX_MUXSEL6), _PLL2, 0),
+#if !STM32MP21
CLK_PLL(_CK_PLL3, PLL3_CK, MUX(MUX_MUXSEL7), _PLL3, 0),
+#endif /* !STM32MP21 */
CLK_PLL(_CK_PLL4, PLL4_CK, MUX(MUX_MUXSEL0), _PLL4, 0),
CLK_PLL(_CK_PLL5, PLL5_CK, MUX(MUX_MUXSEL1), _PLL5, 0),
CLK_PLL(_CK_PLL6, PLL6_CK, MUX(MUX_MUXSEL2), _PLL6, 0),
@@ -1158,21 +1289,35 @@
STM32_DIV(_CK_ICN_APB2, CK_ICN_APB2, _CK_ICN_LS_MCU, 0, DIV_APB2),
STM32_DIV(_CK_ICN_APB3, CK_ICN_APB3, _CK_ICN_LS_MCU, 0, DIV_APB3),
STM32_DIV(_CK_ICN_APB4, CK_ICN_APB4, _CK_ICN_LS_MCU, 0, DIV_APB4),
+#if STM32MP21
+ STM32_DIV(_CK_ICN_APB5, CK_ICN_APB5, _CK_ICN_LS_MCU, 0, DIV_APB5),
+#endif /* STM32MP21 */
STM32_DIV(_CK_ICN_APBDBG, CK_ICN_APBDBG, _CK_ICN_LS_MCU, 0, DIV_APBDBG),
/* KERNEL CLOCK */
STM32_GATE(_CK_SYSRAM, CK_BUS_SYSRAM, _CK_ICN_HS_MCU, 0, GATE_SYSRAM),
STM32_GATE(_CK_RETRAM, CK_BUS_RETRAM, _CK_ICN_HS_MCU, 0, GATE_RETRAM),
STM32_GATE(_CK_SRAM1, CK_BUS_SRAM1, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM1),
+#if !STM32MP21
STM32_GATE(_CK_SRAM2, CK_BUS_SRAM2, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM2),
+#endif /* !STM32MP21 */
STM32_GATE(_CK_DDRPHYC, CK_BUS_DDRPHYC, _CK_ICN_LS_MCU, 0, GATE_DDRPHYC),
STM32_GATE(_CK_SYSCPU1, CK_BUS_SYSCPU1, _CK_ICN_LS_MCU, 0, GATE_SYSCPU1),
STM32_GATE(_CK_CRC, CK_BUS_CRC, _CK_ICN_LS_MCU, 0, GATE_CRC),
+#if !STM32MP21
STM32_GATE(_CK_OSPIIOM, CK_BUS_OSPIIOM, _CK_ICN_LS_MCU, 0, GATE_OSPIIOM),
+#endif /* !STM32MP21 */
STM32_GATE(_CK_BKPSRAM, CK_BUS_BKPSRAM, _CK_ICN_LS_MCU, 0, GATE_BKPSRAM),
+#if STM32MP21
+ STM32_GATE(_CK_HASH1, CK_BUS_HASH1, _CK_ICN_LS_MCU, 0, GATE_HASH1),
+ STM32_GATE(_CK_HASH2, CK_BUS_HASH2, _CK_ICN_LS_MCU, 0, GATE_HASH2),
+ STM32_GATE(_CK_RNG1, CK_BUS_RNG1, _CK_ICN_LS_MCU, 0, GATE_RNG1),
+ STM32_GATE(_CK_RNG2, CK_BUS_RNG2, _CK_ICN_LS_MCU, 0, GATE_RNG2),
+#else /* STM32MP21 */
STM32_GATE(_CK_HASH, CK_BUS_HASH, _CK_ICN_LS_MCU, 0, GATE_HASH),
STM32_GATE(_CK_RNG, CK_BUS_RNG, _CK_ICN_LS_MCU, 0, GATE_RNG),
+#endif /* STM32MP21 */
STM32_GATE(_CK_CRYP1, CK_BUS_CRYP1, _CK_ICN_LS_MCU, 0, GATE_CRYP1),
STM32_GATE(_CK_CRYP2, CK_BUS_CRYP2, _CK_ICN_LS_MCU, 0, GATE_CRYP2),
STM32_GATE(_CK_SAES, CK_BUS_SAES, _CK_ICN_LS_MCU, 0, GATE_SAES),
@@ -1187,18 +1332,27 @@
STM32_GATE(_CK_GPIOG, CK_BUS_GPIOG, _CK_ICN_LS_MCU, 0, GATE_GPIOG),
STM32_GATE(_CK_GPIOH, CK_BUS_GPIOH, _CK_ICN_LS_MCU, 0, GATE_GPIOH),
STM32_GATE(_CK_GPIOI, CK_BUS_GPIOI, _CK_ICN_LS_MCU, 0, GATE_GPIOI),
+#if !STM32MP21
STM32_GATE(_CK_GPIOJ, CK_BUS_GPIOJ, _CK_ICN_LS_MCU, 0, GATE_GPIOJ),
STM32_GATE(_CK_GPIOK, CK_BUS_GPIOK, _CK_ICN_LS_MCU, 0, GATE_GPIOK),
+#endif /* !STM32MP21 */
STM32_GATE(_CK_GPIOZ, CK_BUS_GPIOZ, _CK_ICN_LS_MCU, 0, GATE_GPIOZ),
STM32_GATE(_CK_RTC, CK_BUS_RTC, _CK_ICN_LS_MCU, 0, GATE_RTC),
STM32_GATE(_CK_DDRCP, CK_BUS_DDR, _CK_ICN_DDR, 0, GATE_DDRCP),
/* WARNING 2 CLOCKS FOR ONE GATE */
+#if STM32MP21
+ STM32_GATE(_CK_USBHOHCI, CK_BUS_USBHOHCI, _CK_ICN_HSL, 0, GATE_USBHOHCI),
+ STM32_GATE(_CK_USBHEHCI, CK_BUS_USBHEHCI, _CK_ICN_HSL, 0, GATE_USBHEHCI),
+#else /* STM32MP21 */
STM32_GATE(_CK_USB2OHCI, CK_BUS_USB2OHCI, _CK_ICN_HSL, 0, GATE_USB2OHCI),
STM32_GATE(_CK_USB2EHCI, CK_BUS_USB2EHCI, _CK_ICN_HSL, 0, GATE_USB2EHCI),
+#endif /* STM32MP21 */
+#if !STM32MP21
STM32_GATE(_CK_USB3DR, CK_BUS_USB3DR, _CK_ICN_HSL, 0, GATE_USB3DR),
+#endif /* !STM32MP21 */
STM32_GATE(_CK_BSEC, CK_BUS_BSEC, _CK_ICN_APB3, 0, GATE_BSEC),
STM32_GATE(_CK_IWDG1, CK_BUS_IWDG1, _CK_ICN_APB3, 0, GATE_IWDG1),
@@ -1211,24 +1365,41 @@
STM32_GATE(_CK_UART4, CK_KER_UART4, _CK_FLEXGEN_08, 0, GATE_UART4),
STM32_GATE(_CK_USART3, CK_KER_USART3, _CK_FLEXGEN_09, 0, GATE_USART3),
STM32_GATE(_CK_UART5, CK_KER_UART5, _CK_FLEXGEN_09, 0, GATE_UART5),
+#if STM32MP21
+ STM32_GATE(_CK_I2C1, CK_KER_I2C1, _CK_FLEXGEN_13, 0, GATE_I2C1),
+ STM32_GATE(_CK_I2C2, CK_KER_I2C2, _CK_FLEXGEN_13, 0, GATE_I2C2),
+ STM32_GATE(_CK_USART1, CK_KER_USART1, _CK_FLEXGEN_18, 0, GATE_USART1),
+ STM32_GATE(_CK_USART6, CK_KER_USART6, _CK_FLEXGEN_19, 0, GATE_USART6),
+ STM32_GATE(_CK_UART7, CK_KER_UART7, _CK_FLEXGEN_20, 0, GATE_UART7),
+ STM32_GATE(_CK_I2C3, CK_KER_I2C3, _CK_FLEXGEN_38, 0, GATE_I2C3),
+#else /* STM32MP21 */
STM32_GATE(_CK_I2C1, CK_KER_I2C1, _CK_FLEXGEN_12, 0, GATE_I2C1),
STM32_GATE(_CK_I2C2, CK_KER_I2C2, _CK_FLEXGEN_12, 0, GATE_I2C2),
+#if STM32MP25
STM32_GATE(_CK_I2C3, CK_KER_I2C3, _CK_FLEXGEN_13, 0, GATE_I2C3),
STM32_GATE(_CK_I2C5, CK_KER_I2C5, _CK_FLEXGEN_13, 0, GATE_I2C5),
STM32_GATE(_CK_I2C4, CK_KER_I2C4, _CK_FLEXGEN_14, 0, GATE_I2C4),
STM32_GATE(_CK_I2C6, CK_KER_I2C6, _CK_FLEXGEN_14, 0, GATE_I2C6),
+#endif /* STM32MP25 */
STM32_GATE(_CK_I2C7, CK_KER_I2C7, _CK_FLEXGEN_15, 0, GATE_I2C7),
STM32_GATE(_CK_USART1, CK_KER_USART1, _CK_FLEXGEN_19, 0, GATE_USART1),
STM32_GATE(_CK_USART6, CK_KER_USART6, _CK_FLEXGEN_20, 0, GATE_USART6),
STM32_GATE(_CK_UART7, CK_KER_UART7, _CK_FLEXGEN_21, 0, GATE_UART7),
+#if STM32MP25
STM32_GATE(_CK_UART8, CK_KER_UART8, _CK_FLEXGEN_21, 0, GATE_UART8),
STM32_GATE(_CK_UART9, CK_KER_UART9, _CK_FLEXGEN_22, 0, GATE_UART9),
+#endif /* STM32MP25 */
+#endif /* STM32MP21 */
STM32_GATE(_CK_STGEN, CK_KER_STGEN, _CK_FLEXGEN_33, 0, GATE_STGEN),
+#if !STM32MP21
STM32_GATE(_CK_USB3PCIEPHY, CK_KER_USB3PCIEPHY, _CK_FLEXGEN_34, 0, GATE_USB3PCIEPHY),
STM32_GATE(_CK_USBTC, CK_KER_USBTC, _CK_FLEXGEN_35, 0, GATE_USBTC),
STM32_GATE(_CK_I2C8, CK_KER_I2C8, _CK_FLEXGEN_38, 0, GATE_I2C8),
+#endif /* !STM32MP21 */
STM32_GATE(_CK_OSPI1, CK_KER_OSPI1, _CK_FLEXGEN_48, 0, GATE_OSPI1),
+#if !STM32MP21
STM32_GATE(_CK_OSPI2, CK_KER_OSPI2, _CK_FLEXGEN_49, 0, GATE_OSPI2),
+#endif /* !STM32MP21 */
STM32_GATE(_CK_FMC, CK_KER_FMC, _CK_FLEXGEN_50, 0, GATE_FMC),
STM32_GATE(_CK_SDMMC1, CK_KER_SDMMC1, _CK_FLEXGEN_51, 0, GATE_SDMMC1),
STM32_GATE(_CK_SDMMC2, CK_KER_SDMMC2, _CK_FLEXGEN_52, 0, GATE_SDMMC2),
@@ -1240,7 +1411,9 @@
CLKSRC_CA35SS,
CLKSRC_PLL1,
CLKSRC_PLL2,
+#if !STM32MP21
CLKSRC_PLL3,
+#endif /* !STM32MP21 */
CLKSRC_PLL4,
CLKSRC_PLL5,
CLKSRC_PLL6,
@@ -1656,6 +1829,11 @@
int err;
for (i = _PLL1; i < _PLL_NB; i++) {
+#if STM32MP21
+ if (i == _PLL3) {
+ continue;
+ }
+#endif
err = clk_stm32_pll_init(priv, i);
if (err) {
return err;
@@ -1886,6 +2064,7 @@
static void stm32_enable_oscillator_msi(struct stm32_clk_priv *priv)
{
+#if !STM32MP21
struct stm32_clk_platdata *pdata = priv->pdata;
struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_MSI];
int err;
@@ -1896,6 +2075,7 @@
osci->freq / 1000000U);
panic();
}
+#endif /* !STM32MP21 */
_clk_stm32_enable(priv, _CK_MSI);
}
@@ -2204,6 +2384,11 @@
int subnode = 0;
int err = 0;
+#if STM32MP21
+ if (i == _PLL3) {
+ continue;
+ }
+#endif
snprintf(name, sizeof(name), "st,pll-%u", i + 1);
subnode = fdt_subnode_offset(fdt, node, name);
@@ -2266,49 +2451,53 @@
}
#endif /* IMAGE_BL2 */
-static struct stm32_osci_dt_cfg mp25_osci[NB_OSCILLATOR];
+static struct stm32_osci_dt_cfg mp2_osci[NB_OSCILLATOR];
-static struct stm32_pll_dt_cfg mp25_pll[_PLL_NB];
+static struct stm32_pll_dt_cfg mp2_pll[_PLL_NB];
#define DT_FLEXGEN_CLK_MAX 64
-static uint32_t mp25_flexgen[DT_FLEXGEN_CLK_MAX];
+static uint32_t mp2_flexgen[DT_FLEXGEN_CLK_MAX];
+#if STM32MP21
+#define DT_BUS_CLK_MAX 7
+#else /* STM32MP21 */
#define DT_BUS_CLK_MAX 6
-static uint32_t mp25_busclk[DT_BUS_CLK_MAX];
+#endif /* STM32MP21 */
+static uint32_t mp2_busclk[DT_BUS_CLK_MAX];
#define DT_KERNEL_CLK_MAX 20
-static uint32_t mp25_kernelclk[DT_KERNEL_CLK_MAX];
+static uint32_t mp2_kernelclk[DT_KERNEL_CLK_MAX];
-static struct stm32_clk_platdata stm32mp25_pdata = {
- .osci = mp25_osci,
+static struct stm32_clk_platdata stm32mp2_pdata = {
+ .osci = mp2_osci,
.nosci = NB_OSCILLATOR,
- .pll = mp25_pll,
+ .pll = mp2_pll,
.npll = _PLL_NB,
- .flexgen = mp25_flexgen,
+ .flexgen = mp2_flexgen,
.nflexgen = DT_FLEXGEN_CLK_MAX,
- .busclk = mp25_busclk,
+ .busclk = mp2_busclk,
.nbusclk = DT_BUS_CLK_MAX,
- .kernelclk = mp25_kernelclk,
+ .kernelclk = mp2_kernelclk,
.nkernelclk = DT_KERNEL_CLK_MAX,
};
-static uint8_t refcounts_mp25[CK_LAST];
+static uint8_t refcounts_mp2[CK_LAST];
-static struct stm32_clk_priv stm32mp25_clock_data = {
+static struct stm32_clk_priv stm32mp2_clock_data = {
.base = RCC_BASE,
- .num = ARRAY_SIZE(stm32mp25_clk),
- .clks = stm32mp25_clk,
- .parents = parent_mp25,
- .nb_parents = ARRAY_SIZE(parent_mp25),
- .gates = gates_mp25,
- .nb_gates = ARRAY_SIZE(gates_mp25),
- .div = dividers_mp25,
- .nb_div = ARRAY_SIZE(dividers_mp25),
- .osci_data = stm32mp25_osc_data,
- .nb_osci_data = ARRAY_SIZE(stm32mp25_osc_data),
- .gate_refcounts = refcounts_mp25,
- .pdata = &stm32mp25_pdata,
- .ops_array = ops_array_mp25,
+ .num = ARRAY_SIZE(stm32mp2_clk),
+ .clks = stm32mp2_clk,
+ .parents = parent_mp2,
+ .nb_parents = ARRAY_SIZE(parent_mp2),
+ .gates = gates_mp2,
+ .nb_gates = ARRAY_SIZE(gates_mp2),
+ .div = dividers_mp2,
+ .nb_div = ARRAY_SIZE(dividers_mp2),
+ .osci_data = stm32mp2_osc_data,
+ .nb_osci_data = ARRAY_SIZE(stm32mp2_osc_data),
+ .gate_refcounts = refcounts_mp2,
+ .pdata = &stm32mp2_pdata,
+ .ops_array = ops_array_mp2,
};
int stm32mp2_clk_init(void)
@@ -2317,13 +2506,13 @@
int ret;
#ifdef IMAGE_BL2
- ret = stm32_clk_parse_fdt(&stm32mp25_pdata);
+ ret = stm32_clk_parse_fdt(&stm32mp2_pdata);
if (ret != 0) {
return ret;
}
#endif
- ret = clk_stm32_init(&stm32mp25_clock_data, base);
+ ret = clk_stm32_init(&stm32mp2_clock_data, base);
if (ret != 0) {
return ret;
}
diff --git a/drivers/st/ddr/stm32mp_ddr.c b/drivers/st/ddr/stm32mp_ddr.c
index df2cd83..4aa5c73 100644
--- a/drivers/st/ddr/stm32mp_ddr.c
+++ b/drivers/st/ddr/stm32mp_ddr.c
@@ -44,7 +44,7 @@
ddr_registers[type].name, i);
panic();
} else {
-#if !STM32MP13 && !STM32MP15
+#ifdef STM32MP2X
if (desc[i].qd) {
stm32mp_ddr_start_sw_done(priv->ctl);
}
@@ -52,7 +52,7 @@
value = *((uint32_t *)((uintptr_t)param +
desc[i].par_offset));
mmio_write_32(ptr, value);
-#if !STM32MP13 && !STM32MP15
+#ifdef STM32MP2X
if (desc[i].qd) {
stm32mp_ddr_wait_sw_done_ack(priv->ctl);
}
diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c
index 44d7c09..2d64de3 100644
--- a/drivers/st/gpio/stm32_gpio.c
+++ b/drivers/st/gpio/stm32_gpio.c
@@ -282,7 +282,7 @@
clk_disable(clock);
-#if STM32MP13 || STM32MP15
+#ifdef STM32MP1X
if (status == DT_SECURE) {
stm32mp_register_secure_gpio(bank, pin);
#if !IMAGE_BL2
diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c
index 66988d7..e07d9e7 100644
--- a/drivers/st/mmc/stm32_sdmmc2.c
+++ b/drivers/st/mmc/stm32_sdmmc2.c
@@ -129,7 +129,7 @@
#define DT_SDMMC2_COMPAT "st,stm32-sdmmc2"
#endif
-#if STM32MP13 || STM32MP15
+#ifdef STM32MP1X
#define SDMMC_FIFO_SIZE 64U
#else
#define SDMMC_FIFO_SIZE 1024U
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index e8c4054..b607945 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -91,6 +91,17 @@
#define SERROR_EXCEPTION 0x180
/*******************************************************************************
+ * Encodings for GICv5 EL3 system registers
+ ******************************************************************************/
+#define ICC_PPI_DOMAINR0_EL3 S3_6_C12_C8_4
+#define ICC_PPI_DOMAINR1_EL3 S3_6_C12_C8_5
+#define ICC_PPI_DOMAINR2_EL3 S3_6_C12_C8_6
+#define ICC_PPI_DOMAINR3_EL3 S3_6_C12_C8_7
+
+#define ICC_PPI_DOMAINR_FIELD_MASK ULL(0x3)
+#define ICC_PPI_DOMAINR_COUNT (32)
+
+/*******************************************************************************
* Definitions for CPU system register interface to GICv3
******************************************************************************/
#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
@@ -504,6 +515,11 @@
#define SME2_IMPLEMENTED ULL(0x2)
#define SME_NOT_IMPLEMENTED ULL(0x0)
+/* ID_AA64PFR2_EL1 definitions */
+#define ID_AA64PFR2_EL1 S3_0_C0_C4_2
+#define ID_AA64PFR2_EL1_GCIE_SHIFT 12
+#define ID_AA64PFR2_EL1_GCIE_MASK ULL(0xf)
+
/* ID_PFR1_EL1 definitions */
#define ID_PFR1_VIRTEXT_SHIFT U(12)
#define ID_PFR1_VIRTEXT_MASK U(0xf)
@@ -620,7 +636,11 @@
#define CPACR_EL1_SMEN_MASK ULL(0x3)
/* SCR definitions */
+#if ENABLE_FEAT_GCIE
+#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5) | SCR_FIQ_BIT)
+#else
#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
+#endif
#define SCR_NSE_SHIFT U(62)
#define SCR_FGTEN2_BIT (UL(1) << 59)
#define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT)
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 757ce06..77355cd 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -520,4 +520,11 @@
CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU)
+/*************************************************************************
+ * Function to identify the presence of FEAT_GCIE (GICv5 CPU interface
+ * extension).
+ ************************************************************************/
+CREATE_FEATURE_FUNCS(feat_gcie, id_aa64pfr2_el1, ID_AA64PFR2_EL1_GCIE_SHIFT,
+ ID_AA64PFR2_EL1_GCIE_MASK, 1U, ENABLE_FEAT_GCIE)
+
#endif /* ARCH_FEATURES_H */
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index c885424..a59c531 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -559,6 +559,12 @@
DEFINE_SYSREG_RW_FUNCS(dacr32_el2)
DEFINE_SYSREG_RW_FUNCS(ifsr32_el2)
+/* GICv5 System Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr0_el3, ICC_PPI_DOMAINR0_EL3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr1_el3, ICC_PPI_DOMAINR1_EL3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr2_el3, ICC_PPI_DOMAINR2_EL3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr3_el3, ICC_PPI_DOMAINR3_EL3)
+
/* GICv3 System Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h
index 8b9dfb6..e228495 100644
--- a/include/bl31/interrupt_mgmt.h
+++ b/include/bl31/interrupt_mgmt.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,7 +16,8 @@
#define INTR_TYPE_S_EL1 U(0)
#define INTR_TYPE_EL3 U(1)
#define INTR_TYPE_NS U(2)
-#define MAX_INTR_TYPES U(3)
+#define INTR_TYPE_RL U(3)
+#define MAX_INTR_TYPES U(4)
#define INTR_TYPE_INVAL MAX_INTR_TYPES
/* Interrupt routing modes */
diff --git a/include/drivers/arm/gicv5.h b/include/drivers/arm/gicv5.h
new file mode 100644
index 0000000..d01d24b
--- /dev/null
+++ b/include/drivers/arm/gicv5.h
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GICV5_H
+#define GICV5_H
+
+#ifndef __ASSEMBLER__
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <lib/mmio.h>
+#endif
+
+#include <lib/utils_def.h>
+
+/* Interrupt Domain definitions */
+#define INTDMN_S 0
+#define INTDMN_NS 1
+#define INTDMN_EL3 2
+#define INTDMN_RL 3
+
+/* Trigger modes */
+#define TM_EDGE 0
+#define TM_LEVEL 1
+
+/* Architected PPI numbers */
+#define PPI_TRBIRQ 31
+#define PPI_CNTP 30
+#define PPI_CNTPS 29
+#define PPI_CNTHV 28
+#define PPI_CNTV 27
+#define PPI_CNTHP 26
+#define PPI_GICMNT 25
+#define PPI_CTIIRQ 24
+#define PPI_PMUIRQ 23
+#define PPI_COMMIRQ 22
+#define PPI_PMBIRQ 21
+#define PPI_CNTHPS 20
+#define PPI_CNTHVS 19
+#define PPI_DB_NS 2
+#define PPI_DB_RL 1
+#define PPI_DB_S 0
+
+/* Register fields common to all IRI components.
+ * They have the same name and offset in every config frame */
+#define IRI_AIDR_COMPONENT_SHIFT 8
+#define IRI_AIDR_COMPONENT_WIDTH 4
+#define IRI_AIDR_COMPONENT_IRS 0
+#define IRI_AIDR_COMPONENT_ITS 1
+#define IRI_AIDR_COMPONENT_IWB 2
+#define IRI_AIDR_ARCH_MAJOR_SHIFT 4
+#define IRI_AIDR_ARCH_MAJOR_WIDTH 4
+#define IRI_AIDR_ARCH_MAJOR_V5 0
+#define IRI_AIDR_ARCH_MINOR_SHIFT 0
+#define IRI_AIDR_ARCH_MINOR_WIDTH 4
+#define IRI_AIDR_ARCH_MINOR_P0 0
+
+/* IRS register fields */
+#define IRS_IDR6_SPI_IRS_RANGE_SHIFT 0
+#define IRS_IDR6_SPI_IRS_RANGE_WIDTH 24
+#define IRS_IDR7_SPI_BASE_SHIFT 0
+#define IRS_IDR7_SPI_BASE_WIDTH 24
+
+#define IRS_SPI_STATUSR_IDLE_BIT BIT(0)
+#define IRS_SPI_STATUSR_V_BIT BIT(1)
+
+/* IWB register fields */
+#define IWB_IDR0_DOMAINS_SHIFT 11
+#define IWB_IDR0_DOMAINS_WIDTH 4
+#define IWB_IDR0_IWRANGE_SHIFT 0
+#define IWB_IDR0_IWRANGE_WIDTH 10
+
+#define IWB_CR0_IWBEN_BIT BIT(0)
+#define IWB_CR0_IDLE_BIT BIT(1)
+
+#define IWB_WENABLE_STATUSR_IDLE_BIT BIT(0)
+#define IWB_WDOMAIN_STATUSR_IDLE_BIT BIT(0)
+
+#define IWB_WDOMAINR_DOMAINX_MASK 0x3
+
+#ifndef __ASSEMBLER__
+
+#define _PPI_FIELD_SHIFT(_REG, _ppi_id) \
+ ((_ppi_id % (ICC_PPI_##_REG##_COUNT)) * (64 / ICC_PPI_##_REG##_COUNT))
+
+#define write_icc_ppi_domainr(_var, _ppi_id, _value) \
+ do { \
+ _var |= (uint64_t)_value << _PPI_FIELD_SHIFT(DOMAINR, _ppi_id);\
+ } while (false)
+
+
+#define DEFINE_GICV5_MMIO_WRITE_FUNC(_name, _offset) \
+static inline void write_##_name(uintptr_t base, uint32_t val) \
+{ \
+ mmio_write_32(base + _offset, val); \
+}
+
+#define DEFINE_GICV5_MMIO_READ_FUNC(_name, _offset) \
+static inline uint32_t read_##_name(uintptr_t base) \
+{ \
+ return mmio_read_32(base + _offset); \
+}
+
+#define DEFINE_GICV5_MMIO_WRITE_INDEXED_FUNC(_name, _offset) \
+static inline void write_##_name(uintptr_t base, uint16_t index, uint32_t val) \
+{ \
+ mmio_write_32(base + _offset + (index * sizeof(uint32_t)), val); \
+}
+
+#define DEFINE_GICV5_MMIO_READ_INDEXED_FUNC(_name, _offset) \
+static inline uint32_t read_##_name(uintptr_t base, uint16_t index) \
+{ \
+ return mmio_read_32(base + _offset + (index * sizeof(uint32_t))); \
+}
+
+#define DEFINE_GICV5_MMIO_RW_FUNCS(_name, _offset) \
+ DEFINE_GICV5_MMIO_READ_FUNC(_name, _offset) \
+ DEFINE_GICV5_MMIO_WRITE_FUNC(_name, _offset)
+
+#define DEFINE_GICV5_MMIO_RW_INDEXED_FUNCS(_name, _offset) \
+ DEFINE_GICV5_MMIO_READ_INDEXED_FUNC(_name, _offset) \
+ DEFINE_GICV5_MMIO_WRITE_INDEXED_FUNC(_name, _offset)
+
+DEFINE_GICV5_MMIO_READ_FUNC(iri_aidr, 0x44)
+
+DEFINE_GICV5_MMIO_READ_FUNC(iwb_idr0, 0x00)
+DEFINE_GICV5_MMIO_RW_FUNCS( iwb_cr0, 0x80)
+DEFINE_GICV5_MMIO_READ_FUNC(iwb_wenable_statusr, 0xc0)
+DEFINE_GICV5_MMIO_READ_FUNC(iwb_wdomain_statusr, 0xc4)
+DEFINE_GICV5_MMIO_RW_INDEXED_FUNCS(iwb_wenabler, 0x2000)
+DEFINE_GICV5_MMIO_RW_INDEXED_FUNCS(iwb_wtmr, 0x4000)
+DEFINE_GICV5_MMIO_RW_INDEXED_FUNCS(iwb_wdomainr, 0x6000)
+
+DEFINE_GICV5_MMIO_READ_FUNC(irs_idr6, 0x0018)
+DEFINE_GICV5_MMIO_READ_FUNC(irs_idr7, 0x001c)
+DEFINE_GICV5_MMIO_RW_FUNCS( irs_spi_selr, 0x0108)
+DEFINE_GICV5_MMIO_RW_FUNCS( irs_spi_domainr, 0x010c)
+DEFINE_GICV5_MMIO_RW_FUNCS( irs_spi_cfgr, 0x0114)
+DEFINE_GICV5_MMIO_READ_FUNC(irs_spi_statusr, 0x0118)
+
+#define WAIT_FOR_IDLE(base, reg, reg_up) \
+ do { \
+ while ((read_##reg(base) & reg_up##_IDLE_BIT) == 0U) {} \
+ } while (0)
+
+/* wait for IDLE but also check the V bit was set */
+#define WAIT_FOR_VIDLE(base, reg, reg_up) \
+ do { \
+ uint32_t val; \
+ while (((val = read_##reg(base)) & reg_up##_IDLE_BIT) == 0U) {} \
+ assert((val & reg##_V_BIT) != 0U); \
+ } while (0)
+
+#define WAIT_FOR_VIDLE_IRS_SPI_STATUSR(base) \
+ WAIT_FOR_IDLE(base, irs_spi_statusr, IRS_SPI_STATUSR)
+
+#define WAIT_FOR_IDLE_IWB_WENABLE_STATUSR(base) \
+ WAIT_FOR_IDLE(base, iwb_wenable_statusr, IWB_WENABLE_STATUSR)
+#define WAIT_FOR_IDLE_IWB_WDOMAIN_STATUSR(base) \
+ WAIT_FOR_IDLE(base, iwb_wdomain_statusr, IWB_WDOMAIN_STATUSR)
+#define WAIT_FOR_IDLE_IWB_CR0(base) \
+ WAIT_FOR_IDLE(base, iwb_cr0, IWB_CR0)
+
+#define WIRE_PROP_DESC(_id, _domain, _tm) \
+ { \
+ .id = (_id), \
+ .domain = (_domain), \
+ .tm = (_tm), \
+ }
+
+struct gicv5_wire_props {
+ /* continuous wire ID as seen by the attached component */
+ uint32_t id;
+ /* use the INTDMN_XYZ macros */
+ uint8_t domain:2;
+ /* use the TM_XYZ (eg. TM_EDGE) macros */
+ uint8_t tm:1;
+};
+
+/* to describe every IRS in the system */
+struct gicv5_irs {
+ /* mapped device nGnRnE by the platform*/
+ uintptr_t el3_config_frame;
+ struct gicv5_wire_props *spis;
+ uint32_t num_spis;
+};
+
+/*
+ * to describe every IWB in the system where EL3 is the MPPAS. IWBs that have
+ * another world as an MPPAS need not be included
+ */
+struct gicv5_iwb {
+ /* mapped device nGnRnE by the platform*/
+ uintptr_t config_frame;
+ struct gicv5_wire_props *wires;
+ uint32_t num_wires;
+};
+
+struct gicv5_driver_data {
+ struct gicv5_irs *irss;
+ struct gicv5_iwb *iwbs;
+ uint32_t num_irss;
+ uint32_t num_iwbs;
+};
+
+extern const struct gicv5_driver_data plat_gicv5_driver_data;
+
+void gicv5_driver_init();
+uint8_t gicv5_get_pending_interrupt_type(void);
+bool gicv5_has_interrupt_type(unsigned int type);
+void gicv5_enable_ppis();
+#endif /* __ASSEMBLER__ */
+#endif /* GICV5_H */
diff --git a/include/drivers/st/stm32mp21_pwr.h b/include/drivers/st/stm32mp21_pwr.h
new file mode 100644
index 0000000..570f079
--- /dev/null
+++ b/include/drivers/st/stm32mp21_pwr.h
@@ -0,0 +1,416 @@
+/*
+ * Copyright (c) 2025, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP21_PWR_H
+#define STM32MP21_PWR_H
+
+#include <lib/utils_def.h>
+
+#define PWR_CR1 U(0x00)
+#define PWR_CR2 U(0x04)
+#define PWR_CR3 U(0x08)
+#define PWR_CR7 U(0x18)
+#define PWR_CR8 U(0x1C)
+#define PWR_CR9 U(0x20)
+#define PWR_CR10 U(0x24)
+#define PWR_CR11 U(0x28)
+#define PWR_BDCR U(0x38)
+#define PWR_CPU1CR U(0x40)
+#define PWR_CPU2CR U(0x44)
+#define PWR_D1CR U(0x4C)
+#define PWR_D2CR U(0x50)
+#define PWR_WKUPCR1 U(0x60)
+#define PWR_WKUPCR2 U(0x64)
+#define PWR_WKUPCR3 U(0x68)
+#define PWR_WKUPCR4 U(0x6C)
+#define PWR_WKUPCR5 U(0x70)
+#define PWR_WKUPCR6 U(0x74)
+#define PWR_RSECCFGR U(0x100)
+#define PWR_RPRIVCFGR U(0x104)
+#define PWR_R0CIDCFGR U(0x108)
+#define PWR_R1CIDCFGR U(0x10C)
+#define PWR_R2CIDCFGR U(0x110)
+#define PWR_R3CIDCFGR U(0x114)
+#define PWR_R4CIDCFGR U(0x118)
+#define PWR_R5CIDCFGR U(0x11C)
+#define PWR_R6CIDCFGR U(0x120)
+#define PWR_WIOSECCFGR U(0x180)
+#define PWR_WIOPRIVCFGR U(0x184)
+#define PWR_WIO1CIDCFGR U(0x188)
+#define PWR_WIO1SEMCR U(0x18C)
+#define PWR_WIO2CIDCFGR U(0x190)
+#define PWR_WIO2SEMCR U(0x194)
+#define PWR_WIO3CIDCFGR U(0x198)
+#define PWR_WIO3SEMCR U(0x19C)
+#define PWR_WIO4CIDCFGR U(0x1A0)
+#define PWR_WIO4SEMCR U(0x1A4)
+#define PWR_WIO5CIDCFGR U(0x1A8)
+#define PWR_WIO5SEMCR U(0x1AC)
+#define PWR_WIO6CIDCFGR U(0x1B0)
+#define PWR_WIO6SEMCR U(0x1B4)
+#define PWR_CPU1D1SR U(0x200)
+#define PWR_CPU2D2SR U(0x204)
+#define PWR_DBGR U(0x308)
+#define PWR_VERR U(0x3F4)
+#define PWR_IPIDR U(0x3F8)
+#define PWR_SIDR U(0x3FC)
+
+/* PWR_CR1 register fields */
+#define PWR_CR1_VDDIO3VMEN BIT(0)
+#define PWR_CR1_USB33VMEN BIT(2)
+#define PWR_CR1_AVMEN BIT(4)
+#define PWR_CR1_VDDIO3SV BIT(8)
+#define PWR_CR1_USB33SV BIT(10)
+#define PWR_CR1_ASV BIT(12)
+#define PWR_CR1_VDDIO3RDY BIT(16)
+#define PWR_CR1_USB33RDY BIT(18)
+#define PWR_CR1_ARDY BIT(20)
+#define PWR_CR1_VDDIOVRSEL BIT(24)
+#define PWR_CR1_VDDIO3VRSEL BIT(25)
+#define PWR_CR1_GPVMO BIT(31)
+
+/* PWR_CR2 register fields */
+#define PWR_CR2_MONEN BIT(0)
+#define PWR_CR2_VBATL BIT(8)
+#define PWR_CR2_VBATH BIT(9)
+#define PWR_CR2_TEMPL BIT(10)
+#define PWR_CR2_TEMPH BIT(11)
+
+/* PWR_CR3 register fields */
+#define PWR_CR3_PVDEN BIT(0)
+#define PWR_CR3_PVDO BIT(8)
+
+/* PWR_CR7 register fields */
+#define PWR_CR7_VDDIO2VMEN BIT(0)
+#define PWR_CR7_VDDIO2SV BIT(8)
+#define PWR_CR7_VDDIO2RDY BIT(16)
+#define PWR_CR7_VDDIO2VRSEL BIT(24)
+#define PWR_CR7_VDDIO2VRSTBY BIT(25)
+
+/* PWR_CR8 register fields */
+#define PWR_CR8_VDDIO1VMEN BIT(0)
+#define PWR_CR8_VDDIO1SV BIT(8)
+#define PWR_CR8_VDDIO1RDY BIT(16)
+#define PWR_CR8_VDDIO1VRSEL BIT(24)
+#define PWR_CR8_VDDIO1VRSTBY BIT(25)
+
+/* PWR_CR9 register fields */
+#define PWR_CR9_BKPRBSEN BIT(0)
+
+/* PWR_CR10 register fields */
+#define PWR_CR10_RETRBSEN_MASK GENMASK_32(1, 0)
+#define PWR_CR10_RETRBSEN_SHIFT 0
+#define PWR_CR10_RETRBSEN_DISABLE 0U
+#define PWR_CR10_RETRBSEN_STANDBY_VBAT 1U
+#define PWR_CR10_RETRBSEN_STANDBY 2U
+
+/* PWR_CR11 register fields */
+#define PWR_CR11_DDRRETDIS BIT(0)
+
+/* PWR_BDCR register fields */
+#define PWR_BDCR_DBP BIT(0)
+
+/* PWR_CPU1CR register fields */
+#define PWR_CPU1CR_PDDS_D2 BIT(0)
+#define PWR_CPU1CR_PDDS_D1 BIT(1)
+#define PWR_CPU1CR_VBF BIT(4)
+#define PWR_CPU1CR_STOPF BIT(5)
+#define PWR_CPU1CR_SBF BIT(6)
+#define PWR_CPU1CR_SBF_D1 BIT(7)
+#define PWR_CPU1CR_CSSF BIT(9)
+#define PWR_CPU1CR_STANDBYWFIL2 BIT(15)
+#define PWR_CPU1CR_LPDS_D1 BIT(16)
+#define PWR_CPU1CR_LVDS_D1 BIT(17)
+
+/* PWR_CPU2CR register fields */
+#define PWR_CPU2CR_PDDS_D2 BIT(0)
+#define PWR_CPU2CR_VBF BIT(4)
+#define PWR_CPU2CR_STOPF BIT(5)
+#define PWR_CPU2CR_SBF BIT(6)
+#define PWR_CPU2CR_SBF_D2 BIT(7)
+#define PWR_CPU2CR_CSSF BIT(9)
+#define PWR_CPU2CR_DEEPSLEEP BIT(15)
+#define PWR_CPU2CR_LPDS_D2 BIT(16)
+#define PWR_CPU2CR_LVDS_D2 BIT(17)
+
+/* PWR_D1CR register fields */
+#define PWR_D1CR_LPCFG_D1 BIT(0)
+#define PWR_D1CR_POPL_D1_MASK GENMASK_32(12, 8)
+#define PWR_D1CR_POPL_D1_SHIFT 8
+
+/* PWR_D2CR register fields */
+#define PWR_D2CR_LPCFG_D2 BIT(0)
+#define PWR_D2CR_POPL_D2_MASK GENMASK_32(12, 8)
+#define PWR_D2CR_POPL_D2_SHIFT 8
+#define PWR_D2CR_LPLVDLY_D2_MASK GENMASK_32(18, 16)
+#define PWR_D2CR_LPLVDLY_D2_SHIFT 16
+#define PWR_D2CR_PODH_D2_MASK GENMASK_32(27, 24)
+#define PWR_D2CR_PODH_D2_SHIFT 24
+
+/* PWR_WKUPCR1 register fields */
+#define PWR_WKUPCR1_WKUPC BIT(0)
+#define PWR_WKUPCR1_WKUPP BIT(8)
+#define PWR_WKUPCR1_WKUPPUPD_MASK GENMASK_32(13, 12)
+#define PWR_WKUPCR1_WKUPPUPD_SHIFT 12
+#define PWR_WKUPCR1_WKUPENCPU1 BIT(16)
+#define PWR_WKUPCR1_WKUPENCPU2 BIT(17)
+#define PWR_WKUPCR1_WKUPF BIT(31)
+
+/* PWR_WKUPCR2 register fields */
+#define PWR_WKUPCR2_WKUPC BIT(0)
+#define PWR_WKUPCR2_WKUPP BIT(8)
+#define PWR_WKUPCR2_WKUPPUPD_MASK GENMASK_32(13, 12)
+#define PWR_WKUPCR2_WKUPPUPD_SHIFT 12
+#define PWR_WKUPCR2_WKUPENCPU1 BIT(16)
+#define PWR_WKUPCR2_WKUPENCPU2 BIT(17)
+#define PWR_WKUPCR2_WKUPF BIT(31)
+
+/* PWR_WKUPCR3 register fields */
+#define PWR_WKUPCR3_WKUPC BIT(0)
+#define PWR_WKUPCR3_WKUPP BIT(8)
+#define PWR_WKUPCR3_WKUPPUPD_MASK GENMASK_32(13, 12)
+#define PWR_WKUPCR3_WKUPPUPD_SHIFT 12
+#define PWR_WKUPCR3_WKUPENCPU1 BIT(16)
+#define PWR_WKUPCR3_WKUPENCPU2 BIT(17)
+#define PWR_WKUPCR3_WKUPF BIT(31)
+
+/* PWR_WKUPCR4 register fields */
+#define PWR_WKUPCR4_WKUPC BIT(0)
+#define PWR_WKUPCR4_WKUPP BIT(8)
+#define PWR_WKUPCR4_WKUPPUPD_MASK GENMASK_32(13, 12)
+#define PWR_WKUPCR4_WKUPPUPD_SHIFT 12
+#define PWR_WKUPCR4_WKUPENCPU1 BIT(16)
+#define PWR_WKUPCR4_WKUPENCPU2 BIT(17)
+#define PWR_WKUPCR4_WKUPF BIT(31)
+
+/* PWR_WKUPCR5 register fields */
+#define PWR_WKUPCR5_WKUPC BIT(0)
+#define PWR_WKUPCR5_WKUPP BIT(8)
+#define PWR_WKUPCR5_WKUPPUPD_MASK GENMASK_32(13, 12)
+#define PWR_WKUPCR5_WKUPPUPD_SHIFT 12
+#define PWR_WKUPCR5_WKUPENCPU1 BIT(16)
+#define PWR_WKUPCR5_WKUPENCPU2 BIT(17)
+#define PWR_WKUPCR5_WKUPF BIT(31)
+
+/* PWR_WKUPCR6 register fields */
+#define PWR_WKUPCR6_WKUPC BIT(0)
+#define PWR_WKUPCR6_WKUPP BIT(8)
+#define PWR_WKUPCR6_WKUPPUPD_MASK GENMASK_32(13, 12)
+#define PWR_WKUPCR6_WKUPPUPD_SHIFT 12
+#define PWR_WKUPCR6_WKUPENCPU1 BIT(16)
+#define PWR_WKUPCR6_WKUPENCPU2 BIT(17)
+#define PWR_WKUPCR6_WKUPF BIT(31)
+
+/* PWR_RSECCFGR register fields */
+#define PWR_RSECCFGR_RSEC0 BIT(0)
+#define PWR_RSECCFGR_RSEC1 BIT(1)
+#define PWR_RSECCFGR_RSEC2 BIT(2)
+#define PWR_RSECCFGR_RSEC3 BIT(3)
+#define PWR_RSECCFGR_RSEC4 BIT(4)
+#define PWR_RSECCFGR_RSEC5 BIT(5)
+#define PWR_RSECCFGR_RSEC6 BIT(6)
+
+/* PWR_RPRIVCFGR register fields */
+#define PWR_RPRIVCFGR_RPRIV0 BIT(0)
+#define PWR_RPRIVCFGR_RPRIV1 BIT(1)
+#define PWR_RPRIVCFGR_RPRIV2 BIT(2)
+#define PWR_RPRIVCFGR_RPRIV3 BIT(3)
+#define PWR_RPRIVCFGR_RPRIV4 BIT(4)
+#define PWR_RPRIVCFGR_RPRIV5 BIT(5)
+#define PWR_RPRIVCFGR_RPRIV6 BIT(6)
+
+/* PWR_R0CIDCFGR register fields */
+#define PWR_R0CIDCFGR_CFEN BIT(0)
+#define PWR_R0CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R0CIDCFGR_SCID_SHIFT 4
+
+/* PWR_R1CIDCFGR register fields */
+#define PWR_R1CIDCFGR_CFEN BIT(0)
+#define PWR_R1CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R1CIDCFGR_SCID_SHIFT 4
+
+/* PWR_R2CIDCFGR register fields */
+#define PWR_R2CIDCFGR_CFEN BIT(0)
+#define PWR_R2CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R2CIDCFGR_SCID_SHIFT 4
+
+/* PWR_R3CIDCFGR register fields */
+#define PWR_R3CIDCFGR_CFEN BIT(0)
+#define PWR_R3CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R3CIDCFGR_SCID_SHIFT 4
+
+/* PWR_R4CIDCFGR register fields */
+#define PWR_R4CIDCFGR_CFEN BIT(0)
+#define PWR_R4CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R4CIDCFGR_SCID_SHIFT 4
+
+/* PWR_R5CIDCFGR register fields */
+#define PWR_R5CIDCFGR_CFEN BIT(0)
+#define PWR_R5CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R5CIDCFGR_SCID_SHIFT 4
+
+/* PWR_R6CIDCFGR register fields */
+#define PWR_R6CIDCFGR_CFEN BIT(0)
+#define PWR_R6CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R6CIDCFGR_SCID_SHIFT 4
+
+/* PWR_WIOSECCFGR register fields */
+#define PWR_WIOSECCFGR_WIOSEC1 BIT(0)
+#define PWR_WIOSECCFGR_WIOSEC2 BIT(1)
+#define PWR_WIOSECCFGR_WIOSEC3 BIT(2)
+#define PWR_WIOSECCFGR_WIOSEC4 BIT(3)
+#define PWR_WIOSECCFGR_WIOSEC5 BIT(4)
+#define PWR_WIOSECCFGR_WIOSEC6 BIT(5)
+
+/* PWR_WIOPRIVCFGR register fields */
+#define PWR_WIOPRIVCFGR_WIOPRIV1 BIT(0)
+#define PWR_WIOPRIVCFGR_WIOPRIV2 BIT(1)
+#define PWR_WIOPRIVCFGR_WIOPRIV3 BIT(2)
+#define PWR_WIOPRIVCFGR_WIOPRIV4 BIT(3)
+#define PWR_WIOPRIVCFGR_WIOPRIV5 BIT(4)
+#define PWR_WIOPRIVCFGR_WIOPRIV6 BIT(5)
+
+/* PWR_WIO1CIDCFGR register fields */
+#define PWR_WIO1CIDCFGR_CFEN BIT(0)
+#define PWR_WIO1CIDCFGR_SEM_EN BIT(1)
+#define PWR_WIO1CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO1CIDCFGR_SCID_SHIFT 4
+#define PWR_WIO1CIDCFGR_SEMWLC0 BIT(16)
+#define PWR_WIO1CIDCFGR_SEMWLC1 BIT(17)
+#define PWR_WIO1CIDCFGR_SEMWLC2 BIT(18)
+#define PWR_WIO1CIDCFGR_SEMWLC3 BIT(19)
+#define PWR_WIO1CIDCFGR_SEMWLC4 BIT(20)
+#define PWR_WIO1CIDCFGR_SEMWLC5 BIT(21)
+#define PWR_WIO1CIDCFGR_SEMWLC6 BIT(22)
+#define PWR_WIO1CIDCFGR_SEMWLC7 BIT(23)
+
+/* PWR_WIO1SEMCR register fields */
+#define PWR_WIO1SEMCR_SEM_MUTEX BIT(0)
+#define PWR_WIO1SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO1SEMCR_SEMCID_SHIFT 4
+
+/* PWR_WIO2CIDCFGR register fields */
+#define PWR_WIO2CIDCFGR_CFEN BIT(0)
+#define PWR_WIO2CIDCFGR_SEM_EN BIT(1)
+#define PWR_WIO2CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO2CIDCFGR_SCID_SHIFT 4
+#define PWR_WIO2CIDCFGR_SEMWLC0 BIT(16)
+#define PWR_WIO2CIDCFGR_SEMWLC1 BIT(17)
+#define PWR_WIO2CIDCFGR_SEMWLC2 BIT(18)
+#define PWR_WIO2CIDCFGR_SEMWLC3 BIT(19)
+#define PWR_WIO2CIDCFGR_SEMWLC4 BIT(20)
+#define PWR_WIO2CIDCFGR_SEMWLC5 BIT(21)
+#define PWR_WIO2CIDCFGR_SEMWLC6 BIT(22)
+#define PWR_WIO2CIDCFGR_SEMWLC7 BIT(23)
+
+/* PWR_WIO2SEMCR register fields */
+#define PWR_WIO2SEMCR_SEM_MUTEX BIT(0)
+#define PWR_WIO2SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO2SEMCR_SEMCID_SHIFT 4
+
+/* PWR_WIO3CIDCFGR register fields */
+#define PWR_WIO3CIDCFGR_CFEN BIT(0)
+#define PWR_WIO3CIDCFGR_SEM_EN BIT(1)
+#define PWR_WIO3CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO3CIDCFGR_SCID_SHIFT 4
+#define PWR_WIO3CIDCFGR_SEMWLC0 BIT(16)
+#define PWR_WIO3CIDCFGR_SEMWLC1 BIT(17)
+#define PWR_WIO3CIDCFGR_SEMWLC2 BIT(18)
+#define PWR_WIO3CIDCFGR_SEMWLC3 BIT(19)
+#define PWR_WIO3CIDCFGR_SEMWLC4 BIT(20)
+#define PWR_WIO3CIDCFGR_SEMWLC5 BIT(21)
+#define PWR_WIO3CIDCFGR_SEMWLC6 BIT(22)
+#define PWR_WIO3CIDCFGR_SEMWLC7 BIT(23)
+
+/* PWR_WIO3SEMCR register fields */
+#define PWR_WIO3SEMCR_SEM_MUTEX BIT(0)
+#define PWR_WIO3SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO3SEMCR_SEMCID_SHIFT 4
+
+/* PWR_WIO4CIDCFGR register fields */
+#define PWR_WIO4CIDCFGR_CFEN BIT(0)
+#define PWR_WIO4CIDCFGR_SEM_EN BIT(1)
+#define PWR_WIO4CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO4CIDCFGR_SCID_SHIFT 4
+#define PWR_WIO4CIDCFGR_SEMWLC0 BIT(16)
+#define PWR_WIO4CIDCFGR_SEMWLC1 BIT(17)
+#define PWR_WIO4CIDCFGR_SEMWLC2 BIT(18)
+#define PWR_WIO4CIDCFGR_SEMWLC3 BIT(19)
+#define PWR_WIO4CIDCFGR_SEMWLC4 BIT(20)
+#define PWR_WIO4CIDCFGR_SEMWLC5 BIT(21)
+#define PWR_WIO4CIDCFGR_SEMWLC6 BIT(22)
+#define PWR_WIO4CIDCFGR_SEMWLC7 BIT(23)
+
+/* PWR_WIO4SEMCR register fields */
+#define PWR_WIO4SEMCR_SEM_MUTEX BIT(0)
+#define PWR_WIO4SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO4SEMCR_SEMCID_SHIFT 4
+
+/* PWR_WIO5CIDCFGR register fields */
+#define PWR_WIO5CIDCFGR_CFEN BIT(0)
+#define PWR_WIO5CIDCFGR_SEM_EN BIT(1)
+#define PWR_WIO5CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO5CIDCFGR_SCID_SHIFT 4
+#define PWR_WIO5CIDCFGR_SEMWLC0 BIT(16)
+#define PWR_WIO5CIDCFGR_SEMWLC1 BIT(17)
+#define PWR_WIO5CIDCFGR_SEMWLC2 BIT(18)
+#define PWR_WIO5CIDCFGR_SEMWLC3 BIT(19)
+#define PWR_WIO5CIDCFGR_SEMWLC4 BIT(20)
+#define PWR_WIO5CIDCFGR_SEMWLC5 BIT(21)
+#define PWR_WIO5CIDCFGR_SEMWLC6 BIT(22)
+#define PWR_WIO5CIDCFGR_SEMWLC7 BIT(23)
+
+/* PWR_WIO5SEMCR register fields */
+#define PWR_WIO5SEMCR_SEM_MUTEX BIT(0)
+#define PWR_WIO5SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO5SEMCR_SEMCID_SHIFT 4
+
+/* PWR_WIO6CIDCFGR register fields */
+#define PWR_WIO6CIDCFGR_CFEN BIT(0)
+#define PWR_WIO6CIDCFGR_SEM_EN BIT(1)
+#define PWR_WIO6CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO6CIDCFGR_SCID_SHIFT 4
+#define PWR_WIO6CIDCFGR_SEMWLC0 BIT(16)
+#define PWR_WIO6CIDCFGR_SEMWLC1 BIT(17)
+#define PWR_WIO6CIDCFGR_SEMWLC2 BIT(18)
+#define PWR_WIO6CIDCFGR_SEMWLC3 BIT(19)
+#define PWR_WIO6CIDCFGR_SEMWLC4 BIT(20)
+#define PWR_WIO6CIDCFGR_SEMWLC5 BIT(21)
+#define PWR_WIO6CIDCFGR_SEMWLC6 BIT(22)
+#define PWR_WIO6CIDCFGR_SEMWLC7 BIT(23)
+
+/* PWR_WIO6SEMCR register fields */
+#define PWR_WIO6SEMCR_SEM_MUTEX BIT(0)
+#define PWR_WIO6SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO6SEMCR_SEMCID_SHIFT 4
+
+/* PWR_CPU1D1SR register fields */
+#define PWR_CPU1D1SR_HOLD_BOOT BIT(0)
+#define PWR_CPU1D1SR_CSTATE_MASK GENMASK_32(3, 2)
+#define PWR_CPU1D1SR_CSTATE_SHIFT 2
+#define PWR_CPU1D1SR_DSTATE_MASK GENMASK_32(10, 8)
+#define PWR_CPU1D1SR_DSTATE_SHIFT 8
+
+/* PWR_CPU2D2SR register fields */
+#define PWR_CPU2D2SR_HOLD_BOOT BIT(0)
+#define PWR_CPU2D2SR_WFBEN BIT(1)
+#define PWR_CPU2D2SR_CSTATE_MASK GENMASK_32(3, 2)
+#define PWR_CPU2D2SR_CSTATE_SHIFT 2
+#define PWR_CPU2D2SR_DSTATE_MASK GENMASK_32(10, 8)
+#define PWR_CPU2D2SR_DSTATE_SHIFT 8
+
+/* PWR_DBGR register fields */
+#define PWR_DBGR_VDDIOKRETRAM BIT(16)
+#define PWR_DBGR_VDDIOKBKPRAM BIT(17)
+
+/* PWR_VERR register fields */
+#define PWR_VERR_MINREV_MASK GENMASK_32(3, 0)
+#define PWR_VERR_MINREV_SHIFT 0
+#define PWR_VERR_MAJREV_MASK GENMASK_32(7, 4)
+#define PWR_VERR_MAJREV_SHIFT 4
+
+#endif /* STM32MP21_PWR_H */
+
diff --git a/include/drivers/st/stm32mp21_rcc.h b/include/drivers/st/stm32mp21_rcc.h
new file mode 100644
index 0000000..a3787d0
--- /dev/null
+++ b/include/drivers/st/stm32mp21_rcc.h
@@ -0,0 +1,4668 @@
+/*
+ * Copyright (c) 2025, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP21_RCC_H
+#define STM32MP21_RCC_H
+
+#include <lib/utils_def.h>
+
+#define RCC_SECCFGR0 U(0x0)
+#define RCC_SECCFGR1 U(0x4)
+#define RCC_SECCFGR2 U(0x8)
+#define RCC_SECCFGR3 U(0xC)
+#define RCC_PRIVCFGR0 U(0x10)
+#define RCC_PRIVCFGR1 U(0x14)
+#define RCC_PRIVCFGR2 U(0x18)
+#define RCC_PRIVCFGR3 U(0x1C)
+#define RCC_RCFGLOCKR0 U(0x20)
+#define RCC_RCFGLOCKR1 U(0x24)
+#define RCC_RCFGLOCKR2 U(0x28)
+#define RCC_RCFGLOCKR3 U(0x2C)
+#define RCC_R0CIDCFGR U(0x30)
+#define RCC_R0SEMCR U(0x34)
+#define RCC_R1CIDCFGR U(0x38)
+#define RCC_R1SEMCR U(0x3C)
+#define RCC_R2CIDCFGR U(0x40)
+#define RCC_R2SEMCR U(0x44)
+#define RCC_R3CIDCFGR U(0x48)
+#define RCC_R3SEMCR U(0x4C)
+#define RCC_R4CIDCFGR U(0x50)
+#define RCC_R4SEMCR U(0x54)
+#define RCC_R5CIDCFGR U(0x58)
+#define RCC_R5SEMCR U(0x5C)
+#define RCC_R6CIDCFGR U(0x60)
+#define RCC_R6SEMCR U(0x64)
+#define RCC_R7CIDCFGR U(0x68)
+#define RCC_R7SEMCR U(0x6C)
+#define RCC_R8CIDCFGR U(0x70)
+#define RCC_R8SEMCR U(0x74)
+#define RCC_R9CIDCFGR U(0x78)
+#define RCC_R9SEMCR U(0x7C)
+#define RCC_R10CIDCFGR U(0x80)
+#define RCC_R10SEMCR U(0x84)
+#define RCC_R11CIDCFGR U(0x88)
+#define RCC_R11SEMCR U(0x8C)
+#define RCC_R12CIDCFGR U(0x90)
+#define RCC_R12SEMCR U(0x94)
+#define RCC_R13CIDCFGR U(0x98)
+#define RCC_R13SEMCR U(0x9C)
+#define RCC_R14CIDCFGR U(0xA0)
+#define RCC_R14SEMCR U(0xA4)
+#define RCC_R15CIDCFGR U(0xA8)
+#define RCC_R15SEMCR U(0xAC)
+#define RCC_R16CIDCFGR U(0xB0)
+#define RCC_R16SEMCR U(0xB4)
+#define RCC_R17CIDCFGR U(0xB8)
+#define RCC_R17SEMCR U(0xBC)
+#define RCC_R18CIDCFGR U(0xC0)
+#define RCC_R18SEMCR U(0xC4)
+#define RCC_R19CIDCFGR U(0xC8)
+#define RCC_R19SEMCR U(0xCC)
+#define RCC_R20CIDCFGR U(0xD0)
+#define RCC_R20SEMCR U(0xD4)
+#define RCC_R21CIDCFGR U(0xD8)
+#define RCC_R21SEMCR U(0xDC)
+#define RCC_R22CIDCFGR U(0xE0)
+#define RCC_R22SEMCR U(0xE4)
+#define RCC_R23CIDCFGR U(0xE8)
+#define RCC_R23SEMCR U(0xEC)
+#define RCC_R24CIDCFGR U(0xF0)
+#define RCC_R24SEMCR U(0xF4)
+#define RCC_R25CIDCFGR U(0xF8)
+#define RCC_R25SEMCR U(0xFC)
+#define RCC_R26CIDCFGR U(0x100)
+#define RCC_R26SEMCR U(0x104)
+#define RCC_R27CIDCFGR U(0x108)
+#define RCC_R27SEMCR U(0x10C)
+#define RCC_R28CIDCFGR U(0x110)
+#define RCC_R28SEMCR U(0x114)
+#define RCC_R29CIDCFGR U(0x118)
+#define RCC_R29SEMCR U(0x11C)
+#define RCC_R30CIDCFGR U(0x120)
+#define RCC_R30SEMCR U(0x124)
+#define RCC_R31CIDCFGR U(0x128)
+#define RCC_R31SEMCR U(0x12C)
+#define RCC_R32CIDCFGR U(0x130)
+#define RCC_R32SEMCR U(0x134)
+#define RCC_R33CIDCFGR U(0x138)
+#define RCC_R33SEMCR U(0x13C)
+#define RCC_R34CIDCFGR U(0x140)
+#define RCC_R34SEMCR U(0x144)
+#define RCC_R35CIDCFGR U(0x148)
+#define RCC_R35SEMCR U(0x14C)
+#define RCC_R36CIDCFGR U(0x150)
+#define RCC_R36SEMCR U(0x154)
+#define RCC_R37CIDCFGR U(0x158)
+#define RCC_R37SEMCR U(0x15C)
+#define RCC_R38CIDCFGR U(0x160)
+#define RCC_R38SEMCR U(0x164)
+#define RCC_R39CIDCFGR U(0x168)
+#define RCC_R39SEMCR U(0x16C)
+#define RCC_R40CIDCFGR U(0x170)
+#define RCC_R40SEMCR U(0x174)
+#define RCC_R41CIDCFGR U(0x178)
+#define RCC_R41SEMCR U(0x17C)
+#define RCC_R42CIDCFGR U(0x180)
+#define RCC_R42SEMCR U(0x184)
+#define RCC_R43CIDCFGR U(0x188)
+#define RCC_R43SEMCR U(0x18C)
+#define RCC_R44CIDCFGR U(0x190)
+#define RCC_R44SEMCR U(0x194)
+#define RCC_R45CIDCFGR U(0x198)
+#define RCC_R45SEMCR U(0x19C)
+#define RCC_R46CIDCFGR U(0x1A0)
+#define RCC_R46SEMCR U(0x1A4)
+#define RCC_R47CIDCFGR U(0x1A8)
+#define RCC_R47SEMCR U(0x1AC)
+#define RCC_R48CIDCFGR U(0x1B0)
+#define RCC_R48SEMCR U(0x1B4)
+#define RCC_R49CIDCFGR U(0x1B8)
+#define RCC_R49SEMCR U(0x1BC)
+#define RCC_R50CIDCFGR U(0x1C0)
+#define RCC_R50SEMCR U(0x1C4)
+#define RCC_R51CIDCFGR U(0x1C8)
+#define RCC_R51SEMCR U(0x1CC)
+#define RCC_R52CIDCFGR U(0x1D0)
+#define RCC_R52SEMCR U(0x1D4)
+#define RCC_R53CIDCFGR U(0x1D8)
+#define RCC_R53SEMCR U(0x1DC)
+#define RCC_R54CIDCFGR U(0x1E0)
+#define RCC_R54SEMCR U(0x1E4)
+#define RCC_R55CIDCFGR U(0x1E8)
+#define RCC_R55SEMCR U(0x1EC)
+#define RCC_R56CIDCFGR U(0x1F0)
+#define RCC_R56SEMCR U(0x1F4)
+#define RCC_R57CIDCFGR U(0x1F8)
+#define RCC_R57SEMCR U(0x1FC)
+#define RCC_R58CIDCFGR U(0x200)
+#define RCC_R58SEMCR U(0x204)
+#define RCC_R59CIDCFGR U(0x208)
+#define RCC_R59SEMCR U(0x20C)
+#define RCC_R60CIDCFGR U(0x210)
+#define RCC_R60SEMCR U(0x214)
+#define RCC_R61CIDCFGR U(0x218)
+#define RCC_R61SEMCR U(0x21C)
+#define RCC_R62CIDCFGR U(0x220)
+#define RCC_R62SEMCR U(0x224)
+#define RCC_R63CIDCFGR U(0x228)
+#define RCC_R63SEMCR U(0x22C)
+#define RCC_R64CIDCFGR U(0x230)
+#define RCC_R64SEMCR U(0x234)
+#define RCC_R65CIDCFGR U(0x238)
+#define RCC_R65SEMCR U(0x23C)
+#define RCC_R66CIDCFGR U(0x240)
+#define RCC_R66SEMCR U(0x244)
+#define RCC_R67CIDCFGR U(0x248)
+#define RCC_R67SEMCR U(0x24C)
+#define RCC_R68CIDCFGR U(0x250)
+#define RCC_R68SEMCR U(0x254)
+#define RCC_R69CIDCFGR U(0x258)
+#define RCC_R69SEMCR U(0x25C)
+#define RCC_R70CIDCFGR U(0x260)
+#define RCC_R70SEMCR U(0x264)
+#define RCC_R71CIDCFGR U(0x268)
+#define RCC_R71SEMCR U(0x26C)
+#define RCC_R72CIDCFGR U(0x270)
+#define RCC_R72SEMCR U(0x274)
+#define RCC_R73CIDCFGR U(0x278)
+#define RCC_R73SEMCR U(0x27C)
+#define RCC_R74CIDCFGR U(0x280)
+#define RCC_R74SEMCR U(0x284)
+#define RCC_R75CIDCFGR U(0x288)
+#define RCC_R75SEMCR U(0x28C)
+#define RCC_R76CIDCFGR U(0x290)
+#define RCC_R76SEMCR U(0x294)
+#define RCC_R77CIDCFGR U(0x298)
+#define RCC_R77SEMCR U(0x29C)
+#define RCC_R78CIDCFGR U(0x2A0)
+#define RCC_R78SEMCR U(0x2A4)
+#define RCC_R79CIDCFGR U(0x2A8)
+#define RCC_R79SEMCR U(0x2AC)
+#define RCC_R80CIDCFGR U(0x2B0)
+#define RCC_R80SEMCR U(0x2B4)
+#define RCC_R81CIDCFGR U(0x2B8)
+#define RCC_R81SEMCR U(0x2BC)
+#define RCC_R82CIDCFGR U(0x2C0)
+#define RCC_R82SEMCR U(0x2C4)
+#define RCC_R83CIDCFGR U(0x2C8)
+#define RCC_R83SEMCR U(0x2CC)
+#define RCC_R84CIDCFGR U(0x2D0)
+#define RCC_R84SEMCR U(0x2D4)
+#define RCC_R85CIDCFGR U(0x2D8)
+#define RCC_R85SEMCR U(0x2DC)
+#define RCC_R86CIDCFGR U(0x2E0)
+#define RCC_R86SEMCR U(0x2E4)
+#define RCC_R87CIDCFGR U(0x2E8)
+#define RCC_R87SEMCR U(0x2EC)
+#define RCC_R88CIDCFGR U(0x2F0)
+#define RCC_R88SEMCR U(0x2F4)
+#define RCC_R89CIDCFGR U(0x2F8)
+#define RCC_R89SEMCR U(0x2FC)
+#define RCC_R90CIDCFGR U(0x300)
+#define RCC_R90SEMCR U(0x304)
+#define RCC_R91CIDCFGR U(0x308)
+#define RCC_R91SEMCR U(0x30C)
+#define RCC_R92CIDCFGR U(0x310)
+#define RCC_R92SEMCR U(0x314)
+#define RCC_R93CIDCFGR U(0x318)
+#define RCC_R93SEMCR U(0x31C)
+#define RCC_R94CIDCFGR U(0x320)
+#define RCC_R94SEMCR U(0x324)
+#define RCC_R95CIDCFGR U(0x328)
+#define RCC_R95SEMCR U(0x32C)
+#define RCC_R96CIDCFGR U(0x330)
+#define RCC_R96SEMCR U(0x334)
+#define RCC_R97CIDCFGR U(0x338)
+#define RCC_R97SEMCR U(0x33C)
+#define RCC_R98CIDCFGR U(0x340)
+#define RCC_R98SEMCR U(0x344)
+#define RCC_R99CIDCFGR U(0x348)
+#define RCC_R99SEMCR U(0x34C)
+#define RCC_R100CIDCFGR U(0x350)
+#define RCC_R100SEMCR U(0x354)
+#define RCC_R101CIDCFGR U(0x358)
+#define RCC_R101SEMCR U(0x35C)
+#define RCC_R102CIDCFGR U(0x360)
+#define RCC_R102SEMCR U(0x364)
+#define RCC_R103CIDCFGR U(0x368)
+#define RCC_R103SEMCR U(0x36C)
+#define RCC_R104CIDCFGR U(0x370)
+#define RCC_R104SEMCR U(0x374)
+#define RCC_R105CIDCFGR U(0x378)
+#define RCC_R105SEMCR U(0x37C)
+#define RCC_R106CIDCFGR U(0x380)
+#define RCC_R106SEMCR U(0x384)
+#define RCC_R107CIDCFGR U(0x388)
+#define RCC_R107SEMCR U(0x38C)
+#define RCC_R108CIDCFGR U(0x390)
+#define RCC_R108SEMCR U(0x394)
+#define RCC_R109CIDCFGR U(0x398)
+#define RCC_R109SEMCR U(0x39C)
+#define RCC_R110CIDCFGR U(0x3A0)
+#define RCC_R110SEMCR U(0x3A4)
+#define RCC_R111CIDCFGR U(0x3A8)
+#define RCC_R111SEMCR U(0x3AC)
+#define RCC_R112CIDCFGR U(0x3B0)
+#define RCC_R112SEMCR U(0x3B4)
+#define RCC_R113CIDCFGR U(0x3B8)
+#define RCC_R113SEMCR U(0x3BC)
+#define RCC_GRSTCSETR U(0x400)
+#define RCC_C1RSTCSETR U(0x404)
+#define RCC_C2RSTCSETR U(0x40C)
+#define RCC_HWRSTSCLRR U(0x410)
+#define RCC_C1HWRSTSCLRR U(0x414)
+#define RCC_C2HWRSTSCLRR U(0x418)
+#define RCC_C1BOOTRSTSSETR U(0x41C)
+#define RCC_C1BOOTRSTSCLRR U(0x420)
+#define RCC_C2BOOTRSTSSETR U(0x424)
+#define RCC_C2BOOTRSTSCLRR U(0x428)
+#define RCC_C1SREQSETR U(0x42C)
+#define RCC_C1SREQCLRR U(0x430)
+#define RCC_CPUBOOTCR U(0x434)
+#define RCC_STBYBOOTCR U(0x438)
+#define RCC_LEGBOOTCR U(0x43C)
+#define RCC_BDCR U(0x440)
+#define RCC_RDCR U(0x44C)
+#define RCC_C1MSRDCR U(0x450)
+#define RCC_PWRLPDLYCR U(0x454)
+#define RCC_C1CIESETR U(0x458)
+#define RCC_C1CIFCLRR U(0x45C)
+#define RCC_C2CIESETR U(0x460)
+#define RCC_C2CIFCLRR U(0x464)
+#define RCC_IWDGC1FZSETR U(0x468)
+#define RCC_IWDGC1FZCLRR U(0x46C)
+#define RCC_IWDGC1CFGSETR U(0x470)
+#define RCC_IWDGC1CFGCLRR U(0x474)
+#define RCC_IWDGC2FZSETR U(0x478)
+#define RCC_IWDGC2FZCLRR U(0x47C)
+#define RCC_IWDGC2CFGSETR U(0x480)
+#define RCC_IWDGC2CFGCLRR U(0x484)
+#define RCC_MCO1CFGR U(0x488)
+#define RCC_MCO2CFGR U(0x48C)
+#define RCC_OCENSETR U(0x490)
+#define RCC_OCENCLRR U(0x494)
+#define RCC_OCRDYR U(0x498)
+#define RCC_HSICFGR U(0x49C)
+#define RCC_MSICFGR U(0x4A0)
+#define RCC_LSICR U(0x4A4)
+#define RCC_RTCDIVR U(0x4A8)
+#define RCC_APB1DIVR U(0x4AC)
+#define RCC_APB2DIVR U(0x4B0)
+#define RCC_APB3DIVR U(0x4B4)
+#define RCC_APB4DIVR U(0x4B8)
+#define RCC_APB5DIVR U(0x4BC)
+#define RCC_APBDBGDIVR U(0x4C0)
+#define RCC_TIMG1PRER U(0x4C8)
+#define RCC_TIMG2PRER U(0x4CC)
+#define RCC_LSMCUDIVR U(0x4D0)
+#define RCC_DDRCPCFGR U(0x4D4)
+#define RCC_DDRCAPBCFGR U(0x4D8)
+#define RCC_DDRPHYCAPBCFGR U(0x4DC)
+#define RCC_DDRPHYCCFGR U(0x4E0)
+#define RCC_DDRCFGR U(0x4E4)
+#define RCC_DDRITFCFGR U(0x4E8)
+#define RCC_SYSRAMCFGR U(0x4F0)
+#define RCC_SRAM1CFGR U(0x4F8)
+#define RCC_RETRAMCFGR U(0x500)
+#define RCC_BKPSRAMCFGR U(0x504)
+#define RCC_OSPI1CFGR U(0x514)
+#define RCC_FMCCFGR U(0x51C)
+#define RCC_DBGCFGR U(0x520)
+#define RCC_STMCFGR U(0x524)
+#define RCC_ETRCFGR U(0x528)
+#define RCC_GPIOACFGR U(0x52C)
+#define RCC_GPIOBCFGR U(0x530)
+#define RCC_GPIOCCFGR U(0x534)
+#define RCC_GPIODCFGR U(0x538)
+#define RCC_GPIOECFGR U(0x53C)
+#define RCC_GPIOFCFGR U(0x540)
+#define RCC_GPIOGCFGR U(0x544)
+#define RCC_GPIOHCFGR U(0x548)
+#define RCC_GPIOICFGR U(0x54C)
+#define RCC_GPIOZCFGR U(0x558)
+#define RCC_HPDMA1CFGR U(0x55C)
+#define RCC_HPDMA2CFGR U(0x560)
+#define RCC_HPDMA3CFGR U(0x564)
+#define RCC_IPCC1CFGR U(0x570)
+#define RCC_RTCCFGR U(0x578)
+#define RCC_SYSCPU1CFGR U(0x580)
+#define RCC_BSECCFGR U(0x584)
+#define RCC_PLL2CFGR1 U(0x590)
+#define RCC_PLL2CFGR2 U(0x594)
+#define RCC_PLL2CFGR3 U(0x598)
+#define RCC_PLL2CFGR4 U(0x59C)
+#define RCC_PLL2CFGR5 U(0x5A0)
+#define RCC_PLL2CFGR6 U(0x5A8)
+#define RCC_PLL2CFGR7 U(0x5AC)
+#define RCC_HSIFMONCR U(0x5E0)
+#define RCC_HSIFVALR U(0x5E4)
+#define RCC_MSIFMONCR U(0x5E8)
+#define RCC_MSIFVALR U(0x5EC)
+#define RCC_TIM1CFGR U(0x700)
+#define RCC_TIM2CFGR U(0x704)
+#define RCC_TIM3CFGR U(0x708)
+#define RCC_TIM4CFGR U(0x70C)
+#define RCC_TIM5CFGR U(0x710)
+#define RCC_TIM6CFGR U(0x714)
+#define RCC_TIM7CFGR U(0x718)
+#define RCC_TIM8CFGR U(0x71C)
+#define RCC_TIM10CFGR U(0x720)
+#define RCC_TIM11CFGR U(0x724)
+#define RCC_TIM12CFGR U(0x728)
+#define RCC_TIM13CFGR U(0x72C)
+#define RCC_TIM14CFGR U(0x730)
+#define RCC_TIM15CFGR U(0x734)
+#define RCC_TIM16CFGR U(0x738)
+#define RCC_TIM17CFGR U(0x73C)
+#define RCC_LPTIM1CFGR U(0x744)
+#define RCC_LPTIM2CFGR U(0x748)
+#define RCC_LPTIM3CFGR U(0x74C)
+#define RCC_LPTIM4CFGR U(0x750)
+#define RCC_LPTIM5CFGR U(0x754)
+#define RCC_SPI1CFGR U(0x758)
+#define RCC_SPI2CFGR U(0x75C)
+#define RCC_SPI3CFGR U(0x760)
+#define RCC_SPI4CFGR U(0x764)
+#define RCC_SPI5CFGR U(0x768)
+#define RCC_SPI6CFGR U(0x76C)
+#define RCC_SPDIFRXCFGR U(0x778)
+#define RCC_USART1CFGR U(0x77C)
+#define RCC_USART2CFGR U(0x780)
+#define RCC_USART3CFGR U(0x784)
+#define RCC_UART4CFGR U(0x788)
+#define RCC_UART5CFGR U(0x78C)
+#define RCC_USART6CFGR U(0x790)
+#define RCC_UART7CFGR U(0x794)
+#define RCC_LPUART1CFGR U(0x7A0)
+#define RCC_I2C1CFGR U(0x7A4)
+#define RCC_I2C2CFGR U(0x7A8)
+#define RCC_I2C3CFGR U(0x7AC)
+#define RCC_SAI1CFGR U(0x7C4)
+#define RCC_SAI2CFGR U(0x7C8)
+#define RCC_SAI3CFGR U(0x7CC)
+#define RCC_SAI4CFGR U(0x7D0)
+#define RCC_MDF1CFGR U(0x7D8)
+#define RCC_FDCANCFGR U(0x7E0)
+#define RCC_HDPCFGR U(0x7E4)
+#define RCC_ADC1CFGR U(0x7E8)
+#define RCC_ADC2CFGR U(0x7EC)
+#define RCC_ETH1CFGR U(0x7F0)
+#define RCC_ETH2CFGR U(0x7F4)
+#define RCC_USBHCFGR U(0x7FC)
+#define RCC_USB2PHY1CFGR U(0x800)
+#define RCC_OTGCFGR U(0x808)
+#define RCC_USB2PHY2CFGR U(0x80C)
+#define RCC_STGENCFGR U(0x824)
+#define RCC_SDMMC1CFGR U(0x830)
+#define RCC_SDMMC2CFGR U(0x834)
+#define RCC_SDMMC3CFGR U(0x838)
+#define RCC_LTDCCFGR U(0x840)
+#define RCC_CSICFGR U(0x858)
+#define RCC_DCMIPPCFGR U(0x85C)
+#define RCC_DCMIPSSICFGR U(0x860)
+#define RCC_RNG1CFGR U(0x870)
+#define RCC_RNG2CFGR U(0x874)
+#define RCC_PKACFGR U(0x878)
+#define RCC_SAESCFGR U(0x87C)
+#define RCC_HASH1CFGR U(0x880)
+#define RCC_HASH2CFGR U(0x884)
+#define RCC_CRYP1CFGR U(0x888)
+#define RCC_CRYP2CFGR U(0x88C)
+#define RCC_IWDG1CFGR U(0x894)
+#define RCC_IWDG2CFGR U(0x898)
+#define RCC_IWDG3CFGR U(0x89C)
+#define RCC_IWDG4CFGR U(0x8A0)
+#define RCC_WWDG1CFGR U(0x8A4)
+#define RCC_VREFCFGR U(0x8AC)
+#define RCC_DTSCFGR U(0x8B0)
+#define RCC_CRCCFGR U(0x8B4)
+#define RCC_SERCCFGR U(0x8B8)
+#define RCC_DDRPERFMCFGR U(0x8C0)
+#define RCC_I3C1CFGR U(0x8C8)
+#define RCC_I3C2CFGR U(0x8CC)
+#define RCC_I3C3CFGR U(0x8D0)
+#define RCC_MUXSELCFGR U(0x1000)
+#define RCC_XBAR0CFGR U(0x1018)
+#define RCC_XBAR1CFGR U(0x101C)
+#define RCC_XBAR2CFGR U(0x1020)
+#define RCC_XBAR3CFGR U(0x1024)
+#define RCC_XBAR4CFGR U(0x1028)
+#define RCC_XBAR5CFGR U(0x102C)
+#define RCC_XBAR6CFGR U(0x1030)
+#define RCC_XBAR7CFGR U(0x1034)
+#define RCC_XBAR8CFGR U(0x1038)
+#define RCC_XBAR9CFGR U(0x103C)
+#define RCC_XBAR10CFGR U(0x1040)
+#define RCC_XBAR11CFGR U(0x1044)
+#define RCC_XBAR12CFGR U(0x1048)
+#define RCC_XBAR13CFGR U(0x104C)
+#define RCC_XBAR14CFGR U(0x1050)
+#define RCC_XBAR15CFGR U(0x1054)
+#define RCC_XBAR16CFGR U(0x1058)
+#define RCC_XBAR17CFGR U(0x105C)
+#define RCC_XBAR18CFGR U(0x1060)
+#define RCC_XBAR19CFGR U(0x1064)
+#define RCC_XBAR20CFGR U(0x1068)
+#define RCC_XBAR21CFGR U(0x106C)
+#define RCC_XBAR22CFGR U(0x1070)
+#define RCC_XBAR23CFGR U(0x1074)
+#define RCC_XBAR24CFGR U(0x1078)
+#define RCC_XBAR25CFGR U(0x107C)
+#define RCC_XBAR26CFGR U(0x1080)
+#define RCC_XBAR27CFGR U(0x1084)
+#define RCC_XBAR28CFGR U(0x1088)
+#define RCC_XBAR29CFGR U(0x108C)
+#define RCC_XBAR30CFGR U(0x1090)
+#define RCC_XBAR31CFGR U(0x1094)
+#define RCC_XBAR32CFGR U(0x1098)
+#define RCC_XBAR33CFGR U(0x109C)
+#define RCC_XBAR34CFGR U(0x10A0)
+#define RCC_XBAR35CFGR U(0x10A4)
+#define RCC_XBAR36CFGR U(0x10A8)
+#define RCC_XBAR37CFGR U(0x10AC)
+#define RCC_XBAR38CFGR U(0x10B0)
+#define RCC_XBAR39CFGR U(0x10B4)
+#define RCC_XBAR40CFGR U(0x10B8)
+#define RCC_XBAR41CFGR U(0x10BC)
+#define RCC_XBAR42CFGR U(0x10C0)
+#define RCC_XBAR43CFGR U(0x10C4)
+#define RCC_XBAR44CFGR U(0x10C8)
+#define RCC_XBAR45CFGR U(0x10CC)
+#define RCC_XBAR46CFGR U(0x10D0)
+#define RCC_XBAR47CFGR U(0x10D4)
+#define RCC_XBAR48CFGR U(0x10D8)
+#define RCC_XBAR49CFGR U(0x10DC)
+#define RCC_XBAR50CFGR U(0x10E0)
+#define RCC_XBAR51CFGR U(0x10E4)
+#define RCC_XBAR52CFGR U(0x10E8)
+#define RCC_XBAR53CFGR U(0x10EC)
+#define RCC_XBAR54CFGR U(0x10F0)
+#define RCC_XBAR55CFGR U(0x10F4)
+#define RCC_XBAR56CFGR U(0x10F8)
+#define RCC_XBAR57CFGR U(0x10FC)
+#define RCC_XBAR58CFGR U(0x1100)
+#define RCC_XBAR59CFGR U(0x1104)
+#define RCC_XBAR60CFGR U(0x1108)
+#define RCC_XBAR61CFGR U(0x110C)
+#define RCC_XBAR62CFGR U(0x1110)
+#define RCC_XBAR63CFGR U(0x1114)
+#define RCC_PREDIV0CFGR U(0x1118)
+#define RCC_PREDIV1CFGR U(0x111C)
+#define RCC_PREDIV2CFGR U(0x1120)
+#define RCC_PREDIV3CFGR U(0x1124)
+#define RCC_PREDIV4CFGR U(0x1128)
+#define RCC_PREDIV5CFGR U(0x112C)
+#define RCC_PREDIV6CFGR U(0x1130)
+#define RCC_PREDIV7CFGR U(0x1134)
+#define RCC_PREDIV8CFGR U(0x1138)
+#define RCC_PREDIV9CFGR U(0x113C)
+#define RCC_PREDIV10CFGR U(0x1140)
+#define RCC_PREDIV11CFGR U(0x1144)
+#define RCC_PREDIV12CFGR U(0x1148)
+#define RCC_PREDIV13CFGR U(0x114C)
+#define RCC_PREDIV14CFGR U(0x1150)
+#define RCC_PREDIV15CFGR U(0x1154)
+#define RCC_PREDIV16CFGR U(0x1158)
+#define RCC_PREDIV17CFGR U(0x115C)
+#define RCC_PREDIV18CFGR U(0x1160)
+#define RCC_PREDIV19CFGR U(0x1164)
+#define RCC_PREDIV20CFGR U(0x1168)
+#define RCC_PREDIV21CFGR U(0x116C)
+#define RCC_PREDIV22CFGR U(0x1170)
+#define RCC_PREDIV23CFGR U(0x1174)
+#define RCC_PREDIV24CFGR U(0x1178)
+#define RCC_PREDIV25CFGR U(0x117C)
+#define RCC_PREDIV26CFGR U(0x1180)
+#define RCC_PREDIV27CFGR U(0x1184)
+#define RCC_PREDIV28CFGR U(0x1188)
+#define RCC_PREDIV29CFGR U(0x118C)
+#define RCC_PREDIV30CFGR U(0x1190)
+#define RCC_PREDIV31CFGR U(0x1194)
+#define RCC_PREDIV32CFGR U(0x1198)
+#define RCC_PREDIV33CFGR U(0x119C)
+#define RCC_PREDIV34CFGR U(0x11A0)
+#define RCC_PREDIV35CFGR U(0x11A4)
+#define RCC_PREDIV36CFGR U(0x11A8)
+#define RCC_PREDIV37CFGR U(0x11AC)
+#define RCC_PREDIV38CFGR U(0x11B0)
+#define RCC_PREDIV39CFGR U(0x11B4)
+#define RCC_PREDIV40CFGR U(0x11B8)
+#define RCC_PREDIV41CFGR U(0x11BC)
+#define RCC_PREDIV42CFGR U(0x11C0)
+#define RCC_PREDIV43CFGR U(0x11C4)
+#define RCC_PREDIV44CFGR U(0x11C8)
+#define RCC_PREDIV45CFGR U(0x11CC)
+#define RCC_PREDIV46CFGR U(0x11D0)
+#define RCC_PREDIV47CFGR U(0x11D4)
+#define RCC_PREDIV48CFGR U(0x11D8)
+#define RCC_PREDIV49CFGR U(0x11DC)
+#define RCC_PREDIV50CFGR U(0x11E0)
+#define RCC_PREDIV51CFGR U(0x11E4)
+#define RCC_PREDIV52CFGR U(0x11E8)
+#define RCC_PREDIV53CFGR U(0x11EC)
+#define RCC_PREDIV54CFGR U(0x11F0)
+#define RCC_PREDIV55CFGR U(0x11F4)
+#define RCC_PREDIV56CFGR U(0x11F8)
+#define RCC_PREDIV57CFGR U(0x11FC)
+#define RCC_PREDIV58CFGR U(0x1200)
+#define RCC_PREDIV59CFGR U(0x1204)
+#define RCC_PREDIV60CFGR U(0x1208)
+#define RCC_PREDIV61CFGR U(0x120C)
+#define RCC_PREDIV62CFGR U(0x1210)
+#define RCC_PREDIV63CFGR U(0x1214)
+#define RCC_PREDIVSR1 U(0x1218)
+#define RCC_PREDIVSR2 U(0x121C)
+#define RCC_FINDIV0CFGR U(0x1224)
+#define RCC_FINDIV1CFGR U(0x1228)
+#define RCC_FINDIV2CFGR U(0x122C)
+#define RCC_FINDIV3CFGR U(0x1230)
+#define RCC_FINDIV4CFGR U(0x1234)
+#define RCC_FINDIV5CFGR U(0x1238)
+#define RCC_FINDIV6CFGR U(0x123C)
+#define RCC_FINDIV7CFGR U(0x1240)
+#define RCC_FINDIV8CFGR U(0x1244)
+#define RCC_FINDIV9CFGR U(0x1248)
+#define RCC_FINDIV10CFGR U(0x124C)
+#define RCC_FINDIV11CFGR U(0x1250)
+#define RCC_FINDIV12CFGR U(0x1254)
+#define RCC_FINDIV13CFGR U(0x1258)
+#define RCC_FINDIV14CFGR U(0x125C)
+#define RCC_FINDIV15CFGR U(0x1260)
+#define RCC_FINDIV16CFGR U(0x1264)
+#define RCC_FINDIV17CFGR U(0x1268)
+#define RCC_FINDIV18CFGR U(0x126C)
+#define RCC_FINDIV19CFGR U(0x1270)
+#define RCC_FINDIV20CFGR U(0x1274)
+#define RCC_FINDIV21CFGR U(0x1278)
+#define RCC_FINDIV22CFGR U(0x127C)
+#define RCC_FINDIV23CFGR U(0x1280)
+#define RCC_FINDIV24CFGR U(0x1284)
+#define RCC_FINDIV25CFGR U(0x1288)
+#define RCC_FINDIV26CFGR U(0x128C)
+#define RCC_FINDIV27CFGR U(0x1290)
+#define RCC_FINDIV28CFGR U(0x1294)
+#define RCC_FINDIV29CFGR U(0x1298)
+#define RCC_FINDIV30CFGR U(0x129C)
+#define RCC_FINDIV31CFGR U(0x12A0)
+#define RCC_FINDIV32CFGR U(0x12A4)
+#define RCC_FINDIV33CFGR U(0x12A8)
+#define RCC_FINDIV34CFGR U(0x12AC)
+#define RCC_FINDIV35CFGR U(0x12B0)
+#define RCC_FINDIV36CFGR U(0x12B4)
+#define RCC_FINDIV37CFGR U(0x12B8)
+#define RCC_FINDIV38CFGR U(0x12BC)
+#define RCC_FINDIV39CFGR U(0x12C0)
+#define RCC_FINDIV40CFGR U(0x12C4)
+#define RCC_FINDIV41CFGR U(0x12C8)
+#define RCC_FINDIV42CFGR U(0x12CC)
+#define RCC_FINDIV43CFGR U(0x12D0)
+#define RCC_FINDIV44CFGR U(0x12D4)
+#define RCC_FINDIV45CFGR U(0x12D8)
+#define RCC_FINDIV46CFGR U(0x12DC)
+#define RCC_FINDIV47CFGR U(0x12E0)
+#define RCC_FINDIV48CFGR U(0x12E4)
+#define RCC_FINDIV49CFGR U(0x12E8)
+#define RCC_FINDIV50CFGR U(0x12EC)
+#define RCC_FINDIV51CFGR U(0x12F0)
+#define RCC_FINDIV52CFGR U(0x12F4)
+#define RCC_FINDIV53CFGR U(0x12F8)
+#define RCC_FINDIV54CFGR U(0x12FC)
+#define RCC_FINDIV55CFGR U(0x1300)
+#define RCC_FINDIV56CFGR U(0x1304)
+#define RCC_FINDIV57CFGR U(0x1308)
+#define RCC_FINDIV58CFGR U(0x130C)
+#define RCC_FINDIV59CFGR U(0x1310)
+#define RCC_FINDIV60CFGR U(0x1314)
+#define RCC_FINDIV61CFGR U(0x1318)
+#define RCC_FINDIV62CFGR U(0x131C)
+#define RCC_FINDIV63CFGR U(0x1320)
+#define RCC_FINDIVSR1 U(0x1324)
+#define RCC_FINDIVSR2 U(0x1328)
+#define RCC_FCALCOBS0CFGR U(0x1340)
+#define RCC_FCALCOBS1CFGR U(0x1344)
+#define RCC_FCALCREFCFGR U(0x1348)
+#define RCC_FCALCCR1 U(0x134C)
+#define RCC_FCALCCR2 U(0x1354)
+#define RCC_FCALCSR U(0x1358)
+#define RCC_PLL4CFGR1 U(0x1360)
+#define RCC_PLL4CFGR2 U(0x1364)
+#define RCC_PLL4CFGR3 U(0x1368)
+#define RCC_PLL4CFGR4 U(0x136C)
+#define RCC_PLL4CFGR5 U(0x1370)
+#define RCC_PLL4CFGR6 U(0x1378)
+#define RCC_PLL4CFGR7 U(0x137C)
+#define RCC_PLL5CFGR1 U(0x1388)
+#define RCC_PLL5CFGR2 U(0x138C)
+#define RCC_PLL5CFGR3 U(0x1390)
+#define RCC_PLL5CFGR4 U(0x1394)
+#define RCC_PLL5CFGR5 U(0x1398)
+#define RCC_PLL5CFGR6 U(0x13A0)
+#define RCC_PLL5CFGR7 U(0x13A4)
+#define RCC_PLL6CFGR1 U(0x13B0)
+#define RCC_PLL6CFGR2 U(0x13B4)
+#define RCC_PLL6CFGR3 U(0x13B8)
+#define RCC_PLL6CFGR4 U(0x13BC)
+#define RCC_PLL6CFGR5 U(0x13C0)
+#define RCC_PLL6CFGR6 U(0x13C8)
+#define RCC_PLL6CFGR7 U(0x13CC)
+#define RCC_PLL7CFGR1 U(0x13D8)
+#define RCC_PLL7CFGR2 U(0x13DC)
+#define RCC_PLL7CFGR3 U(0x13E0)
+#define RCC_PLL7CFGR4 U(0x13E4)
+#define RCC_PLL7CFGR5 U(0x13E8)
+#define RCC_PLL7CFGR6 U(0x13F0)
+#define RCC_PLL7CFGR7 U(0x13F4)
+#define RCC_PLL8CFGR1 U(0x1400)
+#define RCC_PLL8CFGR2 U(0x1404)
+#define RCC_PLL8CFGR3 U(0x1408)
+#define RCC_PLL8CFGR4 U(0x140C)
+#define RCC_PLL8CFGR5 U(0x1410)
+#define RCC_PLL8CFGR6 U(0x1418)
+#define RCC_PLL8CFGR7 U(0x141C)
+#define RCC_VERR U(0xFFF4)
+#define RCC_IDR U(0xFFF8)
+#define RCC_SIDR U(0xFFFC)
+
+/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
+#define RCC_MP_ENCLRR_OFFSET U(4)
+
+/* RCC_SECCFGR3 register fields */
+#define RCC_SECCFGR3_SEC_MASK GENMASK_32(17, 0)
+#define RCC_SECCFGR3_SEC_SHIFT 0
+
+/* RCC_PRIVCFGR3 register fields */
+#define RCC_PRIVCFGR3_PRIV_MASK GENMASK_32(17, 0)
+#define RCC_PRIVCFGR3_PRIV_SHIFT 0
+
+/* RCC_RCFGLOCKR3 register fields */
+#define RCC_RCFGLOCKR3_RLOCK_MASK GENMASK_32(17, 0)
+#define RCC_RCFGLOCKR3_RLOCK_SHIFT 0
+
+/* RCC_R0CIDCFGR register fields */
+#define RCC_R0CIDCFGR_CFEN BIT(0)
+#define RCC_R0CIDCFGR_SEM_EN BIT(1)
+#define RCC_R0CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R0CIDCFGR_SCID_SHIFT 4
+#define RCC_R0CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R0CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R0SEMCR register fields */
+#define RCC_R0SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R0SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R0SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R1CIDCFGR register fields */
+#define RCC_R1CIDCFGR_CFEN BIT(0)
+#define RCC_R1CIDCFGR_SEM_EN BIT(1)
+#define RCC_R1CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R1CIDCFGR_SCID_SHIFT 4
+#define RCC_R1CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R1CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R1SEMCR register fields */
+#define RCC_R1SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R1SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R1SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R2CIDCFGR register fields */
+#define RCC_R2CIDCFGR_CFEN BIT(0)
+#define RCC_R2CIDCFGR_SEM_EN BIT(1)
+#define RCC_R2CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R2CIDCFGR_SCID_SHIFT 4
+#define RCC_R2CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R2CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R2SEMCR register fields */
+#define RCC_R2SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R2SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R2SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R3CIDCFGR register fields */
+#define RCC_R3CIDCFGR_CFEN BIT(0)
+#define RCC_R3CIDCFGR_SEM_EN BIT(1)
+#define RCC_R3CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R3CIDCFGR_SCID_SHIFT 4
+#define RCC_R3CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R3CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R3SEMCR register fields */
+#define RCC_R3SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R3SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R3SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R4CIDCFGR register fields */
+#define RCC_R4CIDCFGR_CFEN BIT(0)
+#define RCC_R4CIDCFGR_SEM_EN BIT(1)
+#define RCC_R4CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R4CIDCFGR_SCID_SHIFT 4
+#define RCC_R4CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R4CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R4SEMCR register fields */
+#define RCC_R4SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R4SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R4SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R5CIDCFGR register fields */
+#define RCC_R5CIDCFGR_CFEN BIT(0)
+#define RCC_R5CIDCFGR_SEM_EN BIT(1)
+#define RCC_R5CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R5CIDCFGR_SCID_SHIFT 4
+#define RCC_R5CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R5CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R5SEMCR register fields */
+#define RCC_R5SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R5SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R5SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R6CIDCFGR register fields */
+#define RCC_R6CIDCFGR_CFEN BIT(0)
+#define RCC_R6CIDCFGR_SEM_EN BIT(1)
+#define RCC_R6CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R6CIDCFGR_SCID_SHIFT 4
+#define RCC_R6CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R6CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R6SEMCR register fields */
+#define RCC_R6SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R6SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R6SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R7CIDCFGR register fields */
+#define RCC_R7CIDCFGR_CFEN BIT(0)
+#define RCC_R7CIDCFGR_SEM_EN BIT(1)
+#define RCC_R7CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R7CIDCFGR_SCID_SHIFT 4
+#define RCC_R7CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R7CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R7SEMCR register fields */
+#define RCC_R7SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R7SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R7SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R8CIDCFGR register fields */
+#define RCC_R8CIDCFGR_CFEN BIT(0)
+#define RCC_R8CIDCFGR_SEM_EN BIT(1)
+#define RCC_R8CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R8CIDCFGR_SCID_SHIFT 4
+#define RCC_R8CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R8CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R8SEMCR register fields */
+#define RCC_R8SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R8SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R8SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R9CIDCFGR register fields */
+#define RCC_R9CIDCFGR_CFEN BIT(0)
+#define RCC_R9CIDCFGR_SEM_EN BIT(1)
+#define RCC_R9CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R9CIDCFGR_SCID_SHIFT 4
+#define RCC_R9CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R9CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R9SEMCR register fields */
+#define RCC_R9SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R9SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R9SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R10CIDCFGR register fields */
+#define RCC_R10CIDCFGR_CFEN BIT(0)
+#define RCC_R10CIDCFGR_SEM_EN BIT(1)
+#define RCC_R10CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R10CIDCFGR_SCID_SHIFT 4
+#define RCC_R10CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R10CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R10SEMCR register fields */
+#define RCC_R10SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R10SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R10SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R11CIDCFGR register fields */
+#define RCC_R11CIDCFGR_CFEN BIT(0)
+#define RCC_R11CIDCFGR_SEM_EN BIT(1)
+#define RCC_R11CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R11CIDCFGR_SCID_SHIFT 4
+#define RCC_R11CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R11CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R11SEMCR register fields */
+#define RCC_R11SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R11SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R11SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R12CIDCFGR register fields */
+#define RCC_R12CIDCFGR_CFEN BIT(0)
+#define RCC_R12CIDCFGR_SEM_EN BIT(1)
+#define RCC_R12CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R12CIDCFGR_SCID_SHIFT 4
+#define RCC_R12CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R12CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R12SEMCR register fields */
+#define RCC_R12SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R12SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R12SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R13CIDCFGR register fields */
+#define RCC_R13CIDCFGR_CFEN BIT(0)
+#define RCC_R13CIDCFGR_SEM_EN BIT(1)
+#define RCC_R13CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R13CIDCFGR_SCID_SHIFT 4
+#define RCC_R13CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R13CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R13SEMCR register fields */
+#define RCC_R13SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R13SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R13SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R14CIDCFGR register fields */
+#define RCC_R14CIDCFGR_CFEN BIT(0)
+#define RCC_R14CIDCFGR_SEM_EN BIT(1)
+#define RCC_R14CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R14CIDCFGR_SCID_SHIFT 4
+#define RCC_R14CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R14CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R14SEMCR register fields */
+#define RCC_R14SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R14SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R14SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R15CIDCFGR register fields */
+#define RCC_R15CIDCFGR_CFEN BIT(0)
+#define RCC_R15CIDCFGR_SEM_EN BIT(1)
+#define RCC_R15CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R15CIDCFGR_SCID_SHIFT 4
+#define RCC_R15CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R15CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R15SEMCR register fields */
+#define RCC_R15SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R15SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R15SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R16CIDCFGR register fields */
+#define RCC_R16CIDCFGR_CFEN BIT(0)
+#define RCC_R16CIDCFGR_SEM_EN BIT(1)
+#define RCC_R16CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R16CIDCFGR_SCID_SHIFT 4
+#define RCC_R16CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R16CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R16SEMCR register fields */
+#define RCC_R16SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R16SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R16SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R17CIDCFGR register fields */
+#define RCC_R17CIDCFGR_CFEN BIT(0)
+#define RCC_R17CIDCFGR_SEM_EN BIT(1)
+#define RCC_R17CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R17CIDCFGR_SCID_SHIFT 4
+#define RCC_R17CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R17CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R17SEMCR register fields */
+#define RCC_R17SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R17SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R17SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R18CIDCFGR register fields */
+#define RCC_R18CIDCFGR_CFEN BIT(0)
+#define RCC_R18CIDCFGR_SEM_EN BIT(1)
+#define RCC_R18CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R18CIDCFGR_SCID_SHIFT 4
+#define RCC_R18CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R18CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R18SEMCR register fields */
+#define RCC_R18SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R18SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R18SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R19CIDCFGR register fields */
+#define RCC_R19CIDCFGR_CFEN BIT(0)
+#define RCC_R19CIDCFGR_SEM_EN BIT(1)
+#define RCC_R19CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R19CIDCFGR_SCID_SHIFT 4
+#define RCC_R19CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R19CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R19SEMCR register fields */
+#define RCC_R19SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R19SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R19SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R20CIDCFGR register fields */
+#define RCC_R20CIDCFGR_CFEN BIT(0)
+#define RCC_R20CIDCFGR_SEM_EN BIT(1)
+#define RCC_R20CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R20CIDCFGR_SCID_SHIFT 4
+#define RCC_R20CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R20CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R20SEMCR register fields */
+#define RCC_R20SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R20SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R20SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R21CIDCFGR register fields */
+#define RCC_R21CIDCFGR_CFEN BIT(0)
+#define RCC_R21CIDCFGR_SEM_EN BIT(1)
+#define RCC_R21CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R21CIDCFGR_SCID_SHIFT 4
+#define RCC_R21CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R21CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R21SEMCR register fields */
+#define RCC_R21SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R21SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R21SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R22CIDCFGR register fields */
+#define RCC_R22CIDCFGR_CFEN BIT(0)
+#define RCC_R22CIDCFGR_SEM_EN BIT(1)
+#define RCC_R22CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R22CIDCFGR_SCID_SHIFT 4
+#define RCC_R22CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R22CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R22SEMCR register fields */
+#define RCC_R22SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R22SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R22SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R23CIDCFGR register fields */
+#define RCC_R23CIDCFGR_CFEN BIT(0)
+#define RCC_R23CIDCFGR_SEM_EN BIT(1)
+#define RCC_R23CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R23CIDCFGR_SCID_SHIFT 4
+#define RCC_R23CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R23CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R23SEMCR register fields */
+#define RCC_R23SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R23SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R23SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R24CIDCFGR register fields */
+#define RCC_R24CIDCFGR_CFEN BIT(0)
+#define RCC_R24CIDCFGR_SEM_EN BIT(1)
+#define RCC_R24CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R24CIDCFGR_SCID_SHIFT 4
+#define RCC_R24CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R24CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R24SEMCR register fields */
+#define RCC_R24SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R24SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R24SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R25CIDCFGR register fields */
+#define RCC_R25CIDCFGR_CFEN BIT(0)
+#define RCC_R25CIDCFGR_SEM_EN BIT(1)
+#define RCC_R25CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R25CIDCFGR_SCID_SHIFT 4
+#define RCC_R25CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R25CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R25SEMCR register fields */
+#define RCC_R25SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R25SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R25SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R26CIDCFGR register fields */
+#define RCC_R26CIDCFGR_CFEN BIT(0)
+#define RCC_R26CIDCFGR_SEM_EN BIT(1)
+#define RCC_R26CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R26CIDCFGR_SCID_SHIFT 4
+#define RCC_R26CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R26CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R26SEMCR register fields */
+#define RCC_R26SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R26SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R26SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R27CIDCFGR register fields */
+#define RCC_R27CIDCFGR_CFEN BIT(0)
+#define RCC_R27CIDCFGR_SEM_EN BIT(1)
+#define RCC_R27CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R27CIDCFGR_SCID_SHIFT 4
+#define RCC_R27CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R27CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R27SEMCR register fields */
+#define RCC_R27SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R27SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R27SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R28CIDCFGR register fields */
+#define RCC_R28CIDCFGR_CFEN BIT(0)
+#define RCC_R28CIDCFGR_SEM_EN BIT(1)
+#define RCC_R28CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R28CIDCFGR_SCID_SHIFT 4
+#define RCC_R28CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R28CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R28SEMCR register fields */
+#define RCC_R28SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R28SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R28SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R29CIDCFGR register fields */
+#define RCC_R29CIDCFGR_CFEN BIT(0)
+#define RCC_R29CIDCFGR_SEM_EN BIT(1)
+#define RCC_R29CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R29CIDCFGR_SCID_SHIFT 4
+#define RCC_R29CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R29CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R29SEMCR register fields */
+#define RCC_R29SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R29SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R29SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R30CIDCFGR register fields */
+#define RCC_R30CIDCFGR_CFEN BIT(0)
+#define RCC_R30CIDCFGR_SEM_EN BIT(1)
+#define RCC_R30CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R30CIDCFGR_SCID_SHIFT 4
+#define RCC_R30CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R30CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R30SEMCR register fields */
+#define RCC_R30SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R30SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R30SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R31CIDCFGR register fields */
+#define RCC_R31CIDCFGR_CFEN BIT(0)
+#define RCC_R31CIDCFGR_SEM_EN BIT(1)
+#define RCC_R31CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R31CIDCFGR_SCID_SHIFT 4
+#define RCC_R31CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R31CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R31SEMCR register fields */
+#define RCC_R31SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R31SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R31SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R32CIDCFGR register fields */
+#define RCC_R32CIDCFGR_CFEN BIT(0)
+#define RCC_R32CIDCFGR_SEM_EN BIT(1)
+#define RCC_R32CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R32CIDCFGR_SCID_SHIFT 4
+#define RCC_R32CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R32CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R32SEMCR register fields */
+#define RCC_R32SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R32SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R32SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R33CIDCFGR register fields */
+#define RCC_R33CIDCFGR_CFEN BIT(0)
+#define RCC_R33CIDCFGR_SEM_EN BIT(1)
+#define RCC_R33CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R33CIDCFGR_SCID_SHIFT 4
+#define RCC_R33CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R33CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R33SEMCR register fields */
+#define RCC_R33SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R33SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R33SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R34CIDCFGR register fields */
+#define RCC_R34CIDCFGR_CFEN BIT(0)
+#define RCC_R34CIDCFGR_SEM_EN BIT(1)
+#define RCC_R34CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R34CIDCFGR_SCID_SHIFT 4
+#define RCC_R34CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R34CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R34SEMCR register fields */
+#define RCC_R34SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R34SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R34SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R35CIDCFGR register fields */
+#define RCC_R35CIDCFGR_CFEN BIT(0)
+#define RCC_R35CIDCFGR_SEM_EN BIT(1)
+#define RCC_R35CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R35CIDCFGR_SCID_SHIFT 4
+#define RCC_R35CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R35CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R35SEMCR register fields */
+#define RCC_R35SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R35SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R35SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R36CIDCFGR register fields */
+#define RCC_R36CIDCFGR_CFEN BIT(0)
+#define RCC_R36CIDCFGR_SEM_EN BIT(1)
+#define RCC_R36CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R36CIDCFGR_SCID_SHIFT 4
+#define RCC_R36CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R36CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R36SEMCR register fields */
+#define RCC_R36SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R36SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R36SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R37CIDCFGR register fields */
+#define RCC_R37CIDCFGR_CFEN BIT(0)
+#define RCC_R37CIDCFGR_SEM_EN BIT(1)
+#define RCC_R37CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R37CIDCFGR_SCID_SHIFT 4
+#define RCC_R37CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R37CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R37SEMCR register fields */
+#define RCC_R37SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R37SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R37SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R38CIDCFGR register fields */
+#define RCC_R38CIDCFGR_CFEN BIT(0)
+#define RCC_R38CIDCFGR_SEM_EN BIT(1)
+#define RCC_R38CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R38CIDCFGR_SCID_SHIFT 4
+#define RCC_R38CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R38CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R38SEMCR register fields */
+#define RCC_R38SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R38SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R38SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R39CIDCFGR register fields */
+#define RCC_R39CIDCFGR_CFEN BIT(0)
+#define RCC_R39CIDCFGR_SEM_EN BIT(1)
+#define RCC_R39CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R39CIDCFGR_SCID_SHIFT 4
+#define RCC_R39CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R39CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R39SEMCR register fields */
+#define RCC_R39SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R39SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R39SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R40CIDCFGR register fields */
+#define RCC_R40CIDCFGR_CFEN BIT(0)
+#define RCC_R40CIDCFGR_SEM_EN BIT(1)
+#define RCC_R40CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R40CIDCFGR_SCID_SHIFT 4
+#define RCC_R40CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R40CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R40SEMCR register fields */
+#define RCC_R40SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R40SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R40SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R41CIDCFGR register fields */
+#define RCC_R41CIDCFGR_CFEN BIT(0)
+#define RCC_R41CIDCFGR_SEM_EN BIT(1)
+#define RCC_R41CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R41CIDCFGR_SCID_SHIFT 4
+#define RCC_R41CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R41CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R41SEMCR register fields */
+#define RCC_R41SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R41SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R41SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R42CIDCFGR register fields */
+#define RCC_R42CIDCFGR_CFEN BIT(0)
+#define RCC_R42CIDCFGR_SEM_EN BIT(1)
+#define RCC_R42CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R42CIDCFGR_SCID_SHIFT 4
+#define RCC_R42CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R42CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R42SEMCR register fields */
+#define RCC_R42SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R42SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R42SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R43CIDCFGR register fields */
+#define RCC_R43CIDCFGR_CFEN BIT(0)
+#define RCC_R43CIDCFGR_SEM_EN BIT(1)
+#define RCC_R43CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R43CIDCFGR_SCID_SHIFT 4
+#define RCC_R43CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R43CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R43SEMCR register fields */
+#define RCC_R43SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R43SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R43SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R44CIDCFGR register fields */
+#define RCC_R44CIDCFGR_CFEN BIT(0)
+#define RCC_R44CIDCFGR_SEM_EN BIT(1)
+#define RCC_R44CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R44CIDCFGR_SCID_SHIFT 4
+#define RCC_R44CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R44CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R44SEMCR register fields */
+#define RCC_R44SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R44SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R44SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R45CIDCFGR register fields */
+#define RCC_R45CIDCFGR_CFEN BIT(0)
+#define RCC_R45CIDCFGR_SEM_EN BIT(1)
+#define RCC_R45CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R45CIDCFGR_SCID_SHIFT 4
+#define RCC_R45CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R45CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R45SEMCR register fields */
+#define RCC_R45SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R45SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R45SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R46CIDCFGR register fields */
+#define RCC_R46CIDCFGR_CFEN BIT(0)
+#define RCC_R46CIDCFGR_SEM_EN BIT(1)
+#define RCC_R46CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R46CIDCFGR_SCID_SHIFT 4
+#define RCC_R46CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R46CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R46SEMCR register fields */
+#define RCC_R46SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R46SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R46SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R47CIDCFGR register fields */
+#define RCC_R47CIDCFGR_CFEN BIT(0)
+#define RCC_R47CIDCFGR_SEM_EN BIT(1)
+#define RCC_R47CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R47CIDCFGR_SCID_SHIFT 4
+#define RCC_R47CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R47CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R47SEMCR register fields */
+#define RCC_R47SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R47SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R47SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R48CIDCFGR register fields */
+#define RCC_R48CIDCFGR_CFEN BIT(0)
+#define RCC_R48CIDCFGR_SEM_EN BIT(1)
+#define RCC_R48CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R48CIDCFGR_SCID_SHIFT 4
+#define RCC_R48CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R48CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R48SEMCR register fields */
+#define RCC_R48SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R48SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R48SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R49CIDCFGR register fields */
+#define RCC_R49CIDCFGR_CFEN BIT(0)
+#define RCC_R49CIDCFGR_SEM_EN BIT(1)
+#define RCC_R49CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R49CIDCFGR_SCID_SHIFT 4
+#define RCC_R49CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R49CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R49SEMCR register fields */
+#define RCC_R49SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R49SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R49SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R50CIDCFGR register fields */
+#define RCC_R50CIDCFGR_CFEN BIT(0)
+#define RCC_R50CIDCFGR_SEM_EN BIT(1)
+#define RCC_R50CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R50CIDCFGR_SCID_SHIFT 4
+#define RCC_R50CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R50CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R50SEMCR register fields */
+#define RCC_R50SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R50SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R50SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R51CIDCFGR register fields */
+#define RCC_R51CIDCFGR_CFEN BIT(0)
+#define RCC_R51CIDCFGR_SEM_EN BIT(1)
+#define RCC_R51CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R51CIDCFGR_SCID_SHIFT 4
+#define RCC_R51CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R51CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R51SEMCR register fields */
+#define RCC_R51SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R51SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R51SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R52CIDCFGR register fields */
+#define RCC_R52CIDCFGR_CFEN BIT(0)
+#define RCC_R52CIDCFGR_SEM_EN BIT(1)
+#define RCC_R52CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R52CIDCFGR_SCID_SHIFT 4
+#define RCC_R52CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R52CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R52SEMCR register fields */
+#define RCC_R52SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R52SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R52SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R53CIDCFGR register fields */
+#define RCC_R53CIDCFGR_CFEN BIT(0)
+#define RCC_R53CIDCFGR_SEM_EN BIT(1)
+#define RCC_R53CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R53CIDCFGR_SCID_SHIFT 4
+#define RCC_R53CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R53CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R53SEMCR register fields */
+#define RCC_R53SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R53SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R53SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R54CIDCFGR register fields */
+#define RCC_R54CIDCFGR_CFEN BIT(0)
+#define RCC_R54CIDCFGR_SEM_EN BIT(1)
+#define RCC_R54CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R54CIDCFGR_SCID_SHIFT 4
+#define RCC_R54CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R54CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R54SEMCR register fields */
+#define RCC_R54SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R54SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R54SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R55CIDCFGR register fields */
+#define RCC_R55CIDCFGR_CFEN BIT(0)
+#define RCC_R55CIDCFGR_SEM_EN BIT(1)
+#define RCC_R55CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R55CIDCFGR_SCID_SHIFT 4
+#define RCC_R55CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R55CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R55SEMCR register fields */
+#define RCC_R55SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R55SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R55SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R56CIDCFGR register fields */
+#define RCC_R56CIDCFGR_CFEN BIT(0)
+#define RCC_R56CIDCFGR_SEM_EN BIT(1)
+#define RCC_R56CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R56CIDCFGR_SCID_SHIFT 4
+#define RCC_R56CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R56CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R56SEMCR register fields */
+#define RCC_R56SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R56SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R56SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R57CIDCFGR register fields */
+#define RCC_R57CIDCFGR_CFEN BIT(0)
+#define RCC_R57CIDCFGR_SEM_EN BIT(1)
+#define RCC_R57CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R57CIDCFGR_SCID_SHIFT 4
+#define RCC_R57CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R57CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R57SEMCR register fields */
+#define RCC_R57SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R57SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R57SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R58CIDCFGR register fields */
+#define RCC_R58CIDCFGR_CFEN BIT(0)
+#define RCC_R58CIDCFGR_SEM_EN BIT(1)
+#define RCC_R58CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R58CIDCFGR_SCID_SHIFT 4
+#define RCC_R58CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R58CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R58SEMCR register fields */
+#define RCC_R58SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R58SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R58SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R59CIDCFGR register fields */
+#define RCC_R59CIDCFGR_CFEN BIT(0)
+#define RCC_R59CIDCFGR_SEM_EN BIT(1)
+#define RCC_R59CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R59CIDCFGR_SCID_SHIFT 4
+#define RCC_R59CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R59CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R59SEMCR register fields */
+#define RCC_R59SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R59SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R59SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R60CIDCFGR register fields */
+#define RCC_R60CIDCFGR_CFEN BIT(0)
+#define RCC_R60CIDCFGR_SEM_EN BIT(1)
+#define RCC_R60CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R60CIDCFGR_SCID_SHIFT 4
+#define RCC_R60CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R60CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R60SEMCR register fields */
+#define RCC_R60SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R60SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R60SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R61CIDCFGR register fields */
+#define RCC_R61CIDCFGR_CFEN BIT(0)
+#define RCC_R61CIDCFGR_SEM_EN BIT(1)
+#define RCC_R61CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R61CIDCFGR_SCID_SHIFT 4
+#define RCC_R61CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R61CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R61SEMCR register fields */
+#define RCC_R61SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R61SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R61SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R62CIDCFGR register fields */
+#define RCC_R62CIDCFGR_CFEN BIT(0)
+#define RCC_R62CIDCFGR_SEM_EN BIT(1)
+#define RCC_R62CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R62CIDCFGR_SCID_SHIFT 4
+#define RCC_R62CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R62CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R62SEMCR register fields */
+#define RCC_R62SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R62SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R62SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R63CIDCFGR register fields */
+#define RCC_R63CIDCFGR_CFEN BIT(0)
+#define RCC_R63CIDCFGR_SEM_EN BIT(1)
+#define RCC_R63CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R63CIDCFGR_SCID_SHIFT 4
+#define RCC_R63CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R63CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R63SEMCR register fields */
+#define RCC_R63SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R63SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R63SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R64CIDCFGR register fields */
+#define RCC_R64CIDCFGR_CFEN BIT(0)
+#define RCC_R64CIDCFGR_SEM_EN BIT(1)
+#define RCC_R64CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R64CIDCFGR_SCID_SHIFT 4
+#define RCC_R64CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R64CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R64SEMCR register fields */
+#define RCC_R64SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R64SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R64SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R65CIDCFGR register fields */
+#define RCC_R65CIDCFGR_CFEN BIT(0)
+#define RCC_R65CIDCFGR_SEM_EN BIT(1)
+#define RCC_R65CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R65CIDCFGR_SCID_SHIFT 4
+#define RCC_R65CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R65CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R65SEMCR register fields */
+#define RCC_R65SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R65SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R65SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R66CIDCFGR register fields */
+#define RCC_R66CIDCFGR_CFEN BIT(0)
+#define RCC_R66CIDCFGR_SEM_EN BIT(1)
+#define RCC_R66CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R66CIDCFGR_SCID_SHIFT 4
+#define RCC_R66CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R66CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R66SEMCR register fields */
+#define RCC_R66SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R66SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R66SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R67CIDCFGR register fields */
+#define RCC_R67CIDCFGR_CFEN BIT(0)
+#define RCC_R67CIDCFGR_SEM_EN BIT(1)
+#define RCC_R67CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R67CIDCFGR_SCID_SHIFT 4
+#define RCC_R67CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R67CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R67SEMCR register fields */
+#define RCC_R67SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R67SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R67SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R68CIDCFGR register fields */
+#define RCC_R68CIDCFGR_CFEN BIT(0)
+#define RCC_R68CIDCFGR_SEM_EN BIT(1)
+#define RCC_R68CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R68CIDCFGR_SCID_SHIFT 4
+#define RCC_R68CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R68CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R68SEMCR register fields */
+#define RCC_R68SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R68SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R68SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R69CIDCFGR register fields */
+#define RCC_R69CIDCFGR_CFEN BIT(0)
+#define RCC_R69CIDCFGR_SEM_EN BIT(1)
+#define RCC_R69CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R69CIDCFGR_SCID_SHIFT 4
+#define RCC_R69CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R69CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R69SEMCR register fields */
+#define RCC_R69SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R69SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R69SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R70CIDCFGR register fields */
+#define RCC_R70CIDCFGR_CFEN BIT(0)
+#define RCC_R70CIDCFGR_SEM_EN BIT(1)
+#define RCC_R70CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R70CIDCFGR_SCID_SHIFT 4
+#define RCC_R70CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R70CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R70SEMCR register fields */
+#define RCC_R70SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R70SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R70SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R71CIDCFGR register fields */
+#define RCC_R71CIDCFGR_CFEN BIT(0)
+#define RCC_R71CIDCFGR_SEM_EN BIT(1)
+#define RCC_R71CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R71CIDCFGR_SCID_SHIFT 4
+#define RCC_R71CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R71CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R71SEMCR register fields */
+#define RCC_R71SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R71SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R71SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R72CIDCFGR register fields */
+#define RCC_R72CIDCFGR_CFEN BIT(0)
+#define RCC_R72CIDCFGR_SEM_EN BIT(1)
+#define RCC_R72CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R72CIDCFGR_SCID_SHIFT 4
+#define RCC_R72CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R72CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R72SEMCR register fields */
+#define RCC_R72SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R72SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R72SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R73CIDCFGR register fields */
+#define RCC_R73CIDCFGR_CFEN BIT(0)
+#define RCC_R73CIDCFGR_SEM_EN BIT(1)
+#define RCC_R73CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R73CIDCFGR_SCID_SHIFT 4
+#define RCC_R73CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R73CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R73SEMCR register fields */
+#define RCC_R73SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R73SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R73SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R74CIDCFGR register fields */
+#define RCC_R74CIDCFGR_CFEN BIT(0)
+#define RCC_R74CIDCFGR_SEM_EN BIT(1)
+#define RCC_R74CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R74CIDCFGR_SCID_SHIFT 4
+#define RCC_R74CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R74CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R74SEMCR register fields */
+#define RCC_R74SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R74SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R74SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R75CIDCFGR register fields */
+#define RCC_R75CIDCFGR_CFEN BIT(0)
+#define RCC_R75CIDCFGR_SEM_EN BIT(1)
+#define RCC_R75CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R75CIDCFGR_SCID_SHIFT 4
+#define RCC_R75CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R75CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R75SEMCR register fields */
+#define RCC_R75SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R75SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R75SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R76CIDCFGR register fields */
+#define RCC_R76CIDCFGR_CFEN BIT(0)
+#define RCC_R76CIDCFGR_SEM_EN BIT(1)
+#define RCC_R76CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R76CIDCFGR_SCID_SHIFT 4
+#define RCC_R76CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R76CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R76SEMCR register fields */
+#define RCC_R76SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R76SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R76SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R77CIDCFGR register fields */
+#define RCC_R77CIDCFGR_CFEN BIT(0)
+#define RCC_R77CIDCFGR_SEM_EN BIT(1)
+#define RCC_R77CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R77CIDCFGR_SCID_SHIFT 4
+#define RCC_R77CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R77CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R77SEMCR register fields */
+#define RCC_R77SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R77SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R77SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R78CIDCFGR register fields */
+#define RCC_R78CIDCFGR_CFEN BIT(0)
+#define RCC_R78CIDCFGR_SEM_EN BIT(1)
+#define RCC_R78CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R78CIDCFGR_SCID_SHIFT 4
+#define RCC_R78CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R78CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R78SEMCR register fields */
+#define RCC_R78SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R78SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R78SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R79CIDCFGR register fields */
+#define RCC_R79CIDCFGR_CFEN BIT(0)
+#define RCC_R79CIDCFGR_SEM_EN BIT(1)
+#define RCC_R79CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R79CIDCFGR_SCID_SHIFT 4
+#define RCC_R79CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R79CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R79SEMCR register fields */
+#define RCC_R79SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R79SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R79SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R80CIDCFGR register fields */
+#define RCC_R80CIDCFGR_CFEN BIT(0)
+#define RCC_R80CIDCFGR_SEM_EN BIT(1)
+#define RCC_R80CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R80CIDCFGR_SCID_SHIFT 4
+#define RCC_R80CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R80CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R80SEMCR register fields */
+#define RCC_R80SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R80SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R80SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R81CIDCFGR register fields */
+#define RCC_R81CIDCFGR_CFEN BIT(0)
+#define RCC_R81CIDCFGR_SEM_EN BIT(1)
+#define RCC_R81CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R81CIDCFGR_SCID_SHIFT 4
+#define RCC_R81CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R81CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R81SEMCR register fields */
+#define RCC_R81SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R81SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R81SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R82CIDCFGR register fields */
+#define RCC_R82CIDCFGR_CFEN BIT(0)
+#define RCC_R82CIDCFGR_SEM_EN BIT(1)
+#define RCC_R82CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R82CIDCFGR_SCID_SHIFT 4
+#define RCC_R82CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R82CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R82SEMCR register fields */
+#define RCC_R82SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R82SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R82SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R83CIDCFGR register fields */
+#define RCC_R83CIDCFGR_CFEN BIT(0)
+#define RCC_R83CIDCFGR_SEM_EN BIT(1)
+#define RCC_R83CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R83CIDCFGR_SCID_SHIFT 4
+#define RCC_R83CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R83CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R83SEMCR register fields */
+#define RCC_R83SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R83SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R83SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R84CIDCFGR register fields */
+#define RCC_R84CIDCFGR_CFEN BIT(0)
+#define RCC_R84CIDCFGR_SEM_EN BIT(1)
+#define RCC_R84CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R84CIDCFGR_SCID_SHIFT 4
+#define RCC_R84CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R84CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R84SEMCR register fields */
+#define RCC_R84SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R84SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R84SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R85CIDCFGR register fields */
+#define RCC_R85CIDCFGR_CFEN BIT(0)
+#define RCC_R85CIDCFGR_SEM_EN BIT(1)
+#define RCC_R85CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R85CIDCFGR_SCID_SHIFT 4
+#define RCC_R85CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R85CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R85SEMCR register fields */
+#define RCC_R85SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R85SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R85SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R86CIDCFGR register fields */
+#define RCC_R86CIDCFGR_CFEN BIT(0)
+#define RCC_R86CIDCFGR_SEM_EN BIT(1)
+#define RCC_R86CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R86CIDCFGR_SCID_SHIFT 4
+#define RCC_R86CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R86CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R86SEMCR register fields */
+#define RCC_R86SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R86SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R86SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R87CIDCFGR register fields */
+#define RCC_R87CIDCFGR_CFEN BIT(0)
+#define RCC_R87CIDCFGR_SEM_EN BIT(1)
+#define RCC_R87CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R87CIDCFGR_SCID_SHIFT 4
+#define RCC_R87CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R87CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R87SEMCR register fields */
+#define RCC_R87SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R87SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R87SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R88CIDCFGR register fields */
+#define RCC_R88CIDCFGR_CFEN BIT(0)
+#define RCC_R88CIDCFGR_SEM_EN BIT(1)
+#define RCC_R88CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R88CIDCFGR_SCID_SHIFT 4
+#define RCC_R88CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R88CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R88SEMCR register fields */
+#define RCC_R88SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R88SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R88SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R89CIDCFGR register fields */
+#define RCC_R89CIDCFGR_CFEN BIT(0)
+#define RCC_R89CIDCFGR_SEM_EN BIT(1)
+#define RCC_R89CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R89CIDCFGR_SCID_SHIFT 4
+#define RCC_R89CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R89CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R89SEMCR register fields */
+#define RCC_R89SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R89SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R89SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R90CIDCFGR register fields */
+#define RCC_R90CIDCFGR_CFEN BIT(0)
+#define RCC_R90CIDCFGR_SEM_EN BIT(1)
+#define RCC_R90CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R90CIDCFGR_SCID_SHIFT 4
+#define RCC_R90CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R90CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R90SEMCR register fields */
+#define RCC_R90SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R90SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R90SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R91CIDCFGR register fields */
+#define RCC_R91CIDCFGR_CFEN BIT(0)
+#define RCC_R91CIDCFGR_SEM_EN BIT(1)
+#define RCC_R91CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R91CIDCFGR_SCID_SHIFT 4
+#define RCC_R91CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R91CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R91SEMCR register fields */
+#define RCC_R91SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R91SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R91SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R92CIDCFGR register fields */
+#define RCC_R92CIDCFGR_CFEN BIT(0)
+#define RCC_R92CIDCFGR_SEM_EN BIT(1)
+#define RCC_R92CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R92CIDCFGR_SCID_SHIFT 4
+#define RCC_R92CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R92CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R92SEMCR register fields */
+#define RCC_R92SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R92SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R92SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R93CIDCFGR register fields */
+#define RCC_R93CIDCFGR_CFEN BIT(0)
+#define RCC_R93CIDCFGR_SEM_EN BIT(1)
+#define RCC_R93CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R93CIDCFGR_SCID_SHIFT 4
+#define RCC_R93CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R93CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R93SEMCR register fields */
+#define RCC_R93SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R93SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R93SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R94CIDCFGR register fields */
+#define RCC_R94CIDCFGR_CFEN BIT(0)
+#define RCC_R94CIDCFGR_SEM_EN BIT(1)
+#define RCC_R94CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R94CIDCFGR_SCID_SHIFT 4
+#define RCC_R94CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R94CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R94SEMCR register fields */
+#define RCC_R94SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R94SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R94SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R95CIDCFGR register fields */
+#define RCC_R95CIDCFGR_CFEN BIT(0)
+#define RCC_R95CIDCFGR_SEM_EN BIT(1)
+#define RCC_R95CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R95CIDCFGR_SCID_SHIFT 4
+#define RCC_R95CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R95CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R95SEMCR register fields */
+#define RCC_R95SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R95SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R95SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R96CIDCFGR register fields */
+#define RCC_R96CIDCFGR_CFEN BIT(0)
+#define RCC_R96CIDCFGR_SEM_EN BIT(1)
+#define RCC_R96CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R96CIDCFGR_SCID_SHIFT 4
+#define RCC_R96CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R96CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R96SEMCR register fields */
+#define RCC_R96SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R96SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R96SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R97CIDCFGR register fields */
+#define RCC_R97CIDCFGR_CFEN BIT(0)
+#define RCC_R97CIDCFGR_SEM_EN BIT(1)
+#define RCC_R97CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R97CIDCFGR_SCID_SHIFT 4
+#define RCC_R97CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R97CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R97SEMCR register fields */
+#define RCC_R97SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R97SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R97SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R98CIDCFGR register fields */
+#define RCC_R98CIDCFGR_CFEN BIT(0)
+#define RCC_R98CIDCFGR_SEM_EN BIT(1)
+#define RCC_R98CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R98CIDCFGR_SCID_SHIFT 4
+#define RCC_R98CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R98CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R98SEMCR register fields */
+#define RCC_R98SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R98SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R98SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R99CIDCFGR register fields */
+#define RCC_R99CIDCFGR_CFEN BIT(0)
+#define RCC_R99CIDCFGR_SEM_EN BIT(1)
+#define RCC_R99CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R99CIDCFGR_SCID_SHIFT 4
+#define RCC_R99CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R99CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R99SEMCR register fields */
+#define RCC_R99SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R99SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R99SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R100CIDCFGR register fields */
+#define RCC_R100CIDCFGR_CFEN BIT(0)
+#define RCC_R100CIDCFGR_SEM_EN BIT(1)
+#define RCC_R100CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R100CIDCFGR_SCID_SHIFT 4
+#define RCC_R100CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R100CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R100SEMCR register fields */
+#define RCC_R100SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R100SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R100SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R101CIDCFGR register fields */
+#define RCC_R101CIDCFGR_CFEN BIT(0)
+#define RCC_R101CIDCFGR_SEM_EN BIT(1)
+#define RCC_R101CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R101CIDCFGR_SCID_SHIFT 4
+#define RCC_R101CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R101CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R101SEMCR register fields */
+#define RCC_R101SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R101SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R101SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R102CIDCFGR register fields */
+#define RCC_R102CIDCFGR_CFEN BIT(0)
+#define RCC_R102CIDCFGR_SEM_EN BIT(1)
+#define RCC_R102CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R102CIDCFGR_SCID_SHIFT 4
+#define RCC_R102CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R102CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R102SEMCR register fields */
+#define RCC_R102SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R102SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R102SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R103CIDCFGR register fields */
+#define RCC_R103CIDCFGR_CFEN BIT(0)
+#define RCC_R103CIDCFGR_SEM_EN BIT(1)
+#define RCC_R103CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R103CIDCFGR_SCID_SHIFT 4
+#define RCC_R103CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R103CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R103SEMCR register fields */
+#define RCC_R103SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R103SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R103SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R104CIDCFGR register fields */
+#define RCC_R104CIDCFGR_CFEN BIT(0)
+#define RCC_R104CIDCFGR_SEM_EN BIT(1)
+#define RCC_R104CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R104CIDCFGR_SCID_SHIFT 4
+#define RCC_R104CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R104CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R104SEMCR register fields */
+#define RCC_R104SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R104SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R104SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R105CIDCFGR register fields */
+#define RCC_R105CIDCFGR_CFEN BIT(0)
+#define RCC_R105CIDCFGR_SEM_EN BIT(1)
+#define RCC_R105CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R105CIDCFGR_SCID_SHIFT 4
+#define RCC_R105CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R105CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R105SEMCR register fields */
+#define RCC_R105SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R105SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R105SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R106CIDCFGR register fields */
+#define RCC_R106CIDCFGR_CFEN BIT(0)
+#define RCC_R106CIDCFGR_SEM_EN BIT(1)
+#define RCC_R106CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R106CIDCFGR_SCID_SHIFT 4
+#define RCC_R106CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R106CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R106SEMCR register fields */
+#define RCC_R106SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R106SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R106SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R107CIDCFGR register fields */
+#define RCC_R107CIDCFGR_CFEN BIT(0)
+#define RCC_R107CIDCFGR_SEM_EN BIT(1)
+#define RCC_R107CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R107CIDCFGR_SCID_SHIFT 4
+#define RCC_R107CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R107CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R107SEMCR register fields */
+#define RCC_R107SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R107SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R107SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R108CIDCFGR register fields */
+#define RCC_R108CIDCFGR_CFEN BIT(0)
+#define RCC_R108CIDCFGR_SEM_EN BIT(1)
+#define RCC_R108CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R108CIDCFGR_SCID_SHIFT 4
+#define RCC_R108CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R108CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R108SEMCR register fields */
+#define RCC_R108SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R108SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R108SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R109CIDCFGR register fields */
+#define RCC_R109CIDCFGR_CFEN BIT(0)
+#define RCC_R109CIDCFGR_SEM_EN BIT(1)
+#define RCC_R109CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R109CIDCFGR_SCID_SHIFT 4
+#define RCC_R109CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R109CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R109SEMCR register fields */
+#define RCC_R109SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R109SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R109SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R110CIDCFGR register fields */
+#define RCC_R110CIDCFGR_CFEN BIT(0)
+#define RCC_R110CIDCFGR_SEM_EN BIT(1)
+#define RCC_R110CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R110CIDCFGR_SCID_SHIFT 4
+#define RCC_R110CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R110CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R110SEMCR register fields */
+#define RCC_R110SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R110SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R110SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R111CIDCFGR register fields */
+#define RCC_R111CIDCFGR_CFEN BIT(0)
+#define RCC_R111CIDCFGR_SEM_EN BIT(1)
+#define RCC_R111CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R111CIDCFGR_SCID_SHIFT 4
+#define RCC_R111CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R111CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R111SEMCR register fields */
+#define RCC_R111SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R111SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R111SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R112CIDCFGR register fields */
+#define RCC_R112CIDCFGR_CFEN BIT(0)
+#define RCC_R112CIDCFGR_SEM_EN BIT(1)
+#define RCC_R112CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R112CIDCFGR_SCID_SHIFT 4
+#define RCC_R112CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R112CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R112SEMCR register fields */
+#define RCC_R112SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R112SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R112SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R113CIDCFGR register fields */
+#define RCC_R113CIDCFGR_CFEN BIT(0)
+#define RCC_R113CIDCFGR_SEM_EN BIT(1)
+#define RCC_R113CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R113CIDCFGR_SCID_SHIFT 4
+#define RCC_R113CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R113CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R113SEMCR register fields */
+#define RCC_R113SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R113SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R113SEMCR_SEMCID_SHIFT 4
+
+/* RCC_RxCIDCFGR register fields */
+#define RCC_RxCIDCFGR_CFEN BIT(0)
+#define RCC_RxCIDCFGR_SEM_EN BIT(1)
+#define RCC_RxCIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_RxCIDCFGR_SCID_SHIFT 4
+#define RCC_RxCIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_RxCIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_RxSEMCR register fields */
+#define RCC_RxSEMCR_SEM_MUTEX BIT(0)
+#define RCC_RxSEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_RxSEMCR_SEMCID_SHIFT 4
+
+/* RCC_GRSTCSETR register fields */
+#define RCC_GRSTCSETR_SYSRST BIT(0)
+
+/* RCC_C1RSTCSETR register fields */
+#define RCC_C1RSTCSETR_C1RST BIT(0)
+
+/* RCC_C2RSTCSETR register fields */
+#define RCC_C2RSTCSETR_C2RST BIT(0)
+
+/* RCC_CxRSTCSETR register fields */
+#define RCC_CxRSTCSETR_CxRST BIT(0)
+
+/* RCC_HWRSTSCLRR register fields */
+#define RCC_HWRSTSCLRR_PORRSTF BIT(0)
+#define RCC_HWRSTSCLRR_BORRSTF BIT(1)
+#define RCC_HWRSTSCLRR_PADRSTF BIT(2)
+#define RCC_HWRSTSCLRR_HCSSRSTF BIT(3)
+#define RCC_HWRSTSCLRR_VCORERSTF BIT(4)
+#define RCC_HWRSTSCLRR_SYSC1RSTF BIT(5)
+#define RCC_HWRSTSCLRR_SYSC2RSTF BIT(6)
+#define RCC_HWRSTSCLRR_IWDG1SYSRSTF BIT(7)
+#define RCC_HWRSTSCLRR_IWDG2SYSRSTF BIT(8)
+#define RCC_HWRSTSCLRR_IWDG3SYSRSTF BIT(9)
+#define RCC_HWRSTSCLRR_IWDG4SYSRSTF BIT(10)
+#define RCC_HWRSTSCLRR_RETCRCERRRSTF BIT(12)
+#define RCC_HWRSTSCLRR_RETECCFAILCRCRSTF BIT(13)
+#define RCC_HWRSTSCLRR_RETECCFAILRESTRSTF BIT(14)
+
+/* RCC_C1HWRSTSCLRR register fields */
+#define RCC_C1HWRSTSCLRR_VCPURSTF BIT(0)
+#define RCC_C1HWRSTSCLRR_C1RSTF BIT(1)
+
+/* RCC_C2HWRSTSCLRR register fields */
+#define RCC_C2HWRSTSCLRR_C2RSTF BIT(0)
+
+/* RCC_C1BOOTRSTSSETR register fields */
+#define RCC_C1BOOTRSTSSETR_PORRSTF BIT(0)
+#define RCC_C1BOOTRSTSSETR_BORRSTF BIT(1)
+#define RCC_C1BOOTRSTSSETR_PADRSTF BIT(2)
+#define RCC_C1BOOTRSTSSETR_HCSSRSTF BIT(3)
+#define RCC_C1BOOTRSTSSETR_VCORERSTF BIT(4)
+#define RCC_C1BOOTRSTSSETR_VCPURSTF BIT(5)
+#define RCC_C1BOOTRSTSSETR_SYSC1RSTF BIT(6)
+#define RCC_C1BOOTRSTSSETR_SYSC2RSTF BIT(7)
+#define RCC_C1BOOTRSTSSETR_IWDG1SYSRSTF BIT(8)
+#define RCC_C1BOOTRSTSSETR_IWDG2SYSRSTF BIT(9)
+#define RCC_C1BOOTRSTSSETR_IWDG3SYSRSTF BIT(10)
+#define RCC_C1BOOTRSTSSETR_IWDG4SYSRSTF BIT(11)
+#define RCC_C1BOOTRSTSSETR_C1RSTF BIT(13)
+#define RCC_C1BOOTRSTSSETR_RETCRCERRRSTF BIT(17)
+#define RCC_C1BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18)
+#define RCC_C1BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19)
+#define RCC_C1BOOTRSTSSETR_STBYC1RSTF BIT(20)
+#define RCC_C1BOOTRSTSSETR_D1STBYRSTF BIT(22)
+#define RCC_C1BOOTRSTSSETR_D2STBYRSTF BIT(23)
+
+/* RCC_C1BOOTRSTSCLRR register fields */
+#define RCC_C1BOOTRSTSCLRR_PORRSTF BIT(0)
+#define RCC_C1BOOTRSTSCLRR_BORRSTF BIT(1)
+#define RCC_C1BOOTRSTSCLRR_PADRSTF BIT(2)
+#define RCC_C1BOOTRSTSCLRR_HCSSRSTF BIT(3)
+#define RCC_C1BOOTRSTSCLRR_VCORERSTF BIT(4)
+#define RCC_C1BOOTRSTSCLRR_VCPURSTF BIT(5)
+#define RCC_C1BOOTRSTSCLRR_SYSC1RSTF BIT(6)
+#define RCC_C1BOOTRSTSCLRR_SYSC2RSTF BIT(7)
+#define RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8)
+#define RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9)
+#define RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10)
+#define RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11)
+#define RCC_C1BOOTRSTSCLRR_C1RSTF BIT(13)
+#define RCC_C1BOOTRSTSCLRR_RETCRCERRRSTF BIT(17)
+#define RCC_C1BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18)
+#define RCC_C1BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19)
+#define RCC_C1BOOTRSTSCLRR_STBYC1RSTF BIT(20)
+#define RCC_C1BOOTRSTSCLRR_D1STBYRSTF BIT(22)
+#define RCC_C1BOOTRSTSCLRR_D2STBYRSTF BIT(23)
+
+#define RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF (RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF)
+
+/* RCC_C2BOOTRSTSSETR register fields */
+#define RCC_C2BOOTRSTSSETR_PORRSTF BIT(0)
+#define RCC_C2BOOTRSTSSETR_BORRSTF BIT(1)
+#define RCC_C2BOOTRSTSSETR_PADRSTF BIT(2)
+#define RCC_C2BOOTRSTSSETR_HCSSRSTF BIT(3)
+#define RCC_C2BOOTRSTSSETR_VCORERSTF BIT(4)
+#define RCC_C2BOOTRSTSSETR_SYSC1RSTF BIT(6)
+#define RCC_C2BOOTRSTSSETR_SYSC2RSTF BIT(7)
+#define RCC_C2BOOTRSTSSETR_IWDG1SYSRSTF BIT(8)
+#define RCC_C2BOOTRSTSSETR_IWDG2SYSRSTF BIT(9)
+#define RCC_C2BOOTRSTSSETR_IWDG3SYSRSTF BIT(10)
+#define RCC_C2BOOTRSTSSETR_IWDG4SYSRSTF BIT(11)
+#define RCC_C2BOOTRSTSSETR_C2RSTF BIT(14)
+#define RCC_C2BOOTRSTSSETR_RETCRCERRRSTF BIT(17)
+#define RCC_C2BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18)
+#define RCC_C2BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19)
+#define RCC_C2BOOTRSTSSETR_STBYC2RSTF BIT(21)
+#define RCC_C2BOOTRSTSSETR_D2STBYRSTF BIT(23)
+
+/* RCC_C2BOOTRSTSCLRR register fields */
+#define RCC_C2BOOTRSTSCLRR_PORRSTF BIT(0)
+#define RCC_C2BOOTRSTSCLRR_BORRSTF BIT(1)
+#define RCC_C2BOOTRSTSCLRR_PADRSTF BIT(2)
+#define RCC_C2BOOTRSTSCLRR_HCSSRSTF BIT(3)
+#define RCC_C2BOOTRSTSCLRR_VCORERSTF BIT(4)
+#define RCC_C2BOOTRSTSCLRR_SYSC1RSTF BIT(6)
+#define RCC_C2BOOTRSTSCLRR_SYSC2RSTF BIT(7)
+#define RCC_C2BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8)
+#define RCC_C2BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9)
+#define RCC_C2BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10)
+#define RCC_C2BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11)
+#define RCC_C2BOOTRSTSCLRR_C2RSTF BIT(14)
+#define RCC_C2BOOTRSTSCLRR_RETCRCERRRSTF BIT(17)
+#define RCC_C2BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18)
+#define RCC_C2BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19)
+#define RCC_C2BOOTRSTSCLRR_STBYC2RSTF BIT(21)
+#define RCC_C2BOOTRSTSCLRR_D2STBYRSTF BIT(23)
+
+/* RCC_C1SREQSETR register fields */
+#define RCC_C1SREQSETR_STPREQ_P0 BIT(0)
+#define RCC_C1SREQSETR_STPREQ_P1 BIT(1)
+#define RCC_C1SREQSETR_STPREQ_MASK GENMASK_32(1, 0)
+#define RCC_C1SREQSETR_ESLPREQ BIT(16)
+
+/* RCC_C1SREQCLRR register fields */
+#define RCC_C1SREQCLRR_STPREQ_P0 BIT(0)
+#define RCC_C1SREQCLRR_STPREQ_P1 BIT(1)
+#define RCC_C1SREQCLRR_STPREQ_MASK GENMASK_32(1, 0)
+#define RCC_C1SREQCLRR_ESLPREQ BIT(16)
+
+/* RCC_CPUBOOTCR register fields */
+#define RCC_CPUBOOTCR_BOOT_CPU2 BIT(0)
+#define RCC_CPUBOOTCR_BOOT_CPU1 BIT(1)
+
+/* RCC_STBYBOOTCR register fields */
+#define RCC_STBYBOOTCR_CPU_BEN_SEL BIT(1)
+#define RCC_STBYBOOTCR_COLD_CPU2 BIT(2)
+#define RCC_STBYBOOTCR_CPU2_HW_BEN BIT(4)
+#define RCC_STBYBOOTCR_CPU1_HW_BEN BIT(5)
+#define RCC_STBYBOOTCR_RET_CRCERR_RSTEN BIT(8)
+
+/* RCC_LEGBOOTCR register fields */
+#define RCC_LEGBOOTCR_LEGACY_BEN BIT(0)
+
+/* RCC_BDCR register fields */
+#define RCC_BDCR_LSEON BIT(0)
+#define RCC_BDCR_LSEBYP BIT(1)
+#define RCC_BDCR_LSERDY BIT(2)
+#define RCC_BDCR_LSEDIGBYP BIT(3)
+#define RCC_BDCR_LSEDRV_MASK GENMASK_32(5, 4)
+#define RCC_BDCR_LSEDRV_SHIFT 4
+#define RCC_BDCR_LSECSSON BIT(6)
+#define RCC_BDCR_LSEGFON BIT(7)
+#define RCC_BDCR_LSECSSD BIT(8)
+#define RCC_BDCR_RTCSRC_MASK GENMASK_32(17, 16)
+#define RCC_BDCR_RTCSRC_SHIFT 16
+#define RCC_BDCR_RTCCKEN BIT(20)
+#define RCC_BDCR_VSWRST BIT(31)
+
+/* RCC_RDCR register fields */
+#define RCC_RDCR_MRD_MASK GENMASK_32(20, 16)
+#define RCC_RDCR_MRD_SHIFT 16
+#define RCC_RDCR_EADLY_MASK GENMASK_32(27, 24)
+#define RCC_RDCR_EADLY_SHIFT 24
+
+/* RCC_C1MSRDCR register fields */
+#define RCC_C1MSRDCR_C1MSRD_MASK GENMASK_32(4, 0)
+#define RCC_C1MSRDCR_C1MSRD_SHIFT 0
+#define RCC_C1MSRDCR_C1MSRST BIT(8)
+
+/* RCC_PWRLPDLYCR register fields */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK_32(21, 0)
+#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0
+#define RCC_PWRLPDLYCR_CPU2TMPSKP BIT(24)
+
+/* RCC_C1CIESETR register fields */
+#define RCC_C1CIESETR_LSIRDYIE BIT(0)
+#define RCC_C1CIESETR_LSERDYIE BIT(1)
+#define RCC_C1CIESETR_HSIRDYIE BIT(2)
+#define RCC_C1CIESETR_HSERDYIE BIT(3)
+#define RCC_C1CIESETR_MSIRDYIE BIT(4)
+#define RCC_C1CIESETR_PLL1RDYIE BIT(5)
+#define RCC_C1CIESETR_PLL2RDYIE BIT(6)
+#define RCC_C1CIESETR_PLL3RDYIE BIT(7)
+#define RCC_C1CIESETR_PLL4RDYIE BIT(8)
+#define RCC_C1CIESETR_PLL5RDYIE BIT(9)
+#define RCC_C1CIESETR_PLL6RDYIE BIT(10)
+#define RCC_C1CIESETR_PLL7RDYIE BIT(11)
+#define RCC_C1CIESETR_PLL8RDYIE BIT(12)
+#define RCC_C1CIESETR_LSECSSIE BIT(16)
+#define RCC_C1CIESETR_WKUPIE BIT(20)
+
+/* RCC_C1CIFCLRR register fields */
+#define RCC_C1CIFCLRR_LSIRDYF BIT(0)
+#define RCC_C1CIFCLRR_LSERDYF BIT(1)
+#define RCC_C1CIFCLRR_HSIRDYF BIT(2)
+#define RCC_C1CIFCLRR_HSERDYF BIT(3)
+#define RCC_C1CIFCLRR_MSIRDYF BIT(4)
+#define RCC_C1CIFCLRR_PLL1RDYF BIT(5)
+#define RCC_C1CIFCLRR_PLL2RDYF BIT(6)
+#define RCC_C1CIFCLRR_PLL3RDYF BIT(7)
+#define RCC_C1CIFCLRR_PLL4RDYF BIT(8)
+#define RCC_C1CIFCLRR_PLL5RDYF BIT(9)
+#define RCC_C1CIFCLRR_PLL6RDYF BIT(10)
+#define RCC_C1CIFCLRR_PLL7RDYF BIT(11)
+#define RCC_C1CIFCLRR_PLL8RDYF BIT(12)
+#define RCC_C1CIFCLRR_LSECSSF BIT(16)
+#define RCC_C1CIFCLRR_WKUPF BIT(20)
+
+/* RCC_C2CIESETR register fields */
+#define RCC_C2CIESETR_LSIRDYIE BIT(0)
+#define RCC_C2CIESETR_LSERDYIE BIT(1)
+#define RCC_C2CIESETR_HSIRDYIE BIT(2)
+#define RCC_C2CIESETR_HSERDYIE BIT(3)
+#define RCC_C2CIESETR_MSIRDYIE BIT(4)
+#define RCC_C2CIESETR_PLL1RDYIE BIT(5)
+#define RCC_C2CIESETR_PLL2RDYIE BIT(6)
+#define RCC_C2CIESETR_PLL3RDYIE BIT(7)
+#define RCC_C2CIESETR_PLL4RDYIE BIT(8)
+#define RCC_C2CIESETR_PLL5RDYIE BIT(9)
+#define RCC_C2CIESETR_PLL6RDYIE BIT(10)
+#define RCC_C2CIESETR_PLL7RDYIE BIT(11)
+#define RCC_C2CIESETR_PLL8RDYIE BIT(12)
+#define RCC_C2CIESETR_LSECSSIE BIT(16)
+#define RCC_C2CIESETR_WKUPIE BIT(20)
+
+/* RCC_C2CIFCLRR register fields */
+#define RCC_C2CIFCLRR_LSIRDYF BIT(0)
+#define RCC_C2CIFCLRR_LSERDYF BIT(1)
+#define RCC_C2CIFCLRR_HSIRDYF BIT(2)
+#define RCC_C2CIFCLRR_HSERDYF BIT(3)
+#define RCC_C2CIFCLRR_MSIRDYF BIT(4)
+#define RCC_C2CIFCLRR_PLL1RDYF BIT(5)
+#define RCC_C2CIFCLRR_PLL2RDYF BIT(6)
+#define RCC_C2CIFCLRR_PLL3RDYF BIT(7)
+#define RCC_C2CIFCLRR_PLL4RDYF BIT(8)
+#define RCC_C2CIFCLRR_PLL5RDYF BIT(9)
+#define RCC_C2CIFCLRR_PLL6RDYF BIT(10)
+#define RCC_C2CIFCLRR_PLL7RDYF BIT(11)
+#define RCC_C2CIFCLRR_PLL8RDYF BIT(12)
+#define RCC_C2CIFCLRR_LSECSSF BIT(16)
+#define RCC_C2CIFCLRR_WKUPF BIT(20)
+
+/* RCC_CxCIESETR register fields */
+#define RCC_CxCIESETR_LSIRDYIE BIT(0)
+#define RCC_CxCIESETR_LSERDYIE BIT(1)
+#define RCC_CxCIESETR_HSIRDYIE BIT(2)
+#define RCC_CxCIESETR_HSERDYIE BIT(3)
+#define RCC_CxCIESETR_CSIRDYIE BIT(4)
+#define RCC_CxCIESETR_SHSIRDYIE BIT(5)
+#define RCC_CxCIESETR_PLL1RDYIE BIT(6)
+#define RCC_CxCIESETR_PLL2RDYIE BIT(7)
+#define RCC_CxCIESETR_PLL3RDYIE BIT(8)
+#define RCC_CxCIESETR_PLL4RDYIE BIT(9)
+#define RCC_CxCIESETR_PLL5RDYIE BIT(10)
+#define RCC_CxCIESETR_PLL6RDYIE BIT(11)
+#define RCC_CxCIESETR_PLL7RDYIE BIT(12)
+#define RCC_CxCIESETR_PLL8RDYIE BIT(13)
+#define RCC_CxCIESETR_LSECSSIE BIT(16)
+#define RCC_CxCIESETR_WKUPIE BIT(20)
+
+/* RCC_CxCIFCLRR register fields */
+#define RCC_CxCIFCLRR_LSIRDYF BIT(0)
+#define RCC_CxCIFCLRR_LSERDYF BIT(1)
+#define RCC_CxCIFCLRR_HSIRDYF BIT(2)
+#define RCC_CxCIFCLRR_HSERDYF BIT(3)
+#define RCC_CxCIFCLRR_CSIRDYF BIT(4)
+#define RCC_CxCIFCLRR_SHSIRDYF BIT(5)
+#define RCC_CxCIFCLRR_PLL1RDYF BIT(6)
+#define RCC_CxCIFCLRR_PLL2RDYF BIT(7)
+#define RCC_CxCIFCLRR_PLL3RDYF BIT(8)
+#define RCC_CxCIFCLRR_PLL4RDYF BIT(9)
+#define RCC_CxCIFCLRR_PLL5RDYF BIT(10)
+#define RCC_CxCIFCLRR_PLL6RDYF BIT(11)
+#define RCC_CxCIFCLRR_PLL7RDYF BIT(12)
+#define RCC_CxCIFCLRR_PLL8RDYF BIT(13)
+#define RCC_CxCIFCLRR_LSECSSF BIT(16)
+#define RCC_CxCIFCLRR_WKUPF BIT(20)
+
+/* RCC_IWDGC1FZSETR register fields */
+#define RCC_IWDGC1FZSETR_FZ_IWDG1 BIT(0)
+#define RCC_IWDGC1FZSETR_FZ_IWDG2 BIT(1)
+
+/* RCC_IWDGC1FZCLRR register fields */
+#define RCC_IWDGC1FZCLRR_FZ_IWDG1 BIT(0)
+#define RCC_IWDGC1FZCLRR_FZ_IWDG2 BIT(1)
+
+/* RCC_IWDGC1CFGSETR register fields */
+#define RCC_IWDGC1CFGSETR_IWDG1_SYSRSTEN BIT(0)
+#define RCC_IWDGC1CFGSETR_IWDG2_SYSRSTEN BIT(2)
+#define RCC_IWDGC1CFGSETR_IWDG2_KERRST BIT(18)
+
+/* RCC_IWDGC1CFGCLRR register fields */
+#define RCC_IWDGC1CFGCLRR_IWDG1_SYSRSTEN BIT(0)
+#define RCC_IWDGC1CFGCLRR_IWDG2_SYSRSTEN BIT(2)
+#define RCC_IWDGC1CFGCLRR_IWDG2_KERRST BIT(18)
+
+/* RCC_IWDGC2FZSETR register fields */
+#define RCC_IWDGC2FZSETR_FZ_IWDG3 BIT(0)
+#define RCC_IWDGC2FZSETR_FZ_IWDG4 BIT(1)
+
+/* RCC_IWDGC2FZCLRR register fields */
+#define RCC_IWDGC2FZCLRR_FZ_IWDG3 BIT(0)
+#define RCC_IWDGC2FZCLRR_FZ_IWDG4 BIT(1)
+
+/* RCC_IWDGC2CFGSETR register fields */
+#define RCC_IWDGC2CFGSETR_IWDG3_SYSRSTEN BIT(0)
+#define RCC_IWDGC2CFGSETR_IWDG4_SYSRSTEN BIT(2)
+#define RCC_IWDGC2CFGSETR_IWDG4_KERRST BIT(18)
+
+/* RCC_IWDGC2CFGCLRR register fields */
+#define RCC_IWDGC2CFGCLRR_IWDG3_SYSRSTEN BIT(0)
+#define RCC_IWDGC2CFGCLRR_IWDG4_SYSRSTEN BIT(2)
+#define RCC_IWDGC2CFGCLRR_IWDG4_KERRST BIT(18)
+
+/* RCC_MCO1CFGR register fields */
+#define RCC_MCO1CFGR_MCO1SEL BIT(0)
+#define RCC_MCO1CFGR_MCO1ON BIT(8)
+
+/* RCC_MCO2CFGR register fields */
+#define RCC_MCO2CFGR_MCO2SEL BIT(0)
+#define RCC_MCO2CFGR_MCO2ON BIT(8)
+
+/* RCC_MCOxCFGR register fields */
+#define RCC_MCOxCFGR_MCOxSEL BIT(0)
+#define RCC_MCOxCFGR_MCOxON BIT(8)
+
+/* RCC_OCENSETR register fields */
+#define RCC_OCENSETR_HSION BIT(0)
+#define RCC_OCENSETR_HSIKERON BIT(1)
+#define RCC_OCENSETR_MSION BIT(2)
+#define RCC_OCENSETR_MSIKERON BIT(3)
+#define RCC_OCENSETR_HSEDIV2ON BIT(5)
+#define RCC_OCENSETR_HSEDIV2BYP BIT(6)
+#define RCC_OCENSETR_HSEDIGBYP BIT(7)
+#define RCC_OCENSETR_HSEON BIT(8)
+#define RCC_OCENSETR_HSEKERON BIT(9)
+#define RCC_OCENSETR_HSEBYP BIT(10)
+#define RCC_OCENSETR_HSECSSON BIT(11)
+
+/* RCC_OCENCLRR register fields */
+#define RCC_OCENCLRR_HSION BIT(0)
+#define RCC_OCENCLRR_HSIKERON BIT(1)
+#define RCC_OCENCLRR_MSION BIT(2)
+#define RCC_OCENCLRR_MSIKERON BIT(3)
+#define RCC_OCENCLRR_HSEDIV2ON BIT(5)
+#define RCC_OCENCLRR_HSEDIV2BYP BIT(6)
+#define RCC_OCENCLRR_HSEDIGBYP BIT(7)
+#define RCC_OCENCLRR_HSEON BIT(8)
+#define RCC_OCENCLRR_HSEKERON BIT(9)
+#define RCC_OCENCLRR_HSEBYP BIT(10)
+
+/* RCC_OCRDYR register fields */
+#define RCC_OCRDYR_HSIRDY BIT(0)
+#define RCC_OCRDYR_MSIRDY BIT(2)
+#define RCC_OCRDYR_HSERDY BIT(8)
+#define RCC_OCRDYR_CKREST BIT(25)
+
+/* RCC_HSICFGR register fields */
+#define RCC_HSICFGR_HSITRIM_MASK GENMASK_32(14, 8)
+#define RCC_HSICFGR_HSITRIM_SHIFT 8
+#define RCC_HSICFGR_HSICAL_MASK GENMASK_32(24, 16)
+#define RCC_HSICFGR_HSICAL_SHIFT 16
+
+/* RCC_MSICFGR register fields */
+#define RCC_MSICFGR_MSITRIM_MASK GENMASK_32(12, 8)
+#define RCC_MSICFGR_MSITRIM_SHIFT 8
+#define RCC_MSICFGR_MSICAL_MASK GENMASK_32(23, 16)
+#define RCC_MSICFGR_MSICAL_SHIFT 16
+
+/* RCC_LSICR register fields */
+#define RCC_LSICR_LSION BIT(0)
+#define RCC_LSICR_LSIRDY BIT(1)
+
+/* RCC_RTCDIVR register fields */
+#define RCC_RTCDIVR_RTCDIV_MASK GENMASK_32(5, 0)
+#define RCC_RTCDIVR_RTCDIV_SHIFT 0
+
+/* RCC_APB1DIVR register fields */
+#define RCC_APB1DIVR_APB1DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB1DIVR_APB1DIV_SHIFT 0
+#define RCC_APB1DIVR_APB1DIVRDY BIT(31)
+
+/* RCC_APB2DIVR register fields */
+#define RCC_APB2DIVR_APB2DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB2DIVR_APB2DIV_SHIFT 0
+#define RCC_APB2DIVR_APB2DIVRDY BIT(31)
+
+/* RCC_APB3DIVR register fields */
+#define RCC_APB3DIVR_APB3DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB3DIVR_APB3DIV_SHIFT 0
+#define RCC_APB3DIVR_APB3DIVRDY BIT(31)
+
+/* RCC_APB4DIVR register fields */
+#define RCC_APB4DIVR_APB4DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB4DIVR_APB4DIV_SHIFT 0
+#define RCC_APB4DIVR_APB4DIVRDY BIT(31)
+
+/* RCC_APB5DIVR register fields */
+#define RCC_APB5DIVR_APB5DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB5DIVR_APB5DIV_SHIFT 0
+#define RCC_APB5DIVR_APB5DIVRDY BIT(31)
+
+/* RCC_APBDBGDIVR register fields */
+#define RCC_APBDBGDIVR_APBDBGDIV_MASK GENMASK_32(2, 0)
+#define RCC_APBDBGDIVR_APBDBGDIV_SHIFT 0
+#define RCC_APBDBGDIVR_APBDBGDIVRDY BIT(31)
+
+/* RCC_APBxDIVR register fields */
+#define RCC_APBxDIVR_APBxDIV_MASK GENMASK_32(2, 0)
+#define RCC_APBxDIVR_APBxDIV_SHIFT 0
+#define RCC_APBxDIVR_APBxDIVRDY BIT(31)
+
+/* RCC_TIMG1PRER register fields */
+#define RCC_TIMG1PRER_TIMG1PRE BIT(0)
+#define RCC_TIMG1PRER_TIMG1PRERDY BIT(31)
+
+/* RCC_TIMG2PRER register fields */
+#define RCC_TIMG2PRER_TIMG2PRE BIT(0)
+#define RCC_TIMG2PRER_TIMG2PRERDY BIT(31)
+
+/* RCC_TIMGxPRER register fields */
+#define RCC_TIMGxPRER_TIMGxPRE BIT(0)
+#define RCC_TIMGxPRER_TIMGxPRERDY BIT(31)
+
+/* RCC_LSMCUDIVR register fields */
+#define RCC_LSMCUDIVR_LSMCUDIV BIT(0)
+#define RCC_LSMCUDIVR_LSMCUDIVRDY BIT(31)
+
+/* RCC_DDRCPCFGR register fields */
+#define RCC_DDRCPCFGR_DDRCPRST BIT(0)
+#define RCC_DDRCPCFGR_DDRCPEN BIT(1)
+#define RCC_DDRCPCFGR_DDRCPLPEN BIT(2)
+
+/* RCC_DDRCAPBCFGR register fields */
+#define RCC_DDRCAPBCFGR_DDRCAPBRST BIT(0)
+#define RCC_DDRCAPBCFGR_DDRCAPBEN BIT(1)
+#define RCC_DDRCAPBCFGR_DDRCAPBLPEN BIT(2)
+
+/* RCC_DDRPHYCAPBCFGR register fields */
+#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST BIT(0)
+#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN BIT(1)
+#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN BIT(2)
+
+/* RCC_DDRPHYCCFGR register fields */
+#define RCC_DDRPHYCCFGR_DDRPHYCEN BIT(1)
+
+/* RCC_DDRCFGR register fields */
+#define RCC_DDRCFGR_DDRCFGRST BIT(0)
+#define RCC_DDRCFGR_DDRCFGEN BIT(1)
+#define RCC_DDRCFGR_DDRCFGLPEN BIT(2)
+
+/* RCC_DDRITFCFGR register fields */
+#define RCC_DDRITFCFGR_DDRRST BIT(0)
+#define RCC_DDRITFCFGR_DDRCKMOD_MASK GENMASK_32(5, 4)
+#define RCC_DDRITFCFGR_DDRCKMOD_SHIFT 4
+#define RCC_DDRITFCFGR_DDRCKMOD_HSR BIT(5)
+#define RCC_DDRITFCFGR_DDRSHR BIT(8)
+#define RCC_DDRITFCFGR_DDRPHYDLP BIT(16)
+
+/* RCC_SYSRAMCFGR register fields */
+#define RCC_SYSRAMCFGR_SYSRAMEN BIT(1)
+#define RCC_SYSRAMCFGR_SYSRAMLPEN BIT(2)
+
+/* RCC_SRAM1CFGR register fields */
+#define RCC_SRAM1CFGR_SRAM1EN BIT(1)
+#define RCC_SRAM1CFGR_SRAM1LPEN BIT(2)
+
+/* RCC_RETRAMCFGR register fields */
+#define RCC_RETRAMCFGR_RETRAMEN BIT(1)
+#define RCC_RETRAMCFGR_RETRAMLPEN BIT(2)
+
+/* RCC_BKPSRAMCFGR register fields */
+#define RCC_BKPSRAMCFGR_BKPSRAMEN BIT(1)
+#define RCC_BKPSRAMCFGR_BKPSRAMLPEN BIT(2)
+
+/* RCC_OSPI1CFGR register fields */
+#define RCC_OSPI1CFGR_OSPI1RST BIT(0)
+#define RCC_OSPI1CFGR_OSPI1EN BIT(1)
+#define RCC_OSPI1CFGR_OSPI1LPEN BIT(2)
+#define RCC_OSPI1CFGR_OTFDEC1RST BIT(8)
+#define RCC_OSPI1CFGR_OSPI1DLLRST BIT(16)
+
+/* RCC_OSPIxCFGR register fields */
+#define RCC_OSPIxCFGR_OSPIxRST BIT(0)
+#define RCC_OSPIxCFGR_OSPIxEN BIT(1)
+#define RCC_OSPIxCFGR_OSPIxLPEN BIT(2)
+#define RCC_OSPIxCFGR_OTFDECxRST BIT(8)
+#define RCC_OSPIxCFGR_OSPIxDLLRST BIT(16)
+
+/* RCC_FMCCFGR register fields */
+#define RCC_FMCCFGR_FMCRST BIT(0)
+#define RCC_FMCCFGR_FMCEN BIT(1)
+#define RCC_FMCCFGR_FMCLPEN BIT(2)
+
+/* RCC_DBGCFGR register fields */
+#define RCC_DBGCFGR_DBGEN BIT(8)
+#define RCC_DBGCFGR_TRACEEN BIT(9)
+#define RCC_DBGCFGR_DBGMCUEN BIT(10)
+#define RCC_DBGCFGR_DBGRST BIT(12)
+
+/* RCC_STMCFGR register fields */
+#define RCC_STMCFGR_STMEN BIT(1)
+#define RCC_STMCFGR_STMLPEN BIT(2)
+
+/* RCC_ETRCFGR register fields */
+#define RCC_ETRCFGR_ETREN BIT(1)
+#define RCC_ETRCFGR_ETRLPEN BIT(2)
+
+/* RCC_GPIOACFGR register fields */
+#define RCC_GPIOACFGR_GPIOARST BIT(0)
+#define RCC_GPIOACFGR_GPIOAEN BIT(1)
+#define RCC_GPIOACFGR_GPIOALPEN BIT(2)
+
+/* RCC_GPIOBCFGR register fields */
+#define RCC_GPIOBCFGR_GPIOBRST BIT(0)
+#define RCC_GPIOBCFGR_GPIOBEN BIT(1)
+#define RCC_GPIOBCFGR_GPIOBLPEN BIT(2)
+
+/* RCC_GPIOCCFGR register fields */
+#define RCC_GPIOCCFGR_GPIOCRST BIT(0)
+#define RCC_GPIOCCFGR_GPIOCEN BIT(1)
+#define RCC_GPIOCCFGR_GPIOCLPEN BIT(2)
+
+/* RCC_GPIODCFGR register fields */
+#define RCC_GPIODCFGR_GPIODRST BIT(0)
+#define RCC_GPIODCFGR_GPIODEN BIT(1)
+#define RCC_GPIODCFGR_GPIODLPEN BIT(2)
+
+/* RCC_GPIOECFGR register fields */
+#define RCC_GPIOECFGR_GPIOERST BIT(0)
+#define RCC_GPIOECFGR_GPIOEEN BIT(1)
+#define RCC_GPIOECFGR_GPIOELPEN BIT(2)
+
+/* RCC_GPIOFCFGR register fields */
+#define RCC_GPIOFCFGR_GPIOFRST BIT(0)
+#define RCC_GPIOFCFGR_GPIOFEN BIT(1)
+#define RCC_GPIOFCFGR_GPIOFLPEN BIT(2)
+
+/* RCC_GPIOGCFGR register fields */
+#define RCC_GPIOGCFGR_GPIOGRST BIT(0)
+#define RCC_GPIOGCFGR_GPIOGEN BIT(1)
+#define RCC_GPIOGCFGR_GPIOGLPEN BIT(2)
+
+/* RCC_GPIOHCFGR register fields */
+#define RCC_GPIOHCFGR_GPIOHRST BIT(0)
+#define RCC_GPIOHCFGR_GPIOHEN BIT(1)
+#define RCC_GPIOHCFGR_GPIOHLPEN BIT(2)
+
+/* RCC_GPIOICFGR register fields */
+#define RCC_GPIOICFGR_GPIOIRST BIT(0)
+#define RCC_GPIOICFGR_GPIOIEN BIT(1)
+#define RCC_GPIOICFGR_GPIOILPEN BIT(2)
+
+/* RCC_GPIOZCFGR register fields */
+#define RCC_GPIOZCFGR_GPIOZRST BIT(0)
+#define RCC_GPIOZCFGR_GPIOZEN BIT(1)
+#define RCC_GPIOZCFGR_GPIOZLPEN BIT(2)
+
+/* RCC_GPIOxCFGR register fields */
+#define RCC_GPIOxCFGR_GPIOxRST BIT(0)
+#define RCC_GPIOxCFGR_GPIOxEN BIT(1)
+#define RCC_GPIOxCFGR_GPIOxLPEN BIT(2)
+#define RCC_GPIOxCFGR_GPIOxAMEN BIT(3)
+
+/* RCC_HPDMA1CFGR register fields */
+#define RCC_HPDMA1CFGR_HPDMA1RST BIT(0)
+#define RCC_HPDMA1CFGR_HPDMA1EN BIT(1)
+#define RCC_HPDMA1CFGR_HPDMA1LPEN BIT(2)
+
+/* RCC_HPDMA2CFGR register fields */
+#define RCC_HPDMA2CFGR_HPDMA2RST BIT(0)
+#define RCC_HPDMA2CFGR_HPDMA2EN BIT(1)
+#define RCC_HPDMA2CFGR_HPDMA2LPEN BIT(2)
+
+/* RCC_HPDMA3CFGR register fields */
+#define RCC_HPDMA3CFGR_HPDMA3RST BIT(0)
+#define RCC_HPDMA3CFGR_HPDMA3EN BIT(1)
+#define RCC_HPDMA3CFGR_HPDMA3LPEN BIT(2)
+
+/* RCC_HPDMAxCFGR register fields */
+#define RCC_HPDMAxCFGR_HPDMAxRST BIT(0)
+#define RCC_HPDMAxCFGR_HPDMAxEN BIT(1)
+#define RCC_HPDMAxCFGR_HPDMAxLPEN BIT(2)
+
+/* RCC_IPCC1CFGR register fields */
+#define RCC_IPCC1CFGR_IPCC1RST BIT(0)
+#define RCC_IPCC1CFGR_IPCC1EN BIT(1)
+#define RCC_IPCC1CFGR_IPCC1LPEN BIT(2)
+
+/* RCC_RTCCFGR register fields */
+#define RCC_RTCCFGR_RTCEN BIT(1)
+#define RCC_RTCCFGR_RTCLPEN BIT(2)
+
+/* RCC_SYSCPU1CFGR register fields */
+#define RCC_SYSCPU1CFGR_SYSCPU1EN BIT(1)
+#define RCC_SYSCPU1CFGR_SYSCPU1LPEN BIT(2)
+
+/* RCC_BSECCFGR register fields */
+#define RCC_BSECCFGR_BSECEN BIT(1)
+#define RCC_BSECCFGR_BSECLPEN BIT(2)
+
+/* RCC_PLL2CFGR1 register fields */
+#define RCC_PLL2CFGR1_SSMODRST BIT(0)
+#define RCC_PLL2CFGR1_PLLEN BIT(8)
+#define RCC_PLL2CFGR1_PLLRDY BIT(24)
+#define RCC_PLL2CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL2CFGR2 register fields */
+#define RCC_PLL2CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL2CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL2CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL2CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL2CFGR3 register fields */
+#define RCC_PLL2CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL2CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL2CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL2CFGR3_DACEN BIT(25)
+#define RCC_PLL2CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL2CFGR4 register fields */
+#define RCC_PLL2CFGR4_DSMEN BIT(8)
+#define RCC_PLL2CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL2CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL2CFGR5 register fields */
+#define RCC_PLL2CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL2CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL2CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL2CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL2CFGR6 register fields */
+#define RCC_PLL2CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL2CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL2CFGR7 register fields */
+#define RCC_PLL2CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL2CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLLxCFGR1 register fields */
+#define RCC_PLLxCFGR1_SSMODRST BIT(0)
+#define RCC_PLLxCFGR1_PLLEN BIT(8)
+#define RCC_PLLxCFGR1_PLLRDY BIT(24)
+#define RCC_PLLxCFGR1_CKREFST BIT(28)
+
+/* RCC_PLLxCFGR2 register fields */
+#define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLLxCFGR2_FREFDIV_SHIFT 0
+#define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLLxCFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLLxCFGR3 register fields */
+#define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLLxCFGR3_FRACIN_SHIFT 0
+#define RCC_PLLxCFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLLxCFGR3_DACEN BIT(25)
+#define RCC_PLLxCFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLLxCFGR4 register fields */
+#define RCC_PLLxCFGR4_DSMEN BIT(8)
+#define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLLxCFGR4_BYPASS BIT(10)
+
+/* RCC_PLLxCFGR5 register fields */
+#define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLLxCFGR5_DIVVAL_SHIFT 0
+#define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLLxCFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLLxCFGR6 register fields */
+#define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLLxCFGR7 register fields */
+#define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_HSIFMONCR register fields */
+#define RCC_HSIFMONCR_HSIREF_MASK GENMASK_32(10, 0)
+#define RCC_HSIFMONCR_HSIREF_SHIFT 0
+#define RCC_HSIFMONCR_HSIMONEN BIT(15)
+#define RCC_HSIFMONCR_HSIDEV_MASK GENMASK_32(21, 16)
+#define RCC_HSIFMONCR_HSIDEV_SHIFT 16
+#define RCC_HSIFMONCR_HSIMONIE BIT(30)
+#define RCC_HSIFMONCR_HSIMONF BIT(31)
+
+/* RCC_HSIFVALR register fields */
+#define RCC_HSIFVALR_HSIVAL_MASK GENMASK_32(10, 0)
+#define RCC_HSIFVALR_HSIVAL_SHIFT 0
+
+/* RCC_MSIFMONCR register fields */
+#define RCC_MSIFMONCR_MSIREF_MASK GENMASK_32(8, 0)
+#define RCC_MSIFMONCR_MSIREF_SHIFT 0
+#define RCC_MSIFMONCR_MSIMONEN BIT(15)
+#define RCC_MSIFMONCR_MSIDEV_MASK GENMASK_32(20, 16)
+#define RCC_MSIFMONCR_MSIDEV_SHIFT 16
+#define RCC_MSIFMONCR_MSIMONIE BIT(30)
+#define RCC_MSIFMONCR_MSIMONF BIT(31)
+
+/* RCC_MSIFVALR register fields */
+#define RCC_MSIFVALR_MSIVAL_MASK GENMASK_32(8, 0)
+#define RCC_MSIFVALR_MSIVAL_SHIFT 0
+
+/* RCC_TIM1CFGR register fields */
+#define RCC_TIM1CFGR_TIM1RST BIT(0)
+#define RCC_TIM1CFGR_TIM1EN BIT(1)
+#define RCC_TIM1CFGR_TIM1LPEN BIT(2)
+
+/* RCC_TIM2CFGR register fields */
+#define RCC_TIM2CFGR_TIM2RST BIT(0)
+#define RCC_TIM2CFGR_TIM2EN BIT(1)
+#define RCC_TIM2CFGR_TIM2LPEN BIT(2)
+
+/* RCC_TIM3CFGR register fields */
+#define RCC_TIM3CFGR_TIM3RST BIT(0)
+#define RCC_TIM3CFGR_TIM3EN BIT(1)
+#define RCC_TIM3CFGR_TIM3LPEN BIT(2)
+
+/* RCC_TIM4CFGR register fields */
+#define RCC_TIM4CFGR_TIM4RST BIT(0)
+#define RCC_TIM4CFGR_TIM4EN BIT(1)
+#define RCC_TIM4CFGR_TIM4LPEN BIT(2)
+
+/* RCC_TIM5CFGR register fields */
+#define RCC_TIM5CFGR_TIM5RST BIT(0)
+#define RCC_TIM5CFGR_TIM5EN BIT(1)
+#define RCC_TIM5CFGR_TIM5LPEN BIT(2)
+
+/* RCC_TIM6CFGR register fields */
+#define RCC_TIM6CFGR_TIM6RST BIT(0)
+#define RCC_TIM6CFGR_TIM6EN BIT(1)
+#define RCC_TIM6CFGR_TIM6LPEN BIT(2)
+
+/* RCC_TIM7CFGR register fields */
+#define RCC_TIM7CFGR_TIM7RST BIT(0)
+#define RCC_TIM7CFGR_TIM7EN BIT(1)
+#define RCC_TIM7CFGR_TIM7LPEN BIT(2)
+
+/* RCC_TIM8CFGR register fields */
+#define RCC_TIM8CFGR_TIM8RST BIT(0)
+#define RCC_TIM8CFGR_TIM8EN BIT(1)
+#define RCC_TIM8CFGR_TIM8LPEN BIT(2)
+
+/* RCC_TIM10CFGR register fields */
+#define RCC_TIM10CFGR_TIM10RST BIT(0)
+#define RCC_TIM10CFGR_TIM10EN BIT(1)
+#define RCC_TIM10CFGR_TIM10LPEN BIT(2)
+
+/* RCC_TIM11CFGR register fields */
+#define RCC_TIM11CFGR_TIM11RST BIT(0)
+#define RCC_TIM11CFGR_TIM11EN BIT(1)
+#define RCC_TIM11CFGR_TIM11LPEN BIT(2)
+
+/* RCC_TIM12CFGR register fields */
+#define RCC_TIM12CFGR_TIM12RST BIT(0)
+#define RCC_TIM12CFGR_TIM12EN BIT(1)
+#define RCC_TIM12CFGR_TIM12LPEN BIT(2)
+
+/* RCC_TIM13CFGR register fields */
+#define RCC_TIM13CFGR_TIM13RST BIT(0)
+#define RCC_TIM13CFGR_TIM13EN BIT(1)
+#define RCC_TIM13CFGR_TIM13LPEN BIT(2)
+
+/* RCC_TIM14CFGR register fields */
+#define RCC_TIM14CFGR_TIM14RST BIT(0)
+#define RCC_TIM14CFGR_TIM14EN BIT(1)
+#define RCC_TIM14CFGR_TIM14LPEN BIT(2)
+
+/* RCC_TIM15CFGR register fields */
+#define RCC_TIM15CFGR_TIM15RST BIT(0)
+#define RCC_TIM15CFGR_TIM15EN BIT(1)
+#define RCC_TIM15CFGR_TIM15LPEN BIT(2)
+
+/* RCC_TIM16CFGR register fields */
+#define RCC_TIM16CFGR_TIM16RST BIT(0)
+#define RCC_TIM16CFGR_TIM16EN BIT(1)
+#define RCC_TIM16CFGR_TIM16LPEN BIT(2)
+
+/* RCC_TIM17CFGR register fields */
+#define RCC_TIM17CFGR_TIM17RST BIT(0)
+#define RCC_TIM17CFGR_TIM17EN BIT(1)
+#define RCC_TIM17CFGR_TIM17LPEN BIT(2)
+
+/* RCC_LPTIM1CFGR register fields */
+#define RCC_LPTIM1CFGR_LPTIM1RST BIT(0)
+#define RCC_LPTIM1CFGR_LPTIM1EN BIT(1)
+#define RCC_LPTIM1CFGR_LPTIM1LPEN BIT(2)
+
+/* RCC_LPTIM2CFGR register fields */
+#define RCC_LPTIM2CFGR_LPTIM2RST BIT(0)
+#define RCC_LPTIM2CFGR_LPTIM2EN BIT(1)
+#define RCC_LPTIM2CFGR_LPTIM2LPEN BIT(2)
+
+/* RCC_LPTIM3CFGR register fields */
+#define RCC_LPTIM3CFGR_LPTIM3RST BIT(0)
+#define RCC_LPTIM3CFGR_LPTIM3EN BIT(1)
+#define RCC_LPTIM3CFGR_LPTIM3LPEN BIT(2)
+
+/* RCC_LPTIM4CFGR register fields */
+#define RCC_LPTIM4CFGR_LPTIM4RST BIT(0)
+#define RCC_LPTIM4CFGR_LPTIM4EN BIT(1)
+#define RCC_LPTIM4CFGR_LPTIM4LPEN BIT(2)
+
+/* RCC_LPTIM5CFGR register fields */
+#define RCC_LPTIM5CFGR_LPTIM5RST BIT(0)
+#define RCC_LPTIM5CFGR_LPTIM5EN BIT(1)
+#define RCC_LPTIM5CFGR_LPTIM5LPEN BIT(2)
+
+/* RCC_LPTIMxCFGR register fields */
+#define RCC_LPTIMxCFGR_LPTIMxRST BIT(0)
+#define RCC_LPTIMxCFGR_LPTIMxEN BIT(1)
+#define RCC_LPTIMxCFGR_LPTIMxLPEN BIT(2)
+#define RCC_LPTIMxCFGR_LPTIMxAMEN BIT(3)
+
+/* RCC_SPI1CFGR register fields */
+#define RCC_SPI1CFGR_SPI1RST BIT(0)
+#define RCC_SPI1CFGR_SPI1EN BIT(1)
+#define RCC_SPI1CFGR_SPI1LPEN BIT(2)
+
+/* RCC_SPI2CFGR register fields */
+#define RCC_SPI2CFGR_SPI2RST BIT(0)
+#define RCC_SPI2CFGR_SPI2EN BIT(1)
+#define RCC_SPI2CFGR_SPI2LPEN BIT(2)
+
+/* RCC_SPI3CFGR register fields */
+#define RCC_SPI3CFGR_SPI3RST BIT(0)
+#define RCC_SPI3CFGR_SPI3EN BIT(1)
+#define RCC_SPI3CFGR_SPI3LPEN BIT(2)
+
+/* RCC_SPI4CFGR register fields */
+#define RCC_SPI4CFGR_SPI4RST BIT(0)
+#define RCC_SPI4CFGR_SPI4EN BIT(1)
+#define RCC_SPI4CFGR_SPI4LPEN BIT(2)
+
+/* RCC_SPI5CFGR register fields */
+#define RCC_SPI5CFGR_SPI5RST BIT(0)
+#define RCC_SPI5CFGR_SPI5EN BIT(1)
+#define RCC_SPI5CFGR_SPI5LPEN BIT(2)
+
+/* RCC_SPI6CFGR register fields */
+#define RCC_SPI6CFGR_SPI6RST BIT(0)
+#define RCC_SPI6CFGR_SPI6EN BIT(1)
+#define RCC_SPI6CFGR_SPI6LPEN BIT(2)
+
+/* RCC_SPIxCFGR register fields */
+#define RCC_SPIxCFGR_SPIxRST BIT(0)
+#define RCC_SPIxCFGR_SPIxEN BIT(1)
+#define RCC_SPIxCFGR_SPIxLPEN BIT(2)
+#define RCC_SPIxCFGR_SPIxAMEN BIT(3)
+
+/* RCC_SPDIFRXCFGR register fields */
+#define RCC_SPDIFRXCFGR_SPDIFRXRST BIT(0)
+#define RCC_SPDIFRXCFGR_SPDIFRXEN BIT(1)
+#define RCC_SPDIFRXCFGR_SPDIFRXLPEN BIT(2)
+
+/* RCC_USART1CFGR register fields */
+#define RCC_USART1CFGR_USART1RST BIT(0)
+#define RCC_USART1CFGR_USART1EN BIT(1)
+#define RCC_USART1CFGR_USART1LPEN BIT(2)
+
+/* RCC_USART2CFGR register fields */
+#define RCC_USART2CFGR_USART2RST BIT(0)
+#define RCC_USART2CFGR_USART2EN BIT(1)
+#define RCC_USART2CFGR_USART2LPEN BIT(2)
+
+/* RCC_USART3CFGR register fields */
+#define RCC_USART3CFGR_USART3RST BIT(0)
+#define RCC_USART3CFGR_USART3EN BIT(1)
+#define RCC_USART3CFGR_USART3LPEN BIT(2)
+
+/* RCC_UART4CFGR register fields */
+#define RCC_UART4CFGR_UART4RST BIT(0)
+#define RCC_UART4CFGR_UART4EN BIT(1)
+#define RCC_UART4CFGR_UART4LPEN BIT(2)
+
+/* RCC_UART5CFGR register fields */
+#define RCC_UART5CFGR_UART5RST BIT(0)
+#define RCC_UART5CFGR_UART5EN BIT(1)
+#define RCC_UART5CFGR_UART5LPEN BIT(2)
+
+/* RCC_USART6CFGR register fields */
+#define RCC_USART6CFGR_USART6RST BIT(0)
+#define RCC_USART6CFGR_USART6EN BIT(1)
+#define RCC_USART6CFGR_USART6LPEN BIT(2)
+
+/* RCC_UART7CFGR register fields */
+#define RCC_UART7CFGR_UART7RST BIT(0)
+#define RCC_UART7CFGR_UART7EN BIT(1)
+#define RCC_UART7CFGR_UART7LPEN BIT(2)
+
+/* RCC_USARTxCFGR register fields */
+#define RCC_USARTxCFGR_USARTxRST BIT(0)
+#define RCC_USARTxCFGR_USARTxEN BIT(1)
+#define RCC_USARTxCFGR_USARTxLPEN BIT(2)
+
+/* RCC_UARTxCFGR register fields */
+#define RCC_UARTxCFGR_UARTxRST BIT(0)
+#define RCC_UARTxCFGR_UARTxEN BIT(1)
+#define RCC_UARTxCFGR_UARTxLPEN BIT(2)
+
+/* RCC_LPUART1CFGR register fields */
+#define RCC_LPUART1CFGR_LPUART1RST BIT(0)
+#define RCC_LPUART1CFGR_LPUART1EN BIT(1)
+#define RCC_LPUART1CFGR_LPUART1LPEN BIT(2)
+
+/* RCC_I2C1CFGR register fields */
+#define RCC_I2C1CFGR_I2C1RST BIT(0)
+#define RCC_I2C1CFGR_I2C1EN BIT(1)
+#define RCC_I2C1CFGR_I2C1LPEN BIT(2)
+
+/* RCC_I2C2CFGR register fields */
+#define RCC_I2C2CFGR_I2C2RST BIT(0)
+#define RCC_I2C2CFGR_I2C2EN BIT(1)
+#define RCC_I2C2CFGR_I2C2LPEN BIT(2)
+
+/* RCC_I2C3CFGR register fields */
+#define RCC_I2C3CFGR_I2C3RST BIT(0)
+#define RCC_I2C3CFGR_I2C3EN BIT(1)
+#define RCC_I2C3CFGR_I2C3LPEN BIT(2)
+
+/* RCC_I2CxCFGR register fields */
+#define RCC_I2CxCFGR_I2CxRST BIT(0)
+#define RCC_I2CxCFGR_I2CxEN BIT(1)
+#define RCC_I2CxCFGR_I2CxLPEN BIT(2)
+#define RCC_I2CxCFGR_I2CxAMEN BIT(3)
+
+/* RCC_SAI1CFGR register fields */
+#define RCC_SAI1CFGR_SAI1RST BIT(0)
+#define RCC_SAI1CFGR_SAI1EN BIT(1)
+#define RCC_SAI1CFGR_SAI1LPEN BIT(2)
+
+/* RCC_SAI2CFGR register fields */
+#define RCC_SAI2CFGR_SAI2RST BIT(0)
+#define RCC_SAI2CFGR_SAI2EN BIT(1)
+#define RCC_SAI2CFGR_SAI2LPEN BIT(2)
+
+/* RCC_SAI3CFGR register fields */
+#define RCC_SAI3CFGR_SAI3RST BIT(0)
+#define RCC_SAI3CFGR_SAI3EN BIT(1)
+#define RCC_SAI3CFGR_SAI3LPEN BIT(2)
+
+/* RCC_SAI4CFGR register fields */
+#define RCC_SAI4CFGR_SAI4RST BIT(0)
+#define RCC_SAI4CFGR_SAI4EN BIT(1)
+#define RCC_SAI4CFGR_SAI4LPEN BIT(2)
+
+/* RCC_SAIxCFGR register fields */
+#define RCC_SAIxCFGR_SAIxRST BIT(0)
+#define RCC_SAIxCFGR_SAIxEN BIT(1)
+#define RCC_SAIxCFGR_SAIxLPEN BIT(2)
+
+/* RCC_MDF1CFGR register fields */
+#define RCC_MDF1CFGR_MDF1RST BIT(0)
+#define RCC_MDF1CFGR_MDF1EN BIT(1)
+#define RCC_MDF1CFGR_MDF1LPEN BIT(2)
+
+/* RCC_FDCANCFGR register fields */
+#define RCC_FDCANCFGR_FDCANRST BIT(0)
+#define RCC_FDCANCFGR_FDCANEN BIT(1)
+#define RCC_FDCANCFGR_FDCANLPEN BIT(2)
+
+/* RCC_HDPCFGR register fields */
+#define RCC_HDPCFGR_HDPRST BIT(0)
+#define RCC_HDPCFGR_HDPEN BIT(1)
+
+/* RCC_ADC1CFGR register fields */
+#define RCC_ADC1CFGR_ADC1RST BIT(0)
+#define RCC_ADC1CFGR_ADC1EN BIT(1)
+#define RCC_ADC1CFGR_ADC1LPEN BIT(2)
+#define RCC_ADC1CFGR_ADC1KERSEL BIT(12)
+
+/* RCC_ADC2CFGR register fields */
+#define RCC_ADC2CFGR_ADC2RST BIT(0)
+#define RCC_ADC2CFGR_ADC2EN BIT(1)
+#define RCC_ADC2CFGR_ADC2LPEN BIT(2)
+#define RCC_ADC2CFGR_ADC2KERSEL_MASK GENMASK_32(13, 12)
+#define RCC_ADC2CFGR_ADC2KERSEL_SHIFT 12
+
+/* RCC_ETH1CFGR register fields */
+#define RCC_ETH1CFGR_ETH1RST BIT(0)
+#define RCC_ETH1CFGR_ETH1MACEN BIT(1)
+#define RCC_ETH1CFGR_ETH1MACLPEN BIT(2)
+#define RCC_ETH1CFGR_ETH1STPEN BIT(4)
+#define RCC_ETH1CFGR_ETH1EN BIT(5)
+#define RCC_ETH1CFGR_ETH1LPEN BIT(6)
+#define RCC_ETH1CFGR_ETH1TXEN BIT(8)
+#define RCC_ETH1CFGR_ETH1TXLPEN BIT(9)
+#define RCC_ETH1CFGR_ETH1RXEN BIT(10)
+#define RCC_ETH1CFGR_ETH1RXLPEN BIT(11)
+
+/* RCC_ETH2CFGR register fields */
+#define RCC_ETH2CFGR_ETH2RST BIT(0)
+#define RCC_ETH2CFGR_ETH2MACEN BIT(1)
+#define RCC_ETH2CFGR_ETH2MACLPEN BIT(2)
+#define RCC_ETH2CFGR_ETH2STPEN BIT(4)
+#define RCC_ETH2CFGR_ETH2EN BIT(5)
+#define RCC_ETH2CFGR_ETH2LPEN BIT(6)
+#define RCC_ETH2CFGR_ETH2TXEN BIT(8)
+#define RCC_ETH2CFGR_ETH2TXLPEN BIT(9)
+#define RCC_ETH2CFGR_ETH2RXEN BIT(10)
+#define RCC_ETH2CFGR_ETH2RXLPEN BIT(11)
+
+/* RCC_ETHxCFGR register fields */
+#define RCC_ETHxCFGR_ETHxRST BIT(0)
+#define RCC_ETHxCFGR_ETHxMACEN BIT(1)
+#define RCC_ETHxCFGR_ETHxMACLPEN BIT(2)
+#define RCC_ETHxCFGR_ETHxSTPEN BIT(4)
+#define RCC_ETHxCFGR_ETHxEN BIT(5)
+#define RCC_ETHxCFGR_ETHxLPEN BIT(6)
+#define RCC_ETHxCFGR_ETHxTXEN BIT(8)
+#define RCC_ETHxCFGR_ETHxTXLPEN BIT(9)
+#define RCC_ETHxCFGR_ETHxRXEN BIT(10)
+#define RCC_ETHxCFGR_ETHxRXLPEN BIT(11)
+
+/* RCC_USBHCFGR register fields */
+#define RCC_USBHCFGR_USBHRST BIT(0)
+#define RCC_USBHCFGR_USBHEN BIT(1)
+#define RCC_USBHCFGR_USBHLPEN BIT(2)
+#define RCC_USBHCFGR_USBHSTPEN BIT(4)
+
+/* RCC_USB2PHY1CFGR register fields */
+#define RCC_USB2PHY1CFGR_USB2PHY1RST BIT(0)
+#define RCC_USB2PHY1CFGR_USB2PHY1EN BIT(1)
+#define RCC_USB2PHY1CFGR_USB2PHY1LPEN BIT(2)
+#define RCC_USB2PHY1CFGR_USB2PHY1STPEN BIT(4)
+#define RCC_USB2PHY1CFGR_USB2PHY1CKREFSEL BIT(15)
+
+/* RCC_OTGCFGR register fields */
+#define RCC_OTGCFGR_OTGRST BIT(0)
+#define RCC_OTGCFGR_OTGEN BIT(1)
+#define RCC_OTGCFGR_OTGLPEN BIT(2)
+
+/* RCC_USB2PHY2CFGR register fields */
+#define RCC_USB2PHY2CFGR_USB2PHY2RST BIT(0)
+#define RCC_USB2PHY2CFGR_USB2PHY2EN BIT(1)
+#define RCC_USB2PHY2CFGR_USB2PHY2LPEN BIT(2)
+#define RCC_USB2PHY2CFGR_USB2PHY2STPEN BIT(4)
+#define RCC_USB2PHY2CFGR_USB2PHY2CKREFSEL BIT(15)
+
+/* RCC_USB2PHYxCFGR register fields */
+#define RCC_USB2PHYxCFGR_USB2PHY1RST BIT(0)
+#define RCC_USB2PHYxCFGR_USB2PHY1EN BIT(1)
+#define RCC_USB2PHYxCFGR_USB2PHY1LPEN BIT(2)
+#define RCC_USB2PHYxCFGR_USB2PHY1STPEN BIT(4)
+#define RCC_USB2PHYxCFGR_USB2PHY1CKREFSEL BIT(15)
+
+/* RCC_STGENCFGR register fields */
+#define RCC_STGENCFGR_STGENEN BIT(1)
+#define RCC_STGENCFGR_STGENLPEN BIT(2)
+#define RCC_STGENCFGR_STGENSTPEN BIT(4)
+
+/* RCC_SDMMC1CFGR register fields */
+#define RCC_SDMMC1CFGR_SDMMC1RST BIT(0)
+#define RCC_SDMMC1CFGR_SDMMC1EN BIT(1)
+#define RCC_SDMMC1CFGR_SDMMC1LPEN BIT(2)
+#define RCC_SDMMC1CFGR_SDMMC1DLLRST BIT(16)
+
+/* RCC_SDMMC2CFGR register fields */
+#define RCC_SDMMC2CFGR_SDMMC2RST BIT(0)
+#define RCC_SDMMC2CFGR_SDMMC2EN BIT(1)
+#define RCC_SDMMC2CFGR_SDMMC2LPEN BIT(2)
+#define RCC_SDMMC2CFGR_SDMMC2DLLRST BIT(16)
+
+/* RCC_SDMMC3CFGR register fields */
+#define RCC_SDMMC3CFGR_SDMMC3RST BIT(0)
+#define RCC_SDMMC3CFGR_SDMMC3EN BIT(1)
+#define RCC_SDMMC3CFGR_SDMMC3LPEN BIT(2)
+#define RCC_SDMMC3CFGR_SDMMC3DLLRST BIT(16)
+
+/* RCC_SDMMCxCFGR register fields */
+#define RCC_SDMMCxCFGR_SDMMC1RST BIT(0)
+#define RCC_SDMMCxCFGR_SDMMC1EN BIT(1)
+#define RCC_SDMMCxCFGR_SDMMC1LPEN BIT(2)
+#define RCC_SDMMCxCFGR_SDMMC1DLLRST BIT(16)
+
+/* RCC_LTDCCFGR register fields */
+#define RCC_LTDCCFGR_LTDCRST BIT(0)
+#define RCC_LTDCCFGR_LTDCEN BIT(1)
+#define RCC_LTDCCFGR_LTDCLPEN BIT(2)
+
+/* RCC_CSICFGR register fields */
+#define RCC_CSICFGR_CSIRST BIT(0)
+#define RCC_CSICFGR_CSIEN BIT(1)
+#define RCC_CSICFGR_CSILPEN BIT(2)
+
+/* RCC_DCMIPPCFGR register fields */
+#define RCC_DCMIPPCFGR_DCMIPPRST BIT(0)
+#define RCC_DCMIPPCFGR_DCMIPPEN BIT(1)
+#define RCC_DCMIPPCFGR_DCMIPPLPEN BIT(2)
+
+/* RCC_DCMIPSSICFGR register fields */
+#define RCC_DCMIPSSICFGR_DCMIPSSIRST BIT(0)
+#define RCC_DCMIPSSICFGR_DCMIPSSIEN BIT(1)
+#define RCC_DCMIPSSICFGR_DCMIPSSILPEN BIT(2)
+
+/* RCC_RNG1CFGR register fields */
+#define RCC_RNG1CFGR_RNG1RST BIT(0)
+#define RCC_RNG1CFGR_RNG1EN BIT(1)
+#define RCC_RNG1CFGR_RNG1LPEN BIT(2)
+
+/* RCC_RNG2CFGR register fields */
+#define RCC_RNG2CFGR_RNG2RST BIT(0)
+#define RCC_RNG2CFGR_RNG2EN BIT(1)
+#define RCC_RNG2CFGR_RNG2LPEN BIT(2)
+
+/* RCC_PKACFGR register fields */
+#define RCC_PKACFGR_PKARST BIT(0)
+#define RCC_PKACFGR_PKAEN BIT(1)
+#define RCC_PKACFGR_PKALPEN BIT(2)
+
+/* RCC_SAESCFGR register fields */
+#define RCC_SAESCFGR_SAESRST BIT(0)
+#define RCC_SAESCFGR_SAESEN BIT(1)
+#define RCC_SAESCFGR_SAESLPEN BIT(2)
+
+/* RCC_HASH1CFGR register fields */
+#define RCC_HASH1CFGR_HASH1RST BIT(0)
+#define RCC_HASH1CFGR_HASH1EN BIT(1)
+#define RCC_HASH1CFGR_HASH1LPEN BIT(2)
+
+/* RCC_HASH2CFGR register fields */
+#define RCC_HASH2CFGR_HASH2RST BIT(0)
+#define RCC_HASH2CFGR_HASH2EN BIT(1)
+#define RCC_HASH2CFGR_HASH2LPEN BIT(2)
+
+/* RCC_CRYP1CFGR register fields */
+#define RCC_CRYP1CFGR_CRYP1RST BIT(0)
+#define RCC_CRYP1CFGR_CRYP1EN BIT(1)
+#define RCC_CRYP1CFGR_CRYP1LPEN BIT(2)
+
+/* RCC_CRYP2CFGR register fields */
+#define RCC_CRYP2CFGR_CRYP2RST BIT(0)
+#define RCC_CRYP2CFGR_CRYP2EN BIT(1)
+#define RCC_CRYP2CFGR_CRYP2LPEN BIT(2)
+
+/* RCC_CRYPxCFGR register fields */
+#define RCC_CRYPxCFGR_CRYPxRST BIT(0)
+#define RCC_CRYPxCFGR_CRYPxEN BIT(1)
+#define RCC_CRYPxCFGR_CRYPxLPEN BIT(2)
+
+/* RCC_IWDG1CFGR register fields */
+#define RCC_IWDG1CFGR_IWDG1EN BIT(1)
+#define RCC_IWDG1CFGR_IWDG1LPEN BIT(2)
+
+/* RCC_IWDG2CFGR register fields */
+#define RCC_IWDG2CFGR_IWDG2EN BIT(1)
+#define RCC_IWDG2CFGR_IWDG2LPEN BIT(2)
+
+/* RCC_IWDG3CFGR register fields */
+#define RCC_IWDG3CFGR_IWDG3EN BIT(1)
+#define RCC_IWDG3CFGR_IWDG3LPEN BIT(2)
+
+/* RCC_IWDG4CFGR register fields */
+#define RCC_IWDG4CFGR_IWDG4EN BIT(1)
+#define RCC_IWDG4CFGR_IWDG4LPEN BIT(2)
+
+/* RCC_IWDGxCFGR register fields */
+#define RCC_IWDGxCFGR_IWDGxEN BIT(1)
+#define RCC_IWDGxCFGR_IWDGxLPEN BIT(2)
+
+/* RCC_WWDG1CFGR register fields */
+#define RCC_WWDG1CFGR_WWDG1RST BIT(0)
+#define RCC_WWDG1CFGR_WWDG1EN BIT(1)
+#define RCC_WWDG1CFGR_WWDG1LPEN BIT(2)
+
+/* RCC_VREFCFGR register fields */
+#define RCC_VREFCFGR_VREFRST BIT(0)
+#define RCC_VREFCFGR_VREFEN BIT(1)
+#define RCC_VREFCFGR_VREFLPEN BIT(2)
+
+/* RCC_DTSCFGR register fields */
+#define RCC_DTSCFGR_DTSRST BIT(0)
+#define RCC_DTSCFGR_DTSEN BIT(1)
+#define RCC_DTSCFGR_DTSLPEN BIT(2)
+#define RCC_DTSCFGR_DTSKERSEL_MASK GENMASK_32(13, 12)
+#define RCC_DTSCFGR_DTSKERSEL_SHIFT 12
+
+/* RCC_CRCCFGR register fields */
+#define RCC_CRCCFGR_CRCRST BIT(0)
+#define RCC_CRCCFGR_CRCEN BIT(1)
+#define RCC_CRCCFGR_CRCLPEN BIT(2)
+
+/* RCC_SERCCFGR register fields */
+#define RCC_SERCCFGR_SERCRST BIT(0)
+#define RCC_SERCCFGR_SERCEN BIT(1)
+#define RCC_SERCCFGR_SERCLPEN BIT(2)
+
+/* RCC_DDRPERFMCFGR register fields */
+#define RCC_DDRPERFMCFGR_DDRPERFMRST BIT(0)
+#define RCC_DDRPERFMCFGR_DDRPERFMEN BIT(1)
+#define RCC_DDRPERFMCFGR_DDRPERFMLPEN BIT(2)
+
+/* RCC_I3C1CFGR register fields */
+#define RCC_I3C1CFGR_I3C1RST BIT(0)
+#define RCC_I3C1CFGR_I3C1EN BIT(1)
+#define RCC_I3C1CFGR_I3C1LPEN BIT(2)
+
+/* RCC_I3C2CFGR register fields */
+#define RCC_I3C2CFGR_I3C2RST BIT(0)
+#define RCC_I3C2CFGR_I3C2EN BIT(1)
+#define RCC_I3C2CFGR_I3C2LPEN BIT(2)
+
+/* RCC_I3C3CFGR register fields */
+#define RCC_I3C3CFGR_I3C3RST BIT(0)
+#define RCC_I3C3CFGR_I3C3EN BIT(1)
+#define RCC_I3C3CFGR_I3C3LPEN BIT(2)
+
+/* RCC_I3CxCFGR register fields */
+#define RCC_I3CxCFGR_I3CxRST BIT(0)
+#define RCC_I3CxCFGR_I3CxEN BIT(1)
+#define RCC_I3CxCFGR_I3CxLPEN BIT(2)
+#define RCC_I3CxCFGR_I3CxAMEN BIT(3)
+
+/* RCC_MUXSELCFGR register fields */
+#define RCC_MUXSELCFGR_MUXSEL0_MASK GENMASK_32(2, 0)
+#define RCC_MUXSELCFGR_MUXSEL0_SHIFT 0
+#define RCC_MUXSELCFGR_MUXSEL1_MASK GENMASK_32(6, 4)
+#define RCC_MUXSELCFGR_MUXSEL1_SHIFT 4
+#define RCC_MUXSELCFGR_MUXSEL2_MASK GENMASK_32(10, 8)
+#define RCC_MUXSELCFGR_MUXSEL2_SHIFT 8
+#define RCC_MUXSELCFGR_MUXSEL3_MASK GENMASK_32(14, 12)
+#define RCC_MUXSELCFGR_MUXSEL3_SHIFT 12
+#define RCC_MUXSELCFGR_MUXSEL4_MASK GENMASK_32(18, 16)
+#define RCC_MUXSELCFGR_MUXSEL4_SHIFT 16
+#define RCC_MUXSELCFGR_MUXSEL5_MASK GENMASK_32(21, 20)
+#define RCC_MUXSELCFGR_MUXSEL5_SHIFT 20
+#define RCC_MUXSELCFGR_MUXSEL6_MASK GENMASK_32(25, 24)
+#define RCC_MUXSELCFGR_MUXSEL6_SHIFT 24
+#define RCC_MUXSELCFGR_MUXSEL7_MASK GENMASK_32(29, 28)
+#define RCC_MUXSELCFGR_MUXSEL7_SHIFT 28
+
+/* RCC_XBAR0CFGR register fields */
+#define RCC_XBAR0CFGR_XBAR0SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR0CFGR_XBAR0SEL_SHIFT 0
+#define RCC_XBAR0CFGR_XBAR0EN BIT(6)
+#define RCC_XBAR0CFGR_XBAR0STS BIT(7)
+
+/* RCC_XBAR1CFGR register fields */
+#define RCC_XBAR1CFGR_XBAR1SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR1CFGR_XBAR1SEL_SHIFT 0
+#define RCC_XBAR1CFGR_XBAR1EN BIT(6)
+#define RCC_XBAR1CFGR_XBAR1STS BIT(7)
+
+/* RCC_XBAR2CFGR register fields */
+#define RCC_XBAR2CFGR_XBAR2SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR2CFGR_XBAR2SEL_SHIFT 0
+#define RCC_XBAR2CFGR_XBAR2EN BIT(6)
+#define RCC_XBAR2CFGR_XBAR2STS BIT(7)
+
+/* RCC_XBAR3CFGR register fields */
+#define RCC_XBAR3CFGR_XBAR3SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR3CFGR_XBAR3SEL_SHIFT 0
+#define RCC_XBAR3CFGR_XBAR3EN BIT(6)
+#define RCC_XBAR3CFGR_XBAR3STS BIT(7)
+
+/* RCC_XBAR4CFGR register fields */
+#define RCC_XBAR4CFGR_XBAR4SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR4CFGR_XBAR4SEL_SHIFT 0
+#define RCC_XBAR4CFGR_XBAR4EN BIT(6)
+#define RCC_XBAR4CFGR_XBAR4STS BIT(7)
+
+/* RCC_XBAR5CFGR register fields */
+#define RCC_XBAR5CFGR_XBAR5SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR5CFGR_XBAR5SEL_SHIFT 0
+#define RCC_XBAR5CFGR_XBAR5EN BIT(6)
+#define RCC_XBAR5CFGR_XBAR5STS BIT(7)
+
+/* RCC_XBAR6CFGR register fields */
+#define RCC_XBAR6CFGR_XBAR6SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR6CFGR_XBAR6SEL_SHIFT 0
+#define RCC_XBAR6CFGR_XBAR6EN BIT(6)
+#define RCC_XBAR6CFGR_XBAR6STS BIT(7)
+
+/* RCC_XBAR7CFGR register fields */
+#define RCC_XBAR7CFGR_XBAR7SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR7CFGR_XBAR7SEL_SHIFT 0
+#define RCC_XBAR7CFGR_XBAR7EN BIT(6)
+#define RCC_XBAR7CFGR_XBAR7STS BIT(7)
+
+/* RCC_XBAR8CFGR register fields */
+#define RCC_XBAR8CFGR_XBAR8SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR8CFGR_XBAR8SEL_SHIFT 0
+#define RCC_XBAR8CFGR_XBAR8EN BIT(6)
+#define RCC_XBAR8CFGR_XBAR8STS BIT(7)
+
+/* RCC_XBAR9CFGR register fields */
+#define RCC_XBAR9CFGR_XBAR9SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR9CFGR_XBAR9SEL_SHIFT 0
+#define RCC_XBAR9CFGR_XBAR9EN BIT(6)
+#define RCC_XBAR9CFGR_XBAR9STS BIT(7)
+
+/* RCC_XBAR10CFGR register fields */
+#define RCC_XBAR10CFGR_XBAR10SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR10CFGR_XBAR10SEL_SHIFT 0
+#define RCC_XBAR10CFGR_XBAR10EN BIT(6)
+#define RCC_XBAR10CFGR_XBAR10STS BIT(7)
+
+/* RCC_XBAR11CFGR register fields */
+#define RCC_XBAR11CFGR_XBAR11SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR11CFGR_XBAR11SEL_SHIFT 0
+#define RCC_XBAR11CFGR_XBAR11EN BIT(6)
+#define RCC_XBAR11CFGR_XBAR11STS BIT(7)
+
+/* RCC_XBAR12CFGR register fields */
+#define RCC_XBAR12CFGR_XBAR12SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR12CFGR_XBAR12SEL_SHIFT 0
+#define RCC_XBAR12CFGR_XBAR12EN BIT(6)
+#define RCC_XBAR12CFGR_XBAR12STS BIT(7)
+
+/* RCC_XBAR13CFGR register fields */
+#define RCC_XBAR13CFGR_XBAR13SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR13CFGR_XBAR13SEL_SHIFT 0
+#define RCC_XBAR13CFGR_XBAR13EN BIT(6)
+#define RCC_XBAR13CFGR_XBAR13STS BIT(7)
+
+/* RCC_XBAR14CFGR register fields */
+#define RCC_XBAR14CFGR_XBAR14SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR14CFGR_XBAR14SEL_SHIFT 0
+#define RCC_XBAR14CFGR_XBAR14EN BIT(6)
+#define RCC_XBAR14CFGR_XBAR14STS BIT(7)
+
+/* RCC_XBAR15CFGR register fields */
+#define RCC_XBAR15CFGR_XBAR15SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR15CFGR_XBAR15SEL_SHIFT 0
+#define RCC_XBAR15CFGR_XBAR15EN BIT(6)
+#define RCC_XBAR15CFGR_XBAR15STS BIT(7)
+
+/* RCC_XBAR16CFGR register fields */
+#define RCC_XBAR16CFGR_XBAR16SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR16CFGR_XBAR16SEL_SHIFT 0
+#define RCC_XBAR16CFGR_XBAR16EN BIT(6)
+#define RCC_XBAR16CFGR_XBAR16STS BIT(7)
+
+/* RCC_XBAR17CFGR register fields */
+#define RCC_XBAR17CFGR_XBAR17SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR17CFGR_XBAR17SEL_SHIFT 0
+#define RCC_XBAR17CFGR_XBAR17EN BIT(6)
+#define RCC_XBAR17CFGR_XBAR17STS BIT(7)
+
+/* RCC_XBAR18CFGR register fields */
+#define RCC_XBAR18CFGR_XBAR18SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR18CFGR_XBAR18SEL_SHIFT 0
+#define RCC_XBAR18CFGR_XBAR18EN BIT(6)
+#define RCC_XBAR18CFGR_XBAR18STS BIT(7)
+
+/* RCC_XBAR19CFGR register fields */
+#define RCC_XBAR19CFGR_XBAR19SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR19CFGR_XBAR19SEL_SHIFT 0
+#define RCC_XBAR19CFGR_XBAR19EN BIT(6)
+#define RCC_XBAR19CFGR_XBAR19STS BIT(7)
+
+/* RCC_XBAR20CFGR register fields */
+#define RCC_XBAR20CFGR_XBAR20SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR20CFGR_XBAR20SEL_SHIFT 0
+#define RCC_XBAR20CFGR_XBAR20EN BIT(6)
+#define RCC_XBAR20CFGR_XBAR20STS BIT(7)
+
+/* RCC_XBAR21CFGR register fields */
+#define RCC_XBAR21CFGR_XBAR21SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR21CFGR_XBAR21SEL_SHIFT 0
+#define RCC_XBAR21CFGR_XBAR21EN BIT(6)
+#define RCC_XBAR21CFGR_XBAR21STS BIT(7)
+
+/* RCC_XBAR22CFGR register fields */
+#define RCC_XBAR22CFGR_XBAR22SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR22CFGR_XBAR22SEL_SHIFT 0
+#define RCC_XBAR22CFGR_XBAR22EN BIT(6)
+#define RCC_XBAR22CFGR_XBAR22STS BIT(7)
+
+/* RCC_XBAR23CFGR register fields */
+#define RCC_XBAR23CFGR_XBAR23SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR23CFGR_XBAR23SEL_SHIFT 0
+#define RCC_XBAR23CFGR_XBAR23EN BIT(6)
+#define RCC_XBAR23CFGR_XBAR23STS BIT(7)
+
+/* RCC_XBAR24CFGR register fields */
+#define RCC_XBAR24CFGR_XBAR24SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR24CFGR_XBAR24SEL_SHIFT 0
+#define RCC_XBAR24CFGR_XBAR24EN BIT(6)
+#define RCC_XBAR24CFGR_XBAR24STS BIT(7)
+
+/* RCC_XBAR25CFGR register fields */
+#define RCC_XBAR25CFGR_XBAR25SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR25CFGR_XBAR25SEL_SHIFT 0
+#define RCC_XBAR25CFGR_XBAR25EN BIT(6)
+#define RCC_XBAR25CFGR_XBAR25STS BIT(7)
+
+/* RCC_XBAR26CFGR register fields */
+#define RCC_XBAR26CFGR_XBAR26SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR26CFGR_XBAR26SEL_SHIFT 0
+#define RCC_XBAR26CFGR_XBAR26EN BIT(6)
+#define RCC_XBAR26CFGR_XBAR26STS BIT(7)
+
+/* RCC_XBAR27CFGR register fields */
+#define RCC_XBAR27CFGR_XBAR27SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR27CFGR_XBAR27SEL_SHIFT 0
+#define RCC_XBAR27CFGR_XBAR27EN BIT(6)
+#define RCC_XBAR27CFGR_XBAR27STS BIT(7)
+
+/* RCC_XBAR28CFGR register fields */
+#define RCC_XBAR28CFGR_XBAR28SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR28CFGR_XBAR28SEL_SHIFT 0
+#define RCC_XBAR28CFGR_XBAR28EN BIT(6)
+#define RCC_XBAR28CFGR_XBAR28STS BIT(7)
+
+/* RCC_XBAR29CFGR register fields */
+#define RCC_XBAR29CFGR_XBAR29SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR29CFGR_XBAR29SEL_SHIFT 0
+#define RCC_XBAR29CFGR_XBAR29EN BIT(6)
+#define RCC_XBAR29CFGR_XBAR29STS BIT(7)
+
+/* RCC_XBAR30CFGR register fields */
+#define RCC_XBAR30CFGR_XBAR30SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR30CFGR_XBAR30SEL_SHIFT 0
+#define RCC_XBAR30CFGR_XBAR30EN BIT(6)
+#define RCC_XBAR30CFGR_XBAR30STS BIT(7)
+
+/* RCC_XBAR31CFGR register fields */
+#define RCC_XBAR31CFGR_XBAR31SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR31CFGR_XBAR31SEL_SHIFT 0
+#define RCC_XBAR31CFGR_XBAR31EN BIT(6)
+#define RCC_XBAR31CFGR_XBAR31STS BIT(7)
+
+/* RCC_XBAR32CFGR register fields */
+#define RCC_XBAR32CFGR_XBAR32SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR32CFGR_XBAR32SEL_SHIFT 0
+#define RCC_XBAR32CFGR_XBAR32EN BIT(6)
+#define RCC_XBAR32CFGR_XBAR32STS BIT(7)
+
+/* RCC_XBAR33CFGR register fields */
+#define RCC_XBAR33CFGR_XBAR33SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR33CFGR_XBAR33SEL_SHIFT 0
+#define RCC_XBAR33CFGR_XBAR33EN BIT(6)
+#define RCC_XBAR33CFGR_XBAR33STS BIT(7)
+
+/* RCC_XBAR34CFGR register fields */
+#define RCC_XBAR34CFGR_XBAR34SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR34CFGR_XBAR34SEL_SHIFT 0
+#define RCC_XBAR34CFGR_XBAR34EN BIT(6)
+#define RCC_XBAR34CFGR_XBAR34STS BIT(7)
+
+/* RCC_XBAR35CFGR register fields */
+#define RCC_XBAR35CFGR_XBAR35SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR35CFGR_XBAR35SEL_SHIFT 0
+#define RCC_XBAR35CFGR_XBAR35EN BIT(6)
+#define RCC_XBAR35CFGR_XBAR35STS BIT(7)
+
+/* RCC_XBAR36CFGR register fields */
+#define RCC_XBAR36CFGR_XBAR36SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR36CFGR_XBAR36SEL_SHIFT 0
+#define RCC_XBAR36CFGR_XBAR36EN BIT(6)
+#define RCC_XBAR36CFGR_XBAR36STS BIT(7)
+
+/* RCC_XBAR37CFGR register fields */
+#define RCC_XBAR37CFGR_XBAR37SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR37CFGR_XBAR37SEL_SHIFT 0
+#define RCC_XBAR37CFGR_XBAR37EN BIT(6)
+#define RCC_XBAR37CFGR_XBAR37STS BIT(7)
+
+/* RCC_XBAR38CFGR register fields */
+#define RCC_XBAR38CFGR_XBAR38SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR38CFGR_XBAR38SEL_SHIFT 0
+#define RCC_XBAR38CFGR_XBAR38EN BIT(6)
+#define RCC_XBAR38CFGR_XBAR38STS BIT(7)
+
+/* RCC_XBAR39CFGR register fields */
+#define RCC_XBAR39CFGR_XBAR39SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR39CFGR_XBAR39SEL_SHIFT 0
+#define RCC_XBAR39CFGR_XBAR39EN BIT(6)
+#define RCC_XBAR39CFGR_XBAR39STS BIT(7)
+
+/* RCC_XBAR40CFGR register fields */
+#define RCC_XBAR40CFGR_XBAR40SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR40CFGR_XBAR40SEL_SHIFT 0
+#define RCC_XBAR40CFGR_XBAR40EN BIT(6)
+#define RCC_XBAR40CFGR_XBAR40STS BIT(7)
+
+/* RCC_XBAR41CFGR register fields */
+#define RCC_XBAR41CFGR_XBAR41SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR41CFGR_XBAR41SEL_SHIFT 0
+#define RCC_XBAR41CFGR_XBAR41EN BIT(6)
+#define RCC_XBAR41CFGR_XBAR41STS BIT(7)
+
+/* RCC_XBAR42CFGR register fields */
+#define RCC_XBAR42CFGR_XBAR42SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR42CFGR_XBAR42SEL_SHIFT 0
+#define RCC_XBAR42CFGR_XBAR42EN BIT(6)
+#define RCC_XBAR42CFGR_XBAR42STS BIT(7)
+
+/* RCC_XBAR43CFGR register fields */
+#define RCC_XBAR43CFGR_XBAR43SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR43CFGR_XBAR43SEL_SHIFT 0
+#define RCC_XBAR43CFGR_XBAR43EN BIT(6)
+#define RCC_XBAR43CFGR_XBAR43STS BIT(7)
+
+/* RCC_XBAR44CFGR register fields */
+#define RCC_XBAR44CFGR_XBAR44SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR44CFGR_XBAR44SEL_SHIFT 0
+#define RCC_XBAR44CFGR_XBAR44EN BIT(6)
+#define RCC_XBAR44CFGR_XBAR44STS BIT(7)
+
+/* RCC_XBAR45CFGR register fields */
+#define RCC_XBAR45CFGR_XBAR45SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR45CFGR_XBAR45SEL_SHIFT 0
+#define RCC_XBAR45CFGR_XBAR45EN BIT(6)
+#define RCC_XBAR45CFGR_XBAR45STS BIT(7)
+
+/* RCC_XBAR46CFGR register fields */
+#define RCC_XBAR46CFGR_XBAR46SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR46CFGR_XBAR46SEL_SHIFT 0
+#define RCC_XBAR46CFGR_XBAR46EN BIT(6)
+#define RCC_XBAR46CFGR_XBAR46STS BIT(7)
+
+/* RCC_XBAR47CFGR register fields */
+#define RCC_XBAR47CFGR_XBAR47SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR47CFGR_XBAR47SEL_SHIFT 0
+#define RCC_XBAR47CFGR_XBAR47EN BIT(6)
+#define RCC_XBAR47CFGR_XBAR47STS BIT(7)
+
+/* RCC_XBAR48CFGR register fields */
+#define RCC_XBAR48CFGR_XBAR48SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR48CFGR_XBAR48SEL_SHIFT 0
+#define RCC_XBAR48CFGR_XBAR48EN BIT(6)
+#define RCC_XBAR48CFGR_XBAR48STS BIT(7)
+
+/* RCC_XBAR49CFGR register fields */
+#define RCC_XBAR49CFGR_XBAR49SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR49CFGR_XBAR49SEL_SHIFT 0
+#define RCC_XBAR49CFGR_XBAR49EN BIT(6)
+#define RCC_XBAR49CFGR_XBAR49STS BIT(7)
+
+/* RCC_XBAR50CFGR register fields */
+#define RCC_XBAR50CFGR_XBAR50SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR50CFGR_XBAR50SEL_SHIFT 0
+#define RCC_XBAR50CFGR_XBAR50EN BIT(6)
+#define RCC_XBAR50CFGR_XBAR50STS BIT(7)
+
+/* RCC_XBAR51CFGR register fields */
+#define RCC_XBAR51CFGR_XBAR51SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR51CFGR_XBAR51SEL_SHIFT 0
+#define RCC_XBAR51CFGR_XBAR51EN BIT(6)
+#define RCC_XBAR51CFGR_XBAR51STS BIT(7)
+
+/* RCC_XBAR52CFGR register fields */
+#define RCC_XBAR52CFGR_XBAR52SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR52CFGR_XBAR52SEL_SHIFT 0
+#define RCC_XBAR52CFGR_XBAR52EN BIT(6)
+#define RCC_XBAR52CFGR_XBAR52STS BIT(7)
+
+/* RCC_XBAR53CFGR register fields */
+#define RCC_XBAR53CFGR_XBAR53SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR53CFGR_XBAR53SEL_SHIFT 0
+#define RCC_XBAR53CFGR_XBAR53EN BIT(6)
+#define RCC_XBAR53CFGR_XBAR53STS BIT(7)
+
+/* RCC_XBAR54CFGR register fields */
+#define RCC_XBAR54CFGR_XBAR54SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR54CFGR_XBAR54SEL_SHIFT 0
+#define RCC_XBAR54CFGR_XBAR54EN BIT(6)
+#define RCC_XBAR54CFGR_XBAR54STS BIT(7)
+
+/* RCC_XBAR55CFGR register fields */
+#define RCC_XBAR55CFGR_XBAR55SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR55CFGR_XBAR55SEL_SHIFT 0
+#define RCC_XBAR55CFGR_XBAR55EN BIT(6)
+#define RCC_XBAR55CFGR_XBAR55STS BIT(7)
+
+/* RCC_XBAR56CFGR register fields */
+#define RCC_XBAR56CFGR_XBAR56SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR56CFGR_XBAR56SEL_SHIFT 0
+#define RCC_XBAR56CFGR_XBAR56EN BIT(6)
+#define RCC_XBAR56CFGR_XBAR56STS BIT(7)
+
+/* RCC_XBAR57CFGR register fields */
+#define RCC_XBAR57CFGR_XBAR57SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR57CFGR_XBAR57SEL_SHIFT 0
+#define RCC_XBAR57CFGR_XBAR57EN BIT(6)
+#define RCC_XBAR57CFGR_XBAR57STS BIT(7)
+
+/* RCC_XBAR58CFGR register fields */
+#define RCC_XBAR58CFGR_XBAR58SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR58CFGR_XBAR58SEL_SHIFT 0
+#define RCC_XBAR58CFGR_XBAR58EN BIT(6)
+#define RCC_XBAR58CFGR_XBAR58STS BIT(7)
+
+/* RCC_XBAR59CFGR register fields */
+#define RCC_XBAR59CFGR_XBAR59SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR59CFGR_XBAR59SEL_SHIFT 0
+#define RCC_XBAR59CFGR_XBAR59EN BIT(6)
+#define RCC_XBAR59CFGR_XBAR59STS BIT(7)
+
+/* RCC_XBAR60CFGR register fields */
+#define RCC_XBAR60CFGR_XBAR60SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR60CFGR_XBAR60SEL_SHIFT 0
+#define RCC_XBAR60CFGR_XBAR60EN BIT(6)
+#define RCC_XBAR60CFGR_XBAR60STS BIT(7)
+
+/* RCC_XBAR61CFGR register fields */
+#define RCC_XBAR61CFGR_XBAR61SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR61CFGR_XBAR61SEL_SHIFT 0
+#define RCC_XBAR61CFGR_XBAR61EN BIT(6)
+#define RCC_XBAR61CFGR_XBAR61STS BIT(7)
+
+/* RCC_XBAR62CFGR register fields */
+#define RCC_XBAR62CFGR_XBAR62SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR62CFGR_XBAR62SEL_SHIFT 0
+#define RCC_XBAR62CFGR_XBAR62EN BIT(6)
+#define RCC_XBAR62CFGR_XBAR62STS BIT(7)
+
+/* RCC_XBAR63CFGR register fields */
+#define RCC_XBAR63CFGR_XBAR63SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR63CFGR_XBAR63SEL_SHIFT 0
+#define RCC_XBAR63CFGR_XBAR63EN BIT(6)
+#define RCC_XBAR63CFGR_XBAR63STS BIT(7)
+
+/* RCC_XBARxCFGR register fields */
+#define RCC_XBARxCFGR_XBARxSEL_MASK GENMASK_32(3, 0)
+#define RCC_XBARxCFGR_XBARxSEL_SHIFT 0
+#define RCC_XBARxCFGR_XBARxEN BIT(6)
+#define RCC_XBARxCFGR_XBARxSTS BIT(7)
+
+/* RCC_PREDIV0CFGR register fields */
+#define RCC_PREDIV0CFGR_PREDIV0_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV0CFGR_PREDIV0_SHIFT 0
+
+/* RCC_PREDIV1CFGR register fields */
+#define RCC_PREDIV1CFGR_PREDIV1_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV1CFGR_PREDIV1_SHIFT 0
+
+/* RCC_PREDIV2CFGR register fields */
+#define RCC_PREDIV2CFGR_PREDIV2_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV2CFGR_PREDIV2_SHIFT 0
+
+/* RCC_PREDIV3CFGR register fields */
+#define RCC_PREDIV3CFGR_PREDIV3_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV3CFGR_PREDIV3_SHIFT 0
+
+/* RCC_PREDIV4CFGR register fields */
+#define RCC_PREDIV4CFGR_PREDIV4_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV4CFGR_PREDIV4_SHIFT 0
+
+/* RCC_PREDIV5CFGR register fields */
+#define RCC_PREDIV5CFGR_PREDIV5_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV5CFGR_PREDIV5_SHIFT 0
+
+/* RCC_PREDIV6CFGR register fields */
+#define RCC_PREDIV6CFGR_PREDIV6_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV6CFGR_PREDIV6_SHIFT 0
+
+/* RCC_PREDIV7CFGR register fields */
+#define RCC_PREDIV7CFGR_PREDIV7_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV7CFGR_PREDIV7_SHIFT 0
+
+/* RCC_PREDIV8CFGR register fields */
+#define RCC_PREDIV8CFGR_PREDIV8_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV8CFGR_PREDIV8_SHIFT 0
+
+/* RCC_PREDIV9CFGR register fields */
+#define RCC_PREDIV9CFGR_PREDIV9_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV9CFGR_PREDIV9_SHIFT 0
+
+/* RCC_PREDIV10CFGR register fields */
+#define RCC_PREDIV10CFGR_PREDIV10_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV10CFGR_PREDIV10_SHIFT 0
+
+/* RCC_PREDIV11CFGR register fields */
+#define RCC_PREDIV11CFGR_PREDIV11_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV11CFGR_PREDIV11_SHIFT 0
+
+/* RCC_PREDIV12CFGR register fields */
+#define RCC_PREDIV12CFGR_PREDIV12_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV12CFGR_PREDIV12_SHIFT 0
+
+/* RCC_PREDIV13CFGR register fields */
+#define RCC_PREDIV13CFGR_PREDIV13_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV13CFGR_PREDIV13_SHIFT 0
+
+/* RCC_PREDIV14CFGR register fields */
+#define RCC_PREDIV14CFGR_PREDIV14_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV14CFGR_PREDIV14_SHIFT 0
+
+/* RCC_PREDIV15CFGR register fields */
+#define RCC_PREDIV15CFGR_PREDIV15_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV15CFGR_PREDIV15_SHIFT 0
+
+/* RCC_PREDIV16CFGR register fields */
+#define RCC_PREDIV16CFGR_PREDIV16_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV16CFGR_PREDIV16_SHIFT 0
+
+/* RCC_PREDIV17CFGR register fields */
+#define RCC_PREDIV17CFGR_PREDIV17_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV17CFGR_PREDIV17_SHIFT 0
+
+/* RCC_PREDIV18CFGR register fields */
+#define RCC_PREDIV18CFGR_PREDIV18_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV18CFGR_PREDIV18_SHIFT 0
+
+/* RCC_PREDIV19CFGR register fields */
+#define RCC_PREDIV19CFGR_PREDIV19_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV19CFGR_PREDIV19_SHIFT 0
+
+/* RCC_PREDIV20CFGR register fields */
+#define RCC_PREDIV20CFGR_PREDIV20_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV20CFGR_PREDIV20_SHIFT 0
+
+/* RCC_PREDIV21CFGR register fields */
+#define RCC_PREDIV21CFGR_PREDIV21_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV21CFGR_PREDIV21_SHIFT 0
+
+/* RCC_PREDIV22CFGR register fields */
+#define RCC_PREDIV22CFGR_PREDIV22_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV22CFGR_PREDIV22_SHIFT 0
+
+/* RCC_PREDIV23CFGR register fields */
+#define RCC_PREDIV23CFGR_PREDIV23_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV23CFGR_PREDIV23_SHIFT 0
+
+/* RCC_PREDIV24CFGR register fields */
+#define RCC_PREDIV24CFGR_PREDIV24_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV24CFGR_PREDIV24_SHIFT 0
+
+/* RCC_PREDIV25CFGR register fields */
+#define RCC_PREDIV25CFGR_PREDIV25_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV25CFGR_PREDIV25_SHIFT 0
+
+/* RCC_PREDIV26CFGR register fields */
+#define RCC_PREDIV26CFGR_PREDIV26_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV26CFGR_PREDIV26_SHIFT 0
+
+/* RCC_PREDIV27CFGR register fields */
+#define RCC_PREDIV27CFGR_PREDIV27_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV27CFGR_PREDIV27_SHIFT 0
+
+/* RCC_PREDIV28CFGR register fields */
+#define RCC_PREDIV28CFGR_PREDIV28_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV28CFGR_PREDIV28_SHIFT 0
+
+/* RCC_PREDIV29CFGR register fields */
+#define RCC_PREDIV29CFGR_PREDIV29_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV29CFGR_PREDIV29_SHIFT 0
+
+/* RCC_PREDIV30CFGR register fields */
+#define RCC_PREDIV30CFGR_PREDIV30_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV30CFGR_PREDIV30_SHIFT 0
+
+/* RCC_PREDIV31CFGR register fields */
+#define RCC_PREDIV31CFGR_PREDIV31_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV31CFGR_PREDIV31_SHIFT 0
+
+/* RCC_PREDIV32CFGR register fields */
+#define RCC_PREDIV32CFGR_PREDIV32_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV32CFGR_PREDIV32_SHIFT 0
+
+/* RCC_PREDIV33CFGR register fields */
+#define RCC_PREDIV33CFGR_PREDIV33_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV33CFGR_PREDIV33_SHIFT 0
+
+/* RCC_PREDIV34CFGR register fields */
+#define RCC_PREDIV34CFGR_PREDIV34_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV34CFGR_PREDIV34_SHIFT 0
+
+/* RCC_PREDIV35CFGR register fields */
+#define RCC_PREDIV35CFGR_PREDIV35_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV35CFGR_PREDIV35_SHIFT 0
+
+/* RCC_PREDIV36CFGR register fields */
+#define RCC_PREDIV36CFGR_PREDIV36_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV36CFGR_PREDIV36_SHIFT 0
+
+/* RCC_PREDIV37CFGR register fields */
+#define RCC_PREDIV37CFGR_PREDIV37_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV37CFGR_PREDIV37_SHIFT 0
+
+/* RCC_PREDIV38CFGR register fields */
+#define RCC_PREDIV38CFGR_PREDIV38_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV38CFGR_PREDIV38_SHIFT 0
+
+/* RCC_PREDIV39CFGR register fields */
+#define RCC_PREDIV39CFGR_PREDIV39_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV39CFGR_PREDIV39_SHIFT 0
+
+/* RCC_PREDIV40CFGR register fields */
+#define RCC_PREDIV40CFGR_PREDIV40_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV40CFGR_PREDIV40_SHIFT 0
+
+/* RCC_PREDIV41CFGR register fields */
+#define RCC_PREDIV41CFGR_PREDIV41_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV41CFGR_PREDIV41_SHIFT 0
+
+/* RCC_PREDIV42CFGR register fields */
+#define RCC_PREDIV42CFGR_PREDIV42_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV42CFGR_PREDIV42_SHIFT 0
+
+/* RCC_PREDIV43CFGR register fields */
+#define RCC_PREDIV43CFGR_PREDIV43_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV43CFGR_PREDIV43_SHIFT 0
+
+/* RCC_PREDIV44CFGR register fields */
+#define RCC_PREDIV44CFGR_PREDIV44_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV44CFGR_PREDIV44_SHIFT 0
+
+/* RCC_PREDIV45CFGR register fields */
+#define RCC_PREDIV45CFGR_PREDIV45_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV45CFGR_PREDIV45_SHIFT 0
+
+/* RCC_PREDIV46CFGR register fields */
+#define RCC_PREDIV46CFGR_PREDIV46_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV46CFGR_PREDIV46_SHIFT 0
+
+/* RCC_PREDIV47CFGR register fields */
+#define RCC_PREDIV47CFGR_PREDIV47_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV47CFGR_PREDIV47_SHIFT 0
+
+/* RCC_PREDIV48CFGR register fields */
+#define RCC_PREDIV48CFGR_PREDIV48_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV48CFGR_PREDIV48_SHIFT 0
+
+/* RCC_PREDIV49CFGR register fields */
+#define RCC_PREDIV49CFGR_PREDIV49_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV49CFGR_PREDIV49_SHIFT 0
+
+/* RCC_PREDIV50CFGR register fields */
+#define RCC_PREDIV50CFGR_PREDIV50_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV50CFGR_PREDIV50_SHIFT 0
+
+/* RCC_PREDIV51CFGR register fields */
+#define RCC_PREDIV51CFGR_PREDIV51_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV51CFGR_PREDIV51_SHIFT 0
+
+/* RCC_PREDIV52CFGR register fields */
+#define RCC_PREDIV52CFGR_PREDIV52_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV52CFGR_PREDIV52_SHIFT 0
+
+/* RCC_PREDIV53CFGR register fields */
+#define RCC_PREDIV53CFGR_PREDIV53_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV53CFGR_PREDIV53_SHIFT 0
+
+/* RCC_PREDIV54CFGR register fields */
+#define RCC_PREDIV54CFGR_PREDIV54_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV54CFGR_PREDIV54_SHIFT 0
+
+/* RCC_PREDIV55CFGR register fields */
+#define RCC_PREDIV55CFGR_PREDIV55_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV55CFGR_PREDIV55_SHIFT 0
+
+/* RCC_PREDIV56CFGR register fields */
+#define RCC_PREDIV56CFGR_PREDIV56_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV56CFGR_PREDIV56_SHIFT 0
+
+/* RCC_PREDIV57CFGR register fields */
+#define RCC_PREDIV57CFGR_PREDIV57_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV57CFGR_PREDIV57_SHIFT 0
+
+/* RCC_PREDIV58CFGR register fields */
+#define RCC_PREDIV58CFGR_PREDIV58_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV58CFGR_PREDIV58_SHIFT 0
+
+/* RCC_PREDIV59CFGR register fields */
+#define RCC_PREDIV59CFGR_PREDIV59_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV59CFGR_PREDIV59_SHIFT 0
+
+/* RCC_PREDIV60CFGR register fields */
+#define RCC_PREDIV60CFGR_PREDIV60_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV60CFGR_PREDIV60_SHIFT 0
+
+/* RCC_PREDIV61CFGR register fields */
+#define RCC_PREDIV61CFGR_PREDIV61_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV61CFGR_PREDIV61_SHIFT 0
+
+/* RCC_PREDIV62CFGR register fields */
+#define RCC_PREDIV62CFGR_PREDIV62_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV62CFGR_PREDIV62_SHIFT 0
+
+/* RCC_PREDIV63CFGR register fields */
+#define RCC_PREDIV63CFGR_PREDIV63_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV63CFGR_PREDIV63_SHIFT 0
+
+/* RCC_PREDIVxCFGR register fields */
+#define RCC_PREDIVxCFGR_PREDIVx_MASK GENMASK_32(9, 0)
+#define RCC_PREDIVxCFGR_PREDIVx_SHIFT 0
+
+/* RCC_FINDIV0CFGR register fields */
+#define RCC_FINDIV0CFGR_FINDIV0_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV0CFGR_FINDIV0_SHIFT 0
+#define RCC_FINDIV0CFGR_FINDIV0EN BIT(6)
+
+/* RCC_FINDIV1CFGR register fields */
+#define RCC_FINDIV1CFGR_FINDIV1_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV1CFGR_FINDIV1_SHIFT 0
+#define RCC_FINDIV1CFGR_FINDIV1EN BIT(6)
+
+/* RCC_FINDIV2CFGR register fields */
+#define RCC_FINDIV2CFGR_FINDIV2_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV2CFGR_FINDIV2_SHIFT 0
+#define RCC_FINDIV2CFGR_FINDIV2EN BIT(6)
+
+/* RCC_FINDIV3CFGR register fields */
+#define RCC_FINDIV3CFGR_FINDIV3_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV3CFGR_FINDIV3_SHIFT 0
+#define RCC_FINDIV3CFGR_FINDIV3EN BIT(6)
+
+/* RCC_FINDIV4CFGR register fields */
+#define RCC_FINDIV4CFGR_FINDIV4_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV4CFGR_FINDIV4_SHIFT 0
+#define RCC_FINDIV4CFGR_FINDIV4EN BIT(6)
+
+/* RCC_FINDIV5CFGR register fields */
+#define RCC_FINDIV5CFGR_FINDIV5_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV5CFGR_FINDIV5_SHIFT 0
+#define RCC_FINDIV5CFGR_FINDIV5EN BIT(6)
+
+/* RCC_FINDIV6CFGR register fields */
+#define RCC_FINDIV6CFGR_FINDIV6_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV6CFGR_FINDIV6_SHIFT 0
+#define RCC_FINDIV6CFGR_FINDIV6EN BIT(6)
+
+/* RCC_FINDIV7CFGR register fields */
+#define RCC_FINDIV7CFGR_FINDIV7_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV7CFGR_FINDIV7_SHIFT 0
+#define RCC_FINDIV7CFGR_FINDIV7EN BIT(6)
+
+/* RCC_FINDIV8CFGR register fields */
+#define RCC_FINDIV8CFGR_FINDIV8_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV8CFGR_FINDIV8_SHIFT 0
+#define RCC_FINDIV8CFGR_FINDIV8EN BIT(6)
+
+/* RCC_FINDIV9CFGR register fields */
+#define RCC_FINDIV9CFGR_FINDIV9_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV9CFGR_FINDIV9_SHIFT 0
+#define RCC_FINDIV9CFGR_FINDIV9EN BIT(6)
+
+/* RCC_FINDIV10CFGR register fields */
+#define RCC_FINDIV10CFGR_FINDIV10_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV10CFGR_FINDIV10_SHIFT 0
+#define RCC_FINDIV10CFGR_FINDIV10EN BIT(6)
+
+/* RCC_FINDIV11CFGR register fields */
+#define RCC_FINDIV11CFGR_FINDIV11_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV11CFGR_FINDIV11_SHIFT 0
+#define RCC_FINDIV11CFGR_FINDIV11EN BIT(6)
+
+/* RCC_FINDIV12CFGR register fields */
+#define RCC_FINDIV12CFGR_FINDIV12_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV12CFGR_FINDIV12_SHIFT 0
+#define RCC_FINDIV12CFGR_FINDIV12EN BIT(6)
+
+/* RCC_FINDIV13CFGR register fields */
+#define RCC_FINDIV13CFGR_FINDIV13_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV13CFGR_FINDIV13_SHIFT 0
+#define RCC_FINDIV13CFGR_FINDIV13EN BIT(6)
+
+/* RCC_FINDIV14CFGR register fields */
+#define RCC_FINDIV14CFGR_FINDIV14_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV14CFGR_FINDIV14_SHIFT 0
+#define RCC_FINDIV14CFGR_FINDIV14EN BIT(6)
+
+/* RCC_FINDIV15CFGR register fields */
+#define RCC_FINDIV15CFGR_FINDIV15_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV15CFGR_FINDIV15_SHIFT 0
+#define RCC_FINDIV15CFGR_FINDIV15EN BIT(6)
+
+/* RCC_FINDIV16CFGR register fields */
+#define RCC_FINDIV16CFGR_FINDIV16_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV16CFGR_FINDIV16_SHIFT 0
+#define RCC_FINDIV16CFGR_FINDIV16EN BIT(6)
+
+/* RCC_FINDIV17CFGR register fields */
+#define RCC_FINDIV17CFGR_FINDIV17_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV17CFGR_FINDIV17_SHIFT 0
+#define RCC_FINDIV17CFGR_FINDIV17EN BIT(6)
+
+/* RCC_FINDIV18CFGR register fields */
+#define RCC_FINDIV18CFGR_FINDIV18_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV18CFGR_FINDIV18_SHIFT 0
+#define RCC_FINDIV18CFGR_FINDIV18EN BIT(6)
+
+/* RCC_FINDIV19CFGR register fields */
+#define RCC_FINDIV19CFGR_FINDIV19_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV19CFGR_FINDIV19_SHIFT 0
+#define RCC_FINDIV19CFGR_FINDIV19EN BIT(6)
+
+/* RCC_FINDIV20CFGR register fields */
+#define RCC_FINDIV20CFGR_FINDIV20_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV20CFGR_FINDIV20_SHIFT 0
+#define RCC_FINDIV20CFGR_FINDIV20EN BIT(6)
+
+/* RCC_FINDIV21CFGR register fields */
+#define RCC_FINDIV21CFGR_FINDIV21_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV21CFGR_FINDIV21_SHIFT 0
+#define RCC_FINDIV21CFGR_FINDIV21EN BIT(6)
+
+/* RCC_FINDIV22CFGR register fields */
+#define RCC_FINDIV22CFGR_FINDIV22_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV22CFGR_FINDIV22_SHIFT 0
+#define RCC_FINDIV22CFGR_FINDIV22EN BIT(6)
+
+/* RCC_FINDIV23CFGR register fields */
+#define RCC_FINDIV23CFGR_FINDIV23_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV23CFGR_FINDIV23_SHIFT 0
+#define RCC_FINDIV23CFGR_FINDIV23EN BIT(6)
+
+/* RCC_FINDIV24CFGR register fields */
+#define RCC_FINDIV24CFGR_FINDIV24_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV24CFGR_FINDIV24_SHIFT 0
+#define RCC_FINDIV24CFGR_FINDIV24EN BIT(6)
+
+/* RCC_FINDIV25CFGR register fields */
+#define RCC_FINDIV25CFGR_FINDIV25_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV25CFGR_FINDIV25_SHIFT 0
+#define RCC_FINDIV25CFGR_FINDIV25EN BIT(6)
+
+/* RCC_FINDIV26CFGR register fields */
+#define RCC_FINDIV26CFGR_FINDIV26_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV26CFGR_FINDIV26_SHIFT 0
+#define RCC_FINDIV26CFGR_FINDIV26EN BIT(6)
+
+/* RCC_FINDIV27CFGR register fields */
+#define RCC_FINDIV27CFGR_FINDIV27_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV27CFGR_FINDIV27_SHIFT 0
+#define RCC_FINDIV27CFGR_FINDIV27EN BIT(6)
+
+/* RCC_FINDIV28CFGR register fields */
+#define RCC_FINDIV28CFGR_FINDIV28_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV28CFGR_FINDIV28_SHIFT 0
+#define RCC_FINDIV28CFGR_FINDIV28EN BIT(6)
+
+/* RCC_FINDIV29CFGR register fields */
+#define RCC_FINDIV29CFGR_FINDIV29_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV29CFGR_FINDIV29_SHIFT 0
+#define RCC_FINDIV29CFGR_FINDIV29EN BIT(6)
+
+/* RCC_FINDIV30CFGR register fields */
+#define RCC_FINDIV30CFGR_FINDIV30_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV30CFGR_FINDIV30_SHIFT 0
+#define RCC_FINDIV30CFGR_FINDIV30EN BIT(6)
+
+/* RCC_FINDIV31CFGR register fields */
+#define RCC_FINDIV31CFGR_FINDIV31_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV31CFGR_FINDIV31_SHIFT 0
+#define RCC_FINDIV31CFGR_FINDIV31EN BIT(6)
+
+/* RCC_FINDIV32CFGR register fields */
+#define RCC_FINDIV32CFGR_FINDIV32_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV32CFGR_FINDIV32_SHIFT 0
+#define RCC_FINDIV32CFGR_FINDIV32EN BIT(6)
+
+/* RCC_FINDIV33CFGR register fields */
+#define RCC_FINDIV33CFGR_FINDIV33_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV33CFGR_FINDIV33_SHIFT 0
+#define RCC_FINDIV33CFGR_FINDIV33EN BIT(6)
+
+/* RCC_FINDIV34CFGR register fields */
+#define RCC_FINDIV34CFGR_FINDIV34_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV34CFGR_FINDIV34_SHIFT 0
+#define RCC_FINDIV34CFGR_FINDIV34EN BIT(6)
+
+/* RCC_FINDIV35CFGR register fields */
+#define RCC_FINDIV35CFGR_FINDIV35_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV35CFGR_FINDIV35_SHIFT 0
+#define RCC_FINDIV35CFGR_FINDIV35EN BIT(6)
+
+/* RCC_FINDIV36CFGR register fields */
+#define RCC_FINDIV36CFGR_FINDIV36_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV36CFGR_FINDIV36_SHIFT 0
+#define RCC_FINDIV36CFGR_FINDIV36EN BIT(6)
+
+/* RCC_FINDIV37CFGR register fields */
+#define RCC_FINDIV37CFGR_FINDIV37_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV37CFGR_FINDIV37_SHIFT 0
+#define RCC_FINDIV37CFGR_FINDIV37EN BIT(6)
+
+/* RCC_FINDIV38CFGR register fields */
+#define RCC_FINDIV38CFGR_FINDIV38_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV38CFGR_FINDIV38_SHIFT 0
+#define RCC_FINDIV38CFGR_FINDIV38EN BIT(6)
+
+/* RCC_FINDIV39CFGR register fields */
+#define RCC_FINDIV39CFGR_FINDIV39_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV39CFGR_FINDIV39_SHIFT 0
+#define RCC_FINDIV39CFGR_FINDIV39EN BIT(6)
+
+/* RCC_FINDIV40CFGR register fields */
+#define RCC_FINDIV40CFGR_FINDIV40_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV40CFGR_FINDIV40_SHIFT 0
+#define RCC_FINDIV40CFGR_FINDIV40EN BIT(6)
+
+/* RCC_FINDIV41CFGR register fields */
+#define RCC_FINDIV41CFGR_FINDIV41_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV41CFGR_FINDIV41_SHIFT 0
+#define RCC_FINDIV41CFGR_FINDIV41EN BIT(6)
+
+/* RCC_FINDIV42CFGR register fields */
+#define RCC_FINDIV42CFGR_FINDIV42_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV42CFGR_FINDIV42_SHIFT 0
+#define RCC_FINDIV42CFGR_FINDIV42EN BIT(6)
+
+/* RCC_FINDIV43CFGR register fields */
+#define RCC_FINDIV43CFGR_FINDIV43_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV43CFGR_FINDIV43_SHIFT 0
+#define RCC_FINDIV43CFGR_FINDIV43EN BIT(6)
+
+/* RCC_FINDIV44CFGR register fields */
+#define RCC_FINDIV44CFGR_FINDIV44_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV44CFGR_FINDIV44_SHIFT 0
+#define RCC_FINDIV44CFGR_FINDIV44EN BIT(6)
+
+/* RCC_FINDIV45CFGR register fields */
+#define RCC_FINDIV45CFGR_FINDIV45_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV45CFGR_FINDIV45_SHIFT 0
+#define RCC_FINDIV45CFGR_FINDIV45EN BIT(6)
+
+/* RCC_FINDIV46CFGR register fields */
+#define RCC_FINDIV46CFGR_FINDIV46_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV46CFGR_FINDIV46_SHIFT 0
+#define RCC_FINDIV46CFGR_FINDIV46EN BIT(6)
+
+/* RCC_FINDIV47CFGR register fields */
+#define RCC_FINDIV47CFGR_FINDIV47_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV47CFGR_FINDIV47_SHIFT 0
+#define RCC_FINDIV47CFGR_FINDIV47EN BIT(6)
+
+/* RCC_FINDIV48CFGR register fields */
+#define RCC_FINDIV48CFGR_FINDIV48_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV48CFGR_FINDIV48_SHIFT 0
+#define RCC_FINDIV48CFGR_FINDIV48EN BIT(6)
+
+/* RCC_FINDIV49CFGR register fields */
+#define RCC_FINDIV49CFGR_FINDIV49_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV49CFGR_FINDIV49_SHIFT 0
+#define RCC_FINDIV49CFGR_FINDIV49EN BIT(6)
+
+/* RCC_FINDIV50CFGR register fields */
+#define RCC_FINDIV50CFGR_FINDIV50_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV50CFGR_FINDIV50_SHIFT 0
+#define RCC_FINDIV50CFGR_FINDIV50EN BIT(6)
+
+/* RCC_FINDIV51CFGR register fields */
+#define RCC_FINDIV51CFGR_FINDIV51_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV51CFGR_FINDIV51_SHIFT 0
+#define RCC_FINDIV51CFGR_FINDIV51EN BIT(6)
+
+/* RCC_FINDIV52CFGR register fields */
+#define RCC_FINDIV52CFGR_FINDIV52_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV52CFGR_FINDIV52_SHIFT 0
+#define RCC_FINDIV52CFGR_FINDIV52EN BIT(6)
+
+/* RCC_FINDIV53CFGR register fields */
+#define RCC_FINDIV53CFGR_FINDIV53_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV53CFGR_FINDIV53_SHIFT 0
+#define RCC_FINDIV53CFGR_FINDIV53EN BIT(6)
+
+/* RCC_FINDIV54CFGR register fields */
+#define RCC_FINDIV54CFGR_FINDIV54_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV54CFGR_FINDIV54_SHIFT 0
+#define RCC_FINDIV54CFGR_FINDIV54EN BIT(6)
+
+/* RCC_FINDIV55CFGR register fields */
+#define RCC_FINDIV55CFGR_FINDIV55_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV55CFGR_FINDIV55_SHIFT 0
+#define RCC_FINDIV55CFGR_FINDIV55EN BIT(6)
+
+/* RCC_FINDIV56CFGR register fields */
+#define RCC_FINDIV56CFGR_FINDIV56_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV56CFGR_FINDIV56_SHIFT 0
+#define RCC_FINDIV56CFGR_FINDIV56EN BIT(6)
+
+/* RCC_FINDIV57CFGR register fields */
+#define RCC_FINDIV57CFGR_FINDIV57_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV57CFGR_FINDIV57_SHIFT 0
+#define RCC_FINDIV57CFGR_FINDIV57EN BIT(6)
+
+/* RCC_FINDIV58CFGR register fields */
+#define RCC_FINDIV58CFGR_FINDIV58_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV58CFGR_FINDIV58_SHIFT 0
+#define RCC_FINDIV58CFGR_FINDIV58EN BIT(6)
+
+/* RCC_FINDIV59CFGR register fields */
+#define RCC_FINDIV59CFGR_FINDIV59_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV59CFGR_FINDIV59_SHIFT 0
+#define RCC_FINDIV59CFGR_FINDIV59EN BIT(6)
+
+/* RCC_FINDIV60CFGR register fields */
+#define RCC_FINDIV60CFGR_FINDIV60_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV60CFGR_FINDIV60_SHIFT 0
+#define RCC_FINDIV60CFGR_FINDIV60EN BIT(6)
+
+/* RCC_FINDIV61CFGR register fields */
+#define RCC_FINDIV61CFGR_FINDIV61_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV61CFGR_FINDIV61_SHIFT 0
+#define RCC_FINDIV61CFGR_FINDIV61EN BIT(6)
+
+/* RCC_FINDIV62CFGR register fields */
+#define RCC_FINDIV62CFGR_FINDIV62_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV62CFGR_FINDIV62_SHIFT 0
+#define RCC_FINDIV62CFGR_FINDIV62EN BIT(6)
+
+/* RCC_FINDIV63CFGR register fields */
+#define RCC_FINDIV63CFGR_FINDIV63_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV63CFGR_FINDIV63_SHIFT 0
+#define RCC_FINDIV63CFGR_FINDIV63EN BIT(6)
+
+/* RCC_FINDIVxCFGR register fields */
+#define RCC_FINDIVxCFGR_FINDIVx_MASK GENMASK_32(5, 0)
+#define RCC_FINDIVxCFGR_FINDIVx_SHIFT 0
+#define RCC_FINDIVxCFGR_FINDIVxEN BIT(6)
+
+/* RCC_FCALCOBS0CFGR register fields */
+#define RCC_FCALCOBS0CFGR_CKINTSEL_MASK GENMASK_32(7, 0)
+#define RCC_FCALCOBS0CFGR_CKINTSEL_SHIFT 0
+#define RCC_FCALCOBS0CFGR_CKEXTSEL_MASK GENMASK_32(10, 8)
+#define RCC_FCALCOBS0CFGR_CKEXTSEL_SHIFT 8
+#define RCC_FCALCOBS0CFGR_FCALCCKEXTSEL BIT(15)
+#define RCC_FCALCOBS0CFGR_CKOBSEXTSEL BIT(16)
+#define RCC_FCALCOBS0CFGR_FCALCCKINV BIT(17)
+#define RCC_FCALCOBS0CFGR_CKOBSINV BIT(18)
+#define RCC_FCALCOBS0CFGR_CKOBSDIV_MASK GENMASK_32(24, 22)
+#define RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT 22
+#define RCC_FCALCOBS0CFGR_FCALCCKEN BIT(25)
+#define RCC_FCALCOBS0CFGR_CKOBSEN BIT(26)
+
+/* RCC_FCALCOBS1CFGR register fields */
+#define RCC_FCALCOBS1CFGR_CKINTSEL_MASK GENMASK_32(7, 0)
+#define RCC_FCALCOBS1CFGR_CKINTSEL_SHIFT 0
+#define RCC_FCALCOBS1CFGR_CKEXTSEL_MASK GENMASK_32(10, 8)
+#define RCC_FCALCOBS1CFGR_CKEXTSEL_SHIFT 8
+#define RCC_FCALCOBS1CFGR_CKOBSEXTSEL BIT(16)
+#define RCC_FCALCOBS1CFGR_CKOBSINV BIT(18)
+#define RCC_FCALCOBS1CFGR_CKOBSDIV_MASK GENMASK_32(24, 22)
+#define RCC_FCALCOBS1CFGR_CKOBSDIV_SHIFT 22
+#define RCC_FCALCOBS1CFGR_CKOBSEN BIT(26)
+#define RCC_FCALCOBS1CFGR_FCALCRSTN BIT(27)
+
+/* RCC_FCALCREFCFGR register fields */
+#define RCC_FCALCREFCFGR_FCALCREFCKSEL_MASK GENMASK_32(2, 0)
+#define RCC_FCALCREFCFGR_FCALCREFCKSEL_SHIFT 0
+
+/* RCC_FCALCCR1 register fields */
+#define RCC_FCALCCR1_FCALCRUN BIT(0)
+
+/* RCC_FCALCCR2 register fields */
+#define RCC_FCALCCR2_FCALCMD_MASK GENMASK_32(4, 3)
+#define RCC_FCALCCR2_FCALCMD_SHIFT 3
+#define RCC_FCALCCR2_FCALCTWC_MASK GENMASK_32(14, 11)
+#define RCC_FCALCCR2_FCALCTWC_SHIFT 11
+#define RCC_FCALCCR2_FCALCTYP_MASK GENMASK_32(21, 17)
+#define RCC_FCALCCR2_FCALCTYP_SHIFT 17
+
+/* RCC_FCALCSR register fields */
+#define RCC_FCALCSR_FVAL_MASK GENMASK_32(16, 0)
+#define RCC_FCALCSR_FVAL_SHIFT 0
+#define RCC_FCALCSR_FCALCSTS BIT(19)
+
+/* RCC_PLL4CFGR1 register fields */
+#define RCC_PLL4CFGR1_SSMODRST BIT(0)
+#define RCC_PLL4CFGR1_PLLEN BIT(8)
+#define RCC_PLL4CFGR1_PLLRDY BIT(24)
+#define RCC_PLL4CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL4CFGR2 register fields */
+#define RCC_PLL4CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL4CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL4CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL4CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL4CFGR3 register fields */
+#define RCC_PLL4CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL4CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL4CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL4CFGR3_DACEN BIT(25)
+#define RCC_PLL4CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL4CFGR4 register fields */
+#define RCC_PLL4CFGR4_DSMEN BIT(8)
+#define RCC_PLL4CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL4CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL4CFGR5 register fields */
+#define RCC_PLL4CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL4CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL4CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL4CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL4CFGR6 register fields */
+#define RCC_PLL4CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL4CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL4CFGR7 register fields */
+#define RCC_PLL4CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL4CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLL5CFGR1 register fields */
+#define RCC_PLL5CFGR1_SSMODRST BIT(0)
+#define RCC_PLL5CFGR1_PLLEN BIT(8)
+#define RCC_PLL5CFGR1_PLLRDY BIT(24)
+#define RCC_PLL5CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL5CFGR2 register fields */
+#define RCC_PLL5CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL5CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL5CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL5CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL5CFGR3 register fields */
+#define RCC_PLL5CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL5CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL5CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL5CFGR3_DACEN BIT(25)
+#define RCC_PLL5CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL5CFGR4 register fields */
+#define RCC_PLL5CFGR4_DSMEN BIT(8)
+#define RCC_PLL5CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL5CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL5CFGR5 register fields */
+#define RCC_PLL5CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL5CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL5CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL5CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL5CFGR6 register fields */
+#define RCC_PLL5CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL5CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL5CFGR7 register fields */
+#define RCC_PLL5CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL5CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLL6CFGR1 register fields */
+#define RCC_PLL6CFGR1_SSMODRST BIT(0)
+#define RCC_PLL6CFGR1_PLLEN BIT(8)
+#define RCC_PLL6CFGR1_PLLRDY BIT(24)
+#define RCC_PLL6CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL6CFGR2 register fields */
+#define RCC_PLL6CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL6CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL6CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL6CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL6CFGR3 register fields */
+#define RCC_PLL6CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL6CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL6CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL6CFGR3_DACEN BIT(25)
+#define RCC_PLL6CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL6CFGR4 register fields */
+#define RCC_PLL6CFGR4_DSMEN BIT(8)
+#define RCC_PLL6CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL6CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL6CFGR5 register fields */
+#define RCC_PLL6CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL6CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL6CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL6CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL6CFGR6 register fields */
+#define RCC_PLL6CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL6CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL6CFGR7 register fields */
+#define RCC_PLL6CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL6CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLL7CFGR1 register fields */
+#define RCC_PLL7CFGR1_SSMODRST BIT(0)
+#define RCC_PLL7CFGR1_PLLEN BIT(8)
+#define RCC_PLL7CFGR1_PLLRDY BIT(24)
+#define RCC_PLL7CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL7CFGR2 register fields */
+#define RCC_PLL7CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL7CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL7CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL7CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL7CFGR3 register fields */
+#define RCC_PLL7CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL7CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL7CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL7CFGR3_DACEN BIT(25)
+#define RCC_PLL7CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL7CFGR4 register fields */
+#define RCC_PLL7CFGR4_DSMEN BIT(8)
+#define RCC_PLL7CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL7CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL7CFGR5 register fields */
+#define RCC_PLL7CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL7CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL7CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL7CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL7CFGR6 register fields */
+#define RCC_PLL7CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL7CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL7CFGR7 register fields */
+#define RCC_PLL7CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL7CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLL8CFGR1 register fields */
+#define RCC_PLL8CFGR1_SSMODRST BIT(0)
+#define RCC_PLL8CFGR1_PLLEN BIT(8)
+#define RCC_PLL8CFGR1_PLLRDY BIT(24)
+#define RCC_PLL8CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL8CFGR2 register fields */
+#define RCC_PLL8CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL8CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL8CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL8CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL8CFGR3 register fields */
+#define RCC_PLL8CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL8CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL8CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL8CFGR3_DACEN BIT(25)
+#define RCC_PLL8CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL8CFGR4 register fields */
+#define RCC_PLL8CFGR4_DSMEN BIT(8)
+#define RCC_PLL8CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL8CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL8CFGR5 register fields */
+#define RCC_PLL8CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL8CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL8CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL8CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL8CFGR6 register fields */
+#define RCC_PLL8CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL8CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL8CFGR7 register fields */
+#define RCC_PLL8CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL8CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLLxCFGR1 register fields */
+#define RCC_PLLxCFGR1_SSMODRST BIT(0)
+#define RCC_PLLxCFGR1_PLLEN BIT(8)
+#define RCC_PLLxCFGR1_PLLRDY BIT(24)
+#define RCC_PLLxCFGR1_CKREFST BIT(28)
+
+/* RCC_PLLxCFGR2 register fields */
+#define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLLxCFGR2_FREFDIV_SHIFT 0
+#define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLLxCFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLLxCFGR3 register fields */
+#define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLLxCFGR3_FRACIN_SHIFT 0
+#define RCC_PLLxCFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLLxCFGR3_DACEN BIT(25)
+#define RCC_PLLxCFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLLxCFGR4 register fields */
+#define RCC_PLLxCFGR4_DSMEN BIT(8)
+#define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLLxCFGR4_BYPASS BIT(10)
+
+/* RCC_PLLxCFGR5 register fields */
+#define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLLxCFGR5_DIVVAL_SHIFT 0
+#define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLLxCFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLLxCFGR6 register fields */
+#define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLLxCFGR7 register fields */
+#define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_VERR register fields */
+#define RCC_VERR_MINREV_MASK GENMASK_32(3, 0)
+#define RCC_VERR_MINREV_SHIFT 0
+#define RCC_VERR_MAJREV_MASK GENMASK_32(7, 4)
+#define RCC_VERR_MAJREV_SHIFT 4
+
+#endif /* STM32MP21_RCC_H */
diff --git a/include/drivers/st/stm32mp25_rcc.h b/include/drivers/st/stm32mp25_rcc.h
index d5d228c..752d3c3 100644
--- a/include/drivers/st/stm32mp25_rcc.h
+++ b/include/drivers/st/stm32mp25_rcc.h
@@ -2308,6 +2308,12 @@
#define RCC_C1BOOTRSTSCLRR_D1STBYRSTF BIT(22)
#define RCC_C1BOOTRSTSCLRR_D2STBYRSTF BIT(23)
+#define RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF (RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF)
+
/* RCC_C2BOOTRSTSSETR register fields */
#define RCC_C2BOOTRSTSSETR_PORRSTF BIT(0)
#define RCC_C2BOOTRSTSSETR_BORRSTF BIT(1)
diff --git a/include/drivers/st/stm32mp_ddr.h b/include/drivers/st/stm32mp_ddr.h
index 57b0668..970ff19 100644
--- a/include/drivers/st/stm32mp_ddr.h
+++ b/include/drivers/st/stm32mp_ddr.h
@@ -28,7 +28,7 @@
struct stm32mp_ddr_reg_desc {
uint16_t offset; /* Offset for base address */
uint8_t par_offset; /* Offset for parameter array */
-#if !STM32MP13 && !STM32MP15
+#ifdef STM32MP2X
bool qd; /* quasi-dynamic register if true */
#endif
};
diff --git a/include/dt-bindings/clock/st,stm32mp21-rcc.h b/include/dt-bindings/clock/st,stm32mp21-rcc.h
new file mode 100644
index 0000000..f23c536
--- /dev/null
+++ b/include/dt-bindings/clock/st,stm32mp21-rcc.h
@@ -0,0 +1,429 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
+ * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com>
+ */
+
+#ifndef _DT_BINDINGS_STM32MP21_CLKS_H_
+#define _DT_BINDINGS_STM32MP21_CLKS_H_
+
+/* INTERNAL/EXTERNAL OSCILLATORS */
+#define HSI_CK 0
+#define HSE_CK 1
+#define MSI_CK 2
+#define LSI_CK 3
+#define LSE_CK 4
+#define I2S_CK 5
+#define RTC_CK 6
+#define SPDIF_CK_SYMB 7
+
+/* PLL CLOCKS */
+#define PLL1_CK 8
+#define PLL2_CK 9
+#define PLL4_CK 10
+#define PLL5_CK 11
+#define PLL6_CK 12
+#define PLL7_CK 13
+#define PLL8_CK 14
+
+#define CK_CPU1 15
+
+/* APB DIV CLOCKS */
+#define CK_ICN_APB1 16
+#define CK_ICN_APB2 17
+#define CK_ICN_APB3 18
+#define CK_ICN_APB4 19
+#define CK_ICN_APB5 20
+#define CK_ICN_APBDBG 21
+
+/* GLOBAL TIMER */
+#define TIMG1_CK 22
+#define TIMG2_CK 23
+
+/* FLEXGEN CLOCKS */
+#define CK_ICN_HS_MCU 24
+#define CK_ICN_SDMMC 25
+#define CK_ICN_DDR 26
+#define CK_ICN_DISPLAY 27
+#define CK_ICN_HSL 28
+#define CK_ICN_NIC 29
+#define CK_ICN_VID 30
+#define CK_FLEXGEN_07 31
+#define CK_FLEXGEN_08 32
+#define CK_FLEXGEN_09 33
+#define CK_FLEXGEN_10 34
+#define CK_FLEXGEN_11 35
+#define CK_FLEXGEN_12 36
+#define CK_FLEXGEN_13 37
+#define CK_FLEXGEN_14 38
+#define CK_FLEXGEN_15 39
+#define CK_FLEXGEN_16 40
+#define CK_FLEXGEN_17 41
+#define CK_FLEXGEN_18 42
+#define CK_FLEXGEN_19 43
+#define CK_FLEXGEN_20 44
+#define CK_FLEXGEN_21 45
+#define CK_FLEXGEN_22 46
+#define CK_FLEXGEN_23 47
+#define CK_FLEXGEN_24 48
+#define CK_FLEXGEN_25 49
+#define CK_FLEXGEN_26 50
+#define CK_FLEXGEN_27 51
+#define CK_FLEXGEN_28 52
+#define CK_FLEXGEN_29 53
+#define CK_FLEXGEN_30 54
+#define CK_FLEXGEN_31 55
+#define CK_FLEXGEN_32 56
+#define CK_FLEXGEN_33 57
+#define CK_FLEXGEN_34 58
+#define CK_FLEXGEN_35 59
+#define CK_FLEXGEN_36 60
+#define CK_FLEXGEN_37 61
+#define CK_FLEXGEN_38 62
+#define CK_FLEXGEN_39 63
+#define CK_FLEXGEN_40 64
+#define CK_FLEXGEN_41 65
+#define CK_FLEXGEN_42 66
+#define CK_FLEXGEN_43 67
+#define CK_FLEXGEN_44 68
+#define CK_FLEXGEN_45 69
+#define CK_FLEXGEN_46 70
+#define CK_FLEXGEN_47 71
+#define CK_FLEXGEN_48 72
+#define CK_FLEXGEN_49 73
+#define CK_FLEXGEN_50 74
+#define CK_FLEXGEN_51 75
+#define CK_FLEXGEN_52 76
+#define CK_FLEXGEN_53 77
+#define CK_FLEXGEN_54 78
+#define CK_FLEXGEN_55 79
+#define CK_FLEXGEN_56 80
+#define CK_FLEXGEN_57 81
+#define CK_FLEXGEN_58 82
+#define CK_FLEXGEN_59 83
+#define CK_FLEXGEN_60 84
+#define CK_FLEXGEN_61 85
+#define CK_FLEXGEN_62 86
+#define CK_FLEXGEN_63 87
+
+/* LOW SPEED MCU CLOCK */
+#define CK_ICN_LS_MCU 88
+
+#define CK_BUS_STM 89
+#define CK_BUS_FMC 90
+#define CK_BUS_ETH1 91
+#define CK_BUS_ETH2 92
+#define CK_BUS_DDRPHYC 93
+#define CK_BUS_SYSCPU1 94
+#define CK_BUS_HPDMA1 95
+#define CK_BUS_HPDMA2 96
+#define CK_BUS_HPDMA3 97
+#define CK_BUS_ADC1 98
+#define CK_BUS_ADC2 99
+#define CK_BUS_IPCC1 100
+#define CK_BUS_DCMIPSSI 101
+#define CK_BUS_CRC 102
+#define CK_BUS_MDF1 103
+#define CK_BUS_BKPSRAM 104
+#define CK_BUS_HASH1 105
+#define CK_BUS_HASH2 106
+#define CK_BUS_RNG1 107
+#define CK_BUS_RNG2 108
+#define CK_BUS_CRYP1 109
+#define CK_BUS_CRYP2 110
+#define CK_BUS_SAES 111
+#define CK_BUS_PKA 112
+#define CK_BUS_GPIOA 113
+#define CK_BUS_GPIOB 114
+#define CK_BUS_GPIOC 115
+#define CK_BUS_GPIOD 116
+#define CK_BUS_GPIOE 117
+#define CK_BUS_GPIOF 118
+#define CK_BUS_GPIOG 119
+#define CK_BUS_GPIOH 120
+#define CK_BUS_GPIOI 121
+#define CK_BUS_GPIOZ 122
+#define CK_BUS_RTC 124
+#define CK_BUS_LPUART1 125
+#define CK_BUS_LPTIM3 126
+#define CK_BUS_LPTIM4 127
+#define CK_BUS_LPTIM5 128
+#define CK_BUS_TIM2 129
+#define CK_BUS_TIM3 130
+#define CK_BUS_TIM4 131
+#define CK_BUS_TIM5 132
+#define CK_BUS_TIM6 133
+#define CK_BUS_TIM7 134
+#define CK_BUS_TIM10 135
+#define CK_BUS_TIM11 136
+#define CK_BUS_TIM12 137
+#define CK_BUS_TIM13 138
+#define CK_BUS_TIM14 139
+#define CK_BUS_LPTIM1 140
+#define CK_BUS_LPTIM2 141
+#define CK_BUS_SPI2 142
+#define CK_BUS_SPI3 143
+#define CK_BUS_SPDIFRX 144
+#define CK_BUS_USART2 145
+#define CK_BUS_USART3 146
+#define CK_BUS_UART4 147
+#define CK_BUS_UART5 148
+#define CK_BUS_I2C1 149
+#define CK_BUS_I2C2 150
+#define CK_BUS_I2C3 151
+#define CK_BUS_I3C1 152
+#define CK_BUS_I3C2 153
+#define CK_BUS_I3C3 154
+#define CK_BUS_TIM1 155
+#define CK_BUS_TIM8 156
+#define CK_BUS_TIM15 157
+#define CK_BUS_TIM16 158
+#define CK_BUS_TIM17 159
+#define CK_BUS_SAI1 160
+#define CK_BUS_SAI2 161
+#define CK_BUS_SAI3 162
+#define CK_BUS_SAI4 163
+#define CK_BUS_USART1 164
+#define CK_BUS_USART6 165
+#define CK_BUS_UART7 166
+#define CK_BUS_FDCAN 167
+#define CK_BUS_SPI1 168
+#define CK_BUS_SPI4 169
+#define CK_BUS_SPI5 170
+#define CK_BUS_SPI6 171
+#define CK_BUS_BSEC 172
+#define CK_BUS_IWDG1 173
+#define CK_BUS_IWDG2 174
+#define CK_BUS_IWDG3 175
+#define CK_BUS_IWDG4 176
+#define CK_BUS_WWDG1 177
+#define CK_BUS_VREF 178
+#define CK_BUS_DTS 179
+#define CK_BUS_SERC 180
+#define CK_BUS_HDP 181
+#define CK_BUS_DDRPERFM 182
+#define CK_BUS_OTG 183
+#define CK_BUS_LTDC 184
+#define CK_BUS_CSI 185
+#define CK_BUS_DCMIPP 186
+#define CK_BUS_DDRC 187
+#define CK_BUS_DDRCFG 188
+#define CK_BUS_STGEN 189
+#define CK_SYSDBG 190
+#define CK_KER_TIM2 191
+#define CK_KER_TIM3 192
+#define CK_KER_TIM4 193
+#define CK_KER_TIM5 194
+#define CK_KER_TIM6 195
+#define CK_KER_TIM7 196
+#define CK_KER_TIM10 197
+#define CK_KER_TIM11 198
+#define CK_KER_TIM12 199
+#define CK_KER_TIM13 200
+#define CK_KER_TIM14 201
+#define CK_KER_TIM1 202
+#define CK_KER_TIM8 203
+#define CK_KER_TIM15 204
+#define CK_KER_TIM16 205
+#define CK_KER_TIM17 206
+#define CK_BUS_SYSRAM 207
+#define CK_BUS_RETRAM 208
+#define CK_BUS_OSPI1 209
+#define CK_BUS_OTFD1 210
+#define CK_BUS_SRAM1 211
+#define CK_BUS_SDMMC1 212
+#define CK_BUS_SDMMC2 213
+#define CK_BUS_SDMMC3 214
+#define CK_BUS_DDR 215
+#define CK_BUS_RISAF4 216
+#define CK_BUS_USBHOHCI 217
+#define CK_BUS_USBHEHCI 218
+#define CK_KER_LPTIM1 219
+#define CK_KER_LPTIM2 220
+#define CK_KER_USART2 221
+#define CK_KER_UART4 222
+#define CK_KER_USART3 223
+#define CK_KER_UART5 224
+#define CK_KER_SPI2 225
+#define CK_KER_SPI3 226
+#define CK_KER_SPDIFRX 227
+#define CK_KER_I2C1 228
+#define CK_KER_I2C2 229
+#define CK_KER_I3C1 230
+#define CK_KER_I3C2 231
+#define CK_KER_I2C3 232
+#define CK_KER_I3C3 233
+#define CK_KER_SPI1 234
+#define CK_KER_SPI4 235
+#define CK_KER_SPI5 236
+#define CK_KER_SPI6 237
+#define CK_KER_USART1 238
+#define CK_KER_USART6 239
+#define CK_KER_UART7 240
+#define CK_KER_MDF1 241
+#define CK_KER_SAI1 242
+#define CK_KER_SAI2 243
+#define CK_KER_SAI3 244
+#define CK_KER_SAI4 245
+#define CK_KER_FDCAN 246
+#define CK_KER_CSI 247
+#define CK_KER_CSITXESC 248
+#define CK_KER_CSIPHY 249
+#define CK_KER_STGEN 250
+#define CK_KER_USB2PHY2EN 251
+#define CK_KER_LPUART1 252
+#define CK_KER_LPTIM3 253
+#define CK_KER_LPTIM4 254
+#define CK_KER_LPTIM5 255
+#define CK_KER_TSDBG 256
+#define CK_KER_TPIU 257
+#define CK_BUS_ETR 258
+#define CK_BUS_SYSATB 259
+#define CK_KER_ADC1 260
+#define CK_KER_ADC2 261
+#define CK_KER_OSPI1 262
+#define CK_KER_FMC 263
+#define CK_KER_SDMMC1 264
+#define CK_KER_SDMMC2 265
+#define CK_KER_SDMMC3 266
+#define CK_KER_ETH1 267
+#define CK_KER_ETH2 268
+#define CK_KER_ETH1PTP 269
+#define CK_KER_ETH2PTP 270
+#define CK_KER_USB2PHY1 271
+#define CK_KER_USB2PHY2 272
+#define CK_MCO1 273
+#define CK_MCO2 274
+#define CK_KER_DTS 275
+#define CK_ETH1_RX 276
+#define CK_ETH1_TX 277
+#define CK_ETH1_MAC 278
+#define CK_ETH2_RX 279
+#define CK_ETH2_TX 280
+#define CK_ETH2_MAC 281
+#define CK_ETH1_STP 282
+#define CK_ETH2_STP 283
+#define CK_KER_LTDC 284
+#define HSE_DIV2_CK 285
+#define CK_DBGMCU 286
+#define CK_DAP 287
+#define CK_KER_ETR 288
+#define CK_KER_STM 289
+
+#define STM32MP21_LAST_CLK 290
+
+#define CK_SCMI_ICN_HS_MCU 0
+#define CK_SCMI_ICN_SDMMC 1
+#define CK_SCMI_ICN_DDR 2
+#define CK_SCMI_ICN_DISPLAY 3
+#define CK_SCMI_ICN_HSL 4
+#define CK_SCMI_ICN_NIC 5
+#define CK_SCMI_ICN_VID 6
+#define CK_SCMI_FLEXGEN_07 7
+#define CK_SCMI_FLEXGEN_08 8
+#define CK_SCMI_FLEXGEN_09 9
+#define CK_SCMI_FLEXGEN_10 10
+#define CK_SCMI_FLEXGEN_11 11
+#define CK_SCMI_FLEXGEN_12 12
+#define CK_SCMI_FLEXGEN_13 13
+#define CK_SCMI_FLEXGEN_14 14
+#define CK_SCMI_FLEXGEN_15 15
+#define CK_SCMI_FLEXGEN_16 16
+#define CK_SCMI_FLEXGEN_17 17
+#define CK_SCMI_FLEXGEN_18 18
+#define CK_SCMI_FLEXGEN_19 19
+#define CK_SCMI_FLEXGEN_20 20
+#define CK_SCMI_FLEXGEN_21 21
+#define CK_SCMI_FLEXGEN_22 22
+#define CK_SCMI_FLEXGEN_23 23
+#define CK_SCMI_FLEXGEN_24 24
+#define CK_SCMI_FLEXGEN_25 25
+#define CK_SCMI_FLEXGEN_26 26
+#define CK_SCMI_FLEXGEN_27 27
+#define CK_SCMI_FLEXGEN_28 28
+#define CK_SCMI_FLEXGEN_29 29
+#define CK_SCMI_FLEXGEN_30 30
+#define CK_SCMI_FLEXGEN_31 31
+#define CK_SCMI_FLEXGEN_32 32
+#define CK_SCMI_FLEXGEN_33 33
+#define CK_SCMI_FLEXGEN_34 34
+#define CK_SCMI_FLEXGEN_35 35
+#define CK_SCMI_FLEXGEN_36 36
+#define CK_SCMI_FLEXGEN_37 37
+#define CK_SCMI_FLEXGEN_38 38
+#define CK_SCMI_FLEXGEN_39 39
+#define CK_SCMI_FLEXGEN_40 40
+#define CK_SCMI_FLEXGEN_41 41
+#define CK_SCMI_FLEXGEN_42 42
+#define CK_SCMI_FLEXGEN_43 43
+#define CK_SCMI_FLEXGEN_44 44
+#define CK_SCMI_FLEXGEN_45 45
+#define CK_SCMI_FLEXGEN_46 46
+#define CK_SCMI_FLEXGEN_47 47
+#define CK_SCMI_FLEXGEN_48 48
+#define CK_SCMI_FLEXGEN_49 49
+#define CK_SCMI_FLEXGEN_50 50
+#define CK_SCMI_FLEXGEN_51 51
+#define CK_SCMI_FLEXGEN_52 52
+#define CK_SCMI_FLEXGEN_53 53
+#define CK_SCMI_FLEXGEN_54 54
+#define CK_SCMI_FLEXGEN_55 55
+#define CK_SCMI_FLEXGEN_56 56
+#define CK_SCMI_FLEXGEN_57 57
+#define CK_SCMI_FLEXGEN_58 58
+#define CK_SCMI_FLEXGEN_59 59
+#define CK_SCMI_FLEXGEN_60 60
+#define CK_SCMI_FLEXGEN_61 61
+#define CK_SCMI_FLEXGEN_62 62
+#define CK_SCMI_FLEXGEN_63 63
+#define CK_SCMI_ICN_LS_MCU 64
+#define CK_SCMI_HSE 65
+#define CK_SCMI_LSE 66
+#define CK_SCMI_HSI 67
+#define CK_SCMI_LSI 68
+#define CK_SCMI_MSI 69
+#define CK_SCMI_HSE_DIV2 70
+#define CK_SCMI_CPU1 71
+#define CK_SCMI_SYSCPU1 72
+#define CK_SCMI_PLL2 73
+#define CK_SCMI_RTC 74
+#define CK_SCMI_RTCCK 75
+#define CK_SCMI_ICN_APB1 76
+#define CK_SCMI_ICN_APB2 77
+#define CK_SCMI_ICN_APB3 78
+#define CK_SCMI_ICN_APB4 79
+#define CK_SCMI_ICN_APB5 80
+#define CK_SCMI_ICN_APBDBG 81
+#define CK_SCMI_TIMG1 82
+#define CK_SCMI_TIMG2 83
+#define CK_SCMI_BKPSRAM 84
+#define CK_SCMI_BSEC 85
+#define CK_SCMI_BUS_ETR 86
+#define CK_SCMI_FMC 87
+#define CK_SCMI_GPIOA 88
+#define CK_SCMI_GPIOB 89
+#define CK_SCMI_GPIOC 90
+#define CK_SCMI_GPIOD 91
+#define CK_SCMI_GPIOE 92
+#define CK_SCMI_GPIOF 93
+#define CK_SCMI_GPIOG 94
+#define CK_SCMI_GPIOH 95
+#define CK_SCMI_GPIOI 96
+#define CK_SCMI_GPIOZ 97
+#define CK_SCMI_HPDMA1 98
+#define CK_SCMI_HPDMA2 99
+#define CK_SCMI_HPDMA3 100
+#define CK_SCMI_IPCC1 101
+#define CK_SCMI_RETRAM 102
+#define CK_SCMI_SRAM1 103
+#define CK_SCMI_SYSRAM 104
+#define CK_SCMI_OSPI1 105
+#define CK_SCMI_TPIU 106
+#define CK_SCMI_SYSDBG 107
+#define CK_SCMI_SYSATB 108
+#define CK_SCMI_TSDBG 109
+#define CK_SCMI_BUS_STM 110
+#define CK_SCMI_KER_STM 111
+#define CK_SCMI_KER_ETR 112
+
+#endif /* _DT_BINDINGS_STM32MP21_CLKS_H_ */
diff --git a/include/dt-bindings/clock/stm32mp21-clksrc.h b/include/dt-bindings/clock/stm32mp21-clksrc.h
new file mode 100644
index 0000000..560ca0a
--- /dev/null
+++ b/include/dt-bindings/clock/stm32mp21-clksrc.h
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (C) 2025, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_STM32MP21_CLKSRC_H_
+#define _DT_BINDINGS_CLOCK_STM32MP21_CLKSRC_H_
+
+#define CMD_DIV 0
+#define CMD_MUX 1
+#define CMD_CLK 2
+#define CMD_FLEXGEN 3
+
+#define CMD_ADDR_BIT 0x80000000
+
+#define CMD_SHIFT 26
+#define CMD_MASK 0xFC000000
+#define CMD_DATA_MASK 0x03FFFFFF
+
+#define DIV_ID_SHIFT 8
+#define DIV_ID_MASK 0x0000FF00
+
+#define DIV_DIVN_SHIFT 0
+#define DIV_DIVN_MASK 0x000000FF
+
+#define MUX_ID_SHIFT 4
+#define MUX_ID_MASK 0x00000FF0
+
+#define MUX_SEL_SHIFT 0
+#define MUX_SEL_MASK 0x0000000F
+
+/* CLK define */
+#define CLK_ON_MASK BIT(21)
+#define CLK_ON_SHIFT 21
+
+#define CLK_ID_MASK GENMASK_32(20, 12)
+#define CLK_ID_SHIFT 12
+
+#define CLK_NO_DIV_MASK 0x0000080
+#define CLK_DIV_MASK GENMASK_32(10, 5)
+#define CLK_DIV_SHIFT 5
+
+#define CLK_NO_SEL_MASK 0x00000010
+#define CLK_SEL_MASK GENMASK_32(3, 0)
+#define CLK_SEL_SHIFT 0
+
+#define CLK_CFG(clk_id, sel, div, state) ((CMD_CLK << CMD_SHIFT) |\
+ ((state) << CLK_ON_SHIFT) |\
+ ((clk_id) << CLK_ID_SHIFT) |\
+ ((div) << CLK_DIV_SHIFT) |\
+ ((sel) << CLK_SEL_SHIFT))
+
+#define CLK_OFF 0
+#define CLK_ON 1
+#define CLK_NODIV 0x00000040
+#define CLK_NOMUX 0x00000010
+
+/* Flexgen define */
+#define FLEX_ID_SHIFT 20
+#define FLEX_SEL_SHIFT 16
+#define FLEX_PDIV_SHIFT 6
+#define FLEX_FDIV_SHIFT 0
+
+#define FLEX_ID_MASK GENMASK_32(25, 20)
+#define FLEX_SEL_MASK GENMASK_32(19, 16)
+#define FLEX_PDIV_MASK GENMASK_32(15, 6)
+#define FLEX_FDIV_MASK GENMASK_32(5, 0)
+
+#define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\
+ ((div_id) << DIV_ID_SHIFT |\
+ (div)))
+
+#define MUX_CFG(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\
+ ((mux_id) << MUX_ID_SHIFT |\
+ (sel)))
+
+#define CLK_ADDR_SHIFT 16
+#define CLK_ADDR_MASK 0x7FFF0000
+#define CLK_ADDR_VAL_MASK 0xFFFF
+
+#define DIV_LSMCU 0
+#define DIV_APB1 1
+#define DIV_APB2 2
+#define DIV_APB3 3
+#define DIV_APB4 4
+#define DIV_APB5 5
+#define DIV_APBDBG 6
+#define DIV_RTC 7
+#define DIV_NB 8
+
+#define MUX_MUXSEL0 0
+#define MUX_MUXSEL1 1
+#define MUX_MUXSEL2 2
+#define MUX_MUXSEL3 3
+#define MUX_MUXSEL4 4
+#define MUX_MUXSEL5 5
+#define MUX_MUXSEL6 6
+#define MUX_MUXSEL7 7
+#define MUX_XBARSEL 8
+#define MUX_RTC 9
+#define MUX_MCO1 10
+#define MUX_MCO2 11
+#define MUX_ADC1 12
+#define MUX_ADC2 13
+#define MUX_USB2PHY1 14
+#define MUX_USB2PHY2 15
+#define MUX_DTS 16
+#define MUX_CPU1 17
+#define MUX_NB 18
+
+#define MUXSEL_HSI 0
+#define MUXSEL_HSE 1
+#define MUXSEL_MSI 2
+
+/* KERNEL source clocks */
+#define MUX_RTC_DISABLED 0x0
+#define MUX_RTC_LSE 0x1
+#define MUX_RTC_LSI 0x2
+#define MUX_RTC_HSE 0x3
+
+#define MUX_MCO1_FLEX61 0x0
+#define MUX_MCO1_OBSER0 0x1
+
+#define MUX_MCO2_FLEX62 0x0
+#define MUX_MCO2_OBSER1 0x1
+
+#define MUX_ADC1_FLEX46 0x0
+#define MUX_ADC1_LSMCU 0x1
+
+#define MUX_ADC2_FLEX47 0x0
+#define MUX_ADC2_LSMCU 0x1
+#define MUX_ADC2_FLEX46 0x2
+
+#define MUX_USB2PHY1_FLEX57 0x0
+#define MUX_USB2PHY1_HSE 0x1
+
+#define MUX_USB2PHY2_FLEX58 0x0
+#define MUX_USB2PHY2_HSE 0x1
+
+#define MUX_DTS_HSI 0x0
+#define MUX_DTS_HSE 0x1
+#define MUX_DTS_MSI 0x2
+
+/* PLLs source clocks */
+#define PLL_SRC_HSI 0x0
+#define PLL_SRC_HSE 0x1
+#define PLL_SRC_MSI 0x2
+#define PLL_SRC_DISABLED 0x3
+
+/* XBAR source clocks */
+#define XBAR_SRC_PLL4 0x0
+#define XBAR_SRC_PLL5 0x1
+#define XBAR_SRC_PLL6 0x2
+#define XBAR_SRC_PLL7 0x3
+#define XBAR_SRC_PLL8 0x4
+#define XBAR_SRC_HSI 0x5
+#define XBAR_SRC_HSE 0x6
+#define XBAR_SRC_MSI 0x7
+#define XBAR_SRC_HSI_KER 0x8
+#define XBAR_SRC_HSE_KER 0x9
+#define XBAR_SRC_MSI_KER 0xA
+#define XBAR_SRC_SPDIF_SYMB 0xB
+#define XBAR_SRC_I2S 0xC
+#define XBAR_SRC_LSI 0xD
+#define XBAR_SRC_LSE 0xE
+
+/*
+ * Configure a XBAR channel with its clock source
+ * channel_nb: XBAR channel number from 0 to 63
+ * channel_src: one of the 15 previous XBAR source clocks defines
+ * channel_prediv: value of the PREDIV in channel RCC_PREDIVxCFGR register
+ * can be either 1, 2, 4 or 1024
+ * channel_findiv: value of the FINDIV in channel RCC_FINDIVxCFGR register
+ * from 1 to 64
+ */
+
+#define FLEXGEN_CFG(ch, sel, pdiv, fdiv) ((CMD_FLEXGEN << CMD_SHIFT) |\
+ ((ch) << FLEX_ID_SHIFT) |\
+ ((sel) << FLEX_SEL_SHIFT) |\
+ ((pdiv) << FLEX_PDIV_SHIFT) |\
+ ((fdiv) << FLEX_FDIV_SHIFT))
+
+/* Register addresses of MCO1 & MCO2 */
+#define MCO1 0x488
+#define MCO2 0x48C
+
+#define MCO_OFF 0
+#define MCO_ON 1
+#define MCO_STATUS_SHIFT 8
+
+#define MCO_CFG(addr, sel, status) (CMD_ADDR_BIT |\
+ ((addr) << CLK_ADDR_SHIFT) |\
+ ((status) << MCO_STATUS_SHIFT) |\
+ (sel))
+
+/* define for st,pll /csg */
+#define SSCG_MODE_CENTER_SPREAD 0
+#define SSCG_MODE_DOWN_SPREAD 1
+
+/* define for st,drive */
+#define LSEDRV_LOWEST 0
+#define LSEDRV_MEDIUM_LOW 2
+#define LSEDRV_MEDIUM_HIGH 1
+#define LSEDRV_HIGHEST 3
+
+#endif /* _DT_BINDINGS_CLOCK_STM32MP21_CLKSRC_H_ */
diff --git a/include/dt-bindings/reset/st,stm32mp21-rcc.h b/include/dt-bindings/reset/st,stm32mp21-rcc.h
new file mode 100644
index 0000000..377a170
--- /dev/null
+++ b/include/dt-bindings/reset/st,stm32mp21-rcc.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
+ * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com>
+ */
+
+#ifndef _DT_BINDINGS_STM32MP21_RESET_H_
+#define _DT_BINDINGS_STM32MP21_RESET_H_
+
+/* TF-A use a binding required by driver, not aligned with Linux*/
+
+#define SYS_R 8192
+#define C1_R 8224
+#define C2_R 8288
+#define C2_HOLDBOOT_R 8608
+#define C1_HOLDBOOT_R 8609
+#define VSW_R 8672
+#define C1MS_R 8840
+#define IWDG2_KER_R 9106
+#define IWDG4_KER_R 9234
+#define DDRCP_R 9888
+#define DDRCAPB_R 9920
+#define DDRPHYCAPB_R 9952
+#define DDRCFG_R 10016
+#define DDR_R 10048
+#define OSPI1_R 10400
+#define OSPI1DLL_R 10416
+#define FMC_R 10464
+#define DBG_R 10508
+#define GPIOA_R 10592
+#define GPIOB_R 10624
+#define GPIOC_R 10656
+#define GPIOD_R 10688
+#define GPIOE_R 10720
+#define GPIOF_R 10752
+#define GPIOG_R 10784
+#define GPIOH_R 10816
+#define GPIOI_R 10848
+#define GPIOZ_R 10944
+#define HPDMA1_R 10976
+#define HPDMA2_R 11008
+#define HPDMA3_R 11040
+#define IPCC1_R 11136
+#define SSMOD_R 11392
+#define TIM1_R 14336
+#define TIM2_R 14368
+#define TIM3_R 14400
+#define TIM4_R 14432
+#define TIM5_R 14464
+#define TIM6_R 14496
+#define TIM7_R 14528
+#define TIM8_R 14560
+#define TIM10_R 14592
+#define TIM11_R 14624
+#define TIM12_R 14656
+#define TIM13_R 14688
+#define TIM14_R 14720
+#define TIM15_R 14752
+#define TIM16_R 14784
+#define TIM17_R 14816
+#define LPTIM1_R 14880
+#define LPTIM2_R 14912
+#define LPTIM3_R 14944
+#define LPTIM4_R 14976
+#define LPTIM5_R 15008
+#define SPI1_R 15040
+#define SPI2_R 15072
+#define SPI3_R 15104
+#define SPI4_R 15136
+#define SPI5_R 15168
+#define SPI6_R 15200
+#define SPDIFRX_R 15296
+#define USART1_R 15328
+#define USART2_R 15360
+#define USART3_R 15392
+#define UART4_R 15424
+#define UART5_R 15456
+#define USART6_R 15488
+#define UART7_R 15520
+#define LPUART1_R 15616
+#define I2C1_R 15648
+#define I2C2_R 15680
+#define I2C3_R 15712
+#define SAI1_R 15904
+#define SAI2_R 15936
+#define SAI3_R 15968
+#define SAI4_R 16000
+#define MDF1_R 16064
+#define ADF1_R 16096
+#define FDCAN_R 16128
+#define HDP_R 16160
+#define ADC1_R 16192
+#define ADC2_R 16224
+#define ETH1_R 16256
+#define ETH2_R 16288
+#define USBH_R 16352
+#define USB2PHY1_R 16384
+#define OTG_R 16448
+#define USB2PHY2_R 16480
+#define SDMMC1_R 16768
+#define SDMMC1DLL_R 16784
+#define SDMMC2_R 16800
+#define SDMMC2DLL_R 16816
+#define SDMMC3_R 16832
+#define SDMMC3DLL_R 16848
+#define LTDC_R 16896
+#define CSI_R 17088
+#define DCMIPP_R 17120
+#define DCMIPSSI_R 17152
+#define RNG1_R 17280
+#define RNG2_R 17312
+#define PKA_R 17344
+#define SAES_R 17376
+#define HASH1_R 17408
+#define HASH2_R 17440
+#define CRYP1_R 17472
+#define CRYP2_R 17504
+#define WWDG1_R 17696
+#define VREF_R 17760
+#define DTS_R 17792
+#define CRC_R 17824
+#define SERC_R 17856
+#define I3C1_R 17984
+#define I3C2_R 18016
+#define I3C3_R 18048
+
+#define RST_SCMI_C1_R 0
+#define RST_SCMI_C2_R 1
+#define RST_SCMI_C1_HOLDBOOT_R 2
+#define RST_SCMI_C2_HOLDBOOT_R 3
+#define RST_SCMI_FMC 4
+#define RST_SCMI_OSPI1 5
+#define RST_SCMI_OSPI1DLL 6
+
+#endif /* _DT_BINDINGS_STM32MP21_RESET_H_ */
diff --git a/include/lib/cpus/aarch64/dsu_def.h b/include/lib/cpus/aarch64/dsu_def.h
index 78b3e7f..3f6dbfe 100644
--- a/include/lib/cpus/aarch64/dsu_def.h
+++ b/include/lib/cpus/aarch64/dsu_def.h
@@ -26,14 +26,18 @@
#define CLUSTERIDR_VAR_SHIFT U(4)
#define CLUSTERIDR_VAR_BITS U(4)
+#define CLUSTERREVIDR_EL1 S3_0_C15_C3_2
+
/********************************************************************
* DSU Cluster Auxiliary Control registers definitions
********************************************************************/
#define CLUSTERACTLR_EL1 S3_0_C15_C3_3
#define CLUSTERPWRCTLR_EL1 S3_0_C15_C3_5
-#define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15)
-#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15)
+#define CLUSTERACTLR_EL1_ASSERT_CBUSY (ULL(1) << 8)
+#define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15)
+#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15)
+#define CLUSTERACTLR_EL1_IGNORE_INTERCONNECT_CBUSY (ULL(3) << 20)
/********************************************************************
* Masks applied for DSU errata workarounds
diff --git a/include/lib/cpus/aarch64/dsu_macros.S b/include/lib/cpus/aarch64/dsu_macros.S
index 6c8cb69..fd23f66 100644
--- a/include/lib/cpus/aarch64/dsu_macros.S
+++ b/include/lib/cpus/aarch64/dsu_macros.S
@@ -94,4 +94,44 @@
orr x0, x0, #CLUSTERACTLR_EL1_DISABLE_SCLK_GATING
msr CLUSTERACTLR_EL1, x0
.endm
+
+/*
+ * Check if erratum is fixed via CLUSTERREVIDR_EL1 bit (\bitpos).
+ * If not fixed (bit is clear), set x0 = ERRATA_APPLIES (from x3).
+ * If fixed (bit is set), keep x0 = ERRATA_NOT_APPLIES.
+ */
+.macro check_revidr_bit bitpos:req
+ mrs x4, CLUSTERREVIDR_EL1
+ mov x1, #1
+ lsl x1, x1, #\bitpos
+ tst x1, x4
+ csel x0, x0, x3, NE
+.endm
+
+.macro check_errata_dsu_2900952_applies
+ mov x0, #ERRATA_NOT_APPLIES
+ mov x3, #ERRATA_APPLIES
+
+ /* Check if DSU revision is equal to r2p0 */
+ mrs x1, CLUSTERIDR_EL1
+
+ /* DSU variant and revision bitfields in CLUSTERIDR are adjacent */
+ ubfx x2, x1, #CLUSTERIDR_REV_SHIFT,\
+ #(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS)
+ cmp x2, #(0x2 << CLUSTERIDR_VAR_SHIFT)
+ b.ne 1f
+ check_revidr_bit 1
+1:
+.endm
+
+.macro errata_dsu_2900952_wa_apply
+
+ ldr x1, =((CLUSTERACTLR_EL1_IGNORE_INTERCONNECT_CBUSY | \
+ CLUSTERACTLR_EL1_ASSERT_CBUSY))
+
+ mrs x0, CLUSTERACTLR_EL1
+ orr x0, x0, x1
+ msr CLUSTERACTLR_EL1, x0
+.endm
+
#endif /* DSU_MACROS_S */
diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h
index 235e2b9..bb755e0 100644
--- a/include/lib/cpus/errata.h
+++ b/include/lib/cpus/errata.h
@@ -93,8 +93,9 @@
* NOTE an erratum and CVE id could clash. However, both numbers are very large
* and the probablity is minuscule. Working around this makes code very
* complicated and extremely difficult to read so it is not considered. In the
- * unlikely event that this does happen, prepending the CVE id with a 0 should
- * resolve the conflict
+ * unlikely event that this does happen, the build will fail, and unless the
+ * framework is updated to account for this one of the IDs will need to be
+ * altered to prevent the conflict.
*/
#define NO_ISB 1
#define NO_ASSERT 0
diff --git a/include/lib/libc/string_private.h b/include/lib/libc/string_private.h
index da85fae..ab7647a 100644
--- a/include/lib/libc/string_private.h
+++ b/include/lib/libc/string_private.h
@@ -11,6 +11,7 @@
#include <stddef.h>
+void *memcpy(void *dst, const void *src, size_t len);
int memcmp(const void *s1, const void *s2, size_t len);
int strcmp(const char *s1, const char *s2);
int strncmp(const char *s1, const char *s2, size_t n);
diff --git a/include/lib/psci/psci_lib.h b/include/lib/psci/psci_lib.h
index 8c9296b..1e1d5fc 100644
--- a/include/lib/psci/psci_lib.h
+++ b/include/lib/psci/psci_lib.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -98,6 +98,7 @@
void __dead2 psci_pwrdown_cpu_end_terminal(void);
void psci_pwrdown_cpu_end_wakeup(unsigned int power_level);
void psci_do_manage_extensions(void);
+unsigned int psci_num_cpus_running_on_safe(unsigned int this_core);
#endif /* __ASSEMBLER__ */
diff --git a/include/services/drtm_svc.h b/include/services/drtm_svc.h
index 56ae129..8e27b18 100644
--- a/include/services/drtm_svc.h
+++ b/include/services/drtm_svc.h
@@ -102,7 +102,7 @@
#define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK ULL(0xFFFFFFFF)
#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT U(8)
-#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK ULL(0xF)
+#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK ULL(0xFFFF)
#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT U(0)
#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK ULL(0xFF)
diff --git a/lib/cpus/aarch64/cortex_a520.S b/lib/cpus/aarch64/cortex_a520.S
index ac8019e0..5e0b711 100644
--- a/lib/cpus/aarch64/cortex_a520.S
+++ b/lib/cpus/aarch64/cortex_a520.S
@@ -9,6 +9,7 @@
#include <common/bl_common.h>
#include <cortex_a520.h>
#include <cpu_macros.S>
+#include <dsu_macros.S>
#include <plat_macros.S>
.global check_erratum_cortex_a520_2938996
@@ -37,6 +38,15 @@
check_erratum_ls cortex_a520, ERRATUM(2858100), CPU_REV(0, 1)
+workaround_reset_start cortex_a520, ERRATUM(2900952), ERRATA_DSU_2900952
+ errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_a520, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_a520, ERRATUM(2900952)
+ check_errata_dsu_2900952_applies
+ ret
+check_erratum_custom_end cortex_a520, ERRATUM(2900952)
+
add_erratum_entry cortex_a520, ERRATUM(2938996), ERRATA_A520_2938996
check_erratum_ls cortex_a520, ERRATUM(2938996), CPU_REV(0, 1)
diff --git a/lib/cpus/aarch64/cortex_a720.S b/lib/cpus/aarch64/cortex_a720.S
index e639996..0c713c3 100644
--- a/lib/cpus/aarch64/cortex_a720.S
+++ b/lib/cpus/aarch64/cortex_a720.S
@@ -9,6 +9,7 @@
#include <common/bl_common.h>
#include <cortex_a720.h>
#include <cpu_macros.S>
+#include <dsu_macros.S>
#include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S"
@@ -42,6 +43,15 @@
check_erratum_ls cortex_a720, ERRATUM(2844092), CPU_REV(0, 1)
+workaround_reset_start cortex_a720, ERRATUM(2900952), ERRATA_DSU_2900952
+ errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_a720, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_a720, ERRATUM(2900952)
+ check_errata_dsu_2900952_applies
+ ret
+check_erratum_custom_end cortex_a720, ERRATUM(2900952)
+
workaround_reset_start cortex_a720, ERRATUM(2926083), ERRATA_A720_2926083
/* Erratum 2926083 workaround is required only if SPE is enabled */
#if ENABLE_SPE_FOR_NS != 0
diff --git a/lib/cpus/aarch64/cortex_a725.S b/lib/cpus/aarch64/cortex_a725.S
index 682ca45..e940bde 100644
--- a/lib/cpus/aarch64/cortex_a725.S
+++ b/lib/cpus/aarch64/cortex_a725.S
@@ -9,6 +9,7 @@
#include <common/bl_common.h>
#include <cortex_a725.h>
#include <cpu_macros.S>
+#include <dsu_macros.S>
#include <plat_macros.S>
/* Hardware handled coherency */
@@ -25,6 +26,15 @@
.global check_erratum_cortex_a725_3699564
+workaround_reset_start cortex_a725, ERRATUM(2900952), ERRATA_DSU_2900952
+ errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_a725, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_a725, ERRATUM(2900952)
+ check_errata_dsu_2900952_applies
+ ret
+check_erratum_custom_end cortex_a725, ERRATUM(2900952)
+
add_erratum_entry cortex_a725, ERRATUM(3699564), ERRATA_A725_3699564
check_erratum_ls cortex_a725, ERRATUM(3699564), CPU_REV(0, 1)
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index 1d0c377..b1dc52c 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -9,6 +9,7 @@
#include <common/bl_common.h>
#include <cortex_x4.h>
#include <cpu_macros.S>
+#include <dsu_macros.S>
#include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S"
@@ -64,6 +65,15 @@
check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1)
+workaround_reset_start cortex_x4, ERRATUM(2900952), ERRATA_DSU_2900952
+ errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_x4, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_x4, ERRATUM(2900952)
+ check_errata_dsu_2900952_applies
+ ret
+check_erratum_custom_end cortex_x4, ERRATUM(2900952)
+
workaround_reset_start cortex_x4, ERRATUM(2923985), ERRATA_X4_2923985
sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, (BIT(11) | BIT(10))
workaround_reset_end cortex_x4, ERRATUM(2923985)
diff --git a/lib/cpus/aarch64/cortex_x925.S b/lib/cpus/aarch64/cortex_x925.S
index 0663b21..003dc97 100644
--- a/lib/cpus/aarch64/cortex_x925.S
+++ b/lib/cpus/aarch64/cortex_x925.S
@@ -9,6 +9,7 @@
#include <common/bl_common.h>
#include <cortex_x925.h>
#include <cpu_macros.S>
+#include <dsu_macros.S>
#include <plat_macros.S>
/* Hardware handled coherency */
@@ -23,6 +24,15 @@
cpu_reset_prologue cortex_x925
+workaround_reset_start cortex_x925, ERRATUM(2900952), ERRATA_DSU_2900952
+ errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_x925, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_x925, ERRATUM(2900952)
+ check_errata_dsu_2900952_applies
+ ret
+check_erratum_custom_end cortex_x925, ERRATUM(2900952)
+
add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747
check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1)
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 7cf86a2..a0cb872 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -1075,6 +1075,13 @@
# results in higher DSU power consumption on idle.
CPU_FLAG_LIST += ERRATA_DSU_2313941
+# Flag to apply DSU erratum 2900952 during reset. This erratum applies
+# to some implementations of DSU-120 revision r2p0. Erratum might be fixed
+# in some implementations of r2p0. This can be determined by reading
+# the IMP_CLUSTERREVIDR_EL1 register where a set bit indicates that
+# the erratum is fixed in this part. It is fixed in r2p1.
+CPU_FLAG_LIST += ERRATA_DSU_2900952
+
ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0)
ifeq (${WORKAROUND_CVE_2018_3639},0)
$(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1")
diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c
index ab68467..47e8699 100644
--- a/lib/cpus/errata_report.c
+++ b/lib/cpus/errata_report.c
@@ -31,7 +31,7 @@
/* Errata format: BL stage, CPU, errata ID, message */
#define ERRATA_FORMAT "%s: %s: CPU workaround for %s was %s\n"
-#define CVE_FORMAT "%s: %s: CPU workaround for CVE %u_%u was %s\n"
+#define CVE_FORMAT "%s: %s: CPU workaround for CVE %u_%04u was %s\n"
#define ERRATUM_FORMAT "%s: %s: CPU workaround for erratum %u was %s\n"
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index d04e02f..7795fcf 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -191,6 +191,15 @@
scr_el3 |= SCR_SCTLR2En_BIT;
}
+ if (is_feat_d128_supported()) {
+ /*
+ * Set the D128En bit in SCR_EL3 to enable access to 128-bit
+ * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1,
+ * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers.
+ */
+ scr_el3 |= SCR_D128En_BIT;
+ }
+
write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
if (is_feat_fgt2_supported()) {
diff --git a/lib/libc/memcpy.c b/lib/libc/memcpy.c
index ca31de5..e8be154 100644
--- a/lib/libc/memcpy.c
+++ b/lib/libc/memcpy.c
@@ -12,8 +12,9 @@
const char *s = src;
char *d = dst;
- while (len--)
+ while (len--) {
*d++ = *s++;
+ }
return dst;
}
diff --git a/lib/libc/memmove.c b/lib/libc/memmove.c
index 6451e4e..7aee83f 100644
--- a/lib/libc/memmove.c
+++ b/lib/libc/memmove.c
@@ -24,8 +24,9 @@
const char *end = dst;
const char *s = (const char *)src + len;
char *d = (char *)dst + len;
- while (d != end)
+ while (d != end) {
*--d = *--s;
+ }
}
return dst;
}
diff --git a/lib/libc/printf.c b/lib/libc/printf.c
index c9e8a04..65c5238 100644
--- a/lib/libc/printf.c
+++ b/lib/libc/printf.c
@@ -131,8 +131,9 @@
(void)putchar((int32_t)'-');
unum = (unsigned long long int)-num;
padn--;
- } else
+ } else {
unum = (unsigned long long int)num;
+ }
count += unsigned_num_print(unum, 10,
padc, padn, uppercase);
@@ -164,8 +165,9 @@
padc, padn, uppercase);
break;
case 'z':
- if (sizeof(size_t) == 8U)
+ if (sizeof(size_t) == 8U) {
l_count = 2;
+ }
fmt++;
goto loop;
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 1c634e3..1021ef6 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -215,7 +215,7 @@
******************************************************************************/
bool psci_is_last_on_cpu(unsigned int my_idx)
{
- for (unsigned int cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) {
+ for (unsigned int cpu_idx = 0U; cpu_idx < psci_plat_core_count; cpu_idx++) {
if (cpu_idx == my_idx) {
assert(psci_get_aff_info_state() == AFF_STATE_ON);
continue;
@@ -239,7 +239,7 @@
{
unsigned int cpu_idx;
- for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) {
+ for (cpu_idx = 0U; cpu_idx < psci_plat_core_count; cpu_idx++) {
if (psci_get_aff_info_state_by_idx(cpu_idx) == AFF_STATE_OFF) {
return false;
}
@@ -249,6 +249,33 @@
}
/*******************************************************************************
+ * Counts the number of CPUs in the system that are currently in the ON or
+ * ON_PENDING state.
+ *
+ * @note This function does not acquire any power domain locks. It must only be
+ * called in contexts where it is guaranteed that PSCI state transitions
+ * are not concurrently happening, or where locks are already held.
+ *
+ * @return The number of CPUs currently in AFF_STATE_ON or AFF_STATE_ON_PENDING.
+ ******************************************************************************/
+static unsigned int psci_num_cpus_running(void)
+{
+ unsigned int cpu_idx;
+ unsigned int no_of_cpus = 0U;
+ aff_info_state_t aff_state;
+
+ for (cpu_idx = 0U; cpu_idx < psci_plat_core_count; cpu_idx++) {
+ aff_state = psci_get_aff_info_state_by_idx(cpu_idx);
+ if (aff_state == AFF_STATE_ON ||
+ aff_state == AFF_STATE_ON_PENDING) {
+ no_of_cpus++;
+ }
+ }
+
+ return no_of_cpus;
+}
+
+/*******************************************************************************
* Routine to return the maximum power level to traverse to after a cpu has
* been physically powered up. It is expected to be called immediately after
* reset from assembler code.
@@ -1371,3 +1398,30 @@
return true;
}
+
+/*******************************************************************************
+ * Safely counts the number of CPUs in the system that are currently in the ON
+ * or ON_PENDING state.
+ *
+ * This function acquires and releases the necessary power domain locks to
+ * ensure consistency of the CPU state information.
+ *
+ * @param this_core The index of the current core making the query.
+ *
+ * @return The number of CPUs currently in AFF_STATE_ON or AFF_STATE_ON_PENDING.
+ ******************************************************************************/
+unsigned int psci_num_cpus_running_on_safe(unsigned int this_core)
+{
+ unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
+ unsigned int no_of_cpus;
+
+ psci_get_parent_pwr_domain_nodes(this_core, PLAT_MAX_PWR_LVL, parent_nodes);
+
+ psci_acquire_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes);
+
+ no_of_cpus = psci_num_cpus_running();
+
+ psci_release_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes);
+
+ return no_of_cpus;
+}
diff --git a/make_helpers/arch_features.mk b/make_helpers/arch_features.mk
index 1561a59..a6fd6be 100644
--- a/make_helpers/arch_features.mk
+++ b/make_helpers/arch_features.mk
@@ -58,11 +58,6 @@
armv8-5-a-feats += ${armv8-4-a-feats}
FEAT_LIST := ${armv8-5-a-feats}
-# Enable Memory tagging, Branch Target Identification for aarch64 only.
-ifeq ($(ARCH), aarch64)
- mem_tag_arch_support ?= yes
-endif #(ARCH=aarch64)
-
endif
# Enable the features which are mandatory from ARCH version 8.6 and upwards.
@@ -433,6 +428,9 @@
# Flag to enable access to Arm v9.3 FEAT_D128 extension
ENABLE_FEAT_D128 ?= 0
+# Flag to enable access to GICv5 CPU interface extension (FEAT_GCIE)
+ENABLE_FEAT_GCIE ?= 0
+
#----
#9.4
#----
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index f438a9d..4ccca9f 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -346,11 +346,6 @@
# CTX_INCLUDE_EL2_REGS.
CTX_INCLUDE_EL2_REGS := 0
-# Enable Memory tag extension which is supported for architecture greater
-# than Armv8.5-A
-# By default it is set to "no"
-SUPPORT_STACK_MEMTAG := no
-
# Select workaround for AT speculative behaviour.
ERRATA_SPECULATIVE_AT := 0
diff --git a/plat/allwinner/sun50i_h616/sunxi_power.c b/plat/allwinner/sun50i_h616/sunxi_power.c
index cab7e46..b47149f 100644
--- a/plat/allwinner/sun50i_h616/sunxi_power.c
+++ b/plat/allwinner/sun50i_h616/sunxi_power.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited. All rights reserved.
* Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -49,7 +49,7 @@
int axp_read(uint8_t reg)
{
- uint8_t val;
+ uint8_t val = 0;
int ret;
if (is_using_rsb()) {
diff --git a/plat/amd/versal2/aarch64/common.c b/plat/amd/versal2/aarch64/common.c
index 8d9e05c..9e52f9d 100644
--- a/plat/amd/versal2/aarch64/common.c
+++ b/plat/amd/versal2/aarch64/common.c
@@ -8,12 +8,12 @@
#include <common/debug.h>
#include <common/runtime_svc.h>
+#include <def.h>
#include <drivers/generic_delay_timer.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
-
-#include <def.h>
+#include <plat_clkfunc.h>
#include <plat_common.h>
#include <plat_ipi.h>
#include <plat_private.h>
@@ -123,7 +123,7 @@
uintptr_t crl_base, iou_scntrs_base, psx_base;
crl_base = CRL;
- iou_scntrs_base = IOU_SCNTRS;
+ iou_scntrs_base = IOU_SCNTRS_BASE;
psx_base = PSX_CRF;
/* Reset for system timestamp generator in FPX */
@@ -143,13 +143,11 @@
mmio_write_32(iou_scntrs_base + IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET,
IOU_SCNTRS_CONTROL_EN);
+ /* set cntfrq_el0 value so that software can discover the frequency of the system counter */
+ set_cnt_freq();
+
generic_delay_timer_init();
/* Configure IPI data */
soc_ipi_config_table_init();
}
-
-uint32_t plat_get_syscnt_freq2(void)
-{
- return cpu_clock;
-}
diff --git a/plat/amd/versal2/include/def.h b/plat/amd/versal2/include/def.h
index 9bef9d0..3b42b15 100644
--- a/plat/amd/versal2/include/def.h
+++ b/plat/amd/versal2/include/def.h
@@ -126,8 +126,14 @@
#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U)
-/* IOU SCNTRS */
-#define IOU_SCNTRS U(0xEC920000)
+#define FPD_SYSTMR_CTRL_BASE U(0xEC920000)
+
+/*
+ * Note: There is no IOU_SCNTRS in Versal Gen 2, the equivalent
+ * functionality is provided through FPD_SYSTMR_CTRL. For compatibility
+ * with existing code, maintain the same macro names.
+ */
+#define IOU_SCNTRS_BASE FPD_SYSTMR_CTRL_BASE
#define IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0)
#define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20)
diff --git a/plat/amd/versal2/platform.mk b/plat/amd/versal2/platform.mk
index 283ad42..475e8ff 100644
--- a/plat/amd/versal2/platform.mk
+++ b/plat/amd/versal2/platform.mk
@@ -116,6 +116,7 @@
drivers/delay_timer/generic_delay_timer.c \
${GICV3_SOURCES} \
drivers/arm/pl011/aarch64/pl011_console.S \
+ plat/xilinx/common/plat_clkfunc.c \
plat/common/aarch64/crash_console_helpers.S \
plat/arm/common/arm_common.c \
plat/common/plat_gicv3.c \
diff --git a/plat/amd/versal2/pm_service/pm_client.c b/plat/amd/versal2/pm_service/pm_client.c
index 8d6b9b1..67099a6 100644
--- a/plat/amd/versal2/pm_service/pm_client.c
+++ b/plat/amd/versal2/pm_service/pm_client.c
@@ -336,6 +336,23 @@
uintptr_t val;
if (cpuid != (uint32_t) UNDEFINED_CPUID) {
+ /*
+ * Get the core index and use it to calculate offset for
+ * disabling power down and wakeup interrupts.
+ * i.e., Convert cpu-id to core_index with the following mapping:
+ * cpu-id -> core_index
+ * 0 -> 0
+ * 1 -> 1
+ * 2 -> 4
+ * 3 -> 5
+ * 4 -> 8
+ * 5 -> 9
+ * 6 -> 12
+ * 7 -> 13
+ * to match with register database.
+ */
+ uint32_t core_index = cpuid + ((cpuid / 2U) * 2U);
+
pm_client_lock_get();
/* Clear powerdown request */
@@ -346,10 +363,10 @@
isb();
/* Disabled power down interrupt */
- mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(cpuid),
+ mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(core_index),
APU_PCIL_CORE_X_IDS_POWER_MASK);
/* Disable wake interrupt */
- mmio_write_32(APU_PCIL_CORE_X_IDS_WAKE_REG(cpuid),
+ mmio_write_32(APU_PCIL_CORE_X_IDS_WAKE_REG(core_index),
APU_PCIL_CORE_X_IDS_WAKE_MASK);
pm_client_lock_release();
diff --git a/plat/amd/versal2/pm_service/pm_svc_main.c b/plat/amd/versal2/pm_service/pm_svc_main.c
index 10d2ed2..55fd963 100644
--- a/plat/amd/versal2/pm_service/pm_svc_main.c
+++ b/plat/amd/versal2/pm_service/pm_svc_main.c
@@ -163,7 +163,8 @@
break;
case PM_NOTIFY_CB:
if (sgi != INVALID_SGI) {
- if (payload[2] == EVENT_CPU_PWRDWN) {
+ if ((payload[2] == EVENT_CPU_PWRDWN) &&
+ (NODECLASS(payload[1]) == (uint32_t)XPM_NODECLASS_DEVICE)) {
if (pwrdwn_req_received) {
pwrdwn_req_received = false;
request_cpu_pwrdwn();
@@ -182,7 +183,8 @@
*/
}
notify_os();
- } else if (payload[2] == EVENT_CPU_PWRDWN) {
+ } else if ((payload[2] == EVENT_CPU_PWRDWN) &&
+ (NODECLASS(payload[1]) == (uint32_t)XPM_NODECLASS_DEVICE)) {
request_cpu_pwrdwn();
(void)psci_cpu_off();
} else {
diff --git a/plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c b/plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c
new file mode 100644
index 0000000..7cb88ed
--- /dev/null
+++ b/plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <common/fdt_wrappers.h>
+#include <drivers/arm/gicv3.h>
+
+#include <fconf_hw_config_getter.h>
+
+struct gicv3_config_t gicv3_config;
+
+int fconf_populate_gicv3_config(uintptr_t config)
+{
+ int err;
+ int node;
+ uintptr_t addr;
+
+ /* Necessary to work with libfdt APIs */
+ const void *hw_config_dtb = (const void *)config;
+
+ /*
+ * Find the offset of the node containing "arm,gic-v3" compatible property.
+ * Populating fconf strucutures dynamically is not supported for legacy
+ * systems which use GICv2 IP. Simply skip extracting GIC properties.
+ */
+ node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,gic-v3");
+ if (node < 0) {
+ WARN("FCONF: Unable to locate node with arm,gic-v3 compatible property\n");
+ return 0;
+ }
+ /* The GICv3 DT binding holds at least two address/size pairs,
+ * the first describing the distributor, the second the redistributors.
+ * See: bindings/interrupt-controller/arm,gic-v3.yaml
+ */
+ err = fdt_get_reg_props_by_index(hw_config_dtb, node, 0, &addr, NULL);
+ if (err < 0) {
+ ERROR("FCONF: Failed to read GICD reg property of GIC node\n");
+ return err;
+ }
+ gicv3_config.gicd_base = addr;
+
+ err = fdt_get_reg_props_by_index(hw_config_dtb, node, 1, &addr, NULL);
+ if (err < 0) {
+ ERROR("FCONF: Failed to read GICR reg property of GIC node\n");
+ } else {
+ gicv3_config.gicr_base = addr;
+ }
+
+ return err;
+}
+FCONF_REGISTER_POPULATOR(HW_CONFIG, gicv3_config, fconf_populate_gicv3_config);
diff --git a/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c b/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
index fb7f48e..abc78ce 100644
--- a/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
+++ b/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
@@ -14,7 +14,6 @@
#include <libfdt.h>
#include <plat/common/platform.h>
-struct gicv3_config_t gicv3_config;
struct hw_topology_t soc_topology;
struct uart_serial_config_t uart_serial_config;
struct cpu_timer_t cpu_timer;
@@ -32,45 +31,6 @@
#define ILLEGAL_ADDR ULL(~0)
-int fconf_populate_gicv3_config(uintptr_t config)
-{
- int err;
- int node;
- uintptr_t addr;
-
- /* Necessary to work with libfdt APIs */
- const void *hw_config_dtb = (const void *)config;
-
- /*
- * Find the offset of the node containing "arm,gic-v3" compatible property.
- * Populating fconf strucutures dynamically is not supported for legacy
- * systems which use GICv2 IP. Simply skip extracting GIC properties.
- */
- node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,gic-v3");
- if (node < 0) {
- WARN("FCONF: Unable to locate node with arm,gic-v3 compatible property\n");
- return 0;
- }
- /* The GICv3 DT binding holds at least two address/size pairs,
- * the first describing the distributor, the second the redistributors.
- * See: bindings/interrupt-controller/arm,gic-v3.yaml
- */
- err = fdt_get_reg_props_by_index(hw_config_dtb, node, 0, &addr, NULL);
- if (err < 0) {
- ERROR("FCONF: Failed to read GICD reg property of GIC node\n");
- return err;
- }
- gicv3_config.gicd_base = addr;
-
- err = fdt_get_reg_props_by_index(hw_config_dtb, node, 1, &addr, NULL);
- if (err < 0) {
- ERROR("FCONF: Failed to read GICR reg property of GIC node\n");
- } else {
- gicv3_config.gicr_base = addr;
- }
-
- return err;
-}
int fconf_populate_topology(uintptr_t config)
{
@@ -447,7 +407,6 @@
return 0;
}
-FCONF_REGISTER_POPULATOR(HW_CONFIG, gicv3_config, fconf_populate_gicv3_config);
FCONF_REGISTER_POPULATOR(HW_CONFIG, topology, fconf_populate_topology);
FCONF_REGISTER_POPULATOR(HW_CONFIG, uart_config, fconf_populate_uart_config);
FCONF_REGISTER_POPULATOR(HW_CONFIG, cpu_timer, fconf_populate_cpu_timer);
diff --git a/plat/arm/board/fvp/fdts/fvp_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
index a11c1de..fd6cf78 100644
--- a/plat/arm/board/fvp/fdts/fvp_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
@@ -27,7 +27,7 @@
load-address = <0x0 0x07f00000>;
max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
id = <HW_CONFIG_ID>;
- secondary-load-address = <0x0 0x82000000>;
+ secondary-load-address = <0x0 FVP_HW_CONFIG_ADDR>;
};
/*
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 9d0463d..9c80283 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -68,6 +68,10 @@
#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
DEVICE1_SIZE, \
+ MT_DEVICE | MT_RW | EL3_PAS)
+
+#define MAP_CCN MAP_REGION_FLAT(CCN_BASE, \
+ CCN_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#if FVP_GICR_REGION_PROTECTION
@@ -115,7 +119,7 @@
V2M_MAP_IOFPGA,
MAP_DEVICE0,
#if FVP_INTERCONNECT_DRIVER == FVP_CCN
- MAP_DEVICE1,
+ MAP_CCN,
#endif
#if TRUSTED_BOARD_BOOT
/* To access the Root of Trust Public Key registers. */
@@ -133,7 +137,7 @@
V2M_MAP_IOFPGA,
MAP_DEVICE0,
#if FVP_INTERCONNECT_DRIVER == FVP_CCN
- MAP_DEVICE1,
+ MAP_CCN,
#endif
ARM_MAP_NS_DRAM1,
#ifdef __aarch64__
@@ -208,6 +212,9 @@
MAP_GICD_MEM,
MAP_GICR_MEM,
#else
+#if FVP_INTERCONNECT_DRIVER == FVP_CCN
+ MAP_CCN,
+#endif
MAP_DEVICE1,
#endif /* FVP_GICR_REGION_PROTECTION */
ARM_V2M_MAP_MEM_PROTECT,
@@ -254,6 +261,9 @@
#endif
V2M_MAP_IOFPGA,
MAP_DEVICE0,
+#if FVP_INTERCONNECT_DRIVER == FVP_CCN
+ MAP_CCN,
+#endif
MAP_DEVICE1,
{0}
};
@@ -773,8 +783,8 @@
/* Set number of consoles */
num_consoles = FVP_RMM_CONSOLE_COUNT;
- /* Set number of device non-coherent address ranges based on DT */
- num_ncoh_regions = FCONF_GET_PROPERTY(hw_config, pci_props, num_ncoh_regions);
+ /* Set number of device non-coherent address ranges for FVP RevC */
+ num_ncoh_regions = 2;
/* Set number of SMMUs */
num_smmus = FVP_RMM_SMMU_COUNT;
@@ -907,6 +917,11 @@
(void)memset((void *)ncoh_region_ptr, 0,
sizeof(struct memory_bank) * num_ncoh_regions);
+ /* Set number of device non-coherent address ranges based on DT */
+ num_ncoh_regions = FCONF_GET_PROPERTY(hw_config, pci_props, num_ncoh_regions);
+ /* At least 1 PCIe region need to be described in DT */
+ assert((num_ncoh_regions > 0) && (num_ncoh_regions <= 2));
+
for (unsigned long i = 0UL; i < num_ncoh_regions; i++) {
ncoh_region_ptr[i].base =
FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].base);
@@ -914,6 +929,17 @@
FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].size);
}
+ /*
+ * Workaround if the DT does not specify the 2nd PCIe region. This code can be
+ * removed when upstream DT is updated to have 2nd PCIe region.
+ */
+ if (num_ncoh_regions == 1) {
+ num_ncoh_regions++;
+ /* Add 3GB of 2nd PCIe region */
+ ncoh_region_ptr[1].base = 0x4000000000;
+ ncoh_region_ptr[1].size = 0xc0000000;
+ }
+
/* Update checksum */
checksum += checksum_calc((uint64_t *)ncoh_region_ptr,
sizeof(struct memory_bank) * num_ncoh_regions);
diff --git a/plat/arm/board/fvp/fvp_def.h b/plat/arm/board/fvp/fvp_def.h
index 831eb35..d87be31 100644
--- a/plat/arm/board/fvp/fvp_def.h
+++ b/plat/arm/board/fvp/fvp_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -53,12 +53,12 @@
* In case of FVP models with CCN, the CCN register space overlaps into
* the NSRAM area.
*/
-#if FVP_INTERCONNECT_DRIVER == FVP_CCN
-#define DEVICE1_BASE UL(0x2e000000)
-#define DEVICE1_SIZE UL(0x1A00000)
-#else
-#define DEVICE1_BASE BASE_GICD_BASE
+#define CCN_BASE UL(0x2e000000)
+#define CCN_SIZE UL(0x1000000)
+/* TODO: this covers gicv5, but macros should be adjusted */
+#if USE_GIC_DRIVER != 5
+#define DEVICE1_BASE BASE_GICD_BASE
#if GIC_ENABLE_V4_EXTN
/* GICv4 mapping: GICD + CORE_COUNT * 256KB */
#define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \
@@ -68,10 +68,11 @@
#define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \
(PLATFORM_CORE_COUNT * 0x20000))
#endif /* GIC_ENABLE_V4_EXTN */
-
-#define NSRAM_BASE UL(0x2e000000)
-#define NSRAM_SIZE UL(0x10000)
+#else
+#define DEVICE1_BASE BASE_IWB_BASE
+#define DEVICE1_SIZE ((BASE_IRS_BASE - BASE_IWB_BASE) + SZ_64K)
#endif
+
/* Devices in the second GB */
#define DEVICE2_BASE UL(0x7fe00000)
#define DEVICE2_SIZE UL(0x00200000)
@@ -124,6 +125,15 @@
#define FVP_SP810_CTRL_TIM2_OV BIT_32(20)
#define FVP_SP810_CTRL_TIM3_OV BIT_32(22)
+
+#define NSRAM_BASE UL(0x2e000000)
+#define NSRAM_SIZE UL(0x10000)
+/*
+ * In case of FVP models with CCN, the CCN register space overlaps into
+ * the NSRAM area.
+ */
+#define CCN_BASE UL(0x2e000000)
+#define CCN_SIZE UL(0x1000000)
/*******************************************************************************
* GIC & interrupt handling related constants
******************************************************************************/
@@ -138,6 +148,9 @@
#define BASE_GICD_SIZE UL(0x10000)
#define BASE_GICR_BASE UL(0x2f100000)
+#define BASE_IWB_BASE UL(0x2f000000)
+#define BASE_IRS_BASE UL(0x2f1c0000)
+
#if GIC_ENABLE_V4_EXTN
/* GICv4 redistributor size: 256KB */
#define BASE_GICR_SIZE UL(0x40000)
diff --git a/plat/arm/board/fvp/fvp_gicv5.c b/plat/arm/board/fvp/fvp_gicv5.c
new file mode 100644
index 0000000..73bd9c5
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_gicv5.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/gicv5.h>
+#include <platform_def.h>
+
+/* wire 26 is the timer interrupt. Will be assigned NS by default */
+struct gicv5_wire_props irs0_spis[] = {
+};
+
+struct gicv5_wire_props iwb0_wires[] = {
+};
+
+struct gicv5_irs irss[] = {{
+ .el3_config_frame = BASE_IRS_BASE,
+ .spis = irs0_spis,
+ .num_spis = ARRAY_SIZE(irs0_spis),
+}};
+
+struct gicv5_iwb iwbs[] = {{
+ .config_frame = BASE_IWB_BASE,
+ .wires = iwb0_wires,
+ .num_wires = ARRAY_SIZE(iwb0_wires)
+}};
+
+const struct gicv5_driver_data plat_gicv5_driver_data = {
+ .irss = irss,
+ .iwbs = iwbs,
+ .num_irss = ARRAY_SIZE(irss),
+ .num_iwbs = ARRAY_SIZE(iwbs)
+};
+
+void fvp_gic_driver_pre_init(void)
+{
+}
+
+void fvp_pcpu_init(void)
+{
+}
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 8e8870c..ea1b7e7 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -22,13 +22,6 @@
# only; enable redistributor frames of all CPU cores by default.
FVP_GICR_REGION_PROTECTION := 0
-ifeq (${HW_ASSISTED_COHERENCY}, 0)
-FVP_DT_PREFIX := fvp-base-gicv3-psci
-else
-FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq
-endif
-# fdts is wrong otherwise
-
# Size (in kilobytes) of the Trusted SRAM region to utilize when building for
# the FVP platform.
ifeq (${ENABLE_RME},1)
@@ -137,7 +130,26 @@
GICV3_OVERRIDE_DISTIF_PWR_OPS := 1
FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c
+ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),)
+BL31_SOURCES += plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c
+endif
+ifeq (${HW_ASSISTED_COHERENCY}, 0)
+FVP_DT_PREFIX := fvp-base-gicv3-psci
+else
+FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq
+endif
+else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV5)
+USE_GIC_DRIVER := 5
+ENABLE_FEAT_GCIE := 1
+BL31_SOURCES += plat/arm/board/fvp/fvp_gicv5.c
+FVP_DT_PREFIX := "FVP does not provide a GICv5 dts yet"
+ifneq ($(SPD),none)
+ $(error Error: GICv5 is not compatible with SPDs)
+endif
+ifeq ($(ENABLE_RME),1)
+ $(error Error: GICv5 is not compatible with RME)
+endif
else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2)
USE_GIC_DRIVER := 2
@@ -359,6 +371,10 @@
$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS)))
HW_CONFIG := ${FVP_HW_CONFIG}
+# Allow hw_config's secondary-load-address in the DT to be changed
+FVP_HW_CONFIG_ADDR ?= 0x82000000
+DTC_CPPFLAGS += -DFVP_HW_CONFIG_ADDR=$(FVP_HW_CONFIG_ADDR)
+
# Set default initrd base 128MiB offset of the default kernel address in FVP
INITRD_BASE ?= 0x90000000
diff --git a/plat/common/plat_gicv5.c b/plat/common/plat_gicv5.c
new file mode 100644
index 0000000..e445886
--- /dev/null
+++ b/plat/common/plat_gicv5.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <bl31/interrupt_mgmt.h>
+#include <drivers/arm/gicv5.h>
+
+uint32_t plat_ic_get_pending_interrupt_type(void)
+{
+ return gicv5_get_pending_interrupt_type();
+}
+
+bool plat_ic_has_interrupt_type(unsigned int type)
+{
+ return gicv5_has_interrupt_type(type);
+}
diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c
index a3c3545..dabe865 100644
--- a/plat/intel/soc/agilex/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex/bl31_plat_setup.c
@@ -67,6 +67,11 @@
mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
PLAT_BAUDRATE, &console);
+
+ /* Enable TF-A BL31 logs when running from non-secure world also. */
+ console_set_scope(&console,
+ (CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH));
+
/*
* Check params passed from BL31 should not be NULL,
*/
diff --git a/plat/intel/soc/agilex5/include/agilex5_system_manager.h b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
index 8c86ab1..f4b53e8 100644
--- a/plat/intel/soc/agilex5/include/agilex5_system_manager.h
+++ b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
@@ -160,6 +160,11 @@
#define SOCFPGA_ECC_QSPI_ECC_STARTACC 0x7C
#define SOCFPGA_ECC_QSPI_ECC_WDCTRL 0x80
+/* IOSSM mailbox address */
+#define IOSSM_CMD_PARAM 0x18400438
+#define IOSSM_CMD_TRIG_OP 0x1840043C
+#define IOSSM_CMD_RESP_STATUS 0x1840045C
+
#define DMA0_STREAM_CTRL_REG 0x10D1217C
#define DMA1_STREAM_CTRL_REG 0x10D12180
#define SDM_STREAM_CTRL_REG 0x10D12184
diff --git a/plat/intel/soc/agilex5/soc/agilex5_ddr.c b/plat/intel/soc/agilex5/soc/agilex5_ddr.c
index 0d60324..acf7528 100644
--- a/plat/intel/soc/agilex5/soc/agilex5_ddr.c
+++ b/plat/intel/soc/agilex5/soc/agilex5_ddr.c
@@ -297,7 +297,7 @@
bool full_mem_init = false;
phys_size_t hw_ddr_size;
phys_size_t config_ddr_size;
- struct io96b_info io96b_ctrl;
+ struct io96b_info io96b_ctrl = {0};
enum reset_type reset_t = get_reset_type(mmio_read_32(SOCFPGA_SYSMGR(
BOOT_SCRATCH_COLD_3)));
bool is_dualport = hoff_ptr->ddr_config & BIT(0);
diff --git a/plat/intel/soc/common/include/socfpga_fcs.h b/plat/intel/soc/common/include/socfpga_fcs.h
index f92678f..21d9b66 100644
--- a/plat/intel/soc/common/include/socfpga_fcs.h
+++ b/plat/intel/soc/common/include/socfpga_fcs.h
@@ -76,6 +76,10 @@
#define FCS_MAX_DATA_SIZE 0x20000000 /* 512 MB */
#define FCS_MIN_DATA_SIZE 0x8 /* 8 Bytes */
+#define FCS_AES_DATA_SIZE_CHECK(x) (((x >= FCS_AES_MIN_DATA_SIZE) && \
+ (x <= FCS_AES_MAX_DATA_SIZE)) ? \
+ true : false)
+
#define FCS_GET_DIGEST_CMD_MAX_WORD_SIZE 7U
#define FCS_GET_DIGEST_RESP_MAX_WORD_SIZE 19U
#define FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE 23U
@@ -362,7 +366,7 @@
uint32_t session_id, uint32_t context_id,
uint64_t src_addr, uint32_t src_size,
uint64_t dst_addr, uint32_t dst_size,
- uint32_t aad_size, uint8_t is_finalised,
+ uint32_t padding_size, uint8_t is_finalised,
uint32_t *send_id, uint64_t smmu_src_addr,
uint64_t smmu_dst_addr);
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index f965b7d..4da318b 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -309,7 +309,7 @@
((client_id << MBOX_CLIENT_ID_SHIFT) | \
(job_id << MBOX_JOB_ID_SHIFT) | \
(args_len << MBOX_CMD_LEN_SHIFT) | \
- (indirect << MBOX_CMD_LEN_SHIFT) | \
+ (indirect << MBOX_INDIRECT_SHIFT) | \
cmd)
#define FLAG_SDM_RESPONSE_IS_VALID BIT(0)
@@ -362,7 +362,7 @@
/* SDM client callback template */
typedef uint8_t (*sdm_command_callback)(void *resp, void *cmd,
- uint32_t *ret_args);
+ uint64_t *ret_args);
/* SDM command data structure */
typedef struct sdm_command {
@@ -394,7 +394,7 @@
sdm_command_callback cb, uint32_t *cb_args,
uint32_t cb_args_len);
-int mailbox_response_poll_v3(uint8_t client_id, uint8_t job_id, uint32_t *ret_args,
+int mailbox_response_poll_v3(uint8_t client_id, uint8_t job_id, uint64_t *ret_args,
uint32_t *ret_args_size);
int mailbox_response_poll_on_intr_v3(uint8_t *client_id, uint8_t *job_id,
diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h
index 7f96adb..9e06397 100644
--- a/plat/intel/soc/common/include/socfpga_sip_svc.h
+++ b/plat/intel/soc/common/include/socfpga_sip_svc.h
@@ -153,6 +153,9 @@
/* ATF build version */
#define INTEL_SIP_SMC_ATF_BUILD_VER 0xC200009B
+/* IO96B ECC Error Injection */
+#define INTEL_SIP_SMC_INJECT_IO96B_ECC_ERR 0xC200009C
+
#define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF
#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF
#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET 4U
@@ -163,6 +166,8 @@
#define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\
SYSMGR_ECC_DDR0_MASK |\
SYSMGR_ECC_DDR1_MASK)
+#define IOSSM_ECC_ERR_INJ_DELAY_USECS (40U)
+#define IOSSM_CMD_STATUS_RESP_READY BIT(0)
/* Non-mailbox SMC Call */
#define INTEL_SIP_SMC_SVC_VERSION 0xC2000200
@@ -255,6 +260,12 @@
#define SMC_RET_ARGS_FOUR (4)
#define SMC_RET_ARGS_FIVE (5)
#define SMC_RET_ARGS_SIX (6)
+#define SMC_RET_ARGS_SEVEN (7)
+#define SMC_RET_ARGS_EIGHT (8)
+#define SMC_RET_ARGS_NINE (9)
+#define SMC_RET_ARGS_TEN (10)
+
+#define MBOX_GEN_CMD_MAX_WORDS (0x1000)
/*
* SiP SVC Version3 SMC Functions IDs
@@ -278,6 +289,14 @@
#define ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP (0x420000E8)
#define ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT (0x420000E9)
+/* RSU related commands */
+#define ALTERA_SIP_SMC_ASYNC_RSU_GET_SPT (0x420000EA)
+#define ALTERA_SIP_SMC_ASYNC_RSU_GET_STATUS (0x420000EB)
+#define ALTERA_SIP_SMC_ASYNC_RSU_NOTIFY (0x420000EC)
+
+/* V3 Generic mailbox command. */
+#define ALTERA_SIP_SMC_ASYNC_GEN_MBOX_CMD (0x420000EE)
+
/* FCS crypto service VAB/SDOS commands */
#define ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER (0x4200012C)
#define ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT (0x4200012D)
@@ -344,6 +363,8 @@
#define GET_CLIENT_ID(x) (((x) & 0xF0) >> 4)
#define GET_JOB_ID(x) ((x) & 0x0F)
+#define GET_ADDR64(high, low) (((uint64_t)(high) \
+ << 32) | (low))
#endif /* SIP_SVC_V3 */
#endif /* SOCFPGA_SIP_SVC_H */
diff --git a/plat/intel/soc/common/sip/socfpga_sip_fcs.c b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
index b9c7b59..507a9e9 100644
--- a/plat/intel/soc/common/sip/socfpga_sip_fcs.c
+++ b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
@@ -25,7 +25,7 @@
static fcs_crypto_service_data fcs_ecdsa_get_pubkey_param;
static fcs_crypto_service_data fcs_ecdh_request_param;
-uint8_t fcs_send_cert_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_send_cert_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -42,7 +42,7 @@
return ret_args_len;
}
-uint8_t fcs_cntr_set_preauth_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cntr_set_preauth_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -57,7 +57,7 @@
return ret_args_len;
}
-uint8_t fcs_get_attest_cert_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_get_attest_cert_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -74,7 +74,7 @@
return ret_args_len;
}
-uint8_t fcs_hkdf_request_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_hkdf_request_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -92,7 +92,7 @@
return ret_args_len;
}
-uint8_t fcs_create_cert_reload_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_create_cert_reload_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -107,7 +107,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_get_digest_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_get_digest_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -124,7 +124,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_mac_verify_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_mac_verify_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -144,7 +144,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_hash_sign_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_hash_sign_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -162,7 +162,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_hash_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_hash_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -180,7 +180,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_aes_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_aes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -198,7 +198,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_data_sign_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_data_sign_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -215,7 +215,7 @@
return ret_args_len;
}
-uint8_t fcs_sdos_crypto_request_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_sdos_crypto_request_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -233,7 +233,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_get_public_key_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_get_public_key_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -251,7 +251,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_data_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_data_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -268,7 +268,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_ecdh_request_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_ecdh_request_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -304,6 +304,17 @@
}
}
+/* As of now used on only Agilex5 platform. */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+static bool is_16_bytes_aligned(uint32_t data)
+{
+ if ((data % (MBOX_WORD_BYTE * 4U)) != 0U)
+ return false;
+ else
+ return true;
+}
+#endif
+
static bool is_32_bytes_aligned(uint32_t data)
{
if ((data % (8U * MBOX_WORD_BYTE)) != 0U) {
@@ -2708,7 +2719,7 @@
uint32_t session_id, uint32_t context_id,
uint64_t src_addr, uint32_t src_size,
uint64_t dst_addr, uint32_t dst_size,
- uint32_t aad_size, uint8_t is_finalised,
+ uint32_t padding_size, uint8_t is_finalised,
uint32_t *send_id, uint64_t smmu_src_addr,
uint64_t smmu_dst_addr)
{
@@ -2719,30 +2730,55 @@
uint32_t fcs_aes_crypt_payload[FCS_AES_CMD_MAX_WORD_SIZE];
uint32_t src_addr_sdm = (uint32_t)src_addr;
uint32_t dst_addr_sdm = (uint32_t)dst_addr;
+ bool is_src_size_aligned;
+ bool is_dst_size_aligned;
+ bool is_src_size_valid;
+ bool is_dst_size_valid;
if (fcs_aes_init_payload.session_id != session_id ||
fcs_aes_init_payload.context_id != context_id) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
+ /* Default source and destination size align check, 32 bytes alignment. */
+ is_src_size_aligned = is_32_bytes_aligned(src_size);
+ is_dst_size_aligned = is_32_bytes_aligned(dst_size);
+ is_src_size_valid = FCS_AES_DATA_SIZE_CHECK(src_size);
+ is_dst_size_valid = FCS_AES_DATA_SIZE_CHECK(dst_size);
+
+ /*
+ * Get the requested block mode.
+ * On the Agilex5 platform with GCM and GCM-GHASH modes, the source and destination size
+ * should be in multiples of 16 bytes. For other platforms and other modes, it should be
+ * in multiples of 32 bytes.
+ */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ uint32_t block_mode = fcs_aes_init_payload.crypto_param[0] & FCS_CRYPTO_BLOCK_MODE_MASK;
+
+ if ((block_mode == FCS_CRYPTO_GCM_MODE) ||
+ (block_mode == FCS_CRYPTO_GCM_GHASH_MODE)) {
+ is_src_size_aligned = is_16_bytes_aligned(src_size);
+ is_dst_size_aligned = is_16_bytes_aligned(dst_size);
+ /* The size validity here is, should be 0 or multiples of 16 bytes. */
+ is_src_size_valid = is_16_bytes_aligned(src_size);
+ is_dst_size_valid = is_16_bytes_aligned(dst_size);
+ }
+#endif
+
if ((!is_8_bytes_aligned(src_addr)) ||
- (!is_32_bytes_aligned(src_size)) ||
+ (!is_src_size_aligned) ||
(!is_address_in_ddr_range(src_addr, src_size))) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
if ((!is_8_bytes_aligned(dst_addr)) ||
- (!is_32_bytes_aligned(dst_size)) ||
+ (!is_dst_size_aligned) ||
(!is_address_in_ddr_range(dst_addr, dst_size))) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
- if ((dst_size > FCS_AES_MAX_DATA_SIZE ||
- dst_size < FCS_AES_MIN_DATA_SIZE) ||
- (src_size > FCS_AES_MAX_DATA_SIZE ||
- src_size < FCS_AES_MIN_DATA_SIZE)) {
+ if (!is_src_size_valid || !is_dst_size_valid)
return INTEL_SIP_SMC_STATUS_REJECTED;
- }
/* Prepare crypto header*/
flag = 0;
@@ -2802,11 +2838,14 @@
fcs_aes_crypt_payload[i] = dst_size;
i++;
- /* Additional Authenticated Data size */
- if (aad_size > 0) {
- fcs_aes_crypt_payload[i] = aad_size;
+ /* Padding data size, only on Agilex5 with GCM and GCM-GHASH modes. */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ if ((block_mode == FCS_CRYPTO_GCM_MODE) ||
+ (block_mode == FCS_CRYPTO_GCM_GHASH_MODE)) {
+ fcs_aes_crypt_payload[i] = padding_size;
i++;
}
+#endif
status = ((smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE) ||
(smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE)) ?
@@ -2828,7 +2867,7 @@
sizeof(fcs_aes_init_payload));
}
- if (status < 0U) {
+ if (status < 0) {
return INTEL_SIP_SMC_STATUS_ERROR;
}
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index 3b3b479..bf1b7fb 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -1442,7 +1442,7 @@
}
int mailbox_response_poll_v3(uint8_t client_id, uint8_t job_id,
- uint32_t *ret_args, uint32_t *ret_args_len)
+ uint64_t *ret_args, uint32_t *ret_args_len)
{
sdm_command_t *cmd_desc = NULL;
sdm_response_t *resp_desc = NULL;
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index f4a3ea0..ff19e23 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -9,6 +9,7 @@
#include <assert.h>
#include <common/debug.h>
#include <common/runtime_svc.h>
+#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <tools_share/uuid.h>
@@ -799,10 +800,26 @@
}
return INTEL_SIP_SMC_STATUS_OK;
}
+
+static void intel_inject_io96b_ecc_err(const uint32_t *syndrome, const uint32_t command)
+{
+ volatile uint64_t atf_ddr_buffer;
+ volatile uint64_t val;
+
+ mmio_write_32(IOSSM_CMD_PARAM, *syndrome);
+ mmio_write_32(IOSSM_CMD_TRIG_OP, command);
+ udelay(IOSSM_ECC_ERR_INJ_DELAY_USECS);
+ atf_ddr_buffer = 0xCAFEBABEFEEDFACE; /* Write data */
+ memcpy_s((void *)&val, sizeof(val),
+ (void *)&atf_ddr_buffer, sizeof(atf_ddr_buffer));
+
+ /* Clear response_ready BIT0 of status_register before sending next command. */
+ mmio_clrbits_32(IOSSM_CMD_RESP_STATUS, IOSSM_CMD_STATUS_RESP_READY);
+}
#endif
#if SIP_SVC_V3
-uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -816,7 +833,7 @@
return ret_args_len;
}
-uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -831,7 +848,7 @@
return ret_args_len;
}
-uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -848,7 +865,7 @@
return ret_args_len;
}
-uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -866,35 +883,201 @@
return ret_args_len;
}
-static uintptr_t smc_ret(void *handle, uint32_t *ret_args, uint32_t ret_args_len)
+uint8_t sip_smc_cmd_cb_rsu_status(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
+ uint8_t ret_args_len = 0U;
+ uint32_t retry_counter = ~0U;
+ uint32_t failure_source = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ /* Get the failure source and current image retry counter value from the response. */
+ failure_source = resp->resp_data[5] & RSU_VERSION_ACMF_MASK;
+ retry_counter = resp->resp_data[8];
+
+ if ((retry_counter != ~0U) && (failure_source == 0U))
+ resp->resp_data[5] |= RSU_VERSION_ACMF;
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ /* Current CMF */
+ ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[1], resp->resp_data[0]);
+ /* Last Failing CMF Address */
+ ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[3], resp->resp_data[2]);
+ /* Config State */
+ ret_args[ret_args_len++] = resp->resp_data[4];
+ /* Version */
+ ret_args[ret_args_len++] = (GENMASK(16, 0) & resp->resp_data[5]);
+ /* Failure Source */
+ ret_args[ret_args_len++] = ((GENMASK(32, 17) & resp->resp_data[5]) >> 16);
+ /* Error location */
+ ret_args[ret_args_len++] = resp->resp_data[6];
+ /* Error details */
+ ret_args[ret_args_len++] = resp->resp_data[7];
+ /* Current image retry counter */
+ ret_args[ret_args_len++] = resp->resp_data[8];
+
+ return ret_args_len;
+}
+
+uint8_t sip_smc_cmd_cb_rsu_spt(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ /* Sub Partition Table (SPT) 0 address */
+ ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[0], resp->resp_data[1]);
+ /* Sub Partition Table (SPT) 1 address */
+ ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[2], resp->resp_data[3]);
+
+ return ret_args_len;
+}
+
+static uintptr_t smc_ret(void *handle, uint64_t *ret_args, uint32_t ret_args_len)
+{
+
switch (ret_args_len) {
case SMC_RET_ARGS_ONE:
+ VERBOSE("SVC V3: %s: x0 0x%lx\n", __func__, ret_args[0]);
SMC_RET1(handle, ret_args[0]);
break;
case SMC_RET_ARGS_TWO:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx\n", __func__, ret_args[0], ret_args[1]);
SMC_RET2(handle, ret_args[0], ret_args[1]);
break;
case SMC_RET_ARGS_THREE:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2]);
SMC_RET3(handle, ret_args[0], ret_args[1], ret_args[2]);
break;
case SMC_RET_ARGS_FOUR:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3]);
SMC_RET4(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3]);
break;
case SMC_RET_ARGS_FIVE:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]);
SMC_RET5(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]);
break;
+ case SMC_RET_ARGS_SIX:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx x3 0x%lx, x4 0x%lx x5 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5]);
+ SMC_RET6(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5]);
+ break;
+
+ case SMC_RET_ARGS_SEVEN:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t"
+ "x6 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6]);
+ SMC_RET7(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6]);
+ break;
+
+ case SMC_RET_ARGS_EIGHT:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t"
+ "x6 0x%lx, x7 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6], ret_args[7]);
+ SMC_RET8(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6], ret_args[7]);
+ break;
+
+ case SMC_RET_ARGS_NINE:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t"
+ "x6 0x%lx, x7 0x%lx, x8 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6], ret_args[7], ret_args[8]);
+ SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6], ret_args[7], ret_args[8],
+ 0, 0, 0, 0, 0, 0, 0, 0, 0);
+ break;
+
+ case SMC_RET_ARGS_TEN:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t"
+ "x6 0x%lx, x7 0x%lx x8 0x%lx, x9 0x%lx, x10 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3],
+ ret_args[4], ret_args[5], ret_args[6], ret_args[7], ret_args[8],
+ ret_args[9], ret_args[10]);
+ SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6], ret_args[7], ret_args[8], ret_args[9],
+ 0, 0, 0, 0, 0, 0, 0, 0);
+ break;
+
default:
+ VERBOSE("SVC V3: %s ret_args_len is wrong, please check %d\n ",
+ __func__, ret_args_len);
SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
break;
}
}
+static inline bool is_gen_mbox_cmd_allowed(uint32_t cmd)
+{
+ /* Check if the command is allowed to be executed in generic mbox format */
+ bool is_cmd_allowed = false;
+
+ switch (cmd) {
+ case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION:
+ case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION:
+ case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY:
+ case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY:
+ case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY:
+ case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO:
+ case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY:
+ case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST:
+ case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION:
+ /* These commands are not supported in the generic mailbox format. */
+ break;
+
+ default:
+ is_cmd_allowed = true;
+ break;
+ } /* switch */
+
+ return is_cmd_allowed;
+}
+
/*
* This function is responsible for handling all SiP SVC V3 calls from the
* non-secure world.
@@ -929,8 +1112,8 @@
switch (smc_fid) {
case ALTERA_SIP_SMC_ASYNC_RESP_POLL:
{
- uint32_t ret_args[8] = {0};
- uint32_t ret_args_len;
+ uint64_t ret_args[16] = {0};
+ uint32_t ret_args_len = 0;
status = mailbox_response_poll_v3(GET_CLIENT_ID(x1),
GET_JOB_ID(x1),
@@ -1177,6 +1360,111 @@
SMC_RET1(handle, status);
}
+ case ALTERA_SIP_SMC_ASYNC_RSU_GET_SPT:
+ {
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_GET_SUBPARTITION_TABLE,
+ NULL,
+ 0,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_rsu_spt,
+ NULL,
+ 0);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_RSU_GET_STATUS:
+ {
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_RSU_STATUS,
+ NULL,
+ 0,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_rsu_status,
+ NULL,
+ 0);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_RSU_NOTIFY:
+ {
+ uint32_t notify_code = (uint32_t)x2;
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_HPS_STAGE_NOTIFY,
+ ¬ify_code,
+ 1U,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_ret2,
+ NULL,
+ 0);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_GEN_MBOX_CMD:
+ {
+ /* Filter the required commands here. */
+ if (!is_gen_mbox_cmd_allowed(smc_fid)) {
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+
+ /* Collect all the args passed in, and send the mailbox command. */
+ uint32_t mbox_cmd = (uint32_t)x2;
+ uint32_t *cmd_payload_addr = NULL;
+ uint32_t cmd_payload_len = (uint32_t)x4 / MBOX_WORD_BYTE;
+ uint32_t *resp_payload_addr = NULL;
+ uint32_t resp_payload_len = (uint32_t)x6 / MBOX_WORD_BYTE;
+
+ if ((cmd_payload_len > MBOX_GEN_CMD_MAX_WORDS) ||
+ (resp_payload_len > MBOX_GEN_CMD_MAX_WORDS)) {
+ ERROR("MBOX: 0x%x: Command/Response payload length exceeds max limit\n",
+ smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+
+ /* Make sure we have valid command payload length and buffer */
+ if (cmd_payload_len != 0U) {
+ cmd_payload_addr = (uint32_t *)x3;
+ if (cmd_payload_addr == NULL) {
+ ERROR("MBOX: 0x%x: Command payload address is NULL\n",
+ smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+ }
+
+ /* Make sure we have valid response payload length and buffer */
+ if (resp_payload_len != 0U) {
+ resp_payload_addr = (uint32_t *)x5;
+ if (resp_payload_addr == NULL) {
+ ERROR("MBOX: 0x%x: Response payload address is NULL\n",
+ smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+ }
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ mbox_cmd,
+ (uint32_t *)cmd_payload_addr,
+ cmd_payload_len,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_ret_nbytes_cb,
+ (uint32_t *)resp_payload_addr,
+ resp_payload_len);
+
+ SMC_RET1(handle, status);
+ }
+
case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT:
{
uint32_t session_id = (uint32_t)x2;
@@ -2194,6 +2482,12 @@
SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR,
VERSION_MINOR, VERSION_PATCH);
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ case INTEL_SIP_SMC_INJECT_IO96B_ECC_ERR:
+ intel_inject_io96b_ecc_err((uint32_t *)&x1, (uint32_t)x2);
+ SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK);
+#endif
+
default:
return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
cookie, handle, flags);
diff --git a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h
index 4d99df1..e1ead97 100644
--- a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h
+++ b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h
@@ -71,6 +71,7 @@
PER_CPU_PWR_DATA(ctrl, 0, 7); \
break; \
default: \
+ PER_CPU_PWR_DATA(ctrl, 0, 0); \
assert(0); \
break; \
} })
diff --git a/plat/mediatek/drivers/pmic/mt6359p/mt6359p_psc.c b/plat/mediatek/drivers/pmic/mt6359p/mt6359p_psc.c
new file mode 100644
index 0000000..6c0eb9c
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt6359p/mt6359p_psc.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+#include <drivers/pmic/pmic_psc.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <pmic_wrap_init_common.h>
+
+#include "registers.h"
+
+static const struct pmic_psc_reg mt6359p_psc_regs[] = {
+ PMIC_PSC_REG(RG_PWRHOLD, MT6359P_PPCCTL0, 0),
+ PMIC_PSC_REG(RG_CRST, MT6359P_PPCCTL1, 0),
+ PMIC_PSC_REG(RG_SMART_RST_SDN_EN, MT6359P_STRUP_CON12, 9),
+ PMIC_PSC_REG(RG_SMART_RST_MODE, MT6359P_STRUP_CON12, 10),
+};
+
+static const struct pmic_psc_config mt6359p_psc_config = {
+ .read_field = pwrap_read_field,
+ .write_field = pwrap_write_field,
+ .regs = mt6359p_psc_regs,
+ .reg_size = ARRAY_SIZE(mt6359p_psc_regs),
+};
+
+static int mt6359p_psc_init(void)
+{
+ return pmic_psc_register(&mt6359p_psc_config);
+}
+
+MTK_PLAT_SETUP_0_INIT(mt6359p_psc_init);
diff --git a/plat/mediatek/drivers/pmic/mt6359p/registers.h b/plat/mediatek/drivers/pmic/mt6359p/registers.h
new file mode 100644
index 0000000..f1b2a6d
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt6359p/registers.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef REGISTER_H
+#define REGISTER_H
+
+/* PMIC Registers for PSC */
+#define MT6359P_PPCCTL0 0xa08
+#define MT6359P_PPCCTL1 0xa0a
+#define MT6359P_STRUP_CON12 0xa12
+
+#endif /* REGISTER_H */
diff --git a/plat/mediatek/drivers/pmic/mt6359p/rules.mk b/plat/mediatek/drivers/pmic/mt6359p/rules.mk
new file mode 100644
index 0000000..39908f8
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt6359p/rules.mk
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := mt6359p
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/${PMIC_CHIP}_psc.c
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/pmic/mt8189/pmic_lowpower_init.c b/plat/mediatek/drivers/pmic/mt8189/pmic_lowpower_init.c
new file mode 100644
index 0000000..aa90b86
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt8189/pmic_lowpower_init.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+
+#include <drivers/pmic/mt6319_lowpower_reg.h>
+#include <drivers/pmic/mt6359p_set_lowpower.h>
+#include <drivers/pmic/pmic_swap_api.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <pmic_wrap_init_common.h>
+
+#define PMIC_SLVID_BUCK_SET_LP(_chip, _slvid, _name, _user, _en, _mode, _cfg) \
+{ \
+ struct spmi_device *sdev = lowpower_sdev[_slvid]; \
+ if (sdev) {\
+ pmic_spmi_update_bits(sdev, \
+ _chip##_RG_BUCK_##_name##_##_user##_OP_CFG_ADDR, \
+ 1 << _user, \
+ _cfg ? 1 << _user : 0); \
+ pmic_spmi_update_bits(sdev, \
+ _chip##_RG_BUCK_##_name##_##_user##_OP_MODE_ADDR, \
+ 1 << _user, \
+ _mode ? 1 << _user : 0); \
+ pmic_spmi_update_bits(sdev, \
+ _chip##_RG_BUCK_##_name##_##_user##_OP_EN_ADDR, \
+ 1 << _user, \
+ _en ? 1 << _user : 0); \
+ } \
+}
+
+struct spmi_device *lowpower_sdev[SPMI_MAX_SLAVE_ID];
+
+static const uint8_t lowpower_slvid_arr[] = {
+ SPMI_SLAVE_7,
+};
+
+static int pmic_spmi_update_bits(struct spmi_device *sdev, uint16_t reg,
+ uint8_t mask, uint8_t val)
+{
+ uint8_t orig = 0;
+ int ret = 0;
+
+ ret = spmi_ext_register_readl(sdev, reg, &orig, 1);
+ if (ret < 0)
+ return ret;
+ orig &= ~mask;
+ orig |= val & mask;
+ ret = spmi_ext_register_writel(sdev, reg, &orig, 1);
+ return ret;
+}
+
+static int pmic_lowpower_init(void)
+{
+ uint8_t i, slvid;
+
+ for (i = 0; i < ARRAY_SIZE(lowpower_slvid_arr); i++) {
+ slvid = lowpower_slvid_arr[i];
+ lowpower_sdev[slvid] = get_spmi_device(SPMI_MASTER_P_1, slvid);
+ if (!lowpower_sdev[slvid])
+ return -ENODEV;
+ }
+
+ PMIC_SLVID_BUCK_SET_LP(MT6319, SPMI_SLAVE_7, VBUCK3, HW0, true, OP_MODE_LP, HW_LP);
+
+ PMIC_BUCK_SET_LP(MT6359P, VPROC2, HW0, true, OP_MODE_LP, HW_OFF);
+ PMIC_BUCK_SET_LP(MT6359P, VPROC2, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_BUCK_SET_LP(MT6359P, VGPU11, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_BUCK_SET_LP(MT6359P, VGPU11, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_BUCK_SET_LP(MT6359P, VS1, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_BUCK_SET_LP(MT6359P, VS1, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_BUCK_SET_LP(MT6359P, VS2, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_BUCK_SET_LP(MT6359P, VS2, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VRF12, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VRF12, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VA12, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VA12, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VA09, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VA09, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VAUX18, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VAUX18, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VXO22, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VXO22, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VUSB, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VUSB, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VUFS, HW0, true, OP_MODE_LP, HW_LP);
+
+ return 0;
+}
+
+MTK_PLAT_SETUP_0_INIT(pmic_lowpower_init);
diff --git a/plat/mediatek/drivers/pmic/mt8189/pmic_shutdown_cfg.c b/plat/mediatek/drivers/pmic/mt8189/pmic_shutdown_cfg.c
new file mode 100644
index 0000000..dbb5852
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt8189/pmic_shutdown_cfg.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "../mt6359p/registers.h"
+#include <drivers/pmic/pmic_shutdown_cfg.h>
+#include <drivers/spmi/spmi_common.h>
+#include <drivers/spmi_api.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <pmic_wrap_init_common.h>
+
+#define MT6319_RG_SEQ_OFF 0x2d
+#define MT6319_TOP_RST_MISC_CLR 0x128
+#define MT6319_TOP_DIG_WPK_H 0x3a9
+#define MT6319_TOP_DIG_WPK_H_MASK 0xFF
+#define MT6319_TOP_DIG_WPK_H_SHIFT 0
+#define MT6319_TOP_DIG_WPK 0x3a8
+#define MT6319_TOP_DIG_WPK_MASK 0xFF
+#define MT6319_TOP_DIG_WPK_SHIFT 0
+
+
+int pmic_shutdown_cfg(void)
+{
+/*
+ * In mt8189, the pmic_shutdown_cfg() api does not need to read and write the
+ * pmic register to determine the return value and in order not to modify the
+ * common code to affect other ICs, the pmic_shutdown_cfg() will directly
+ * return 1.
+ */
+ return 1;
+}
+
+static void shutdown_slave_dev(struct spmi_device *dev)
+{
+ spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK_H, 0x63,
+ MT6319_TOP_DIG_WPK_H_MASK,
+ MT6319_TOP_DIG_WPK_H_SHIFT);
+ spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK, 0x15,
+ MT6319_TOP_DIG_WPK_MASK,
+ MT6319_TOP_DIG_WPK_SHIFT);
+
+ /* Disable WDTRSTB_EN */
+ spmi_ext_register_writel_field(dev, MT6319_TOP_RST_MISC_CLR, 1, 0x1, 0);
+ /* Normal sequence power off when PAD_EN falling */
+ spmi_ext_register_writel_field(dev, MT6319_RG_SEQ_OFF, 1, 0x1, 0);
+
+ spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK_H, 0,
+ MT6319_TOP_DIG_WPK_H_MASK,
+ MT6319_TOP_DIG_WPK_H_SHIFT);
+ spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK, 0,
+ MT6319_TOP_DIG_WPK_MASK,
+ MT6319_TOP_DIG_WPK_SHIFT);
+
+}
+
+int spmi_shutdown(void)
+{
+ struct spmi_device *mt6319_sdev;
+
+ mt6319_sdev = get_spmi_device(SPMI_MASTER_P_1, SPMI_SLAVE_7);
+ if (!mt6319_sdev)
+ return -ENODEV;
+ shutdown_slave_dev(mt6319_sdev);
+
+ if (mmio_read_32((uintptr_t)CHIP_ID_REG) == MTK_CPU_ID_MT8189 &&
+ mmio_read_32((uintptr_t)CPU_SEG_ID_REG) == MTK_CPU_SEG_ID_MT8189H) {
+ mt6319_sdev = get_spmi_device(SPMI_MASTER_P_1, SPMI_SLAVE_8);
+ if (!mt6319_sdev)
+ return -ENODEV;
+ shutdown_slave_dev(mt6319_sdev);
+ }
+
+ /* clear main pmic power hold */
+ pwrap_write_field(MT6359P_PPCCTL0, 0, 0x1, 0);
+
+ return 0;
+}
diff --git a/plat/mediatek/drivers/pmic/mt8189/pmic_swap_api.c b/plat/mediatek/drivers/pmic/mt8189/pmic_swap_api.c
new file mode 100644
index 0000000..0310389
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt8189/pmic_swap_api.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+
+#include <drivers/pmic/pmic_swap_api.h>
+
+/* No need to check second pmic mt6369 */
+bool is_second_pmic_pp_swap(void)
+{
+ return false;
+}
diff --git a/plat/mediatek/drivers/pmic/rules.mk b/plat/mediatek/drivers/pmic/rules.mk
index 0280df8..dc228ee 100644
--- a/plat/mediatek/drivers/pmic/rules.mk
+++ b/plat/mediatek/drivers/pmic/rules.mk
@@ -8,15 +8,15 @@
MODULE := pmic
-ifneq (${PMIC_CHIP}, mt6363)
-LOCAL_SRCS-y += ${LOCAL_DIR}/pmic.c
-PLAT_INCLUDES += -I${LOCAL_DIR}/
-else
-LOCAL_SRCS-y := ${LOCAL_DIR}/pmic_psc.c
+ifeq (${CONFIG_MTK_PMIC_SHUTDOWN_V2}, y)
LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_common_swap_api.c
+LOCAL_SRCS-y := ${LOCAL_DIR}/pmic_psc.c
LOCAL_SRCS-${CONFIG_MTK_PMIC_LOWPOWER} += ${LOCAL_DIR}/${MTK_SOC}/pmic_lowpower_init.c
LOCAL_SRCS-${CONFIG_MTK_PMIC_LOWPOWER} += ${LOCAL_DIR}/${MTK_SOC}/pmic_swap_api.c
LOCAL_SRCS-${CONFIG_MTK_PMIC_SHUTDOWN_CFG} += ${LOCAL_DIR}/${MTK_SOC}/pmic_shutdown_cfg.c
+else
+LOCAL_SRCS-y += ${LOCAL_DIR}/pmic.c
+PLAT_INCLUDES += -I${LOCAL_DIR}/
endif
$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/pmic_wrap/mt8189/pmic_wrap_init.h b/plat/mediatek/drivers/pmic_wrap/mt8189/pmic_wrap_init.h
new file mode 100644
index 0000000..9647326
--- /dev/null
+++ b/plat/mediatek/drivers/pmic_wrap/mt8189/pmic_wrap_init.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_WRAP_INIT_H
+#define PMIC_WRAP_INIT_H
+
+#include <platform_def.h>
+#include <pmic_wrap_init_common.h>
+
+#define PWRAP_DEBUG 0
+
+/* PMIC_WRAP registers */
+struct mt8189_pmic_wrap_regs {
+ uint32_t init_done;
+ uint32_t reserved[511];
+ struct {
+ uint32_t cmd;
+ uint32_t wdata;
+ uint32_t reserved1[3];
+ uint32_t rdata;
+ uint32_t reserved2[3];
+ uint32_t vldclr;
+ uint32_t sta;
+ uint32_t reserved3[5];
+ } wacs[4];
+};
+
+static struct mt8189_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE;
+
+#define PMIF_SPI_SWINF_NO 2
+
+#endif /* PMIC_WRAP_INIT_H */
diff --git a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h
index 4ba1f5c..3a30435 100644
--- a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h
+++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h
@@ -12,10 +12,14 @@
#include "platform_def.h"
/* external API */
+int32_t pmic_wrap_test(void);
int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
+int32_t pwrap_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift);
int32_t pwrap_write(uint32_t adr, uint32_t wdata);
+int32_t pwrap_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift);
-#define GET_WACS_FSM(x) ((x >> 1) & 0x7)
+#define GET_SWINF_INIT_DONE(x) ((x>>15) & 0x00000001)
+#define GET_WACS_FSM(x) ((x >> 1) & 0x7)
/* macro for SWINF_FSM */
#define SWINF_FSM_IDLE (0x00)
@@ -43,6 +47,11 @@
E_PWR_INIT_SIDLY_FAIL = 11,
E_PWR_RESET_TIMEOUT = 12,
E_PWR_TIMEOUT = 13,
+ E_PWR_INVALID_SWINF = 14,
+ E_PWR_INVALID_CMD = 15,
+ E_PWR_INVALID_PMIFID = 16,
+ E_PWR_INVALID_SLVID = 17,
+ E_PWR_INVALID_BYTECNT = 18,
E_PWR_INIT_RESET_SPI = 20,
E_PWR_INIT_SIDLY = 21,
E_PWR_INIT_REG_CLOCK = 22,
diff --git a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v3.c b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v3.c
new file mode 100644
index 0000000..4e9c321
--- /dev/null
+++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v3.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/spinlock.h>
+
+#include <mtk_mmap_pool.h>
+#include "pmic_wrap_init.h"
+#include "pmic_wrap_v3.h"
+
+static spinlock_t wrp_lock;
+
+static uint32_t pwrap_check_idle(uintptr_t wacs_register, uintptr_t wacs_vldclr_register,
+ uint32_t timeout_us)
+{
+ uint32_t reg_rdata = 0U, retry;
+
+ retry = (timeout_us + PWRAP_POLL_STEP_US) / PWRAP_POLL_STEP_US;
+ while (retry != 0) {
+ udelay(PWRAP_POLL_STEP_US);
+ reg_rdata = mmio_read_32(wacs_register);
+ /* if last read command timeout,clear vldclr bit
+ * read command state machine:FSM_REQ-->wfdle-->WFVLDCLR;
+ * write:FSM_REQ-->idle
+ */
+ switch (GET_WACS_FSM(reg_rdata)) {
+ case SWINF_FSM_WFVLDCLR:
+ mmio_write_32(wacs_vldclr_register, 0x1);
+ INFO("WACS_FSM = SWINF_FSM_WFVLDCLR\n");
+ break;
+ case SWINF_FSM_WFDLE:
+ INFO("WACS_FSM = SWINF_FSM_WFDLE\n");
+ break;
+ case SWINF_FSM_REQ:
+ INFO("WACS_FSM = SWINF_FSM_REQ\n");
+ break;
+ case SWINF_FSM_IDLE:
+ goto done;
+ default:
+ break;
+ }
+ retry--;
+ }
+
+done:
+ if (retry == 0) {
+ /* timeout */
+ return E_PWR_WAIT_IDLE_TIMEOUT;
+ }
+
+ return 0U;
+}
+
+static uint32_t pwrap_check_vldclr(uintptr_t wacs_register, uint32_t timeout_us)
+{
+ uint32_t reg_rdata = 0U, retry;
+
+ retry = (timeout_us + PWRAP_POLL_STEP_US) / PWRAP_POLL_STEP_US;
+ while (retry != 0) {
+ udelay(PWRAP_POLL_STEP_US);
+ reg_rdata = mmio_read_32(wacs_register);
+ if (GET_WACS_FSM(reg_rdata) == SWINF_FSM_WFVLDCLR) {
+ break;
+ }
+ retry--;
+ }
+
+ if (retry == 0) {
+ /* timeout */
+ return E_PWR_WAIT_IDLE_TIMEOUT;
+ }
+
+ return 0U;
+}
+
+static int32_t pwrap_swinf_acc(uint32_t swinf_no, uint32_t cmd, uint32_t write,
+ uint32_t pmifid, uint32_t slvid, uint32_t addr,
+ uint32_t bytecnt, uint32_t wdata, uint32_t *rdata)
+{
+ uint32_t reg_rdata = 0x0;
+ int32_t ret = 0x0;
+
+ /* Check argument validation */
+ if ((swinf_no & ~(0x3)) != 0)
+ return -E_PWR_INVALID_SWINF;
+ if ((cmd & ~(0x3)) != 0)
+ return -E_PWR_INVALID_CMD;
+ if ((write & ~(0x1)) != 0)
+ return -E_PWR_INVALID_RW;
+ if ((pmifid & ~(0x1)) != 0)
+ return -E_PWR_INVALID_PMIFID;
+ if ((slvid & ~(0xf)) != 0)
+ return -E_PWR_INVALID_SLVID;
+ if ((addr & ~(0xffff)) != 0)
+ return -E_PWR_INVALID_ADDR;
+ if ((bytecnt & ~(0x1)) != 0)
+ return -E_PWR_INVALID_BYTECNT;
+ if ((wdata & ~(0xffff)) != 0)
+ return -E_PWR_INVALID_WDAT;
+
+ spin_lock(&wrp_lock);
+ /* Check whether INIT_DONE is set */
+ if (pmifid == 0)
+ reg_rdata = mmio_read_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].sta));
+
+ if (GET_SWINF_INIT_DONE(reg_rdata) != 0x1) {
+ ERROR("[PWRAP] init not finish\n");
+ ret = -E_PWR_NOT_INIT_DONE;
+ goto end;
+ }
+
+ /* Wait for Software Interface FSM state to be IDLE */
+ ret = pwrap_check_idle((uintptr_t)(&mtk_pwrap->wacs[swinf_no].sta),
+ (uintptr_t)(&mtk_pwrap->wacs[swinf_no].vldclr), TIMEOUT_WAIT_IDLE);
+ if (ret != 0) {
+ ERROR("[PWRAP] fsm_idle fail\n");
+ goto end;
+ }
+
+ /* Set the write data */
+ if (write == 1) {
+ if (pmifid == 0)
+ mmio_write_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].wdata), wdata);
+ }
+
+ /* Send the command */
+ if (pmifid == 0)
+ mmio_write_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].cmd),
+ (cmd << 30) | (write << 29) | (slvid << 24) | (bytecnt << 16) | addr);
+
+ if (write == 0) {
+ if (rdata == NULL) {
+ ERROR("[PWRAP] rdata null\n");
+ ret = -E_PWR_INVALID_ARG;
+ goto end;
+ }
+
+ /* Wait for Software Interface FSM to be WFVLDCLR */
+ /* read the data and clear the valid flag */
+ ret = pwrap_check_vldclr((uintptr_t)(&mtk_pwrap->wacs[swinf_no].sta), TIMEOUT_READ);
+ if (ret != 0) {
+ ERROR("[PWRAP] fsm_vldclr fail\n");
+ goto end;
+ }
+
+ if (pmifid == 0) {
+ *rdata = mmio_read_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].rdata));
+ mmio_write_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].vldclr), 0x1);
+ }
+ }
+
+end:
+ spin_unlock(&wrp_lock);
+ if (ret < 0)
+ ERROR("%s fail, ret=%d\n", __func__, ret);
+ return ret;
+}
+
+/* external API for pmic_wrap user */
+
+int32_t pwrap_read(uint32_t adr, uint32_t *rdata)
+{
+ return pwrap_swinf_acc(PMIF_SPI_SWINF_NO, DEFAULT_CMD, 0, PMIF_SPI_PMIFID,
+ DEFAULT_SLVID, adr, DEFAULT_BYTECNT, 0x0, rdata);
+}
+
+int32_t pwrap_write(uint32_t adr, uint32_t wdata)
+{
+ return pwrap_swinf_acc(PMIF_SPI_SWINF_NO, DEFAULT_CMD, 1, PMIF_SPI_PMIFID,
+ DEFAULT_SLVID, adr, DEFAULT_BYTECNT, wdata, 0x0);
+}
+
+int32_t pwrap_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift)
+{
+ uint32_t rdata;
+ int32_t ret;
+
+ if (!val)
+ return -E_PWR_INVALID_ARG;
+ ret = pwrap_read(reg, &rdata);
+ if (ret == 0x0)
+ *val = (rdata >> shift) & mask;
+
+ return ret;
+}
+
+int32_t pwrap_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift)
+{
+ uint32_t data;
+ int32_t ret;
+
+ ret = pwrap_read(reg, &data);
+ if (ret != 0)
+ return ret;
+
+ data = data & ~(mask << shift);
+ data |= (val << shift);
+ ret = pwrap_write(reg, data);
+
+ return ret;
+}
+
+#if PWRAP_DEBUG
+static int32_t pwrap_read_test(void)
+{
+ uint32_t rdata = 0;
+ int32_t ret;
+
+ ret = pwrap_read(DEW_READ_TEST, &rdata);
+ if (rdata != DEFAULT_VALUE_READ_TEST) {
+ ERROR("[PWRAP] Read fail,rdata=0x%x,exp=0x5aa5,ret=0x%x\n", rdata, ret);
+ return -E_PWR_READ_TEST_FAIL;
+ }
+ INFO("[PWRAP] Read Test pass,ret=%x\n", ret);
+ return 0;
+}
+
+static int32_t pwrap_write_test(void)
+{
+ uint32_t rdata = 0;
+ int32_t ret;
+ int32_t ret1;
+
+ ret = pwrap_write(DEW_WRITE_TEST, PWRAP_WRITE_TEST_VALUE);
+ ret1 = pwrap_read(DEW_WRITE_TEST, &rdata);
+ if ((rdata != PWRAP_WRITE_TEST_VALUE) || (ret != 0) || (ret1 != 0)) {
+ ERROR("[PWRAP] Write fail,rdata=0x%x,exp=0xa55a,ret=0x%x,ret1=0x%x\n",
+ rdata, ret, ret1);
+ return -E_PWR_WRITE_TEST_FAIL;
+ }
+ INFO("[PWRAP] Write Test pass\n");
+ return 0;
+}
+
+int32_t pmic_wrap_test(void)
+{
+ int32_t ret;
+
+ INFO("[PWRAP] Read/Write Test start\n");
+
+ ret = pwrap_read_test();
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = pwrap_write_test();
+ if (ret != 0) {
+ return ret;
+ }
+ INFO("[PWRAP] Read/Write Test done\n");
+
+ return 0;
+}
+#endif
diff --git a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_v3.h b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_v3.h
new file mode 100644
index 0000000..075c2d5
--- /dev/null
+++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_v3.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_WRAP_V3_H
+#define PMIC_WRAP_V3_H
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <drivers/console.h>
+
+#define PMIF_REG_RANGE (0x774)
+#define PMICSPI_MST_REG_RANGE (0x80)
+#define DEFAULT_CMD 0
+#define DEFAULT_SLVID 0
+#define DEFAULT_BYTECNT 0
+#define PMIF_SPI_PMIFID 0
+/* #define PWRAP_DEBUG 1 */
+
+#if PWRAP_DEBUG
+#define PWRAP_LOG(fmts, args...) do {\
+ console_init(gteearg.atf_log_port, UART_CLOCK, UART_BAUDRATE);\
+ INFO("[%s:%d] -" fmts, __func__, __LINE__, ##args);\
+ console_uninit();\
+ } while (0)
+#endif
+
+/**********************************************************/
+#define DEFAULT_VALUE_READ_TEST (0x5aa5)
+#define PWRAP_WRITE_TEST_VALUE (0xa55a)
+#define PWRAP_POLL_STEP_US (10)
+
+/* timeout setting */
+enum {
+ TIMEOUT_RESET = 50, /* us */
+ TIMEOUT_READ = 50, /* us */
+ TIMEOUT_WAIT_IDLE = 50 /* us */
+};
+
+#endif /* PMIC_WRAP_V3_H */
diff --git a/plat/mediatek/drivers/pmic_wrap/rules.mk b/plat/mediatek/drivers/pmic_wrap/rules.mk
index 9ba44a6..662c7e4 100644
--- a/plat/mediatek/drivers/pmic_wrap/rules.mk
+++ b/plat/mediatek/drivers/pmic_wrap/rules.mk
@@ -10,6 +10,8 @@
ifeq (${USE_PMIC_WRAP_INIT_V2}, 1)
LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init_v2.c
+else ifeq (${USE_PMIC_WRAP_INIT_V3}, 1)
+LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init_v3.c
else
LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init.c
endif
diff --git a/plat/mediatek/drivers/spmi/mt8189/platform_pmif_spmi.c b/plat/mediatek/drivers/spmi/mt8189/platform_pmif_spmi.c
new file mode 100644
index 0000000..417f779
--- /dev/null
+++ b/plat/mediatek/drivers/spmi/mt8189/platform_pmif_spmi.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+#include <drivers/spmi/pmif_common.h>
+#include <drivers/spmi/pmif_v1/pmif.h>
+#include <drivers/spmi/spmi_common.h>
+#include <drivers/spmi/spmi_sw.h>
+#include <drivers/spmi_api.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <mtk_mmap_pool.h>
+
+#define SPMI_GROUP_ID 0xB
+#define SPMI_DEBUG 0
+
+static uint16_t mt6xxx_regs[] = {
+ [PMIF_INIT_DONE] = 0x0000,
+ [PMIF_INF_EN] = 0x0024,
+ [PMIF_ARB_EN] = 0x0150,
+ [PMIF_IRQ_EVENT_EN_0] = 0x0420,
+ [PMIF_IRQ_FLAG_0] = 0x0428,
+ [PMIF_IRQ_CLR_0] = 0x042C,
+ [PMIF_IRQ_EVENT_EN_2] = 0x0440,
+ [PMIF_IRQ_FLAG_2] = 0x0448,
+ [PMIF_IRQ_CLR_2] = 0x044C,
+ [PMIF_WDT_CTRL] = 0x0470,
+ [PMIF_WDT_EVENT_EN_1] = 0x047C,
+ [PMIF_WDT_FLAG_1] = 0x0480,
+ [PMIF_SWINF_2_ACC] = 0x0880,
+ [PMIF_SWINF_2_WDATA_31_0] = 0x0884,
+ [PMIF_SWINF_2_WDATA_63_32] = 0x0888,
+ [PMIF_SWINF_2_RDATA_31_0] = 0x0894,
+ [PMIF_SWINF_2_RDATA_63_32] = 0x0898,
+ [PMIF_SWINF_2_VLD_CLR] = 0x08A4,
+ [PMIF_SWINF_2_STA] = 0x08A8,
+ [PMIF_SWINF_3_ACC] = 0x08C0,
+ [PMIF_SWINF_3_WDATA_31_0] = 0x08C4,
+ [PMIF_SWINF_3_WDATA_63_32] = 0x08C8,
+ [PMIF_SWINF_3_RDATA_31_0] = 0x08D4,
+ [PMIF_SWINF_3_RDATA_63_32] = 0x08D8,
+ [PMIF_SWINF_3_VLD_CLR] = 0x08E4,
+ [PMIF_SWINF_3_STA] = 0x08E8,
+ /* hw mpu */
+ [PMIF_PMIC_ALL_RGN_EN_1] = 0x09B0,
+ [PMIF_PMIC_ALL_RGN_EN_2] = 0x0D30,
+ [PMIF_PMIC_ALL_RGN_0_START] = 0x09B4,
+ [PMIF_PMIC_ALL_RGN_0_END] = 0x09B8,
+ [PMIF_PMIC_ALL_RGN_1_START] = 0x09BC,
+ [PMIF_PMIC_ALL_RGN_1_END] = 0x09C0,
+ [PMIF_PMIC_ALL_RGN_2_START] = 0x09C4,
+ [PMIF_PMIC_ALL_RGN_2_END] = 0x09C8,
+ [PMIF_PMIC_ALL_RGN_3_START] = 0x09CC,
+ [PMIF_PMIC_ALL_RGN_3_END] = 0x09D0,
+ [PMIF_PMIC_ALL_RGN_31_START] = 0x0D34,
+ [PMIF_PMIC_ALL_RGN_31_END] = 0x0D38,
+ [PMIF_PMIC_ALL_INVLD_SLVID] = 0x0AAC,
+ [PMIF_PMIC_ALL_RGN_0_PER0] = 0x0AB0,
+ [PMIF_PMIC_ALL_RGN_0_PER1] = 0x0AB4,
+ [PMIF_PMIC_ALL_RGN_1_PER0] = 0x0AB8,
+ [PMIF_PMIC_ALL_RGN_2_PER0] = 0x0AC0,
+ [PMIF_PMIC_ALL_RGN_3_PER0] = 0x0AC8,
+ [PMIF_PMIC_ALL_RGN_31_PER0] = 0x0E34,
+ [PMIF_PMIC_ALL_RGN_31_PER1] = 0x0E38,
+ [PMIF_PMIC_ALL_RGN_OTHERS_PER0] = 0x0BA8,
+ [PMIF_PMIC_ALL_RGN_OTHERS_PER1] = 0x0BAC,
+};
+
+static uint16_t mt6xxx_spmi_regs[] = {
+ [SPMI_OP_ST_CTRL] = 0x0000,
+ [SPMI_GRP_ID_EN] = 0x0004,
+ [SPMI_OP_ST_STA] = 0x0008,
+ [SPMI_MST_SAMPL] = 0x000c,
+ [SPMI_MST_REQ_EN] = 0x0010,
+ [SPMI_RCS_CTRL] = 0x0014,
+ [SPMI_SLV_3_0_EINT] = 0x0020,
+ [SPMI_SLV_7_4_EINT] = 0x0024,
+ [SPMI_SLV_B_8_EINT] = 0x0028,
+ [SPMI_SLV_F_C_EINT] = 0x002c,
+ [SPMI_REC_CTRL] = 0x0040,
+ [SPMI_REC0] = 0x0044,
+ [SPMI_REC1] = 0x0048,
+ [SPMI_REC2] = 0x004c,
+ [SPMI_REC3] = 0x0050,
+ [SPMI_REC4] = 0x0054,
+ [SPMI_REC_CMD_DEC] = 0x005c,
+ [SPMI_DEC_DBG] = 0x00f8,
+ [SPMI_MST_DBG] = 0x00fc,
+};
+
+struct pmif pmif_spmi_arb[] = {
+ {
+ .regs = mt6xxx_regs,
+ .spmimst_regs = mt6xxx_spmi_regs,
+ .mstid = SPMI_MASTER_0,
+ .read_cmd = pmif_spmi_read_cmd,
+ .write_cmd = pmif_spmi_write_cmd,
+ },
+ {
+ .regs = mt6xxx_regs,
+ .spmimst_regs = mt6xxx_spmi_regs,
+ .mstid = SPMI_MASTER_1,
+ .read_cmd = pmif_spmi_read_cmd,
+ .write_cmd = pmif_spmi_write_cmd,
+ },
+ {
+ .base = (unsigned int *)PMIF_SPMI_P_BASE,
+ .regs = mt6xxx_regs,
+ .spmimst_base = (unsigned int *)SPMI_MST_P_BASE,
+ .spmimst_regs = mt6xxx_spmi_regs,
+ .mstid = SPMI_MASTER_P_1,
+ .read_cmd = pmif_spmi_read_cmd,
+ .write_cmd = pmif_spmi_write_cmd,
+ },
+};
+
+static struct spmi_device spmi_dev[] = {
+ {
+ .slvid = SPMI_SLAVE_7, /* MT6319 */
+ .grpiden = 0x800,
+ .type = BUCK_CPU,
+ .type_id = BUCK_CPU_ID,
+ .mstid = SPMI_MASTER_P_1,/* spmi-p */
+ .hwcid_addr = 0x09,
+ .hwcid_val = 0x15,
+ .swcid_addr = 0x0B,
+ .swcid_val = 0x15,
+ .wpk_key_addr = 0x3A8,
+ .wpk_key_val = 0x6315,
+ .tma_key_addr = 0x39F,
+ .tma_key_val = 0x9CEA,
+ .pmif_arb = &pmif_spmi_arb[SPMI_MASTER_P_1],
+ },
+ {
+ .slvid = SPMI_SLAVE_8, /* MT6319 */
+ .grpiden = 0x800,
+ .type = BUCK_CPU,
+ .type_id = BUCK_CPU_ID,
+ .mstid = SPMI_MASTER_P_1,/* spmi-p */
+ .hwcid_addr = 0x09,
+ .hwcid_val = 0x15,
+ .swcid_addr = 0x0B,
+ .swcid_val = 0x15,
+ .wpk_key_addr = 0x3A8,
+ .wpk_key_val = 0x6315,
+ .tma_key_addr = 0x39F,
+ .tma_key_val = 0x9CEA,
+ .pmif_arb = &pmif_spmi_arb[SPMI_MASTER_P_1],
+ },
+};
+
+int platform_pmif_spmi_init(void)
+{
+/*
+ * The MT8189 chipset comes in two variants: MT8189G and MT8189H. The
+ * MT8189G variant uses a single PMIC IC (MT6319), whereas the MT8189H
+ * variant uses two PMIC ICs. To ensure driver compatibility, we utilize
+ * the CPU ID and segment ID to accurately determine the required number
+ * of SPMIF instances.
+ */
+ if (mmio_read_32((uintptr_t)CHIP_ID_REG) == MTK_CPU_ID_MT8189 &&
+ mmio_read_32((uintptr_t)CPU_SEG_ID_REG) == MTK_CPU_SEG_ID_MT8189G)
+ spmi_device_register(spmi_dev, 1);
+ else
+ spmi_device_register(spmi_dev, ARRAY_SIZE(spmi_dev));
+
+ return 0;
+}
+MTK_ARCH_INIT(platform_pmif_spmi_init);
diff --git a/plat/mediatek/include/drivers/pmic/mt6319_lowpower_reg.h b/plat/mediatek/include/drivers/pmic/mt6319_lowpower_reg.h
new file mode 100644
index 0000000..71a2d2b
--- /dev/null
+++ b/plat/mediatek/include/drivers/pmic/mt6319_lowpower_reg.h
@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT6319_LOWPOWER_REG_H
+#define MT6319_LOWPOWER_REG_H
+
+#define MT6319_RG_LDO_VDIG18_SW_OP_EN_ADDR 0x0196
+#define MT6319_RG_LDO_VDIG18_HW_OP_EN_ADDR 0x0196
+#define MT6319_RG_VDIG18_PWROFF_OP_EN_ADDR 0x0197
+#define MT6319_RG_BUCK_VBUCK1_HW0_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW1_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW2_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW3_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW4_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW5_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW6_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW7_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW8_OP_EN_ADDR 0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW9_OP_EN_ADDR 0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW10_OP_EN_ADDR 0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW11_OP_EN_ADDR 0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW12_OP_EN_ADDR 0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW13_OP_EN_ADDR 0x1708
+#define MT6319_RG_BUCK_VBUCK1_SW_OP_EN_ADDR 0x1490
+#define MT6319_RG_BUCK_VBUCK1_HW0_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW1_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW2_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW3_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW4_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW5_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW6_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW7_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW8_OP_CFG_ADDR 0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW9_OP_CFG_ADDR 0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW10_OP_CFG_ADDR 0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW11_OP_CFG_ADDR 0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW12_OP_CFG_ADDR 0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW13_OP_CFG_ADDR 0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW0_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW1_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW2_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW3_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW4_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW5_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW6_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW7_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW8_OP_MODE_ADDR 0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW9_OP_MODE_ADDR 0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW10_OP_MODE_ADDR 0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW11_OP_MODE_ADDR 0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW12_OP_MODE_ADDR 0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW13_OP_MODE_ADDR 0x170e
+#define MT6319_RG_BUCK_VBUCK2_HW0_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW1_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW2_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW3_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW4_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW5_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW6_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW7_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW8_OP_EN_ADDR 0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW9_OP_EN_ADDR 0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW10_OP_EN_ADDR 0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW11_OP_EN_ADDR 0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW12_OP_EN_ADDR 0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW13_OP_EN_ADDR 0x1711
+#define MT6319_RG_BUCK_VBUCK2_SW_OP_EN_ADDR 0x1510
+#define MT6319_RG_BUCK_VBUCK2_HW0_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW1_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW2_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW3_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW4_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW5_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW6_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW7_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW8_OP_CFG_ADDR 0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW9_OP_CFG_ADDR 0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW10_OP_CFG_ADDR 0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW11_OP_CFG_ADDR 0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW12_OP_CFG_ADDR 0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW13_OP_CFG_ADDR 0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW0_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW1_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW2_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW3_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW4_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW5_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW6_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW7_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW8_OP_MODE_ADD 0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW9_OP_MODE_ADDR 0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW10_OP_MODE_ADDR 0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW11_OP_MODE_ADDR 0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW12_OP_MODE_ADDR 0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW13_OP_MODE_ADDR 0x1717
+#define MT6319_RG_BUCK_VBUCK3_HW0_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW1_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW2_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW3_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW4_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW5_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW6_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW7_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW8_OP_EN_ADDR 0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW9_OP_EN_ADDR 0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW10_OP_EN_ADDR 0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW11_OP_EN_ADDR 0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW12_OP_EN_ADDR 0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW13_OP_EN_ADDR 0x171a
+#define MT6319_RG_BUCK_VBUCK3_SW_OP_EN_ADDR 0x1590
+#define MT6319_RG_BUCK_VBUCK3_HW0_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW1_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW2_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW3_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW4_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW5_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW6_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW7_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW8_OP_CFG_ADDR 0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW9_OP_CFG_ADDR 0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW10_OP_CFG_ADDR 0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW11_OP_CFG_ADDR 0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW12_OP_CFG_ADDR 0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW13_OP_CFG_ADDR 0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW0_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW1_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW2_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW3_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW4_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW5_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW6_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW7_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW8_OP_MODE_ADDR 0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW9_OP_MODE_ADDR 0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW10_OP_MODE_ADDR 0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW11_OP_MODE_ADDR 0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW12_OP_MODE_ADDR 0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW13_OP_MODE_ADDR 0x1720
+#define MT6319_RG_BUCK_VBUCK4_HW0_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW1_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW2_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW3_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW4_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW5_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW6_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW7_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW8_OP_EN_ADDR 0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW9_OP_EN_ADDR 0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW10_OP_EN_ADDR 0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW11_OP_EN_ADDR 0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW12_OP_EN_ADDR 0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW13_OP_EN_ADDR 0x1723
+#define MT6319_RG_BUCK_VBUCK4_SW_OP_EN_ADDR 0x1610
+#define MT6319_RG_BUCK_VBUCK4_HW0_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW1_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW2_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW3_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW4_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW5_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW6_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW7_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW8_OP_CFG_ADDR 0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW9_OP_CFG_ADDR 0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW10_OP_CFG_ADDR 0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW11_OP_CFG_ADDR 0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW12_OP_CFG_ADDR 0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW13_OP_CFG_ADDR 0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW0_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW1_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW2_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW3_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW4_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW5_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW6_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW7_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW8_OP_MODE_ADDR 0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW9_OP_MODE_ADDR 0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW10_OP_MODE_ADDR 0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW11_OP_MODE_ADDR 0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW12_OP_MODE_ADDR 0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW13_OP_MODE_ADDR 0x1729
+
+#endif /* MT6319_LOWPOWER_REG_H */
diff --git a/plat/mediatek/include/drivers/pmic/mt6359p_lowpower_reg.h b/plat/mediatek/include/drivers/pmic/mt6359p_lowpower_reg.h
new file mode 100644
index 0000000..7e14f00
--- /dev/null
+++ b/plat/mediatek/include/drivers/pmic/mt6359p_lowpower_reg.h
@@ -0,0 +1,1593 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT6359P_LOWPOWER_REG_H
+#define MT6359P_LOWPOWER_REG_H
+
+#define MT6359P_RG_BUCK_VPU_VOSEL_SLEEP_ADDR 0x148e
+#define MT6359P_RG_BUCK_VPU_HW0_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW1_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW2_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW3_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW4_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW5_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW6_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW7_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW8_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW9_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW10_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW11_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW12_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW13_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW14_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_SW_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW0_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW1_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW2_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW3_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW4_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW5_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW6_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW7_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW8_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW9_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW10_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW11_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW12_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW13_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW14_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW0_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VPU_HW1_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VPU_HW2_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VPU_HW3_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VPU_HW4_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VPU_HW5_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VPU_HW6_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VPU_HW7_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VPU_HW8_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VPU_HW9_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VPU_HW10_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VPU_HW11_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VPU_HW12_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VPU_HW13_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VPU_HW14_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VCORE_VOSEL_SLEEP_ADDR 0x150e
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_SW_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VGPU11_VOSEL_SLEEP_ADDR 0x158e
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_SW_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VGPU12_VOSEL_SLEEP_ADDR 0x160e
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_SW_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VMODEM_VOSEL_SLEEP_ADDR 0x168e
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_SW_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VPROC1_VOSEL_SLEEP_ADDR 0x170e
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_SW_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VPROC2_VOSEL_SLEEP_ADDR 0x178e
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_SW_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VS1_VOSEL_SLEEP_ADDR 0x180e
+#define MT6359P_RG_BUCK_VS1_HW0_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW1_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW2_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW3_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW4_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW5_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW6_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW7_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW8_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW9_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW10_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW11_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW12_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW13_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW14_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_SW_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW0_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW1_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW2_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW3_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW4_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW5_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW6_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW7_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW8_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW9_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW10_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW11_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW12_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW13_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW14_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW0_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VS1_HW1_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VS1_HW2_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VS1_HW3_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VS1_HW4_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VS1_HW5_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VS1_HW6_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VS1_HW7_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VS1_HW8_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VS1_HW9_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VS1_HW10_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VS1_HW11_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VS1_HW12_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VS1_HW13_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VS1_HW14_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VS2_VOSEL_SLEEP_ADDR 0x188e
+#define MT6359P_RG_BUCK_VS2_HW0_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW1_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW2_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW3_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW4_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW5_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW6_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW7_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW8_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW9_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW10_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW11_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW12_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW13_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW14_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_SW_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW0_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW1_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW2_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW3_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW4_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW5_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW6_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW7_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW8_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW9_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW10_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW11_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW12_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW13_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW14_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW0_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VS2_HW1_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VS2_HW2_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VS2_HW3_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VS2_HW4_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VS2_HW5_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VS2_HW6_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VS2_HW7_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VS2_HW8_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VS2_HW9_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VS2_HW10_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VS2_HW11_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VS2_HW12_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VS2_HW13_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VS2_HW14_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_LDO_VFE28_OP_MODE_ADDR 0x1b8a
+#define MT6359P_RG_LDO_VFE28_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VFE28_HW0_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW1_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW2_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW3_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW4_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW5_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW6_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW7_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW8_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW9_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW10_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW11_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW12_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW13_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW14_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_SW_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW0_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW1_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW2_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW3_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW4_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW5_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW6_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW7_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW8_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW9_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW10_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW11_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW12_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW13_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW14_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_SW_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VXO22_OP_MODE_ADDR 0x1b9c
+#define MT6359P_RG_LDO_VXO22_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VXO22_HW0_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW1_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW2_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW3_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW4_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW5_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW6_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW7_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW8_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW9_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW10_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW11_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW12_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW13_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW14_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_SW_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW0_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW1_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW2_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW3_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW4_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW5_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW6_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW7_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW8_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW9_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW10_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW11_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW12_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW13_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW14_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_SW_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VRF18_OP_MODE_ADDR 0x1bae
+#define MT6359P_RG_LDO_VRF18_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VRF18_HW0_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW1_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW2_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW3_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW4_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW5_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW6_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW7_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW8_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW9_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW10_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW11_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW12_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW13_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW14_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_SW_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW0_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW1_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW2_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW3_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW4_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW5_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW6_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW7_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW8_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW9_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW10_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW11_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW12_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW13_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW14_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_SW_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF12_OP_MODE_ADDR 0x1bc0
+#define MT6359P_RG_LDO_VRF12_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VRF12_HW0_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW1_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW2_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW3_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW4_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW5_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW6_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW7_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW8_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW9_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW10_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW11_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW12_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW13_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW14_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_SW_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW0_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW1_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW2_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW3_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW4_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW5_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW6_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW7_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW8_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW9_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW10_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW11_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW12_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW13_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW14_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_SW_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VEFUSE_OP_MODE_ADDR 0x1bd2
+#define MT6359P_RG_LDO_VEFUSE_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VEFUSE_HW0_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW1_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW2_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW3_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW4_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW5_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW6_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW7_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW8_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW9_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW10_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW11_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW12_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW13_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW14_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_SW_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW0_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW1_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW2_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW3_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW4_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW5_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW6_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW7_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW8_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW9_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW10_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW11_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW12_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW13_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW14_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_SW_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VCN33_1_OP_MODE_ADDR 0x1be4
+#define MT6359P_RG_LDO_VCN33_1_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VCN33_1_HW0_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW1_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW2_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW3_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW4_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW5_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW6_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW7_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW8_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW9_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW10_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW11_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW12_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW13_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW14_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_SW_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW0_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW1_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW2_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW3_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW4_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW5_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW6_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW7_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW8_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW9_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW10_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW11_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW12_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW13_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW14_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_SW_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_2_OP_MODE_ADDR 0x1c0a
+#define MT6359P_RG_LDO_VCN33_2_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VCN33_2_HW0_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW1_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW2_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW3_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW4_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW5_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW6_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW7_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW8_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW9_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW10_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW11_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW12_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW13_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW14_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_SW_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW0_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW1_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW2_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW3_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW4_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW5_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW6_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW7_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW8_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW9_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW10_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW11_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW12_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW13_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW14_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_SW_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN13_OP_MODE_ADDR 0x1c1e
+#define MT6359P_RG_LDO_VCN13_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VCN13_HW0_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW1_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW2_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW3_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW4_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW5_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW6_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW7_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW8_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW9_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW10_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW11_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW12_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW13_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW14_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_SW_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW0_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW1_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW2_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW3_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW4_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW5_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW6_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW7_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW8_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW9_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW10_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW11_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW12_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW13_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW14_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_SW_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN18_OP_MODE_ADDR 0x1c30
+#define MT6359P_RG_LDO_VCN18_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VCN18_HW0_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW1_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW2_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW3_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW4_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW5_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW6_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW7_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW8_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW9_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW10_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW11_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW12_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW13_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW14_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_SW_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW0_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW1_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW2_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW3_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW4_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW5_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW6_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW7_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW8_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW9_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW10_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW11_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW12_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW13_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW14_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_SW_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VA09_OP_MODE_ADDR 0x1c42
+#define MT6359P_RG_LDO_VA09_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VA09_HW0_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW1_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW2_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW3_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW4_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW5_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW6_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW7_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW8_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW9_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW10_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW11_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW12_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW13_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW14_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_SW_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW0_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW1_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW2_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW3_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW4_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW5_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW6_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW7_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW8_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW9_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW10_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW11_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW12_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW13_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW14_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_SW_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VCAMIO_OP_MODE_ADDR 0x1c54
+#define MT6359P_RG_LDO_VCAMIO_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VCAMIO_HW0_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW1_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW2_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW3_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW4_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW5_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW6_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW7_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW8_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW9_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW10_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW11_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW12_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW13_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW14_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_SW_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW0_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW1_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW2_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW3_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW4_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW5_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW6_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW7_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW8_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW9_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW10_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW11_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW12_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW13_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW14_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_SW_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VA12_OP_MODE_ADDR 0x1c66
+#define MT6359P_RG_LDO_VA12_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VA12_HW0_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW1_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW2_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW3_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW4_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW5_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW6_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW7_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW8_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW9_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW10_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW11_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW12_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW13_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW14_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_SW_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW0_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW1_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW2_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW3_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW4_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW5_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW6_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW7_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW8_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW9_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW10_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW11_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW12_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW13_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW14_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_SW_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VAUX18_OP_MODE_ADDR 0x1c8a
+#define MT6359P_RG_LDO_VAUX18_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VAUX18_HW0_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW1_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW2_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW3_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW4_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW5_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW6_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW7_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW8_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW9_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW10_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW11_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW12_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW13_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW14_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_SW_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW0_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW1_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW2_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW3_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW4_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW5_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW6_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW7_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW8_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW9_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW10_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW11_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW12_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW13_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW14_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_SW_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUD18_OP_MODE_ADDR 0x1c9c
+#define MT6359P_RG_LDO_VAUD18_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VAUD18_HW0_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW1_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW2_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW3_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW4_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW5_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW6_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW7_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW8_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW9_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW10_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW11_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW12_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW13_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW14_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_SW_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW0_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW1_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW2_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW3_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW4_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW5_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW6_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW7_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW8_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW9_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW10_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW11_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW12_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW13_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW14_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_SW_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VIO18_OP_MODE_ADDR 0x1cae
+#define MT6359P_RG_LDO_VIO18_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VIO18_HW0_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW1_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW2_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW3_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW4_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW5_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW6_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW7_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW8_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW9_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW10_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW11_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW12_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW13_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW14_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_SW_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW0_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW1_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW2_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW3_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW4_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW5_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW6_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW7_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW8_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW9_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW10_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW11_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW12_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW13_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW14_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_SW_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VEMC_OP_MODE_ADDR 0x1cc0
+#define MT6359P_RG_LDO_VEMC_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VEMC_HW0_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW1_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW2_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW3_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW4_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW5_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW6_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW7_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW8_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW9_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW10_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW11_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW12_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW13_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW14_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_SW_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW0_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW1_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW2_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW3_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW4_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW5_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW6_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW7_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW8_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW9_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW10_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW11_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW12_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW13_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW14_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_SW_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VSIM1_OP_MODE_ADDR 0x1cd2
+#define MT6359P_RG_LDO_VSIM1_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VSIM1_HW0_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW1_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW2_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW3_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW4_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW5_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW6_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW7_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW8_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW9_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW10_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW11_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW12_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW13_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW14_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_SW_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW0_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW1_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW2_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW3_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW4_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW5_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW6_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW7_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW8_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW9_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW10_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW11_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW12_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW13_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW14_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_SW_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM2_OP_MODE_ADDR 0x1ce4
+#define MT6359P_RG_LDO_VSIM2_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VSIM2_HW0_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW1_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW2_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW3_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW4_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW5_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW6_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW7_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW8_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW9_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW10_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW11_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW12_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW13_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW14_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_SW_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW0_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW1_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW2_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW3_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW4_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW5_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW6_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW7_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW8_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW9_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW10_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW11_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW12_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW13_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW14_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_SW_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VUSB_OP_MODE_ADDR 0x1d0a
+#define MT6359P_RG_LDO_VUSB_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VUSB_HW0_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW1_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW2_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW3_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW4_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW5_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW6_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW7_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW8_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW9_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW10_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW11_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW12_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW13_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW14_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_SW_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW0_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW1_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW2_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW3_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW4_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW5_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW6_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW7_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW8_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW9_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW10_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW11_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW12_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW13_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW14_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_SW_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VRFCK_OP_MODE_ADDR 0x1d1e
+#define MT6359P_RG_LDO_VRFCK_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VRFCK_HW0_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW1_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW2_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW3_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW4_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW5_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW6_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW7_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW8_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW9_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW10_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW11_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW12_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW13_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW14_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_SW_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW0_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW1_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW2_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW3_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW4_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW5_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW6_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW7_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW8_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW9_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW10_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW11_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW12_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW13_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW14_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_SW_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VBBCK_OP_MODE_ADDR 0x1d30
+#define MT6359P_RG_LDO_VBBCK_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VBBCK_HW0_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW1_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW2_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW3_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW4_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW5_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW6_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW7_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW8_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW9_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW10_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW11_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW12_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW13_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW14_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_SW_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW0_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW1_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW2_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW3_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW4_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW5_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW6_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW7_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW8_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW9_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW10_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW11_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW12_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW13_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW14_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_SW_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBIF28_OP_MODE_ADDR 0x1d42
+#define MT6359P_RG_LDO_VBIF28_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VBIF28_HW0_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW1_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW2_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW3_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW4_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW5_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW6_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW7_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW8_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW9_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW10_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW11_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW12_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW13_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW14_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_SW_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW0_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW1_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW2_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW3_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW4_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW5_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW6_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW7_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW8_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW9_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW10_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW11_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW12_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW13_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW14_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_SW_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VIBR_OP_MODE_ADDR 0x1d54
+#define MT6359P_RG_LDO_VIBR_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VIBR_HW0_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW1_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW2_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW3_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW4_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW5_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW6_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW7_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW8_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW9_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW10_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW11_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW12_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW13_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW14_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_SW_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW0_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW1_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW2_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW3_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW4_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW5_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW6_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW7_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW8_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW9_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW10_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW11_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW12_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW13_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW14_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_SW_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIO28_OP_MODE_ADDR 0x1d66
+#define MT6359P_RG_LDO_VIO28_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VIO28_HW0_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW1_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW2_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW3_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW4_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW5_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW6_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW7_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW8_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW9_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW10_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW11_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW12_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW13_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW14_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_SW_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW0_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW1_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW2_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW3_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW4_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW5_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW6_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW7_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW8_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW9_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW10_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW11_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW12_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW13_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW14_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_SW_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VM18_OP_MODE_ADDR 0x1d8a
+#define MT6359P_RG_LDO_VM18_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VM18_HW0_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW1_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW2_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW3_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW4_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW5_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW6_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW7_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW8_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW9_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW10_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW11_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW12_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW13_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW14_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_SW_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW0_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW1_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW2_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW3_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW4_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW5_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW6_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW7_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW8_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW9_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW10_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW11_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW12_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW13_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW14_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_SW_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VUFS_OP_MODE_ADDR 0x1d9c
+#define MT6359P_RG_LDO_VUFS_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VUFS_HW0_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW1_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW2_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW3_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW4_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW5_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW6_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW7_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW8_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW9_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW10_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW11_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW12_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW13_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW14_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_SW_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW0_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW1_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW2_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW3_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW4_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW5_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW6_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW7_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW8_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW9_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW10_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW11_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW12_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW13_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW14_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_SW_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VSRAM_PROC1_OP_MODE_ADDR 0x1e8a
+#define MT6359P_RG_LDO_VSRAM_PROC1_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_SLEEP_ADDR 0x1e8e
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW0_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW1_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW2_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW3_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW4_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW5_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW6_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW7_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW8_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW9_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW10_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW11_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW12_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW13_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW14_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_SW_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW0_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW1_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW2_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW3_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW4_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW5_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW6_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW7_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW8_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW9_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW10_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW11_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW12_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW13_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW14_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_SW_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC2_OP_MODE_ADDR 0x1eaa
+#define MT6359P_RG_LDO_VSRAM_PROC2_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_SLEEP_ADDR 0x1eae
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW0_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW1_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW2_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW3_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW4_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW5_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW6_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW7_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW8_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW9_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW10_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW11_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW12_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW13_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW14_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_SW_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW0_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW1_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW2_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW3_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW4_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW5_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW6_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW7_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW8_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW9_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW10_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW11_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW12_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW13_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW14_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_SW_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_OTHERS_OP_MODE_ADDR 0x1f0a
+#define MT6359P_RG_LDO_VSRAM_OTHERS_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP_ADDR 0x1f0e
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW0_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW1_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW2_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW3_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW4_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW5_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW6_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW7_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW8_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW9_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW10_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW11_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW12_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW13_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW14_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_SW_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW0_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW1_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW2_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW3_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW4_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW5_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW6_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW7_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW8_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW9_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW10_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW11_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW12_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW13_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW14_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_SW_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP_ADDR 0x1f28
+#define MT6359P_RG_LDO_VSRAM_MD_OP_MODE_ADDR 0x1f30
+#define MT6359P_RG_LDO_VSRAM_MD_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VSRAM_MD_VOSEL_SLEEP_ADDR 0x1f34
+#define MT6359P_RG_LDO_VSRAM_MD_HW0_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW1_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW2_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW3_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW4_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW5_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW6_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW7_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW8_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW9_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW10_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW11_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW12_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW13_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW14_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_SW_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW0_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW1_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW2_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW3_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW4_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW5_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW6_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW7_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW8_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW9_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW10_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW11_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW12_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW13_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW14_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_SW_OP_CFG_ADDR 0x1f42
+
+#endif /* MT6359P_LOWPOWER_REG_H */
diff --git a/plat/mediatek/include/drivers/pmic/mt6359p_set_lowpower.h b/plat/mediatek/include/drivers/pmic/mt6359p_set_lowpower.h
new file mode 100644
index 0000000..60b49bf
--- /dev/null
+++ b/plat/mediatek/include/drivers/pmic/mt6359p_set_lowpower.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT6359P_SET_LOWPOWER_H
+#define MT6359P_SET_LOWPOWER_H
+
+#include <stdint.h>
+
+#include "mt6359p_lowpower_reg.h"
+#include <pmic_wrap_init_common.h>
+
+#define OP_MODE_MU (0)
+#define OP_MODE_LP (1)
+
+#define HW_OFF (0)
+#define HW_ON (0)
+#define HW_LP (1)
+
+enum {
+ HW0 = 0,
+ HW1,
+ HW2,
+ HW3,
+ HW4,
+ HW5,
+ HW6,
+ HW7,
+ HW8,
+ HW9,
+ HW10,
+ HW11,
+ HW12,
+ HW13,
+ HW14,
+};
+
+#define PMIC_BUCK_SET_LP(_chip, _name, _user, _en, _mode, _cfg) \
+{ \
+ pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_CFG_ADDR, \
+ 1 << _user, \
+ (_cfg & 0x1) ? 1 << _user : 0); \
+ pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_MODE_ADDR, \
+ 1 << _user, \
+ _mode ? 1 << _user : 0); \
+ pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_EN_ADDR, \
+ 1 << _user, \
+ _en ? 1 << _user : 0); \
+}
+
+#define PMIC_LDO_SET_LP(_chip, _name, _user, _en, _mode, _cfg) \
+{ \
+ if (_user <= HW2) { \
+ pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_OP_MODE_ADDR, \
+ 1 << (_user + _chip##_RG_LDO_##_name##_OP_MODE_SHIFT), \
+ _mode ? 1 << (_user + _chip##_RG_LDO_##_name##_OP_MODE_SHIFT) : 0); \
+ } \
+ pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_##_user##_OP_CFG_ADDR, \
+ 1 << _user, \
+ (_cfg & 0x1) ? 1 << _user : 0); \
+ pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_##_user##_OP_EN_ADDR, \
+ 1 << _user, \
+ _en ? 1 << _user : 0); \
+}
+
+static inline int pmic_wrap_update_bits(uint32_t reg, uint32_t mask, uint32_t val)
+{
+ uint32_t orig = 0;
+ int ret = 0;
+
+ ret = pwrap_read(reg, &orig);
+ if (ret < 0)
+ return ret;
+
+ orig &= ~mask;
+ orig |= val & mask;
+
+ ret = pwrap_write(reg, orig);
+ return ret;
+}
+
+#endif /* MT6359P_MT6359P_SET_LOWPOWER_H */
diff --git a/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h b/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h
index f79612d..4f0517f 100644
--- a/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h
+++ b/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h
@@ -12,6 +12,7 @@
#include <drivers/spmi_api.h>
#include "mt6316_lowpower_reg.h"
+#include "mt6319_lowpower_reg.h"
#include "mt6363_lowpower_reg.h"
#include "mt6373_lowpower_reg.h"
diff --git a/plat/mediatek/mt8189/include/platform_def.h b/plat/mediatek/mt8189/include/platform_def.h
index 067ebcc..54bf5ba 100644
--- a/plat/mediatek/mt8189/include/platform_def.h
+++ b/plat/mediatek/mt8189/include/platform_def.h
@@ -143,4 +143,40 @@
******************************************************************************/
#define SYSTIMER_BASE (IO_PHYS + 0x0CC10000)
+/*******************************************************************************
+ * SPMI related definitions
+ ******************************************************************************/
+#define SPMI_MST_P_BASE (IO_PHYS + 0x0CC00000)
+#define PMIF_SPMI_P_BASE (IO_PHYS + 0x0CC06000)
+#define SPMI_MST_P_SIZE (0x1000)
+
+/*******************************************************************************
+ * PWRAP related definitions
+ ******************************************************************************/
+#define PMICSPI_MST_BASE (IO_PHYS + 0x0c013000)
+#define PMICSPI_MST_SIZE (0x1000)
+#define PMIC_WRAP_BASE (IO_PHYS + 0x0CC04000)
+#define PMIF_SPI_BASE (0x1CC04000)
+#define PWRAP_REG_BASE (0x1C013000)
+#define PWRAP_WRAP_EN (PWRAP_REG_BASE + 0x14)
+
+/*******************************************************************************
+ * PMIC regsister related definitions
+ ******************************************************************************/
+#define PMIC_REG_BASE (0x0000)
+#define PWRAP_SIZE (0x1000)
+#define DEW_READ_TEST (PMIC_REG_BASE + 0x040e)
+#define DEW_WRITE_TEST (PMIC_REG_BASE + 0x0410)
+
+/*******************************************************************************
+ * Differentiate between 3G and 2.6G-related definitions
+ ******************************************************************************/
+#define EFUSEC_BASE (IO_PHYS + 0x01F10000)
+#define CHIP_ID_REG (EFUSEC_BASE + 0x7A0)
+#define CPU_SEG_ID_REG (EFUSEC_BASE + 0x7E0)
+
+#define MTK_CPU_ID_MT8189 0x81890000
+#define MTK_CPU_SEG_ID_MT8189G 0x20
+#define MTK_CPU_SEG_ID_MT8189H 0x21
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/mediatek/mt8189/plat_config.mk b/plat/mediatek/mt8189/plat_config.mk
index f06555b..6293052 100644
--- a/plat/mediatek/mt8189/plat_config.mk
+++ b/plat/mediatek/mt8189/plat_config.mk
@@ -23,6 +23,14 @@
PLAT_EXTRA_RODATA_INCLUDES := 1
CONFIG_MTK_DISABLE_CACHE_AS_RAM := $(COREBOOT)
+CONFIG_MTK_PMIC := y
+CONFIG_MTK_PMIC_LOWPOWER := y
+CONFIG_MTK_PMIC_SHUTDOWN_CFG := y
+CONFIG_MTK_PMIC_SHUTDOWN_V2 := y
+CONFIG_MTK_SPMI := y
+PMIC_CHIP := mt6359p
+USE_PMIC_WRAP_INIT_V3 := 1
+
# Configs for A78 and A55
CTX_INCLUDE_AARCH32_REGS := 0
ERRATA_A55_1530923 := 1
diff --git a/plat/mediatek/mt8189/platform.mk b/plat/mediatek/mt8189/platform.mk
index c0c0427..381071a 100644
--- a/plat/mediatek/mt8189/platform.mk
+++ b/plat/mediatek/mt8189/platform.mk
@@ -31,7 +31,10 @@
MODULES-y += $(MTK_PLAT)/drivers/gic600
MODULES-y += $(MTK_PLAT)/drivers/iommu
MODULES-y += $(MTK_PLAT)/drivers/mcusys
+MODULES-y += $(MTK_PLAT)/drivers/pmic_wrap
MODULES-y += $(MTK_PLAT)/drivers/timer
+MODULES-$(CONFIG_MTK_PMIC) += $(MTK_PLAT)/drivers/pmic
+MODULES-$(CONFIG_MTK_SPMI) += $(MTK_PLAT)/drivers/spmi
PLAT_BL_COMMON_SOURCES := common/desc_image_load.c \
drivers/ti/uart/aarch64/16550_console.S \
diff --git a/plat/mediatek/mt8195/plat_sip_calls.c b/plat/mediatek/mt8195/plat_sip_calls.c
index 2debeff..faa0ba5 100644
--- a/plat/mediatek/mt8195/plat_sip_calls.c
+++ b/plat/mediatek/mt8195/plat_sip_calls.c
@@ -31,7 +31,7 @@
case MTK_SIP_TEE_MPU_PERM_SET_AARCH64:
case MTK_SIP_TEE_MPU_PERM_SET_AARCH32:
ret = emi_mpu_sip_handler(x1, x2, x3);
- SMC_RET2(handle, ret, ret_val);
+ SMC_RET1(handle, ret);
break;
case MTK_SIP_DP_CONTROL_AARCH32:
case MTK_SIP_DP_CONTROL_AARCH64:
diff --git a/plat/mediatek/mt8196/plat_config.mk b/plat/mediatek/mt8196/plat_config.mk
index e0dd87e..a7f17e1 100644
--- a/plat/mediatek/mt8196/plat_config.mk
+++ b/plat/mediatek/mt8196/plat_config.mk
@@ -59,6 +59,7 @@
CONFIG_MTK_PMIC := y
CONFIG_MTK_PMIC_LOWPOWER := y
CONFIG_MTK_PMIC_SHUTDOWN_CFG := y
+CONFIG_MTK_PMIC_SHUTDOWN_V2 := y
CONFIG_MTK_PMIC_SPT_SUPPORT := n
CONFIG_MTK_SMMU_SID := y
CONFIG_MTK_SPMI := y
diff --git a/plat/st/common/common.mk b/plat/st/common/common.mk
index 4dbb949..56a8814 100644
--- a/plat/st/common/common.mk
+++ b/plat/st/common/common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
+# Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
# Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -27,7 +27,10 @@
STM32_HEADER_BL2_BINARY_TYPE := 0x10
TF_CFLAGS += -Wsign-compare
+ifeq ($(findstring clang,$(notdir $(CC))),)
+# Only for GCC
TF_CFLAGS += -Wformat-signedness
+endif
# Number of TF-A copies in the device
STM32_TF_A_COPIES := 2
diff --git a/plat/st/common/common_rules.mk b/plat/st/common/common_rules.mk
index 88c1087..bb7e3c5 100644
--- a/plat/st/common/common_rules.mk
+++ b/plat/st/common/common_rules.mk
@@ -71,8 +71,13 @@
tf-a-%.stm32: tf-a-%.bin ${STM32_DEPS}
$(s)echo
$(s)echo "Generate $@"
+ifeq ($($(ARCH)-ld-id),llvm-lld)
+ $(eval LOADADDR = 0x$(shell cat $(@:.stm32=.map) | grep '\.data$$' | awk '{print $$1}'))
+ $(eval ENTRY = 0x$(shell cat $(@:.stm32=.map) | grep "__BL2_IMAGE_START" | awk '{print $$1}'))
+else
$(eval LOADADDR = $(shell cat $(@:.stm32=.map) | grep '^RAM' | awk '{print $$2}'))
$(eval ENTRY = $(shell cat $(@:.stm32=.map) | grep "__BL2_IMAGE_START" | awk '{print $$1}'))
+endif
$(q)${STM32IMAGE} -s $< -d $@ \
-l $(LOADADDR) -e ${ENTRY} \
-v ${STM32_TF_VERSION} \
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index e700823..0e0586b 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -17,6 +17,8 @@
# Default Device tree
DTB_FILE_NAME ?= stm32mp157c-ev1.dtb
+TF_CFLAGS += -DSTM32MP1X
+
STM32MP13 ?= 0
STM32MP15 ?= 0
diff --git a/plat/st/stm32mp1/stm32mp1.S b/plat/st/stm32mp1/stm32mp1.S
index aee4f0e..a688f4d 100644
--- a/plat/st/stm32mp1/stm32mp1.S
+++ b/plat/st/stm32mp1/stm32mp1.S
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-.section .bl2_image
+.section .bl2_image, "a"
.incbin BL2_BIN_PATH
-.section .dtb_image
+.section .dtb_image, "a"
.incbin DTB_BIN_PATH
diff --git a/plat/st/stm32mp1/stm32mp1.ld.S b/plat/st/stm32mp1/stm32mp1.ld.S
index 1be8219..c9d9873 100644
--- a/plat/st/stm32mp1/stm32mp1.ld.S
+++ b/plat/st/stm32mp1/stm32mp1.ld.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,17 +33,17 @@
} >HEADER
. = STM32MP_BINARY_BASE;
- .data . : {
+ .data : {
. = ALIGN(PAGE_SIZE);
__DATA_START__ = .;
- *(.data*)
+ FILL(0);
/*
* dtb.
* The strongest and only alignment contraint is MMU 4K page.
* Indeed as images below will be removed, 4K pages will be re-used.
*/
- . = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE );
+ . = ABSOLUTE( STM32MP_BL2_DTB_BASE );
__DTB_IMAGE_START__ = .;
*(.dtb_image*)
__DTB_IMAGE_END__ = .;
@@ -54,9 +54,9 @@
* Indeed as images below will be removed, 4K pages will be re-used.
*/
#if SEPARATE_CODE_AND_RODATA
- . = ( STM32MP_BL2_RO_BASE - STM32MP_BINARY_BASE );
+ . = ABSOLUTE( STM32MP_BL2_RO_BASE );
#else
- . = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE );
+ . = ABSOLUTE( STM32MP_BL2_BASE );
#endif
__BL2_IMAGE_START__ = .;
*(.bl2_image*)
diff --git a/plat/st/stm32mp2/aarch64/stm32mp2.S b/plat/st/stm32mp2/aarch64/stm32mp2.S
index 1866b8b..6c32972 100644
--- a/plat/st/stm32mp2/aarch64/stm32mp2.S
+++ b/plat/st/stm32mp2/aarch64/stm32mp2.S
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-.section .bl2_image
+.section .bl2_image, "a"
.incbin BL2_BIN_PATH
-.section .dtb_image
+.section .dtb_image, "a"
.incbin DTB_BIN_PATH
diff --git a/plat/st/stm32mp2/aarch64/stm32mp2.ld.S b/plat/st/stm32mp2/aarch64/stm32mp2.ld.S
index 48bf424..cf71f27 100644
--- a/plat/st/stm32mp2/aarch64/stm32mp2.ld.S
+++ b/plat/st/stm32mp2/aarch64/stm32mp2.ld.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,17 +33,17 @@
} >HEADER
. = STM32MP_BINARY_BASE;
- .data . : {
+ .data : {
. = ALIGN(PAGE_SIZE);
__DATA_START__ = .;
- *(.data*)
+ FILL(0);
/*
* dtb.
* The strongest and only alignment contraint is MMU 4K page.
* Indeed as images below will be removed, 4K pages will be re-used.
*/
- . = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE );
+ . = ABSOLUTE( STM32MP_BL2_DTB_BASE );
__DTB_IMAGE_START__ = .;
*(.dtb_image*)
__DTB_IMAGE_END__ = .;
@@ -54,9 +54,9 @@
* Indeed as images below will be removed, 4K pages will be re-used.
*/
#if SEPARATE_CODE_AND_RODATA
- . = ( STM32MP_BL2_RO_BASE - STM32MP_BINARY_BASE );
+ . = ABSOLUTE( STM32MP_BL2_RO_BASE );
#else
- . = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE );
+ . = ABSOLUTE( STM32MP_BL2_BASE );
#endif
__BL2_IMAGE_START__ = .;
*(.bl2_image*)
diff --git a/plat/st/stm32mp2/bl2_plat_setup.c b/plat/st/stm32mp2/bl2_plat_setup.c
index 621b784..1d49fe7 100644
--- a/plat/st/stm32mp2/bl2_plat_setup.c
+++ b/plat/st/stm32mp2/bl2_plat_setup.c
@@ -34,97 +34,46 @@
static void print_reset_reason(void)
{
uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_C1BOOTRSTSCLRR);
+ const char *reason_str = "Unidentified";
- if (rstsr == 0U) {
- WARN("Reset reason unknown\n");
- return;
+#if !STM32MP21
+ if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) {
+ INFO("CA35 processor core 1 reset\n");
}
-
- INFO("Reset reason (0x%x):\n", rstsr);
+#endif /* !STM32MP21 */
if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) == 0U) {
if ((rstsr & RCC_C1BOOTRSTSCLRR_STBYC1RSTF) != 0U) {
- INFO("System exits from Standby for CA35\n");
- return;
+ reason_str = "System exits from Standby for CA35";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) {
+ reason_str = "D1 domain exits from DStandby";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_VCPURSTF) != 0U) {
+ reason_str = "System reset from VCPU monitor";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) {
+ reason_str = "CA35 reset by CM33 (C1RST)";
+ } else {
+ reason_str = "Unidentified";
}
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) {
- INFO("D1 domain exits from DStandby\n");
- return;
+ } else {
+ if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) {
+ reason_str = "Power-on reset (por_rstn)";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) {
+ reason_str = "Brownout reset (bor_rstn)";
+ } else if ((rstsr & (RCC_C1BOOTRSTSSETR_SYSC2RSTF |
+ RCC_C1BOOTRSTSSETR_SYSC1RSTF)) != 0U) {
+ reason_str = "System reset (SYSRST)";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) {
+ reason_str = "Clock failure on HSE";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF) != 0U) {
+ reason_str = "IWDG system reset (iwdgX_out_rst)";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) {
+ reason_str = "Pin reset from NRST";
+ } else {
+ reason_str = "Unidentified";
}
}
- if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) {
- INFO(" Power-on Reset (rst_por)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) {
- INFO(" Brownout Reset (rst_bor)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC2RSTF) != 0U) {
- INFO(" System reset (SYSRST) by M33\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC1RSTF) != 0U) {
- INFO(" System reset (SYSRST) by A35\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) {
- INFO(" Clock failure on HSE\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF) != 0U) {
- INFO(" IWDG1 system reset (rst_iwdg1)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF) != 0U) {
- INFO(" IWDG2 system reset (rst_iwdg2)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF) != 0U) {
- INFO(" IWDG3 system reset (rst_iwdg3)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF) != 0U) {
- INFO(" IWDG4 system reset (rst_iwdg4)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF) != 0U) {
- INFO(" IWDG5 system reset (rst_iwdg5)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) {
- INFO(" A35 processor core 1 reset\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) {
- INFO(" Pad Reset from NRST\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_VCORERSTF) != 0U) {
- INFO(" Reset due to a failure of VDD_CORE\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) {
- INFO(" A35 processor reset\n");
- return;
- }
-
- ERROR(" Unidentified reset reason\n");
+ INFO("Reset reason: %s (0x%x)\n", reason_str, rstsr);
}
void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
@@ -164,11 +113,19 @@
* The protection is enable at each reset by hardware
* and must be disabled by software.
*/
+#if STM32MP21
+ mmio_setbits_32(pwr_base + PWR_BDCR, PWR_BDCR_DBP);
+
+ while ((mmio_read_32(pwr_base + PWR_BDCR) & PWR_BDCR_DBP) == 0U) {
+ ;
+ }
+#else /* STM32MP21 */
mmio_setbits_32(pwr_base + PWR_BDCR1, PWR_BDCR1_DBD3P);
while ((mmio_read_32(pwr_base + PWR_BDCR1) & PWR_BDCR1_DBD3P) == 0U) {
;
}
+#endif /* STM32MP21 */
/* Reset backup domain on cold boot cases */
if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) {
diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
index 06298a4..c20435b 100644
--- a/plat/st/stm32mp2/platform.mk
+++ b/plat/st/stm32mp2/platform.mk
@@ -30,11 +30,36 @@
# Default Device tree
DTB_FILE_NAME ?= stm32mp257f-ev1.dtb
-STM32MP25 := 1
+TF_CFLAGS += -DSTM32MP2X
-# STM32 image header version v2.2
+STM32MP21 ?= 0
+STM32MP23 ?= 0
+STM32MP25 ?= 0
+
+ifneq ($(findstring stm32mp21,$(DTB_FILE_NAME)),)
+STM32MP21 := 1
+endif
+ifneq ($(findstring stm32mp23,$(DTB_FILE_NAME)),)
+STM32MP23 := 1
+endif
+ifneq ($(findstring stm32mp25,$(DTB_FILE_NAME)),)
+STM32MP25 := 1
+endif
+ifneq ($(filter 1,$(STM32MP21) $(STM32MP23) $(STM32MP25)), 1)
+$(warning STM32MP21=$(STM32MP21))
+$(warning STM32MP23=$(STM32MP23))
+$(warning STM32MP25=$(STM32MP25))
+$(warning DTB_FILE_NAME=$(DTB_FILE_NAME))
+$(error Cannot enable more than one STM32MP2x flag)
+endif
+
+# STM32 image header version v2.2 or v2.3 for STM32MP21
STM32_HEADER_VERSION_MAJOR := 2
+ifeq ($(STM32MP21),1)
+STM32_HEADER_VERSION_MINOR := 3
+else
STM32_HEADER_VERSION_MINOR := 2
+endif
# Set load address for serial boot devices
DWL_BUFFER_BASE ?= 0x87000000
@@ -110,6 +135,8 @@
STM32MP_DDR3_TYPE \
STM32MP_DDR4_TYPE \
STM32MP_LPDDR4_TYPE \
+ STM32MP21 \
+ STM32MP23 \
STM32MP25 \
STM32MP_BL33_EL1 \
)))
@@ -133,6 +160,8 @@
STM32MP_DDR3_TYPE \
STM32MP_DDR4_TYPE \
STM32MP_LPDDR4_TYPE \
+ STM32MP21 \
+ STM32MP23 \
STM32MP25 \
STM32MP_BL33_EL1 \
)))
diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h
index 90dbcb8..27fc5f9 100644
--- a/plat/st/stm32mp2/stm32mp2_def.h
+++ b/plat/st/stm32mp2/stm32mp2_def.h
@@ -10,16 +10,31 @@
#include <common/tbbr/tbbr_img_def.h>
#ifndef __ASSEMBLER__
#include <drivers/st/bsec.h>
-#endif
-#include <drivers/st/stm32mp25_rcc.h>
-#ifndef __ASSEMBLER__
#include <drivers/st/stm32mp2_clk.h>
#endif
+#if STM32MP21
+#include <drivers/st/stm32mp21_pwr.h>
+#include <drivers/st/stm32mp21_rcc.h>
+#else /* STM32MP21 */
#include <drivers/st/stm32mp2_pwr.h>
+#include <drivers/st/stm32mp25_rcc.h>
+#endif /* STM32MP21 */
+#if STM32MP21
+#include <dt-bindings/clock/st,stm32mp21-rcc.h>
+#include <dt-bindings/clock/stm32mp21-clksrc.h>
+#include <dt-bindings/reset/st,stm32mp21-rcc.h>
+#endif /* STM32MP21 */
+#if STM32MP23
#include <dt-bindings/clock/stm32mp25-clks.h>
#include <dt-bindings/clock/stm32mp25-clksrc.h>
-#include <dt-bindings/gpio/stm32-gpio.h>
#include <dt-bindings/reset/stm32mp25-resets.h>
+#endif /* STM32MP23 */
+#if STM32MP25
+#include <dt-bindings/clock/stm32mp25-clks.h>
+#include <dt-bindings/clock/stm32mp25-clksrc.h>
+#include <dt-bindings/reset/stm32mp25-resets.h>
+#endif /* STM32MP25 */
+#include <dt-bindings/gpio/stm32-gpio.h>
#ifndef __ASSEMBLER__
#include <boot_api.h>
@@ -422,7 +437,11 @@
#define DT_BSEC_COMPAT "st,stm32mp25-bsec"
#define DT_DDR_COMPAT "st,stm32mp2-ddr"
#define DT_PWR_COMPAT "st,stm32mp25-pwr"
+#if STM32MP21
+#define DT_RCC_CLK_COMPAT "st,stm32mp21-rcc"
+#else
#define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc"
+#endif
#define DT_SDMMC2_COMPAT "st,stm32mp25-sdmmc2"
#define DT_UART_COMPAT "st,stm32h7-uart"
diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c
index df49f48..c679344c 100644
--- a/plat/ti/k3/common/k3_psci.c
+++ b/plat/ti/k3/common/k3_psci.c
@@ -226,14 +226,6 @@
wfi();
}
-static int k3_validate_power_state(unsigned int power_state,
- psci_power_state_t *req_state)
-{
- /* TODO: perform the proper validation */
-
- return PSCI_E_SUCCESS;
-}
-
static void k3_pwr_domain_suspend_to_mode(const psci_power_state_t *target_state, uint8_t mode)
{
unsigned int core, proc_id;
@@ -294,7 +286,6 @@
.get_sys_suspend_power_state = k3_get_sys_suspend_power_state,
.system_off = k3_system_off,
.system_reset = k3_system_reset,
- .validate_power_state = k3_validate_power_state,
};
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
diff --git a/plat/xilinx/common/include/pm_node.h b/plat/xilinx/common/include/pm_node.h
index 0efebdf..982a410 100644
--- a/plat/xilinx/common/include/pm_node.h
+++ b/plat/xilinx/common/include/pm_node.h
@@ -22,6 +22,7 @@
#define NODE_SUBCLASS_MASK_BITS GENMASK_32(5, 0)
#define NODE_TYPE_MASK_BITS GENMASK_32(5, 0)
#define NODE_INDEX_MASK_BITS GENMASK_32(13, 0)
+#define NODE_CLASS_MASK (NODE_CLASS_MASK_BITS << NODE_CLASS_SHIFT)
#define NODEID(CLASS, SUBCLASS, TYPE, INDEX) \
((((CLASS) & NODE_CLASS_MASK_BITS) << NODE_CLASS_SHIFT) | \
@@ -29,6 +30,8 @@
(((TYPE) & NODE_TYPE_MASK_BITS) << NODE_TYPE_SHIFT) | \
(((INDEX) & NODE_INDEX_MASK_BITS) << NODE_INDEX_SHIFT))
+#define NODECLASS(ID) (((ID) & NODE_CLASS_MASK) >> NODE_CLASS_SHIFT)
+
/*********************************************************************
* Enum definitions
********************************************************************/
diff --git a/plat/xilinx/common/pm_service/pm_svc_main.c b/plat/xilinx/common/pm_service/pm_svc_main.c
index 77ebb62..b8ff926 100644
--- a/plat/xilinx/common/pm_service/pm_svc_main.c
+++ b/plat/xilinx/common/pm_service/pm_svc_main.c
@@ -170,7 +170,8 @@
break;
case PM_NOTIFY_CB:
if (sgi != INVALID_SGI) {
- if (payload[2] == EVENT_CPU_PWRDWN) {
+ if ((payload[2] == EVENT_CPU_PWRDWN) &&
+ (NODECLASS(payload[1]) == (uint32_t)XPM_NODECLASS_DEVICE)) {
if (pwrdwn_req_received) {
pwrdwn_req_received = false;
request_cpu_pwrdwn();
@@ -182,7 +183,8 @@
}
notify_os();
} else {
- if (payload[2] == EVENT_CPU_PWRDWN) {
+ if ((payload[2] == EVENT_CPU_PWRDWN) &&
+ (NODECLASS(payload[1]) == (uint32_t)XPM_NODECLASS_DEVICE)) {
request_cpu_pwrdwn();
(void)psci_cpu_off();
}
diff --git a/services/std_svc/drtm/drtm_dma_prot.h b/services/std_svc/drtm/drtm_dma_prot.h
index 79dc9cb..5ccff87 100644
--- a/services/std_svc/drtm/drtm_dma_prot.h
+++ b/services/std_svc/drtm/drtm_dma_prot.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -20,7 +20,7 @@
enum dma_prot_type {
PROTECT_NONE = -1,
PROTECT_MEM_ALL = 0,
- PROTECT_MEM_REGION = 2,
+ PROTECT_MEM_REGION = 1,
};
struct dma_prot {
diff --git a/services/std_svc/drtm/drtm_measurements.c b/services/std_svc/drtm/drtm_measurements.c
index 7214e23..4518d37 100644
--- a/services/std_svc/drtm/drtm_measurements.c
+++ b/services/std_svc/drtm/drtm_measurements.c
@@ -138,7 +138,8 @@
/* PCR-17: End of DCE measurements. */
rc = drtm_event_log_measure_and_record((uintptr_t)drtm_event_arm_sep_data,
strlen(drtm_event_arm_sep_data),
- DRTM_EVENT_ARM_SEPARATOR, NULL,
+ DRTM_EVENT_ARM_SEPARATOR,
+ drtm_event_arm_sep_data,
PCR_17);
CHECK_RC(rc, drtm_event_log_measure_and_record(DRTM_EVENT_ARM_SEPARATOR));
@@ -188,7 +189,7 @@
/* PCR-18: Measure the DLME image entry point. */
dlme_img_ep = DL_ARGS_GET_DLME_ENTRY_POINT(a);
- drtm_event_log_measure_and_record((uintptr_t)&dlme_img_ep,
+ drtm_event_log_measure_and_record((uintptr_t)&(a->dlme_img_ep_off),
sizeof(dlme_img_ep),
DRTM_EVENT_ARM_DLME_EP, NULL,
PCR_18);
@@ -197,7 +198,8 @@
/* PCR-18: End of DCE measurements. */
rc = drtm_event_log_measure_and_record((uintptr_t)drtm_event_arm_sep_data,
strlen(drtm_event_arm_sep_data),
- DRTM_EVENT_ARM_SEPARATOR, NULL,
+ DRTM_EVENT_ARM_SEPARATOR,
+ drtm_event_arm_sep_data,
PCR_18);
CHECK_RC(rc,
drtm_event_log_measure_and_record(DRTM_EVENT_ARM_SEPARATOR));
diff --git a/services/std_svc/sdei/sdei_event.c b/services/std_svc/sdei/sdei_event.c
index cc8f557..9c7f74a 100644
--- a/services/std_svc/sdei/sdei_event.c
+++ b/services/std_svc/sdei/sdei_event.c
@@ -61,11 +61,13 @@
* Both shared and private maps are stored in single-dimensional array. Private
* event entries are kept for each PE forming a 2D array.
*/
-sdei_entry_t *get_event_entry_target_pe(long int mapsub, unsigned int nm, uint64_t target_pe)
+sdei_entry_t *get_event_entry_target_pe(long int mapsub, unsigned int nm,
+uint64_t target_pe)
{
sdei_entry_t *cpu_priv_base;
- unsigned int base_idx;
+ unsigned int base_idx = 0U;
long int idx;
+ int target_pos;
/*
* For a private map, find the index of the mapping in the
@@ -74,9 +76,17 @@
idx = mapsub;
/* Base of private mappings for this CPU */
- base_idx = (unsigned int) plat_core_pos_by_mpidr(target_pe);
+ target_pos = plat_core_pos_by_mpidr(target_pe);
+
+ if ((target_pos < 0) || ((unsigned int)target_pos >= PLATFORM_CORE_COUNT)) {
+ return NULL;
+ }
+
+ base_idx = (unsigned int) target_pos;
base_idx *= nm;
+
cpu_priv_base = &sdei_private_event_table[base_idx];
+
/*
* Return the address of the entry at the same index in the
* per-CPU event entry.
diff --git a/services/std_svc/sdei/sdei_intr_mgmt.c b/services/std_svc/sdei/sdei_intr_mgmt.c
index 4854b2e..40c3c24 100644
--- a/services/std_svc/sdei/sdei_intr_mgmt.c
+++ b/services/std_svc/sdei/sdei_intr_mgmt.c
@@ -61,9 +61,12 @@
bool sdei_is_target_pe_masked(uint64_t target_pe)
{
- const sdei_cpu_state_t *state = sdei_get_target_pe_state(target_pe);
-
- return state->pe_masked;
+ int errstat = plat_core_pos_by_mpidr(target_pe);
+ if (errstat >= 0) {
+ const sdei_cpu_state_t *state = &cpu_state[errstat];
+ return state->pe_masked;
+ }
+ return true;
}
int64_t sdei_pe_mask(void)
diff --git a/services/std_svc/sdei/sdei_main.c b/services/std_svc/sdei/sdei_main.c
index bbc9f73..52c01e8 100644
--- a/services/std_svc/sdei/sdei_main.c
+++ b/services/std_svc/sdei/sdei_main.c
@@ -948,6 +948,9 @@
if (map_priv->ev_num == SDEI_EVENT_0) {
se = get_event_entry_target_pe((long int) i,
(unsigned int) SDEI_PRIVATE_MAPPING()->num_maps, target_pe);
+ if (se == NULL) {
+ return SDEI_EINVAL;
+ }
if (!(GET_EV_STATE((se), REGISTERED))) {
return SDEI_EINVAL;
}