| commit | 69970765fa9f9ec7a9de2408e50ea21d681df1c2 | [log] [tgz] |
|---|---|---|
| author | xiandong.wang <xiandong.wang@mediatek.corp-partner.google.com> | Mon Jul 07 14:06:57 2025 +0800 |
| committer | Xiandong Wang <xiandong.wang@mediatek.com> | Fri Jul 25 11:46:37 2025 +0800 |
| tree | 11c36686966fe3e67722179a789298a3ddd87e7f | |
| parent | 67c23966aee63b96ac19490b51e9a1049f4d6e92 [diff] |
feat(mt8189): add support display driver After a suspend/resume cycle, the display's register state reverts to its default state. Therefore, display must set the register state to normal, allowing the GCE and CPU to have the authority to configure this register. Signed-off-by: xiandong.wang <xiandong.wang@mediatek.com> Change-Id: I124eb0eae17d7ab263c23374b70c3b6155dc7c3a