feat(nxp-clk): add MC_CGM clock objects
The MC_CGM1 clock objects will participate in A53 clocking.
Change-Id: I7309b630d72ac0ad66df7c299b678454220e0581
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
index dd81d66..69a9d21 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
@@ -145,6 +145,9 @@
case s32cc_clkmux_t:
ret = -ENOTSUP;
break;
+ case s32cc_shared_clkmux_t:
+ ret = -ENOTSUP;
+ break;
case s32cc_pll_t:
ret = -ENOTSUP;
break;
@@ -261,6 +264,7 @@
ret = set_osc_freq(module, rate, orate, depth);
break;
case s32cc_clkmux_t:
+ case s32cc_shared_clkmux_t:
case s32cc_pll_t:
case s32cc_pll_out_div_t:
ret = -ENOTSUP;
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_modules.c b/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
index b75c3ff..1f381b6 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
@@ -40,6 +40,14 @@
static struct s32cc_clk arm_pll_phi0_clk =
S32CC_FREQ_MODULE_CLK(arm_pll_phi0_div, 0, GHZ);
+/* MC_CGM1 */
+static struct s32cc_clkmux cgm1_mux0 =
+ S32CC_SHARED_CLKMUX_INIT(S32CC_CGM1, 0, 3,
+ S32CC_CLK_FIRC,
+ S32CC_CLK_ARM_PLL_PHI0,
+ S32CC_CLK_ARM_PLL_DFS2, 0, 0);
+static struct s32cc_clk cgm1_mux0_clk = S32CC_MODULE_CLK(cgm1_mux0);
+
static struct s32cc_clk *s32cc_hw_clk_list[5] = {
/* Oscillators */
[S32CC_CLK_ID(S32CC_CLK_FIRC)] = &firc_clk,
@@ -55,10 +63,12 @@
.n_clks = ARRAY_SIZE(s32cc_hw_clk_list),
};
-static struct s32cc_clk *s32cc_arch_clk_list[2] = {
+static struct s32cc_clk *s32cc_arch_clk_list[3] = {
/* ARM PLL */
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_MUX)] = &arm_pll_mux_clk,
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_VCO)] = &arm_pll_vco_clk,
+ /* MC_CGM1 */
+ [S32CC_CLK_ID(S32CC_CLK_MC_CGM1_MUX0)] = &cgm1_mux0_clk,
};
static struct s32cc_clk_array s32cc_arch_clocks = {