diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
index 6ec6742..258817f 100644
--- a/lib/cpus/aarch64/cortex_a510.S
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -128,6 +128,15 @@
 
 check_erratum_ls cortex_a510, ERRATUM(2288014), CPU_REV(1, 0)
 
+workaround_reset_start cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941
+	errata_dsu_2313941_wa_impl
+workaround_reset_end cortex_a510, ERRATUM(2313941)
+
+check_erratum_custom_start cortex_a510, ERRATUM(2313941)
+	check_errata_dsu_2313941_impl
+	ret
+check_erratum_custom_end cortex_a510, ERRATUM(2313941)
+
 workaround_reset_start cortex_a510, ERRATUM(2347730), ERRATA_A510_2347730
 	/*
 	 * Set CPUACTLR_EL1[17] to 1'b1, which disables
@@ -169,15 +178,6 @@
 
 check_erratum_ls cortex_a510, ERRATUM(2684597), CPU_REV(1, 2)
 
-workaround_reset_start cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941
-	errata_dsu_2313941_wa_impl
-workaround_reset_end cortex_a510, ERRATUM(2313941)
-
-check_erratum_custom_start cortex_a510, ERRATUM(2313941)
-	check_errata_dsu_2313941_impl
-	ret
-check_erratum_custom_end cortex_a510, ERRATUM(2313941)
-
 .global check_erratum_cortex_a510_2971420
 add_erratum_entry cortex_a510, ERRATUM(2971420), ERRATA_A510_2971420
 check_erratum_range cortex_a510, ERRATUM(2971420), CPU_REV(0, 1), CPU_REV(1, 3)
diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S
index cf91431..f5921a2 100644
--- a/lib/cpus/aarch64/cortex_a55.S
+++ b/lib/cpus/aarch64/cortex_a55.S
@@ -22,24 +22,6 @@
 
 cpu_reset_prologue cortex_a55
 
-workaround_reset_start cortex_a55, ERRATUM(798953), ERRATA_DSU_798953
-	errata_dsu_798953_wa_impl
-workaround_reset_end cortex_a55, ERRATUM(798953)
-
-check_erratum_custom_start cortex_a55, ERRATUM(798953)
-	check_errata_dsu_798953_impl
-	ret
-check_erratum_custom_end cortex_a55, ERRATUM(798953)
-
-workaround_reset_start cortex_a55, ERRATUM(936184), ERRATA_DSU_936184
-	errata_dsu_936184_wa_impl
-workaround_reset_end cortex_a55, ERRATUM(936184)
-
-check_erratum_custom_start cortex_a55, ERRATUM(936184)
-	check_errata_dsu_936184_impl
-	ret
-check_erratum_custom_end cortex_a55, ERRATUM(936184)
-
 workaround_reset_start cortex_a55, ERRATUM(768277), ERRATA_A55_768277
 	sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
 workaround_reset_end cortex_a55, ERRATUM(768277)
@@ -71,6 +53,15 @@
 
 check_erratum_ls cortex_a55, ERRATUM(798797), CPU_REV(0, 0)
 
+workaround_reset_start cortex_a55, ERRATUM(798953), ERRATA_DSU_798953
+	errata_dsu_798953_wa_impl
+workaround_reset_end cortex_a55, ERRATUM(798953)
+
+check_erratum_custom_start cortex_a55, ERRATUM(798953)
+	check_errata_dsu_798953_impl
+	ret
+check_erratum_custom_end cortex_a55, ERRATUM(798953)
+
 workaround_reset_start cortex_a55, ERRATUM(846532), ERRATA_A55_846532
 	sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
 workaround_reset_end cortex_a55, ERRATUM(846532)
@@ -83,6 +74,15 @@
 
 check_erratum_ls cortex_a55, ERRATUM(903758), CPU_REV(0, 1)
 
+workaround_reset_start cortex_a55, ERRATUM(936184), ERRATA_DSU_936184
+	errata_dsu_936184_wa_impl
+workaround_reset_end cortex_a55, ERRATUM(936184)
+
+check_erratum_custom_start cortex_a55, ERRATUM(936184)
+	check_errata_dsu_936184_impl
+	ret
+check_erratum_custom_end cortex_a55, ERRATUM(936184)
+
 workaround_reset_start cortex_a55, ERRATUM(1221012), ERRATA_A55_1221012
 	mov	x0, #0x0020
 	movk	x0, #0x0850, lsl #16
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 822ef05..36bb0ca 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -301,6 +301,24 @@
 endfunc apply_cve_2018_3639_sync_wa
 #endif /* DYNAMIC_WORKAROUND_CVE_2018_3639 */
 
+workaround_reset_start cortex_a76, ERRATUM(798953), ERRATA_DSU_798953
+	errata_dsu_798953_wa_impl
+workaround_reset_end cortex_a76, ERRATUM(798953)
+
+check_erratum_custom_start cortex_a76, ERRATUM(798953)
+	check_errata_dsu_798953_impl
+	ret
+check_erratum_custom_end cortex_a76, ERRATUM(798953)
+
+workaround_reset_start cortex_a76, ERRATUM(936184), ERRATA_DSU_936184
+	errata_dsu_936184_wa_impl
+workaround_reset_end cortex_a76, ERRATUM(936184)
+
+check_erratum_custom_start cortex_a76, ERRATUM(936184)
+	check_errata_dsu_936184_impl
+	ret
+check_erratum_custom_end cortex_a76, ERRATUM(936184)
+
 workaround_reset_start cortex_a76, ERRATUM(1073348), ERRATA_A76_1073348
 	sysreg_bit_set CORTEX_A76_CPUACTLR_EL1 ,CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION
 workaround_reset_end cortex_a76, ERRATUM(1073348)
@@ -411,6 +429,11 @@
 	ret
 endfunc cortex_a76_disable_wa_cve_2018_3639
 
+check_erratum_chosen cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+
+/* erratum has no workaround in the cpu. Generic code must take care */
+add_erratum_entry cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+
 /* --------------------------------------------------------------
  * Errata Workaround for Cortex A76 Errata #1165522.
  * This applies only to revisions <= r3p0 of Cortex A76.
@@ -427,29 +450,6 @@
 	ret
 check_erratum_custom_end cortex_a76, ERRATUM(1165522)
 
-check_erratum_chosen cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-
-/* erratum has no workaround in the cpu. Generic code must take care */
-add_erratum_entry cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-
-workaround_reset_start cortex_a76, ERRATUM(798953), ERRATA_DSU_798953
-	errata_dsu_798953_wa_impl
-workaround_reset_end cortex_a76, ERRATUM(798953)
-
-check_erratum_custom_start cortex_a76, ERRATUM(798953)
-	check_errata_dsu_798953_impl
-	ret
-check_erratum_custom_end cortex_a76, ERRATUM(798953)
-
-workaround_reset_start cortex_a76, ERRATUM(936184), ERRATA_DSU_936184
-	errata_dsu_936184_wa_impl
-workaround_reset_end cortex_a76, ERRATUM(936184)
-
-check_erratum_custom_start cortex_a76, ERRATUM(936184)
-	check_errata_dsu_936184_impl
-	ret
-check_erratum_custom_end cortex_a76, ERRATUM(936184)
-
 cpu_reset_func_start cortex_a76
 
 #if WORKAROUND_CVE_2018_3639
diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c
index 03d18ec..ab68467 100644
--- a/lib/cpus/errata_report.c
+++ b/lib/cpus/errata_report.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -63,9 +63,6 @@
 #else /* !REPORT_ERRATA */
 /*
  * New errata status message printer
- * The order checking function is hidden behind the FEATURE_DETECTION flag to
- * save space. This functionality is only useful on development and platform
- * bringup builds, when FEATURE_DETECTION should be used anyway
  */
 void generic_errata_report(void)
 {
@@ -73,11 +70,6 @@
 	struct erratum_entry *entry = cpu_ops->errata_list_start;
 	struct erratum_entry *end = cpu_ops->errata_list_end;
 	long rev_var = cpu_get_rev_var();
-#if FEATURE_DETECTION
-	uint32_t last_erratum_id = 0;
-	uint16_t last_cve_yr = 0;
-	bool check_cve = false;
-#endif /* FEATURE_DETECTION */
 
 	for (; entry != end; entry += 1) {
 		uint64_t status = entry->check_func(rev_var);
@@ -94,24 +86,6 @@
 		}
 
 		print_status(status, cpu_ops->cpu_str, entry->cve, entry->id);
-
-#if FEATURE_DETECTION
-		if (entry->cve) {
-			if (last_cve_yr > entry->cve ||
-			   (last_cve_yr == entry->cve && last_erratum_id >= entry->id)) {
-				WARN("CVE %u_%u was out of order!\n",
-				      entry->cve, entry->id);
-			}
-			check_cve = true;
-			last_cve_yr = entry->cve;
-		} else {
-			if (last_erratum_id >= entry->id || check_cve) {
-				WARN("Erratum %u was out of order!\n",
-				      entry->id);
-			}
-		}
-		last_erratum_id = entry->id;
-#endif /* FEATURE_DETECTION */
 	}
 }