diff --git a/common/fdt_wrappers.c b/common/fdt_wrappers.c
index 5aad14e..dd7a0fa 100644
--- a/common/fdt_wrappers.c
+++ b/common/fdt_wrappers.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,12 +7,14 @@
 /* Helper functions to offer easier navigation of Device Tree Blob */
 
 #include <assert.h>
+#include <errno.h>
 #include <string.h>
 
 #include <libfdt.h>
 
 #include <common/debug.h>
 #include <common/fdt_wrappers.h>
+#include <common/uuid.h>
 
 /*
  * Read cells from a given property of the given node. Any number of 32-bit
@@ -152,6 +154,39 @@
 }
 
 /*
+ * Read UUID from a given property of the given node. Returns 0 on success,
+ * and a negative value upon error.
+ */
+int fdtw_read_uuid(const void *dtb, int node, const char *prop,
+		   unsigned int length, uint8_t *uuid)
+{
+	/* Buffer for UUID string (plus NUL terminator) */
+	char uuid_string[UUID_STRING_LENGTH + 1U];
+	int err;
+
+	assert(dtb != NULL);
+	assert(prop != NULL);
+	assert(uuid != NULL);
+	assert(node >= 0);
+
+	if (length < UUID_BYTES_LENGTH) {
+		return -EINVAL;
+	}
+
+	err = fdtw_read_string(dtb, node, prop, uuid_string,
+			       UUID_STRING_LENGTH + 1U);
+	if (err != 0) {
+		return err;
+	}
+
+	if (read_uuid(uuid, uuid_string) != 0) {
+		return -FDT_ERR_BADVALUE;
+	}
+
+	return 0;
+}
+
+/*
  * Write cells in place to a given property of the given node. At most 2 cells
  * of the property are written. Returns 0 on success, and -1 upon error.
  */
diff --git a/common/uuid.c b/common/uuid.c
new file mode 100644
index 0000000..dd3c7b0
--- /dev/null
+++ b/common/uuid.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <common/uuid.h>
+
+/* Return the hex nibble value of a char */
+static int8_t hex_val(char hex)
+{
+	int8_t val = 0;
+
+	if ((hex >= '0') && (hex <= '9')) {
+		val = (int8_t)(hex - '0');
+	} else if ((hex >= 'a') && (hex <= 'f')) {
+		val = (int8_t)(hex - 'a' + 0xa);
+	} else if ((hex >= 'A') && (hex <= 'F')) {
+		val = (int8_t)(hex - 'A' + 0xa);
+	} else {
+		val = -1;
+	}
+
+	return val;
+}
+
+/*
+ * Read hex_src_len hex characters from hex_src, convert to bytes and
+ * store in buffer pointed to by dest
+ */
+static int read_hex(uint8_t *dest, char *hex_src, unsigned int hex_src_len)
+{
+	int8_t nibble;
+	uint8_t byte;
+
+	/*
+	 * The string length must be a multiple of 2 to represent an
+	 * exact number of bytes.
+	 */
+	assert((hex_src_len % 2U) == 0U);
+
+	for (unsigned int i = 0U; i < (hex_src_len / 2U); i++) {
+		nibble = 0;
+		byte = 0U;
+
+		nibble = hex_val(hex_src[2U * i]);
+		if (nibble < 0) {
+			return -1;
+		}
+		byte = (uint8_t)nibble;
+		byte <<= 4U;
+
+		nibble = hex_val(hex_src[(2U * i) + 1U]);
+		if (nibble < 0) {
+			return -1;
+		}
+		byte |= (uint8_t)nibble;
+
+		*dest = byte;
+		dest++;
+	}
+
+	return 0;
+}
+
+/* Parse UUIDs of the form aabbccdd-eeff-4099-8877-665544332211 */
+int read_uuid(uint8_t *dest, char *uuid)
+{
+	int err;
+
+	/* Check that we have enough characters */
+	if (strnlen(uuid, UUID_STRING_LENGTH) != UUID_STRING_LENGTH) {
+		WARN("UUID string is too short\n");
+		return -EINVAL;
+	}
+
+	/* aabbccdd */
+	err = read_hex(dest, uuid, 8);
+	uuid += 8;
+	dest += 4;
+
+	/* Check for '-' */
+	err |= ((*uuid == '-') ? 0 : -1);
+	uuid++;
+
+	/* eeff */
+	err |= read_hex(dest, uuid, 4);
+	uuid += 4;
+	dest += 2;
+
+	/* Check for '-' */
+	err |= ((*uuid == '-') ? 0 : -1);
+	uuid++;
+
+	/* 4099 */
+	err |= read_hex(dest, uuid, 4);
+	uuid += 4;
+	dest += 2;
+
+	/* Check for '-' */
+	err |= ((*uuid == '-') ? 0 : -1);
+	uuid++;
+
+	/* 8877 */
+	err |= read_hex(dest, uuid, 4);
+	uuid += 4;
+	dest += 2;
+
+	/* Check for '-' */
+	err |= ((*uuid == '-') ? 0 : -1);
+	uuid++;
+
+	/* 665544332211 */
+	err |= read_hex(dest, uuid, 12);
+	uuid += 12;
+	dest += 6;
+
+	if (err < 0) {
+		WARN("Error parsing UUID\n");
+		/* Clear the buffer on error */
+		memset((void *)dest, '\0', UUID_BYTES_LENGTH * sizeof(uint8_t));
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index 55c8bda..3e8dd91 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst
@@ -44,7 +44,9 @@
 +-----------------+---------------------------+------------------------------+
 | v2.4            | 2nd week of Nov '20       | 4th week of Oct '20          |
 +-----------------+---------------------------+------------------------------+
-| v2.5            | 2nd week of May '21       | 4th week of Apr '21          |
+| v2.5            | 3rd week of May '21       | 5th week of Apr '21          |
++-----------------+---------------------------+------------------------------+
+| v2.6            | 4th week of Oct '21       | 1st week of Oct '21          |
 +-----------------+---------------------------+------------------------------+
 
 Removal of Deprecated Interfaces
@@ -64,4 +66,4 @@
 
 --------------
 
-*Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/components/secure-partition-manager.rst b/docs/components/secure-partition-manager.rst
index 9a65e64..842345a 100644
--- a/docs/components/secure-partition-manager.rst
+++ b/docs/components/secure-partition-manager.rst
@@ -7,6 +7,8 @@
 ========
 
 +--------+-----------------------------------+
+| DMA    | Direct Memory Access              |
++--------+-----------------------------------+
 | DTB    | Device Tree Blob                  |
 +--------+-----------------------------------+
 | DTS    | Device Tree Source                |
@@ -33,6 +35,8 @@
 +--------+-----------------------------------+
 | PSA    | Platform Security Architecture    |
 +--------+-----------------------------------+
+| SMMU   | System Memory Management Unit     |
++--------+-----------------------------------+
 | SP     | Secure Partition                  |
 +--------+-----------------------------------+
 | SPM    | Secure Partition Manager          |
@@ -832,6 +836,114 @@
 to the SPMC when the primary SP EC boots, or be supplied through the SP
 manifest.
 
+Support for SMMUv3 in Hafnium
+=============================
+
+An SMMU is analogous to an MMU in a CPU. It performs address translations for
+Direct Memory Access (DMA) requests from system I/O devices.
+The responsibilities of an SMMU include:
+
+-  Translation: Incoming DMA requests are translated from bus address space to
+   system physical address space using translation tables compliant to
+   Armv8/Armv7 VMSA descriptor format.
+-  Protection: An I/O device can be prohibited from read, write access to a
+   memory region or allowed.
+-  Isolation: Traffic from each individial device can be independently managed.
+   The devices are differentiated from each other using unique translation
+   tables.
+
+The following diagram illustrates a typical SMMU IP integrated in a SoC with
+several I/O devices along with Interconnect and Memory system.
+
+.. image:: ../resources/diagrams/MMU-600.png
+
+SMMU has several versions including SMMUv1, SMMUv2 and SMMUv3. Hafnium provides
+support for SMMUv3 driver in both Normal and Secure World. A brief introduction
+of SMMUv3 functionality and the corresponding software support in Hafnium is
+provided here.
+
+SMMUv3 features
+---------------
+
+-  SMMUv3 provides Stage1, Stage2 translation as well as nested (Stage1 + Stage2)
+   translation support. It can either bypass or abort incoming translations as
+   well.
+-  Traffic (memory transactions) from each upstream I/O peripheral device,
+   referred to as Stream, can be independently managed using a combination of
+   several memory based configuration structures. This allows the SMMUv3 to
+   support a large number of streams with each stream assigned to a unique
+   translation context.
+-  Support for Armv8.1 VMSA where the SMMU shares the translation tables with
+   a Processing Element. AArch32(LPAE) and AArch64 translation table format
+   are supported by SMMUv3.
+-  SMMUv3 offers non-secure stream support with secure stream support being
+   optional. Logically, SMMUv3 behaves as if there is an indepdendent SMMU
+   instance for secure and non-secure stream support.
+-  It also supports sub-streams to differentiate traffic from a virtualized
+   peripheral associated with a VM/SP.
+-  Additionally, SMMUv3.2 provides support for PEs implementing Armv8.4-A
+   extensions. Consequently, SPM depends on Secure EL2 support in SMMUv3.2
+   for providing Secure Stage2 translation support to upstream peripheral
+   devices.
+
+SMMUv3 Programming Interfaces
+-----------------------------
+
+SMMUv3 has three software interfaces that are used by the Hafnium driver to
+configure the behaviour of SMMUv3 and manage the streams.
+
+-  Memory based data strutures that provide unique translation context for
+   each stream.
+-  Memory based circular buffers for command queue and event queue.
+-  A large number of SMMU configuration registers that are memory mapped during
+   boot time by Hafnium driver. Except a few registers, all configuration
+   registers have independent secure and non-secure versions to configure the
+   behaviour of SMMUv3 for translation of secure and non-secure streams
+   respectively.
+
+Peripheral device manifest
+--------------------------
+
+Currently, SMMUv3 driver in Hafnium only supports dependent peripheral devices.
+These devices are dependent on PE endpoint to initiate and receive memory
+management transactions on their behalf. The acccess to the MMIO regions of
+any such device is assigned to the endpoint during boot. Moreover, SMMUv3 driver
+uses the same stage 2 translations for the device as those used by partition
+manager on behalf of the PE endpoint. This ensures that the peripheral device
+has the same visibility of the physical address space as the endpoint. The
+device node of the corresponding partition manifest (refer to `[1]`_ section 3.2
+) must specify these additional properties for each peripheral device in the
+system :
+
+-  smmu-id: This field helps to identify the SMMU instance that this device is
+   upstream of.
+-  stream-ids: List of stream IDs assigned to this device.
+
+.. code:: shell
+
+    smmuv3-testengine {
+        base-address = <0x00000000 0x2bfe0000>;
+        pages-count = <32>;
+        attributes = <0x3>;
+        smmu-id = <0>;
+        stream-ids = <0x0 0x1>;
+        interrupts = <0x2 0x3>, <0x4 0x5>;
+        exclusive-access;
+    };
+
+SMMUv3 driver limitations
+-------------------------
+
+The primary design goal for the Hafnium SMMU driver is to support secure
+streams.
+
+-  Currently, the driver only supports Stage2 translations. No support for
+   Stage1 or nested translations.
+-  Supports only AArch64 translation format.
+-  No support for features such as PCI Express (PASIDs, ATS, PRI), MSI, RAS,
+   Fault handling, Performance Monitor Extensions, Event Handling, MPAM.
+-  No support for independent peripheral devices.
+
 References
 ==========
 
diff --git a/docs/license.rst b/docs/license.rst
index 2f97043..f0caa39 100644
--- a/docs/license.rst
+++ b/docs/license.rst
@@ -76,5 +76,14 @@
    BSD-3-Clause license. Any contributions to this code must be made under the
    terms of both licenses.
 
+-  Some source files originating from the Linux source tree, which are
+   disjunctively dual licensed (GPL-2.0 OR MIT), are redistributed under the
+   terms of the MIT license. These files are:
+
+   -  ``include/dt-bindings/interrupt-controller/arm-gic.h``
+
+   See the original `Linux MIT license`_.
+
 .. _FreeBSD: http://www.freebsd.org
+.. _Linux MIT license: https://raw.githubusercontent.com/torvalds/linux/master/LICENSES/preferred/MIT
 .. _SCC: http://www.simple-cc.org/
diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst
index 2aa9738..79b40d1 100644
--- a/docs/plat/arm/arm-build-options.rst
+++ b/docs/plat/arm/arm-build-options.rst
@@ -132,6 +132,12 @@
    valid value greater than 1, the platform code performs required configuration
    to support multi-chip operation.
 
+- ``CSS_SGI_PLATFORM_VARIANT``: Selects the variant of a SGI/RD platform. A
+    particular SGI/RD platform may have multiple variants which may differ in
+    core count, cluster count or other peripherals. This build option is used
+    to select the appropriate platform variant for the build. The range of
+    valid values is platform specific.
+
 --------------
 
 *Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
diff --git a/docs/plat/deprecated.rst b/docs/plat/deprecated.rst
new file mode 100644
index 0000000..203ae00
--- /dev/null
+++ b/docs/plat/deprecated.rst
@@ -0,0 +1,18 @@
+Deprecated platforms
+====================
+
+Process of deprecating a platform
+---------------------------------
+
+Platform can be deprecated and its source can be kept in repository for a cooling
+off period before deleting it or it can be deleted straight away. For later types
+Deprecated/Deleted version would be same.
+
+List of deprecated platforms
+----------------------------
+
++----------------+----------------+--------------------+--------------------+
+|    Platform    |     Vendor     | Deprecated version |  Deleted version   |
++================+================+====================+====================+
+|    sgm775      |      Arm       |        2.5         |       2.7          |
++----------------+----------------+--------------------+--------------------+
diff --git a/docs/plat/imx8m.rst b/docs/plat/imx8m.rst
index f184b69..0408730 100644
--- a/docs/plat/imx8m.rst
+++ b/docs/plat/imx8m.rst
@@ -43,3 +43,17 @@
 used to generate flash.bin, and flash.bin needs to be flashed into SD card
 with certain offset for BOOT ROM. the u-boot and imx-mkimage will be upstreamed
 soon, this doc will be updated once they are ready, and the link will be posted.
+
+TBBR Boot Sequence
+------------------
+
+When setting NEED_BL2=1 on imx8mm. We support an alternative way of
+boot sequence to support TBBR.
+
+Bootrom --> SPL --> BL2 --> BL31 --> BL33(u-boot with UEFI) --> grub
+
+This helps us to fulfill the SystemReady EBBR standard.
+BL2 will be in the FIT image and SPL will verify it.
+All of the BL3x will be put in the FIP image. BL2 will verify them.
+In U-boot we turn on the UEFI secure boot features so it can verify
+grub. And we use grub to verify linux kernel.
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index 3cbb552..4dc9ecd 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -9,6 +9,7 @@
 
    allwinner
    arm/index
+   deprecated
    meson-axg
    meson-gxbb
    meson-gxl
@@ -20,6 +21,7 @@
    marvell/index
    mt8183
    mt8192
+   mt8195
    nvidia-tegra
    warp7
    imx8
diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst
index c74ff7a..c9f5e82 100644
--- a/docs/plat/marvell/armada/build.rst
+++ b/docs/plat/marvell/armada/build.rst
@@ -112,6 +112,11 @@
         This option is needed on Turris MOX as a workaround to a HW bug which causes reset to
         sometime hang the board.
 
+- A3720_DB_PM_WAKEUP_SRC
+
+        For Armada 3720 Develpment Board only, when ``A3720_DB_PM_WAKEUP_SRC=1``,
+        TF-A will setup PM wake up src configuration. This option is disabled by default.
+
 - MARVELL_SECURE_BOOT
 
         Build trusted(=1)/non trusted(=0) image, default is non trusted.
diff --git a/docs/plat/mt8195.rst b/docs/plat/mt8195.rst
new file mode 100644
index 0000000..b2aeea2
--- /dev/null
+++ b/docs/plat/mt8195.rst
@@ -0,0 +1,21 @@
+MediaTek 8195
+=============
+
+MediaTek 8195 (MT8195) is a 64-bit ARM SoC introduced by MediaTek in 2021.
+The chip incorporates eight cores - four Cortex-A55 little cores and Cortex-A76.
+Cortex-A76 can operate at up to 2.2 GHz.
+Cortex-A55 can operate at up to 2.0 GHz.
+
+Boot Sequence
+-------------
+
+::
+
+    Boot Rom --> Coreboot --> TF-A BL31 --> Depthcharge --> Linux Kernel
+
+How to Build
+------------
+
+.. code:: shell
+
+    make CROSS_COMPILE=aarch64-linux-gnu- PLAT=mt8195 DEBUG=1 COREBOOT=1
diff --git a/docs/resources/diagrams/MMU-600.png b/docs/resources/diagrams/MMU-600.png
new file mode 100644
index 0000000..9cbc243
--- /dev/null
+++ b/docs/resources/diagrams/MMU-600.png
Binary files differ
diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c
index 91ee1be..c7f84af 100644
--- a/drivers/auth/auth_mod.c
+++ b/drivers/auth/auth_mod.c
@@ -222,19 +222,25 @@
  * To protect the system against rollback, the platform includes a non-volatile
  * counter whose value can only be increased. All certificates include a counter
  * value that should not be lower than the value stored in the platform. If the
- * value is larger, the counter in the platform must be updated to the new
- * value.
+ * value is larger, the counter in the platform must be updated to the new value
+ * (provided it has been authenticated).
  *
  * Return: 0 = success, Otherwise = error
+ * Returns additionally,
+ * cert_nv_ctr -> NV counter value present in the certificate
+ * need_nv_ctr_upgrade = 0 -> platform NV counter upgrade is not needed
+ * need_nv_ctr_upgrade = 1 -> platform NV counter upgrade is needed
  */
 static int auth_nvctr(const auth_method_param_nv_ctr_t *param,
 		      const auth_img_desc_t *img_desc,
-		      void *img, unsigned int img_len)
+		      void *img, unsigned int img_len,
+		      unsigned int *cert_nv_ctr,
+		      bool *need_nv_ctr_upgrade)
 {
 	char *p;
 	void *data_ptr = NULL;
 	unsigned int data_len, len, i;
-	unsigned int cert_nv_ctr, plat_nv_ctr;
+	unsigned int plat_nv_ctr;
 	int rc = 0;
 
 	/* Get the counter value from current image. The AM expects the IPM
@@ -265,22 +271,20 @@
 	}
 
 	/* Convert to unsigned int. This code is for a little-endian CPU */
-	cert_nv_ctr = 0;
+	*cert_nv_ctr = 0;
 	for (i = 0; i < len; i++) {
-		cert_nv_ctr = (cert_nv_ctr << 8) | *p++;
+		*cert_nv_ctr = (*cert_nv_ctr << 8) | *p++;
 	}
 
 	/* Get the counter from the platform */
 	rc = plat_get_nv_ctr(param->plat_nv_ctr->cookie, &plat_nv_ctr);
 	return_if_error(rc);
 
-	if (cert_nv_ctr < plat_nv_ctr) {
+	if (*cert_nv_ctr < plat_nv_ctr) {
 		/* Invalid NV-counter */
 		return 1;
-	} else if (cert_nv_ctr > plat_nv_ctr) {
-		rc = plat_set_nv_ctr2(param->plat_nv_ctr->cookie,
-			img_desc, cert_nv_ctr);
-		return_if_error(rc);
+	} else if (*cert_nv_ctr > plat_nv_ctr) {
+		*need_nv_ctr_upgrade = true;
 	}
 
 	return 0;
@@ -351,6 +355,10 @@
 	void *param_ptr;
 	unsigned int param_len;
 	int rc, i;
+	unsigned int cert_nv_ctr = 0;
+	bool need_nv_ctr_upgrade = false;
+	bool sig_auth_done = false;
+	const auth_method_param_nv_ctr_t *nv_ctr_param = NULL;
 
 	/* Get the image descriptor from the chain of trust */
 	img_desc = FCONF_GET_PROPERTY(tbbr, cot, img_id);
@@ -376,10 +384,13 @@
 		case AUTH_METHOD_SIG:
 			rc = auth_signature(&auth_method->param.sig,
 					img_desc, img_ptr, img_len);
+			sig_auth_done = true;
 			break;
 		case AUTH_METHOD_NV_CTR:
-			rc = auth_nvctr(&auth_method->param.nv_ctr,
-					img_desc, img_ptr, img_len);
+			nv_ctr_param = &auth_method->param.nv_ctr;
+			rc = auth_nvctr(nv_ctr_param,
+					img_desc, img_ptr, img_len,
+					&cert_nv_ctr, &need_nv_ctr_upgrade);
 			break;
 		default:
 			/* Unknown authentication method */
@@ -389,6 +400,16 @@
 		return_if_error(rc);
 	}
 
+	/*
+	 * Do platform NV counter upgrade only if the certificate gets
+	 * authenticated, and platform NV-counter upgrade is needed.
+	 */
+	if (need_nv_ctr_upgrade && sig_auth_done) {
+		rc = plat_set_nv_ctr2(nv_ctr_param->plat_nv_ctr->cookie,
+				      img_desc, cert_nv_ctr);
+		return_if_error(rc);
+	}
+
 	/* Extract the parameters indicated in the image descriptor to
 	 * authenticate the children images. */
 	if (img_desc->authenticated_data != NULL) {
diff --git a/drivers/renesas/rcar/ddr/boot_init_dram.h b/drivers/renesas/common/ddr/boot_init_dram.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/boot_init_dram.h
rename to drivers/renesas/common/ddr/boot_init_dram.h
diff --git a/drivers/renesas/common/ddr/ddr.mk b/drivers/renesas/common/ddr/ddr.mk
new file mode 100644
index 0000000..9483686
--- /dev/null
+++ b/drivers/renesas/common/ddr/ddr.mk
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq ($(RCAR_LSI),$(filter $(RCAR_LSI),${RCAR_E3} ${RZ_G2E}))
+    include drivers/renesas/common/ddr/ddr_a/ddr_a.mk
+    BL2_SOURCES += drivers/renesas/common/ddr/dram_sub_func.c
+else ifeq (${RCAR_LSI},${RCAR_D3})
+    include drivers/renesas/common/ddr/ddr_a/ddr_a.mk
+else ifeq (${RCAR_LSI},${RCAR_V3M})
+    include drivers/renesas/common/ddr/ddr_a/ddr_a.mk
+else
+    include drivers/renesas/common/ddr/ddr_b/ddr_b.mk
+    BL2_SOURCES += drivers/renesas/common/ddr/dram_sub_func.c
+endif
diff --git a/drivers/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h b/drivers/renesas/common/ddr/ddr_a/boot_init_dram_regdef.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h
rename to drivers/renesas/common/ddr/ddr_a/boot_init_dram_regdef.h
diff --git a/drivers/renesas/common/ddr/ddr_a/ddr_a.mk b/drivers/renesas/common/ddr/ddr_a/ddr_a.mk
new file mode 100644
index 0000000..cd6433d
--- /dev/null
+++ b/drivers/renesas/common/ddr/ddr_a/ddr_a.mk
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq ($(RCAR_LSI),$(filter $(RCAR_LSI),${RCAR_E3} ${RZ_G2E}))
+BL2_SOURCES += drivers/renesas/common/ddr/ddr_a/ddr_init_e3.c
+else ifeq (${RCAR_LSI},${RCAR_D3})
+BL2_SOURCES += drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c
+else
+BL2_SOURCES += drivers/renesas/common/ddr/ddr_a/ddr_init_v3m.c
+endif
diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c b/drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
rename to drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c
diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/renesas/common/ddr/ddr_a/ddr_init_e3.c
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
rename to drivers/renesas/common/ddr/ddr_a/ddr_init_e3.c
diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c b/drivers/renesas/common/ddr/ddr_a/ddr_init_v3m.c
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
rename to drivers/renesas/common/ddr/ddr_a/ddr_init_v3m.c
diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
similarity index 99%
rename from drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
rename to drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
index ac83c9a..aa3bc24 100644
--- a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
+++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation.
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -36,6 +36,10 @@
 #define RCAR_E3		3	/* NON */
 #define RCAR_H3N	4
 
+#define RZ_G2M		100U
+#define RZ_G2H		101U
+#define RZ_G2N		102U
+
 #define RCAR_CUT_10	0
 #define RCAR_CUT_11	1
 #define RCAR_CUT_20	10
@@ -51,11 +55,11 @@
 #else
 #if (RCAR_LSI == RCAR_H3)
 static const uint32_t prr_product = PRR_PRODUCT_H3;
-#elif(RCAR_LSI == RCAR_M3)
+#elif(RCAR_LSI == RCAR_M3 || RCAR_LSI == RZ_G2M)
 static const uint32_t prr_product = PRR_PRODUCT_M3;
-#elif(RCAR_LSI == RCAR_M3N)
+#elif(RCAR_LSI == RCAR_M3N || RCAR_LSI == RZ_G2N)
 static const uint32_t prr_product = PRR_PRODUCT_M3N;
-#elif(RCAR_LSI == RCAR_H3N)
+#elif(RCAR_LSI == RCAR_H3N || RCAR_LSI == RZ_G2H)
 static const uint32_t prr_product = PRR_PRODUCT_H3;
 #endif /* RCAR_LSI */
 
diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c
similarity index 86%
rename from drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
rename to drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c
index de126de..45b6b08 100644
--- a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
+++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c
@@ -1,11 +1,19 @@
 /*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation.
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#ifndef RZG_SOC
+#define RZG_SOC		0
+#endif
+
+#if (RZG_SOC == 1)
+#define BOARDNUM 4
+#else
 #define BOARDNUM 22
+#endif /* RZG_SOC == 1 */
 #define BOARD_JUDGE_AUTO
 
 #ifdef BOARD_JUDGE_AUTO
@@ -66,6 +74,225 @@
 	0x000F,\
 	0x010F}
 
+#if (RZG_SOC == 1)
+static const struct _boardcnf boardcnfs[BOARDNUM] = {
+	{
+/* boardcnf[0] HopeRun HiHope RZ/G2M 16Gbit/1rank/2ch board with G2M SoC */
+	 .phyvalid = 0x03U,
+	 .dbi_en = 0x01U,
+	 .cacs_dly = 0x02c0U,
+	 .cacs_dly_adj = 0x0U,
+	 .dqdm_dly_w = 0x0300U,
+	 .dqdm_dly_r = 0x00a0U,
+	 .ch = {
+		{
+		 { 0x04U, 0xffU },
+		 0x00345201UL,
+		 0x3201U,
+		 { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+		 { 0x08U, 0x08U, 0x08U, 0x08U },
+		 WDQLVL_PAT,
+		 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+		 { 0, 0, 0, 0 },
+		 { 0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0 },
+		 { 0, 0, 0, 0 },
+		 { 0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0 }
+		},
+		{
+		 { 0x04U, 0xffU },
+		 0x00302154UL,
+		 0x2310U,
+		 { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+		 { 0x08U, 0x08U, 0x08U, 0x08U },
+		 WDQLVL_PAT,
+		 { 0, 0, 0, 0, 0, 0, 0, 0,  0, 0 },
+		 { 0, 0, 0, 0 },
+		 { 0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0 },
+		 { 0, 0, 0, 0 },
+		 { 0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0 }
+		}
+		}
+	},
+/* boardcnf[1] HopeRun HiHope RZ/G2M 8Gbit/2rank/2ch board with G2M SoC */
+	{
+	 0x03U,
+	 0x01U,
+	 0x02c0U,
+	 0x0U,
+	 0x0300U,
+	 0x00a0U,
+	{
+		{
+		 { 0x02U, 0x02U },
+		 0x00345201UL,
+		 0x3201U,
+		 { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+		 { 0x08U, 0x08U, 0x08U, 0x08U },
+		 WDQLVL_PAT,
+		 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+		 { 0, 0, 0, 0 },
+		 { 0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0 },
+		 { 0, 0, 0, 0 },
+		 { 0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0 }
+		},
+		{
+		 { 0x02U, 0x02U },
+		 0x00302154UL,
+		 0x2310,
+		 { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+		 { 0x08U, 0x08U, 0x08U, 0x08U },
+		 WDQLVL_PAT,
+		 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+		 { 0, 0, 0, 0 },
+		 { 0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0 },
+		{ 0, 0, 0, 0 },
+		{ 0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0 }
+		}
+	}
+	},
+/* boardcnf[2] HopeRun HiHope RZ/G2H board 16Gbit/1rank/2ch */
+	{
+		0x05U,
+		0x01U,
+		0x0300U,
+		0,
+		0x0300U,
+		0x00a0U,
+		{
+			{
+				{ 0x04U, 0xffU },
+				0x00345201UL,
+				0x3201U,
+				{ 0x01672543U, 0x45367012U, 0x45632107U, 0x60715234U },
+				{ 0x08U, 0x08U, 0x08U, 0x08U },
+				WDQLVL_PAT,
+				{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 }
+			},
+			{
+				{ 0x04U, 0xffU },
+				0x00302154UL,
+				0x2310U,
+				{ 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+				{ 0x08U, 0x08U, 0x08U, 0x08U },
+				WDQLVL_PAT,
+				{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 }
+			},
+			{
+				{ 0x04U, 0xffU },
+				0x00302154UL,
+				0x2310U,
+				{ 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+				{ 0x08U, 0x08U, 0x08U, 0x08U },
+				WDQLVL_PAT,
+				{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 }
+			},
+			{
+				{ 0xffU, 0xffU },
+				0UL,
+				0U,
+				{ 0U, 0U, 0U, 0U },
+				{ 0U, 0U, 0U, 0U },
+				WDQLVL_PAT,
+				{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 }
+			}
+		}
+	},
+/* boardcnf[3] HopeRun HiHope RZ/G2N board 16Gbit/2rank/1ch */
+	{
+		0x01U,
+		0x01U,
+		0x0300U,
+		0,
+		0x0300U,
+		0x00a0U,
+		{
+			{
+				{ 0x04U, 0x04U },
+				0x00345201UL,
+				0x3201U,
+				{ 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+				{ 0x08U, 0x08U, 0x08U, 0x08U },
+				WDQLVL_PAT,
+				{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 }
+			}
+		}
+	},
+};
+#else
 static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	{
 /* boardcnf[0] RENESAS SALVATOR-X board with M3-W/SIP */
@@ -1535,6 +1762,7 @@
 	}
 	}
 };
+#endif /* RZG_SOC == 1 */
 
 void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div)
 {
@@ -1636,7 +1864,7 @@
 #define GPIO_INDT5	0xE605500CU
 #define GPIO_GPSR6	0xE6060118U
 
-#if (RCAR_GEN3_ULCB == 0)
+#if (RCAR_GEN3_ULCB == 0) && (RZG_SOC == 0)
 static void pfc_write_and_poll(uint32_t a, uint32_t v)
 {
 	mmio_write_32(PFC_PMMR, ~v);
@@ -1652,7 +1880,7 @@
 #define RCAR_GEN3_ULCB		0
 #endif
 
-#if (RCAR_GEN3_ULCB == 0)	/* non Starter Kit */
+#if (RCAR_GEN3_ULCB == 0) && (RZG_SOC == 0)	/* non Starter Kit */
 
 static uint32_t opencheck_SSI_WS6(void)
 {
@@ -1709,9 +1937,43 @@
 
 #endif
 
+#if (RZG_SOC == 1)
+#define LPDDR4_2RANK   (0x01U << 25U)
+
+static uint32_t rzg2_board_judge(void)
+{
+	uint32_t brd;
+
+	switch (prr_product) {
+	case PRR_PRODUCT_M3:
+		brd = 1U;
+		if ((mmio_read_32(PRR) & PRR_CUT_MASK) != RCAR_M3_CUT_VER11) {
+			if ((mmio_read_32(GPIO_INDT5) & LPDDR4_2RANK) == 0U) {
+				brd = 0U;
+			}
+		}
+		break;
+	case PRR_PRODUCT_H3:
+		brd = 2U;
+		break;
+	case PRR_PRODUCT_M3N:
+		brd = 3U;
+		break;
+	default:
+		brd = 99U;
+	}
+
+	return brd;
+}
+#endif /* RZG_SOC == 1 */
+
 static uint32_t _board_judge(void)
 {
 	uint32_t brd;
+
+#if (RZG_SOC == 1)
+	brd = rzg2_board_judge();
+#else
 #if (RCAR_GEN3_ULCB == 1)
 	/* Starter Kit */
 	if (prr_product == PRR_PRODUCT_H3) {
@@ -1798,6 +2060,7 @@
 		}
 	}
 #endif
+#endif /* RZG_SOC == 1 */
 
 	return brd;
 }
diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
rename to drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h
diff --git a/drivers/renesas/common/ddr/ddr_b/ddr_b.mk b/drivers/renesas/common/ddr/ddr_b/ddr_b.mk
new file mode 100644
index 0000000..0334780
--- /dev/null
+++ b/drivers/renesas/common/ddr/ddr_b/ddr_b.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BL2_SOURCES += drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
diff --git a/drivers/renesas/rcar/ddr/ddr_b/ddr_regdef.h b/drivers/renesas/common/ddr/ddr_b/ddr_regdef.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_b/ddr_regdef.h
rename to drivers/renesas/common/ddr/ddr_b/ddr_regdef.h
diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
rename to drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3.h
diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3ver2.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h
rename to drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3ver2.h
diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h
rename to drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3.h
diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3n.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
rename to drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3n.h
diff --git a/drivers/renesas/rcar/ddr/dram_sub_func.c b/drivers/renesas/common/ddr/dram_sub_func.c
similarity index 100%
rename from drivers/renesas/rcar/ddr/dram_sub_func.c
rename to drivers/renesas/common/ddr/dram_sub_func.c
diff --git a/drivers/renesas/rcar/ddr/dram_sub_func.h b/drivers/renesas/common/ddr/dram_sub_func.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/dram_sub_func.h
rename to drivers/renesas/common/ddr/dram_sub_func.h
diff --git a/drivers/renesas/common/emmc/emmc_registers.h b/drivers/renesas/common/emmc/emmc_registers.h
index 392abb8..7fae5e4 100644
--- a/drivers/renesas/common/emmc/emmc_registers.h
+++ b/drivers/renesas/common/emmc/emmc_registers.h
@@ -11,11 +11,11 @@
 #define MMC_CH0		(0U)	/* SDHI2/MMC0 */
 #define MMC_CH1		(1U)	/* SDHI3/MMC1 */
 
-#if (RCAR_LSI == RCAR_E3)  || (RCAR_LSI == RZ_G2M)
-#define USE_MMC_CH	(MMC_CH1)	/* R-Car E3 or RZ/G2M */
-#else /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2M */
+#if (RCAR_LSI == RCAR_E3)  || (RCAR_LSI == RZ_G2M) || (RCAR_LSI == RZ_G2H) || (RCAR_LSI == RZ_G2N)
+#define USE_MMC_CH	(MMC_CH1)	/* R-Car E3 or RZ/G2{H,M,N} */
+#else /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2{H,M,N} */
 #define USE_MMC_CH	(MMC_CH0)	/* R-Car H3/M3/M3N */
-#endif /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2M */
+#endif /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2{H,M,N} */
 
 #define BIT0	(0x00000001U)
 #define BIT1	(0x00000002U)
diff --git a/drivers/renesas/common/watchdog/swdt.c b/drivers/renesas/common/watchdog/swdt.c
index 05987ab..1a351ca 100644
--- a/drivers/renesas/common/watchdog/swdt.c
+++ b/drivers/renesas/common/watchdog/swdt.c
@@ -78,7 +78,7 @@
 void rcar_swdt_init(void)
 {
 	uint32_t rmsk, sr;
-#if (RCAR_LSI != RCAR_E3)
+#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RZ_G2E)
 	uint32_t reg, val, product_cut, chk_data;
 
 	reg = mmio_read_32(RCAR_PRR);
@@ -94,7 +94,7 @@
 	mmio_write_32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE |
 		      WTCSRA_WOVFE | WTCSRA_CKS_DIV16);
 
-#if (RCAR_LSI == RCAR_E3)
+#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
 	mmio_write_32(SWDT_WTCNT, WTCNT_UPPER_BYTE | WTCNT_COUNT_7p81k);
 #else
 	val = WTCNT_UPPER_BYTE;
diff --git a/drivers/renesas/rcar/ddr/ddr.mk b/drivers/renesas/rcar/ddr/ddr.mk
deleted file mode 100644
index c26993d..0000000
--- a/drivers/renesas/rcar/ddr/ddr.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-ifeq (${RCAR_LSI},${RCAR_E3})
-    include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
-    BL2_SOURCES += drivers/renesas/rcar/ddr/dram_sub_func.c
-else ifeq (${RCAR_LSI},${RCAR_D3})
-    include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
-else ifeq (${RCAR_LSI},${RCAR_V3M})
-    include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
-else
-    include drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk
-    BL2_SOURCES += drivers/renesas/rcar/ddr/dram_sub_func.c
-endif
diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk b/drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
deleted file mode 100644
index 7882558..0000000
--- a/drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-ifeq (${RCAR_LSI},${RCAR_E3})
-BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
-else ifeq (${RCAR_LSI},${RCAR_D3})
-BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
-else
-BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
-endif
diff --git a/drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk b/drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk
deleted file mode 100644
index 2bcc292..0000000
--- a/drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
diff --git a/drivers/renesas/rzg/board/board.c b/drivers/renesas/rzg/board/board.c
index cfbb047..7636372 100644
--- a/drivers/renesas/rzg/board/board.c
+++ b/drivers/renesas/rzg/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,7 +13,15 @@
 #include "rcar_def.h"
 
 #ifndef BOARD_DEFAULT
+#if (RCAR_LSI == RZ_G2H)
+#define BOARD_DEFAULT		(BOARD_HIHOPE_RZ_G2H << BOARD_CODE_SHIFT)
+#elif (RCAR_LSI == RZ_G2N)
+#define BOARD_DEFAULT		(BOARD_HIHOPE_RZ_G2N << BOARD_CODE_SHIFT)
+#elif (RCAR_LSI == RZ_G2E)
+#define BOARD_DEFAULT		(BOARD_EK874_RZ_G2E << BOARD_CODE_SHIFT)
+#else
 #define BOARD_DEFAULT		(BOARD_HIHOPE_RZ_G2M << BOARD_CODE_SHIFT)
+#endif /* RCAR_LSI == RZ_G2H */
 #endif /* BOARD_DEFAULT */
 
 #define BOARD_CODE_MASK		(0xF8U)
@@ -27,9 +35,15 @@
 #define GP5_25_BIT	(0x01U << 25)
 
 #define HM_ID	{ 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+#define HH_ID	HM_ID
+#define HN_ID	{ 0x20U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+#define EK_ID	HM_ID
 
 const char *g_board_tbl[] = {
 	[BOARD_HIHOPE_RZ_G2M] = "HiHope RZ/G2M",
+	[BOARD_HIHOPE_RZ_G2H] = "HiHope RZ/G2H",
+	[BOARD_HIHOPE_RZ_G2N] = "HiHope RZ/G2N",
+	[BOARD_EK874_RZ_G2E] = "EK874 RZ/G2E",
 	[BOARD_UNKNOWN] = "unknown"
 };
 
@@ -38,8 +52,14 @@
 	static uint8_t board_id = BOARD_ID_UNKNOWN;
 	const uint8_t board_tbl[][8] = {
 		[BOARD_HIHOPE_RZ_G2M] = HM_ID,
+		[BOARD_HIHOPE_RZ_G2H] = HH_ID,
+		[BOARD_HIHOPE_RZ_G2N] = HN_ID,
+		[BOARD_EK874_RZ_G2E] = EK_ID,
 	};
-	uint32_t reg, boardInfo;
+	uint32_t reg;
+#if (RCAR_LSI != RZ_G2E)
+	uint32_t boardInfo;
+#endif /* RCAR_LSI == RZ_G2E */
 
 	if (board_id == BOARD_ID_UNKNOWN) {
 		board_id = BOARD_DEFAULT;
@@ -50,15 +70,28 @@
 	if (*type >= ARRAY_SIZE(board_tbl)) {
 		/* no revision information, set Rev0.0. */
 		*rev = 0;
+		return;
+	}
+
+	reg = mmio_read_32(RCAR_PRR);
+#if (RCAR_LSI == RZ_G2E)
+	if (reg & RCAR_MINOR_MASK) {
+		*rev = 0x30U;
 	} else {
-		reg = mmio_read_32(RCAR_PRR);
-		if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) {
+		*rev = board_tbl[*type][(uint8_t)(board_id & BOARD_REV_MASK)];
+	}
+#else
+	if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) {
+		*rev = board_tbl[*type][(uint8_t)(board_id & BOARD_REV_MASK)];
+	} else {
+		reg = mmio_read_32(GPIO_INDT5);
+		if (reg & GP5_25_BIT) {
 			*rev = board_tbl[*type][(uint8_t)(board_id & BOARD_REV_MASK)];
 		} else {
-			boardInfo = mmio_read_32(GPIO_INDT5) &
-				    (GP5_19_BIT | GP5_21_BIT);
+			boardInfo = reg & (GP5_19_BIT | GP5_21_BIT);
 			*rev = (((boardInfo & GP5_19_BIT) >> 14) |
 				((boardInfo & GP5_21_BIT) >> 17)) + 0x30U;
 		}
 	}
+#endif /* RCAR_LSI == RZ_G2E */
 }
diff --git a/drivers/renesas/rzg/board/board.h b/drivers/renesas/rzg/board/board.h
index c0c3d0c..1a76849 100644
--- a/drivers/renesas/rzg/board/board.h
+++ b/drivers/renesas/rzg/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,6 +9,9 @@
 
 enum rzg2_board_id {
 	BOARD_HIHOPE_RZ_G2M = 0,
+	BOARD_HIHOPE_RZ_G2H,
+	BOARD_HIHOPE_RZ_G2N,
+	BOARD_EK874_RZ_G2E,
 	BOARD_UNKNOWN
 };
 
diff --git a/drivers/renesas/rzg/ddr/boot_init_dram.h b/drivers/renesas/rzg/ddr/boot_init_dram.h
deleted file mode 100644
index 294582f..0000000
--- a/drivers/renesas/rzg/ddr/boot_init_dram.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef BOOT_INIT_DRAM_H
-#define BOOT_INIT_DRAM_H
-
-extern int32_t rzg_dram_init(void);
-
-#define INITDRAM_OK		0
-#define INITDRAM_NG		0xffffffff
-#define INITDRAM_ERR_I		0xffffffff
-#define INITDRAM_ERR_O		0xfffffffe
-#define INITDRAM_ERR_T		0xfffffff0
-
-#endif /* BOOT_INIT_DRAM_H */
diff --git a/drivers/renesas/rzg/ddr/ddr.mk b/drivers/renesas/rzg/ddr/ddr.mk
deleted file mode 100644
index 7558216..0000000
--- a/drivers/renesas/rzg/ddr/ddr.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-include drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk
diff --git a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c
deleted file mode 100644
index 45259e3..0000000
--- a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c
+++ /dev/null
@@ -1,3700 +0,0 @@
-/*
- * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <common/debug.h>
-#include <lib/mmio.h>
-
-#include "boot_init_dram.h"
-#include "boot_init_dram_regdef.h"
-#include "ddr_regdef.h"
-#include "dram_sub_func.h"
-#include "init_dram_tbl_g2m.h"
-#include "micro_delay.h"
-#include "rcar_def.h"
-
-/* load board configuration */
-#include "boot_init_dram_config.c"
-
-#define DDR_BACKUPMODE
-#define FATAL_MSG(x) NOTICE(x)
-
-/* variables */
-#ifdef RCAR_DDR_FIXED_LSI_TYPE
-#ifndef RCAR_AUTO
-#define RCAR_AUTO	99U
-#define RZ_G2M		100U
-
-#define RCAR_CUT_10	0U
-#define RCAR_CUT_11	1U
-#define RCAR_CUT_20	10U
-#define RCAR_CUT_30	20U
-#endif /* RCAR_AUTO */
-#ifndef RCAR_LSI
-#define RCAR_LSI	RCAR_AUTO
-#endif
-
-#if (RCAR_LSI == RCAR_AUTO)
-static uint32_t prr_product;
-static uint32_t prr_cut;
-#else /* RCAR_LSI == RCAR_AUTO */
-#if (RCAR_LSI == RZ_G2M)
-static const uint32_t prr_product = PRR_PRODUCT_M3;
-#endif /* RCAR_LSI == RZ_G2M */
-
-#ifndef RCAR_LSI_CUT
-static uint32_t prr_cut;
-#else /* RCAR_LSI_CUT */
-#if (RCAR_LSI_CUT == RCAR_CUT_10)
-static const uint32_t prr_cut = PRR_PRODUCT_10;
-#elif(RCAR_LSI_CUT == RCAR_CUT_11)
-static const uint32_t prr_cut = PRR_PRODUCT_11;
-#elif(RCAR_LSI_CUT == RCAR_CUT_20)
-static const uint32_t prr_cut = PRR_PRODUCT_20;
-#elif(RCAR_LSI_CUT == RCAR_CUT_30)
-static const uint32_t prr_cut = PRR_PRODUCT_30;
-#endif /* RCAR_LSI_CUT == RCAR_CUT_10 */
-#endif /* RCAR_LSI_CUT */
-#endif /* RCAR_LSI == RCAR_AUTO */
-#else /* RCAR_DDR_FIXED_LSI_TYPE */
-static uint32_t prr_product;
-static uint32_t prr_cut;
-#endif /* RCAR_DDR_FIXED_LSI_TYPE */
-
-static const uint32_t *p_ddr_regdef_tbl;
-static uint32_t brd_clk;
-static uint32_t brd_clkdiv;
-static uint32_t brd_clkdiva;
-static uint32_t ddr_mbps;
-static uint32_t ddr_mbpsdiv;
-static uint32_t ddr_tccd;
-static uint32_t ddr_phycaslice;
-static const struct _boardcnf *board_cnf;
-static uint32_t ddr_phyvalid;
-static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
-static uint32_t ch_have_this_cs[CS_CNT] __aligned(64);
-static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT * 2U][9U];
-static uint32_t max_density;
-static uint32_t ddr0800_mul;
-static uint32_t ddr_mul;
-static uint32_t DDR_PHY_SLICE_REGSET_OFS;
-static uint32_t DDR_PHY_ADR_V_REGSET_OFS;
-static uint32_t DDR_PHY_ADR_I_REGSET_OFS;
-static uint32_t DDR_PHY_ADR_G_REGSET_OFS;
-static uint32_t DDR_PI_REGSET_OFS;
-static uint32_t DDR_PHY_SLICE_REGSET_SIZE;
-static uint32_t DDR_PHY_ADR_V_REGSET_SIZE;
-static uint32_t DDR_PHY_ADR_I_REGSET_SIZE;
-static uint32_t DDR_PHY_ADR_G_REGSET_SIZE;
-static uint32_t DDR_PI_REGSET_SIZE;
-static uint32_t DDR_PHY_SLICE_REGSET_NUM;
-static uint32_t DDR_PHY_ADR_V_REGSET_NUM;
-static uint32_t DDR_PHY_ADR_I_REGSET_NUM;
-static uint32_t DDR_PHY_ADR_G_REGSET_NUM;
-static uint32_t DDR_PI_REGSET_NUM;
-static uint32_t DDR_PHY_ADR_I_NUM;
-#define DDR_PHY_REGSET_MAX 128
-#define DDR_PI_REGSET_MAX 320
-static uint32_t _cnf_DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX];
-static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX];
-static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX];
-static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX];
-static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX];
-static uint32_t pll3_mode;
-static uint32_t loop_max;
-#ifdef DDR_BACKUPMODE
-uint32_t ddr_backup = DRAM_BOOT_STATUS_COLD;
-/* #define DDR_BACKUPMODE_HALF  */  /* for Half channel(ch0,1 only) */
-#endif
-
-#ifdef DDR_QOS_INIT_SETTING	/*  only for non qos_init */
-#define OPERATING_FREQ			(400U)	/* Mhz */
-#define BASE_SUB_SLOT_NUM		(0x6U)
-#define SUB_SLOT_CYCLE			(0x7EU)	/* 126 */
-#define QOSWT_WTSET0_CYCLE		\
-	((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / \
-	OPERATING_FREQ)	/* unit:ns */
-
-uint32_t get_refperiod(void)
-{
-	return QOSWT_WTSET0_CYCLE;
-}
-#else /*  DDR_QOS_INIT_SETTING */
-extern uint32_t get_refperiod(void);
-#endif /* DDR_QOS_INIT_SETTING */
-
-#define _reg_PHY_RX_CAL_X_NUM 11U
-static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = {
-	_reg_PHY_RX_CAL_DQ0,
-	_reg_PHY_RX_CAL_DQ1,
-	_reg_PHY_RX_CAL_DQ2,
-	_reg_PHY_RX_CAL_DQ3,
-	_reg_PHY_RX_CAL_DQ4,
-	_reg_PHY_RX_CAL_DQ5,
-	_reg_PHY_RX_CAL_DQ6,
-	_reg_PHY_RX_CAL_DQ7,
-	_reg_PHY_RX_CAL_DM,
-	_reg_PHY_RX_CAL_DQS,
-	_reg_PHY_RX_CAL_FDBK
-};
-
-#define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10U
-static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY
-	[_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = {
-	_reg_PHY_CLK_WRDQ0_SLAVE_DELAY,
-	_reg_PHY_CLK_WRDQ1_SLAVE_DELAY,
-	_reg_PHY_CLK_WRDQ2_SLAVE_DELAY,
-	_reg_PHY_CLK_WRDQ3_SLAVE_DELAY,
-	_reg_PHY_CLK_WRDQ4_SLAVE_DELAY,
-	_reg_PHY_CLK_WRDQ5_SLAVE_DELAY,
-	_reg_PHY_CLK_WRDQ6_SLAVE_DELAY,
-	_reg_PHY_CLK_WRDQ7_SLAVE_DELAY,
-	_reg_PHY_CLK_WRDM_SLAVE_DELAY,
-	_reg_PHY_CLK_WRDQS_SLAVE_DELAY
-};
-
-#define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9U
-static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY
-	[_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = {
-	_reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY
-};
-
-#define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9U
-static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY
-	[_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = {
-	_reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY
-};
-
-#define _reg_PHY_PAD_TERM_X_NUM 8U
-static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = {
-	_reg_PHY_PAD_FDBK_TERM,
-	_reg_PHY_PAD_DATA_TERM,
-	_reg_PHY_PAD_DQS_TERM,
-	_reg_PHY_PAD_ADDR_TERM,
-	_reg_PHY_PAD_CLK_TERM,
-	_reg_PHY_PAD_CKE_TERM,
-	_reg_PHY_PAD_RST_TERM,
-	_reg_PHY_PAD_CS_TERM
-};
-
-#define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10U
-static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X
-	[_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = {
-	_reg_PHY_ADR0_CLK_WR_SLAVE_DELAY,
-	_reg_PHY_ADR1_CLK_WR_SLAVE_DELAY,
-	_reg_PHY_ADR2_CLK_WR_SLAVE_DELAY,
-	_reg_PHY_ADR3_CLK_WR_SLAVE_DELAY,
-	_reg_PHY_ADR4_CLK_WR_SLAVE_DELAY,
-	_reg_PHY_ADR5_CLK_WR_SLAVE_DELAY,
-
-	_reg_PHY_GRP_SLAVE_DELAY_0,
-	_reg_PHY_GRP_SLAVE_DELAY_1,
-	_reg_PHY_GRP_SLAVE_DELAY_2,
-	_reg_PHY_GRP_SLAVE_DELAY_3
-};
-
-/* Prototypes */
-static inline uint32_t vch_nxt(uint32_t pos);
-static void cpg_write_32(uint32_t a, uint32_t v);
-static void pll3_control(uint32_t high);
-static inline void dsb_sev(void);
-static void wait_dbcmd(void);
-static void send_dbcmd(uint32_t cmd);
-static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd);
-static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata);
-static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata);
-static inline uint32_t ddr_regdef(uint32_t _regdef);
-static inline uint32_t ddr_regdef_adr(uint32_t _regdef);
-static inline uint32_t ddr_regdef_lsb(uint32_t _regdef);
-static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
-			 uint32_t val);
-static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef);
-static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val);
-static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val);
-static void ddr_setval_ach(uint32_t regdef, uint32_t val);
-static void ddr_setval_ach_as(uint32_t regdef, uint32_t val);
-static uint32_t ddr_getval(uint32_t ch, uint32_t regdef);
-static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p);
-static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p);
-static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size);
-static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val);
-static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef);
-static uint32_t ddrphy_regif_chk(void);
-static inline void ddrphy_regif_idle(void);
-static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps,
-			 uint16_t cyc);
-static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv,
-			 uint16_t *_js2);
-static int16_t _f_scale_adj(int16_t ps);
-static void ddrtbl_load(void);
-static void ddr_config_sub(void);
-static void ddr_config(void);
-static void dbsc_regset(void);
-static void dbsc_regset_post(void);
-static uint32_t dfi_init_start(void);
-static void change_lpddr4_en(uint32_t mode);
-static uint32_t set_term_code(void);
-static void ddr_register_set(void);
-static inline uint32_t wait_freqchgreq(uint32_t assert);
-static inline void set_freqchgack(uint32_t assert);
-static inline void set_dfifrequency(uint32_t freq);
-static uint32_t pll3_freq(uint32_t on);
-static void update_dly(void);
-static uint32_t pi_training_go(void);
-static uint32_t init_ddr(void);
-static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick);
-static uint32_t wdqdm_man1(void);
-static uint32_t wdqdm_man(void);
-static uint32_t rdqdm_man1(void);
-static uint32_t rdqdm_man(void);
-
-static int32_t _find_change(uint64_t val, uint32_t dir);
-static uint32_t _rx_offset_cal_updn(uint32_t code);
-static uint32_t rx_offset_cal(void);
-static uint32_t rx_offset_cal_hw(void);
-static void adjust_wpath_latency(void);
-
-struct ddrt_data {
-	int32_t init_temp;	/* Initial Temperature (do) */
-	uint32_t init_cal[4U];	/* Initial io-code (4 is for G2H) */
-	uint32_t tcomp_cal[4U];	/* Temp. compensated io-code (4 is for G2H) */
-};
-
-static struct ddrt_data tcal;
-
-static void pvtcode_update(void);
-static void pvtcode_update2(void);
-static void ddr_padcal_tcompensate_getinit(uint32_t override);
-
-#ifndef DDR_FAST_INIT
-static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2U][9U];
-static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2U][9U];
-static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2U][9U];
-static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
-static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2U];
-static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
-static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
-
-static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9U];
-static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9U];
-static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9U];
-static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
-static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
-static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
-static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
-#endif/* DDR_FAST_INIT */
-
-/* macro for channel selection loop */
-static inline uint32_t vch_nxt(uint32_t pos)
-{
-	uint32_t posn;
-
-	for (posn = pos; posn < DRAM_CH_CNT; posn++) {
-		if ((ddr_phyvalid & (1U << posn)) != 0U) {
-			break;
-		}
-	}
-	return posn;
-}
-
-#define foreach_vch(ch) \
-for (ch = vch_nxt(0U); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1U))
-
-#define foreach_ech(ch) \
-for (ch = 0U; ch < DRAM_CH_CNT; ch++)
-
-/* Printing functions */
-#define MSG_LF(...)
-
-/* clock settings, reset control */
-static void cpg_write_32(uint32_t a, uint32_t v)
-{
-	mmio_write_32(CPG_CPGWPR, ~v);
-	mmio_write_32(a, v);
-}
-
-static void wait_for_pll3_status_bit_turned_on(void)
-{
-	uint32_t data_l;
-
-	do {
-		data_l = mmio_read_32(CPG_PLLECR);
-	} while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
-	dsb_sev();
-}
-
-static void pll3_control(uint32_t high)
-{
-	uint32_t data_l, data_div, data_mul, tmp_div;
-
-	if (high != 0U) {
-		tmp_div = 3999U * brd_clkdiv * (brd_clkdiva + 1U) /
-			(brd_clk * ddr_mul) / 2U;
-		data_mul = ((ddr_mul * tmp_div) - 1U) << 24U;
-		pll3_mode = 1U;
-		loop_max = 2U;
-	} else {
-		tmp_div = 3999U * brd_clkdiv * (brd_clkdiva + 1U) /
-			(brd_clk * ddr0800_mul) / 2U;
-		data_mul = ((ddr0800_mul * tmp_div) - 1U) << 24U;
-		pll3_mode = 0U;
-		loop_max = 8U;
-	}
-
-	switch (tmp_div) {
-	case 1:
-		data_div = 0U;
-		break;
-	case 2:
-	case 3:
-	case 4:
-		data_div = tmp_div;
-		break;
-	default:
-		data_div = 6U;
-		data_mul = (data_mul * tmp_div) / 3U;
-		break;
-	}
-	data_mul = data_mul | (brd_clkdiva << 7);
-
-	/* PLL3 disable */
-	data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT;
-	cpg_write_32(CPG_PLLECR, data_l);
-	dsb_sev();
-
-	if (prr_product == PRR_PRODUCT_M3) {
-		/* PLL3 DIV resetting(Lowest value:3) */
-		data_l = 0x00030003U | (0xFF80FF80U & mmio_read_32(CPG_FRQCRD));
-		cpg_write_32(CPG_FRQCRD, data_l);
-		dsb_sev();
-
-		/* zb3 clk stop */
-		data_l = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR);
-		cpg_write_32(CPG_ZB3CKCR, data_l);
-		dsb_sev();
-
-		/* PLL3 enable */
-		data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
-		cpg_write_32(CPG_PLLECR, data_l);
-		dsb_sev();
-
-		wait_for_pll3_status_bit_turned_on();
-
-		/* PLL3 DIV resetting (Highest value:0) */
-		data_l = (0xFF80FF80U & mmio_read_32(CPG_FRQCRD));
-		cpg_write_32(CPG_FRQCRD, data_l);
-		dsb_sev();
-
-		/* DIV SET KICK */
-		data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
-		cpg_write_32(CPG_FRQCRB, data_l);
-		dsb_sev();
-
-		/* PLL3 multiplier set */
-		cpg_write_32(CPG_PLL3CR, data_mul);
-		dsb_sev();
-
-		wait_for_pll3_status_bit_turned_on();
-
-		/* PLL3 DIV resetting(Target value) */
-		data_l = (data_div << 16U) | data_div |
-			 (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80U);
-		cpg_write_32(CPG_FRQCRD, data_l);
-		dsb_sev();
-
-		/* DIV SET KICK */
-		data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
-		cpg_write_32(CPG_FRQCRB, data_l);
-		dsb_sev();
-
-		wait_for_pll3_status_bit_turned_on();
-
-		/* zb3 clk start */
-		data_l = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR);
-		cpg_write_32(CPG_ZB3CKCR, data_l);
-		dsb_sev();
-	}
-}
-
-/* barrier */
-static inline void dsb_sev(void)
-{
-	__asm__ __volatile__("dsb sy");
-}
-
-/* DDR memory register access */
-static void wait_dbcmd(void)
-{
-	uint32_t data_l;
-	/* dummy read */
-	data_l = mmio_read_32(DBSC_DBCMD);
-	dsb_sev();
-	while (true) {
-		/* wait DBCMD 1=busy, 0=ready */
-		data_l = mmio_read_32(DBSC_DBWAIT);
-		dsb_sev();
-		if ((data_l & 0x00000001U) == 0x00U) {
-			break;
-		}
-	}
-}
-
-static void send_dbcmd(uint32_t cmd)
-{
-	/* dummy read */
-	wait_dbcmd();
-	mmio_write_32(DBSC_DBCMD, cmd);
-	dsb_sev();
-}
-
-static void dbwait_loop(uint32_t wait_loop)
-{
-	uint32_t i;
-
-	for (i = 0U; i < wait_loop; i++) {
-		wait_dbcmd();
-	}
-}
-
-/* DDRPHY register access (raw) */
-static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd)
-{
-	uint32_t val;
-	uint32_t loop;
-
-	val = 0U;
-	mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
-	dsb_sev();
-
-	while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
-		dsb_sev();
-	}
-	dsb_sev();
-
-	for (loop = 0U; loop < loop_max; loop++) {
-		val = mmio_read_32(DBSC_DBPDRGD(phyno));
-		dsb_sev();
-	}
-
-	return val;
-}
-
-static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata)
-{
-	uint32_t loop;
-
-	mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
-	dsb_sev();
-	for (loop = 0U; loop < loop_max; loop++) {
-		mmio_read_32(DBSC_DBPDRGA(phyno));
-		dsb_sev();
-	}
-	mmio_write_32(DBSC_DBPDRGD(phyno), regdata);
-	dsb_sev();
-
-	for (loop = 0U; loop < loop_max; loop++) {
-		mmio_read_32(DBSC_DBPDRGD(phyno));
-		dsb_sev();
-	}
-}
-
-static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata)
-{
-	uint32_t ch;
-	uint32_t loop;
-
-	foreach_vch(ch) {
-		mmio_write_32(DBSC_DBPDRGA(ch), regadd);
-		dsb_sev();
-	}
-
-	foreach_vch(ch) {
-		mmio_write_32(DBSC_DBPDRGD(ch), regdata);
-		dsb_sev();
-	}
-
-	for (loop = 0U; loop < loop_max; loop++) {
-		mmio_read_32(DBSC_DBPDRGD(0));
-		dsb_sev();
-	}
-}
-
-static inline void ddrphy_regif_idle(void)
-{
-	reg_ddrphy_read(0U, ddr_regdef_adr(_reg_PI_INT_STATUS));
-	dsb_sev();
-}
-
-/* DDRPHY register access (field modify) */
-static inline uint32_t ddr_regdef(uint32_t _regdef)
-{
-	return p_ddr_regdef_tbl[_regdef];
-}
-
-static inline uint32_t ddr_regdef_adr(uint32_t _regdef)
-{
-	return DDR_REGDEF_ADR(p_ddr_regdef_tbl[_regdef]);
-}
-
-static inline uint32_t ddr_regdef_lsb(uint32_t _regdef)
-{
-	return DDR_REGDEF_LSB(p_ddr_regdef_tbl[_regdef]);
-}
-
-static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
-			 uint32_t val)
-{
-	uint32_t adr;
-	uint32_t lsb;
-	uint32_t len;
-	uint32_t msk;
-	uint32_t tmp;
-	uint32_t regdef;
-
-	regdef = ddr_regdef(_regdef);
-	adr = DDR_REGDEF_ADR(regdef) + 0x80U * slice;
-	len = DDR_REGDEF_LEN(regdef);
-	lsb = DDR_REGDEF_LSB(regdef);
-	if (len == 0x20U) {
-		msk = 0xffffffffU;
-	} else {
-		msk = ((1U << len) - 1U) << lsb;
-	}
-
-	tmp = reg_ddrphy_read(ch, adr);
-	tmp = (tmp & (~msk)) | ((val << lsb) & msk);
-	reg_ddrphy_write(ch, adr, tmp);
-}
-
-static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef)
-{
-	uint32_t adr;
-	uint32_t lsb;
-	uint32_t len;
-	uint32_t msk;
-	uint32_t tmp;
-	uint32_t regdef;
-
-	regdef = ddr_regdef(_regdef);
-	adr = DDR_REGDEF_ADR(regdef) + 0x80U * slice;
-	len = DDR_REGDEF_LEN(regdef);
-	lsb = DDR_REGDEF_LSB(regdef);
-	if (len == 0x20U) {
-		msk = 0xffffffffU;
-	} else {
-		msk = ((1U << len) - 1U);
-	}
-
-	tmp = reg_ddrphy_read(ch, adr);
-	tmp = (tmp >> lsb) & msk;
-
-	return tmp;
-}
-
-static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val)
-{
-	ddr_setval_s(ch, 0U, regdef, val);
-}
-
-static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val)
-{
-	uint32_t ch;
-
-	foreach_vch(ch) {
-	    ddr_setval_s(ch, slice, regdef, val);
-	}
-}
-
-static void ddr_setval_ach(uint32_t regdef, uint32_t val)
-{
-	ddr_setval_ach_s(0U, regdef, val);
-}
-
-static void ddr_setval_ach_as(uint32_t regdef, uint32_t val)
-{
-	uint32_t slice;
-
-	for (slice = 0U; slice < SLICE_CNT; slice++) {
-		ddr_setval_ach_s(slice, regdef, val);
-	}
-}
-
-static uint32_t ddr_getval(uint32_t ch, uint32_t regdef)
-{
-	return ddr_getval_s(ch, 0U, regdef);
-}
-
-static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p)
-{
-	uint32_t ch;
-
-	foreach_vch(ch) {
-	    p[ch] = ddr_getval_s(ch, 0U, regdef);
-	}
-	return p[0U];
-}
-
-static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p)
-{
-	uint32_t ch, slice;
-	uint32_t *pp;
-
-	pp = p;
-	foreach_vch(ch) {
-		for (slice = 0U; slice < SLICE_CNT; slice++) {
-			*pp++ = ddr_getval_s(ch, slice, regdef);
-		}
-	}
-	return p[0U];
-}
-
-/* handling functions for setting ddrphy value table */
-static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size)
-{
-	uint32_t i;
-
-	for (i = 0U; i < size; i++) {
-		to[i] = from[i];
-	}
-}
-
-static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val)
-{
-	uint32_t adr;
-	uint32_t lsb;
-	uint32_t len;
-	uint32_t msk;
-	uint32_t tmp;
-	uint32_t adrmsk;
-	uint32_t regdef;
-
-	regdef = ddr_regdef(_regdef);
-	adr = DDR_REGDEF_ADR(regdef);
-	len = DDR_REGDEF_LEN(regdef);
-	lsb = DDR_REGDEF_LSB(regdef);
-	if (len == 0x20U) {
-		msk = 0xffffffffU;
-	} else {
-		msk = ((1U << len) - 1U) << lsb;
-	}
-
-	if (adr < 0x400U) {
-		adrmsk = 0xffU;
-	} else {
-		adrmsk = 0x7fU;
-	}
-
-	tmp = tbl[adr & adrmsk];
-	tmp = (tmp & (~msk)) | ((val << lsb) & msk);
-	tbl[adr & adrmsk] = tmp;
-}
-
-static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef)
-{
-	uint32_t adr;
-	uint32_t lsb;
-	uint32_t len;
-	uint32_t msk;
-	uint32_t tmp;
-	uint32_t adrmsk;
-	uint32_t regdef;
-
-	regdef = ddr_regdef(_regdef);
-	adr = DDR_REGDEF_ADR(regdef);
-	len = DDR_REGDEF_LEN(regdef);
-	lsb = DDR_REGDEF_LSB(regdef);
-	if (len == 0x20U) {
-		msk = 0xffffffffU;
-	} else {
-		msk = ((1U << len) - 1U);
-	}
-
-	if (adr < 0x400U) {
-		adrmsk = 0xffU;
-	} else {
-		adrmsk = 0x7fU;
-	}
-
-	tmp = tbl[adr & adrmsk];
-	tmp = (tmp >> lsb) & msk;
-
-	return tmp;
-}
-
-/* DDRPHY register access handling */
-static uint32_t ddrphy_regif_chk(void)
-{
-	uint32_t tmp_ach[DRAM_CH_CNT];
-	uint32_t ch;
-	uint32_t err;
-	uint32_t PI_VERSION_CODE;
-
-	if (prr_product == PRR_PRODUCT_M3) {
-		PI_VERSION_CODE = 0x2041U; /* G2M */
-	}
-
-	ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach);
-	err = 0U;
-	foreach_vch(ch) {
-		if (tmp_ach[ch] != PI_VERSION_CODE) {
-			err = 1U;
-		}
-	}
-	return err;
-}
-
-/* functions and parameters for timing setting */
-struct _jedec_spec1 {
-	uint16_t fx3;
-	uint8_t rlwodbi;
-	uint8_t rlwdbi;
-	uint8_t WL;
-	uint8_t nwr;
-	uint8_t nrtp;
-	uint8_t odtlon;
-	uint8_t MR1;
-	uint8_t MR2;
-};
-
-#define JS1_USABLEC_SPEC_LO 2U
-#define JS1_USABLEC_SPEC_HI 5U
-#define JS1_FREQ_TBL_NUM 8
-#define JS1_MR1(f) (0x04U | ((f) << 4U))
-#define JS1_MR2(f) (0x00U | ((f) << 3U) | (f))
-static const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = {
-	/* 533.333Mbps */
-	{  800U,  6U,  6U,  4U,  6U,  8U, 0U, JS1_MR1(0U), JS1_MR2(0U) | 0x40U },
-	/* 1066.666Mbps */
-	{ 1600U, 10U, 12U,  8U, 10U,  8U, 0U, JS1_MR1(1U), JS1_MR2(1U) | 0x40U },
-	/* 1600.000Mbps */
-	{ 2400U, 14U, 16U, 12U, 16U,  8U, 6U, JS1_MR1(2U), JS1_MR2(2U) | 0x40U },
-	/* 2133.333Mbps */
-	{ 3200U, 20U, 22U, 10U, 20U,  8U, 4U, JS1_MR1(3U), JS1_MR2(3U) },
-	/* 2666.666Mbps */
-	{ 4000U, 24U, 28U, 12U, 24U, 10U, 4U, JS1_MR1(4U), JS1_MR2(4U) },
-	/* 3200.000Mbps */
-	{ 4800U, 28U, 32U, 14U, 30U, 12U, 6U, JS1_MR1(5U), JS1_MR2(5U) },
-	/* 3733.333Mbps */
-	{ 5600U, 32U, 36U, 16U, 34U, 14U, 6U, JS1_MR1(6U), JS1_MR2(6U) },
-	/* 4266.666Mbps */
-	{ 6400U, 36U, 40U, 18U, 40U, 16U, 8U, JS1_MR1(7U), JS1_MR2(7U) }
-};
-
-struct _jedec_spec2 {
-	uint16_t ps;
-	uint16_t cyc;
-};
-
-#define js2_tsr 0
-#define js2_txp 1
-#define js2_trtp 2
-#define js2_trcd 3
-#define js2_trppb 4
-#define js2_trpab 5
-#define js2_tras 6
-#define js2_twr 7
-#define js2_twtr 8
-#define js2_trrd 9
-#define js2_tppd 10
-#define js2_tfaw 11
-#define js2_tdqsck 12
-#define js2_tckehcmd 13
-#define js2_tckelcmd 14
-#define js2_tckelpd 15
-#define js2_tmrr 16
-#define js2_tmrw 17
-#define js2_tmrd 18
-#define js2_tzqcalns 19
-#define js2_tzqlat 20
-#define js2_tiedly 21
-#define js2_tODTon_min 22
-#define JS2_TBLCNT 23
-
-#define js2_trcpb (JS2_TBLCNT)
-#define js2_trcab (JS2_TBLCNT + 1)
-#define js2_trfcab (JS2_TBLCNT + 2)
-#define JS2_CNT (JS2_TBLCNT + 3)
-
-#ifndef JS2_DERATE
-#define JS2_DERATE 0
-#endif
-static const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = {
-	{
-/* tSR */	{ 15000, 3 },
-/* tXP */	{ 7500, 3 },
-/* tRTP */	{ 7500, 8 },
-/* tRCD */	{ 18000, 4 },
-/* tRPpb */	{ 18000, 3 },
-/* tRPab */	{ 21000, 3 },
-/* tRAS  */	{ 42000, 3 },
-/* tWR   */	{ 18000, 4 },
-/* tWTR  */	{ 10000, 8 },
-/* tRRD  */	{ 10000, 4 },
-/* tPPD  */	{ 0, 0 },
-/* tFAW  */	{ 40000, 0 },
-/* tDQSCK */	{ 3500, 0 },
-/* tCKEHCMD */	{ 7500, 3 },
-/* tCKELCMD */	{ 7500, 3 },
-/* tCKELPD */	{ 7500, 3 },
-/* tMRR */	{ 0, 8 },
-/* tMRW */	{ 10000, 10 },
-/* tMRD */	{ 14000, 10 },
-/* tZQCALns */	{ 1000 * 10, 0 },
-/* tZQLAT */	{ 30000, 10 },
-/* tIEdly */	{ 12500, 0 },
-/* tODTon_min */{ 1500, 0 }
-	 }, {
-/* tSR */	{ 15000, 3 },
-/* tXP */	{ 7500, 3 },
-/* tRTP */	{ 7500, 8 },
-/* tRCD */	{ 19875, 4 },
-/* tRPpb */	{ 19875, 3 },
-/* tRPab */	{ 22875, 3 },
-/* tRAS */	{ 43875, 3 },
-/* tWR */	{ 18000, 4 },
-/* tWTR */	{ 10000, 8 },
-/* tRRD */	{ 11875, 4 },
-/* tPPD */	{ 0, 0 },
-/* tFAW */	{ 40000, 0 },
-/* tDQSCK */	{ 3600, 0 },
-/* tCKEHCMD */	{ 7500, 3 },
-/* tCKELCMD */	{ 7500, 3 },
-/* tCKELPD */	{ 7500, 3 },
-/* tMRR */	{ 0, 8 },
-/* tMRW */	{ 10000, 10 },
-/* tMRD */	{ 14000, 10 },
-/* tZQCALns */	{ 1000 * 10, 0 },
-/* tZQLAT */	{ 30000, 10 },
-/* tIEdly */	{ 12500, 0 },
-/* tODTon_min */{ 1500, 0 }
-	}
-};
-
-static const uint16_t jedec_spec2_trfc_ab[7] = {
-	/* 4Gb, 6Gb,  8Gb,  12Gb, 16Gb, 24Gb(non), 32Gb(non) */
-	 130U, 180U, 180U, 280U, 280U, 560U, 560U
-};
-
-static uint32_t js1_ind;
-static uint16_t js2[JS2_CNT];
-static uint8_t RL;
-static uint8_t WL;
-
-static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps,
-			 uint16_t cyc)
-{
-	uint16_t ret = cyc;
-	uint32_t tmp;
-	uint32_t div;
-
-	tmp = (((uint32_t)(ps) + 9U) / 10U) * _ddr_mbps;
-	div = tmp / (200000U * _ddr_mbpsdiv);
-	if (tmp != (div * 200000U * _ddr_mbpsdiv)) {
-		div = div + 1U;
-	}
-
-	if (div > cyc) {
-		ret = (uint16_t)div;
-	}
-
-	return ret;
-}
-
-static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv,
-			 uint16_t *_js2)
-{
-	int i;
-
-	for (i = 0; i < JS2_TBLCNT; i++) {
-		_js2[i] = _f_scale(_ddr_mbps, _ddr_mbpsdiv,
-				   jedec_spec2[JS2_DERATE][i].ps,
-				   jedec_spec2[JS2_DERATE][i].cyc);
-	}
-
-	_js2[js2_trcpb] = _js2[js2_tras] + _js2[js2_trppb];
-	_js2[js2_trcab] = _js2[js2_tras] + _js2[js2_trpab];
-}
-
-/* scaler for DELAY value */
-static int16_t _f_scale_adj(int16_t ps)
-{
-	int32_t tmp;
-	/*
-	 * tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000;
-	 *     = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125
-	 *     = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125
-	 */
-	tmp = (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps /
-		(int32_t)ddr_mbpsdiv;
-	tmp = (int32_t)tmp / (int32_t)15625;
-
-	return (int16_t)tmp;
-}
-
-static const uint32_t reg_pi_mr1_data_fx_csx[2U][CSAB_CNT] = {
-	{
-	 _reg_PI_MR1_DATA_F0_0,
-	 _reg_PI_MR1_DATA_F0_1,
-	 _reg_PI_MR1_DATA_F0_2,
-	 _reg_PI_MR1_DATA_F0_3},
-	{
-	 _reg_PI_MR1_DATA_F1_0,
-	 _reg_PI_MR1_DATA_F1_1,
-	 _reg_PI_MR1_DATA_F1_2,
-	 _reg_PI_MR1_DATA_F1_3}
-};
-
-static const uint32_t reg_pi_mr2_data_fx_csx[2U][CSAB_CNT] = {
-	{
-	 _reg_PI_MR2_DATA_F0_0,
-	 _reg_PI_MR2_DATA_F0_1,
-	 _reg_PI_MR2_DATA_F0_2,
-	 _reg_PI_MR2_DATA_F0_3},
-	{
-	 _reg_PI_MR2_DATA_F1_0,
-	 _reg_PI_MR2_DATA_F1_1,
-	 _reg_PI_MR2_DATA_F1_2,
-	 _reg_PI_MR2_DATA_F1_3}
-};
-
-static const uint32_t reg_pi_mr3_data_fx_csx[2U][CSAB_CNT] = {
-	{
-	 _reg_PI_MR3_DATA_F0_0,
-	 _reg_PI_MR3_DATA_F0_1,
-	 _reg_PI_MR3_DATA_F0_2,
-	 _reg_PI_MR3_DATA_F0_3},
-	{
-	 _reg_PI_MR3_DATA_F1_0,
-	 _reg_PI_MR3_DATA_F1_1,
-	 _reg_PI_MR3_DATA_F1_2,
-	 _reg_PI_MR3_DATA_F1_3}
-};
-
-static const uint32_t reg_pi_mr11_data_fx_csx[2U][CSAB_CNT] = {
-	{
-	 _reg_PI_MR11_DATA_F0_0,
-	 _reg_PI_MR11_DATA_F0_1,
-	 _reg_PI_MR11_DATA_F0_2,
-	 _reg_PI_MR11_DATA_F0_3},
-	{
-	 _reg_PI_MR11_DATA_F1_0,
-	 _reg_PI_MR11_DATA_F1_1,
-	 _reg_PI_MR11_DATA_F1_2,
-	 _reg_PI_MR11_DATA_F1_3}
-};
-
-static const uint32_t reg_pi_mr12_data_fx_csx[2U][CSAB_CNT] = {
-	{
-	 _reg_PI_MR12_DATA_F0_0,
-	 _reg_PI_MR12_DATA_F0_1,
-	 _reg_PI_MR12_DATA_F0_2,
-	 _reg_PI_MR12_DATA_F0_3},
-	{
-	 _reg_PI_MR12_DATA_F1_0,
-	 _reg_PI_MR12_DATA_F1_1,
-	 _reg_PI_MR12_DATA_F1_2,
-	 _reg_PI_MR12_DATA_F1_3}
-};
-
-static const uint32_t reg_pi_mr14_data_fx_csx[2U][CSAB_CNT] = {
-	{
-	 _reg_PI_MR14_DATA_F0_0,
-	 _reg_PI_MR14_DATA_F0_1,
-	 _reg_PI_MR14_DATA_F0_2,
-	 _reg_PI_MR14_DATA_F0_3},
-	{
-	 _reg_PI_MR14_DATA_F1_0,
-	 _reg_PI_MR14_DATA_F1_1,
-	 _reg_PI_MR14_DATA_F1_2,
-	 _reg_PI_MR14_DATA_F1_3}
-};
-
-/*
- * regif pll w/a   ( REGIF G2M WA )
- */
-static void regif_pll_wa(void)
-{
-	uint32_t ch;
-	uint32_t reg_ofs;
-
-	/*  PLL setting for PHY : G2M */
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT),
-			   (0x5064U <<
-			    ddr_regdef_lsb(_reg_PHY_PLL_WAIT)));
-
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL),
-			   (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-			     _reg_PHY_PLL_CTRL_TOP) << 16) |
-			   ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-					 _reg_PHY_PLL_CTRL));
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA),
-			   ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-					 _reg_PHY_PLL_CTRL_CA));
-
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL),
-			   (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-			     _reg_PHY_LP4_BOOT_PLL_CTRL_CA) << 16) |
-			   ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-					 _reg_PHY_LP4_BOOT_PLL_CTRL));
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_TOP_PLL_CTRL),
-			   ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-					 _reg_PHY_LP4_BOOT_TOP_PLL_CTRL));
-
-	reg_ofs = ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS;
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS),
-			   _cnf_DDR_PHY_ADR_G_REGSET[reg_ofs]);
-
-	/* protect register interface */
-	ddrphy_regif_idle();
-	pll3_control(0U);
-
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN),
-			   (0x01U << ddr_regdef_lsb(_reg_PHY_DLL_RST_EN)));
-	ddrphy_regif_idle();
-
-	/*
-	 * init start
-	 * dbdficnt0:
-	 * dfi_dram_clk_disable=1
-	 * dfi_frequency = 0
-	 * freq_ratio = 01 (2:1)
-	 * init_start =0
-	 */
-	foreach_vch(ch) {
-	    mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10U);
-	}
-	dsb_sev();
-
-	/*
-	 * dbdficnt0:
-	 * dfi_dram_clk_disable=1
-	 * dfi_frequency = 0
-	 * freq_ratio = 01 (2:1)
-	 * init_start =1
-	 */
-	foreach_vch(ch) {
-	    mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11U);
-	}
-	dsb_sev();
-
-	foreach_ech(ch) {
-		if ((board_cnf->phyvalid & BIT(ch)) != 0U) {
-			while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1fU) != 0x1fU) {
-			}
-		}
-	}
-	dsb_sev();
-}
-
-/* load table data into DDR registers */
-static void ddrtbl_load(void)
-{
-	uint32_t i;
-	uint32_t slice;
-	uint32_t csab;
-	uint32_t adr;
-	uint32_t data_l;
-	uint32_t tmp[3];
-	uint16_t dataS;
-
-	/*
-	 * TIMING REGISTERS
-	 * search jedec_spec1 index
-	 */
-	for (i = JS1_USABLEC_SPEC_LO; i < (uint32_t)JS1_FREQ_TBL_NUM - 1U; i++) {
-		if ((js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U) != 0U) {
-			break;
-		}
-	}
-	if (i > JS1_USABLEC_SPEC_HI) {
-		js1_ind = JS1_USABLEC_SPEC_HI;
-	} else {
-		js1_ind = i;
-	}
-
-	if (board_cnf->dbi_en != 0U) {
-		RL = js1[js1_ind].rlwdbi;
-	} else {
-		RL = js1[js1_ind].rlwodbi;
-	}
-
-	WL = js1[js1_ind].WL;
-
-	/* calculate jedec_spec2 */
-	_f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2);
-
-	/* PREPARE TBL */
-	if (prr_product == PRR_PRODUCT_M3) {
-		/*  G2M */
-		_tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
-			 DDR_PHY_SLICE_REGSET_G2M, DDR_PHY_SLICE_REGSET_NUM_G2M);
-		_tblcopy(_cnf_DDR_PHY_ADR_V_REGSET,
-			 DDR_PHY_ADR_V_REGSET_G2M, DDR_PHY_ADR_V_REGSET_NUM_G2M);
-		_tblcopy(_cnf_DDR_PHY_ADR_I_REGSET,
-			 DDR_PHY_ADR_I_REGSET_G2M, DDR_PHY_ADR_I_REGSET_NUM_G2M);
-		_tblcopy(_cnf_DDR_PHY_ADR_G_REGSET,
-			 DDR_PHY_ADR_G_REGSET_G2M, DDR_PHY_ADR_G_REGSET_NUM_G2M);
-		_tblcopy(_cnf_DDR_PI_REGSET,
-			 DDR_PI_REGSET_G2M, DDR_PI_REGSET_NUM_G2M);
-
-		DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_G2M;
-		DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_G2M;
-		DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_G2M;
-		DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_G2M;
-		DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_G2M;
-		DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_G2M;
-		DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_G2M;
-		DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_G2M;
-		DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_G2M;
-		DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_G2M;
-		DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_G2M;
-		DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_G2M;
-		DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_G2M;
-		DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_G2M;
-		DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_G2M;
-
-		DDR_PHY_ADR_I_NUM = 2U;
-	}
-
-	/* on fly gate adjust */
-	if ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10)) {
-		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
-			      _reg_ON_FLY_GATE_ADJUST_EN, 0x00);
-	}
-
-	/* Adjust PI parameters */
-#ifdef _def_LPDDR4_ODT
-	for (i = 0U; i < 2U; i++) {
-		for (csab = 0U; csab < CSAB_CNT; csab++) {
-			ddrtbl_setval(_cnf_DDR_PI_REGSET,
-				      reg_pi_mr11_data_fx_csx[i][csab],
-				      _def_LPDDR4_ODT);
-		}
-	}
-#endif /* _def_LPDDR4_ODT */
-
-#ifdef _def_LPDDR4_VREFCA
-	for (i = 0U; i < 2U; i++) {
-		for (csab = 0U; csab < CSAB_CNT; csab++) {
-			ddrtbl_setval(_cnf_DDR_PI_REGSET,
-				      reg_pi_mr12_data_fx_csx[i][csab],
-				      _def_LPDDR4_VREFCA);
-		}
-	}
-#endif /* _def_LPDDR4_VREFCA */
-
-	if ((js2[js2_tiedly]) >= 0x0eU) {
-		dataS = 0x0eU;
-	} else {
-		dataS = js2[js2_tiedly];
-	}
-
-	ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS);
-	ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY,
-		      (dataS - 2U));
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS);
-
-	if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD) != 0U) {
-		data_l = WL - 1U;
-	} else {
-		data_l = WL;
-	}
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, data_l - 2U);
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, data_l);
-
-	if (board_cnf->dbi_en != 0U) {
-		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE,
-			      0x01U);
-		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
-			      _reg_PHY_WDQLVL_DATADM_MASK, 0x000U);
-	} else {
-		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE,
-			      0x00U);
-		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
-			      _reg_PHY_WDQLVL_DATADM_MASK, 0x100U);
-	}
-
-	tmp[0] = js1[js1_ind].MR1;
-	tmp[1] = js1[js1_ind].MR2;
-	data_l = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0);
-	if (board_cnf->dbi_en != 0U) {
-		tmp[2] = data_l | 0xc0U;
-	} else {
-		tmp[2] = data_l & (~0xc0U);
-	}
-
-	for (i = 0U; i < 2U; i++) {
-		for (csab = 0U; csab < CSAB_CNT; csab++) {
-			ddrtbl_setval(_cnf_DDR_PI_REGSET,
-				      reg_pi_mr1_data_fx_csx[i][csab], tmp[0]);
-			ddrtbl_setval(_cnf_DDR_PI_REGSET,
-				      reg_pi_mr2_data_fx_csx[i][csab], tmp[1]);
-			ddrtbl_setval(_cnf_DDR_PI_REGSET,
-				      reg_pi_mr3_data_fx_csx[i][csab], tmp[2]);
-		}
-	}
-
-	/* DDRPHY INT START */
-	regif_pll_wa();
-	dbwait_loop(5U);
-
-	/* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
-			   BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
-	ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01U);
-
-	/* SET DATA SLICE TABLE */
-	for (slice = 0U; slice < SLICE_CNT; slice++) {
-		adr =
-		    DDR_PHY_SLICE_REGSET_OFS +
-		    DDR_PHY_SLICE_REGSET_SIZE * slice;
-		for (i = 0U; i < DDR_PHY_SLICE_REGSET_NUM; i++) {
-			reg_ddrphy_write_a(adr + i,
-					   _cnf_DDR_PHY_SLICE_REGSET[i]);
-		}
-	}
-
-	/* SET ADR SLICE TABLE */
-	adr = DDR_PHY_ADR_V_REGSET_OFS;
-	for (i = 0U; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
-		reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]);
-	}
-
-	if ((prr_product == PRR_PRODUCT_M3) &&
-	    ((0x00ffffffU & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40U))
-	    != 0x00U)) {
-		adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE;
-		for (i = 0U; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
-			reg_ddrphy_write_a(adr + i,
-					   _cnf_DDR_PHY_ADR_V_REGSET[i]);
-		}
-		ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
-			      _reg_PHY_ADR_DISABLE, 0x02);
-		DDR_PHY_ADR_I_NUM -= 1U;
-		ddr_phycaslice = 1U;
-
-#ifndef _def_LPDDR4_ODT
-		for (i = 0U; i < 2U; i++) {
-			for (csab = 0U; csab < CSAB_CNT; csab++) {
-				ddrtbl_setval(_cnf_DDR_PI_REGSET,
-					      reg_pi_mr11_data_fx_csx[i][csab],
-					      0x66);
-			}
-		}
-#endif/* _def_LPDDR4_ODT */
-	} else {
-		ddr_phycaslice = 0U;
-	}
-
-	if (DDR_PHY_ADR_I_NUM > 0U) {
-		for (slice = 0U; slice < DDR_PHY_ADR_I_NUM; slice++) {
-			adr =
-			    DDR_PHY_ADR_I_REGSET_OFS +
-			    DDR_PHY_ADR_I_REGSET_SIZE * slice;
-			for (i = 0U; i < DDR_PHY_ADR_I_REGSET_NUM; i++) {
-				reg_ddrphy_write_a(adr + i,
-						   _cnf_DDR_PHY_ADR_I_REGSET
-						   [i]);
-			}
-		}
-	}
-
-	/* SET ADRCTRL SLICE TABLE */
-	adr = DDR_PHY_ADR_G_REGSET_OFS;
-	for (i = 0U; i < DDR_PHY_ADR_G_REGSET_NUM; i++) {
-		reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]);
-	}
-
-	/* SET PI REGISTERS */
-	adr = DDR_PI_REGSET_OFS;
-	for (i = 0U; i < DDR_PI_REGSET_NUM; i++) {
-		reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]);
-	}
-}
-
-/* CONFIGURE DDR REGISTERS */
-static void ddr_config_sub(void)
-{
-	const uint32_t _par_CALVL_DEVICE_MAP = 1U;
-	uint8_t high_byte[SLICE_CNT];
-	uint32_t ch, slice;
-	uint32_t data_l;
-	uint32_t tmp;
-	uint32_t i;
-
-	foreach_vch(ch) {
-		/* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */
-		for (slice = 0U; slice < SLICE_CNT; slice++) {
-			high_byte[slice] =
-			    (board_cnf->ch[ch].dqs_swap >> (4U * slice)) % 2U;
-			ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0,
-				     board_cnf->ch[ch].dq_swap[slice]);
-			ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1,
-				     board_cnf->ch[ch].dm_swap[slice]);
-			if (high_byte[slice] != 0U) {
-				/* HIGHER 16 BYTE */
-				ddr_setval_s(ch, slice,
-					     _reg_PHY_CALVL_VREF_DRIVING_SLICE,
-					     0x00);
-			} else {
-				/* LOWER 16 BYTE */
-				ddr_setval_s(ch, slice,
-					     _reg_PHY_CALVL_VREF_DRIVING_SLICE,
-					     0x01);
-			}
-		}
-
-		/* BOARD SETTINGS (CA,ADDR_SEL) */
-		data_l = (0x00ffffffU & (uint32_t)(board_cnf->ch[ch].ca_swap)) |
-			0x00888888U;
-
-		/* --- ADR_CALVL_SWIZZLE --- */
-		if (prr_product == PRR_PRODUCT_M3) {
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l);
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0,
-				   0x00000000);
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l);
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1,
-				   0x00000000);
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP,
-				   _par_CALVL_DEVICE_MAP);
-		} else {
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l);
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000);
-			ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP,
-				   _par_CALVL_DEVICE_MAP);
-		}
-
-		/* --- ADR_ADDR_SEL --- */
-		data_l = 0U;
-		tmp = board_cnf->ch[ch].ca_swap;
-		for (i = 0U; i < 6U; i++) {
-			data_l |= ((tmp & 0x0fU) << (i * 5U));
-			tmp = tmp >> 4;
-		}
-		ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, data_l);
-		if (ddr_phycaslice == 1U) {
-			/* ----------- adr slice2 swap ----------- */
-			tmp  = (uint32_t)((board_cnf->ch[ch].ca_swap) >> 40);
-			data_l = (tmp & 0x00ffffffU) | 0x00888888U;
-
-			/* --- ADR_CALVL_SWIZZLE --- */
-			if (prr_product == PRR_PRODUCT_M3) {
-				ddr_setval_s(ch, 2,
-					     _reg_PHY_ADR_CALVL_SWIZZLE0_0,
-					     data_l);
-				ddr_setval_s(ch, 2,
-					     _reg_PHY_ADR_CALVL_SWIZZLE1_0,
-					     0x00000000);
-				ddr_setval_s(ch, 2,
-					     _reg_PHY_ADR_CALVL_SWIZZLE0_1,
-					     data_l);
-				ddr_setval_s(ch, 2,
-					     _reg_PHY_ADR_CALVL_SWIZZLE1_1,
-					     0x00000000);
-				ddr_setval_s(ch, 2,
-					     _reg_PHY_ADR_CALVL_DEVICE_MAP,
-					     _par_CALVL_DEVICE_MAP);
-			} else {
-				ddr_setval_s(ch, 2,
-					     _reg_PHY_ADR_CALVL_SWIZZLE0,
-					     data_l);
-				ddr_setval_s(ch, 2,
-					     _reg_PHY_ADR_CALVL_SWIZZLE1,
-					     0x00000000);
-				ddr_setval_s(ch, 2,
-					     _reg_PHY_CALVL_DEVICE_MAP,
-					     _par_CALVL_DEVICE_MAP);
-			}
-
-			/* --- ADR_ADDR_SEL --- */
-			data_l = 0U;
-			for (i = 0U; i < 6U; i++) {
-				data_l |= ((tmp & 0x0fU) << (i * 5U));
-				tmp = tmp >> 4U;
-			}
-
-			ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l);
-		}
-
-		/* BOARD SETTINGS (BYTE_ORDER_SEL) */
-		if (prr_product == PRR_PRODUCT_M3) {
-			/* --- DATA_BYTE_SWAP --- */
-			data_l = 0U;
-			tmp = board_cnf->ch[ch].dqs_swap;
-			for (i = 0U; i < 4U; i++) {
-				data_l |= ((tmp & 0x03U) << (i * 2U));
-				tmp = tmp >> 4U;
-			}
-		} else {
-			/* --- DATA_BYTE_SWAP --- */
-			data_l = board_cnf->ch[ch].dqs_swap;
-			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01);
-			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0,
-				   (data_l) & 0x0fU);
-			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1,
-				   (data_l >> 4U * 1U) & 0x0fU);
-			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2,
-				   (data_l >> 4U * 2U) & 0x0fU);
-			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3,
-				   (data_l >> 4U * 3U) & 0x0fU);
-
-			ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00U);
-		}
-		ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, data_l);
-	}
-}
-
-static void ddr_config(void)
-{
-	uint32_t num_cacs_dly = _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM;
-	uint32_t reg_ofs, dly;
-	uint32_t ch, slice;
-	uint32_t data_l;
-	uint32_t tmp;
-	uint32_t i;
-	int8_t _adj;
-	int16_t adj;
-	uint32_t dq;
-	union {
-		uint32_t ui32[4];
-		uint8_t ui8[16];
-	} patt;
-	uint16_t patm;
-
-	/* configure ddrphy registers */
-	ddr_config_sub();
-
-	/* WDQ_USER_PATT */
-	foreach_vch(ch) {
-		for (slice = 0U; slice < SLICE_CNT; slice++) {
-			patm = 0U;
-			for (i = 0U; i < 16U; i++) {
-				tmp = board_cnf->ch[ch].wdqlvl_patt[i];
-				patt.ui8[i] = tmp & 0xffU;
-				if ((tmp & 0x100U) != 0U) {
-					patm |= (1U << (uint16_t)i);
-				}
-			}
-			ddr_setval_s(ch, slice, _reg_PHY_USER_PATT0,
-				     patt.ui32[0]);
-			ddr_setval_s(ch, slice, _reg_PHY_USER_PATT1,
-				     patt.ui32[1]);
-			ddr_setval_s(ch, slice, _reg_PHY_USER_PATT2,
-				     patt.ui32[2]);
-			ddr_setval_s(ch, slice, _reg_PHY_USER_PATT3,
-				     patt.ui32[3]);
-			ddr_setval_s(ch, slice, _reg_PHY_USER_PATT4, patm);
-		}
-	}
-
-	/* CACS DLY */
-	data_l = board_cnf->cacs_dly + (uint32_t)_f_scale_adj(board_cnf->cacs_dly_adj);
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 0x00U);
-	foreach_vch(ch) {
-		for (i = 0U; i < num_cacs_dly - 4U; i++) {
-			adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
-			dly = _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i];
-			ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, dly,
-				      data_l + (uint32_t)adj);
-			reg_ofs = ddr_regdef_adr(dly) - DDR_PHY_ADR_V_REGSET_OFS;
-			reg_ddrphy_write(ch, ddr_regdef_adr(dly),
-					_cnf_DDR_PHY_ADR_V_REGSET[reg_ofs]);
-		}
-
-		for (i = num_cacs_dly - 4U; i < num_cacs_dly; i++) {
-			adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
-			dly = _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i];
-			ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, dly,
-				      data_l + (uint32_t)adj);
-			reg_ofs = ddr_regdef_adr(dly) - DDR_PHY_ADR_G_REGSET_OFS;
-			reg_ddrphy_write(ch, ddr_regdef_adr(dly),
-					_cnf_DDR_PHY_ADR_G_REGSET[reg_ofs]);
-		}
-
-		if (ddr_phycaslice == 1U) {
-			for (i = 0U; i < 6U; i++) {
-				adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i + num_cacs_dly]);
-				dly = _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i];
-				ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, dly,
-					      data_l + (uint32_t)adj);
-				reg_ofs = ddr_regdef_adr(dly) - DDR_PHY_ADR_V_REGSET_OFS;
-				reg_ddrphy_write(ch, ddr_regdef_adr(dly) + 0x0100U,
-						 _cnf_DDR_PHY_ADR_V_REGSET[reg_ofs]);
-			}
-		}
-	}
-
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
-			   BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
-
-	/* WDQDM DLY */
-	data_l = board_cnf->dqdm_dly_w;
-	foreach_vch(ch) {
-		for (slice = 0U; slice < SLICE_CNT; slice++) {
-			for (i = 0U; i <= 8U; i++) {
-				dq = slice * 8U + (uint32_t)i;
-				if (i == 8U) {
-					_adj = board_cnf->ch[ch].dm_adj_w[slice];
-				} else {
-					_adj = board_cnf->ch[ch].dq_adj_w[dq];
-				}
-				adj = _f_scale_adj(_adj);
-				ddr_setval_s(ch, slice,
-					     _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
-					     data_l + (uint32_t)adj);
-			}
-		}
-	}
-
-	/* RDQDM DLY */
-	data_l = board_cnf->dqdm_dly_r;
-	foreach_vch(ch) {
-		for (slice = 0U; slice < SLICE_CNT; slice++) {
-			for (i = 0U; i <= 8U; i++) {
-				dq = slice * 8U + (uint32_t)i;
-				if (i == 8U) {
-					_adj = board_cnf->ch[ch].dm_adj_r[slice];
-				} else {
-					_adj = board_cnf->ch[ch].dq_adj_r[dq];
-				}
-				adj = _f_scale_adj(_adj);
-				dly = _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i];
-				ddr_setval_s(ch, slice, dly, data_l + (uint32_t)adj);
-				dly = _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i];
-				ddr_setval_s(ch, slice, dly, data_l + (uint32_t)adj);
-			}
-		}
-	}
-}
-
-/* DBSC register setting functions */
-static void dbsc_regset_pre(void)
-{
-	uint32_t ch, csab;
-	uint32_t data_l;
-
-	/* PRIMARY SETTINGS */
-	/* LPDDR4, BL=16, DFI interface */
-	mmio_write_32(DBSC_DBKIND, 0x0000000aU);
-	mmio_write_32(DBSC_DBBL, 0x00000002U);
-	mmio_write_32(DBSC_DBPHYCONF0, 0x00000001U);
-
-	/* FREQRATIO=2 */
-	mmio_write_32(DBSC_DBSYSCONF1, 0x00000002U);
-
-	/*
-	 * DRAM SIZE REGISTER:
-	 * set all ranks as density=0(4Gb) for PHY initialization
-	 */
-	foreach_vch(ch) {
-		for (csab = 0U; csab < 4U; csab++) {
-			mmio_write_32(DBSC_DBMEMCONF(ch, csab),
-				      DBMEMCONF_REGD(0U));
-		}
-	}
-
-	if (prr_product == PRR_PRODUCT_M3) {
-		data_l = 0xe4e4e4e4U;
-		foreach_ech(ch) {
-			if ((ddr_phyvalid & (1U << ch)) != 0U) {
-				data_l = (data_l & (~(0x000000FFU << (ch * 8U))))
-					| (((board_cnf->ch[ch].dqs_swap & 0x0003U)
-					| ((board_cnf->ch[ch].dqs_swap & 0x0030U) >> 2U)
-					| ((board_cnf->ch[ch].dqs_swap & 0x0300U) >> 4U)
-					| ((board_cnf->ch[ch].dqs_swap & 0x3000U) >> 6U))
-					   << (ch * 8U));
-			}
-		}
-		mmio_write_32(DBSC_DBBSWAP, data_l);
-	}
-}
-
-static void dbsc_regset(void)
-{
-	int32_t i;
-	uint32_t ch;
-	uint32_t data_l;
-	uint32_t data_l2;
-	uint32_t wdql;
-	uint32_t dqenltncy;
-	uint32_t dql;
-	uint32_t dqienltncy;
-	uint32_t wrcslat;
-	uint32_t wrcsgap;
-	uint32_t rdcslat;
-	uint32_t rdcsgap;
-	uint32_t scfctst0_act_act;
-	uint32_t scfctst0_rda_act;
-	uint32_t scfctst0_wra_act;
-	uint32_t scfctst0_pre_act;
-	uint32_t scfctst1_rd_wr;
-	uint32_t scfctst1_wr_rd;
-	uint32_t scfctst1_act_rd_wr;
-	uint32_t scfctst1_asyncofs;
-	uint32_t dbschhrw1_sctrfcab;
-
-	/* RFC */
-	js2[js2_trfcab] =
-	    _f_scale(ddr_mbps, ddr_mbpsdiv,
-		     jedec_spec2_trfc_ab[max_density] * 1000U, 0U);
-	/* DBTR0.CL  : RL */
-	mmio_write_32(DBSC_DBTR(0), RL);
-
-	/* DBTR1.CWL : WL */
-	mmio_write_32(DBSC_DBTR(1), WL);
-
-	/* DBTR2.AL  : 0 */
-	mmio_write_32(DBSC_DBTR(2), 0U);
-
-	/* DBTR3.TRCD: tRCD */
-	mmio_write_32(DBSC_DBTR(3), js2[js2_trcd]);
-
-	/* DBTR4.TRPA,TRP: tRPab,tRPpb */
-	mmio_write_32(DBSC_DBTR(4), (js2[js2_trpab] << 16) | js2[js2_trppb]);
-
-	/* DBTR5.TRC : use tRCpb */
-	mmio_write_32(DBSC_DBTR(5), js2[js2_trcpb]);
-
-	/* DBTR6.TRAS : tRAS */
-	mmio_write_32(DBSC_DBTR(6), js2[js2_tras]);
-
-	/* DBTR7.TRRD : tRRD */
-	mmio_write_32(DBSC_DBTR(7), (js2[js2_trrd] << 16) | js2[js2_trrd]);
-
-	/* DBTR8.TFAW : tFAW */
-	mmio_write_32(DBSC_DBTR(8), js2[js2_tfaw]);
-
-	/* DBTR9.TRDPR : tRTP */
-	mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]);
-
-	/* DBTR10.TWR : nWR */
-	mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr);
-
-	/*
-	 * DBTR11.TRDWR : RL +  BL / 2 + Rounddown(tRPST) + PHY_ODTLoff -
-	 * odtlon + tDQSCK - tODTon,min +
-	 * PCB delay (out+in) + tPHY_ODToff
-	 */
-	mmio_write_32(DBSC_DBTR(11),
-		      RL + (16U / 2U) + 1U + 2U - js1[js1_ind].odtlon +
-		      js2[js2_tdqsck] - js2[js2_tODTon_min] +
-		      _f_scale(ddr_mbps, ddr_mbpsdiv, 1300, 0));
-
-	/* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */
-	data_l = WL + 1U + (16U / 2U) + js2[js2_twtr];
-	mmio_write_32(DBSC_DBTR(12), (data_l << 16) | data_l);
-
-	/* DBTR13.TRFCAB : tRFCab */
-	mmio_write_32(DBSC_DBTR(13), js2[js2_trfcab]);
-
-	/* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */
-	mmio_write_32(DBSC_DBTR(14),
-		      (js2[js2_tckehcmd] << 16) | (js2[js2_tckehcmd]));
-
-	/* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */
-	mmio_write_32(DBSC_DBTR(15), (js2[js2_tsr] << 16) | (js2[js2_tckelpd]));
-
-	/* DBTR16 */
-	/* WDQL : tphy_wrlat + tphy_wrdata */
-	wdql = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1);
-	/* DQENLTNCY : tphy_wrlat = WL-2 : PHY_WRITE_PATH_LAT_ADD == 0
-	 *             tphy_wrlat = WL-3 : PHY_WRITE_PATH_LAT_ADD != 0
-	 */
-	dqenltncy = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1);
-	/* DQL : tphy_rdlat + trdata_en */
-	/* it is not important for dbsc */
-	dql = RL + 16U;
-	/* DQIENLTNCY : trdata_en */
-	dqienltncy = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1) - 1U;
-	mmio_write_32(DBSC_DBTR(16),
-		      (dqienltncy << 24) | (dql << 16) | (dqenltncy << 8) | wdql);
-
-	/* DBTR24 */
-	/* WRCSLAT = WRLAT -5 */
-	wrcslat = wdql - 5U;
-	/* WRCSGAP = 5 */
-	wrcsgap = 5U;
-	/* RDCSLAT = RDLAT_ADJ +2 */
-	rdcslat = dqienltncy;
-	if (prr_product != PRR_PRODUCT_M3) {
-		rdcslat += 2U;
-	}
-	/* RDCSGAP = 6 */
-	rdcsgap = 6U;
-	if (prr_product == PRR_PRODUCT_M3) {
-		rdcsgap = 4U;
-	}
-	mmio_write_32(DBSC_DBTR(24),
-		      (rdcsgap << 24) | (rdcslat << 16) | (wrcsgap << 8) | wrcslat);
-
-	/* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0) */
-	mmio_write_32(DBSC_DBTR(17),
-		      (js2[js2_tmrr] << 24) | (js2[js2_tmrd] << 16));
-
-	/* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */
-	mmio_write_32(DBSC_DBTR(18), 0);
-
-	/* DBTR19.TZQCL, TZQCS : do not use in LPDDR4 */
-	mmio_write_32(DBSC_DBTR(19), 0);
-
-	/* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */
-	data_l = js2[js2_trfcab] + js2[js2_tckehcmd];
-	mmio_write_32(DBSC_DBTR(20), (data_l << 16) | data_l);
-
-	/* DBTR21.TCCD */
-	/* DBTR23.TCCD */
-	if (ddr_tccd == 8U) {
-		data_l = 8U;
-		mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
-		mmio_write_32(DBSC_DBTR(23), 0x00000002);
-	} else if (ddr_tccd <= 11U) {
-		data_l = 11U;
-		mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
-		mmio_write_32(DBSC_DBTR(23), 0x00000000);
-	} else {
-		data_l = ddr_tccd;
-		mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
-		mmio_write_32(DBSC_DBTR(23), 0x00000000);
-	}
-
-	/* DBTR22.ZQLAT : */
-	data_l = js2[js2_tzqcalns] * 100U;	/*  1000 * 1000 ps */
-	data_l = (data_l << 16U) | (js2[js2_tzqlat] + 24U + 20U);
-	mmio_write_32(DBSC_DBTR(22), data_l);
-
-	/* DBTR25 : do not use in LPDDR4 */
-	mmio_write_32(DBSC_DBTR(25), 0U);
-
-	/*
-	 * DBRNK :
-	 * DBSC_DBRNK2 rkrr
-	 * DBSC_DBRNK3 rkrw
-	 * DBSC_DBRNK4 rkwr
-	 * DBSC_DBRNK5 rkww
-	 */
-#define _par_DBRNK_VAL	(0x7007U)
-
-	for (i = 0; i < 4; i++) {
-		data_l = (_par_DBRNK_VAL >> ((uint32_t)i * 4U)) & 0x0fU;
-		data_l2 = 0U;
-		foreach_vch(ch) {
-			data_l2 = data_l2 | (data_l << (4U * ch));
-		}
-		mmio_write_32(DBSC_DBRNK(2 + i), data_l2);
-	}
-	mmio_write_32(DBSC_DBADJ0, 0x00000000U);
-
-	/* timing registers for scheduler */
-	/* SCFCTST0 */
-	/* SCFCTST0 ACT-ACT */
-	scfctst0_act_act = js2[js2_trcpb] * 800UL * ddr_mbpsdiv / ddr_mbps;
-	/* SCFCTST0 RDA-ACT */
-	scfctst0_rda_act = ((16U / 2U) + js2[js2_trtp] - 8U +
-		  js2[js2_trppb]) * 800UL * ddr_mbpsdiv / ddr_mbps;
-	/* SCFCTST0 WRA-ACT */
-	scfctst0_wra_act = (WL + 1U + (16U / 2U) +
-		  js1[js1_ind].nwr) * 800UL * ddr_mbpsdiv / ddr_mbps;
-	/* SCFCTST0 PRE-ACT */
-	scfctst0_pre_act = js2[js2_trppb];
-	mmio_write_32(DBSC_SCFCTST0,
-		      (scfctst0_act_act << 24) | (scfctst0_rda_act << 16) |
-		      (scfctst0_wra_act << 8) | scfctst0_pre_act);
-
-	/* SCFCTST1 */
-	/* SCFCTST1 RD-WR */
-	scfctst1_rd_wr = (mmio_read_32(DBSC_DBTR(11)) & 0xffU) * 800UL * ddr_mbpsdiv /
-		ddr_mbps;
-	/* SCFCTST1 WR-RD */
-	scfctst1_wr_rd = (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800UL * ddr_mbpsdiv /
-		ddr_mbps;
-	/* SCFCTST1 ACT-RD/WR */
-	scfctst1_act_rd_wr = js2[js2_trcd] * 800UL * ddr_mbpsdiv / ddr_mbps;
-	/* SCFCTST1 ASYNCOFS */
-	scfctst1_asyncofs = 12U;
-	mmio_write_32(DBSC_SCFCTST1,
-		      (scfctst1_rd_wr << 24) | (scfctst1_wr_rd << 16) |
-		      (scfctst1_act_rd_wr << 8) | scfctst1_asyncofs);
-
-	/* DBSCHRW1 */
-	/* DBSCHRW1 SCTRFCAB */
-	dbschhrw1_sctrfcab = js2[js2_trfcab] * 800UL * ddr_mbpsdiv / ddr_mbps;
-	data_l = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000U) >> 16) +
-		  (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFFU) +
-		  (0x28U * 2U)) * 400U * 2U * ddr_mbpsdiv / ddr_mbps + 7U;
-	if (dbschhrw1_sctrfcab < data_l) {
-		dbschhrw1_sctrfcab = data_l;
-	}
-
-	if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) {
-		mmio_write_32(DBSC_DBSCHRW1, dbschhrw1_sctrfcab +
-			      ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFFU) *
-			       400U * 2U * ddr_mbpsdiv + (ddr_mbps - 1U)) / ddr_mbps - 3U);
-	} else {
-		mmio_write_32(DBSC_DBSCHRW1, dbschhrw1_sctrfcab +
-			      ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFFU) *
-			       400U * 2U * ddr_mbpsdiv + (ddr_mbps - 1U)) / ddr_mbps);
-	}
-
-	/* QOS and CAM */
-#ifdef DDR_QOS_INIT_SETTING	/*  only for non qos_init */
-	/* wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) */
-	mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218U);
-	/* 0(fillunit),8(dirtymax),4(dirtymin) */
-	mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4U);
-	/* stop_tolerance */
-	mmio_write_32(DBSC_DBSCHRW0, 0x22421111U);
-	/* rd-wr/wr-rd toggle priority */
-	mmio_write_32(DBSC_SCFCTST2, 0x012F1123U);
-	mmio_write_32(DBSC_DBSCHSZ0, 0x00000001U);
-	mmio_write_32(DBSC_DBSCHCNT0, 0x000F0037U);
-
-	/* QoS Settings */
-	mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
-	mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
-	mmio_write_32(DBSC_DBSCHQOS02, 0x00000000U);
-	mmio_write_32(DBSC_DBSCHQOS03, 0x00000000U);
-	mmio_write_32(DBSC_DBSCHQOS40, 0x00000300U);
-	mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
-	mmio_write_32(DBSC_DBSCHQOS42, 0x00000200U);
-	mmio_write_32(DBSC_DBSCHQOS43, 0x00000100U);
-	mmio_write_32(DBSC_DBSCHQOS90, 0x00000100U);
-	mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
-	mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
-	mmio_write_32(DBSC_DBSCHQOS93, 0x00000040U);
-	mmio_write_32(DBSC_DBSCHQOS120, 0x00000040U);
-	mmio_write_32(DBSC_DBSCHQOS121, 0x00000030U);
-	mmio_write_32(DBSC_DBSCHQOS122, 0x00000020U);
-	mmio_write_32(DBSC_DBSCHQOS123, 0x00000010U);
-	mmio_write_32(DBSC_DBSCHQOS130, 0x00000100U);
-	mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
-	mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
-	mmio_write_32(DBSC_DBSCHQOS133, 0x00000040U);
-	mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
-	mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
-	mmio_write_32(DBSC_DBSCHQOS142, 0x00000080U);
-	mmio_write_32(DBSC_DBSCHQOS143, 0x00000040U);
-	mmio_write_32(DBSC_DBSCHQOS150, 0x00000040U);
-	mmio_write_32(DBSC_DBSCHQOS151, 0x00000030U);
-	mmio_write_32(DBSC_DBSCHQOS152, 0x00000020U);
-	mmio_write_32(DBSC_DBSCHQOS153, 0x00000010U);
-
-	mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
-#endif /* DDR_QOS_INIT_SETTING */
-
-	/* resrdis */
-	mmio_write_32(DBSC_DBBCAMDIS, 0x00000001U);
-}
-
-static void dbsc_regset_post(void)
-{
-	uint32_t slice, rdlat_max, rdlat_min;
-	uint32_t ch, cs;
-	uint32_t data_l;
-	uint32_t srx;
-
-	rdlat_max = 0U;
-	rdlat_min = 0xffffU;
-	foreach_vch(ch) {
-		for (cs = 0U; cs < CS_CNT; cs++) {
-			if ((ch_have_this_cs[cs] & (1U << ch)) != 0U) {
-				for (slice = 0U; slice < SLICE_CNT; slice++) {
-					ddr_setval_s(ch, slice,
-						     _reg_PHY_PER_CS_TRAINING_INDEX,
-						     cs);
-					data_l = ddr_getval_s(ch, slice,
-							      _reg_PHY_RDDQS_LATENCY_ADJUST);
-					if (data_l > rdlat_max) {
-						rdlat_max = data_l;
-					}
-					if (data_l < rdlat_min) {
-						rdlat_min = data_l;
-					}
-				}
-			}
-		}
-	}
-
-	mmio_write_32(DBSC_DBTR(24),
-		      ((rdlat_max + 2U) << 24) +
-		      ((rdlat_max + 2U) << 16) +
-		      mmio_read_32(DBSC_DBTR(24)));
-
-	/* set ddr density information */
-	foreach_ech(ch) {
-		for (cs = 0U; cs < CS_CNT; cs++) {
-			if (ddr_density[ch][cs] == 0xffU) {
-				mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00U);
-			} else {
-				mmio_write_32(DBSC_DBMEMCONF(ch, cs),
-					      DBMEMCONF_REGD(ddr_density[ch]
-							     [cs]));
-			}
-		}
-		mmio_write_32(DBSC_DBMEMCONF(ch, 2), 0x00000000U);
-		mmio_write_32(DBSC_DBMEMCONF(ch, 3), 0x00000000U);
-	}
-
-	mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010U);
-
-	/* set DBI */
-	if (board_cnf->dbi_en != 0U) {
-		mmio_write_32(DBSC_DBDBICNT, 0x00000003U);
-	}
-
-	/* set REFCYCLE */
-	data_l = (get_refperiod()) * ddr_mbps / 2000U / ddr_mbpsdiv;
-	mmio_write_32(DBSC_DBRFCNF1, 0x00080000U | (data_l & 0x0000ffffU));
-	mmio_write_32(DBSC_DBRFCNF2, 0x00010000U | DBSC_REFINTS);
-
-#if RCAR_REWT_TRAINING != 0
-	/* Periodic-WriteDQ Training seeting */
-	if ((prr_product == PRR_PRODUCT_M3) &&
-	    (prr_cut == PRR_PRODUCT_10)) {
-		/* G2M Ver.1.0 not support */
-	} else {
-		/* G2M Ver.1.1 or later */
-		mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000U);
-
-		ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04U);
-		ddr_setval_ach_as(_reg_PHY_WDQLVL_QTR_DLY_STEP, 0x0FU);
-		ddr_setval_ach_as(_reg_PHY_WDQLVL_DLY_STEP, 0x50U);
-		ddr_setval_ach_as(_reg_PHY_WDQLVL_DQDM_SLV_DLY_START, 0x0300U);
-
-		ddr_setval_ach(_reg_PI_WDQLVL_CS_MAP,
-			       ddrtbl_getval(_cnf_DDR_PI_REGSET,
-					     _reg_PI_WDQLVL_CS_MAP));
-		ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1fU);
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00U);
-		ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01U);
-		ddr_setval_ach(_reg_PI_TREF_F0, 0x0000U);
-		ddr_setval_ach(_reg_PI_TREF_F1, 0x0000U);
-		ddr_setval_ach(_reg_PI_TREF_F2, 0x0000U);
-
-		if (prr_product == PRR_PRODUCT_M3) {
-			ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02U);
-		} else {
-			ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02U);
-		}
-		ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01U);
-
-		/* DFI_PHYMSTR_ACK , WTmode setting */
-		/* DFI_PHYMSTR_ACK: WTmode =b'01 */
-		mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011U);
-	}
-#endif /* RCAR_REWT_TRAINING */
-	/* periodic dram zqcal enable */
-	mmio_write_32(DBSC_DBCALCNF, 0x01000010U);
-
-	/* periodic phy ctrl update enable */
-	if ((prr_product == PRR_PRODUCT_M3) &&
-	    (prr_cut < PRR_PRODUCT_30)) {
-		/* non : G2M Ver.1.x not support */
-	} else {
-		mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001U);
-	}
-
-#ifdef DDR_BACKUPMODE
-	/* SRX */
-	srx = 0x0A840001U; /* for All channels */
-	if (ddr_backup == DRAM_BOOT_STATUS_WARM) {
-#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0, 1 only) */
-		NOTICE("BL2: [DEBUG_MESS] DDR_BACKUPMODE_HALF\n");
-		srx = 0x0A040001U;
-#endif /* DDR_BACKUPMODE_HALF */
-		send_dbcmd(srx);
-	}
-#endif /* DDR_BACKUPMODE */
-
-	/* set Auto Refresh */
-	mmio_write_32(DBSC_DBRFEN, 0x00000001U);
-
-#if RCAR_REWT_TRAINING != 0
-	/* Periodic WriteDQ Traning */
-	if ((prr_product == PRR_PRODUCT_M3) &&
-	    (prr_cut == PRR_PRODUCT_10)) {
-		/* non : G2M Ver.1.0 not support */
-	} else {
-		/* G2M Ver.1.1 or later */
-		ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100U);
-	}
-#endif /* RCAR_REWT_TRAINING */
-
-	/* dram access enable */
-	mmio_write_32(DBSC_DBACEN, 0x00000001U);
-
-	MSG_LF(__func__ "(done)");
-}
-
-/* DFI_INIT_START */
-static uint32_t dfi_init_start(void)
-{
-	uint32_t ch;
-	uint32_t phytrainingok;
-	uint32_t retry;
-	uint32_t data_l;
-	uint32_t ret = 0U;
-	const uint32_t RETRY_MAX = 0x10000U;
-
-	ddr_setval_ach_as(_reg_PHY_DLL_RST_EN, 0x02U);
-	dsb_sev();
-	ddrphy_regif_idle();
-
-	/* dll_rst negate */
-	foreach_vch(ch) {
-	    mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01U);
-	}
-	dsb_sev();
-
-	/* wait init_complete */
-	phytrainingok = 0U;
-	retry = 0U;
-	while (retry++ < RETRY_MAX) {
-		foreach_vch(ch) {
-			data_l = mmio_read_32(DBSC_DBDFISTAT(ch));
-			if (data_l & 0x00000001U)  {
-				phytrainingok |= (1U << ch);
-			}
-		}
-		dsb_sev();
-		if (phytrainingok == ddr_phyvalid)  {
-			break;
-		}
-		if (retry % 256U == 0U) {
-			ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01U);
-		}
-	}
-
-	/* all ch ok? */
-	if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) {
-		ret = 0xffU;
-		goto done;
-	}
-
-	/*
-	 * dbdficnt0:
-	 * dfi_dram_clk_disable=0
-	 * dfi_frequency = 0
-	 * freq_ratio = 01 (2:1)
-	 * init_start =0
-	 */
-	foreach_vch(ch) {
-	    mmio_write_32(DBSC_DBDFICNT(ch), 0x00000010U);
-	}
-	dsb_sev();
-done:
-	return ret;
-}
-
-/* drivability setting : CMOS MODE ON/OFF */
-static void change_lpddr4_en(uint32_t mode)
-{
-	uint32_t ch;
-	uint32_t i;
-	uint32_t data_l;
-	const uint32_t _reg_PHY_PAD_DRIVE_X[3] = {
-		_reg_PHY_PAD_ADDR_DRIVE,
-		_reg_PHY_PAD_CLK_DRIVE,
-		_reg_PHY_PAD_CS_DRIVE
-	};
-
-	foreach_vch(ch) {
-		for (i = 0U; i < 3U; i++) {
-			data_l = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]);
-			if (mode != 0U) {
-				data_l |= (1U << 14);
-			} else {
-				data_l &= ~(1U << 14);
-			}
-			ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], data_l);
-		}
-	}
-}
-
-/* drivability setting */
-static uint32_t set_term_code(void)
-{
-	uint32_t i;
-	uint32_t ch, index;
-	uint32_t data_l;
-	uint32_t chip_id[2];
-	uint32_t term_code;
-	uint32_t override;
-
-	term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-				  _reg_PHY_PAD_DATA_TERM);
-	override = 0U;
-	for (i = 0U; i < 2U; i++) {
-		chip_id[i] = mmio_read_32(LIFEC_CHIPID(i));
-	}
-
-	index = 0U;
-	while (true) {
-		if (termcode_by_sample[index][0] == 0xffffffff) {
-			break;
-		}
-		if ((termcode_by_sample[index][0] == chip_id[0]) &&
-		    (termcode_by_sample[index][1] == chip_id[1])) {
-			term_code = termcode_by_sample[index][2];
-			override = 1;
-			break;
-		}
-		index++;
-	}
-
-	if (override != 0U) {
-		for (index = 0U; index < _reg_PHY_PAD_TERM_X_NUM; index++) {
-			data_l =
-			    ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-					  _reg_PHY_PAD_TERM_X[index]);
-			data_l = (data_l & 0xfffe0000U) | term_code;
-			ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], data_l);
-		}
-	} else if ((prr_product == PRR_PRODUCT_M3) &&
-		   (prr_cut == PRR_PRODUCT_10)) {
-		/*  non */
-	} else {
-		ddr_setval_ach(_reg_PHY_PAD_TERM_X[0],
-			       (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-					      _reg_PHY_PAD_TERM_X[0]) & 0xFFFE0000U));
-		ddr_setval_ach(_reg_PHY_CAL_CLEAR_0, 0x01U);
-		ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01U);
-		foreach_vch(ch) {
-			do {
-				data_l =
-				    ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0);
-			} while (!(data_l & 0x00800000U));
-		}
-
-		/* G2M Ver.1.1 or later */
-		foreach_vch(ch) {
-			for (index = 0U; index < _reg_PHY_PAD_TERM_X_NUM;
-			     index++) {
-				data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[index]);
-				ddr_setval(ch, _reg_PHY_PAD_TERM_X[index],
-					   (data_l & 0xFFFE0FFFU) | 0x00015000U);
-			}
-		}
-	}
-
-	ddr_padcal_tcompensate_getinit(override);
-
-	return 0U;
-}
-
-/* DDR mode register setting */
-static void ddr_register_set(void)
-{
-	int32_t fspwp;
-	uint32_t tmp;
-
-	for (fspwp = 1; fspwp >= 0; fspwp--) {
-		/*MR13, fspwp */
-		send_dbcmd(0x0e840d08U | ((2U - fspwp) << 6));
-
-		tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
-				    reg_pi_mr1_data_fx_csx[fspwp][0]);
-		send_dbcmd(0x0e840100U | tmp);
-
-		tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
-				    reg_pi_mr2_data_fx_csx[fspwp][0]);
-		send_dbcmd(0x0e840200U | tmp);
-
-		tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
-				    reg_pi_mr3_data_fx_csx[fspwp][0]);
-		send_dbcmd(0x0e840300U | tmp);
-
-		tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
-				    reg_pi_mr11_data_fx_csx[fspwp][0]);
-		send_dbcmd(0x0e840b00U | tmp);
-
-		tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
-				    reg_pi_mr12_data_fx_csx[fspwp][0]);
-		send_dbcmd(0x0e840c00U | tmp);
-
-		tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
-				    reg_pi_mr14_data_fx_csx[fspwp][0]);
-		send_dbcmd(0x0e840e00U | tmp);
-		/* MR22 */
-		send_dbcmd(0x0e841616U);
-
-		/* ZQCAL start */
-		send_dbcmd(0x0d84004FU);
-
-		/* ZQLAT */
-		send_dbcmd(0x0d840051U);
-	}
-
-	/* MR13, fspwp */
-	send_dbcmd(0x0e840d08U);
-}
-
-/* Training handshake functions */
-static inline uint32_t wait_freqchgreq(uint32_t assert)
-{
-	uint32_t data_l;
-	uint32_t count;
-	uint32_t ch;
-
-	count = 100000U;
-
-	if (assert != 0U) {
-		do {
-			data_l = 1U;
-			foreach_vch(ch) {
-				data_l &= mmio_read_32(DBSC_DBPDSTAT(ch));
-			}
-			count = count - 1U;
-		} while (((data_l & 0x01U) != 0x01U) && (count != 0U));
-	} else {
-		do {
-			data_l = 0U;
-			foreach_vch(ch) {
-				data_l |= mmio_read_32(DBSC_DBPDSTAT(ch));
-			}
-			count = count - 1U;
-		} while (((data_l & 0x01U) != 0x00U) && (count != 0U));
-	}
-
-	return (count == 0U);
-}
-
-static inline void set_freqchgack(uint32_t assert)
-{
-	uint32_t ch;
-	uint32_t data_l;
-
-	if (assert != 0U) {
-		data_l = 0x0CF20000U;
-	} else {
-		data_l = 0x00000000U;
-	}
-
-	foreach_vch(ch) {
-	    mmio_write_32(DBSC_DBPDCNT2(ch), data_l);
-	}
-}
-
-static inline void set_dfifrequency(uint32_t freq)
-{
-	uint32_t ch;
-
-	foreach_vch(ch) {
-		mmio_clrsetbits_32(DBSC_DBDFICNT(ch), 0x1fU << 24, freq << 24);
-	}
-	dsb_sev();
-}
-
-static uint32_t pll3_freq(uint32_t on)
-{
-	uint32_t timeout;
-
-	timeout = wait_freqchgreq(1U);
-
-	if (timeout != 0U) {
-		return 1U;
-	}
-
-	pll3_control(on);
-	set_dfifrequency(on);
-
-	set_freqchgack(1U);
-	timeout = wait_freqchgreq(0U);
-	set_freqchgack(0U);
-
-	if (timeout != 0U) {
-		FATAL_MSG("BL2: Time out[2]\n");
-		return 1U;
-	}
-
-	return 0U;
-}
-
-/* update dly */
-static void update_dly(void)
-{
-	ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01U);
-	ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01U);
-}
-
-/* training by pi */
-static uint32_t pi_training_go(void)
-{
-	uint32_t flag;
-	uint32_t data_l;
-	uint32_t retry;
-	const uint32_t RETRY_MAX = 4096U * 16U;
-	uint32_t ch;
-	uint32_t mst_ch;
-	uint32_t cur_frq;
-	uint32_t complete;
-	uint32_t frqchg_req;
-
-	/* pi_start */
-	ddr_setval_ach(_reg_PI_START, 0x01U);
-	foreach_vch(ch) {
-	    ddr_getval(ch, _reg_PI_INT_STATUS);
-	}
-
-	/* set dfi_phymstr_ack = 1 */
-	mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001U);
-	dsb_sev();
-
-	/* wait pi_int_status[0] */
-	mst_ch = 0U;
-	flag = 0U;
-	complete = 0U;
-	cur_frq = 0U;
-	for (retry = 0U; retry < RETRY_MAX; retry++) {
-		frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01;
-
-		if (frqchg_req != 0U) {
-			if (cur_frq != 0U) {
-				/* Low frequency */
-				flag = pll3_freq(0U);
-				cur_frq = 0U;
-			} else {
-				/* High frequency */
-				flag = pll3_freq(1U);
-				cur_frq = 1U;
-			}
-			if (flag != 0U) {
-				break;
-			}
-		} else {
-			if (cur_frq != 0U) {
-				foreach_vch(ch) {
-					if ((complete & (1U << ch)) != 0U) {
-						continue;
-					}
-					data_l = ddr_getval(ch, _reg_PI_INT_STATUS);
-					if ((data_l & 0x01U) != 0U) {
-						complete |= (1U << ch);
-					}
-				}
-				if (complete == ddr_phyvalid) {
-					break;
-				}
-			}
-		}
-	}
-	foreach_vch(ch) {
-		/* dummy read */
-		data_l = ddr_getval_s(ch, 0U, _reg_PHY_CAL_RESULT2_OBS_0);
-		data_l = ddr_getval(ch, _reg_PI_INT_STATUS);
-		ddr_setval(ch, _reg_PI_INT_ACK, data_l);
-	}
-	if (ddrphy_regif_chk() != 0U) {
-		complete = 0xfdU;
-	}
-	return complete;
-}
-
-/* Initialize DDR */
-static uint32_t init_ddr(void)
-{
-	uint32_t i;
-	uint32_t data_l;
-	uint32_t phytrainingok;
-	uint32_t ch, slice;
-	uint32_t index;
-	uint32_t err;
-	int16_t adj;
-
-	MSG_LF(__func__ ":0\n");
-
-	/* unlock phy */
-	/* Unlock DDRPHY register(AGAIN) */
-	foreach_vch(ch) {
-	    mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55AU);
-	}
-	dsb_sev();
-
-	reg_ddrphy_write_a(0x00001010U, 0x00000001U);
-	/* DBSC register pre-setting */
-	dbsc_regset_pre();
-
-	/* load ddrphy registers */
-	ddrtbl_load();
-
-	/* configure ddrphy registers */
-	ddr_config();
-
-	/* dfi_reset assert */
-	foreach_vch(ch) {
-	    mmio_write_32(DBSC_DBPDCNT0(ch), 0x01U);
-	}
-	dsb_sev();
-
-	/* dbsc register set */
-	dbsc_regset();
-	MSG_LF(__func__ ":1\n");
-
-	/* dfi_reset negate */
-	foreach_vch(ch) {
-	    mmio_write_32(DBSC_DBPDCNT0(ch), 0x00U);
-	}
-	dsb_sev();
-
-	/* dfi_init_start (start ddrphy) */
-	err = dfi_init_start();
-	if (err != 0U) {
-		return INITDRAM_ERR_I;
-	}
-	MSG_LF(__func__ ":2\n");
-
-	/* ddr backupmode end */
-#ifdef DDR_BACKUPMODE
-	if (ddr_backup != 0U) {
-		NOTICE("BL2: [WARM_BOOT]\n");
-	} else {
-		NOTICE("BL2: [COLD_BOOT]\n");
-	}
-#endif
-	MSG_LF(__func__ ":3\n");
-
-	/* override term code after dfi_init_complete */
-	err = set_term_code();
-	if (err != 0U) {
-		return INITDRAM_ERR_I;
-	}
-	MSG_LF(__func__ ":4\n");
-
-	/* rx offset calibration */
-	if (prr_cut > PRR_PRODUCT_11) {
-		err = rx_offset_cal_hw();
-	} else {
-		err = rx_offset_cal();
-	}
-	if (err != 0U) {
-		return INITDRAM_ERR_O;
-	}
-	MSG_LF(__func__ ":5\n");
-
-	/* Dummy PDE */
-	send_dbcmd(0x08840000U);
-
-	/* PDX */
-	send_dbcmd(0x08840001U);
-
-	/* check register i/f is alive */
-	err = ddrphy_regif_chk();
-	if (err != 0U) {
-		return INITDRAM_ERR_O;
-	}
-	MSG_LF(__func__ ":6\n");
-
-	/* phy initialize end */
-
-	/* setup DDR mode registers */
-	/* CMOS MODE */
-	change_lpddr4_en(0);
-
-	/* MRS */
-	ddr_register_set();
-
-	/* Thermal sensor setting */
-	/* THCTR Bit6: PONM=0 , Bit0: THSST=1  */
-	data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBFU) | 0x00000001U;
-	mmio_write_32(THS1_THCTR, data_l);
-
-	/* LPDDR4 MODE */
-	change_lpddr4_en(1);
-
-	MSG_LF(__func__ ":7\n");
-
-	/* mask CS_MAP if RANKx is not found */
-	foreach_vch(ch) {
-		data_l = ddr_getval(ch, _reg_PI_CS_MAP);
-		if ((ch_have_this_cs[1] & (1U << ch)) == 0U) {
-			data_l = data_l & 0x05U;
-		}
-		ddr_setval(ch, _reg_PI_CS_MAP, data_l);
-	}
-
-	/* exec pi_training */
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
-			   BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
-	ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00U);
-
-	foreach_vch(ch) {
-		for (slice = 0U; slice < SLICE_CNT; slice++) {
-			ddr_setval_s(ch, slice,
-				     _reg_PHY_PER_CS_TRAINING_EN,
-				     ((ch_have_this_cs[1]) >> ch) & 0x01U);
-		}
-	}
-
-	phytrainingok = pi_training_go();
-
-	if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) {
-		return INITDRAM_ERR_T | phytrainingok;
-	}
-
-	MSG_LF(__func__ ":8\n");
-
-	/* CACS DLY ADJUST */
-	data_l = board_cnf->cacs_dly + (uint32_t)_f_scale_adj(board_cnf->cacs_dly_adj);
-	foreach_vch(ch) {
-		for (i = 0U; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
-			adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
-			ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
-				   data_l + (uint32_t)adj);
-		}
-
-		if (ddr_phycaslice == 1U) {
-			for (i = 0U; i < 6U; i++) {
-				index = i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM;
-				adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[index]);
-				ddr_setval_s(ch, 2U,
-					     _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
-					     data_l + (uint32_t)adj);
-			}
-		}
-	}
-
-	update_dly();
-	MSG_LF(__func__ ":9\n");
-
-	/* Adjust write path latency */
-	if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD) != 0U) {
-		adjust_wpath_latency();
-	}
-
-	/* RDQLVL Training */
-	if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0U) {
-		ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01U);
-	}
-
-	err = rdqdm_man();
-
-	if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0U) {
-		ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00U);
-	}
-
-	if (err != 0U) {
-		return INITDRAM_ERR_T;
-	}
-	update_dly();
-	MSG_LF(__func__ ":10\n");
-
-	/* WDQLVL Training */
-	err = wdqdm_man();
-	if (err != 0U) {
-		return INITDRAM_ERR_T;
-	}
-	update_dly();
-	MSG_LF(__func__ ":11\n");
-
-	dbsc_regset_post();
-	MSG_LF(__func__ ":12\n");
-
-	return phytrainingok;
-}
-
-/* SW LEVELING COMMON */
-static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick)
-{
-	const uint32_t RETRY_MAX = 0x1000U;
-	uint32_t ch, data_l;
-	uint32_t waiting;
-	uint32_t retry;
-	uint32_t err = 0U;
-
-	/* set EXIT -> OP_DONE is cleared */
-	ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01);
-
-	/* kick */
-	foreach_vch(ch) {
-		if ((ch_have_this_cs[ddr_csn % 2U] & (1U << ch)) != 0U) {
-			ddr_setval(ch, reg_cs, ddr_csn);
-			ddr_setval(ch, reg_kick, 0x01U);
-		}
-	}
-	foreach_vch(ch) {
-		/*PREPARE ADDR REGISTER (for SWLVL_OP_DONE) */
-		ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
-	}
-	waiting = ch_have_this_cs[ddr_csn % 2U];
-	dsb_sev();
-	retry = RETRY_MAX;
-	do {
-		foreach_vch(ch) {
-			if ((waiting & (1U << ch)) == 0U) {
-				continue;
-			}
-			data_l = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
-			if ((data_l & 0x01U) != 0U) {
-				waiting &= ~(1U << ch);
-			}
-		}
-		retry--;
-	} while ((waiting != 0U) && (retry > 0U));
-	if (retry == 0U) {
-		err = 1U;
-	}
-
-	dsb_sev();
-	/* set EXIT -> OP_DONE is cleared */
-	ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01U);
-	dsb_sev();
-
-	return err;
-}
-
-/* WDQ TRAINING */
-#ifndef DDR_FAST_INIT
-static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
-{
-	uint32_t cs, slice;
-	uint32_t data_l;
-	int32_t i, k;
-
-	/* clr of training results buffer */
-	cs = ddr_csn % 2U;
-	data_l = board_cnf->dqdm_dly_w;
-	for (slice = 0U; slice < SLICE_CNT; slice++) {
-		k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
-		if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) {
-			continue;
-		}
-
-		for (i = 0; i <= 8; i++) {
-			if ((ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) != 0U) {
-				wdqdm_dly[ch][cs][slice][i] =
-				    wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
-			} else {
-				wdqdm_dly[ch][cs][slice][i] = data_l;
-			}
-			wdqdm_le[ch][cs][slice][i] = 0U;
-			wdqdm_te[ch][cs][slice][i] = 0U;
-		}
-		wdqdm_st[ch][cs][slice] = 0U;
-		wdqdm_win[ch][cs][slice] = 0U;
-	}
-}
-
-static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
-{
-	const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0U;
-	uint32_t cs, slice;
-	uint32_t data_l;
-	int32_t min_win;
-	int32_t i, k;
-	uint32_t err;
-	int32_t win;
-	int8_t _adj;
-	int16_t adj;
-	uint32_t dq;
-
-	/* analysis of training results */
-	err = 0U;
-	for (slice = 0U; slice < SLICE_CNT; slice += 1U) {
-		k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
-		if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) {
-			continue;
-		}
-
-		cs = ddr_csn % 2U;
-		ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
-		for (i = 0; i < 9; i++) {
-			dq = slice * 8U + i;
-			if (i == 8) {
-				_adj = board_cnf->ch[ch].dm_adj_w[slice];
-			} else {
-				_adj = board_cnf->ch[ch].dq_adj_w[dq];
-			}
-			adj = _f_scale_adj(_adj);
-
-			data_l =
-			    ddr_getval_s(ch, slice,
-					 _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj;
-			ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
-				     data_l);
-			wdqdm_dly[ch][cs][slice][i] = data_l;
-		}
-		ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00);
-		data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS);
-		wdqdm_st[ch][cs][slice] = data_l;
-		min_win = INT_LEAST32_MAX;
-		for (i = 0; i <= 8; i++) {
-			ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT,
-				     i);
-
-			data_l =
-			    ddr_getval_s(ch, slice,
-					 _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS);
-			wdqdm_te[ch][cs][slice][i] = data_l;
-			data_l =
-			    ddr_getval_s(ch, slice,
-					 _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS);
-			wdqdm_le[ch][cs][slice][i] = data_l;
-			win = (int32_t)wdqdm_te[ch][cs][slice][i] -
-			      wdqdm_le[ch][cs][slice][i];
-			if (min_win > win) {
-				min_win = win;
-			}
-			if (data_l >= _par_WDQLVL_RETRY_THRES) {
-				err = 2;
-			}
-		}
-		wdqdm_win[ch][cs][slice] = min_win;
-		ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
-			     ((ch_have_this_cs[1]) >> ch) & 0x01);
-	}
-	return err;
-}
-#endif/* DDR_FAST_INIT */
-
-static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore)
-{
-	uint32_t tgt_cs, src_cs;
-	uint32_t ch, slice;
-	uint32_t tmp_r;
-	uint32_t i;
-
-	/* copy of training results */
-	foreach_vch(ch) {
-		for (tgt_cs = 0U; tgt_cs < CS_CNT; tgt_cs++) {
-			for (slice = 0U; slice < SLICE_CNT; slice++) {
-				ddr_setval_s(ch, slice,
-					     _reg_PHY_PER_CS_TRAINING_INDEX,
-					     tgt_cs);
-				src_cs = ddr_csn % 2U;
-				if ((ch_have_this_cs[1] & (1U << ch)) == 0U) {
-					src_cs = 0U;
-				}
-				for (i = 0U; i <= 4U; i += 4U) {
-					if (restore != 0U) {
-						tmp_r = rdqdm_dly[ch][tgt_cs][slice][i];
-					} else {
-						tmp_r = rdqdm_dly[ch][src_cs][slice][i];
-					}
-
-					ddr_setval_s(ch, slice,
-						     _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i],
-						     tmp_r);
-				}
-			}
-		}
-	}
-}
-
-static uint32_t wdqdm_man1(void)
-{
-	uint32_t mr14_csab0_bak[DRAM_CH_CNT];
-	uint32_t ch, cs, ddr_csn;
-	uint32_t data_l;
-	uint32_t err = 0U;
-#ifndef DDR_FAST_INIT
-	uint32_t err_flg = 0U;
-#endif/* DDR_FAST_INIT */
-
-	/* CLEAR PREV RESULT */
-	for (cs = 0U; cs < CS_CNT; cs++) {
-		ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs);
-		ddr_setval_ach_as(_reg_PHY_WDQLVL_CLR_PREV_RESULTS, 0x01U);
-	}
-	ddrphy_regif_idle();
-
-	for (ddr_csn = 0U; ddr_csn < CSAB_CNT; ddr_csn++) {
-		if (((prr_product == PRR_PRODUCT_M3) &&
-		     (prr_cut == PRR_PRODUCT_10))) {
-			wdqdm_cp(ddr_csn, 0U);
-		}
-
-		foreach_vch(ch) {
-			data_l = ddr_getval(ch, reg_pi_mr14_data_fx_csx[1][ddr_csn]);
-			ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], data_l);
-		}
-
-		/* KICK WDQLVL */
-		err = swlvl1(ddr_csn, _reg_PI_WDQLVL_CS, _reg_PI_WDQLVL_REQ);
-		if (err != 0U) {
-			goto err_exit;
-		}
-
-		if (ddr_csn == 0U) {
-			foreach_vch(ch) {
-				mr14_csab0_bak[ch] = ddr_getval(ch,
-								reg_pi_mr14_data_fx_csx[1][0]);
-			}
-		} else {
-			foreach_vch(ch) {
-				ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0],
-					   mr14_csab0_bak[ch]);
-			}
-		}
-#ifndef DDR_FAST_INIT
-		foreach_vch(ch) {
-			if ((ch_have_this_cs[ddr_csn % 2U] & (1U << ch)) == 0U) {
-				wdqdm_clr1(ch, ddr_csn);
-				continue;
-			}
-			err = wdqdm_ana1(ch, ddr_csn);
-			if (err != 0U) {
-				err_flg |= (1U << (ddr_csn * 4U + ch));
-			}
-			ddrphy_regif_idle();
-		}
-#endif/* DDR_FAST_INIT */
-	}
-err_exit:
-#ifndef DDR_FAST_INIT
-	err |= err_flg;
-#endif/* DDR_FAST_INIT */
-
-	return err;
-}
-
-static uint32_t wdqdm_man(void)
-{
-	uint32_t datal, ch, ddr_csn, mr14_bkup[4][4];
-	const uint32_t retry_max = 0x10U;
-	uint32_t err, retry_cnt;
-
-	datal = RL + js2[js2_tdqsck] + (16U / 2U) + 1U - WL + 2U + 2U + 19U;
-	if ((mmio_read_32(DBSC_DBTR(11)) & 0xFF) > datal) {
-		datal = mmio_read_32(DBSC_DBTR(11)) & 0xFF;
-	}
-	ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, datal);
-
-	ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR,
-		       (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
-
-	ddr_setval_ach(_reg_PI_TRFC_F0, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
-	ddr_setval_ach(_reg_PI_TRFC_F1, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
-
-	retry_cnt = 0U;
-	err = 0U;
-	do {
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01);
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x01);
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0C);
-		dsb_sev();
-		err = wdqdm_man1();
-		foreach_vch(ch) {
-			for (ddr_csn = 0U; ddr_csn < CSAB_CNT; ddr_csn++) {
-				mr14_bkup[ch][ddr_csn] =
-				    ddr_getval(ch, reg_pi_mr14_data_fx_csx
-					       [1][ddr_csn]);
-				dsb_sev();
-			}
-		}
-
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x04);
-
-		pvtcode_update();
-		err = wdqdm_man1();
-		foreach_vch(ch) {
-			for (ddr_csn = 0U; ddr_csn < CSAB_CNT; ddr_csn++) {
-				mr14_bkup[ch][ddr_csn] =
-				    (mr14_bkup[ch][ddr_csn] +
-				     ddr_getval(ch, reg_pi_mr14_data_fx_csx
-						[1][ddr_csn])) / 2U;
-				ddr_setval(ch,
-					   reg_pi_mr14_data_fx_csx[1]
-					   [ddr_csn],
-					   mr14_bkup[ch][ddr_csn]);
-			}
-		}
-
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x0U);
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0U);
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_START_POINT, 0x0U);
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT, 0x0U);
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE, 0x0U);
-
-		pvtcode_update2();
-		err = wdqdm_man1();
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x0U);
-
-	} while ((err != 0U) && (++retry_cnt < retry_max));
-
-	if (prr_product == PRR_PRODUCT_M3 && prr_cut <= PRR_PRODUCT_10) {
-		wdqdm_cp(0U, 1U);
-	}
-
-	return (retry_cnt >= retry_max);
-}
-
-/* RDQ TRAINING */
-#ifndef DDR_FAST_INIT
-static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
-{
-	uint32_t cs, slice;
-	uint32_t data_l;
-	int32_t i, k;
-
-	/* clr of training results buffer */
-	cs = ddr_csn % 2U;
-	data_l = board_cnf->dqdm_dly_r;
-	for (slice = 0U; slice < SLICE_CNT; slice++) {
-		k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
-		if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) {
-			continue;
-		}
-
-		for (i = 0; i <= 8; i++) {
-			if ((ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) != 0U) {
-				rdqdm_dly[ch][cs][slice][i] =
-				    rdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
-				rdqdm_dly[ch][cs][slice + SLICE_CNT][i] =
-				    rdqdm_dly[ch][CS_CNT - 1 - cs][slice + SLICE_CNT][i];
-			} else {
-				rdqdm_dly[ch][cs][slice][i] = data_l;
-				rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l;
-			}
-			rdqdm_le[ch][cs][slice][i] = 0U;
-			rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0U;
-			rdqdm_te[ch][cs][slice][i] = 0U;
-			rdqdm_te[ch][cs][slice + SLICE_CNT][i] = 0U;
-			rdqdm_nw[ch][cs][slice][i] = 0U;
-			rdqdm_nw[ch][cs][slice + SLICE_CNT][i] = 0U;
-		}
-		rdqdm_st[ch][cs][slice] = 0U;
-		rdqdm_win[ch][cs][slice] = 0U;
-	}
-}
-
-static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
-{
-	uint32_t rdq_status_obs_select;
-	uint32_t cs, slice;
-	uint32_t data_l;
-	uint32_t err;
-	uint32_t dq;
-	int32_t min_win;
-	int8_t _adj;
-	int16_t adj;
-	int32_t min_win;
-	int32_t win;
-	int32_t i, k;
-
-	/* analysis of training results */
-	err = 0U;
-	for (slice = 0U; slice < SLICE_CNT; slice++) {
-		k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
-		if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) {
-			continue;
-		}
-
-		cs = ddr_csn % 2U;
-		ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
-		ddrphy_regif_idle();
-
-		ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX);
-		ddrphy_regif_idle();
-
-		for (i = 0; i <= 8; i++) {
-			dq = slice * 8 + i;
-			if (i == 8) {
-				_adj = board_cnf->ch[ch].dm_adj_r[slice];
-			} else {
-				_adj = board_cnf->ch[ch].dq_adj_r[dq];
-			}
-
-			adj = _f_scale_adj(_adj);
-
-			data_l = ddr_getval_s(ch, slice,
-					      _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
-			ddr_setval_s(ch, slice,
-				     _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i],
-				     data_l);
-			rdqdm_dly[ch][cs][slice][i] = data_l;
-
-			data_l = ddr_getval_s(ch, slice,
-					      _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
-			ddr_setval_s(ch, slice,
-				     _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i],
-				     data_l);
-			rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l;
-		}
-		min_win = INT_LEAST32_MAX;
-		for (i = 0; i <= 8; i++) {
-			data_l =
-			    ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS);
-			rdqdm_st[ch][cs][slice] = data_l;
-			rdqdm_st[ch][cs][slice + SLICE_CNT] = data_l;
-			/* k : rise/fall */
-			for (k = 0; k < 2; k++) {
-				if (i == 8) {
-					rdq_status_obs_select = 16 + 8 * k;
-				} else {
-					rdq_status_obs_select = i + k * 8;
-				}
-				ddr_setval_s(ch, slice,
-					     _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT,
-					     rdq_status_obs_select);
-
-				data_l =
-				    ddr_getval_s(ch, slice,
-						 _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS);
-				rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] = data_l;
-
-				data_l =
-				    ddr_getval_s(ch, slice,
-						 _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS);
-				rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] = data_l;
-
-				data_l =
-				    ddr_getval_s(ch, slice,
-						 _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS);
-				rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] = data_l;
-
-				win =
-				    (int32_t)rdqdm_te[ch][cs][slice +
-							      SLICE_CNT *
-							      k][i] -
-				    rdqdm_le[ch][cs][slice + SLICE_CNT * k][i];
-				if (i != 8) {
-					if (min_win > win) {
-						min_win = win;
-					}
-				}
-			}
-		}
-		rdqdm_win[ch][cs][slice] = min_win;
-		if (min_win <= 0) {
-			err = 2;
-		}
-	}
-	return err;
-}
-#else /* DDR_FAST_INIT */
-static void rdqdm_man1_set(uint32_t ddr_csn, uint32_t ch, uint32_t slice)
-{
-	uint32_t i, adj, data_l;
-
-	for (i = 0U; i <= 8U; i++) {
-		if (i == 8U) {
-			adj = _f_scale_adj(board_cnf->ch[ch].dm_adj_r[slice]);
-		} else {
-			adj = _f_scale_adj(board_cnf->ch[ch].dq_adj_r[slice * 8U + i]);
-		}
-		ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn);
-		data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
-		ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], data_l);
-		rdqdm_dly[ch][ddr_csn][slice][i] = data_l;
-		rdqdm_dly[ch][ddr_csn | 1U][slice][i] = data_l;
-
-		data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
-		ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], data_l);
-		rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = data_l;
-		rdqdm_dly[ch][ddr_csn | 1U][slice + SLICE_CNT][i] = data_l;
-	}
-}
-#endif /* DDR_FAST_INIT */
-
-static uint32_t rdqdm_man1(void)
-{
-	uint32_t ch;
-	uint32_t ddr_csn;
-	uint32_t val;
-#ifdef DDR_FAST_INIT
-	uint32_t slice;
-#endif/* DDR_FAST_INIT */
-	uint32_t err;
-
-	/* manual execution of training */
-	err = 0U;
-
-	for (ddr_csn = 0U; ddr_csn < CSAB_CNT; ddr_csn++) {
-		/* KICK RDQLVL */
-		err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ);
-		if (err != 0U) {
-			goto err_exit;
-		}
-#ifndef DDR_FAST_INIT
-		foreach_vch(ch) {
-			if ((ch_have_this_cs[ddr_csn % 2] & (1U << ch)) == 0U) {
-				rdqdm_clr1(ch, ddr_csn);
-				ddrphy_regif_idle();
-				continue;
-			}
-			err = rdqdm_ana1(ch, ddr_csn);
-			ddrphy_regif_idle();
-			if (err != 0U)  {
-				goto err_exit;
-			}
-		}
-#else/* DDR_FAST_INIT */
-		foreach_vch(ch) {
-			if ((ch_have_this_cs[ddr_csn] & (1U << ch)) != 0U) {
-				for (slice = 0U; slice < SLICE_CNT; slice++) {
-					val = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS);
-					if (val != 0x0D00FFFFU) {
-						err = (1U << ch) | (0x10U << slice);
-						goto err_exit;
-					}
-				}
-			}
-			if ((prr_product == PRR_PRODUCT_M3) &&
-			    (prr_cut <= PRR_PRODUCT_10)) {
-				for (slice = 0U; slice < SLICE_CNT; slice++) {
-					rdqdm_man1_set(ddr_csn, ch, slice);
-				}
-			}
-		}
-		ddrphy_regif_idle();
-
-#endif/* DDR_FAST_INIT */
-	}
-
-err_exit:
-	return err;
-}
-
-static uint32_t rdqdm_man(void)
-{
-	uint32_t err, retry_cnt;
-	const uint32_t retry_max = 0x01U;
-
-	ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE,
-			  0x00000004U | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-						     _reg_PHY_DQ_TSEL_ENABLE));
-	ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE,
-			  0x00000004U | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-						     _reg_PHY_DQS_TSEL_ENABLE));
-	ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT,
-			  0xFF0FFFFFU & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-						     _reg_PHY_DQ_TSEL_SELECT));
-	ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT,
-			  0xFF0FFFFFU & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-						     _reg_PHY_DQS_TSEL_SELECT));
-
-	retry_cnt = 0U;
-	do {
-		err = rdqdm_man1();
-		ddrphy_regif_idle();
-	} while ((err != 0U) && (++retry_cnt < retry_max));
-	ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE,
-			  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-					_reg_PHY_DQ_TSEL_ENABLE));
-	ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE,
-			  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-					_reg_PHY_DQS_TSEL_ENABLE));
-	ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT,
-			  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-					_reg_PHY_DQ_TSEL_SELECT));
-	ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT,
-			  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-					_reg_PHY_DQS_TSEL_SELECT));
-
-	return (retry_cnt >= retry_max);
-}
-
-/* rx offset calibration */
-static int32_t _find_change(uint64_t val, uint32_t dir)
-{
-	int32_t i;
-	uint32_t startval;
-	uint32_t curval;
-	const int32_t VAL_END = 0x3fU;
-
-	if (dir == 0U) {
-		startval = (val & 0x01U);
-		for (i = 1; i <= VAL_END; i++) {
-			curval = (val >> i) & 0x01U;
-			if (curval != startval) {
-				return i;
-			}
-		}
-		return VAL_END;
-	}
-
-	startval = (val >> dir) & 0x01U;
-	for (i = (int32_t)dir - 1; i >= 0; i--) {
-		curval = (val >> i) & 0x01U;
-		if (curval != startval) {
-			return i;
-		}
-	}
-
-	return 0;
-}
-
-static uint32_t _rx_offset_cal_updn(uint32_t code)
-{
-	const uint32_t CODE_MAX = 0x40U;
-	uint32_t tmp;
-
-	if (code == 0U) {
-		tmp = (1U << 6) | (CODE_MAX - 1U);
-	} else {
-		tmp = (code << 6) | (CODE_MAX - code);
-	}
-
-	return tmp;
-}
-
-static uint32_t rx_offset_cal(void)
-{
-	uint32_t index;
-	uint32_t code;
-	const uint32_t CODE_MAX = 0x40U;
-	const uint32_t CODE_STEP = 2U;
-	uint32_t ch, slice;
-	uint32_t tmp;
-	uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
-	uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM];
-	uint64_t tmpval;
-	int32_t lsb, msb;
-
-	ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01);
-	foreach_vch(ch) {
-		for (slice = 0U; slice < SLICE_CNT; slice++) {
-			for (index = 0U; index < _reg_PHY_RX_CAL_X_NUM; index++) {
-				val[ch][slice][index] = 0U;
-			}
-		}
-	}
-
-	for (code = 0U; code < CODE_MAX / CODE_STEP; code++) {
-		tmp = _rx_offset_cal_updn(code * CODE_STEP);
-		for (index = 0U; index < _reg_PHY_RX_CAL_X_NUM; index++) {
-			ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp);
-		}
-		dsb_sev();
-		ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as);
-
-		foreach_vch(ch) {
-			for (slice = 0U; slice < SLICE_CNT; slice++) {
-				tmp = tmp_ach_as[ch][slice];
-				for (index = 0U; index < _reg_PHY_RX_CAL_X_NUM;
-				     index++) {
-					if ((tmp & (1U << index)) != 0U) {
-						val[ch][slice][index] |=
-						    (1ULL << code);
-					} else {
-						val[ch][slice][index] &=
-						    ~(1ULL << code);
-					}
-				}
-			}
-		}
-	}
-	foreach_vch(ch) {
-		for (slice = 0U; slice < SLICE_CNT; slice++) {
-			for (index = 0U; index < _reg_PHY_RX_CAL_X_NUM;
-			     index++) {
-				tmpval = val[ch][slice][index];
-				lsb = _find_change(tmpval, 0U);
-				msb = _find_change(tmpval,
-						   (CODE_MAX / CODE_STEP) - 1U);
-				tmp = (lsb + msb) >> 1U;
-
-				tmp = _rx_offset_cal_updn(tmp * CODE_STEP);
-				ddr_setval_s(ch, slice,
-					     _reg_PHY_RX_CAL_X[index], tmp);
-			}
-		}
-	}
-	ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00);
-
-	return 0U;
-}
-
-static uint32_t rx_offset_cal_hw(void)
-{
-	uint32_t ch, slice;
-	uint32_t retry;
-	uint32_t complete;
-	uint32_t tmp;
-	uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
-
-	ddr_setval_ach_as(_reg_PHY_RX_CAL_X[9], 0x00);
-	ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00);
-	ddr_setval_ach_as(_reg_PHY_RX_CAL_SAMPLE_WAIT, 0x0f);
-
-	retry = 0U;
-	while (retry < 4096U) {
-		if ((retry & 0xffU) == 0U) {
-			ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01);
-		}
-		foreach_vch(ch)  {
-			for (slice = 0U; slice < SLICE_CNT; slice++) {
-				tmp_ach_as[ch][slice] =
-					ddr_getval_s(ch, slice,
-						     _reg_PHY_RX_CAL_X[9]);
-			}
-		}
-
-		complete = 1U;
-		foreach_vch(ch) {
-			for (slice = 0U; slice < SLICE_CNT; slice++) {
-				tmp = tmp_ach_as[ch][slice];
-				tmp = (tmp & 0x3fU) + ((tmp >> 6) & 0x3fU);
-				if (tmp != 0x40U) {
-					complete = 0U;
-				}
-			}
-		}
-		if (complete != 0U) {
-			break;
-		}
-
-		retry++;
-	}
-
-	return (complete == 0U);
-}
-
-/* adjust wpath latency */
-static void adjust_wpath_latency(void)
-{
-	uint32_t ch, cs, slice;
-	uint32_t dly;
-	uint32_t wpath_add;
-	const uint32_t _par_EARLY_THRESHOLD_VAL = 0x180U;
-
-	foreach_vch(ch) {
-		for (slice = 0U; slice < SLICE_CNT; slice += 1U) {
-			for (cs = 0U; cs < CS_CNT; cs++) {
-				ddr_setval_s(ch, slice,
-					     _reg_PHY_PER_CS_TRAINING_INDEX,
-					     cs);
-				ddr_getval_s(ch, slice,
-					     _reg_PHY_PER_CS_TRAINING_INDEX);
-				dly =
-				    ddr_getval_s(ch, slice,
-						 _reg_PHY_CLK_WRDQS_SLAVE_DELAY);
-				if (dly <= _par_EARLY_THRESHOLD_VAL) {
-					continue;
-				}
-
-				wpath_add =
-				    ddr_getval_s(ch, slice,
-						 _reg_PHY_WRITE_PATH_LAT_ADD);
-				ddr_setval_s(ch, slice,
-					     _reg_PHY_WRITE_PATH_LAT_ADD,
-					     wpath_add - 1U);
-			}
-		}
-	}
-}
-
-/* DDR Initialize entry */
-int32_t rzg_dram_init(void)
-{
-	uint32_t ch, cs;
-	uint32_t data_l;
-	uint32_t bus_mbps, bus_mbpsdiv;
-	uint32_t tmp_tccd;
-	uint32_t failcount;
-	uint32_t cnf_boardtype;
-	int32_t ret = INITDRAM_NG;
-
-	/* Thermal sensor setting */
-	data_l = mmio_read_32(CPG_MSTPSR5);
-	if ((data_l & BIT(22)) != 0U) {	/*  case THS/TSC Standby */
-		data_l &= ~BIT(22);
-		cpg_write_32(CPG_SMSTPCR5, data_l);
-		while ((mmio_read_32(CPG_MSTPSR5) & BIT(22)) != 0U) {
-			/*  wait bit=0 */
-		}
-	}
-
-	/* THCTR Bit6: PONM=0 , Bit0: THSST=0   */
-	data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE;
-	mmio_write_32(THS1_THCTR, data_l);
-
-	/* Judge product and cut */
-#ifdef RCAR_DDR_FIXED_LSI_TYPE
-#if (RCAR_LSI == RCAR_AUTO)
-	prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
-	prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
-#else /* RCAR_LSI */
-#ifndef RCAR_LSI_CUT
-	prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
-#endif /* RCAR_LSI_CUT */
-#endif /* RCAR_LSI */
-#else /* RCAR_DDR_FIXED_LSI_TYPE */
-	prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
-	prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
-#endif /* RCAR_DDR_FIXED_LSI_TYPE */
-
-	if (prr_product == PRR_PRODUCT_M3) {
-		p_ddr_regdef_tbl =
-			(const uint32_t *)&DDR_REGDEF_TBL[1][0];
-	} else {
-		FATAL_MSG("BL2: DDR:Unknown Product\n");
-		goto done;
-	}
-
-	if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) {
-		/* non : G2M Ver.1.x not support */
-	} else {
-		mmio_write_32(DBSC_DBSYSCNT0, 0x00001234U);
-	}
-
-	/* Judge board type */
-	cnf_boardtype = boardcnf_get_brd_type(prr_product);
-	if (cnf_boardtype >= (uint32_t)BOARDNUM) {
-		FATAL_MSG("BL2: DDR:Unknown Board\n");
-		goto done;
-	}
-	board_cnf = (const struct _boardcnf *)&boardcnfs[cnf_boardtype];
-
-/* RCAR_DRAM_SPLIT_2CH           (2U) */
-#if RCAR_DRAM_SPLIT == 2
-	ddr_phyvalid = board_cnf->phyvalid;
-#else /* RCAR_DRAM_SPLIT_2CH */
-	ddr_phyvalid = board_cnf->phyvalid;
-#endif /* RCAR_DRAM_SPLIT_2CH */
-
-	max_density = 0U;
-
-	for (cs = 0U; cs < CS_CNT; cs++) {
-		ch_have_this_cs[cs] = 0U;
-	}
-
-	foreach_ech(ch) {
-		for (cs = 0U; cs < CS_CNT; cs++) {
-			ddr_density[ch][cs] = 0xffU;
-		}
-	}
-
-	foreach_vch(ch) {
-		for (cs = 0U; cs < CS_CNT; cs++) {
-			data_l = board_cnf->ch[ch].ddr_density[cs];
-			ddr_density[ch][cs] = data_l;
-
-			if (data_l == 0xffU) {
-				continue;
-			}
-			if (data_l > max_density) {
-				max_density = data_l;
-			}
-			ch_have_this_cs[cs] |= (1U << ch);
-		}
-	}
-
-	/* Judge board clock frequency (in MHz) */
-	boardcnf_get_brd_clk(cnf_boardtype, &brd_clk, &brd_clkdiv);
-	if ((brd_clk / brd_clkdiv) > 25U) {
-		brd_clkdiva = 1U;
-	} else {
-		brd_clkdiva = 0U;
-	}
-
-	/* Judge ddr operating frequency clock(in Mbps) */
-	boardcnf_get_ddr_mbps(cnf_boardtype, &ddr_mbps, &ddr_mbpsdiv);
-
-	ddr0800_mul = CLK_DIV(800U, 2U, brd_clk, brd_clkdiv * (brd_clkdiva + 1U));
-
-	ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2U, brd_clk,
-			  brd_clkdiv * (brd_clkdiva + 1U));
-
-	/* Adjust tccd */
-	data_l = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13;
-	bus_mbps = 0U;
-	bus_mbpsdiv = 0U;
-	switch (data_l) {
-	case 0:
-		bus_mbps = brd_clk * 0x60U * 2U;
-		bus_mbpsdiv = brd_clkdiv * 1U;
-		break;
-	case 1:
-		bus_mbps = brd_clk * 0x50U * 2U;
-		bus_mbpsdiv = brd_clkdiv * 1U;
-		break;
-	case 2:
-		bus_mbps = brd_clk * 0x40U * 2U;
-		bus_mbpsdiv = brd_clkdiv * 1U;
-		break;
-	case 3:
-		bus_mbps = brd_clk * 0x60U * 2U;
-		bus_mbpsdiv = brd_clkdiv * 2U;
-		break;
-	default:
-		bus_mbps = brd_clk * 0x60U * 2U;
-		bus_mbpsdiv = brd_clkdiv * 2U;
-		WARN("BL2: DDR using default values for adjusting tccd");
-		break;
-	}
-	tmp_tccd = CLK_DIV(ddr_mbps * 8U, ddr_mbpsdiv, bus_mbps, bus_mbpsdiv);
-	if (8U * ddr_mbps * bus_mbpsdiv != tmp_tccd * bus_mbps * ddr_mbpsdiv) {
-		tmp_tccd = tmp_tccd + 1U;
-	}
-
-	if (tmp_tccd < 8U) {
-		ddr_tccd = 8U;
-	} else {
-		ddr_tccd = tmp_tccd;
-	}
-
-	NOTICE("BL2: DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION);
-
-	MSG_LF("Start\n");
-
-	/* PLL Setting */
-	pll3_control(1U);
-
-	/* initialize DDR */
-	data_l = init_ddr();
-	if (data_l == ddr_phyvalid) {
-		failcount = 0U;
-	} else {
-		failcount = 1U;
-	}
-
-	foreach_vch(ch) {
-	    mmio_write_32(DBSC_DBPDLK(ch), 0x00000000U);
-	}
-	if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) {
-		/* non : G2M Ver.1.x not support */
-	} else {
-		mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
-	}
-
-	if (failcount == 0U) {
-		ret = INITDRAM_OK;
-	}
-
-done:
-	return ret;
-}
-
-static void pvtcode_update(void)
-{
-	uint32_t ch;
-	uint32_t data_l;
-	uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init;
-	int32_t pvtp_tmp, pvtn_tmp;
-
-	foreach_vch(ch) {
-		pvtn_init = (tcal.tcomp_cal[ch] & 0xFC0U) >> 6;
-		pvtp_init = (tcal.tcomp_cal[ch] & 0x03FU) >> 0;
-
-		if (8912U * pvtp_init > 44230U) {
-			pvtp_tmp = (5000U + 8912U * pvtp_init - 44230U) / 10000U;
-		} else {
-			pvtp_tmp =
-			    -((-(5000 + 8912 * pvtp_init - 44230)) / 10000);
-		}
-		pvtn_tmp = (5000U + 5776U * (uint32_t)pvtn_init + 30280U) / 10000U;
-
-		pvtn[ch] = (uint32_t)pvtn_tmp + pvtn_init;
-		pvtp[ch] = (uint32_t)pvtp_tmp + pvtp_init;
-
-		if (pvtn[ch] > 63U) {
-			pvtn[ch] = 63U;
-			pvtp[ch] =
-			    (pvtp_tmp) * (63 - 6 * pvtn_tmp -
-					  pvtn_init) / (pvtn_tmp) +
-			    6 * pvtp_tmp + pvtp_init;
-		}
-
-		data_l = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000U;
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
-				 data_l | 0x00020000U);
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
-				 data_l);
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
-				 data_l);
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
-				 data_l);
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
-				 data_l);
-	}
-}
-
-static void pvtcode_update2(void)
-{
-	uint32_t ch;
-
-	foreach_vch(ch) {
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
-				 tcal.init_cal[ch] | 0x00020000U);
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
-				 tcal.init_cal[ch]);
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
-				 tcal.init_cal[ch]);
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
-				 tcal.init_cal[ch]);
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
-				 tcal.init_cal[ch]);
-	}
-}
-
-static void ddr_padcal_tcompensate_getinit(uint32_t override)
-{
-	uint32_t ch;
-	uint32_t data_l;
-	uint32_t pvtp, pvtn;
-
-	tcal.init_temp = 0;
-	for (ch = 0U; ch < 4U; ch++) {
-		tcal.init_cal[ch] = 0U;
-		tcal.tcomp_cal[ch] = 0U;
-	}
-
-	foreach_vch(ch) {
-		tcal.init_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]);
-		tcal.tcomp_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]);
-	}
-
-	if (override == 0U) {
-		data_l = mmio_read_32(THS1_TEMP);
-		if (data_l < 2800U) {
-			tcal.init_temp =
-			    (143 * (int32_t)data_l - 359000) / 1000;
-		} else {
-			tcal.init_temp =
-			    (121 * (int32_t)data_l - 296300) / 1000;
-		}
-
-		foreach_vch(ch) {
-			pvtp = (tcal.init_cal[ch] >> 0) & 0x000003FU;
-			pvtn = (tcal.init_cal[ch] >> 6) & 0x000003FU;
-			if ((int32_t)pvtp >
-			    ((tcal.init_temp * 29 - 3625) / 1000)) {
-				pvtp = (int32_t)pvtp +
-				    ((3625 - tcal.init_temp * 29) / 1000);
-			} else {
-				pvtp = 0U;
-			}
-
-			if ((int32_t)pvtn >
-			    ((tcal.init_temp * 54 - 6750) / 1000)) {
-				pvtn = (int32_t)pvtn +
-				    ((6750 - tcal.init_temp * 54) / 1000);
-			} else {
-				pvtn = 0U;
-			}
-
-			tcal.init_cal[ch] = 0x00015000U | (pvtn << 6) | pvtp;
-		}
-		tcal.init_temp = 125;
-	}
-}
-
-#ifndef DDR_QOS_INIT_SETTING
-/* For QoS init */
-uint8_t rzg_get_boardcnf_phyvalid(void)
-{
-	return ddr_phyvalid;
-}
-#endif /* DDR_QOS_INIT_SETTING */
diff --git a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_config.c b/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_config.c
deleted file mode 100644
index 345ef24..0000000
--- a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_config.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#define BOARDNUM 2
-#define BOARD_JUDGE_AUTO
-
-#ifdef BOARD_JUDGE_AUTO
-static uint32_t _board_judge(uint32_t prr_product);
-
-static uint32_t boardcnf_get_brd_type(uint32_t prr_product)
-{
-	return _board_judge(prr_product);
-}
-#else /* BOARD_JUDGE_AUTO */
-static uint32_t boardcnf_get_brd_type(void)
-{
-	return 1U;
-}
-#endif /* BOARD_JUDGE_AUTO */
-
-#define DDR_FAST_INIT
-
-struct _boardcnf_ch {
-	uint8_t ddr_density[CS_CNT];
-	uint64_t ca_swap;
-	uint16_t dqs_swap;
-	uint32_t dq_swap[SLICE_CNT];
-	uint8_t dm_swap[SLICE_CNT];
-	uint16_t wdqlvl_patt[16];
-	int8_t cacs_adj[16];
-	int8_t dm_adj_w[SLICE_CNT];
-	int8_t dq_adj_w[SLICE_CNT * 8U];
-	int8_t dm_adj_r[SLICE_CNT];
-	int8_t dq_adj_r[SLICE_CNT * 8U];
-};
-
-struct _boardcnf {
-	uint8_t phyvalid;
-	uint8_t dbi_en;
-	uint16_t cacs_dly;
-	int16_t cacs_dly_adj;
-	uint16_t dqdm_dly_w;
-	uint16_t dqdm_dly_r;
-	struct _boardcnf_ch ch[DRAM_CH_CNT];
-};
-
-#define WDQLVL_PAT {\
-	0x00AA,\
-	0x0055,\
-	0x00AA,\
-	0x0155,\
-	0x01CC,\
-	0x0133,\
-	0x00CC,\
-	0x0033,\
-	0x00F0,\
-	0x010F,\
-	0x01F0,\
-	0x010F,\
-	0x00F0,\
-	0x00F0,\
-	0x000F,\
-	0x010F}
-
-static const struct _boardcnf boardcnfs[BOARDNUM] = {
-	{
-/* boardcnf[0] HopeRun HiHope RZ/G2M 16Gbit/1rank/2ch board with G2M SoC */
-	 .phyvalid = 0x03,
-	 .dbi_en = 0x01,
-	 .cacs_dly = 0x02c0,
-	 .cacs_dly_adj = 0,
-	 .dqdm_dly_w = 0x0300,
-	 .dqdm_dly_r = 0x00a0,
-	 .ch = {
-		{
-		 {0x04, 0xff},
-		 0x00345201U,
-		 0x3201,
-		 {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
-		 {0x08, 0x08, 0x08, 0x08},
-		 WDQLVL_PAT,
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0},
-		 {0, 0, 0, 0},
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0},
-		 {0, 0, 0, 0},
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0}
-		},
-
-		{
-		 {0x04, 0xff},
-		 0x00302154U,
-		 0x2310,
-		 {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
-		 {0x08, 0x08, 0x08, 0x08},
-		 WDQLVL_PAT,
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0},
-		 {0, 0, 0, 0},
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0},
-		 {0, 0, 0, 0},
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0}
-		}
-		}
-	},
-/* boardcnf[1] HopeRun HiHope RZ/G2M 8Gbit/2rank/2ch board with G2M SoC */
-	{
-	 0x03,
-	 0x01,
-	 0x02c0,
-	 0,
-	 0x0300,
-	 0x00a0,
-	{
-		{
-		 {0x02, 0x02},
-		 0x00345201U,
-		 0x3201,
-		 {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
-		 {0x08, 0x08, 0x08, 0x08},
-		 WDQLVL_PAT,
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0},
-		 {0, 0, 0, 0},
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0},
-		 {0, 0, 0, 0},
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0}
-		},
-		{
-		 {0x02, 0x02},
-		 0x00302154U,
-		 0x2310,
-		 {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
-		 {0x08, 0x08, 0x08, 0x08},
-		 WDQLVL_PAT,
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0},
-		 {0, 0, 0, 0},
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0},
-		{0, 0, 0, 0},
-		{0, 0, 0, 0, 0, 0, 0, 0,
-		 0, 0, 0, 0, 0, 0, 0, 0,
-		 0, 0, 0, 0, 0, 0, 0, 0,
-		 0, 0, 0, 0, 0, 0, 0, 0}
-		}
-	}
-	}
-};
-
-void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div)
-{
-	uint32_t md;
-
-	md = (mmio_read_32(RST_MODEMR) >> 13) & 0x3U;
-	switch (md) {
-	case 0x0U:
-		*clk = 50U;
-		*div = 3U;
-		break;
-	case 0x1U:
-		*clk = 60U;
-		*div = 3U;
-		break;
-	case 0x2U:
-		*clk = 75U;
-		*div = 3U;
-		break;
-	case 0x3U:
-		*clk = 100U;
-		*div = 3U;
-		break;
-	default:
-		break;
-	}
-	(void)brd;
-}
-
-void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div)
-{
-	uint32_t md;
-
-	md = (mmio_read_32(RST_MODEMR) >> 17U) & 0x5U;
-	md = (md | (md >> 1U)) & 0x3U;
-	switch (md) {
-	case 0x0U:
-		*mbps = 3200U;
-		*div = 1U;
-		break;
-	case 0x1U:
-		*mbps = 2800U;
-		*div = 1U;
-		break;
-	case 0x2U:
-		*mbps = 2400U;
-		*div = 1U;
-		break;
-	case 0x3U:
-		*mbps = 1600U;
-		*div = 1U;
-		break;
-	default:
-		break;
-	}
-	(void)brd;
-}
-
-#define _def_REFPERIOD  1890
-
-#define M3_SAMPLE_TT_A84        0xB866CC10U, 0x3B250421U
-#define M3_SAMPLE_TT_A85        0xB866CC10U, 0x3AA50421U
-#define M3_SAMPLE_TT_A86        0xB866CC10U, 0x3AA48421U
-#define M3_SAMPLE_FF_B45        0xB866CC10U, 0x3AB00C21U
-#define M3_SAMPLE_FF_B49        0xB866CC10U, 0x39B10C21U
-#define M3_SAMPLE_FF_B56        0xB866CC10U, 0x3AAF8C21U
-#define M3_SAMPLE_SS_E24        0xB866CC10U, 0x3BA39421U
-#define M3_SAMPLE_SS_E28        0xB866CC10U, 0x3C231421U
-#define M3_SAMPLE_SS_E32        0xB866CC10U, 0x3C241421U
-
-static const uint32_t termcode_by_sample[20][3] = {
-	{ M3_SAMPLE_TT_A84, 0x000158D5U },
-	{ M3_SAMPLE_TT_A85, 0x00015955U },
-	{ M3_SAMPLE_TT_A86, 0x00015955U },
-	{ M3_SAMPLE_FF_B45, 0x00015690U },
-	{ M3_SAMPLE_FF_B49, 0x00015753U },
-	{ M3_SAMPLE_FF_B56, 0x00015793U },
-	{ M3_SAMPLE_SS_E24, 0x00015996U },
-	{ M3_SAMPLE_SS_E28, 0x000159D7U },
-	{ M3_SAMPLE_SS_E32, 0x00015997U },
-	{ 0xFFFFFFFFU, 0xFFFFFFFFU, 0x0001554FU}
-};
-
-#ifdef BOARD_JUDGE_AUTO
-/* Board detect function */
-#define GPIO_INDT5	0xE605500CU
-#define LPDDR4_2RANK	(0x01U << 25U)
-
-static uint32_t _board_judge(uint32_t prr_product)
-{
-	uint32_t boardInfo;
-	uint32_t boardid = 1U;
-
-	if (prr_product == PRR_PRODUCT_M3) {
-		if ((mmio_read_32(PRR) & PRR_CUT_MASK) != RCAR_M3_CUT_VER11) {
-			boardInfo = mmio_read_32(GPIO_INDT5);
-			if ((boardInfo & LPDDR4_2RANK) == 0U) {
-				boardid = 0U;
-			}
-		}
-	}
-
-	return boardid;
-}
-#endif /* BOARD_JUDGE_AUTO */
diff --git a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_regdef.h
deleted file mode 100644
index 9f1c936..0000000
--- a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_regdef.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef RZG_BOOT_INIT_DRAM_REGDEF_H
-#define RZG_BOOT_INIT_DRAM_REGDEF_H
-
-#define RCAR_DDR_VERSION	"rev.0.40"
-#define DRAM_CH_CNT		0x04U
-#define SLICE_CNT		0x04U
-#define CS_CNT			0x02U
-
-/* order : CS0A, CS0B, CS1A, CS1B */
-#define CSAB_CNT		(CS_CNT * 2U)
-
-/* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */
-#define CHAB_CNT		(DRAM_CH_CNT * 2)
-
-/* pll setting */
-#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
-#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
-
-/* for ddr density setting */
-#define DBMEMCONF_REG(d3, row, bank, col, dw)	\
-	(((d3) << 30U) | ((row) << 24U) | ((bank) << 16U) | ((col) << 8U) | (dw))
-
-#define DBMEMCONF_REGD(density)		\
-	(DBMEMCONF_REG((density) % 2U, ((density) + 1U) / \
-	2U + (29U - 3U - 10U - 2U), 3U, 10U, 2U))
-
-#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
-
-/* refresh mode */
-#define DBSC_REFINTS		(0x0U)
-
-/* system registers */
-#define CPG_FRQCRB		(CPG_BASE + 0x0004U)
-
-#define CPG_PLLECR		(CPG_BASE + 0x00D0U)
-#define CPG_MSTPSR5		(CPG_BASE + 0x003CU)
-#define CPG_SRCR4		(CPG_BASE + 0x00BCU)
-#define CPG_PLL3CR		(CPG_BASE + 0x00DCU)
-#define CPG_ZB3CKCR		(CPG_BASE + 0x0380U)
-#define CPG_FRQCRD		(CPG_BASE + 0x00E4U)
-#define CPG_SMSTPCR5		(CPG_BASE + 0x0144U)
-#define CPG_CPGWPR		(CPG_BASE + 0x0900U)
-#define CPG_SRSTCLR4		(CPG_BASE + 0x0950U)
-
-#define CPG_FRQCRB_KICK_BIT	BIT(31)
-#define CPG_PLLECR_PLL3E_BIT	BIT(3)
-#define CPG_PLLECR_PLL3ST_BIT	BIT(11)
-#define CPG_ZB3CKCR_ZB3ST_BIT	BIT(11)
-
-#define RST_BASE		(0xE6160000U)
-#define RST_MODEMR		(RST_BASE + 0x0060U)
-
-#define LIFEC_CHIPID(x)		(0xE6110040U + 0x04U * (x))
-
-/* DBSC registers */
-#include "ddr_regs.h"
-
-#define DBSC_DBMONCONF4		0xE6793010U
-
-#define DBSC_PLL_LOCK(ch)	(0xE6794054U + 0x100U * (ch))
-#define DBSC_PLL_LOCK_0		0xE6794054U
-#define DBSC_PLL_LOCK_1		0xE6794154U
-#define DBSC_PLL_LOCK_2		0xE6794254U
-#define DBSC_PLL_LOCK_3		0xE6794354U
-
-/* STAT registers */
-#define MSTAT_SL_INIT		0xE67E8000U
-#define MSTAT_REF_ARS		0xE67E8004U
-#define MSTATQ_STATQC		0xE67E8008U
-#define MSTATQ_WTENABLE		0xE67E8030U
-#define MSTATQ_WTREFRESH	0xE67E8034U
-#define MSTATQ_WTSETTING0	0xE67E8038U
-#define MSTATQ_WTSETTING1	0xE67E803CU
-
-#define QOS_BASE1		(0xE67F0000U)
-#define QOSCTRL_RAS		(QOS_BASE1 + 0x0000U)
-#define QOSCTRL_FIXTH		(QOS_BASE1 + 0x0004U)
-#define QOSCTRL_RAEN		(QOS_BASE1 + 0x0018U)
-#define QOSCTRL_REGGD		(QOS_BASE1 + 0x0020U)
-#define QOSCTRL_DANN		(QOS_BASE1 + 0x0030U)
-#define QOSCTRL_DANT		(QOS_BASE1 + 0x0038U)
-#define QOSCTRL_EC		(QOS_BASE1 + 0x003CU)
-#define QOSCTRL_EMS		(QOS_BASE1 + 0x0040U)
-#define QOSCTRL_INSFC		(QOS_BASE1 + 0x0050U)
-#define QOSCTRL_BERR		(QOS_BASE1 + 0x0054U)
-#define QOSCTRL_RACNT0		(QOS_BASE1 + 0x0080U)
-#define QOSCTRL_STATGEN0	(QOS_BASE1 + 0x0088U)
-
-/* other module */
-#define THS1_THCTR		0xE6198020U
-#define THS1_TEMP		0xE6198028U
-
-#endif /* RZG_BOOT_INIT_DRAM_REGDEF_H */
diff --git a/drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk b/drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk
deleted file mode 100644
index c137f26..0000000
--- a/drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-BL2_SOURCES += drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c
diff --git a/drivers/renesas/rzg/ddr/ddr_b/ddr_regdef.h b/drivers/renesas/rzg/ddr/ddr_b/ddr_regdef.h
deleted file mode 100644
index 1da455f..0000000
--- a/drivers/renesas/rzg/ddr/ddr_b/ddr_regdef.h
+++ /dev/null
@@ -1,5891 +0,0 @@
-/*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef RZG_DDR_REGDEF_H
-#define RZG_DDR_REGDEF_H
-
-#define _reg_PHY_DQ_DM_SWIZZLE0                            0x00000000U
-#define _reg_PHY_DQ_DM_SWIZZLE1                            0x00000001U
-#define _reg_PHY_CLK_WR_BYPASS_SLAVE_DELAY                 0x00000002U
-#define _reg_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY             0x00000003U
-#define _reg_PHY_BYPASS_TWO_CYC_PREAMBLE                   0x00000004U
-#define _reg_PHY_CLK_BYPASS_OVERRIDE                       0x00000005U
-#define _reg_PHY_SW_WRDQ0_SHIFT                            0x00000006U
-#define _reg_PHY_SW_WRDQ1_SHIFT                            0x00000007U
-#define _reg_PHY_SW_WRDQ2_SHIFT                            0x00000008U
-#define _reg_PHY_SW_WRDQ3_SHIFT                            0x00000009U
-#define _reg_PHY_SW_WRDQ4_SHIFT                            0x0000000aU
-#define _reg_PHY_SW_WRDQ5_SHIFT                            0x0000000bU
-#define _reg_PHY_SW_WRDQ6_SHIFT                            0x0000000cU
-#define _reg_PHY_SW_WRDQ7_SHIFT                            0x0000000dU
-#define _reg_PHY_SW_WRDM_SHIFT                             0x0000000eU
-#define _reg_PHY_SW_WRDQS_SHIFT                            0x0000000fU
-#define _reg_PHY_DQ_TSEL_ENABLE                            0x00000010U
-#define _reg_PHY_DQ_TSEL_SELECT                            0x00000011U
-#define _reg_PHY_DQS_TSEL_ENABLE                           0x00000012U
-#define _reg_PHY_DQS_TSEL_SELECT                           0x00000013U
-#define _reg_PHY_TWO_CYC_PREAMBLE                          0x00000014U
-#define _reg_PHY_DBI_MODE                                  0x00000015U
-#define _reg_PHY_PER_RANK_CS_MAP                           0x00000016U
-#define _reg_PHY_PER_CS_TRAINING_MULTICAST_EN              0x00000017U
-#define _reg_PHY_PER_CS_TRAINING_INDEX                     0x00000018U
-#define _reg_PHY_LP4_BOOT_RDDATA_EN_IE_DLY                 0x00000019U
-#define _reg_PHY_LP4_BOOT_RDDATA_EN_DLY                    0x0000001aU
-#define _reg_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY               0x0000001bU
-#define _reg_PHY_LP4_BOOT_RPTR_UPDATE                      0x0000001cU
-#define _reg_PHY_LP4_BOOT_RDDQS_GATE_SLAVE_DELAY           0x0000001dU
-#define _reg_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST             0x0000001eU
-#define _reg_PHY_LP4_BOOT_WRPATH_GATE_DISABLE              0x0000001fU
-#define _reg_PHY_LP4_BOOT_RDDATA_EN_OE_DLY                 0x00000020U
-#define _reg_PHY_LPBK_CONTROL                              0x00000021U
-#define _reg_PHY_LPBK_DFX_TIMEOUT_EN                       0x00000022U
-#define _reg_PHY_AUTO_TIMING_MARGIN_CONTROL                0x00000023U
-#define _reg_PHY_AUTO_TIMING_MARGIN_OBS                    0x00000024U
-#define _reg_PHY_SLICE_PWR_RDC_DISABLE                     0x00000025U
-#define _reg_PHY_PRBS_PATTERN_START                        0x00000026U
-#define _reg_PHY_PRBS_PATTERN_MASK                         0x00000027U
-#define _reg_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY               0x00000028U
-#define _reg_PHY_GATE_ERROR_DELAY_SELECT                   0x00000029U
-#define _reg_SC_PHY_SNAP_OBS_REGS                          0x0000002aU
-#define _reg_PHY_LPDDR                                     0x0000002bU
-#define _reg_PHY_LPDDR_TYPE                                0x0000002cU
-#define _reg_PHY_GATE_SMPL1_SLAVE_DELAY                    0x0000002dU
-#define _reg_PHY_GATE_SMPL2_SLAVE_DELAY                    0x0000002eU
-#define _reg_ON_FLY_GATE_ADJUST_EN                         0x0000002fU
-#define _reg_PHY_GATE_TRACKING_OBS                         0x00000030U
-#define _reg_PHY_DFI40_POLARITY                            0x00000031U
-#define _reg_PHY_LP4_PST_AMBLE                             0x00000032U
-#define _reg_PHY_RDLVL_PATT8                               0x00000033U
-#define _reg_PHY_RDLVL_PATT9                               0x00000034U
-#define _reg_PHY_RDLVL_PATT10                              0x00000035U
-#define _reg_PHY_RDLVL_PATT11                              0x00000036U
-#define _reg_PHY_LP4_RDLVL_PATT8                           0x00000037U
-#define _reg_PHY_LP4_RDLVL_PATT9                           0x00000038U
-#define _reg_PHY_LP4_RDLVL_PATT10                          0x00000039U
-#define _reg_PHY_LP4_RDLVL_PATT11                          0x0000003aU
-#define _reg_PHY_SLAVE_LOOP_CNT_UPDATE                     0x0000003bU
-#define _reg_PHY_SW_FIFO_PTR_RST_DISABLE                   0x0000003cU
-#define _reg_PHY_MASTER_DLY_LOCK_OBS_SELECT                0x0000003dU
-#define _reg_PHY_RDDQ_ENC_OBS_SELECT                       0x0000003eU
-#define _reg_PHY_RDDQS_DQ_ENC_OBS_SELECT                   0x0000003fU
-#define _reg_PHY_WR_ENC_OBS_SELECT                         0x00000040U
-#define _reg_PHY_WR_SHIFT_OBS_SELECT                       0x00000041U
-#define _reg_PHY_FIFO_PTR_OBS_SELECT                       0x00000042U
-#define _reg_PHY_LVL_DEBUG_MODE                            0x00000043U
-#define _reg_SC_PHY_LVL_DEBUG_CONT                         0x00000044U
-#define _reg_PHY_WRLVL_CAPTURE_CNT                         0x00000045U
-#define _reg_PHY_WRLVL_UPDT_WAIT_CNT                       0x00000046U
-#define _reg_PHY_WRLVL_DQ_MASK                             0x00000047U
-#define _reg_PHY_GTLVL_CAPTURE_CNT                         0x00000048U
-#define _reg_PHY_GTLVL_UPDT_WAIT_CNT                       0x00000049U
-#define _reg_PHY_RDLVL_CAPTURE_CNT                         0x0000004aU
-#define _reg_PHY_RDLVL_UPDT_WAIT_CNT                       0x0000004bU
-#define _reg_PHY_RDLVL_OP_MODE                             0x0000004cU
-#define _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT                 0x0000004dU
-#define _reg_PHY_RDLVL_DATA_MASK                           0x0000004eU
-#define _reg_PHY_RDLVL_DATA_SWIZZLE                        0x0000004fU
-#define _reg_PHY_WDQLVL_BURST_CNT                          0x00000050U
-#define _reg_PHY_WDQLVL_PATT                               0x00000051U
-#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET           0x00000052U
-#define _reg_PHY_WDQLVL_UPDT_WAIT_CNT                      0x00000053U
-#define _reg_PHY_WDQLVL_DQDM_OBS_SELECT                    0x00000054U
-#define _reg_PHY_WDQLVL_QTR_DLY_STEP                       0x00000055U
-#define _reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS                0x00000056U
-#define _reg_PHY_WDQLVL_CLR_PREV_RESULTS                   0x00000057U
-#define _reg_PHY_WDQLVL_DATADM_MASK                        0x00000058U
-#define _reg_PHY_USER_PATT0                                0x00000059U
-#define _reg_PHY_USER_PATT1                                0x0000005aU
-#define _reg_PHY_USER_PATT2                                0x0000005bU
-#define _reg_PHY_USER_PATT3                                0x0000005cU
-#define _reg_PHY_USER_PATT4                                0x0000005dU
-#define _reg_PHY_DQ_SWIZZLING                              0x0000005eU
-#define _reg_PHY_CALVL_VREF_DRIVING_SLICE                  0x0000005fU
-#define _reg_SC_PHY_MANUAL_CLEAR                           0x00000060U
-#define _reg_PHY_FIFO_PTR_OBS                              0x00000061U
-#define _reg_PHY_LPBK_RESULT_OBS                           0x00000062U
-#define _reg_PHY_LPBK_ERROR_COUNT_OBS                      0x00000063U
-#define _reg_PHY_MASTER_DLY_LOCK_OBS                       0x00000064U
-#define _reg_PHY_RDDQ_SLV_DLY_ENC_OBS                      0x00000065U
-#define _reg_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS                0x00000066U
-#define _reg_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS       0x00000067U
-#define _reg_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS       0x00000068U
-#define _reg_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS                0x00000069U
-#define _reg_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS                0x0000006aU
-#define _reg_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS                 0x0000006bU
-#define _reg_PHY_WR_ADDER_SLV_DLY_ENC_OBS                  0x0000006cU
-#define _reg_PHY_WR_SHIFT_OBS                              0x0000006dU
-#define _reg_PHY_WRLVL_HARD0_DELAY_OBS                     0x0000006eU
-#define _reg_PHY_WRLVL_HARD1_DELAY_OBS                     0x0000006fU
-#define _reg_PHY_WRLVL_STATUS_OBS                          0x00000070U
-#define _reg_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS                0x00000071U
-#define _reg_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS                0x00000072U
-#define _reg_PHY_WRLVL_ERROR_OBS                           0x00000073U
-#define _reg_PHY_GTLVL_HARD0_DELAY_OBS                     0x00000074U
-#define _reg_PHY_GTLVL_HARD1_DELAY_OBS                     0x00000075U
-#define _reg_PHY_GTLVL_STATUS_OBS                          0x00000076U
-#define _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS                 0x00000077U
-#define _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS                 0x00000078U
-#define _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS            0x00000079U
-#define _reg_PHY_RDLVL_STATUS_OBS                          0x0000007aU
-#define _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS                    0x0000007bU
-#define _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS                    0x0000007cU
-#define _reg_PHY_WDQLVL_STATUS_OBS                         0x0000007dU
-#define _reg_PHY_DDL_MODE                                  0x0000007eU
-#define _reg_PHY_DDL_TEST_OBS                              0x0000007fU
-#define _reg_PHY_DDL_TEST_MSTR_DLY_OBS                     0x00000080U
-#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD                   0x00000081U
-#define _reg_PHY_LP4_WDQS_OE_EXTEND                        0x00000082U
-#define _reg_SC_PHY_RX_CAL_START                           0x00000083U
-#define _reg_PHY_RX_CAL_OVERRIDE                           0x00000084U
-#define _reg_PHY_RX_CAL_SAMPLE_WAIT                        0x00000085U
-#define _reg_PHY_RX_CAL_DQ0                                0x00000086U
-#define _reg_PHY_RX_CAL_DQ1                                0x00000087U
-#define _reg_PHY_RX_CAL_DQ2                                0x00000088U
-#define _reg_PHY_RX_CAL_DQ3                                0x00000089U
-#define _reg_PHY_RX_CAL_DQ4                                0x0000008aU
-#define _reg_PHY_RX_CAL_DQ5                                0x0000008bU
-#define _reg_PHY_RX_CAL_DQ6                                0x0000008cU
-#define _reg_PHY_RX_CAL_DQ7                                0x0000008dU
-#define _reg_PHY_RX_CAL_DM                                 0x0000008eU
-#define _reg_PHY_RX_CAL_DQS                                0x0000008fU
-#define _reg_PHY_RX_CAL_FDBK                               0x00000090U
-#define _reg_PHY_RX_CAL_OBS                                0x00000091U
-#define _reg_PHY_RX_CAL_LOCK_OBS                           0x00000092U
-#define _reg_PHY_RX_CAL_DISABLE                            0x00000093U
-#define _reg_PHY_CLK_WRDQ0_SLAVE_DELAY                     0x00000094U
-#define _reg_PHY_CLK_WRDQ1_SLAVE_DELAY                     0x00000095U
-#define _reg_PHY_CLK_WRDQ2_SLAVE_DELAY                     0x00000096U
-#define _reg_PHY_CLK_WRDQ3_SLAVE_DELAY                     0x00000097U
-#define _reg_PHY_CLK_WRDQ4_SLAVE_DELAY                     0x00000098U
-#define _reg_PHY_CLK_WRDQ5_SLAVE_DELAY                     0x00000099U
-#define _reg_PHY_CLK_WRDQ6_SLAVE_DELAY                     0x0000009aU
-#define _reg_PHY_CLK_WRDQ7_SLAVE_DELAY                     0x0000009bU
-#define _reg_PHY_CLK_WRDM_SLAVE_DELAY                      0x0000009cU
-#define _reg_PHY_CLK_WRDQS_SLAVE_DELAY                     0x0000009dU
-#define _reg_PHY_WRLVL_THRESHOLD_ADJUST                    0x0000009eU
-#define _reg_PHY_RDDQ0_SLAVE_DELAY                         0x0000009fU
-#define _reg_PHY_RDDQ1_SLAVE_DELAY                         0x000000a0U
-#define _reg_PHY_RDDQ2_SLAVE_DELAY                         0x000000a1U
-#define _reg_PHY_RDDQ3_SLAVE_DELAY                         0x000000a2U
-#define _reg_PHY_RDDQ4_SLAVE_DELAY                         0x000000a3U
-#define _reg_PHY_RDDQ5_SLAVE_DELAY                         0x000000a4U
-#define _reg_PHY_RDDQ6_SLAVE_DELAY                         0x000000a5U
-#define _reg_PHY_RDDQ7_SLAVE_DELAY                         0x000000a6U
-#define _reg_PHY_RDDM_SLAVE_DELAY                          0x000000a7U
-#define _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY                0x000000a8U
-#define _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY                0x000000a9U
-#define _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY                0x000000aaU
-#define _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY                0x000000abU
-#define _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY                0x000000acU
-#define _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY                0x000000adU
-#define _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY                0x000000aeU
-#define _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY                0x000000afU
-#define _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY                0x000000b0U
-#define _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY                0x000000b1U
-#define _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY                0x000000b2U
-#define _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY                0x000000b3U
-#define _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY                0x000000b4U
-#define _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY                0x000000b5U
-#define _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY                0x000000b6U
-#define _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY                0x000000b7U
-#define _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY                 0x000000b8U
-#define _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY                 0x000000b9U
-#define _reg_PHY_RDDQS_GATE_SLAVE_DELAY                    0x000000baU
-#define _reg_PHY_RDDQS_LATENCY_ADJUST                      0x000000bbU
-#define _reg_PHY_WRITE_PATH_LAT_ADD                        0x000000bcU
-#define _reg_PHY_WRLVL_DELAY_EARLY_THRESHOLD               0x000000bdU
-#define _reg_PHY_WRLVL_DELAY_PERIOD_THRESHOLD              0x000000beU
-#define _reg_PHY_WRLVL_EARLY_FORCE_ZERO                    0x000000bfU
-#define _reg_PHY_GTLVL_RDDQS_SLV_DLY_START                 0x000000c0U
-#define _reg_PHY_GTLVL_LAT_ADJ_START                       0x000000c1U
-#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_START                 0x000000c2U
-#define _reg_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START              0x000000c3U
-#define _reg_PHY_FDBK_PWR_CTRL                             0x000000c4U
-#define _reg_PHY_DQ_OE_TIMING                              0x000000c5U
-#define _reg_PHY_DQ_TSEL_RD_TIMING                         0x000000c6U
-#define _reg_PHY_DQ_TSEL_WR_TIMING                         0x000000c7U
-#define _reg_PHY_DQS_OE_TIMING                             0x000000c8U
-#define _reg_PHY_DQS_TSEL_RD_TIMING                        0x000000c9U
-#define _reg_PHY_DQS_OE_RD_TIMING                          0x000000caU
-#define _reg_PHY_DQS_TSEL_WR_TIMING                        0x000000cbU
-#define _reg_PHY_PER_CS_TRAINING_EN                        0x000000ccU
-#define _reg_PHY_DQ_IE_TIMING                              0x000000cdU
-#define _reg_PHY_DQS_IE_TIMING                             0x000000ceU
-#define _reg_PHY_RDDATA_EN_IE_DLY                          0x000000cfU
-#define _reg_PHY_IE_MODE                                   0x000000d0U
-#define _reg_PHY_RDDATA_EN_DLY                             0x000000d1U
-#define _reg_PHY_RDDATA_EN_TSEL_DLY                        0x000000d2U
-#define _reg_PHY_RDDATA_EN_OE_DLY                          0x000000d3U
-#define _reg_PHY_SW_MASTER_MODE                            0x000000d4U
-#define _reg_PHY_MASTER_DELAY_START                        0x000000d5U
-#define _reg_PHY_MASTER_DELAY_STEP                         0x000000d6U
-#define _reg_PHY_MASTER_DELAY_WAIT                         0x000000d7U
-#define _reg_PHY_MASTER_DELAY_HALF_MEASURE                 0x000000d8U
-#define _reg_PHY_RPTR_UPDATE                               0x000000d9U
-#define _reg_PHY_WRLVL_DLY_STEP                            0x000000daU
-#define _reg_PHY_WRLVL_RESP_WAIT_CNT                       0x000000dbU
-#define _reg_PHY_GTLVL_DLY_STEP                            0x000000dcU
-#define _reg_PHY_GTLVL_RESP_WAIT_CNT                       0x000000ddU
-#define _reg_PHY_GTLVL_BACK_STEP                           0x000000deU
-#define _reg_PHY_GTLVL_FINAL_STEP                          0x000000dfU
-#define _reg_PHY_WDQLVL_DLY_STEP                           0x000000e0U
-#define _reg_PHY_TOGGLE_PRE_SUPPORT                        0x000000e1U
-#define _reg_PHY_RDLVL_DLY_STEP                            0x000000e2U
-#define _reg_PHY_WRPATH_GATE_DISABLE                       0x000000e3U
-#define _reg_PHY_WRPATH_GATE_TIMING                        0x000000e4U
-#define _reg_PHY_ADR0_SW_WRADDR_SHIFT                      0x000000e5U
-#define _reg_PHY_ADR1_SW_WRADDR_SHIFT                      0x000000e6U
-#define _reg_PHY_ADR2_SW_WRADDR_SHIFT                      0x000000e7U
-#define _reg_PHY_ADR3_SW_WRADDR_SHIFT                      0x000000e8U
-#define _reg_PHY_ADR4_SW_WRADDR_SHIFT                      0x000000e9U
-#define _reg_PHY_ADR5_SW_WRADDR_SHIFT                      0x000000eaU
-#define _reg_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY             0x000000ebU
-#define _reg_PHY_ADR_CLK_BYPASS_OVERRIDE                   0x000000ecU
-#define _reg_SC_PHY_ADR_MANUAL_CLEAR                       0x000000edU
-#define _reg_PHY_ADR_LPBK_RESULT_OBS                       0x000000eeU
-#define _reg_PHY_ADR_LPBK_ERROR_COUNT_OBS                  0x000000efU
-#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT            0x000000f0U
-#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS                   0x000000f1U
-#define _reg_PHY_ADR_BASE_SLV_DLY_ENC_OBS                  0x000000f2U
-#define _reg_PHY_ADR_ADDER_SLV_DLY_ENC_OBS                 0x000000f3U
-#define _reg_PHY_ADR_SLAVE_LOOP_CNT_UPDATE                 0x000000f4U
-#define _reg_PHY_ADR_SLV_DLY_ENC_OBS_SELECT                0x000000f5U
-#define _reg_SC_PHY_ADR_SNAP_OBS_REGS                      0x000000f6U
-#define _reg_PHY_ADR_TSEL_ENABLE                           0x000000f7U
-#define _reg_PHY_ADR_LPBK_CONTROL                          0x000000f8U
-#define _reg_PHY_ADR_PRBS_PATTERN_START                    0x000000f9U
-#define _reg_PHY_ADR_PRBS_PATTERN_MASK                     0x000000faU
-#define _reg_PHY_ADR_PWR_RDC_DISABLE                       0x000000fbU
-#define _reg_PHY_ADR_TYPE                                  0x000000fcU
-#define _reg_PHY_ADR_WRADDR_SHIFT_OBS                      0x000000fdU
-#define _reg_PHY_ADR_IE_MODE                               0x000000feU
-#define _reg_PHY_ADR_DDL_MODE                              0x000000ffU
-#define _reg_PHY_ADR_DDL_TEST_OBS                          0x00000100U
-#define _reg_PHY_ADR_DDL_TEST_MSTR_DLY_OBS                 0x00000101U
-#define _reg_PHY_ADR_CALVL_START                           0x00000102U
-#define _reg_PHY_ADR_CALVL_COARSE_DLY                      0x00000103U
-#define _reg_PHY_ADR_CALVL_QTR                             0x00000104U
-#define _reg_PHY_ADR_CALVL_SWIZZLE0                        0x00000105U
-#define _reg_PHY_ADR_CALVL_SWIZZLE1                        0x00000106U
-#define _reg_PHY_ADR_CALVL_SWIZZLE0_0                      0x00000107U
-#define _reg_PHY_ADR_CALVL_SWIZZLE1_0                      0x00000108U
-#define _reg_PHY_ADR_CALVL_SWIZZLE0_1                      0x00000109U
-#define _reg_PHY_ADR_CALVL_SWIZZLE1_1                      0x0000010aU
-#define _reg_PHY_ADR_CALVL_DEVICE_MAP                      0x0000010bU
-#define _reg_PHY_ADR_CALVL_RANK_CTRL                       0x0000010cU
-#define _reg_PHY_ADR_CALVL_NUM_PATTERNS                    0x0000010dU
-#define _reg_PHY_ADR_CALVL_CAPTURE_CNT                     0x0000010eU
-#define _reg_PHY_ADR_CALVL_RESP_WAIT_CNT                   0x0000010fU
-#define _reg_PHY_ADR_CALVL_DEBUG_MODE                      0x00000110U
-#define _reg_SC_PHY_ADR_CALVL_DEBUG_CONT                   0x00000111U
-#define _reg_SC_PHY_ADR_CALVL_ERROR_CLR                    0x00000112U
-#define _reg_PHY_ADR_CALVL_OBS_SELECT                      0x00000113U
-#define _reg_PHY_ADR_CALVL_OBS0                            0x00000114U
-#define _reg_PHY_ADR_CALVL_OBS1                            0x00000115U
-#define _reg_PHY_ADR_CALVL_RESULT                          0x00000116U
-#define _reg_PHY_ADR_CALVL_FG_0                            0x00000117U
-#define _reg_PHY_ADR_CALVL_BG_0                            0x00000118U
-#define _reg_PHY_ADR_CALVL_FG_1                            0x00000119U
-#define _reg_PHY_ADR_CALVL_BG_1                            0x0000011aU
-#define _reg_PHY_ADR_CALVL_FG_2                            0x0000011bU
-#define _reg_PHY_ADR_CALVL_BG_2                            0x0000011cU
-#define _reg_PHY_ADR_CALVL_FG_3                            0x0000011dU
-#define _reg_PHY_ADR_CALVL_BG_3                            0x0000011eU
-#define _reg_PHY_ADR_ADDR_SEL                              0x0000011fU
-#define _reg_PHY_ADR_LP4_BOOT_SLV_DELAY                    0x00000120U
-#define _reg_PHY_ADR_BIT_MASK                              0x00000121U
-#define _reg_PHY_ADR_SEG_MASK                              0x00000122U
-#define _reg_PHY_ADR_CALVL_TRAIN_MASK                      0x00000123U
-#define _reg_PHY_ADR_CSLVL_TRAIN_MASK                      0x00000124U
-#define _reg_PHY_ADR_SW_TXIO_CTRL                          0x00000125U
-#define _reg_PHY_ADR_TSEL_SELECT                           0x00000126U
-#define _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY                   0x00000127U
-#define _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY                   0x00000128U
-#define _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY                   0x00000129U
-#define _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY                   0x0000012aU
-#define _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY                   0x0000012bU
-#define _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY                   0x0000012cU
-#define _reg_PHY_ADR_SW_MASTER_MODE                        0x0000012dU
-#define _reg_PHY_ADR_MASTER_DELAY_START                    0x0000012eU
-#define _reg_PHY_ADR_MASTER_DELAY_STEP                     0x0000012fU
-#define _reg_PHY_ADR_MASTER_DELAY_WAIT                     0x00000130U
-#define _reg_PHY_ADR_MASTER_DELAY_HALF_MEASURE             0x00000131U
-#define _reg_PHY_ADR_CALVL_DLY_STEP                        0x00000132U
-#define _reg_PHY_FREQ_SEL                                  0x00000133U
-#define _reg_PHY_FREQ_SEL_FROM_REGIF                       0x00000134U
-#define _reg_PHY_FREQ_SEL_MULTICAST_EN                     0x00000135U
-#define _reg_PHY_FREQ_SEL_INDEX                            0x00000136U
-#define _reg_PHY_SW_GRP_SHIFT_0                            0x00000137U
-#define _reg_PHY_SW_GRP_SHIFT_1                            0x00000138U
-#define _reg_PHY_SW_GRP_SHIFT_2                            0x00000139U
-#define _reg_PHY_SW_GRP_SHIFT_3                            0x0000013aU
-#define _reg_PHY_GRP_BYPASS_SLAVE_DELAY                    0x0000013bU
-#define _reg_PHY_SW_GRP_BYPASS_SHIFT                       0x0000013cU
-#define _reg_PHY_GRP_BYPASS_OVERRIDE                       0x0000013dU
-#define _reg_SC_PHY_MANUAL_UPDATE                          0x0000013eU
-#define _reg_SC_PHY_MANUAL_UPDATE_PHYUPD_ENABLE            0x0000013fU
-#define _reg_PHY_LP4_BOOT_DISABLE                          0x00000140U
-#define _reg_PHY_CSLVL_ENABLE                              0x00000141U
-#define _reg_PHY_CSLVL_CS_MAP                              0x00000142U
-#define _reg_PHY_CSLVL_START                               0x00000143U
-#define _reg_PHY_CSLVL_QTR                                 0x00000144U
-#define _reg_PHY_CSLVL_COARSE_CHK                          0x00000145U
-#define _reg_PHY_CSLVL_CAPTURE_CNT                         0x00000146U
-#define _reg_PHY_CSLVL_COARSE_DLY                          0x00000147U
-#define _reg_PHY_CSLVL_COARSE_CAPTURE_CNT                  0x00000148U
-#define _reg_PHY_CSLVL_DEBUG_MODE                          0x00000149U
-#define _reg_SC_PHY_CSLVL_DEBUG_CONT                       0x0000014aU
-#define _reg_SC_PHY_CSLVL_ERROR_CLR                        0x0000014bU
-#define _reg_PHY_CSLVL_OBS0                                0x0000014cU
-#define _reg_PHY_CSLVL_OBS1                                0x0000014dU
-#define _reg_PHY_CALVL_CS_MAP                              0x0000014eU
-#define _reg_PHY_GRP_SLV_DLY_ENC_OBS_SELECT                0x0000014fU
-#define _reg_PHY_GRP_SHIFT_OBS_SELECT                      0x00000150U
-#define _reg_PHY_GRP_SLV_DLY_ENC_OBS                       0x00000151U
-#define _reg_PHY_GRP_SHIFT_OBS                             0x00000152U
-#define _reg_PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE              0x00000153U
-#define _reg_PHY_ADRCTL_SNAP_OBS_REGS                      0x00000154U
-#define _reg_PHY_DFI_PHYUPD_TYPE                           0x00000155U
-#define _reg_PHY_ADRCTL_LPDDR                              0x00000156U
-#define _reg_PHY_LP4_ACTIVE                                0x00000157U
-#define _reg_PHY_LPDDR3_CS                                 0x00000158U
-#define _reg_PHY_CALVL_RESULT_MASK                         0x00000159U
-#define _reg_SC_PHY_UPDATE_CLK_CAL_VALUES                  0x0000015aU
-#define _reg_PHY_SW_TXIO_CTRL_0                            0x0000015bU
-#define _reg_PHY_SW_TXIO_CTRL_1                            0x0000015cU
-#define _reg_PHY_SW_TXIO_CTRL_2                            0x0000015dU
-#define _reg_PHY_SW_TXIO_CTRL_3                            0x0000015eU
-#define _reg_PHY_MEMCLK_SW_TXIO_CTRL                       0x0000015fU
-#define _reg_PHY_CA_SW_TXPWR_CTRL                          0x00000160U
-#define _reg_PHY_MEMCLK_SW_TXPWR_CTRL                      0x00000161U
-#define _reg_PHY_USER_DEF_REG_AC_0                         0x00000162U
-#define _reg_PHY_USER_DEF_REG_AC_1                         0x00000163U
-#define _reg_PHY_USER_DEF_REG_AC_2                         0x00000164U
-#define _reg_PHY_USER_DEF_REG_AC_3                         0x00000165U
-#define _reg_PHY_UPDATE_CLK_CAL_VALUES                     0x00000166U
-#define _reg_PHY_CONTINUOUS_CLK_CAL_UPDATE                 0x00000167U
-#define _reg_PHY_PLL_CTRL                                  0x00000168U
-#define _reg_PHY_PLL_CTRL_TOP                              0x00000169U
-#define _reg_PHY_PLL_CTRL_CA                               0x0000016aU
-#define _reg_PHY_PLL_BYPASS                                0x0000016bU
-#define _reg_PHY_LOW_FREQ_SEL                              0x0000016cU
-#define _reg_PHY_PAD_VREF_CTRL_DQ_0                        0x0000016dU
-#define _reg_PHY_PAD_VREF_CTRL_DQ_1                        0x0000016eU
-#define _reg_PHY_PAD_VREF_CTRL_DQ_2                        0x0000016fU
-#define _reg_PHY_PAD_VREF_CTRL_DQ_3                        0x00000170U
-#define _reg_PHY_PAD_VREF_CTRL_AC                          0x00000171U
-#define _reg_PHY_CSLVL_DLY_STEP                            0x00000172U
-#define _reg_PHY_SET_DFI_INPUT_0                           0x00000173U
-#define _reg_PHY_SET_DFI_INPUT_1                           0x00000174U
-#define _reg_PHY_SET_DFI_INPUT_2                           0x00000175U
-#define _reg_PHY_SET_DFI_INPUT_3                           0x00000176U
-#define _reg_PHY_GRP_SLAVE_DELAY_0                         0x00000177U
-#define _reg_PHY_GRP_SLAVE_DELAY_1                         0x00000178U
-#define _reg_PHY_GRP_SLAVE_DELAY_2                         0x00000179U
-#define _reg_PHY_GRP_SLAVE_DELAY_3                         0x0000017aU
-#define _reg_PHY_CS_ACS_ALLOCATION_0                       0x0000017bU
-#define _reg_PHY_CS_ACS_ALLOCATION_1                       0x0000017cU
-#define _reg_PHY_CS_ACS_ALLOCATION_2                       0x0000017dU
-#define _reg_PHY_CS_ACS_ALLOCATION_3                       0x0000017eU
-#define _reg_PHY_LP4_BOOT_PLL_CTRL                         0x0000017fU
-#define _reg_PHY_LP4_BOOT_PLL_CTRL_CA                      0x00000180U
-#define _reg_PHY_LP4_BOOT_TOP_PLL_CTRL                     0x00000181U
-#define _reg_PHY_PLL_CTRL_OVERRIDE                         0x00000182U
-#define _reg_PHY_PLL_WAIT                                  0x00000183U
-#define _reg_PHY_PLL_WAIT_TOP                              0x00000184U
-#define _reg_PHY_PLL_OBS_0                                 0x00000185U
-#define _reg_PHY_PLL_OBS_1                                 0x00000186U
-#define _reg_PHY_PLL_OBS_2                                 0x00000187U
-#define _reg_PHY_PLL_OBS_3                                 0x00000188U
-#define _reg_PHY_PLL_OBS_4                                 0x00000189U
-#define _reg_PHY_PLL_TESTOUT_SEL                           0x0000018aU
-#define _reg_PHY_TCKSRE_WAIT                               0x0000018bU
-#define _reg_PHY_LP4_BOOT_LOW_FREQ_SEL                     0x0000018cU
-#define _reg_PHY_LP_WAKEUP                                 0x0000018dU
-#define _reg_PHY_LS_IDLE_EN                                0x0000018eU
-#define _reg_PHY_LP_CTRLUPD_CNTR_CFG                       0x0000018fU
-#define _reg_PHY_TDFI_PHY_WRDELAY                          0x00000190U
-#define _reg_PHY_PAD_FDBK_DRIVE                            0x00000191U
-#define _reg_PHY_PAD_DATA_DRIVE                            0x00000192U
-#define _reg_PHY_PAD_DQS_DRIVE                             0x00000193U
-#define _reg_PHY_PAD_ADDR_DRIVE                            0x00000194U
-#define _reg_PHY_PAD_CLK_DRIVE                             0x00000195U
-#define _reg_PHY_PAD_FDBK_TERM                             0x00000196U
-#define _reg_PHY_PAD_DATA_TERM                             0x00000197U
-#define _reg_PHY_PAD_DQS_TERM                              0x00000198U
-#define _reg_PHY_PAD_ADDR_TERM                             0x00000199U
-#define _reg_PHY_PAD_CLK_TERM                              0x0000019aU
-#define _reg_PHY_PAD_CKE_DRIVE                             0x0000019bU
-#define _reg_PHY_PAD_CKE_TERM                              0x0000019cU
-#define _reg_PHY_PAD_RST_DRIVE                             0x0000019dU
-#define _reg_PHY_PAD_RST_TERM                              0x0000019eU
-#define _reg_PHY_PAD_CS_DRIVE                              0x0000019fU
-#define _reg_PHY_PAD_CS_TERM                               0x000001a0U
-#define _reg_PHY_PAD_ODT_DRIVE                             0x000001a1U
-#define _reg_PHY_PAD_ODT_TERM                              0x000001a2U
-#define _reg_PHY_ADRCTL_RX_CAL                             0x000001a3U
-#define _reg_PHY_ADRCTL_LP3_RX_CAL                         0x000001a4U
-#define _reg_PHY_TST_CLK_PAD_CTRL                          0x000001a5U
-#define _reg_PHY_TST_CLK_PAD_CTRL2                         0x000001a6U
-#define _reg_PHY_CAL_MODE_0                                0x000001a7U
-#define _reg_PHY_CAL_CLEAR_0                               0x000001a8U
-#define _reg_PHY_CAL_START_0                               0x000001a9U
-#define _reg_PHY_CAL_INTERVAL_COUNT_0                      0x000001aaU
-#define _reg_PHY_CAL_SAMPLE_WAIT_0                         0x000001abU
-#define _reg_PHY_LP4_BOOT_CAL_CLK_SELECT_0                 0x000001acU
-#define _reg_PHY_CAL_CLK_SELECT_0                          0x000001adU
-#define _reg_PHY_CAL_RESULT_OBS_0                          0x000001aeU
-#define _reg_PHY_CAL_RESULT2_OBS_0                         0x000001afU
-#define _reg_PHY_CAL_CPTR_CNT_0                            0x000001b0U
-#define _reg_PHY_CAL_SETTLING_PRD_0                        0x000001b1U
-#define _reg_PHY_CAL_PU_FINE_ADJ_0                         0x000001b2U
-#define _reg_PHY_CAL_PD_FINE_ADJ_0                         0x000001b3U
-#define _reg_PHY_CAL_RCV_FINE_ADJ_0                        0x000001b4U
-#define _reg_PHY_CAL_DBG_CFG_0                             0x000001b5U
-#define _reg_SC_PHY_PAD_DBG_CONT_0                         0x000001b6U
-#define _reg_PHY_CAL_RESULT3_OBS_0                         0x000001b7U
-#define _reg_PHY_ADRCTL_PVT_MAP_0                          0x000001b8U
-#define _reg_PHY_CAL_SLOPE_ADJ_0                           0x000001b9U
-#define _reg_PHY_CAL_SLOPE_ADJ_PASS2_0                     0x000001baU
-#define _reg_PHY_CAL_TWO_PASS_CFG_0                        0x000001bbU
-#define _reg_PHY_CAL_SW_CAL_CFG_0                          0x000001bcU
-#define _reg_PHY_CAL_RANGE_MIN_0                           0x000001bdU
-#define _reg_PHY_CAL_RANGE_MAX_0                           0x000001beU
-#define _reg_PHY_PAD_ATB_CTRL                              0x000001bfU
-#define _reg_PHY_ADRCTL_MANUAL_UPDATE                      0x000001c0U
-#define _reg_PHY_AC_LPBK_ERR_CLEAR                         0x000001c1U
-#define _reg_PHY_AC_LPBK_OBS_SELECT                        0x000001c2U
-#define _reg_PHY_AC_LPBK_ENABLE                            0x000001c3U
-#define _reg_PHY_AC_LPBK_CONTROL                           0x000001c4U
-#define _reg_PHY_AC_PRBS_PATTERN_START                     0x000001c5U
-#define _reg_PHY_AC_PRBS_PATTERN_MASK                      0x000001c6U
-#define _reg_PHY_AC_LPBK_RESULT_OBS                        0x000001c7U
-#define _reg_PHY_AC_CLK_LPBK_OBS_SELECT                    0x000001c8U
-#define _reg_PHY_AC_CLK_LPBK_ENABLE                        0x000001c9U
-#define _reg_PHY_AC_CLK_LPBK_CONTROL                       0x000001caU
-#define _reg_PHY_AC_CLK_LPBK_RESULT_OBS                    0x000001cbU
-#define _reg_PHY_AC_PWR_RDC_DISABLE                        0x000001ccU
-#define _reg_PHY_DATA_BYTE_ORDER_SEL                       0x000001cdU
-#define _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH                  0x000001ceU
-#define _reg_PHY_LPDDR4_CONNECT                            0x000001cfU
-#define _reg_PHY_CALVL_DEVICE_MAP                          0x000001d0U
-#define _reg_PHY_ADR_DISABLE                               0x000001d1U
-#define _reg_PHY_ADRCTL_MSTR_DLY_ENC_SEL                   0x000001d2U
-#define _reg_PHY_CS_DLY_UPT_PER_AC_SLICE                   0x000001d3U
-#define _reg_PHY_DDL_AC_ENABLE                             0x000001d4U
-#define _reg_PHY_DDL_AC_MODE                               0x000001d5U
-#define _reg_PHY_PAD_BACKGROUND_CAL                        0x000001d6U
-#define _reg_PHY_INIT_UPDATE_CONFIG                        0x000001d7U
-#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD_AC                0x000001d8U
-#define _reg_PHY_DLL_RST_EN                                0x000001d9U
-#define _reg_PHY_AC_INIT_COMPLETE_OBS                      0x000001daU
-#define _reg_PHY_DS_INIT_COMPLETE_OBS                      0x000001dbU
-#define _reg_PHY_UPDATE_MASK                               0x000001dcU
-#define _reg_PHY_PLL_SWITCH_CNT                            0x000001ddU
-#define _reg_PI_START                                      0x000001deU
-#define _reg_PI_DRAM_CLASS                                 0x000001dfU
-#define _reg_PI_VERSION                                    0x000001e0U
-#define _reg_PI_NORMAL_LVL_SEQ                             0x000001e1U
-#define _reg_PI_INIT_LVL_EN                                0x000001e2U
-#define _reg_PI_NOTCARE_PHYUPD                             0x000001e3U
-#define _reg_PI_ONBUS_MBIST                                0x000001e4U
-#define _reg_PI_TCMD_GAP                                   0x000001e5U
-#define _reg_PI_MASTER_ACK_DURATION_MIN                    0x000001e6U
-#define _reg_PI_DFI_VERSION                                0x000001e7U
-#define _reg_PI_TDFI_PHYMSTR_TYPE0                         0x000001e8U
-#define _reg_PI_TDFI_PHYMSTR_TYPE1                         0x000001e9U
-#define _reg_PI_TDFI_PHYMSTR_TYPE2                         0x000001eaU
-#define _reg_PI_TDFI_PHYMSTR_TYPE3                         0x000001ebU
-#define _reg_PI_DFI_PHYMSTR_TYPE                           0x000001ecU
-#define _reg_PI_DFI_PHYMSTR_CS_STATE_R                     0x000001edU
-#define _reg_PI_DFI_PHYMSTR_STATE_SEL_R                    0x000001eeU
-#define _reg_PI_TDFI_PHYMSTR_MAX_F0                        0x000001efU
-#define _reg_PI_TDFI_PHYMSTR_RESP_F0                       0x000001f0U
-#define _reg_PI_TDFI_PHYMSTR_MAX_F1                        0x000001f1U
-#define _reg_PI_TDFI_PHYMSTR_RESP_F1                       0x000001f2U
-#define _reg_PI_TDFI_PHYMSTR_MAX_F2                        0x000001f3U
-#define _reg_PI_TDFI_PHYMSTR_RESP_F2                       0x000001f4U
-#define _reg_PI_TDFI_PHYUPD_RESP_F0                        0x000001f5U
-#define _reg_PI_TDFI_PHYUPD_TYPE0_F0                       0x000001f6U
-#define _reg_PI_TDFI_PHYUPD_TYPE1_F0                       0x000001f7U
-#define _reg_PI_TDFI_PHYUPD_TYPE2_F0                       0x000001f8U
-#define _reg_PI_TDFI_PHYUPD_TYPE3_F0                       0x000001f9U
-#define _reg_PI_TDFI_PHYUPD_RESP_F1                        0x000001faU
-#define _reg_PI_TDFI_PHYUPD_TYPE0_F1                       0x000001fbU
-#define _reg_PI_TDFI_PHYUPD_TYPE1_F1                       0x000001fcU
-#define _reg_PI_TDFI_PHYUPD_TYPE2_F1                       0x000001fdU
-#define _reg_PI_TDFI_PHYUPD_TYPE3_F1                       0x000001feU
-#define _reg_PI_TDFI_PHYUPD_RESP_F2                        0x000001ffU
-#define _reg_PI_TDFI_PHYUPD_TYPE0_F2                       0x00000200U
-#define _reg_PI_TDFI_PHYUPD_TYPE1_F2                       0x00000201U
-#define _reg_PI_TDFI_PHYUPD_TYPE2_F2                       0x00000202U
-#define _reg_PI_TDFI_PHYUPD_TYPE3_F2                       0x00000203U
-#define _reg_PI_CONTROL_ERROR_STATUS                       0x00000204U
-#define _reg_PI_EXIT_AFTER_INIT_CALVL                      0x00000205U
-#define _reg_PI_FREQ_MAP                                   0x00000206U
-#define _reg_PI_INIT_WORK_FREQ                             0x00000207U
-#define _reg_PI_INIT_DFS_CALVL_ONLY                        0x00000208U
-#define _reg_PI_POWER_ON_SEQ_BYPASS_ARRAY                  0x00000209U
-#define _reg_PI_POWER_ON_SEQ_END_ARRAY                     0x0000020aU
-#define _reg_PI_SEQ1_PAT                                   0x0000020bU
-#define _reg_PI_SEQ1_PAT_MASK                              0x0000020cU
-#define _reg_PI_SEQ2_PAT                                   0x0000020dU
-#define _reg_PI_SEQ2_PAT_MASK                              0x0000020eU
-#define _reg_PI_SEQ3_PAT                                   0x0000020fU
-#define _reg_PI_SEQ3_PAT_MASK                              0x00000210U
-#define _reg_PI_SEQ4_PAT                                   0x00000211U
-#define _reg_PI_SEQ4_PAT_MASK                              0x00000212U
-#define _reg_PI_SEQ5_PAT                                   0x00000213U
-#define _reg_PI_SEQ5_PAT_MASK                              0x00000214U
-#define _reg_PI_SEQ6_PAT                                   0x00000215U
-#define _reg_PI_SEQ6_PAT_MASK                              0x00000216U
-#define _reg_PI_SEQ7_PAT                                   0x00000217U
-#define _reg_PI_SEQ7_PAT_MASK                              0x00000218U
-#define _reg_PI_SEQ8_PAT                                   0x00000219U
-#define _reg_PI_SEQ8_PAT_MASK                              0x0000021aU
-#define _reg_PI_WDT_DISABLE                                0x0000021bU
-#define _reg_PI_SW_RST_N                                   0x0000021cU
-#define _reg_RESERVED_R0                                   0x0000021dU
-#define _reg_PI_CS_MAP                                     0x0000021eU
-#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F0                  0x0000021fU
-#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F1                  0x00000220U
-#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F2                  0x00000221U
-#define _reg_PI_TMRR                                       0x00000222U
-#define _reg_PI_WRLAT_F0                                   0x00000223U
-#define _reg_PI_ADDITIVE_LAT_F0                            0x00000224U
-#define _reg_PI_CASLAT_LIN_F0                              0x00000225U
-#define _reg_PI_WRLAT_F1                                   0x00000226U
-#define _reg_PI_ADDITIVE_LAT_F1                            0x00000227U
-#define _reg_PI_CASLAT_LIN_F1                              0x00000228U
-#define _reg_PI_WRLAT_F2                                   0x00000229U
-#define _reg_PI_ADDITIVE_LAT_F2                            0x0000022aU
-#define _reg_PI_CASLAT_LIN_F2                              0x0000022bU
-#define _reg_PI_PREAMBLE_SUPPORT                           0x0000022cU
-#define _reg_PI_AREFRESH                                   0x0000022dU
-#define _reg_PI_MCAREF_FORWARD_ONLY                        0x0000022eU
-#define _reg_PI_TRFC_F0                                    0x0000022fU
-#define _reg_PI_TREF_F0                                    0x00000230U
-#define _reg_PI_TRFC_F1                                    0x00000231U
-#define _reg_PI_TREF_F1                                    0x00000232U
-#define _reg_PI_TRFC_F2                                    0x00000233U
-#define _reg_PI_TREF_F2                                    0x00000234U
-#define _reg_RESERVED_H3VER2                               0x00000235U
-#define _reg_PI_TREF_INTERVAL                              0x00000236U
-#define _reg_PI_FREQ_CHANGE_REG_COPY                       0x00000237U
-#define _reg_PI_FREQ_SEL_FROM_REGIF                        0x00000238U
-#define _reg_PI_SWLVL_LOAD                                 0x00000239U
-#define _reg_PI_SWLVL_OP_DONE                              0x0000023aU
-#define _reg_PI_SW_WRLVL_RESP_0                            0x0000023bU
-#define _reg_PI_SW_WRLVL_RESP_1                            0x0000023cU
-#define _reg_PI_SW_WRLVL_RESP_2                            0x0000023dU
-#define _reg_PI_SW_WRLVL_RESP_3                            0x0000023eU
-#define _reg_PI_SW_RDLVL_RESP_0                            0x0000023fU
-#define _reg_PI_SW_RDLVL_RESP_1                            0x00000240U
-#define _reg_PI_SW_RDLVL_RESP_2                            0x00000241U
-#define _reg_PI_SW_RDLVL_RESP_3                            0x00000242U
-#define _reg_PI_SW_CALVL_RESP_0                            0x00000243U
-#define _reg_PI_SW_LEVELING_MODE                           0x00000244U
-#define _reg_PI_SWLVL_START                                0x00000245U
-#define _reg_PI_SWLVL_EXIT                                 0x00000246U
-#define _reg_PI_SWLVL_WR_SLICE_0                           0x00000247U
-#define _reg_PI_SWLVL_RD_SLICE_0                           0x00000248U
-#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_0                  0x00000249U
-#define _reg_PI_SW_WDQLVL_RESP_0                           0x0000024aU
-#define _reg_PI_SWLVL_WR_SLICE_1                           0x0000024bU
-#define _reg_PI_SWLVL_RD_SLICE_1                           0x0000024cU
-#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_1                  0x0000024dU
-#define _reg_PI_SW_WDQLVL_RESP_1                           0x0000024eU
-#define _reg_PI_SWLVL_WR_SLICE_2                           0x0000024fU
-#define _reg_PI_SWLVL_RD_SLICE_2                           0x00000250U
-#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_2                  0x00000251U
-#define _reg_PI_SW_WDQLVL_RESP_2                           0x00000252U
-#define _reg_PI_SWLVL_WR_SLICE_3                           0x00000253U
-#define _reg_PI_SWLVL_RD_SLICE_3                           0x00000254U
-#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_3                  0x00000255U
-#define _reg_PI_SW_WDQLVL_RESP_3                           0x00000256U
-#define _reg_PI_SW_WDQLVL_VREF                             0x00000257U
-#define _reg_PI_SWLVL_SM2_START                            0x00000258U
-#define _reg_PI_SWLVL_SM2_WR                               0x00000259U
-#define _reg_PI_SWLVL_SM2_RD                               0x0000025aU
-#define _reg_PI_SEQUENTIAL_LVL_REQ                         0x0000025bU
-#define _reg_PI_DFS_PERIOD_EN                              0x0000025cU
-#define _reg_PI_SRE_PERIOD_EN                              0x0000025dU
-#define _reg_PI_DFI40_POLARITY                             0x0000025eU
-#define _reg_PI_16BIT_DRAM_CONNECT                         0x0000025fU
-#define _reg_PI_TDFI_CTRL_DELAY_F0                         0x00000260U
-#define _reg_PI_TDFI_CTRL_DELAY_F1                         0x00000261U
-#define _reg_PI_TDFI_CTRL_DELAY_F2                         0x00000262U
-#define _reg_PI_WRLVL_REQ                                  0x00000263U
-#define _reg_PI_WRLVL_CS                                   0x00000264U
-#define _reg_PI_WLDQSEN                                    0x00000265U
-#define _reg_PI_WLMRD                                      0x00000266U
-#define _reg_PI_WRLVL_EN_F0                                0x00000267U
-#define _reg_PI_WRLVL_EN_F1                                0x00000268U
-#define _reg_PI_WRLVL_EN_F2                                0x00000269U
-#define _reg_PI_WRLVL_EN                                   0x0000026aU
-#define _reg_PI_WRLVL_INTERVAL                             0x0000026bU
-#define _reg_PI_WRLVL_PERIODIC                             0x0000026cU
-#define _reg_PI_WRLVL_ON_SREF_EXIT                         0x0000026dU
-#define _reg_PI_WRLVL_DISABLE_DFS                          0x0000026eU
-#define _reg_PI_WRLVL_RESP_MASK                            0x0000026fU
-#define _reg_PI_WRLVL_ROTATE                               0x00000270U
-#define _reg_PI_WRLVL_CS_MAP                               0x00000271U
-#define _reg_PI_WRLVL_ERROR_STATUS                         0x00000272U
-#define _reg_PI_TDFI_WRLVL_EN                              0x00000273U
-#define _reg_PI_TDFI_WRLVL_WW_F0                           0x00000274U
-#define _reg_PI_TDFI_WRLVL_WW_F1                           0x00000275U
-#define _reg_PI_TDFI_WRLVL_WW_F2                           0x00000276U
-#define _reg_PI_TDFI_WRLVL_WW                              0x00000277U
-#define _reg_PI_TDFI_WRLVL_RESP                            0x00000278U
-#define _reg_PI_TDFI_WRLVL_MAX                             0x00000279U
-#define _reg_PI_WRLVL_STROBE_NUM                           0x0000027aU
-#define _reg_PI_WRLVL_MRR_DQ_RETURN_HIZ                    0x0000027bU
-#define _reg_PI_WRLVL_EN_DEASSERT_2_MRR                    0x0000027cU
-#define _reg_PI_TODTL_2CMD_F0                              0x0000027dU
-#define _reg_PI_ODT_EN_F0                                  0x0000027eU
-#define _reg_PI_TODTL_2CMD_F1                              0x0000027fU
-#define _reg_PI_ODT_EN_F1                                  0x00000280U
-#define _reg_PI_TODTL_2CMD_F2                              0x00000281U
-#define _reg_PI_ODT_EN_F2                                  0x00000282U
-#define _reg_PI_TODTH_WR                                   0x00000283U
-#define _reg_PI_TODTH_RD                                   0x00000284U
-#define _reg_PI_ODT_RD_MAP_CS0                             0x00000285U
-#define _reg_PI_ODT_WR_MAP_CS0                             0x00000286U
-#define _reg_PI_ODT_RD_MAP_CS1                             0x00000287U
-#define _reg_PI_ODT_WR_MAP_CS1                             0x00000288U
-#define _reg_PI_ODT_RD_MAP_CS2                             0x00000289U
-#define _reg_PI_ODT_WR_MAP_CS2                             0x0000028aU
-#define _reg_PI_ODT_RD_MAP_CS3                             0x0000028bU
-#define _reg_PI_ODT_WR_MAP_CS3                             0x0000028cU
-#define _reg_PI_EN_ODT_ASSERT_EXCEPT_RD                    0x0000028dU
-#define _reg_PI_ODTLON_F0                                  0x0000028eU
-#define _reg_PI_TODTON_MIN_F0                              0x0000028fU
-#define _reg_PI_ODTLON_F1                                  0x00000290U
-#define _reg_PI_TODTON_MIN_F1                              0x00000291U
-#define _reg_PI_ODTLON_F2                                  0x00000292U
-#define _reg_PI_TODTON_MIN_F2                              0x00000293U
-#define _reg_PI_WR_TO_ODTH_F0                              0x00000294U
-#define _reg_PI_WR_TO_ODTH_F1                              0x00000295U
-#define _reg_PI_WR_TO_ODTH_F2                              0x00000296U
-#define _reg_PI_RD_TO_ODTH_F0                              0x00000297U
-#define _reg_PI_RD_TO_ODTH_F1                              0x00000298U
-#define _reg_PI_RD_TO_ODTH_F2                              0x00000299U
-#define _reg_PI_ADDRESS_MIRRORING                          0x0000029aU
-#define _reg_PI_RDLVL_REQ                                  0x0000029bU
-#define _reg_PI_RDLVL_GATE_REQ                             0x0000029cU
-#define _reg_PI_RDLVL_CS                                   0x0000029dU
-#define _reg_PI_RDLVL_PAT_0                                0x0000029eU
-#define _reg_PI_RDLVL_PAT_1                                0x0000029fU
-#define _reg_PI_RDLVL_PAT_2                                0x000002a0U
-#define _reg_PI_RDLVL_PAT_3                                0x000002a1U
-#define _reg_PI_RDLVL_PAT_4                                0x000002a2U
-#define _reg_PI_RDLVL_PAT_5                                0x000002a3U
-#define _reg_PI_RDLVL_PAT_6                                0x000002a4U
-#define _reg_PI_RDLVL_PAT_7                                0x000002a5U
-#define _reg_PI_RDLVL_SEQ_EN                               0x000002a6U
-#define _reg_PI_RDLVL_GATE_SEQ_EN                          0x000002a7U
-#define _reg_PI_RDLVL_PERIODIC                             0x000002a8U
-#define _reg_PI_RDLVL_ON_SREF_EXIT                         0x000002a9U
-#define _reg_PI_RDLVL_DISABLE_DFS                          0x000002aaU
-#define _reg_PI_RDLVL_GATE_PERIODIC                        0x000002abU
-#define _reg_PI_RDLVL_GATE_ON_SREF_EXIT                    0x000002acU
-#define _reg_PI_RDLVL_GATE_DISABLE_DFS                     0x000002adU
-#define _reg_RESERVED_R1                                   0x000002aeU
-#define _reg_PI_RDLVL_ROTATE                               0x000002afU
-#define _reg_PI_RDLVL_GATE_ROTATE                          0x000002b0U
-#define _reg_PI_RDLVL_CS_MAP                               0x000002b1U
-#define _reg_PI_RDLVL_GATE_CS_MAP                          0x000002b2U
-#define _reg_PI_TDFI_RDLVL_RR                              0x000002b3U
-#define _reg_PI_TDFI_RDLVL_RESP                            0x000002b4U
-#define _reg_PI_RDLVL_RESP_MASK                            0x000002b5U
-#define _reg_PI_TDFI_RDLVL_EN                              0x000002b6U
-#define _reg_PI_RDLVL_EN_F0                                0x000002b7U
-#define _reg_PI_RDLVL_GATE_EN_F0                           0x000002b8U
-#define _reg_PI_RDLVL_EN_F1                                0x000002b9U
-#define _reg_PI_RDLVL_GATE_EN_F1                           0x000002baU
-#define _reg_PI_RDLVL_EN_F2                                0x000002bbU
-#define _reg_PI_RDLVL_GATE_EN_F2                           0x000002bcU
-#define _reg_PI_RDLVL_EN                                   0x000002bdU
-#define _reg_PI_RDLVL_GATE_EN                              0x000002beU
-#define _reg_PI_TDFI_RDLVL_MAX                             0x000002bfU
-#define _reg_PI_RDLVL_ERROR_STATUS                         0x000002c0U
-#define _reg_PI_RDLVL_INTERVAL                             0x000002c1U
-#define _reg_PI_RDLVL_GATE_INTERVAL                        0x000002c2U
-#define _reg_PI_RDLVL_PATTERN_START                        0x000002c3U
-#define _reg_PI_RDLVL_PATTERN_NUM                          0x000002c4U
-#define _reg_PI_RDLVL_STROBE_NUM                           0x000002c5U
-#define _reg_PI_RDLVL_GATE_STROBE_NUM                      0x000002c6U
-#define _reg_PI_LPDDR4_RDLVL_PATTERN_8                     0x000002c7U
-#define _reg_PI_LPDDR4_RDLVL_PATTERN_9                     0x000002c8U
-#define _reg_PI_LPDDR4_RDLVL_PATTERN_10                    0x000002c9U
-#define _reg_PI_LPDDR4_RDLVL_PATTERN_11                    0x000002caU
-#define _reg_PI_RD_PREAMBLE_TRAINING_EN                    0x000002cbU
-#define _reg_PI_REG_DIMM_ENABLE                            0x000002ccU
-#define _reg_PI_RDLAT_ADJ_F0                               0x000002cdU
-#define _reg_PI_RDLAT_ADJ_F1                               0x000002ceU
-#define _reg_PI_RDLAT_ADJ_F2                               0x000002cfU
-#define _reg_PI_TDFI_RDDATA_EN                             0x000002d0U
-#define _reg_PI_WRLAT_ADJ_F0                               0x000002d1U
-#define _reg_PI_WRLAT_ADJ_F1                               0x000002d2U
-#define _reg_PI_WRLAT_ADJ_F2                               0x000002d3U
-#define _reg_PI_TDFI_PHY_WRLAT                             0x000002d4U
-#define _reg_PI_TDFI_WRCSLAT_F0                            0x000002d5U
-#define _reg_PI_TDFI_WRCSLAT_F1                            0x000002d6U
-#define _reg_PI_TDFI_WRCSLAT_F2                            0x000002d7U
-#define _reg_PI_TDFI_RDCSLAT_F0                            0x000002d8U
-#define _reg_PI_TDFI_RDCSLAT_F1                            0x000002d9U
-#define _reg_PI_TDFI_RDCSLAT_F2                            0x000002daU
-#define _reg_PI_TDFI_PHY_WRDATA_F0                         0x000002dbU
-#define _reg_PI_TDFI_PHY_WRDATA_F1                         0x000002dcU
-#define _reg_PI_TDFI_PHY_WRDATA_F2                         0x000002ddU
-#define _reg_PI_TDFI_PHY_WRDATA                            0x000002deU
-#define _reg_PI_CALVL_REQ                                  0x000002dfU
-#define _reg_PI_CALVL_CS                                   0x000002e0U
-#define _reg_RESERVED_R2                                   0x000002e1U
-#define _reg_RESERVED_R3                                   0x000002e2U
-#define _reg_PI_CALVL_SEQ_EN                               0x000002e3U
-#define _reg_PI_CALVL_PERIODIC                             0x000002e4U
-#define _reg_PI_CALVL_ON_SREF_EXIT                         0x000002e5U
-#define _reg_PI_CALVL_DISABLE_DFS                          0x000002e6U
-#define _reg_PI_CALVL_ROTATE                               0x000002e7U
-#define _reg_PI_CALVL_CS_MAP                               0x000002e8U
-#define _reg_PI_TDFI_CALVL_EN                              0x000002e9U
-#define _reg_PI_TDFI_CALVL_CC_F0                           0x000002eaU
-#define _reg_PI_TDFI_CALVL_CAPTURE_F0                      0x000002ebU
-#define _reg_PI_TDFI_CALVL_CC_F1                           0x000002ecU
-#define _reg_PI_TDFI_CALVL_CAPTURE_F1                      0x000002edU
-#define _reg_PI_TDFI_CALVL_CC_F2                           0x000002eeU
-#define _reg_PI_TDFI_CALVL_CAPTURE_F2                      0x000002efU
-#define _reg_PI_TDFI_CALVL_RESP                            0x000002f0U
-#define _reg_PI_TDFI_CALVL_MAX                             0x000002f1U
-#define _reg_PI_CALVL_RESP_MASK                            0x000002f2U
-#define _reg_PI_CALVL_EN_F0                                0x000002f3U
-#define _reg_PI_CALVL_EN_F1                                0x000002f4U
-#define _reg_PI_CALVL_EN_F2                                0x000002f5U
-#define _reg_PI_CALVL_EN                                   0x000002f6U
-#define _reg_PI_CALVL_ERROR_STATUS                         0x000002f7U
-#define _reg_PI_CALVL_INTERVAL                             0x000002f8U
-#define _reg_PI_TCACKEL                                    0x000002f9U
-#define _reg_PI_TCAMRD                                     0x000002faU
-#define _reg_PI_TCACKEH                                    0x000002fbU
-#define _reg_PI_TMRZ_F0                                    0x000002fcU
-#define _reg_PI_TCAENT_F0                                  0x000002fdU
-#define _reg_PI_TMRZ_F1                                    0x000002feU
-#define _reg_PI_TCAENT_F1                                  0x000002ffU
-#define _reg_PI_TMRZ_F2                                    0x00000300U
-#define _reg_PI_TCAENT_F2                                  0x00000301U
-#define _reg_PI_TCAEXT                                     0x00000302U
-#define _reg_PI_CA_TRAIN_VREF_EN                           0x00000303U
-#define _reg_PI_TDFI_CACSCA_F0                             0x00000304U
-#define _reg_PI_TDFI_CASEL_F0                              0x00000305U
-#define _reg_PI_TVREF_SHORT_F0                             0x00000306U
-#define _reg_PI_TVREF_LONG_F0                              0x00000307U
-#define _reg_PI_TDFI_CACSCA_F1                             0x00000308U
-#define _reg_PI_TDFI_CASEL_F1                              0x00000309U
-#define _reg_PI_TVREF_SHORT_F1                             0x0000030aU
-#define _reg_PI_TVREF_LONG_F1                              0x0000030bU
-#define _reg_PI_TDFI_CACSCA_F2                             0x0000030cU
-#define _reg_PI_TDFI_CASEL_F2                              0x0000030dU
-#define _reg_PI_TVREF_SHORT_F2                             0x0000030eU
-#define _reg_PI_TVREF_LONG_F2                              0x0000030fU
-#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F0          0x00000310U
-#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F0           0x00000311U
-#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F1          0x00000312U
-#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F1           0x00000313U
-#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F2          0x00000314U
-#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F2           0x00000315U
-#define _reg_PI_CALVL_VREF_INITIAL_START_POINT             0x00000316U
-#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT              0x00000317U
-#define _reg_PI_CALVL_VREF_INITIAL_STEPSIZE                0x00000318U
-#define _reg_PI_CALVL_VREF_NORMAL_STEPSIZE                 0x00000319U
-#define _reg_PI_CALVL_VREF_DELTA_F0                        0x0000031aU
-#define _reg_PI_CALVL_VREF_DELTA_F1                        0x0000031bU
-#define _reg_PI_CALVL_VREF_DELTA_F2                        0x0000031cU
-#define _reg_PI_CALVL_VREF_DELTA                           0x0000031dU
-#define _reg_PI_TDFI_INIT_START_MIN                        0x0000031eU
-#define _reg_PI_TDFI_INIT_COMPLETE_MIN                     0x0000031fU
-#define _reg_PI_TDFI_CALVL_STROBE_F0                       0x00000320U
-#define _reg_PI_TXP_F0                                     0x00000321U
-#define _reg_PI_TMRWCKEL_F0                                0x00000322U
-#define _reg_PI_TCKELCK_F0                                 0x00000323U
-#define _reg_PI_TDFI_CALVL_STROBE_F1                       0x00000324U
-#define _reg_PI_TXP_F1                                     0x00000325U
-#define _reg_PI_TMRWCKEL_F1                                0x00000326U
-#define _reg_PI_TCKELCK_F1                                 0x00000327U
-#define _reg_PI_TDFI_CALVL_STROBE_F2                       0x00000328U
-#define _reg_PI_TXP_F2                                     0x00000329U
-#define _reg_PI_TMRWCKEL_F2                                0x0000032aU
-#define _reg_PI_TCKELCK_F2                                 0x0000032bU
-#define _reg_PI_TCKCKEH                                    0x0000032cU
-#define _reg_PI_CALVL_STROBE_NUM                           0x0000032dU
-#define _reg_PI_SW_CA_TRAIN_VREF                           0x0000032eU
-#define _reg_PI_TDFI_INIT_START_F0                         0x0000032fU
-#define _reg_PI_TDFI_INIT_COMPLETE_F0                      0x00000330U
-#define _reg_PI_TDFI_INIT_START_F1                         0x00000331U
-#define _reg_PI_TDFI_INIT_COMPLETE_F1                      0x00000332U
-#define _reg_PI_TDFI_INIT_START_F2                         0x00000333U
-#define _reg_PI_TDFI_INIT_COMPLETE_F2                      0x00000334U
-#define _reg_PI_CLKDISABLE_2_INIT_START                    0x00000335U
-#define _reg_PI_INIT_STARTORCOMPLETE_2_CLKDISABLE          0x00000336U
-#define _reg_PI_DRAM_CLK_DISABLE_DEASSERT_SEL              0x00000337U
-#define _reg_PI_REFRESH_BETWEEN_SEGMENT_DISABLE            0x00000338U
-#define _reg_PI_TCKEHDQS_F0                                0x00000339U
-#define _reg_PI_TCKEHDQS_F1                                0x0000033aU
-#define _reg_PI_TCKEHDQS_F2                                0x0000033bU
-#define _reg_PI_MC_DFS_PI_SET_VREF_ENABLE                  0x0000033cU
-#define _reg_PI_WDQLVL_VREF_EN                             0x0000033dU
-#define _reg_PI_WDQLVL_BST_NUM                             0x0000033eU
-#define _reg_PI_TDFI_WDQLVL_WR_F0                          0x0000033fU
-#define _reg_PI_TDFI_WDQLVL_WR_F1                          0x00000340U
-#define _reg_PI_TDFI_WDQLVL_WR_F2                          0x00000341U
-#define _reg_PI_TDFI_WDQLVL_WR                             0x00000342U
-#define _reg_PI_TDFI_WDQLVL_RW                             0x00000343U
-#define _reg_PI_WDQLVL_RESP_MASK                           0x00000344U
-#define _reg_PI_WDQLVL_ROTATE                              0x00000345U
-#define _reg_PI_WDQLVL_CS_MAP                              0x00000346U
-#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F0         0x00000347U
-#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0          0x00000348U
-#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1         0x00000349U
-#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1          0x0000034aU
-#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F2         0x0000034bU
-#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2          0x0000034cU
-#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT            0x0000034dU
-#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT             0x0000034eU
-#define _reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE               0x0000034fU
-#define _reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE                0x00000350U
-#define _reg_PI_WDQLVL_VREF_DELTA_F0                       0x00000351U
-#define _reg_PI_WDQLVL_VREF_DELTA_F1                       0x00000352U
-#define _reg_PI_WDQLVL_VREF_DELTA_F2                       0x00000353U
-#define _reg_PI_WDQLVL_VREF_DELTA                          0x00000354U
-#define _reg_PI_WDQLVL_PERIODIC                            0x00000355U
-#define _reg_PI_WDQLVL_REQ                                 0x00000356U
-#define _reg_PI_WDQLVL_CS                                  0x00000357U
-#define _reg_PI_TDFI_WDQLVL_EN                             0x00000358U
-#define _reg_PI_TDFI_WDQLVL_RESP                           0x00000359U
-#define _reg_PI_TDFI_WDQLVL_MAX                            0x0000035aU
-#define _reg_PI_WDQLVL_INTERVAL                            0x0000035bU
-#define _reg_PI_WDQLVL_EN_F0                               0x0000035cU
-#define _reg_PI_WDQLVL_EN_F1                               0x0000035dU
-#define _reg_PI_WDQLVL_EN_F2                               0x0000035eU
-#define _reg_PI_WDQLVL_EN                                  0x0000035fU
-#define _reg_PI_WDQLVL_ON_SREF_EXIT                        0x00000360U
-#define _reg_PI_WDQLVL_DISABLE_DFS                         0x00000361U
-#define _reg_PI_WDQLVL_ERROR_STATUS                        0x00000362U
-#define _reg_PI_MR1_DATA_F0_0                              0x00000363U
-#define _reg_PI_MR2_DATA_F0_0                              0x00000364U
-#define _reg_PI_MR3_DATA_F0_0                              0x00000365U
-#define _reg_PI_MR11_DATA_F0_0                             0x00000366U
-#define _reg_PI_MR12_DATA_F0_0                             0x00000367U
-#define _reg_PI_MR14_DATA_F0_0                             0x00000368U
-#define _reg_PI_MR22_DATA_F0_0                             0x00000369U
-#define _reg_PI_MR1_DATA_F1_0                              0x0000036aU
-#define _reg_PI_MR2_DATA_F1_0                              0x0000036bU
-#define _reg_PI_MR3_DATA_F1_0                              0x0000036cU
-#define _reg_PI_MR11_DATA_F1_0                             0x0000036dU
-#define _reg_PI_MR12_DATA_F1_0                             0x0000036eU
-#define _reg_PI_MR14_DATA_F1_0                             0x0000036fU
-#define _reg_PI_MR22_DATA_F1_0                             0x00000370U
-#define _reg_PI_MR1_DATA_F2_0                              0x00000371U
-#define _reg_PI_MR2_DATA_F2_0                              0x00000372U
-#define _reg_PI_MR3_DATA_F2_0                              0x00000373U
-#define _reg_PI_MR11_DATA_F2_0                             0x00000374U
-#define _reg_PI_MR12_DATA_F2_0                             0x00000375U
-#define _reg_PI_MR14_DATA_F2_0                             0x00000376U
-#define _reg_PI_MR22_DATA_F2_0                             0x00000377U
-#define _reg_PI_MR13_DATA_0                                0x00000378U
-#define _reg_PI_MR1_DATA_F0_1                              0x00000379U
-#define _reg_PI_MR2_DATA_F0_1                              0x0000037aU
-#define _reg_PI_MR3_DATA_F0_1                              0x0000037bU
-#define _reg_PI_MR11_DATA_F0_1                             0x0000037cU
-#define _reg_PI_MR12_DATA_F0_1                             0x0000037dU
-#define _reg_PI_MR14_DATA_F0_1                             0x0000037eU
-#define _reg_PI_MR22_DATA_F0_1                             0x0000037fU
-#define _reg_PI_MR1_DATA_F1_1                              0x00000380U
-#define _reg_PI_MR2_DATA_F1_1                              0x00000381U
-#define _reg_PI_MR3_DATA_F1_1                              0x00000382U
-#define _reg_PI_MR11_DATA_F1_1                             0x00000383U
-#define _reg_PI_MR12_DATA_F1_1                             0x00000384U
-#define _reg_PI_MR14_DATA_F1_1                             0x00000385U
-#define _reg_PI_MR22_DATA_F1_1                             0x00000386U
-#define _reg_PI_MR1_DATA_F2_1                              0x00000387U
-#define _reg_PI_MR2_DATA_F2_1                              0x00000388U
-#define _reg_PI_MR3_DATA_F2_1                              0x00000389U
-#define _reg_PI_MR11_DATA_F2_1                             0x0000038aU
-#define _reg_PI_MR12_DATA_F2_1                             0x0000038bU
-#define _reg_PI_MR14_DATA_F2_1                             0x0000038cU
-#define _reg_PI_MR22_DATA_F2_1                             0x0000038dU
-#define _reg_PI_MR13_DATA_1                                0x0000038eU
-#define _reg_PI_MR1_DATA_F0_2                              0x0000038fU
-#define _reg_PI_MR2_DATA_F0_2                              0x00000390U
-#define _reg_PI_MR3_DATA_F0_2                              0x00000391U
-#define _reg_PI_MR11_DATA_F0_2                             0x00000392U
-#define _reg_PI_MR12_DATA_F0_2                             0x00000393U
-#define _reg_PI_MR14_DATA_F0_2                             0x00000394U
-#define _reg_PI_MR22_DATA_F0_2                             0x00000395U
-#define _reg_PI_MR1_DATA_F1_2                              0x00000396U
-#define _reg_PI_MR2_DATA_F1_2                              0x00000397U
-#define _reg_PI_MR3_DATA_F1_2                              0x00000398U
-#define _reg_PI_MR11_DATA_F1_2                             0x00000399U
-#define _reg_PI_MR12_DATA_F1_2                             0x0000039aU
-#define _reg_PI_MR14_DATA_F1_2                             0x0000039bU
-#define _reg_PI_MR22_DATA_F1_2                             0x0000039cU
-#define _reg_PI_MR1_DATA_F2_2                              0x0000039dU
-#define _reg_PI_MR2_DATA_F2_2                              0x0000039eU
-#define _reg_PI_MR3_DATA_F2_2                              0x0000039fU
-#define _reg_PI_MR11_DATA_F2_2                             0x000003a0U
-#define _reg_PI_MR12_DATA_F2_2                             0x000003a1U
-#define _reg_PI_MR14_DATA_F2_2                             0x000003a2U
-#define _reg_PI_MR22_DATA_F2_2                             0x000003a3U
-#define _reg_PI_MR13_DATA_2                                0x000003a4U
-#define _reg_PI_MR1_DATA_F0_3                              0x000003a5U
-#define _reg_PI_MR2_DATA_F0_3                              0x000003a6U
-#define _reg_PI_MR3_DATA_F0_3                              0x000003a7U
-#define _reg_PI_MR11_DATA_F0_3                             0x000003a8U
-#define _reg_PI_MR12_DATA_F0_3                             0x000003a9U
-#define _reg_PI_MR14_DATA_F0_3                             0x000003aaU
-#define _reg_PI_MR22_DATA_F0_3                             0x000003abU
-#define _reg_PI_MR1_DATA_F1_3                              0x000003acU
-#define _reg_PI_MR2_DATA_F1_3                              0x000003adU
-#define _reg_PI_MR3_DATA_F1_3                              0x000003aeU
-#define _reg_PI_MR11_DATA_F1_3                             0x000003afU
-#define _reg_PI_MR12_DATA_F1_3                             0x000003b0U
-#define _reg_PI_MR14_DATA_F1_3                             0x000003b1U
-#define _reg_PI_MR22_DATA_F1_3                             0x000003b2U
-#define _reg_PI_MR1_DATA_F2_3                              0x000003b3U
-#define _reg_PI_MR2_DATA_F2_3                              0x000003b4U
-#define _reg_PI_MR3_DATA_F2_3                              0x000003b5U
-#define _reg_PI_MR11_DATA_F2_3                             0x000003b6U
-#define _reg_PI_MR12_DATA_F2_3                             0x000003b7U
-#define _reg_PI_MR14_DATA_F2_3                             0x000003b8U
-#define _reg_PI_MR22_DATA_F2_3                             0x000003b9U
-#define _reg_PI_MR13_DATA_3                                0x000003baU
-#define _reg_PI_BANK_DIFF                                  0x000003bbU
-#define _reg_PI_ROW_DIFF                                   0x000003bcU
-#define _reg_PI_TFC_F0                                     0x000003bdU
-#define _reg_PI_TFC_F1                                     0x000003beU
-#define _reg_PI_TFC_F2                                     0x000003bfU
-#define _reg_PI_TCCD                                       0x000003c0U
-#define _reg_PI_TRTP_F0                                    0x000003c1U
-#define _reg_PI_TRP_F0                                     0x000003c2U
-#define _reg_PI_TRCD_F0                                    0x000003c3U
-#define _reg_PI_TWTR_F0                                    0x000003c4U
-#define _reg_PI_TWR_F0                                     0x000003c5U
-#define _reg_PI_TRAS_MAX_F0                                0x000003c6U
-#define _reg_PI_TRAS_MIN_F0                                0x000003c7U
-#define _reg_PI_TDQSCK_MAX_F0                              0x000003c8U
-#define _reg_PI_TCCDMW_F0                                  0x000003c9U
-#define _reg_PI_TSR_F0                                     0x000003caU
-#define _reg_PI_TMRD_F0                                    0x000003cbU
-#define _reg_PI_TMRW_F0                                    0x000003ccU
-#define _reg_PI_TMOD_F0                                    0x000003cdU
-#define _reg_PI_TRTP_F1                                    0x000003ceU
-#define _reg_PI_TRP_F1                                     0x000003cfU
-#define _reg_PI_TRCD_F1                                    0x000003d0U
-#define _reg_PI_TWTR_F1                                    0x000003d1U
-#define _reg_PI_TWR_F1                                     0x000003d2U
-#define _reg_PI_TRAS_MAX_F1                                0x000003d3U
-#define _reg_PI_TRAS_MIN_F1                                0x000003d4U
-#define _reg_PI_TDQSCK_MAX_F1                              0x000003d5U
-#define _reg_PI_TCCDMW_F1                                  0x000003d6U
-#define _reg_PI_TSR_F1                                     0x000003d7U
-#define _reg_PI_TMRD_F1                                    0x000003d8U
-#define _reg_PI_TMRW_F1                                    0x000003d9U
-#define _reg_PI_TMOD_F1                                    0x000003daU
-#define _reg_PI_TRTP_F2                                    0x000003dbU
-#define _reg_PI_TRP_F2                                     0x000003dcU
-#define _reg_PI_TRCD_F2                                    0x000003ddU
-#define _reg_PI_TWTR_F2                                    0x000003deU
-#define _reg_PI_TWR_F2                                     0x000003dfU
-#define _reg_PI_TRAS_MAX_F2                                0x000003e0U
-#define _reg_PI_TRAS_MIN_F2                                0x000003e1U
-#define _reg_PI_TDQSCK_MAX_F2                              0x000003e2U
-#define _reg_PI_TCCDMW_F2                                  0x000003e3U
-#define _reg_PI_TSR_F2                                     0x000003e4U
-#define _reg_PI_TMRD_F2                                    0x000003e5U
-#define _reg_PI_TMRW_F2                                    0x000003e6U
-#define _reg_PI_TMOD_F2                                    0x000003e7U
-#define _reg_RESERVED_R4                                   0x000003e8U
-#define _reg_RESERVED_R5                                   0x000003e9U
-#define _reg_RESERVED_R6                                   0x000003eaU
-#define _reg_RESERVED_R7                                   0x000003ebU
-#define _reg_RESERVED_R8                                   0x000003ecU
-#define _reg_RESERVED_R9                                   0x000003edU
-#define _reg_RESERVED_R10                                  0x000003eeU
-#define _reg_RESERVED_R11                                  0x000003efU
-#define _reg_RESERVED_R12                                  0x000003f0U
-#define _reg_RESERVED_R13                                  0x000003f1U
-#define _reg_RESERVED_R14                                  0x000003f2U
-#define _reg_RESERVED_R15                                  0x000003f3U
-#define _reg_RESERVED_R16                                  0x000003f4U
-#define _reg_RESERVED_R17                                  0x000003f5U
-#define _reg_RESERVED_R18                                  0x000003f6U
-#define _reg_RESERVED_R19                                  0x000003f7U
-#define _reg_RESERVED_R20                                  0x000003f8U
-#define _reg_RESERVED_R21                                  0x000003f9U
-#define _reg_RESERVED_R22                                  0x000003faU
-#define _reg_RESERVED_R23                                  0x000003fbU
-#define _reg_PI_INT_STATUS                                 0x000003fcU
-#define _reg_PI_INT_ACK                                    0x000003fdU
-#define _reg_PI_INT_MASK                                   0x000003feU
-#define _reg_PI_BIST_EXP_DATA_P0                           0x000003ffU
-#define _reg_PI_BIST_EXP_DATA_P1                           0x00000400U
-#define _reg_PI_BIST_EXP_DATA_P2                           0x00000401U
-#define _reg_PI_BIST_EXP_DATA_P3                           0x00000402U
-#define _reg_PI_BIST_FAIL_DATA_P0                          0x00000403U
-#define _reg_PI_BIST_FAIL_DATA_P1                          0x00000404U
-#define _reg_PI_BIST_FAIL_DATA_P2                          0x00000405U
-#define _reg_PI_BIST_FAIL_DATA_P3                          0x00000406U
-#define _reg_PI_BIST_FAIL_ADDR_P0                          0x00000407U
-#define _reg_PI_BIST_FAIL_ADDR_P1                          0x00000408U
-#define _reg_PI_BSTLEN                                     0x00000409U
-#define _reg_PI_LONG_COUNT_MASK                            0x0000040aU
-#define _reg_PI_CMD_SWAP_EN                                0x0000040bU
-#define _reg_PI_CKE_MUX_0                                  0x0000040cU
-#define _reg_PI_CKE_MUX_1                                  0x0000040dU
-#define _reg_PI_CKE_MUX_2                                  0x0000040eU
-#define _reg_PI_CKE_MUX_3                                  0x0000040fU
-#define _reg_PI_CS_MUX_0                                   0x00000410U
-#define _reg_PI_CS_MUX_1                                   0x00000411U
-#define _reg_PI_CS_MUX_2                                   0x00000412U
-#define _reg_PI_CS_MUX_3                                   0x00000413U
-#define _reg_PI_RAS_N_MUX                                  0x00000414U
-#define _reg_PI_CAS_N_MUX                                  0x00000415U
-#define _reg_PI_WE_N_MUX                                   0x00000416U
-#define _reg_PI_BANK_MUX_0                                 0x00000417U
-#define _reg_PI_BANK_MUX_1                                 0x00000418U
-#define _reg_PI_BANK_MUX_2                                 0x00000419U
-#define _reg_PI_ODT_MUX_0                                  0x0000041aU
-#define _reg_PI_ODT_MUX_1                                  0x0000041bU
-#define _reg_PI_ODT_MUX_2                                  0x0000041cU
-#define _reg_PI_ODT_MUX_3                                  0x0000041dU
-#define _reg_PI_RESET_N_MUX_0                              0x0000041eU
-#define _reg_PI_RESET_N_MUX_1                              0x0000041fU
-#define _reg_PI_RESET_N_MUX_2                              0x00000420U
-#define _reg_PI_RESET_N_MUX_3                              0x00000421U
-#define _reg_PI_DATA_BYTE_SWAP_EN                          0x00000422U
-#define _reg_PI_DATA_BYTE_SWAP_SLICE0                      0x00000423U
-#define _reg_PI_DATA_BYTE_SWAP_SLICE1                      0x00000424U
-#define _reg_PI_DATA_BYTE_SWAP_SLICE2                      0x00000425U
-#define _reg_PI_DATA_BYTE_SWAP_SLICE3                      0x00000426U
-#define _reg_PI_CTRLUPD_REQ_PER_AREF_EN                    0x00000427U
-#define _reg_PI_TDFI_CTRLUPD_MIN                           0x00000428U
-#define _reg_PI_TDFI_CTRLUPD_MAX_F0                        0x00000429U
-#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F0                   0x0000042aU
-#define _reg_PI_TDFI_CTRLUPD_MAX_F1                        0x0000042bU
-#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F1                   0x0000042cU
-#define _reg_PI_TDFI_CTRLUPD_MAX_F2                        0x0000042dU
-#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F2                   0x0000042eU
-#define _reg_PI_UPDATE_ERROR_STATUS                        0x0000042fU
-#define _reg_PI_BIST_GO                                    0x00000430U
-#define _reg_PI_BIST_RESULT                                0x00000431U
-#define _reg_PI_ADDR_SPACE                                 0x00000432U
-#define _reg_PI_BIST_DATA_CHECK                            0x00000433U
-#define _reg_PI_BIST_ADDR_CHECK                            0x00000434U
-#define _reg_PI_BIST_START_ADDRESS_P0                      0x00000435U
-#define _reg_PI_BIST_START_ADDRESS_P1                      0x00000436U
-#define _reg_PI_BIST_DATA_MASK_P0                          0x00000437U
-#define _reg_PI_BIST_DATA_MASK_P1                          0x00000438U
-#define _reg_PI_BIST_ERR_COUNT                             0x00000439U
-#define _reg_PI_BIST_ERR_STOP                              0x0000043aU
-#define _reg_PI_BIST_ADDR_MASK_0_P0                        0x0000043bU
-#define _reg_PI_BIST_ADDR_MASK_0_P1                        0x0000043cU
-#define _reg_PI_BIST_ADDR_MASK_1_P0                        0x0000043dU
-#define _reg_PI_BIST_ADDR_MASK_1_P1                        0x0000043eU
-#define _reg_PI_BIST_ADDR_MASK_2_P0                        0x0000043fU
-#define _reg_PI_BIST_ADDR_MASK_2_P1                        0x00000440U
-#define _reg_PI_BIST_ADDR_MASK_3_P0                        0x00000441U
-#define _reg_PI_BIST_ADDR_MASK_3_P1                        0x00000442U
-#define _reg_PI_BIST_ADDR_MASK_4_P0                        0x00000443U
-#define _reg_PI_BIST_ADDR_MASK_4_P1                        0x00000444U
-#define _reg_PI_BIST_ADDR_MASK_5_P0                        0x00000445U
-#define _reg_PI_BIST_ADDR_MASK_5_P1                        0x00000446U
-#define _reg_PI_BIST_ADDR_MASK_6_P0                        0x00000447U
-#define _reg_PI_BIST_ADDR_MASK_6_P1                        0x00000448U
-#define _reg_PI_BIST_ADDR_MASK_7_P0                        0x00000449U
-#define _reg_PI_BIST_ADDR_MASK_7_P1                        0x0000044aU
-#define _reg_PI_BIST_ADDR_MASK_8_P0                        0x0000044bU
-#define _reg_PI_BIST_ADDR_MASK_8_P1                        0x0000044cU
-#define _reg_PI_BIST_ADDR_MASK_9_P0                        0x0000044dU
-#define _reg_PI_BIST_ADDR_MASK_9_P1                        0x0000044eU
-#define _reg_PI_BIST_MODE                                  0x0000044fU
-#define _reg_PI_BIST_ADDR_MODE                             0x00000450U
-#define _reg_PI_BIST_PAT_MODE                              0x00000451U
-#define _reg_PI_BIST_USER_PAT_P0                           0x00000452U
-#define _reg_PI_BIST_USER_PAT_P1                           0x00000453U
-#define _reg_PI_BIST_USER_PAT_P2                           0x00000454U
-#define _reg_PI_BIST_USER_PAT_P3                           0x00000455U
-#define _reg_PI_BIST_PAT_NUM                               0x00000456U
-#define _reg_PI_BIST_STAGE_0                               0x00000457U
-#define _reg_PI_BIST_STAGE_1                               0x00000458U
-#define _reg_PI_BIST_STAGE_2                               0x00000459U
-#define _reg_PI_BIST_STAGE_3                               0x0000045aU
-#define _reg_PI_BIST_STAGE_4                               0x0000045bU
-#define _reg_PI_BIST_STAGE_5                               0x0000045cU
-#define _reg_PI_BIST_STAGE_6                               0x0000045dU
-#define _reg_PI_BIST_STAGE_7                               0x0000045eU
-#define _reg_PI_COL_DIFF                                   0x0000045fU
-#define _reg_PI_SELF_REFRESH_EN                            0x00000460U
-#define _reg_PI_TXSR_F0                                    0x00000461U
-#define _reg_PI_TXSR_F1                                    0x00000462U
-#define _reg_PI_TXSR_F2                                    0x00000463U
-#define _reg_PI_MONITOR_SRC_SEL_0                          0x00000464U
-#define _reg_PI_MONITOR_CAP_SEL_0                          0x00000465U
-#define _reg_PI_MONITOR_0                                  0x00000466U
-#define _reg_PI_MONITOR_SRC_SEL_1                          0x00000467U
-#define _reg_PI_MONITOR_CAP_SEL_1                          0x00000468U
-#define _reg_PI_MONITOR_1                                  0x00000469U
-#define _reg_PI_MONITOR_SRC_SEL_2                          0x0000046aU
-#define _reg_PI_MONITOR_CAP_SEL_2                          0x0000046bU
-#define _reg_PI_MONITOR_2                                  0x0000046cU
-#define _reg_PI_MONITOR_SRC_SEL_3                          0x0000046dU
-#define _reg_PI_MONITOR_CAP_SEL_3                          0x0000046eU
-#define _reg_PI_MONITOR_3                                  0x0000046fU
-#define _reg_PI_MONITOR_SRC_SEL_4                          0x00000470U
-#define _reg_PI_MONITOR_CAP_SEL_4                          0x00000471U
-#define _reg_PI_MONITOR_4                                  0x00000472U
-#define _reg_PI_MONITOR_SRC_SEL_5                          0x00000473U
-#define _reg_PI_MONITOR_CAP_SEL_5                          0x00000474U
-#define _reg_PI_MONITOR_5                                  0x00000475U
-#define _reg_PI_MONITOR_SRC_SEL_6                          0x00000476U
-#define _reg_PI_MONITOR_CAP_SEL_6                          0x00000477U
-#define _reg_PI_MONITOR_6                                  0x00000478U
-#define _reg_PI_MONITOR_SRC_SEL_7                          0x00000479U
-#define _reg_PI_MONITOR_CAP_SEL_7                          0x0000047aU
-#define _reg_PI_MONITOR_7                                  0x0000047bU
-#define _reg_PI_MONITOR_STROBE                             0x0000047cU
-#define _reg_PI_DLL_LOCK                                   0x0000047dU
-#define _reg_PI_FREQ_NUMBER_STATUS                         0x0000047eU
-#define _reg_RESERVED_R24                                  0x0000047fU
-#define _reg_PI_PHYMSTR_TYPE                               0x00000480U
-#define _reg_PI_POWER_REDUC_EN                             0x00000481U
-#define _reg_RESERVED_R25                                  0x00000482U
-#define _reg_RESERVED_R26                                  0x00000483U
-#define _reg_RESERVED_R27                                  0x00000484U
-#define _reg_RESERVED_R28                                  0x00000485U
-#define _reg_RESERVED_R29                                  0x00000486U
-#define _reg_RESERVED_R30                                  0x00000487U
-#define _reg_RESERVED_R31                                  0x00000488U
-#define _reg_RESERVED_R32                                  0x00000489U
-#define _reg_RESERVED_R33                                  0x0000048aU
-#define _reg_RESERVED_R34                                  0x0000048bU
-#define _reg_RESERVED_R35                                  0x0000048cU
-#define _reg_RESERVED_R36                                  0x0000048dU
-#define _reg_RESERVED_R37                                  0x0000048eU
-#define _reg_RESERVED_R38                                  0x0000048fU
-#define _reg_RESERVED_R39                                  0x00000490U
-#define _reg_PI_WRLVL_MAX_STROBE_PEND                      0x00000491U
-#define _reg_PI_TSDO_F0                                    0x00000492U
-#define _reg_PI_TSDO_F1                                    0x00000493U
-#define _reg_PI_TSDO_F2                                    0x00000494U
-
-#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xffffU)
-#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xffU)
-#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xffU)
-
-static const uint32_t DDR_REGDEF_TBL[4][1173] = {
-	{
-/*0000*/ 0xffffffffU,
-/*0001*/ 0xffffffffU,
-/*0002*/ 0x000b0400U,
-/*0003*/ 0xffffffffU,
-/*0004*/ 0xffffffffU,
-/*0005*/ 0x10010400U,
-/*0006*/ 0x18050400U,
-/*0007*/ 0x00050401U,
-/*0008*/ 0x08050401U,
-/*0009*/ 0x10050401U,
-/*000a*/ 0x18050401U,
-/*000b*/ 0x00050402U,
-/*000c*/ 0x08050402U,
-/*000d*/ 0x10050402U,
-/*000e*/ 0x18050402U,
-/*000f*/ 0x00040403U,
-/*0010*/ 0x08030403U,
-/*0011*/ 0x00180404U,
-/*0012*/ 0x18030404U,
-/*0013*/ 0x00180405U,
-/*0014*/ 0x18020405U,
-/*0015*/ 0x00010406U,
-/*0016*/ 0x08020406U,
-/*0017*/ 0x10010406U,
-/*0018*/ 0x18010406U,
-/*0019*/ 0x00020407U,
-/*001a*/ 0x08040407U,
-/*001b*/ 0x10040407U,
-/*001c*/ 0x18040407U,
-/*001d*/ 0x000a0408U,
-/*001e*/ 0x10040408U,
-/*001f*/ 0xffffffffU,
-/*0020*/ 0xffffffffU,
-/*0021*/ 0x18070408U,
-/*0022*/ 0xffffffffU,
-/*0023*/ 0xffffffffU,
-/*0024*/ 0xffffffffU,
-/*0025*/ 0xffffffffU,
-/*0026*/ 0xffffffffU,
-/*0027*/ 0xffffffffU,
-/*0028*/ 0x000a0409U,
-/*0029*/ 0x10040409U,
-/*002a*/ 0x18010409U,
-/*002b*/ 0x0001040aU,
-/*002c*/ 0x0802040aU,
-/*002d*/ 0x1009040aU,
-/*002e*/ 0x0009040bU,
-/*002f*/ 0x1002040bU,
-/*0030*/ 0x0020040cU,
-/*0031*/ 0xffffffffU,
-/*0032*/ 0x0001040dU,
-/*0033*/ 0xffffffffU,
-/*0034*/ 0xffffffffU,
-/*0035*/ 0xffffffffU,
-/*0036*/ 0xffffffffU,
-/*0037*/ 0x0020040eU,
-/*0038*/ 0x0020040fU,
-/*0039*/ 0x00200410U,
-/*003a*/ 0x00200411U,
-/*003b*/ 0x00030412U,
-/*003c*/ 0x08010412U,
-/*003d*/ 0x10030412U,
-/*003e*/ 0x18030412U,
-/*003f*/ 0x00040413U,
-/*0040*/ 0x08040413U,
-/*0041*/ 0x10040413U,
-/*0042*/ 0x18040413U,
-/*0043*/ 0x00010414U,
-/*0044*/ 0x08010414U,
-/*0045*/ 0x10060414U,
-/*0046*/ 0x18040414U,
-/*0047*/ 0xffffffffU,
-/*0048*/ 0x00060415U,
-/*0049*/ 0x08040415U,
-/*004a*/ 0x10060415U,
-/*004b*/ 0x18040415U,
-/*004c*/ 0x00020416U,
-/*004d*/ 0x08050416U,
-/*004e*/ 0x10080416U,
-/*004f*/ 0x00200417U,
-/*0050*/ 0x00060418U,
-/*0051*/ 0x08030418U,
-/*0052*/ 0x100b0418U,
-/*0053*/ 0x00040419U,
-/*0054*/ 0x08040419U,
-/*0055*/ 0x10040419U,
-/*0056*/ 0xffffffffU,
-/*0057*/ 0x18010419U,
-/*0058*/ 0x0009041aU,
-/*0059*/ 0x0020041bU,
-/*005a*/ 0x0020041cU,
-/*005b*/ 0x0020041dU,
-/*005c*/ 0x0020041eU,
-/*005d*/ 0x0010041fU,
-/*005e*/ 0x00200420U,
-/*005f*/ 0x00010421U,
-/*0060*/ 0x08060421U,
-/*0061*/ 0x10080421U,
-/*0062*/ 0x00200422U,
-/*0063*/ 0xffffffffU,
-/*0064*/ 0x000a0423U,
-/*0065*/ 0x10060423U,
-/*0066*/ 0x18070423U,
-/*0067*/ 0x00080424U,
-/*0068*/ 0x08080424U,
-/*0069*/ 0x100a0424U,
-/*006a*/ 0x00070425U,
-/*006b*/ 0x08080425U,
-/*006c*/ 0x10080425U,
-/*006d*/ 0x18030425U,
-/*006e*/ 0x000a0426U,
-/*006f*/ 0x100a0426U,
-/*0070*/ 0x00110427U,
-/*0071*/ 0x00090428U,
-/*0072*/ 0x10090428U,
-/*0073*/ 0x00100429U,
-/*0074*/ 0x100e0429U,
-/*0075*/ 0x000e042aU,
-/*0076*/ 0x100c042aU,
-/*0077*/ 0x000a042bU,
-/*0078*/ 0x100a042bU,
-/*0079*/ 0x0002042cU,
-/*007a*/ 0x0020042dU,
-/*007b*/ 0x000b042eU,
-/*007c*/ 0x100b042eU,
-/*007d*/ 0x0020042fU,
-/*007e*/ 0x00120430U,
-/*007f*/ 0x00200431U,
-/*0080*/ 0x00200432U,
-/*0081*/ 0xffffffffU,
-/*0082*/ 0xffffffffU,
-/*0083*/ 0x00010433U,
-/*0084*/ 0x08010433U,
-/*0085*/ 0x10080433U,
-/*0086*/ 0x000c0434U,
-/*0087*/ 0x100c0434U,
-/*0088*/ 0x000c0435U,
-/*0089*/ 0x100c0435U,
-/*008a*/ 0x000c0436U,
-/*008b*/ 0x100c0436U,
-/*008c*/ 0x000c0437U,
-/*008d*/ 0x100c0437U,
-/*008e*/ 0x000c0438U,
-/*008f*/ 0x100c0438U,
-/*0090*/ 0x000c0439U,
-/*0091*/ 0x100b0439U,
-/*0092*/ 0xffffffffU,
-/*0093*/ 0xffffffffU,
-/*0094*/ 0x000b043aU,
-/*0095*/ 0x100b043aU,
-/*0096*/ 0x000b043bU,
-/*0097*/ 0x100b043bU,
-/*0098*/ 0x000b043cU,
-/*0099*/ 0x100b043cU,
-/*009a*/ 0x000b043dU,
-/*009b*/ 0x100b043dU,
-/*009c*/ 0x000b043eU,
-/*009d*/ 0x100a043eU,
-/*009e*/ 0xffffffffU,
-/*009f*/ 0x000a043fU,
-/*00a0*/ 0x100a043fU,
-/*00a1*/ 0x000a0440U,
-/*00a2*/ 0x100a0440U,
-/*00a3*/ 0x000a0441U,
-/*00a4*/ 0x100a0441U,
-/*00a5*/ 0x000a0442U,
-/*00a6*/ 0x100a0442U,
-/*00a7*/ 0xffffffffU,
-/*00a8*/ 0x000a0443U,
-/*00a9*/ 0x100a0443U,
-/*00aa*/ 0x000a0444U,
-/*00ab*/ 0x100a0444U,
-/*00ac*/ 0x000a0445U,
-/*00ad*/ 0x100a0445U,
-/*00ae*/ 0x000a0446U,
-/*00af*/ 0x100a0446U,
-/*00b0*/ 0x000a0447U,
-/*00b1*/ 0x100a0447U,
-/*00b2*/ 0x000a0448U,
-/*00b3*/ 0x100a0448U,
-/*00b4*/ 0x000a0449U,
-/*00b5*/ 0x100a0449U,
-/*00b6*/ 0x000a044aU,
-/*00b7*/ 0x100a044aU,
-/*00b8*/ 0x000a044bU,
-/*00b9*/ 0x100a044bU,
-/*00ba*/ 0x000a044cU,
-/*00bb*/ 0x1004044cU,
-/*00bc*/ 0x1803044cU,
-/*00bd*/ 0x000a044dU,
-/*00be*/ 0x100a044dU,
-/*00bf*/ 0x0001044eU,
-/*00c0*/ 0x080a044eU,
-/*00c1*/ 0x1804044eU,
-/*00c2*/ 0x000b044fU,
-/*00c3*/ 0x100a044fU,
-/*00c4*/ 0xffffffffU,
-/*00c5*/ 0x00080450U,
-/*00c6*/ 0x08080450U,
-/*00c7*/ 0x10080450U,
-/*00c8*/ 0x18080450U,
-/*00c9*/ 0x00080451U,
-/*00ca*/ 0xffffffffU,
-/*00cb*/ 0x08080451U,
-/*00cc*/ 0x10010451U,
-/*00cd*/ 0x18080451U,
-/*00ce*/ 0x00080452U,
-/*00cf*/ 0x08020452U,
-/*00d0*/ 0x10020452U,
-/*00d1*/ 0x18040452U,
-/*00d2*/ 0x00040453U,
-/*00d3*/ 0xffffffffU,
-/*00d4*/ 0x08040453U,
-/*00d5*/ 0x100a0453U,
-/*00d6*/ 0x00060454U,
-/*00d7*/ 0x08080454U,
-/*00d8*/ 0xffffffffU,
-/*00d9*/ 0x10040454U,
-/*00da*/ 0x18040454U,
-/*00db*/ 0x00050455U,
-/*00dc*/ 0x08040455U,
-/*00dd*/ 0x10050455U,
-/*00de*/ 0x000a0456U,
-/*00df*/ 0x100a0456U,
-/*00e0*/ 0x00080457U,
-/*00e1*/ 0xffffffffU,
-/*00e2*/ 0x08040457U,
-/*00e3*/ 0xffffffffU,
-/*00e4*/ 0xffffffffU,
-/*00e5*/ 0x00050600U,
-/*00e6*/ 0x08050600U,
-/*00e7*/ 0x10050600U,
-/*00e8*/ 0x18050600U,
-/*00e9*/ 0x00050601U,
-/*00ea*/ 0x08050601U,
-/*00eb*/ 0x100b0601U,
-/*00ec*/ 0x00010602U,
-/*00ed*/ 0x08030602U,
-/*00ee*/ 0x00200603U,
-/*00ef*/ 0xffffffffU,
-/*00f0*/ 0x00030604U,
-/*00f1*/ 0x080a0604U,
-/*00f2*/ 0xffffffffU,
-/*00f3*/ 0xffffffffU,
-/*00f4*/ 0x18030604U,
-/*00f5*/ 0x00030605U,
-/*00f6*/ 0x08010605U,
-/*00f7*/ 0x10010605U,
-/*00f8*/ 0x18060605U,
-/*00f9*/ 0xffffffffU,
-/*00fa*/ 0xffffffffU,
-/*00fb*/ 0xffffffffU,
-/*00fc*/ 0x00020606U,
-/*00fd*/ 0x08030606U,
-/*00fe*/ 0x10010606U,
-/*00ff*/ 0x000f0607U,
-/*0100*/ 0x00200608U,
-/*0101*/ 0x00200609U,
-/*0102*/ 0x000b060aU,
-/*0103*/ 0x100b060aU,
-/*0104*/ 0x000b060bU,
-/*0105*/ 0xffffffffU,
-/*0106*/ 0xffffffffU,
-/*0107*/ 0x0018060cU,
-/*0108*/ 0x0018060dU,
-/*0109*/ 0x0018060eU,
-/*010a*/ 0x0018060fU,
-/*010b*/ 0x1804060fU,
-/*010c*/ 0x00050610U,
-/*010d*/ 0x08020610U,
-/*010e*/ 0x10040610U,
-/*010f*/ 0x18040610U,
-/*0110*/ 0x00010611U,
-/*0111*/ 0x08010611U,
-/*0112*/ 0x10010611U,
-/*0113*/ 0x18030611U,
-/*0114*/ 0x00200612U,
-/*0115*/ 0x00200613U,
-/*0116*/ 0x00010614U,
-/*0117*/ 0x08140614U,
-/*0118*/ 0x00140615U,
-/*0119*/ 0x00140616U,
-/*011a*/ 0x00140617U,
-/*011b*/ 0x00140618U,
-/*011c*/ 0x00140619U,
-/*011d*/ 0x0014061aU,
-/*011e*/ 0x0014061bU,
-/*011f*/ 0x0018061cU,
-/*0120*/ 0x000a061dU,
-/*0121*/ 0x1006061dU,
-/*0122*/ 0x1806061dU,
-/*0123*/ 0x0006061eU,
-/*0124*/ 0xffffffffU,
-/*0125*/ 0xffffffffU,
-/*0126*/ 0x0008061fU,
-/*0127*/ 0x080b061fU,
-/*0128*/ 0x000b0620U,
-/*0129*/ 0x100b0620U,
-/*012a*/ 0x000b0621U,
-/*012b*/ 0x100b0621U,
-/*012c*/ 0x000b0622U,
-/*012d*/ 0x10040622U,
-/*012e*/ 0x000a0623U,
-/*012f*/ 0x10060623U,
-/*0130*/ 0x18080623U,
-/*0131*/ 0xffffffffU,
-/*0132*/ 0x00040624U,
-/*0133*/ 0xffffffffU,
-/*0134*/ 0xffffffffU,
-/*0135*/ 0x00010700U,
-/*0136*/ 0x08020700U,
-/*0137*/ 0x10050700U,
-/*0138*/ 0x18050700U,
-/*0139*/ 0x00050701U,
-/*013a*/ 0x08050701U,
-/*013b*/ 0x100b0701U,
-/*013c*/ 0x00050702U,
-/*013d*/ 0x08010702U,
-/*013e*/ 0x10010702U,
-/*013f*/ 0xffffffffU,
-/*0140*/ 0x18010702U,
-/*0141*/ 0x00010703U,
-/*0142*/ 0x08040703U,
-/*0143*/ 0x100b0703U,
-/*0144*/ 0x000b0704U,
-/*0145*/ 0xffffffffU,
-/*0146*/ 0x10040704U,
-/*0147*/ 0x000b0705U,
-/*0148*/ 0x10040705U,
-/*0149*/ 0x18010705U,
-/*014a*/ 0x00010706U,
-/*014b*/ 0x08010706U,
-/*014c*/ 0x00200707U,
-/*014d*/ 0x00200708U,
-/*014e*/ 0x00080709U,
-/*014f*/ 0x080a0709U,
-/*0150*/ 0x18050709U,
-/*0151*/ 0x000a070aU,
-/*0152*/ 0x1003070aU,
-/*0153*/ 0x1803070aU,
-/*0154*/ 0x0001070bU,
-/*0155*/ 0x0802070bU,
-/*0156*/ 0x1001070bU,
-/*0157*/ 0x1801070bU,
-/*0158*/ 0x0001070cU,
-/*0159*/ 0x0802070cU,
-/*015a*/ 0xffffffffU,
-/*015b*/ 0xffffffffU,
-/*015c*/ 0xffffffffU,
-/*015d*/ 0xffffffffU,
-/*015e*/ 0xffffffffU,
-/*015f*/ 0xffffffffU,
-/*0160*/ 0xffffffffU,
-/*0161*/ 0xffffffffU,
-/*0162*/ 0xffffffffU,
-/*0163*/ 0xffffffffU,
-/*0164*/ 0xffffffffU,
-/*0165*/ 0xffffffffU,
-/*0166*/ 0x1001070cU,
-/*0167*/ 0x1801070cU,
-/*0168*/ 0x000d070dU,
-/*0169*/ 0xffffffffU,
-/*016a*/ 0xffffffffU,
-/*016b*/ 0x0005070eU,
-/*016c*/ 0x0001070fU,
-/*016d*/ 0x080e070fU,
-/*016e*/ 0x000e0710U,
-/*016f*/ 0x100e0710U,
-/*0170*/ 0x000e0711U,
-/*0171*/ 0x100e0711U,
-/*0172*/ 0x00040712U,
-/*0173*/ 0xffffffffU,
-/*0174*/ 0xffffffffU,
-/*0175*/ 0xffffffffU,
-/*0176*/ 0xffffffffU,
-/*0177*/ 0x080b0712U,
-/*0178*/ 0x000b0713U,
-/*0179*/ 0x100b0713U,
-/*017a*/ 0x000b0714U,
-/*017b*/ 0xffffffffU,
-/*017c*/ 0xffffffffU,
-/*017d*/ 0xffffffffU,
-/*017e*/ 0xffffffffU,
-/*017f*/ 0x000d0715U,
-/*0180*/ 0xffffffffU,
-/*0181*/ 0xffffffffU,
-/*0182*/ 0x10100715U,
-/*0183*/ 0x00080716U,
-/*0184*/ 0xffffffffU,
-/*0185*/ 0x08100716U,
-/*0186*/ 0x00100717U,
-/*0187*/ 0x10100717U,
-/*0188*/ 0x00100718U,
-/*0189*/ 0x10100718U,
-/*018a*/ 0x00030719U,
-/*018b*/ 0x08040719U,
-/*018c*/ 0x10010719U,
-/*018d*/ 0x18040719U,
-/*018e*/ 0xffffffffU,
-/*018f*/ 0xffffffffU,
-/*0190*/ 0x0001071aU,
-/*0191*/ 0x0812071aU,
-/*0192*/ 0x000a071bU,
-/*0193*/ 0x100c071bU,
-/*0194*/ 0x0012071cU,
-/*0195*/ 0x0014071dU,
-/*0196*/ 0x0012071eU,
-/*0197*/ 0x0011071fU,
-/*0198*/ 0x00110720U,
-/*0199*/ 0x00120721U,
-/*019a*/ 0x00120722U,
-/*019b*/ 0x00120723U,
-/*019c*/ 0x00120724U,
-/*019d*/ 0x00120725U,
-/*019e*/ 0x00120726U,
-/*019f*/ 0x00120727U,
-/*01a0*/ 0x00120728U,
-/*01a1*/ 0xffffffffU,
-/*01a2*/ 0xffffffffU,
-/*01a3*/ 0x00190729U,
-/*01a4*/ 0x0019072aU,
-/*01a5*/ 0x0020072bU,
-/*01a6*/ 0x0017072cU,
-/*01a7*/ 0x1808072cU,
-/*01a8*/ 0x0001072dU,
-/*01a9*/ 0x0801072dU,
-/*01aa*/ 0x0020072eU,
-/*01ab*/ 0x0008072fU,
-/*01ac*/ 0xffffffffU,
-/*01ad*/ 0x0803072fU,
-/*01ae*/ 0x00180730U,
-/*01af*/ 0x00180731U,
-/*01b0*/ 0xffffffffU,
-/*01b1*/ 0xffffffffU,
-/*01b2*/ 0xffffffffU,
-/*01b3*/ 0xffffffffU,
-/*01b4*/ 0xffffffffU,
-/*01b5*/ 0xffffffffU,
-/*01b6*/ 0xffffffffU,
-/*01b7*/ 0xffffffffU,
-/*01b8*/ 0xffffffffU,
-/*01b9*/ 0xffffffffU,
-/*01ba*/ 0xffffffffU,
-/*01bb*/ 0xffffffffU,
-/*01bc*/ 0xffffffffU,
-/*01bd*/ 0xffffffffU,
-/*01be*/ 0xffffffffU,
-/*01bf*/ 0x00100732U,
-/*01c0*/ 0x10010732U,
-/*01c1*/ 0x18010732U,
-/*01c2*/ 0x00050733U,
-/*01c3*/ 0x00200734U,
-/*01c4*/ 0x00090735U,
-/*01c5*/ 0xffffffffU,
-/*01c6*/ 0xffffffffU,
-/*01c7*/ 0x00200736U,
-/*01c8*/ 0x00040737U,
-/*01c9*/ 0x08100737U,
-/*01ca*/ 0x18060737U,
-/*01cb*/ 0x00100738U,
-/*01cc*/ 0xffffffffU,
-/*01cd*/ 0xffffffffU,
-/*01ce*/ 0xffffffffU,
-/*01cf*/ 0xffffffffU,
-/*01d0*/ 0xffffffffU,
-/*01d1*/ 0xffffffffU,
-/*01d2*/ 0xffffffffU,
-/*01d3*/ 0xffffffffU,
-/*01d4*/ 0x00200739U,
-/*01d5*/ 0x000b073aU,
-/*01d6*/ 0xffffffffU,
-/*01d7*/ 0xffffffffU,
-/*01d8*/ 0xffffffffU,
-/*01d9*/ 0xffffffffU,
-/*01da*/ 0xffffffffU,
-/*01db*/ 0xffffffffU,
-/*01dc*/ 0xffffffffU,
-/*01dd*/ 0xffffffffU,
-/*01de*/ 0x00010200U,
-/*01df*/ 0x08040200U,
-/*01e0*/ 0x10100200U,
-/*01e1*/ 0x00010201U,
-/*01e2*/ 0x08010201U,
-/*01e3*/ 0xffffffffU,
-/*01e4*/ 0xffffffffU,
-/*01e5*/ 0x10100201U,
-/*01e6*/ 0xffffffffU,
-/*01e7*/ 0xffffffffU,
-/*01e8*/ 0xffffffffU,
-/*01e9*/ 0xffffffffU,
-/*01ea*/ 0xffffffffU,
-/*01eb*/ 0xffffffffU,
-/*01ec*/ 0xffffffffU,
-/*01ed*/ 0xffffffffU,
-/*01ee*/ 0xffffffffU,
-/*01ef*/ 0x00200202U,
-/*01f0*/ 0x00100203U,
-/*01f1*/ 0x00200204U,
-/*01f2*/ 0x00100205U,
-/*01f3*/ 0x00200206U,
-/*01f4*/ 0x00100207U,
-/*01f5*/ 0x10100207U,
-/*01f6*/ 0x00200208U,
-/*01f7*/ 0x00200209U,
-/*01f8*/ 0x0020020aU,
-/*01f9*/ 0x0020020bU,
-/*01fa*/ 0x0010020cU,
-/*01fb*/ 0x0020020dU,
-/*01fc*/ 0x0020020eU,
-/*01fd*/ 0x0020020fU,
-/*01fe*/ 0x00200210U,
-/*01ff*/ 0x00100211U,
-/*0200*/ 0x00200212U,
-/*0201*/ 0x00200213U,
-/*0202*/ 0x00200214U,
-/*0203*/ 0x00200215U,
-/*0204*/ 0x00090216U,
-/*0205*/ 0x10010216U,
-/*0206*/ 0x00200217U,
-/*0207*/ 0x00050218U,
-/*0208*/ 0x08010218U,
-/*0209*/ 0x10080218U,
-/*020a*/ 0x18080218U,
-/*020b*/ 0x001c0219U,
-/*020c*/ 0x001c021aU,
-/*020d*/ 0x001c021bU,
-/*020e*/ 0x001c021cU,
-/*020f*/ 0x001c021dU,
-/*0210*/ 0x001c021eU,
-/*0211*/ 0x001c021fU,
-/*0212*/ 0x001c0220U,
-/*0213*/ 0x001c0221U,
-/*0214*/ 0x001c0222U,
-/*0215*/ 0x001c0223U,
-/*0216*/ 0x001c0224U,
-/*0217*/ 0x001c0225U,
-/*0218*/ 0x001c0226U,
-/*0219*/ 0x001c0227U,
-/*021a*/ 0x001c0228U,
-/*021b*/ 0x00010229U,
-/*021c*/ 0x08010229U,
-/*021d*/ 0x10010229U,
-/*021e*/ 0x18040229U,
-/*021f*/ 0x0008022aU,
-/*0220*/ 0x0808022aU,
-/*0221*/ 0x1008022aU,
-/*0222*/ 0x1804022aU,
-/*0223*/ 0x0006022bU,
-/*0224*/ 0xffffffffU,
-/*0225*/ 0x0807022bU,
-/*0226*/ 0x1006022bU,
-/*0227*/ 0xffffffffU,
-/*0228*/ 0x1807022bU,
-/*0229*/ 0x0006022cU,
-/*022a*/ 0xffffffffU,
-/*022b*/ 0x0807022cU,
-/*022c*/ 0x1002022cU,
-/*022d*/ 0x1801022cU,
-/*022e*/ 0xffffffffU,
-/*022f*/ 0x000a022dU,
-/*0230*/ 0x1010022dU,
-/*0231*/ 0x000a022eU,
-/*0232*/ 0x1010022eU,
-/*0233*/ 0x000a022fU,
-/*0234*/ 0x1010022fU,
-/*0235*/ 0xffffffffU,
-/*0236*/ 0x00100230U,
-/*0237*/ 0xffffffffU,
-/*0238*/ 0xffffffffU,
-/*0239*/ 0x10010230U,
-/*023a*/ 0x18010230U,
-/*023b*/ 0x00010231U,
-/*023c*/ 0x08010231U,
-/*023d*/ 0x10010231U,
-/*023e*/ 0x18010231U,
-/*023f*/ 0x00020232U,
-/*0240*/ 0x08020232U,
-/*0241*/ 0x10020232U,
-/*0242*/ 0x18020232U,
-/*0243*/ 0x00020233U,
-/*0244*/ 0x08030233U,
-/*0245*/ 0x10010233U,
-/*0246*/ 0x18010233U,
-/*0247*/ 0x00010234U,
-/*0248*/ 0x08010234U,
-/*0249*/ 0xffffffffU,
-/*024a*/ 0x10020234U,
-/*024b*/ 0x18010234U,
-/*024c*/ 0x00010235U,
-/*024d*/ 0xffffffffU,
-/*024e*/ 0x08020235U,
-/*024f*/ 0x10010235U,
-/*0250*/ 0x18010235U,
-/*0251*/ 0xffffffffU,
-/*0252*/ 0x00020236U,
-/*0253*/ 0x08010236U,
-/*0254*/ 0x10010236U,
-/*0255*/ 0xffffffffU,
-/*0256*/ 0x18020236U,
-/*0257*/ 0x00070237U,
-/*0258*/ 0x08010237U,
-/*0259*/ 0x10010237U,
-/*025a*/ 0x18010237U,
-/*025b*/ 0x00010238U,
-/*025c*/ 0x08010238U,
-/*025d*/ 0x10010238U,
-/*025e*/ 0xffffffffU,
-/*025f*/ 0x18010238U,
-/*0260*/ 0x00040239U,
-/*0261*/ 0x08040239U,
-/*0262*/ 0x10040239U,
-/*0263*/ 0x18010239U,
-/*0264*/ 0x0002023aU,
-/*0265*/ 0x0806023aU,
-/*0266*/ 0x1006023aU,
-/*0267*/ 0xffffffffU,
-/*0268*/ 0xffffffffU,
-/*0269*/ 0xffffffffU,
-/*026a*/ 0x1802023aU,
-/*026b*/ 0x0010023bU,
-/*026c*/ 0x1001023bU,
-/*026d*/ 0x1801023bU,
-/*026e*/ 0xffffffffU,
-/*026f*/ 0x0004023cU,
-/*0270*/ 0x0801023cU,
-/*0271*/ 0x1004023cU,
-/*0272*/ 0x1802023cU,
-/*0273*/ 0x0008023dU,
-/*0274*/ 0xffffffffU,
-/*0275*/ 0xffffffffU,
-/*0276*/ 0xffffffffU,
-/*0277*/ 0x080a023dU,
-/*0278*/ 0x0020023eU,
-/*0279*/ 0x0020023fU,
-/*027a*/ 0x00050240U,
-/*027b*/ 0x08010240U,
-/*027c*/ 0x10050240U,
-/*027d*/ 0x18080240U,
-/*027e*/ 0x00010241U,
-/*027f*/ 0x08080241U,
-/*0280*/ 0x10010241U,
-/*0281*/ 0x18080241U,
-/*0282*/ 0x00010242U,
-/*0283*/ 0x08040242U,
-/*0284*/ 0x10040242U,
-/*0285*/ 0x18040242U,
-/*0286*/ 0x00040243U,
-/*0287*/ 0x08040243U,
-/*0288*/ 0x10040243U,
-/*0289*/ 0x18040243U,
-/*028a*/ 0x00040244U,
-/*028b*/ 0x08040244U,
-/*028c*/ 0x10040244U,
-/*028d*/ 0x18010244U,
-/*028e*/ 0x00040245U,
-/*028f*/ 0x08040245U,
-/*0290*/ 0x10040245U,
-/*0291*/ 0x18040245U,
-/*0292*/ 0x00040246U,
-/*0293*/ 0x08040246U,
-/*0294*/ 0x10060246U,
-/*0295*/ 0x18060246U,
-/*0296*/ 0x00060247U,
-/*0297*/ 0x08060247U,
-/*0298*/ 0x10060247U,
-/*0299*/ 0x18060247U,
-/*029a*/ 0xffffffffU,
-/*029b*/ 0x00010248U,
-/*029c*/ 0x08010248U,
-/*029d*/ 0x10020248U,
-/*029e*/ 0xffffffffU,
-/*029f*/ 0xffffffffU,
-/*02a0*/ 0xffffffffU,
-/*02a1*/ 0xffffffffU,
-/*02a2*/ 0xffffffffU,
-/*02a3*/ 0xffffffffU,
-/*02a4*/ 0xffffffffU,
-/*02a5*/ 0xffffffffU,
-/*02a6*/ 0x18040248U,
-/*02a7*/ 0x00040249U,
-/*02a8*/ 0x08010249U,
-/*02a9*/ 0x10010249U,
-/*02aa*/ 0xffffffffU,
-/*02ab*/ 0x18010249U,
-/*02ac*/ 0x0001024aU,
-/*02ad*/ 0xffffffffU,
-/*02ae*/ 0x0801024aU,
-/*02af*/ 0x1001024aU,
-/*02b0*/ 0x1801024aU,
-/*02b1*/ 0x0004024bU,
-/*02b2*/ 0x0804024bU,
-/*02b3*/ 0x100a024bU,
-/*02b4*/ 0x0020024cU,
-/*02b5*/ 0x0004024dU,
-/*02b6*/ 0x0808024dU,
-/*02b7*/ 0xffffffffU,
-/*02b8*/ 0xffffffffU,
-/*02b9*/ 0xffffffffU,
-/*02ba*/ 0xffffffffU,
-/*02bb*/ 0xffffffffU,
-/*02bc*/ 0xffffffffU,
-/*02bd*/ 0x1002024dU,
-/*02be*/ 0x1802024dU,
-/*02bf*/ 0x0020024eU,
-/*02c0*/ 0x0002024fU,
-/*02c1*/ 0x0810024fU,
-/*02c2*/ 0x00100250U,
-/*02c3*/ 0x10040250U,
-/*02c4*/ 0x18040250U,
-/*02c5*/ 0x00050251U,
-/*02c6*/ 0x08050251U,
-/*02c7*/ 0xffffffffU,
-/*02c8*/ 0xffffffffU,
-/*02c9*/ 0xffffffffU,
-/*02ca*/ 0xffffffffU,
-/*02cb*/ 0x10010251U,
-/*02cc*/ 0x18010251U,
-/*02cd*/ 0x00070252U,
-/*02ce*/ 0x08070252U,
-/*02cf*/ 0x10070252U,
-/*02d0*/ 0x18070252U,
-/*02d1*/ 0x00070253U,
-/*02d2*/ 0x08070253U,
-/*02d3*/ 0x10070253U,
-/*02d4*/ 0x18070253U,
-/*02d5*/ 0x00070254U,
-/*02d6*/ 0x08070254U,
-/*02d7*/ 0x10070254U,
-/*02d8*/ 0xffffffffU,
-/*02d9*/ 0xffffffffU,
-/*02da*/ 0xffffffffU,
-/*02db*/ 0xffffffffU,
-/*02dc*/ 0xffffffffU,
-/*02dd*/ 0xffffffffU,
-/*02de*/ 0x18030254U,
-/*02df*/ 0x00010255U,
-/*02e0*/ 0x08020255U,
-/*02e1*/ 0x10010255U,
-/*02e2*/ 0x18040255U,
-/*02e3*/ 0x00020256U,
-/*02e4*/ 0x08010256U,
-/*02e5*/ 0x10010256U,
-/*02e6*/ 0xffffffffU,
-/*02e7*/ 0x18010256U,
-/*02e8*/ 0x00040257U,
-/*02e9*/ 0x08080257U,
-/*02ea*/ 0x100a0257U,
-/*02eb*/ 0x000a0258U,
-/*02ec*/ 0x100a0258U,
-/*02ed*/ 0x000a0259U,
-/*02ee*/ 0x100a0259U,
-/*02ef*/ 0x000a025aU,
-/*02f0*/ 0x0020025bU,
-/*02f1*/ 0x0020025cU,
-/*02f2*/ 0x0001025dU,
-/*02f3*/ 0xffffffffU,
-/*02f4*/ 0xffffffffU,
-/*02f5*/ 0xffffffffU,
-/*02f6*/ 0x0802025dU,
-/*02f7*/ 0x1002025dU,
-/*02f8*/ 0x0010025eU,
-/*02f9*/ 0x1005025eU,
-/*02fa*/ 0x1806025eU,
-/*02fb*/ 0x0005025fU,
-/*02fc*/ 0x0805025fU,
-/*02fd*/ 0x100e025fU,
-/*02fe*/ 0x00050260U,
-/*02ff*/ 0x080e0260U,
-/*0300*/ 0x18050260U,
-/*0301*/ 0x000e0261U,
-/*0302*/ 0x10050261U,
-/*0303*/ 0x18010261U,
-/*0304*/ 0x00050262U,
-/*0305*/ 0x08050262U,
-/*0306*/ 0x100a0262U,
-/*0307*/ 0x000a0263U,
-/*0308*/ 0x10050263U,
-/*0309*/ 0x18050263U,
-/*030a*/ 0x000a0264U,
-/*030b*/ 0x100a0264U,
-/*030c*/ 0x00050265U,
-/*030d*/ 0x08050265U,
-/*030e*/ 0x100a0265U,
-/*030f*/ 0x000a0266U,
-/*0310*/ 0xffffffffU,
-/*0311*/ 0xffffffffU,
-/*0312*/ 0xffffffffU,
-/*0313*/ 0xffffffffU,
-/*0314*/ 0xffffffffU,
-/*0315*/ 0xffffffffU,
-/*0316*/ 0x10070266U,
-/*0317*/ 0x18070266U,
-/*0318*/ 0x00040267U,
-/*0319*/ 0x08040267U,
-/*031a*/ 0xffffffffU,
-/*031b*/ 0xffffffffU,
-/*031c*/ 0xffffffffU,
-/*031d*/ 0x10040267U,
-/*031e*/ 0x18080267U,
-/*031f*/ 0x00080268U,
-/*0320*/ 0x08040268U,
-/*0321*/ 0xffffffffU,
-/*0322*/ 0xffffffffU,
-/*0323*/ 0xffffffffU,
-/*0324*/ 0x10040268U,
-/*0325*/ 0xffffffffU,
-/*0326*/ 0xffffffffU,
-/*0327*/ 0xffffffffU,
-/*0328*/ 0x18040268U,
-/*0329*/ 0xffffffffU,
-/*032a*/ 0xffffffffU,
-/*032b*/ 0xffffffffU,
-/*032c*/ 0x00040269U,
-/*032d*/ 0x08050269U,
-/*032e*/ 0x10070269U,
-/*032f*/ 0x18080269U,
-/*0330*/ 0x0010026aU,
-/*0331*/ 0x1008026aU,
-/*0332*/ 0x0010026bU,
-/*0333*/ 0x1008026bU,
-/*0334*/ 0x0010026cU,
-/*0335*/ 0x1008026cU,
-/*0336*/ 0x1808026cU,
-/*0337*/ 0x0001026dU,
-/*0338*/ 0x0801026dU,
-/*0339*/ 0x1006026dU,
-/*033a*/ 0x1806026dU,
-/*033b*/ 0x0006026eU,
-/*033c*/ 0xffffffffU,
-/*033d*/ 0x0801026eU,
-/*033e*/ 0x1003026eU,
-/*033f*/ 0xffffffffU,
-/*0340*/ 0xffffffffU,
-/*0341*/ 0xffffffffU,
-/*0342*/ 0x000a026fU,
-/*0343*/ 0x100a026fU,
-/*0344*/ 0x00040270U,
-/*0345*/ 0x08010270U,
-/*0346*/ 0x10040270U,
-/*0347*/ 0xffffffffU,
-/*0348*/ 0xffffffffU,
-/*0349*/ 0xffffffffU,
-/*034a*/ 0xffffffffU,
-/*034b*/ 0xffffffffU,
-/*034c*/ 0xffffffffU,
-/*034d*/ 0x18070270U,
-/*034e*/ 0x00070271U,
-/*034f*/ 0x08050271U,
-/*0350*/ 0x10050271U,
-/*0351*/ 0xffffffffU,
-/*0352*/ 0xffffffffU,
-/*0353*/ 0xffffffffU,
-/*0354*/ 0x18040271U,
-/*0355*/ 0x00010272U,
-/*0356*/ 0x08010272U,
-/*0357*/ 0x10020272U,
-/*0358*/ 0x18080272U,
-/*0359*/ 0x00200273U,
-/*035a*/ 0x00200274U,
-/*035b*/ 0x00100275U,
-/*035c*/ 0xffffffffU,
-/*035d*/ 0xffffffffU,
-/*035e*/ 0xffffffffU,
-/*035f*/ 0x10020275U,
-/*0360*/ 0x18010275U,
-/*0361*/ 0xffffffffU,
-/*0362*/ 0x00020276U,
-/*0363*/ 0x08080276U,
-/*0364*/ 0x10080276U,
-/*0365*/ 0x18080276U,
-/*0366*/ 0x00080277U,
-/*0367*/ 0x08080277U,
-/*0368*/ 0x10080277U,
-/*0369*/ 0xffffffffU,
-/*036a*/ 0x18080277U,
-/*036b*/ 0x00080278U,
-/*036c*/ 0x08080278U,
-/*036d*/ 0x10080278U,
-/*036e*/ 0x18080278U,
-/*036f*/ 0x00080279U,
-/*0370*/ 0xffffffffU,
-/*0371*/ 0x08080279U,
-/*0372*/ 0x10080279U,
-/*0373*/ 0x18080279U,
-/*0374*/ 0x0008027aU,
-/*0375*/ 0x0808027aU,
-/*0376*/ 0x1008027aU,
-/*0377*/ 0xffffffffU,
-/*0378*/ 0x1808027aU,
-/*0379*/ 0x0008027bU,
-/*037a*/ 0x0808027bU,
-/*037b*/ 0x1008027bU,
-/*037c*/ 0x1808027bU,
-/*037d*/ 0x0008027cU,
-/*037e*/ 0x0808027cU,
-/*037f*/ 0xffffffffU,
-/*0380*/ 0x1008027cU,
-/*0381*/ 0x1808027cU,
-/*0382*/ 0x0008027dU,
-/*0383*/ 0x0808027dU,
-/*0384*/ 0x1008027dU,
-/*0385*/ 0x1808027dU,
-/*0386*/ 0xffffffffU,
-/*0387*/ 0x0008027eU,
-/*0388*/ 0x0808027eU,
-/*0389*/ 0x1008027eU,
-/*038a*/ 0x1808027eU,
-/*038b*/ 0x0008027fU,
-/*038c*/ 0x0808027fU,
-/*038d*/ 0xffffffffU,
-/*038e*/ 0x1008027fU,
-/*038f*/ 0x1808027fU,
-/*0390*/ 0x00080280U,
-/*0391*/ 0x08080280U,
-/*0392*/ 0x10080280U,
-/*0393*/ 0x18080280U,
-/*0394*/ 0x00080281U,
-/*0395*/ 0xffffffffU,
-/*0396*/ 0x08080281U,
-/*0397*/ 0x10080281U,
-/*0398*/ 0x18080281U,
-/*0399*/ 0x00080282U,
-/*039a*/ 0x08080282U,
-/*039b*/ 0x10080282U,
-/*039c*/ 0xffffffffU,
-/*039d*/ 0x18080282U,
-/*039e*/ 0x00080283U,
-/*039f*/ 0x08080283U,
-/*03a0*/ 0x10080283U,
-/*03a1*/ 0x18080283U,
-/*03a2*/ 0x00080284U,
-/*03a3*/ 0xffffffffU,
-/*03a4*/ 0x08080284U,
-/*03a5*/ 0x10080284U,
-/*03a6*/ 0x18080284U,
-/*03a7*/ 0x00080285U,
-/*03a8*/ 0x08080285U,
-/*03a9*/ 0x10080285U,
-/*03aa*/ 0x18080285U,
-/*03ab*/ 0xffffffffU,
-/*03ac*/ 0x00080286U,
-/*03ad*/ 0x08080286U,
-/*03ae*/ 0x10080286U,
-/*03af*/ 0x18080286U,
-/*03b0*/ 0x00080287U,
-/*03b1*/ 0x08080287U,
-/*03b2*/ 0xffffffffU,
-/*03b3*/ 0x10080287U,
-/*03b4*/ 0x18080287U,
-/*03b5*/ 0x00080288U,
-/*03b6*/ 0x08080288U,
-/*03b7*/ 0x10080288U,
-/*03b8*/ 0x18080288U,
-/*03b9*/ 0xffffffffU,
-/*03ba*/ 0x00080289U,
-/*03bb*/ 0x08020289U,
-/*03bc*/ 0x10030289U,
-/*03bd*/ 0x000a028aU,
-/*03be*/ 0x100a028aU,
-/*03bf*/ 0x000a028bU,
-/*03c0*/ 0x1005028bU,
-/*03c1*/ 0x1804028bU,
-/*03c2*/ 0x0008028cU,
-/*03c3*/ 0x0808028cU,
-/*03c4*/ 0x1006028cU,
-/*03c5*/ 0x1806028cU,
-/*03c6*/ 0x0011028dU,
-/*03c7*/ 0x1808028dU,
-/*03c8*/ 0x0004028eU,
-/*03c9*/ 0x0806028eU,
-/*03ca*/ 0xffffffffU,
-/*03cb*/ 0x1006028eU,
-/*03cc*/ 0x1808028eU,
-/*03cd*/ 0xffffffffU,
-/*03ce*/ 0x0004028fU,
-/*03cf*/ 0x0808028fU,
-/*03d0*/ 0x1008028fU,
-/*03d1*/ 0x1806028fU,
-/*03d2*/ 0x00060290U,
-/*03d3*/ 0x08110290U,
-/*03d4*/ 0x00080291U,
-/*03d5*/ 0x08040291U,
-/*03d6*/ 0x10060291U,
-/*03d7*/ 0xffffffffU,
-/*03d8*/ 0x18060291U,
-/*03d9*/ 0x00080292U,
-/*03da*/ 0xffffffffU,
-/*03db*/ 0x08040292U,
-/*03dc*/ 0x10080292U,
-/*03dd*/ 0x18080292U,
-/*03de*/ 0x00060293U,
-/*03df*/ 0x08060293U,
-/*03e0*/ 0x00110294U,
-/*03e1*/ 0x18080294U,
-/*03e2*/ 0x00040295U,
-/*03e3*/ 0x08060295U,
-/*03e4*/ 0xffffffffU,
-/*03e5*/ 0x10060295U,
-/*03e6*/ 0x18080295U,
-/*03e7*/ 0xffffffffU,
-/*03e8*/ 0x00040296U,
-/*03e9*/ 0x08040296U,
-/*03ea*/ 0x10040296U,
-/*03eb*/ 0x18040296U,
-/*03ec*/ 0x00040297U,
-/*03ed*/ 0x08040297U,
-/*03ee*/ 0x10040297U,
-/*03ef*/ 0x18040297U,
-/*03f0*/ 0x00040298U,
-/*03f1*/ 0x08040298U,
-/*03f2*/ 0x10040298U,
-/*03f3*/ 0x18040298U,
-/*03f4*/ 0x00040299U,
-/*03f5*/ 0x08040299U,
-/*03f6*/ 0x10040299U,
-/*03f7*/ 0x18040299U,
-/*03f8*/ 0x0004029aU,
-/*03f9*/ 0x0804029aU,
-/*03fa*/ 0x1004029aU,
-/*03fb*/ 0x1804029aU,
-/*03fc*/ 0x0011029bU,
-/*03fd*/ 0x0010029cU,
-/*03fe*/ 0x0011029dU,
-/*03ff*/ 0x0020029eU,
-/*0400*/ 0x0020029fU,
-/*0401*/ 0x002002a0U,
-/*0402*/ 0x002002a1U,
-/*0403*/ 0x002002a2U,
-/*0404*/ 0x002002a3U,
-/*0405*/ 0x002002a4U,
-/*0406*/ 0x002002a5U,
-/*0407*/ 0x002002a6U,
-/*0408*/ 0x000202a7U,
-/*0409*/ 0x080502a7U,
-/*040a*/ 0x100502a7U,
-/*040b*/ 0xffffffffU,
-/*040c*/ 0xffffffffU,
-/*040d*/ 0xffffffffU,
-/*040e*/ 0xffffffffU,
-/*040f*/ 0xffffffffU,
-/*0410*/ 0xffffffffU,
-/*0411*/ 0xffffffffU,
-/*0412*/ 0xffffffffU,
-/*0413*/ 0xffffffffU,
-/*0414*/ 0xffffffffU,
-/*0415*/ 0xffffffffU,
-/*0416*/ 0xffffffffU,
-/*0417*/ 0xffffffffU,
-/*0418*/ 0xffffffffU,
-/*0419*/ 0xffffffffU,
-/*041a*/ 0xffffffffU,
-/*041b*/ 0xffffffffU,
-/*041c*/ 0xffffffffU,
-/*041d*/ 0xffffffffU,
-/*041e*/ 0xffffffffU,
-/*041f*/ 0xffffffffU,
-/*0420*/ 0xffffffffU,
-/*0421*/ 0xffffffffU,
-/*0422*/ 0xffffffffU,
-/*0423*/ 0xffffffffU,
-/*0424*/ 0xffffffffU,
-/*0425*/ 0xffffffffU,
-/*0426*/ 0xffffffffU,
-/*0427*/ 0x180102a7U,
-/*0428*/ 0x000402a8U,
-/*0429*/ 0x081002a8U,
-/*042a*/ 0x002002a9U,
-/*042b*/ 0x001002aaU,
-/*042c*/ 0x002002abU,
-/*042d*/ 0x001002acU,
-/*042e*/ 0x002002adU,
-/*042f*/ 0x000702aeU,
-/*0430*/ 0x080102aeU,
-/*0431*/ 0x100202aeU,
-/*0432*/ 0x180602aeU,
-/*0433*/ 0x000102afU,
-/*0434*/ 0x080102afU,
-/*0435*/ 0x002002b0U,
-/*0436*/ 0x000202b1U,
-/*0437*/ 0x002002b2U,
-/*0438*/ 0x002002b3U,
-/*0439*/ 0xffffffffU,
-/*043a*/ 0xffffffffU,
-/*043b*/ 0xffffffffU,
-/*043c*/ 0xffffffffU,
-/*043d*/ 0xffffffffU,
-/*043e*/ 0xffffffffU,
-/*043f*/ 0xffffffffU,
-/*0440*/ 0xffffffffU,
-/*0441*/ 0xffffffffU,
-/*0442*/ 0xffffffffU,
-/*0443*/ 0xffffffffU,
-/*0444*/ 0xffffffffU,
-/*0445*/ 0xffffffffU,
-/*0446*/ 0xffffffffU,
-/*0447*/ 0xffffffffU,
-/*0448*/ 0xffffffffU,
-/*0449*/ 0xffffffffU,
-/*044a*/ 0xffffffffU,
-/*044b*/ 0xffffffffU,
-/*044c*/ 0xffffffffU,
-/*044d*/ 0xffffffffU,
-/*044e*/ 0xffffffffU,
-/*044f*/ 0xffffffffU,
-/*0450*/ 0xffffffffU,
-/*0451*/ 0xffffffffU,
-/*0452*/ 0xffffffffU,
-/*0453*/ 0xffffffffU,
-/*0454*/ 0xffffffffU,
-/*0455*/ 0xffffffffU,
-/*0456*/ 0xffffffffU,
-/*0457*/ 0xffffffffU,
-/*0458*/ 0xffffffffU,
-/*0459*/ 0xffffffffU,
-/*045a*/ 0xffffffffU,
-/*045b*/ 0xffffffffU,
-/*045c*/ 0xffffffffU,
-/*045d*/ 0xffffffffU,
-/*045e*/ 0xffffffffU,
-/*045f*/ 0x000402b4U,
-/*0460*/ 0xffffffffU,
-/*0461*/ 0xffffffffU,
-/*0462*/ 0xffffffffU,
-/*0463*/ 0xffffffffU,
-/*0464*/ 0xffffffffU,
-/*0465*/ 0xffffffffU,
-/*0466*/ 0xffffffffU,
-/*0467*/ 0xffffffffU,
-/*0468*/ 0xffffffffU,
-/*0469*/ 0xffffffffU,
-/*046a*/ 0xffffffffU,
-/*046b*/ 0xffffffffU,
-/*046c*/ 0xffffffffU,
-/*046d*/ 0xffffffffU,
-/*046e*/ 0xffffffffU,
-/*046f*/ 0xffffffffU,
-/*0470*/ 0xffffffffU,
-/*0471*/ 0xffffffffU,
-/*0472*/ 0xffffffffU,
-/*0473*/ 0xffffffffU,
-/*0474*/ 0xffffffffU,
-/*0475*/ 0xffffffffU,
-/*0476*/ 0xffffffffU,
-/*0477*/ 0xffffffffU,
-/*0478*/ 0xffffffffU,
-/*0479*/ 0xffffffffU,
-/*047a*/ 0xffffffffU,
-/*047b*/ 0xffffffffU,
-/*047c*/ 0xffffffffU,
-/*047d*/ 0xffffffffU,
-/*047e*/ 0xffffffffU,
-/*047f*/ 0xffffffffU,
-/*0480*/ 0xffffffffU,
-/*0481*/ 0xffffffffU,
-/*0482*/ 0xffffffffU,
-/*0483*/ 0xffffffffU,
-/*0484*/ 0xffffffffU,
-/*0485*/ 0xffffffffU,
-/*0486*/ 0xffffffffU,
-/*0487*/ 0xffffffffU,
-/*0488*/ 0xffffffffU,
-/*0489*/ 0xffffffffU,
-/*048a*/ 0xffffffffU,
-/*048b*/ 0xffffffffU,
-/*048c*/ 0xffffffffU,
-/*048d*/ 0xffffffffU,
-/*048e*/ 0xffffffffU,
-/*048f*/ 0xffffffffU,
-/*0490*/ 0xffffffffU,
-/*0491*/ 0xffffffffU,
-/*0492*/ 0xffffffffU,
-/*0493*/ 0xffffffffU,
-/*0494*/ 0xffffffffU,
-	 },
-	{
-/*0000*/ 0x00200800U,
-/*0001*/ 0x00040801U,
-/*0002*/ 0x080b0801U,
-/*0003*/ 0xffffffffU,
-/*0004*/ 0xffffffffU,
-/*0005*/ 0x18010801U,
-/*0006*/ 0x00050802U,
-/*0007*/ 0x08050802U,
-/*0008*/ 0x10050802U,
-/*0009*/ 0x18050802U,
-/*000a*/ 0x00050803U,
-/*000b*/ 0x08050803U,
-/*000c*/ 0x10050803U,
-/*000d*/ 0x18050803U,
-/*000e*/ 0x00050804U,
-/*000f*/ 0x08040804U,
-/*0010*/ 0x10030804U,
-/*0011*/ 0x00180805U,
-/*0012*/ 0x18030805U,
-/*0013*/ 0x00180806U,
-/*0014*/ 0x18020806U,
-/*0015*/ 0x00010807U,
-/*0016*/ 0x08020807U,
-/*0017*/ 0x10010807U,
-/*0018*/ 0x18010807U,
-/*0019*/ 0x00020808U,
-/*001a*/ 0x08040808U,
-/*001b*/ 0x10040808U,
-/*001c*/ 0x18040808U,
-/*001d*/ 0x000a0809U,
-/*001e*/ 0x10040809U,
-/*001f*/ 0xffffffffU,
-/*0020*/ 0xffffffffU,
-/*0021*/ 0x18070809U,
-/*0022*/ 0xffffffffU,
-/*0023*/ 0xffffffffU,
-/*0024*/ 0xffffffffU,
-/*0025*/ 0xffffffffU,
-/*0026*/ 0xffffffffU,
-/*0027*/ 0xffffffffU,
-/*0028*/ 0x000a080aU,
-/*0029*/ 0x1005080aU,
-/*002a*/ 0x1801080aU,
-/*002b*/ 0x0001080bU,
-/*002c*/ 0x0802080bU,
-/*002d*/ 0x1009080bU,
-/*002e*/ 0x0009080cU,
-/*002f*/ 0x1002080cU,
-/*0030*/ 0x0020080dU,
-/*0031*/ 0xffffffffU,
-/*0032*/ 0x0001080eU,
-/*0033*/ 0xffffffffU,
-/*0034*/ 0xffffffffU,
-/*0035*/ 0xffffffffU,
-/*0036*/ 0xffffffffU,
-/*0037*/ 0x0020080fU,
-/*0038*/ 0x00200810U,
-/*0039*/ 0x00200811U,
-/*003a*/ 0x00200812U,
-/*003b*/ 0x00030813U,
-/*003c*/ 0x08010813U,
-/*003d*/ 0x10030813U,
-/*003e*/ 0x18030813U,
-/*003f*/ 0x00040814U,
-/*0040*/ 0x08040814U,
-/*0041*/ 0x10040814U,
-/*0042*/ 0x18040814U,
-/*0043*/ 0x00010815U,
-/*0044*/ 0x08010815U,
-/*0045*/ 0x10060815U,
-/*0046*/ 0x18040815U,
-/*0047*/ 0xffffffffU,
-/*0048*/ 0x00060816U,
-/*0049*/ 0x08040816U,
-/*004a*/ 0x10060816U,
-/*004b*/ 0x18040816U,
-/*004c*/ 0x00020817U,
-/*004d*/ 0x08050817U,
-/*004e*/ 0x10080817U,
-/*004f*/ 0x00200818U,
-/*0050*/ 0x00060819U,
-/*0051*/ 0x08030819U,
-/*0052*/ 0x100b0819U,
-/*0053*/ 0x0004081aU,
-/*0054*/ 0x0804081aU,
-/*0055*/ 0x1004081aU,
-/*0056*/ 0xffffffffU,
-/*0057*/ 0x1801081aU,
-/*0058*/ 0x0009081bU,
-/*0059*/ 0x0020081cU,
-/*005a*/ 0x0020081dU,
-/*005b*/ 0x0020081eU,
-/*005c*/ 0x0020081fU,
-/*005d*/ 0x00100820U,
-/*005e*/ 0xffffffffU,
-/*005f*/ 0x10010820U,
-/*0060*/ 0x18060820U,
-/*0061*/ 0x00080821U,
-/*0062*/ 0x00200822U,
-/*0063*/ 0xffffffffU,
-/*0064*/ 0x000a0823U,
-/*0065*/ 0x10060823U,
-/*0066*/ 0x18070823U,
-/*0067*/ 0x00080824U,
-/*0068*/ 0x08080824U,
-/*0069*/ 0x100a0824U,
-/*006a*/ 0x00070825U,
-/*006b*/ 0x08080825U,
-/*006c*/ 0x10080825U,
-/*006d*/ 0x18030825U,
-/*006e*/ 0x000a0826U,
-/*006f*/ 0x100a0826U,
-/*0070*/ 0x00110827U,
-/*0071*/ 0x00090828U,
-/*0072*/ 0x10090828U,
-/*0073*/ 0x00100829U,
-/*0074*/ 0x100e0829U,
-/*0075*/ 0x000e082aU,
-/*0076*/ 0x100c082aU,
-/*0077*/ 0x000a082bU,
-/*0078*/ 0x100a082bU,
-/*0079*/ 0x0002082cU,
-/*007a*/ 0x0020082dU,
-/*007b*/ 0x000b082eU,
-/*007c*/ 0x100b082eU,
-/*007d*/ 0x0020082fU,
-/*007e*/ 0x00120830U,
-/*007f*/ 0x00200831U,
-/*0080*/ 0x00200832U,
-/*0081*/ 0xffffffffU,
-/*0082*/ 0xffffffffU,
-/*0083*/ 0x00010833U,
-/*0084*/ 0x08010833U,
-/*0085*/ 0x10080833U,
-/*0086*/ 0x000c0834U,
-/*0087*/ 0x100c0834U,
-/*0088*/ 0x000c0835U,
-/*0089*/ 0x100c0835U,
-/*008a*/ 0x000c0836U,
-/*008b*/ 0x100c0836U,
-/*008c*/ 0x000c0837U,
-/*008d*/ 0x100c0837U,
-/*008e*/ 0x000c0838U,
-/*008f*/ 0x100c0838U,
-/*0090*/ 0x000c0839U,
-/*0091*/ 0x100b0839U,
-/*0092*/ 0xffffffffU,
-/*0093*/ 0xffffffffU,
-/*0094*/ 0x000b083aU,
-/*0095*/ 0x100b083aU,
-/*0096*/ 0x000b083bU,
-/*0097*/ 0x100b083bU,
-/*0098*/ 0x000b083cU,
-/*0099*/ 0x100b083cU,
-/*009a*/ 0x000b083dU,
-/*009b*/ 0x100b083dU,
-/*009c*/ 0x000b083eU,
-/*009d*/ 0x100a083eU,
-/*009e*/ 0xffffffffU,
-/*009f*/ 0x000a083fU,
-/*00a0*/ 0x100a083fU,
-/*00a1*/ 0x000a0840U,
-/*00a2*/ 0x100a0840U,
-/*00a3*/ 0x000a0841U,
-/*00a4*/ 0x100a0841U,
-/*00a5*/ 0x000a0842U,
-/*00a6*/ 0x100a0842U,
-/*00a7*/ 0x000a0843U,
-/*00a8*/ 0x100a0843U,
-/*00a9*/ 0x000a0844U,
-/*00aa*/ 0x100a0844U,
-/*00ab*/ 0x000a0845U,
-/*00ac*/ 0x100a0845U,
-/*00ad*/ 0x000a0846U,
-/*00ae*/ 0x100a0846U,
-/*00af*/ 0x000a0847U,
-/*00b0*/ 0x100a0847U,
-/*00b1*/ 0x000a0848U,
-/*00b2*/ 0x100a0848U,
-/*00b3*/ 0x000a0849U,
-/*00b4*/ 0x100a0849U,
-/*00b5*/ 0x000a084aU,
-/*00b6*/ 0x100a084aU,
-/*00b7*/ 0x000a084bU,
-/*00b8*/ 0x100a084bU,
-/*00b9*/ 0x000a084cU,
-/*00ba*/ 0x100a084cU,
-/*00bb*/ 0x0004084dU,
-/*00bc*/ 0x0803084dU,
-/*00bd*/ 0x100a084dU,
-/*00be*/ 0x000a084eU,
-/*00bf*/ 0x1001084eU,
-/*00c0*/ 0x000a084fU,
-/*00c1*/ 0x1004084fU,
-/*00c2*/ 0x000b0850U,
-/*00c3*/ 0x100a0850U,
-/*00c4*/ 0xffffffffU,
-/*00c5*/ 0x00080851U,
-/*00c6*/ 0x08080851U,
-/*00c7*/ 0x10080851U,
-/*00c8*/ 0x18080851U,
-/*00c9*/ 0x00080852U,
-/*00ca*/ 0xffffffffU,
-/*00cb*/ 0x08080852U,
-/*00cc*/ 0x10010852U,
-/*00cd*/ 0x18080852U,
-/*00ce*/ 0x00080853U,
-/*00cf*/ 0x08020853U,
-/*00d0*/ 0x10020853U,
-/*00d1*/ 0x18040853U,
-/*00d2*/ 0x00040854U,
-/*00d3*/ 0xffffffffU,
-/*00d4*/ 0x08040854U,
-/*00d5*/ 0x100a0854U,
-/*00d6*/ 0x00060855U,
-/*00d7*/ 0x08080855U,
-/*00d8*/ 0xffffffffU,
-/*00d9*/ 0x10040855U,
-/*00da*/ 0x18040855U,
-/*00db*/ 0x00050856U,
-/*00dc*/ 0x08040856U,
-/*00dd*/ 0x10050856U,
-/*00de*/ 0x000a0857U,
-/*00df*/ 0x100a0857U,
-/*00e0*/ 0x00080858U,
-/*00e1*/ 0xffffffffU,
-/*00e2*/ 0x08040858U,
-/*00e3*/ 0xffffffffU,
-/*00e4*/ 0xffffffffU,
-/*00e5*/ 0x00050a00U,
-/*00e6*/ 0x08050a00U,
-/*00e7*/ 0x10050a00U,
-/*00e8*/ 0x18050a00U,
-/*00e9*/ 0x00050a01U,
-/*00ea*/ 0x08050a01U,
-/*00eb*/ 0x100b0a01U,
-/*00ec*/ 0x00010a02U,
-/*00ed*/ 0x08030a02U,
-/*00ee*/ 0x00200a03U,
-/*00ef*/ 0xffffffffU,
-/*00f0*/ 0x00030a04U,
-/*00f1*/ 0x080a0a04U,
-/*00f2*/ 0xffffffffU,
-/*00f3*/ 0xffffffffU,
-/*00f4*/ 0x18030a04U,
-/*00f5*/ 0x00030a05U,
-/*00f6*/ 0x08010a05U,
-/*00f7*/ 0x10010a05U,
-/*00f8*/ 0x18060a05U,
-/*00f9*/ 0xffffffffU,
-/*00fa*/ 0xffffffffU,
-/*00fb*/ 0xffffffffU,
-/*00fc*/ 0x00020a06U,
-/*00fd*/ 0x08030a06U,
-/*00fe*/ 0x10010a06U,
-/*00ff*/ 0x000f0a07U,
-/*0100*/ 0x00200a08U,
-/*0101*/ 0x00200a09U,
-/*0102*/ 0x000b0a0aU,
-/*0103*/ 0x100b0a0aU,
-/*0104*/ 0x000b0a0bU,
-/*0105*/ 0xffffffffU,
-/*0106*/ 0xffffffffU,
-/*0107*/ 0x00180a0cU,
-/*0108*/ 0x00180a0dU,
-/*0109*/ 0x00180a0eU,
-/*010a*/ 0x00180a0fU,
-/*010b*/ 0x18040a0fU,
-/*010c*/ 0x00020a10U,
-/*010d*/ 0x08020a10U,
-/*010e*/ 0x10040a10U,
-/*010f*/ 0x18040a10U,
-/*0110*/ 0x00010a11U,
-/*0111*/ 0x08010a11U,
-/*0112*/ 0x10010a11U,
-/*0113*/ 0x18030a11U,
-/*0114*/ 0x00200a12U,
-/*0115*/ 0x00200a13U,
-/*0116*/ 0xffffffffU,
-/*0117*/ 0x00140a14U,
-/*0118*/ 0x00140a15U,
-/*0119*/ 0x00140a16U,
-/*011a*/ 0x00140a17U,
-/*011b*/ 0x00140a18U,
-/*011c*/ 0x00140a19U,
-/*011d*/ 0x00140a1aU,
-/*011e*/ 0x00140a1bU,
-/*011f*/ 0x001e0a1cU,
-/*0120*/ 0x000a0a1dU,
-/*0121*/ 0x10060a1dU,
-/*0122*/ 0x18060a1dU,
-/*0123*/ 0x00060a1eU,
-/*0124*/ 0xffffffffU,
-/*0125*/ 0x08060a1eU,
-/*0126*/ 0x00080a1fU,
-/*0127*/ 0x080b0a1fU,
-/*0128*/ 0x000b0a20U,
-/*0129*/ 0x100b0a20U,
-/*012a*/ 0x000b0a21U,
-/*012b*/ 0x100b0a21U,
-/*012c*/ 0x000b0a22U,
-/*012d*/ 0x10040a22U,
-/*012e*/ 0x000a0a23U,
-/*012f*/ 0x10060a23U,
-/*0130*/ 0x18080a23U,
-/*0131*/ 0xffffffffU,
-/*0132*/ 0x00040a24U,
-/*0133*/ 0xffffffffU,
-/*0134*/ 0xffffffffU,
-/*0135*/ 0x00010b80U,
-/*0136*/ 0x08020b80U,
-/*0137*/ 0x10050b80U,
-/*0138*/ 0x18050b80U,
-/*0139*/ 0x00050b81U,
-/*013a*/ 0x08050b81U,
-/*013b*/ 0x100b0b81U,
-/*013c*/ 0x00050b82U,
-/*013d*/ 0x08010b82U,
-/*013e*/ 0x10010b82U,
-/*013f*/ 0xffffffffU,
-/*0140*/ 0x18010b82U,
-/*0141*/ 0x00010b83U,
-/*0142*/ 0x08040b83U,
-/*0143*/ 0x100b0b83U,
-/*0144*/ 0x000b0b84U,
-/*0145*/ 0xffffffffU,
-/*0146*/ 0x10040b84U,
-/*0147*/ 0x000b0b85U,
-/*0148*/ 0x10040b85U,
-/*0149*/ 0x18010b85U,
-/*014a*/ 0x00010b86U,
-/*014b*/ 0x08010b86U,
-/*014c*/ 0x00200b87U,
-/*014d*/ 0x00200b88U,
-/*014e*/ 0x00080b89U,
-/*014f*/ 0x080a0b89U,
-/*0150*/ 0x18050b89U,
-/*0151*/ 0x000a0b8aU,
-/*0152*/ 0x10030b8aU,
-/*0153*/ 0x18030b8aU,
-/*0154*/ 0x00010b8bU,
-/*0155*/ 0x08020b8bU,
-/*0156*/ 0x10010b8bU,
-/*0157*/ 0x18010b8bU,
-/*0158*/ 0x00010b8cU,
-/*0159*/ 0x08030b8cU,
-/*015a*/ 0xffffffffU,
-/*015b*/ 0x10040b8cU,
-/*015c*/ 0x18040b8cU,
-/*015d*/ 0x00040b8dU,
-/*015e*/ 0x08040b8dU,
-/*015f*/ 0xffffffffU,
-/*0160*/ 0xffffffffU,
-/*0161*/ 0xffffffffU,
-/*0162*/ 0xffffffffU,
-/*0163*/ 0xffffffffU,
-/*0164*/ 0xffffffffU,
-/*0165*/ 0xffffffffU,
-/*0166*/ 0xffffffffU,
-/*0167*/ 0xffffffffU,
-/*0168*/ 0x000d0b8eU,
-/*0169*/ 0x100d0b8eU,
-/*016a*/ 0x000d0b8fU,
-/*016b*/ 0x00050b90U,
-/*016c*/ 0x00010b91U,
-/*016d*/ 0x080e0b91U,
-/*016e*/ 0x000e0b92U,
-/*016f*/ 0x100e0b92U,
-/*0170*/ 0x000e0b93U,
-/*0171*/ 0x100e0b93U,
-/*0172*/ 0x00040b94U,
-/*0173*/ 0x08040b94U,
-/*0174*/ 0x10040b94U,
-/*0175*/ 0x18040b94U,
-/*0176*/ 0x00040b95U,
-/*0177*/ 0x080b0b95U,
-/*0178*/ 0x000b0b96U,
-/*0179*/ 0x100b0b96U,
-/*017a*/ 0x000b0b97U,
-/*017b*/ 0xffffffffU,
-/*017c*/ 0xffffffffU,
-/*017d*/ 0xffffffffU,
-/*017e*/ 0xffffffffU,
-/*017f*/ 0x000d0b98U,
-/*0180*/ 0x100d0b98U,
-/*0181*/ 0x000d0b99U,
-/*0182*/ 0x10100b99U,
-/*0183*/ 0x10080b8dU,
-/*0184*/ 0x18080b8dU,
-/*0185*/ 0x00100b9aU,
-/*0186*/ 0x10100b9aU,
-/*0187*/ 0x00100b9bU,
-/*0188*/ 0x10100b9bU,
-/*0189*/ 0x00100b9cU,
-/*018a*/ 0x10030b9cU,
-/*018b*/ 0x18040b9cU,
-/*018c*/ 0x00010b9dU,
-/*018d*/ 0x08040b9dU,
-/*018e*/ 0xffffffffU,
-/*018f*/ 0xffffffffU,
-/*0190*/ 0x10010b9dU,
-/*0191*/ 0x00140b9eU,
-/*0192*/ 0x000a0b9fU,
-/*0193*/ 0x100c0b9fU,
-/*0194*/ 0x00120ba0U,
-/*0195*/ 0x00140ba1U,
-/*0196*/ 0x00120ba2U,
-/*0197*/ 0x00110ba3U,
-/*0198*/ 0x00110ba4U,
-/*0199*/ 0x00120ba5U,
-/*019a*/ 0x00120ba6U,
-/*019b*/ 0x00120ba7U,
-/*019c*/ 0x00120ba8U,
-/*019d*/ 0x00120ba9U,
-/*019e*/ 0x00120baaU,
-/*019f*/ 0x00120babU,
-/*01a0*/ 0x00120bacU,
-/*01a1*/ 0xffffffffU,
-/*01a2*/ 0xffffffffU,
-/*01a3*/ 0x00190badU,
-/*01a4*/ 0x00190baeU,
-/*01a5*/ 0x00200bafU,
-/*01a6*/ 0x00170bb0U,
-/*01a7*/ 0x18080bb0U,
-/*01a8*/ 0x00010bb1U,
-/*01a9*/ 0x08010bb1U,
-/*01aa*/ 0x00200bb2U,
-/*01ab*/ 0x00080bb3U,
-/*01ac*/ 0xffffffffU,
-/*01ad*/ 0x08030bb3U,
-/*01ae*/ 0x00180bb4U,
-/*01af*/ 0x00180bb5U,
-/*01b0*/ 0xffffffffU,
-/*01b1*/ 0xffffffffU,
-/*01b2*/ 0xffffffffU,
-/*01b3*/ 0xffffffffU,
-/*01b4*/ 0xffffffffU,
-/*01b5*/ 0xffffffffU,
-/*01b6*/ 0xffffffffU,
-/*01b7*/ 0xffffffffU,
-/*01b8*/ 0xffffffffU,
-/*01b9*/ 0xffffffffU,
-/*01ba*/ 0xffffffffU,
-/*01bb*/ 0xffffffffU,
-/*01bc*/ 0xffffffffU,
-/*01bd*/ 0xffffffffU,
-/*01be*/ 0xffffffffU,
-/*01bf*/ 0x00100bb6U,
-/*01c0*/ 0x10010bb6U,
-/*01c1*/ 0x18010bb6U,
-/*01c2*/ 0x00050bb7U,
-/*01c3*/ 0x00200bb8U,
-/*01c4*/ 0x00090bb9U,
-/*01c5*/ 0xffffffffU,
-/*01c6*/ 0xffffffffU,
-/*01c7*/ 0x00200bbaU,
-/*01c8*/ 0x00040bbbU,
-/*01c9*/ 0x08100bbbU,
-/*01ca*/ 0x18060bbbU,
-/*01cb*/ 0x00100bbcU,
-/*01cc*/ 0xffffffffU,
-/*01cd*/ 0x10080bbcU,
-/*01ce*/ 0xffffffffU,
-/*01cf*/ 0xffffffffU,
-/*01d0*/ 0xffffffffU,
-/*01d1*/ 0x18030bbcU,
-/*01d2*/ 0x00020bbdU,
-/*01d3*/ 0xffffffffU,
-/*01d4*/ 0x00200bbeU,
-/*01d5*/ 0x000b0bbfU,
-/*01d6*/ 0xffffffffU,
-/*01d7*/ 0xffffffffU,
-/*01d8*/ 0xffffffffU,
-/*01d9*/ 0x10020bbfU,
-/*01da*/ 0xffffffffU,
-/*01db*/ 0xffffffffU,
-/*01dc*/ 0xffffffffU,
-/*01dd*/ 0xffffffffU,
-/*01de*/ 0x00010200U,
-/*01df*/ 0x08040200U,
-/*01e0*/ 0x10100200U,
-/*01e1*/ 0x00010201U,
-/*01e2*/ 0x08010201U,
-/*01e3*/ 0xffffffffU,
-/*01e4*/ 0xffffffffU,
-/*01e5*/ 0x10100201U,
-/*01e6*/ 0xffffffffU,
-/*01e7*/ 0xffffffffU,
-/*01e8*/ 0xffffffffU,
-/*01e9*/ 0xffffffffU,
-/*01ea*/ 0xffffffffU,
-/*01eb*/ 0xffffffffU,
-/*01ec*/ 0xffffffffU,
-/*01ed*/ 0xffffffffU,
-/*01ee*/ 0xffffffffU,
-/*01ef*/ 0x00200202U,
-/*01f0*/ 0x00100203U,
-/*01f1*/ 0x00200204U,
-/*01f2*/ 0x00100205U,
-/*01f3*/ 0x00200206U,
-/*01f4*/ 0x00100207U,
-/*01f5*/ 0x10100207U,
-/*01f6*/ 0x00200208U,
-/*01f7*/ 0x00200209U,
-/*01f8*/ 0x0020020aU,
-/*01f9*/ 0x0020020bU,
-/*01fa*/ 0x0010020cU,
-/*01fb*/ 0x0020020dU,
-/*01fc*/ 0x0020020eU,
-/*01fd*/ 0x0020020fU,
-/*01fe*/ 0x00200210U,
-/*01ff*/ 0x00100211U,
-/*0200*/ 0x00200212U,
-/*0201*/ 0x00200213U,
-/*0202*/ 0x00200214U,
-/*0203*/ 0x00200215U,
-/*0204*/ 0x00090216U,
-/*0205*/ 0x10010216U,
-/*0206*/ 0x00200217U,
-/*0207*/ 0x00050218U,
-/*0208*/ 0x08010218U,
-/*0209*/ 0x10080218U,
-/*020a*/ 0x18080218U,
-/*020b*/ 0x001e0219U,
-/*020c*/ 0x001e021aU,
-/*020d*/ 0x001e021bU,
-/*020e*/ 0x001e021cU,
-/*020f*/ 0x001e021dU,
-/*0210*/ 0x001e021eU,
-/*0211*/ 0x001e021fU,
-/*0212*/ 0x001e0220U,
-/*0213*/ 0x001e0221U,
-/*0214*/ 0x001e0222U,
-/*0215*/ 0x001e0223U,
-/*0216*/ 0x001e0224U,
-/*0217*/ 0x001e0225U,
-/*0218*/ 0x001e0226U,
-/*0219*/ 0x001e0227U,
-/*021a*/ 0x001e0228U,
-/*021b*/ 0x00010229U,
-/*021c*/ 0x08010229U,
-/*021d*/ 0x10010229U,
-/*021e*/ 0x18040229U,
-/*021f*/ 0x0008022aU,
-/*0220*/ 0x0808022aU,
-/*0221*/ 0x1008022aU,
-/*0222*/ 0x1804022aU,
-/*0223*/ 0x0005022bU,
-/*0224*/ 0x0806022bU,
-/*0225*/ 0x1007022bU,
-/*0226*/ 0x1805022bU,
-/*0227*/ 0x0006022cU,
-/*0228*/ 0x0807022cU,
-/*0229*/ 0x1005022cU,
-/*022a*/ 0x1806022cU,
-/*022b*/ 0x0007022dU,
-/*022c*/ 0x0802022dU,
-/*022d*/ 0x1001022dU,
-/*022e*/ 0xffffffffU,
-/*022f*/ 0x000a022eU,
-/*0230*/ 0x1010022eU,
-/*0231*/ 0x000a022fU,
-/*0232*/ 0x1010022fU,
-/*0233*/ 0x000a0230U,
-/*0234*/ 0x10100230U,
-/*0235*/ 0xffffffffU,
-/*0236*/ 0x00100231U,
-/*0237*/ 0xffffffffU,
-/*0238*/ 0xffffffffU,
-/*0239*/ 0x10010231U,
-/*023a*/ 0x18010231U,
-/*023b*/ 0x00010232U,
-/*023c*/ 0x08010232U,
-/*023d*/ 0x10010232U,
-/*023e*/ 0x18010232U,
-/*023f*/ 0x00020233U,
-/*0240*/ 0x08020233U,
-/*0241*/ 0x10020233U,
-/*0242*/ 0x18020233U,
-/*0243*/ 0x00020234U,
-/*0244*/ 0x08030234U,
-/*0245*/ 0x10010234U,
-/*0246*/ 0x18010234U,
-/*0247*/ 0x00010235U,
-/*0248*/ 0x08010235U,
-/*0249*/ 0xffffffffU,
-/*024a*/ 0x10020235U,
-/*024b*/ 0x18010235U,
-/*024c*/ 0x00010236U,
-/*024d*/ 0xffffffffU,
-/*024e*/ 0x08020236U,
-/*024f*/ 0x10010236U,
-/*0250*/ 0x18010236U,
-/*0251*/ 0xffffffffU,
-/*0252*/ 0x00020237U,
-/*0253*/ 0x08010237U,
-/*0254*/ 0x10010237U,
-/*0255*/ 0xffffffffU,
-/*0256*/ 0x18020237U,
-/*0257*/ 0x00070238U,
-/*0258*/ 0x08010238U,
-/*0259*/ 0x10010238U,
-/*025a*/ 0x18010238U,
-/*025b*/ 0x00010239U,
-/*025c*/ 0x08010239U,
-/*025d*/ 0x10010239U,
-/*025e*/ 0xffffffffU,
-/*025f*/ 0x18010239U,
-/*0260*/ 0x0004023aU,
-/*0261*/ 0x0804023aU,
-/*0262*/ 0x1004023aU,
-/*0263*/ 0x1801023aU,
-/*0264*/ 0x0002023bU,
-/*0265*/ 0x0806023bU,
-/*0266*/ 0x1006023bU,
-/*0267*/ 0xffffffffU,
-/*0268*/ 0xffffffffU,
-/*0269*/ 0xffffffffU,
-/*026a*/ 0x1802023bU,
-/*026b*/ 0x0010023cU,
-/*026c*/ 0x1001023cU,
-/*026d*/ 0x1801023cU,
-/*026e*/ 0xffffffffU,
-/*026f*/ 0x0004023dU,
-/*0270*/ 0x0801023dU,
-/*0271*/ 0x1004023dU,
-/*0272*/ 0x1802023dU,
-/*0273*/ 0x0008023eU,
-/*0274*/ 0xffffffffU,
-/*0275*/ 0xffffffffU,
-/*0276*/ 0xffffffffU,
-/*0277*/ 0x080a023eU,
-/*0278*/ 0x0020023fU,
-/*0279*/ 0x00200240U,
-/*027a*/ 0x00050241U,
-/*027b*/ 0x08010241U,
-/*027c*/ 0x10050241U,
-/*027d*/ 0x18080241U,
-/*027e*/ 0x00010242U,
-/*027f*/ 0x08080242U,
-/*0280*/ 0x10010242U,
-/*0281*/ 0x18080242U,
-/*0282*/ 0x00010243U,
-/*0283*/ 0x08040243U,
-/*0284*/ 0x10040243U,
-/*0285*/ 0x18040243U,
-/*0286*/ 0x00040244U,
-/*0287*/ 0x08040244U,
-/*0288*/ 0x10040244U,
-/*0289*/ 0x18040244U,
-/*028a*/ 0x00040245U,
-/*028b*/ 0x08040245U,
-/*028c*/ 0x10040245U,
-/*028d*/ 0x18010245U,
-/*028e*/ 0x00040246U,
-/*028f*/ 0x08040246U,
-/*0290*/ 0x10040246U,
-/*0291*/ 0x18040246U,
-/*0292*/ 0x00040247U,
-/*0293*/ 0x08040247U,
-/*0294*/ 0x10060247U,
-/*0295*/ 0x18060247U,
-/*0296*/ 0x00060248U,
-/*0297*/ 0x08060248U,
-/*0298*/ 0x10060248U,
-/*0299*/ 0x18060248U,
-/*029a*/ 0x00040249U,
-/*029b*/ 0x08010249U,
-/*029c*/ 0x10010249U,
-/*029d*/ 0x18020249U,
-/*029e*/ 0xffffffffU,
-/*029f*/ 0xffffffffU,
-/*02a0*/ 0xffffffffU,
-/*02a1*/ 0xffffffffU,
-/*02a2*/ 0xffffffffU,
-/*02a3*/ 0xffffffffU,
-/*02a4*/ 0xffffffffU,
-/*02a5*/ 0xffffffffU,
-/*02a6*/ 0x0004024aU,
-/*02a7*/ 0x0804024aU,
-/*02a8*/ 0x1001024aU,
-/*02a9*/ 0x1801024aU,
-/*02aa*/ 0xffffffffU,
-/*02ab*/ 0x0001024bU,
-/*02ac*/ 0x0801024bU,
-/*02ad*/ 0xffffffffU,
-/*02ae*/ 0x1001024bU,
-/*02af*/ 0x1801024bU,
-/*02b0*/ 0x0001024cU,
-/*02b1*/ 0x0804024cU,
-/*02b2*/ 0x1004024cU,
-/*02b3*/ 0x000a024dU,
-/*02b4*/ 0x0020024eU,
-/*02b5*/ 0x0004024fU,
-/*02b6*/ 0x0808024fU,
-/*02b7*/ 0xffffffffU,
-/*02b8*/ 0xffffffffU,
-/*02b9*/ 0xffffffffU,
-/*02ba*/ 0xffffffffU,
-/*02bb*/ 0xffffffffU,
-/*02bc*/ 0xffffffffU,
-/*02bd*/ 0x1002024fU,
-/*02be*/ 0x1802024fU,
-/*02bf*/ 0x00200250U,
-/*02c0*/ 0x00020251U,
-/*02c1*/ 0x08100251U,
-/*02c2*/ 0x00100252U,
-/*02c3*/ 0x10040252U,
-/*02c4*/ 0x18040252U,
-/*02c5*/ 0x00050253U,
-/*02c6*/ 0x08050253U,
-/*02c7*/ 0xffffffffU,
-/*02c8*/ 0xffffffffU,
-/*02c9*/ 0xffffffffU,
-/*02ca*/ 0xffffffffU,
-/*02cb*/ 0x10010253U,
-/*02cc*/ 0x18010253U,
-/*02cd*/ 0x00080254U,
-/*02ce*/ 0x08080254U,
-/*02cf*/ 0x10080254U,
-/*02d0*/ 0x18080254U,
-/*02d1*/ 0x00080255U,
-/*02d2*/ 0x08080255U,
-/*02d3*/ 0x10080255U,
-/*02d4*/ 0x18080255U,
-/*02d5*/ 0x00080256U,
-/*02d6*/ 0x08080256U,
-/*02d7*/ 0x10080256U,
-/*02d8*/ 0xffffffffU,
-/*02d9*/ 0xffffffffU,
-/*02da*/ 0xffffffffU,
-/*02db*/ 0xffffffffU,
-/*02dc*/ 0xffffffffU,
-/*02dd*/ 0xffffffffU,
-/*02de*/ 0x18030256U,
-/*02df*/ 0x00010257U,
-/*02e0*/ 0x08020257U,
-/*02e1*/ 0x10010257U,
-/*02e2*/ 0x18040257U,
-/*02e3*/ 0x00020258U,
-/*02e4*/ 0x08010258U,
-/*02e5*/ 0x10010258U,
-/*02e6*/ 0xffffffffU,
-/*02e7*/ 0x18010258U,
-/*02e8*/ 0x00040259U,
-/*02e9*/ 0x08080259U,
-/*02ea*/ 0x100a0259U,
-/*02eb*/ 0x000a025aU,
-/*02ec*/ 0x100a025aU,
-/*02ed*/ 0x000a025bU,
-/*02ee*/ 0x100a025bU,
-/*02ef*/ 0x000a025cU,
-/*02f0*/ 0x0020025dU,
-/*02f1*/ 0x0020025eU,
-/*02f2*/ 0x0001025fU,
-/*02f3*/ 0xffffffffU,
-/*02f4*/ 0xffffffffU,
-/*02f5*/ 0xffffffffU,
-/*02f6*/ 0x0802025fU,
-/*02f7*/ 0x1002025fU,
-/*02f8*/ 0x00100260U,
-/*02f9*/ 0x10050260U,
-/*02fa*/ 0x18060260U,
-/*02fb*/ 0x00050261U,
-/*02fc*/ 0x08050261U,
-/*02fd*/ 0x100e0261U,
-/*02fe*/ 0x00050262U,
-/*02ff*/ 0x080e0262U,
-/*0300*/ 0x18050262U,
-/*0301*/ 0x000e0263U,
-/*0302*/ 0x10050263U,
-/*0303*/ 0x18010263U,
-/*0304*/ 0x00050264U,
-/*0305*/ 0x08050264U,
-/*0306*/ 0x100a0264U,
-/*0307*/ 0x000a0265U,
-/*0308*/ 0x10050265U,
-/*0309*/ 0x18050265U,
-/*030a*/ 0x000a0266U,
-/*030b*/ 0x100a0266U,
-/*030c*/ 0x00050267U,
-/*030d*/ 0x08050267U,
-/*030e*/ 0x100a0267U,
-/*030f*/ 0x000a0268U,
-/*0310*/ 0xffffffffU,
-/*0311*/ 0xffffffffU,
-/*0312*/ 0xffffffffU,
-/*0313*/ 0xffffffffU,
-/*0314*/ 0xffffffffU,
-/*0315*/ 0xffffffffU,
-/*0316*/ 0x10070268U,
-/*0317*/ 0x18070268U,
-/*0318*/ 0x00040269U,
-/*0319*/ 0x08040269U,
-/*031a*/ 0xffffffffU,
-/*031b*/ 0xffffffffU,
-/*031c*/ 0xffffffffU,
-/*031d*/ 0x10040269U,
-/*031e*/ 0x18080269U,
-/*031f*/ 0x0008026aU,
-/*0320*/ 0x0804026aU,
-/*0321*/ 0xffffffffU,
-/*0322*/ 0xffffffffU,
-/*0323*/ 0xffffffffU,
-/*0324*/ 0x1004026aU,
-/*0325*/ 0xffffffffU,
-/*0326*/ 0xffffffffU,
-/*0327*/ 0xffffffffU,
-/*0328*/ 0x1804026aU,
-/*0329*/ 0xffffffffU,
-/*032a*/ 0xffffffffU,
-/*032b*/ 0xffffffffU,
-/*032c*/ 0x0004026bU,
-/*032d*/ 0x0805026bU,
-/*032e*/ 0x1007026bU,
-/*032f*/ 0x1808026bU,
-/*0330*/ 0x0010026cU,
-/*0331*/ 0x1008026cU,
-/*0332*/ 0x0010026dU,
-/*0333*/ 0x1008026dU,
-/*0334*/ 0x0010026eU,
-/*0335*/ 0x1008026eU,
-/*0336*/ 0x1808026eU,
-/*0337*/ 0x0001026fU,
-/*0338*/ 0x0801026fU,
-/*0339*/ 0x1006026fU,
-/*033a*/ 0x1806026fU,
-/*033b*/ 0x00060270U,
-/*033c*/ 0xffffffffU,
-/*033d*/ 0x08010270U,
-/*033e*/ 0x10030270U,
-/*033f*/ 0xffffffffU,
-/*0340*/ 0xffffffffU,
-/*0341*/ 0xffffffffU,
-/*0342*/ 0x000a0271U,
-/*0343*/ 0x100a0271U,
-/*0344*/ 0x00040272U,
-/*0345*/ 0x08010272U,
-/*0346*/ 0x10040272U,
-/*0347*/ 0xffffffffU,
-/*0348*/ 0xffffffffU,
-/*0349*/ 0xffffffffU,
-/*034a*/ 0xffffffffU,
-/*034b*/ 0xffffffffU,
-/*034c*/ 0xffffffffU,
-/*034d*/ 0x18070272U,
-/*034e*/ 0x00070273U,
-/*034f*/ 0x08050273U,
-/*0350*/ 0x10050273U,
-/*0351*/ 0xffffffffU,
-/*0352*/ 0xffffffffU,
-/*0353*/ 0xffffffffU,
-/*0354*/ 0x18040273U,
-/*0355*/ 0x00010274U,
-/*0356*/ 0x08010274U,
-/*0357*/ 0x10020274U,
-/*0358*/ 0x18080274U,
-/*0359*/ 0x00200275U,
-/*035a*/ 0x00200276U,
-/*035b*/ 0x00100277U,
-/*035c*/ 0xffffffffU,
-/*035d*/ 0xffffffffU,
-/*035e*/ 0xffffffffU,
-/*035f*/ 0x10020277U,
-/*0360*/ 0x18010277U,
-/*0361*/ 0xffffffffU,
-/*0362*/ 0x00020278U,
-/*0363*/ 0x08100278U,
-/*0364*/ 0x00100279U,
-/*0365*/ 0x10100279U,
-/*0366*/ 0x0008027aU,
-/*0367*/ 0x0808027aU,
-/*0368*/ 0x1008027aU,
-/*0369*/ 0xffffffffU,
-/*036a*/ 0x0010027bU,
-/*036b*/ 0x1010027bU,
-/*036c*/ 0x0010027cU,
-/*036d*/ 0x1008027cU,
-/*036e*/ 0x1808027cU,
-/*036f*/ 0x0008027dU,
-/*0370*/ 0xffffffffU,
-/*0371*/ 0x0810027dU,
-/*0372*/ 0x0010027eU,
-/*0373*/ 0x1010027eU,
-/*0374*/ 0x0008027fU,
-/*0375*/ 0x0808027fU,
-/*0376*/ 0x1008027fU,
-/*0377*/ 0xffffffffU,
-/*0378*/ 0x1808027fU,
-/*0379*/ 0x00100280U,
-/*037a*/ 0x10100280U,
-/*037b*/ 0x00100281U,
-/*037c*/ 0x10080281U,
-/*037d*/ 0x18080281U,
-/*037e*/ 0x00080282U,
-/*037f*/ 0xffffffffU,
-/*0380*/ 0x08100282U,
-/*0381*/ 0x00100283U,
-/*0382*/ 0x10100283U,
-/*0383*/ 0x00080284U,
-/*0384*/ 0x08080284U,
-/*0385*/ 0x10080284U,
-/*0386*/ 0xffffffffU,
-/*0387*/ 0x00100285U,
-/*0388*/ 0x10100285U,
-/*0389*/ 0x00100286U,
-/*038a*/ 0x10080286U,
-/*038b*/ 0x18080286U,
-/*038c*/ 0x00080287U,
-/*038d*/ 0xffffffffU,
-/*038e*/ 0x08080287U,
-/*038f*/ 0x10100287U,
-/*0390*/ 0x00100288U,
-/*0391*/ 0x10100288U,
-/*0392*/ 0x00080289U,
-/*0393*/ 0x08080289U,
-/*0394*/ 0x10080289U,
-/*0395*/ 0xffffffffU,
-/*0396*/ 0x0010028aU,
-/*0397*/ 0x1010028aU,
-/*0398*/ 0x0010028bU,
-/*0399*/ 0x1008028bU,
-/*039a*/ 0x1808028bU,
-/*039b*/ 0x0008028cU,
-/*039c*/ 0xffffffffU,
-/*039d*/ 0x0810028cU,
-/*039e*/ 0x0010028dU,
-/*039f*/ 0x1010028dU,
-/*03a0*/ 0x0008028eU,
-/*03a1*/ 0x0808028eU,
-/*03a2*/ 0x1008028eU,
-/*03a3*/ 0xffffffffU,
-/*03a4*/ 0x1808028eU,
-/*03a5*/ 0x0010028fU,
-/*03a6*/ 0x1010028fU,
-/*03a7*/ 0x00100290U,
-/*03a8*/ 0x10080290U,
-/*03a9*/ 0x18080290U,
-/*03aa*/ 0x00080291U,
-/*03ab*/ 0xffffffffU,
-/*03ac*/ 0x08100291U,
-/*03ad*/ 0x00100292U,
-/*03ae*/ 0x10100292U,
-/*03af*/ 0x00080293U,
-/*03b0*/ 0x08080293U,
-/*03b1*/ 0x10080293U,
-/*03b2*/ 0xffffffffU,
-/*03b3*/ 0x00100294U,
-/*03b4*/ 0x10100294U,
-/*03b5*/ 0x00100295U,
-/*03b6*/ 0x10080295U,
-/*03b7*/ 0x18080295U,
-/*03b8*/ 0x00080296U,
-/*03b9*/ 0xffffffffU,
-/*03ba*/ 0x08080296U,
-/*03bb*/ 0x10020296U,
-/*03bc*/ 0x18030296U,
-/*03bd*/ 0x000a0297U,
-/*03be*/ 0x100a0297U,
-/*03bf*/ 0x000a0298U,
-/*03c0*/ 0x10050298U,
-/*03c1*/ 0x18040298U,
-/*03c2*/ 0x00080299U,
-/*03c3*/ 0x08080299U,
-/*03c4*/ 0x10060299U,
-/*03c5*/ 0x18060299U,
-/*03c6*/ 0x0011029aU,
-/*03c7*/ 0x1808029aU,
-/*03c8*/ 0x0004029bU,
-/*03c9*/ 0x0806029bU,
-/*03ca*/ 0xffffffffU,
-/*03cb*/ 0x1006029bU,
-/*03cc*/ 0x1808029bU,
-/*03cd*/ 0x0008029cU,
-/*03ce*/ 0x0804029cU,
-/*03cf*/ 0x1008029cU,
-/*03d0*/ 0x1808029cU,
-/*03d1*/ 0x0006029dU,
-/*03d2*/ 0x0806029dU,
-/*03d3*/ 0x0011029eU,
-/*03d4*/ 0x1808029eU,
-/*03d5*/ 0x0004029fU,
-/*03d6*/ 0x0806029fU,
-/*03d7*/ 0xffffffffU,
-/*03d8*/ 0x1006029fU,
-/*03d9*/ 0x1808029fU,
-/*03da*/ 0x000802a0U,
-/*03db*/ 0x080402a0U,
-/*03dc*/ 0x100802a0U,
-/*03dd*/ 0x180802a0U,
-/*03de*/ 0x000602a1U,
-/*03df*/ 0x080602a1U,
-/*03e0*/ 0x001102a2U,
-/*03e1*/ 0x180802a2U,
-/*03e2*/ 0x000402a3U,
-/*03e3*/ 0x080602a3U,
-/*03e4*/ 0xffffffffU,
-/*03e5*/ 0x100602a3U,
-/*03e6*/ 0x180802a3U,
-/*03e7*/ 0x000802a4U,
-/*03e8*/ 0x080402a4U,
-/*03e9*/ 0x100402a4U,
-/*03ea*/ 0x180402a4U,
-/*03eb*/ 0x000402a5U,
-/*03ec*/ 0x080402a5U,
-/*03ed*/ 0x100402a5U,
-/*03ee*/ 0x180402a5U,
-/*03ef*/ 0x000402a6U,
-/*03f0*/ 0x080402a6U,
-/*03f1*/ 0x100402a6U,
-/*03f2*/ 0x180402a6U,
-/*03f3*/ 0x000402a7U,
-/*03f4*/ 0x080402a7U,
-/*03f5*/ 0x100402a7U,
-/*03f6*/ 0x180402a7U,
-/*03f7*/ 0x000402a8U,
-/*03f8*/ 0x080402a8U,
-/*03f9*/ 0x100402a8U,
-/*03fa*/ 0x180402a8U,
-/*03fb*/ 0x000402a9U,
-/*03fc*/ 0x081202a9U,
-/*03fd*/ 0x001102aaU,
-/*03fe*/ 0x001202abU,
-/*03ff*/ 0x002002acU,
-/*0400*/ 0x002002adU,
-/*0401*/ 0x002002aeU,
-/*0402*/ 0x002002afU,
-/*0403*/ 0x002002b0U,
-/*0404*/ 0x002002b1U,
-/*0405*/ 0x002002b2U,
-/*0406*/ 0x002002b3U,
-/*0407*/ 0x002002b4U,
-/*0408*/ 0x000302b5U,
-/*0409*/ 0x080502b5U,
-/*040a*/ 0x100502b5U,
-/*040b*/ 0x180102b5U,
-/*040c*/ 0x000502b6U,
-/*040d*/ 0x080502b6U,
-/*040e*/ 0x100502b6U,
-/*040f*/ 0x180502b6U,
-/*0410*/ 0x000502b7U,
-/*0411*/ 0x080502b7U,
-/*0412*/ 0x100502b7U,
-/*0413*/ 0x180502b7U,
-/*0414*/ 0x000502b8U,
-/*0415*/ 0x080502b8U,
-/*0416*/ 0x100502b8U,
-/*0417*/ 0x180502b8U,
-/*0418*/ 0x000502b9U,
-/*0419*/ 0x080502b9U,
-/*041a*/ 0x100502b9U,
-/*041b*/ 0x180502b9U,
-/*041c*/ 0x000502baU,
-/*041d*/ 0x080502baU,
-/*041e*/ 0x100502baU,
-/*041f*/ 0x180502baU,
-/*0420*/ 0x000502bbU,
-/*0421*/ 0x080502bbU,
-/*0422*/ 0x100102bbU,
-/*0423*/ 0x180202bbU,
-/*0424*/ 0x000202bcU,
-/*0425*/ 0x080202bcU,
-/*0426*/ 0x100202bcU,
-/*0427*/ 0x180102bcU,
-/*0428*/ 0x000402bdU,
-/*0429*/ 0x081002bdU,
-/*042a*/ 0x002002beU,
-/*042b*/ 0x001002bfU,
-/*042c*/ 0x002002c0U,
-/*042d*/ 0x001002c1U,
-/*042e*/ 0x002002c2U,
-/*042f*/ 0x000702c3U,
-/*0430*/ 0x080102c3U,
-/*0431*/ 0x100202c3U,
-/*0432*/ 0x180602c3U,
-/*0433*/ 0x000102c4U,
-/*0434*/ 0x080102c4U,
-/*0435*/ 0x002002c5U,
-/*0436*/ 0x000302c6U,
-/*0437*/ 0x002002c7U,
-/*0438*/ 0x002002c8U,
-/*0439*/ 0xffffffffU,
-/*043a*/ 0xffffffffU,
-/*043b*/ 0xffffffffU,
-/*043c*/ 0xffffffffU,
-/*043d*/ 0xffffffffU,
-/*043e*/ 0xffffffffU,
-/*043f*/ 0xffffffffU,
-/*0440*/ 0xffffffffU,
-/*0441*/ 0xffffffffU,
-/*0442*/ 0xffffffffU,
-/*0443*/ 0xffffffffU,
-/*0444*/ 0xffffffffU,
-/*0445*/ 0xffffffffU,
-/*0446*/ 0xffffffffU,
-/*0447*/ 0xffffffffU,
-/*0448*/ 0xffffffffU,
-/*0449*/ 0xffffffffU,
-/*044a*/ 0xffffffffU,
-/*044b*/ 0xffffffffU,
-/*044c*/ 0xffffffffU,
-/*044d*/ 0xffffffffU,
-/*044e*/ 0xffffffffU,
-/*044f*/ 0xffffffffU,
-/*0450*/ 0xffffffffU,
-/*0451*/ 0xffffffffU,
-/*0452*/ 0xffffffffU,
-/*0453*/ 0xffffffffU,
-/*0454*/ 0xffffffffU,
-/*0455*/ 0xffffffffU,
-/*0456*/ 0xffffffffU,
-/*0457*/ 0xffffffffU,
-/*0458*/ 0xffffffffU,
-/*0459*/ 0xffffffffU,
-/*045a*/ 0xffffffffU,
-/*045b*/ 0xffffffffU,
-/*045c*/ 0xffffffffU,
-/*045d*/ 0xffffffffU,
-/*045e*/ 0xffffffffU,
-/*045f*/ 0x000402c9U,
-/*0460*/ 0xffffffffU,
-/*0461*/ 0xffffffffU,
-/*0462*/ 0xffffffffU,
-/*0463*/ 0xffffffffU,
-/*0464*/ 0xffffffffU,
-/*0465*/ 0xffffffffU,
-/*0466*/ 0xffffffffU,
-/*0467*/ 0xffffffffU,
-/*0468*/ 0xffffffffU,
-/*0469*/ 0xffffffffU,
-/*046a*/ 0xffffffffU,
-/*046b*/ 0xffffffffU,
-/*046c*/ 0xffffffffU,
-/*046d*/ 0xffffffffU,
-/*046e*/ 0xffffffffU,
-/*046f*/ 0xffffffffU,
-/*0470*/ 0xffffffffU,
-/*0471*/ 0xffffffffU,
-/*0472*/ 0xffffffffU,
-/*0473*/ 0xffffffffU,
-/*0474*/ 0xffffffffU,
-/*0475*/ 0xffffffffU,
-/*0476*/ 0xffffffffU,
-/*0477*/ 0xffffffffU,
-/*0478*/ 0xffffffffU,
-/*0479*/ 0xffffffffU,
-/*047a*/ 0xffffffffU,
-/*047b*/ 0xffffffffU,
-/*047c*/ 0xffffffffU,
-/*047d*/ 0xffffffffU,
-/*047e*/ 0xffffffffU,
-/*047f*/ 0xffffffffU,
-/*0480*/ 0xffffffffU,
-/*0481*/ 0xffffffffU,
-/*0482*/ 0xffffffffU,
-/*0483*/ 0xffffffffU,
-/*0484*/ 0xffffffffU,
-/*0485*/ 0xffffffffU,
-/*0486*/ 0xffffffffU,
-/*0487*/ 0xffffffffU,
-/*0488*/ 0xffffffffU,
-/*0489*/ 0xffffffffU,
-/*048a*/ 0xffffffffU,
-/*048b*/ 0xffffffffU,
-/*048c*/ 0xffffffffU,
-/*048d*/ 0xffffffffU,
-/*048e*/ 0xffffffffU,
-/*048f*/ 0xffffffffU,
-/*0490*/ 0xffffffffU,
-/*0491*/ 0xffffffffU,
-/*0492*/ 0xffffffffU,
-/*0493*/ 0xffffffffU,
-/*0494*/ 0xffffffffU,
-	 },
-	{
-/*0000*/ 0x00200400U,
-/*0001*/ 0x00040401U,
-/*0002*/ 0x080b0401U,
-/*0003*/ 0x000a0402U,
-/*0004*/ 0x10020402U,
-/*0005*/ 0x18010402U,
-/*0006*/ 0x00050403U,
-/*0007*/ 0x08050403U,
-/*0008*/ 0x10050403U,
-/*0009*/ 0x18050403U,
-/*000a*/ 0x00050404U,
-/*000b*/ 0x08050404U,
-/*000c*/ 0x10050404U,
-/*000d*/ 0x18050404U,
-/*000e*/ 0x00050405U,
-/*000f*/ 0x08040405U,
-/*0010*/ 0x10030405U,
-/*0011*/ 0x00180406U,
-/*0012*/ 0x18030406U,
-/*0013*/ 0x00180407U,
-/*0014*/ 0x18020407U,
-/*0015*/ 0x00010408U,
-/*0016*/ 0x08020408U,
-/*0017*/ 0x10010408U,
-/*0018*/ 0x18010408U,
-/*0019*/ 0x00020409U,
-/*001a*/ 0x08040409U,
-/*001b*/ 0x10040409U,
-/*001c*/ 0x18040409U,
-/*001d*/ 0xffffffffU,
-/*001e*/ 0x0004040aU,
-/*001f*/ 0xffffffffU,
-/*0020*/ 0xffffffffU,
-/*0021*/ 0x0809040aU,
-/*0022*/ 0x1801040aU,
-/*0023*/ 0x0020040bU,
-/*0024*/ 0x001c040cU,
-/*0025*/ 0x0001040dU,
-/*0026*/ 0x0807040dU,
-/*0027*/ 0x1009040dU,
-/*0028*/ 0x000a040eU,
-/*0029*/ 0x1005040eU,
-/*002a*/ 0x1801040eU,
-/*002b*/ 0x1001040fU,
-/*002c*/ 0x1802040fU,
-/*002d*/ 0x0009040fU,
-/*002e*/ 0x00090410U,
-/*002f*/ 0x10020410U,
-/*0030*/ 0x00200411U,
-/*0031*/ 0x00010412U,
-/*0032*/ 0x08020412U,
-/*0033*/ 0xffffffffU,
-/*0034*/ 0xffffffffU,
-/*0035*/ 0xffffffffU,
-/*0036*/ 0xffffffffU,
-/*0037*/ 0x00200413U,
-/*0038*/ 0x00200414U,
-/*0039*/ 0x00200415U,
-/*003a*/ 0x00200416U,
-/*003b*/ 0x00030417U,
-/*003c*/ 0x08010417U,
-/*003d*/ 0x10040417U,
-/*003e*/ 0x18030417U,
-/*003f*/ 0x00040418U,
-/*0040*/ 0x08040418U,
-/*0041*/ 0x10040418U,
-/*0042*/ 0x18040418U,
-/*0043*/ 0x00010419U,
-/*0044*/ 0x08010419U,
-/*0045*/ 0x10060419U,
-/*0046*/ 0x18040419U,
-/*0047*/ 0xffffffffU,
-/*0048*/ 0x0006041aU,
-/*0049*/ 0x0804041aU,
-/*004a*/ 0x1006041aU,
-/*004b*/ 0x1804041aU,
-/*004c*/ 0x0002041bU,
-/*004d*/ 0x0805041bU,
-/*004e*/ 0x1008041bU,
-/*004f*/ 0xffffffffU,
-/*0050*/ 0x1806041bU,
-/*0051*/ 0x0003041cU,
-/*0052*/ 0x080b041cU,
-/*0053*/ 0x1804041cU,
-/*0054*/ 0x0004041dU,
-/*0055*/ 0x0804041dU,
-/*0056*/ 0x1001041dU,
-/*0057*/ 0xffffffffU,
-/*0058*/ 0x0009041eU,
-/*0059*/ 0x0020041fU,
-/*005a*/ 0x00200420U,
-/*005b*/ 0x00200421U,
-/*005c*/ 0x00200422U,
-/*005d*/ 0x00100423U,
-/*005e*/ 0xffffffffU,
-/*005f*/ 0x10010423U,
-/*0060*/ 0x18060423U,
-/*0061*/ 0x00080424U,
-/*0062*/ 0x00200425U,
-/*0063*/ 0x00100426U,
-/*0064*/ 0x100a0426U,
-/*0065*/ 0x00060427U,
-/*0066*/ 0x08070427U,
-/*0067*/ 0x10080427U,
-/*0068*/ 0x18080427U,
-/*0069*/ 0x000a0428U,
-/*006a*/ 0x10070428U,
-/*006b*/ 0x18080428U,
-/*006c*/ 0x00080429U,
-/*006d*/ 0x08030429U,
-/*006e*/ 0x100a0429U,
-/*006f*/ 0x000a042aU,
-/*0070*/ 0x0011042bU,
-/*0071*/ 0x0009042cU,
-/*0072*/ 0x1009042cU,
-/*0073*/ 0x0010042dU,
-/*0074*/ 0x100e042dU,
-/*0075*/ 0x000e042eU,
-/*0076*/ 0x0012042fU,
-/*0077*/ 0x000a0430U,
-/*0078*/ 0x100a0430U,
-/*0079*/ 0x00020431U,
-/*007a*/ 0x00200432U,
-/*007b*/ 0x000b0433U,
-/*007c*/ 0x100b0433U,
-/*007d*/ 0x00200434U,
-/*007e*/ 0x00120435U,
-/*007f*/ 0x00200436U,
-/*0080*/ 0x00200437U,
-/*0081*/ 0x00080438U,
-/*0082*/ 0x08010438U,
-/*0083*/ 0x10010438U,
-/*0084*/ 0x18010438U,
-/*0085*/ 0x00080439U,
-/*0086*/ 0x080c0439U,
-/*0087*/ 0x000c043aU,
-/*0088*/ 0x100c043aU,
-/*0089*/ 0x000c043bU,
-/*008a*/ 0x100c043bU,
-/*008b*/ 0x000c043cU,
-/*008c*/ 0x100c043cU,
-/*008d*/ 0x000c043dU,
-/*008e*/ 0x100c043dU,
-/*008f*/ 0x000c043eU,
-/*0090*/ 0x100c043eU,
-/*0091*/ 0x000b043fU,
-/*0092*/ 0x1009043fU,
-/*0093*/ 0x00010440U,
-/*0094*/ 0x000b0441U,
-/*0095*/ 0x100b0441U,
-/*0096*/ 0x000b0442U,
-/*0097*/ 0x100b0442U,
-/*0098*/ 0x000b0443U,
-/*0099*/ 0x100b0443U,
-/*009a*/ 0x000b0444U,
-/*009b*/ 0x100b0444U,
-/*009c*/ 0x000b0445U,
-/*009d*/ 0x100a0445U,
-/*009e*/ 0x00020446U,
-/*009f*/ 0x080a0446U,
-/*00a0*/ 0x000a0447U,
-/*00a1*/ 0x100a0447U,
-/*00a2*/ 0x000a0448U,
-/*00a3*/ 0x100a0448U,
-/*00a4*/ 0x000a0449U,
-/*00a5*/ 0x100a0449U,
-/*00a6*/ 0x000a044aU,
-/*00a7*/ 0x100a044aU,
-/*00a8*/ 0x000a044bU,
-/*00a9*/ 0x100a044bU,
-/*00aa*/ 0x000a044cU,
-/*00ab*/ 0x100a044cU,
-/*00ac*/ 0x000a044dU,
-/*00ad*/ 0x100a044dU,
-/*00ae*/ 0x000a044eU,
-/*00af*/ 0x100a044eU,
-/*00b0*/ 0x000a044fU,
-/*00b1*/ 0x100a044fU,
-/*00b2*/ 0x000a0450U,
-/*00b3*/ 0x100a0450U,
-/*00b4*/ 0x000a0451U,
-/*00b5*/ 0x100a0451U,
-/*00b6*/ 0x000a0452U,
-/*00b7*/ 0x100a0452U,
-/*00b8*/ 0x000a0453U,
-/*00b9*/ 0x100a0453U,
-/*00ba*/ 0x000a0454U,
-/*00bb*/ 0x10040454U,
-/*00bc*/ 0x18030454U,
-/*00bd*/ 0x000a0455U,
-/*00be*/ 0x100a0455U,
-/*00bf*/ 0x00010456U,
-/*00c0*/ 0x080a0456U,
-/*00c1*/ 0x18040456U,
-/*00c2*/ 0x000b0457U,
-/*00c3*/ 0x100a0457U,
-/*00c4*/ 0x00030458U,
-/*00c5*/ 0x00080459U,
-/*00c6*/ 0x08080459U,
-/*00c7*/ 0x10080459U,
-/*00c8*/ 0x18080459U,
-/*00c9*/ 0x0008045aU,
-/*00ca*/ 0xffffffffU,
-/*00cb*/ 0x0808045aU,
-/*00cc*/ 0x1001045aU,
-/*00cd*/ 0x1808045aU,
-/*00ce*/ 0x0008045bU,
-/*00cf*/ 0x0802045bU,
-/*00d0*/ 0x1002045bU,
-/*00d1*/ 0x1805045bU,
-/*00d2*/ 0x0005045cU,
-/*00d3*/ 0xffffffffU,
-/*00d4*/ 0x0804045cU,
-/*00d5*/ 0x100a045cU,
-/*00d6*/ 0x0006045dU,
-/*00d7*/ 0x0808045dU,
-/*00d8*/ 0x1008045dU,
-/*00d9*/ 0x1804045dU,
-/*00da*/ 0x0004045eU,
-/*00db*/ 0x0805045eU,
-/*00dc*/ 0x1004045eU,
-/*00dd*/ 0x1805045eU,
-/*00de*/ 0x000a045fU,
-/*00df*/ 0x100a045fU,
-/*00e0*/ 0x00080460U,
-/*00e1*/ 0xffffffffU,
-/*00e2*/ 0x08040460U,
-/*00e3*/ 0xffffffffU,
-/*00e4*/ 0xffffffffU,
-/*00e5*/ 0x00050600U,
-/*00e6*/ 0x08050600U,
-/*00e7*/ 0x10050600U,
-/*00e8*/ 0x18050600U,
-/*00e9*/ 0x00050601U,
-/*00ea*/ 0x08050601U,
-/*00eb*/ 0x100b0601U,
-/*00ec*/ 0x00010602U,
-/*00ed*/ 0x08030602U,
-/*00ee*/ 0x00200603U,
-/*00ef*/ 0x00100604U,
-/*00f0*/ 0x10040604U,
-/*00f1*/ 0x000a0605U,
-/*00f2*/ 0x10090605U,
-/*00f3*/ 0x00080606U,
-/*00f4*/ 0x08030606U,
-/*00f5*/ 0x10030606U,
-/*00f6*/ 0x18010606U,
-/*00f7*/ 0x00010607U,
-/*00f8*/ 0x08070607U,
-/*00f9*/ 0x10070607U,
-/*00fa*/ 0x18050607U,
-/*00fb*/ 0x00010608U,
-/*00fc*/ 0x08020608U,
-/*00fd*/ 0x10030608U,
-/*00fe*/ 0x18010608U,
-/*00ff*/ 0x000f0609U,
-/*0100*/ 0x0020060aU,
-/*0101*/ 0x0020060bU,
-/*0102*/ 0x000b060cU,
-/*0103*/ 0x100b060cU,
-/*0104*/ 0x000b060dU,
-/*0105*/ 0x0018060eU,
-/*0106*/ 0x0018060fU,
-/*0107*/ 0xffffffffU,
-/*0108*/ 0xffffffffU,
-/*0109*/ 0xffffffffU,
-/*010a*/ 0xffffffffU,
-/*010b*/ 0xffffffffU,
-/*010c*/ 0x1802060fU,
-/*010d*/ 0x00020610U,
-/*010e*/ 0x08040610U,
-/*010f*/ 0x10040610U,
-/*0110*/ 0x18010610U,
-/*0111*/ 0x00010611U,
-/*0112*/ 0x08010611U,
-/*0113*/ 0x10030611U,
-/*0114*/ 0x00200612U,
-/*0115*/ 0x00200613U,
-/*0116*/ 0xffffffffU,
-/*0117*/ 0x00140614U,
-/*0118*/ 0x00140615U,
-/*0119*/ 0x00140616U,
-/*011a*/ 0x00140617U,
-/*011b*/ 0x00140618U,
-/*011c*/ 0x00140619U,
-/*011d*/ 0x0014061aU,
-/*011e*/ 0x0014061bU,
-/*011f*/ 0x0018061cU,
-/*0120*/ 0x000a061dU,
-/*0121*/ 0x1006061dU,
-/*0122*/ 0x1806061dU,
-/*0123*/ 0x0006061eU,
-/*0124*/ 0xffffffffU,
-/*0125*/ 0x0806061eU,
-/*0126*/ 0x0008061fU,
-/*0127*/ 0x080b061fU,
-/*0128*/ 0x000b0620U,
-/*0129*/ 0x100b0620U,
-/*012a*/ 0x000b0621U,
-/*012b*/ 0x100b0621U,
-/*012c*/ 0x000b0622U,
-/*012d*/ 0x10040622U,
-/*012e*/ 0x000a0623U,
-/*012f*/ 0x10060623U,
-/*0130*/ 0x18080623U,
-/*0131*/ 0x00080624U,
-/*0132*/ 0x08040624U,
-/*0133*/ 0x00020680U,
-/*0134*/ 0x00010681U,
-/*0135*/ 0x08010681U,
-/*0136*/ 0x10020681U,
-/*0137*/ 0x18050681U,
-/*0138*/ 0x00050682U,
-/*0139*/ 0x08050682U,
-/*013a*/ 0x10050682U,
-/*013b*/ 0x000b0683U,
-/*013c*/ 0x10050683U,
-/*013d*/ 0x18010683U,
-/*013e*/ 0x00010684U,
-/*013f*/ 0xffffffffU,
-/*0140*/ 0x08010684U,
-/*0141*/ 0x10010684U,
-/*0142*/ 0x18040684U,
-/*0143*/ 0x000b0685U,
-/*0144*/ 0x100b0685U,
-/*0145*/ 0x000b0686U,
-/*0146*/ 0x10040686U,
-/*0147*/ 0x000b0687U,
-/*0148*/ 0x10040687U,
-/*0149*/ 0x18010687U,
-/*014a*/ 0x00010688U,
-/*014b*/ 0x08010688U,
-/*014c*/ 0x00200689U,
-/*014d*/ 0x0020068aU,
-/*014e*/ 0x0008068bU,
-/*014f*/ 0x080a068bU,
-/*0150*/ 0x1805068bU,
-/*0151*/ 0x000a068cU,
-/*0152*/ 0x1003068cU,
-/*0153*/ 0x1803068cU,
-/*0154*/ 0x0001068dU,
-/*0155*/ 0x0802068dU,
-/*0156*/ 0x1001068dU,
-/*0157*/ 0x1801068dU,
-/*0158*/ 0x0001068eU,
-/*0159*/ 0x0802068eU,
-/*015a*/ 0x1001068eU,
-/*015b*/ 0x0004068fU,
-/*015c*/ 0x0804068fU,
-/*015d*/ 0x1004068fU,
-/*015e*/ 0x1804068fU,
-/*015f*/ 0x00010690U,
-/*0160*/ 0x08010690U,
-/*0161*/ 0x10010690U,
-/*0162*/ 0x00200691U,
-/*0163*/ 0x00200692U,
-/*0164*/ 0x00200693U,
-/*0165*/ 0x00200694U,
-/*0166*/ 0xffffffffU,
-/*0167*/ 0x1801068eU,
-/*0168*/ 0x000d0696U,
-/*0169*/ 0x100d0696U,
-/*016a*/ 0x000d0697U,
-/*016b*/ 0x00050698U,
-/*016c*/ 0x00010699U,
-/*016d*/ 0x080e0699U,
-/*016e*/ 0x000e069aU,
-/*016f*/ 0x100e069aU,
-/*0170*/ 0x000e069bU,
-/*0171*/ 0x100e069bU,
-/*0172*/ 0x0004069cU,
-/*0173*/ 0x0804069cU,
-/*0174*/ 0x1004069cU,
-/*0175*/ 0x1804069cU,
-/*0176*/ 0x0004069dU,
-/*0177*/ 0x080b069dU,
-/*0178*/ 0x000b069eU,
-/*0179*/ 0x100b069eU,
-/*017a*/ 0x000b069fU,
-/*017b*/ 0xffffffffU,
-/*017c*/ 0xffffffffU,
-/*017d*/ 0xffffffffU,
-/*017e*/ 0xffffffffU,
-/*017f*/ 0x000d06a0U,
-/*0180*/ 0x100d06a0U,
-/*0181*/ 0x000d06a1U,
-/*0182*/ 0x101006a1U,
-/*0183*/ 0x00080695U,
-/*0184*/ 0x08080695U,
-/*0185*/ 0x001006a2U,
-/*0186*/ 0x101006a2U,
-/*0187*/ 0x001006a3U,
-/*0188*/ 0x101006a3U,
-/*0189*/ 0x001006a4U,
-/*018a*/ 0x100306a4U,
-/*018b*/ 0x180406a4U,
-/*018c*/ 0x000106a5U,
-/*018d*/ 0x080806a5U,
-/*018e*/ 0x100106a5U,
-/*018f*/ 0x180506a5U,
-/*0190*/ 0x000106a6U,
-/*0191*/ 0x081406a6U,
-/*0192*/ 0x000a06a7U,
-/*0193*/ 0x100c06a7U,
-/*0194*/ 0x001206a8U,
-/*0195*/ 0x001406a9U,
-/*0196*/ 0x001206aaU,
-/*0197*/ 0x001106abU,
-/*0198*/ 0x001106acU,
-/*0199*/ 0x001206adU,
-/*019a*/ 0x001206aeU,
-/*019b*/ 0x001206afU,
-/*019c*/ 0x001206b0U,
-/*019d*/ 0x001206b1U,
-/*019e*/ 0x001206b2U,
-/*019f*/ 0x001206b3U,
-/*01a0*/ 0x001206b4U,
-/*01a1*/ 0x001206b5U,
-/*01a2*/ 0x001206b6U,
-/*01a3*/ 0x000e06b7U,
-/*01a4*/ 0x100d06b7U,
-/*01a5*/ 0x002006b8U,
-/*01a6*/ 0x001706b9U,
-/*01a7*/ 0x000906baU,
-/*01a8*/ 0x100106baU,
-/*01a9*/ 0x180106baU,
-/*01aa*/ 0x002006bbU,
-/*01ab*/ 0x000806bcU,
-/*01ac*/ 0x080306bcU,
-/*01ad*/ 0x100306bcU,
-/*01ae*/ 0x001806bdU,
-/*01af*/ 0x001806beU,
-/*01b0*/ 0x180706beU,
-/*01b1*/ 0x000506bfU,
-/*01b2*/ 0x080806bfU,
-/*01b3*/ 0x100806bfU,
-/*01b4*/ 0x180806bfU,
-/*01b5*/ 0x000106c0U,
-/*01b6*/ 0x080106c0U,
-/*01b7*/ 0x002006c1U,
-/*01b8*/ 0xffffffffU,
-/*01b9*/ 0xffffffffU,
-/*01ba*/ 0xffffffffU,
-/*01bb*/ 0xffffffffU,
-/*01bc*/ 0xffffffffU,
-/*01bd*/ 0xffffffffU,
-/*01be*/ 0xffffffffU,
-/*01bf*/ 0x001006c2U,
-/*01c0*/ 0x100106c2U,
-/*01c1*/ 0x180106c2U,
-/*01c2*/ 0x000206c3U,
-/*01c3*/ 0x080406c3U,
-/*01c4*/ 0x100906c3U,
-/*01c5*/ 0x000706c4U,
-/*01c6*/ 0x080406c4U,
-/*01c7*/ 0x002006c5U,
-/*01c8*/ 0x000106c6U,
-/*01c9*/ 0x080206c6U,
-/*01ca*/ 0x100606c6U,
-/*01cb*/ 0x001006c7U,
-/*01cc*/ 0x100106c7U,
-/*01cd*/ 0x002006c8U,
-/*01ce*/ 0x000806c9U,
-/*01cf*/ 0x080106c9U,
-/*01d0*/ 0x100506c9U,
-/*01d1*/ 0xffffffffU,
-/*01d2*/ 0x180206c9U,
-/*01d3*/ 0x000106caU,
-/*01d4*/ 0x002006cbU,
-/*01d5*/ 0x000b06ccU,
-/*01d6*/ 0x100106ccU,
-/*01d7*/ 0x180306ccU,
-/*01d8*/ 0x000806cdU,
-/*01d9*/ 0x080206cdU,
-/*01da*/ 0x100c06cdU,
-/*01db*/ 0x000406ceU,
-/*01dc*/ 0x080106ceU,
-/*01dd*/ 0xffffffffU,
-/*01de*/ 0x00010200U,
-/*01df*/ 0x08040200U,
-/*01e0*/ 0x10100200U,
-/*01e1*/ 0x00010201U,
-/*01e2*/ 0x08010201U,
-/*01e3*/ 0x10010201U,
-/*01e4*/ 0xffffffffU,
-/*01e5*/ 0x00100202U,
-/*01e6*/ 0x10080202U,
-/*01e7*/ 0xffffffffU,
-/*01e8*/ 0xffffffffU,
-/*01e9*/ 0xffffffffU,
-/*01ea*/ 0xffffffffU,
-/*01eb*/ 0xffffffffU,
-/*01ec*/ 0xffffffffU,
-/*01ed*/ 0xffffffffU,
-/*01ee*/ 0xffffffffU,
-/*01ef*/ 0x00200203U,
-/*01f0*/ 0x00100204U,
-/*01f1*/ 0x00200205U,
-/*01f2*/ 0x00100206U,
-/*01f3*/ 0x00200207U,
-/*01f4*/ 0x00100208U,
-/*01f5*/ 0x00140209U,
-/*01f6*/ 0x0020020aU,
-/*01f7*/ 0x0020020bU,
-/*01f8*/ 0x0020020cU,
-/*01f9*/ 0x0020020dU,
-/*01fa*/ 0x0014020eU,
-/*01fb*/ 0x0020020fU,
-/*01fc*/ 0x00200210U,
-/*01fd*/ 0x00200211U,
-/*01fe*/ 0x00200212U,
-/*01ff*/ 0x00140213U,
-/*0200*/ 0x00200214U,
-/*0201*/ 0x00200215U,
-/*0202*/ 0x00200216U,
-/*0203*/ 0x00200217U,
-/*0204*/ 0x00090218U,
-/*0205*/ 0x10010218U,
-/*0206*/ 0x00200219U,
-/*0207*/ 0x0005021aU,
-/*0208*/ 0x0801021aU,
-/*0209*/ 0x1008021aU,
-/*020a*/ 0x1808021aU,
-/*020b*/ 0x001c021bU,
-/*020c*/ 0x001c021cU,
-/*020d*/ 0x001c021dU,
-/*020e*/ 0x001c021eU,
-/*020f*/ 0x001c021fU,
-/*0210*/ 0x001c0220U,
-/*0211*/ 0x001c0221U,
-/*0212*/ 0x001c0222U,
-/*0213*/ 0x001c0223U,
-/*0214*/ 0x001c0224U,
-/*0215*/ 0x001c0225U,
-/*0216*/ 0x001c0226U,
-/*0217*/ 0x001c0227U,
-/*0218*/ 0x001c0228U,
-/*0219*/ 0x001c0229U,
-/*021a*/ 0x001c022aU,
-/*021b*/ 0x0001022bU,
-/*021c*/ 0x0801022bU,
-/*021d*/ 0x1001022bU,
-/*021e*/ 0x1804022bU,
-/*021f*/ 0x0008022cU,
-/*0220*/ 0x0808022cU,
-/*0221*/ 0x1008022cU,
-/*0222*/ 0x1804022cU,
-/*0223*/ 0x0007022dU,
-/*0224*/ 0xffffffffU,
-/*0225*/ 0x0807022dU,
-/*0226*/ 0x1007022dU,
-/*0227*/ 0xffffffffU,
-/*0228*/ 0x1807022dU,
-/*0229*/ 0x0007022eU,
-/*022a*/ 0xffffffffU,
-/*022b*/ 0x0807022eU,
-/*022c*/ 0x1002022eU,
-/*022d*/ 0x1801022eU,
-/*022e*/ 0x0001022fU,
-/*022f*/ 0x080a022fU,
-/*0230*/ 0x00140230U,
-/*0231*/ 0x000a0231U,
-/*0232*/ 0x00140232U,
-/*0233*/ 0x000a0233U,
-/*0234*/ 0x00140234U,
-/*0235*/ 0x18010234U,
-/*0236*/ 0x00100235U,
-/*0237*/ 0x10050235U,
-/*0238*/ 0x18010235U,
-/*0239*/ 0x00010236U,
-/*023a*/ 0x08010236U,
-/*023b*/ 0x10010236U,
-/*023c*/ 0x18010236U,
-/*023d*/ 0x00010237U,
-/*023e*/ 0x08010237U,
-/*023f*/ 0x10020237U,
-/*0240*/ 0x18020237U,
-/*0241*/ 0x00020238U,
-/*0242*/ 0x08020238U,
-/*0243*/ 0x10020238U,
-/*0244*/ 0x18030238U,
-/*0245*/ 0x00010239U,
-/*0246*/ 0x08010239U,
-/*0247*/ 0x10010239U,
-/*0248*/ 0x18010239U,
-/*0249*/ 0xffffffffU,
-/*024a*/ 0x0002023aU,
-/*024b*/ 0x0801023aU,
-/*024c*/ 0x1001023aU,
-/*024d*/ 0xffffffffU,
-/*024e*/ 0x1802023aU,
-/*024f*/ 0x0001023bU,
-/*0250*/ 0x0801023bU,
-/*0251*/ 0xffffffffU,
-/*0252*/ 0x1002023bU,
-/*0253*/ 0x1801023bU,
-/*0254*/ 0x0001023cU,
-/*0255*/ 0xffffffffU,
-/*0256*/ 0x0802023cU,
-/*0257*/ 0x1007023cU,
-/*0258*/ 0x1801023cU,
-/*0259*/ 0x0001023dU,
-/*025a*/ 0x0801023dU,
-/*025b*/ 0x1001023dU,
-/*025c*/ 0x1801023dU,
-/*025d*/ 0x0001023eU,
-/*025e*/ 0x0801023eU,
-/*025f*/ 0x1001023eU,
-/*0260*/ 0x1804023eU,
-/*0261*/ 0x0004023fU,
-/*0262*/ 0x0804023fU,
-/*0263*/ 0x1001023fU,
-/*0264*/ 0x1802023fU,
-/*0265*/ 0x00060240U,
-/*0266*/ 0x08060240U,
-/*0267*/ 0x10020240U,
-/*0268*/ 0x18020240U,
-/*0269*/ 0x00020241U,
-/*026a*/ 0xffffffffU,
-/*026b*/ 0x08100241U,
-/*026c*/ 0x18010241U,
-/*026d*/ 0x00010242U,
-/*026e*/ 0x08010242U,
-/*026f*/ 0x10040242U,
-/*0270*/ 0x18010242U,
-/*0271*/ 0x00040243U,
-/*0272*/ 0x08020243U,
-/*0273*/ 0x10080243U,
-/*0274*/ 0xffffffffU,
-/*0275*/ 0xffffffffU,
-/*0276*/ 0xffffffffU,
-/*0277*/ 0x000a0244U,
-/*0278*/ 0x00200245U,
-/*0279*/ 0x00200246U,
-/*027a*/ 0x00050247U,
-/*027b*/ 0x08010247U,
-/*027c*/ 0x10050247U,
-/*027d*/ 0x18080247U,
-/*027e*/ 0x00010248U,
-/*027f*/ 0x08080248U,
-/*0280*/ 0x10010248U,
-/*0281*/ 0x18080248U,
-/*0282*/ 0x00010249U,
-/*0283*/ 0x08040249U,
-/*0284*/ 0x10040249U,
-/*0285*/ 0x18040249U,
-/*0286*/ 0x0004024aU,
-/*0287*/ 0x0804024aU,
-/*0288*/ 0x1004024aU,
-/*0289*/ 0x1804024aU,
-/*028a*/ 0x0004024bU,
-/*028b*/ 0x0804024bU,
-/*028c*/ 0x1004024bU,
-/*028d*/ 0x1801024bU,
-/*028e*/ 0x0004024cU,
-/*028f*/ 0x0804024cU,
-/*0290*/ 0x1004024cU,
-/*0291*/ 0x1804024cU,
-/*0292*/ 0x0004024dU,
-/*0293*/ 0x0804024dU,
-/*0294*/ 0x1006024dU,
-/*0295*/ 0x1806024dU,
-/*0296*/ 0x0006024eU,
-/*0297*/ 0x0806024eU,
-/*0298*/ 0x1006024eU,
-/*0299*/ 0x1806024eU,
-/*029a*/ 0xffffffffU,
-/*029b*/ 0x0001024fU,
-/*029c*/ 0x0801024fU,
-/*029d*/ 0x1002024fU,
-/*029e*/ 0xffffffffU,
-/*029f*/ 0xffffffffU,
-/*02a0*/ 0xffffffffU,
-/*02a1*/ 0xffffffffU,
-/*02a2*/ 0xffffffffU,
-/*02a3*/ 0xffffffffU,
-/*02a4*/ 0xffffffffU,
-/*02a5*/ 0xffffffffU,
-/*02a6*/ 0x1804024fU,
-/*02a7*/ 0x00040250U,
-/*02a8*/ 0x08010250U,
-/*02a9*/ 0x10010250U,
-/*02aa*/ 0x18010250U,
-/*02ab*/ 0x00010251U,
-/*02ac*/ 0x08010251U,
-/*02ad*/ 0x10010251U,
-/*02ae*/ 0x18010251U,
-/*02af*/ 0x00010252U,
-/*02b0*/ 0x08010252U,
-/*02b1*/ 0x10040252U,
-/*02b2*/ 0x18040252U,
-/*02b3*/ 0x000a0253U,
-/*02b4*/ 0x00200254U,
-/*02b5*/ 0x00040255U,
-/*02b6*/ 0x08080255U,
-/*02b7*/ 0x10020255U,
-/*02b8*/ 0x18020255U,
-/*02b9*/ 0x00020256U,
-/*02ba*/ 0x08020256U,
-/*02bb*/ 0x10020256U,
-/*02bc*/ 0x18020256U,
-/*02bd*/ 0xffffffffU,
-/*02be*/ 0xffffffffU,
-/*02bf*/ 0x00200257U,
-/*02c0*/ 0x00020258U,
-/*02c1*/ 0x08100258U,
-/*02c2*/ 0x00100259U,
-/*02c3*/ 0x10040259U,
-/*02c4*/ 0x18040259U,
-/*02c5*/ 0x0005025aU,
-/*02c6*/ 0x0805025aU,
-/*02c7*/ 0x0020025bU,
-/*02c8*/ 0x0020025cU,
-/*02c9*/ 0x0020025dU,
-/*02ca*/ 0x0020025eU,
-/*02cb*/ 0x0001025fU,
-/*02cc*/ 0x0801025fU,
-/*02cd*/ 0x1007025fU,
-/*02ce*/ 0x1807025fU,
-/*02cf*/ 0x00070260U,
-/*02d0*/ 0x08070260U,
-/*02d1*/ 0x10070260U,
-/*02d2*/ 0x18070260U,
-/*02d3*/ 0x00070261U,
-/*02d4*/ 0x08070261U,
-/*02d5*/ 0x10070261U,
-/*02d6*/ 0x18070261U,
-/*02d7*/ 0x00070262U,
-/*02d8*/ 0x08070262U,
-/*02d9*/ 0x10070262U,
-/*02da*/ 0x18070262U,
-/*02db*/ 0x00030263U,
-/*02dc*/ 0x08030263U,
-/*02dd*/ 0x10030263U,
-/*02de*/ 0xffffffffU,
-/*02df*/ 0x18010263U,
-/*02e0*/ 0x00020264U,
-/*02e1*/ 0x08010264U,
-/*02e2*/ 0x10040264U,
-/*02e3*/ 0x18020264U,
-/*02e4*/ 0x00010265U,
-/*02e5*/ 0x08010265U,
-/*02e6*/ 0x10010265U,
-/*02e7*/ 0x18010265U,
-/*02e8*/ 0x00040266U,
-/*02e9*/ 0x08080266U,
-/*02ea*/ 0x100a0266U,
-/*02eb*/ 0x000a0267U,
-/*02ec*/ 0x100a0267U,
-/*02ed*/ 0x000a0268U,
-/*02ee*/ 0x100a0268U,
-/*02ef*/ 0x000a0269U,
-/*02f0*/ 0x0020026aU,
-/*02f1*/ 0x0020026bU,
-/*02f2*/ 0x0001026cU,
-/*02f3*/ 0x0802026cU,
-/*02f4*/ 0x1002026cU,
-/*02f5*/ 0x1802026cU,
-/*02f6*/ 0xffffffffU,
-/*02f7*/ 0x0002026dU,
-/*02f8*/ 0x0810026dU,
-/*02f9*/ 0x1805026dU,
-/*02fa*/ 0x0006026eU,
-/*02fb*/ 0x0805026eU,
-/*02fc*/ 0x1005026eU,
-/*02fd*/ 0x000e026fU,
-/*02fe*/ 0x1005026fU,
-/*02ff*/ 0x000e0270U,
-/*0300*/ 0x10050270U,
-/*0301*/ 0x000e0271U,
-/*0302*/ 0x10050271U,
-/*0303*/ 0x18010271U,
-/*0304*/ 0x00050272U,
-/*0305*/ 0x08050272U,
-/*0306*/ 0x100a0272U,
-/*0307*/ 0x000a0273U,
-/*0308*/ 0x10050273U,
-/*0309*/ 0x18050273U,
-/*030a*/ 0x000a0274U,
-/*030b*/ 0x100a0274U,
-/*030c*/ 0x00050275U,
-/*030d*/ 0x08050275U,
-/*030e*/ 0x100a0275U,
-/*030f*/ 0x000a0276U,
-/*0310*/ 0xffffffffU,
-/*0311*/ 0xffffffffU,
-/*0312*/ 0xffffffffU,
-/*0313*/ 0xffffffffU,
-/*0314*/ 0xffffffffU,
-/*0315*/ 0xffffffffU,
-/*0316*/ 0x10070276U,
-/*0317*/ 0x18070276U,
-/*0318*/ 0x00040277U,
-/*0319*/ 0x08040277U,
-/*031a*/ 0xffffffffU,
-/*031b*/ 0xffffffffU,
-/*031c*/ 0xffffffffU,
-/*031d*/ 0x10040277U,
-/*031e*/ 0x18080277U,
-/*031f*/ 0x00080278U,
-/*0320*/ 0x08040278U,
-/*0321*/ 0xffffffffU,
-/*0322*/ 0xffffffffU,
-/*0323*/ 0xffffffffU,
-/*0324*/ 0x10040278U,
-/*0325*/ 0xffffffffU,
-/*0326*/ 0xffffffffU,
-/*0327*/ 0xffffffffU,
-/*0328*/ 0x18040278U,
-/*0329*/ 0xffffffffU,
-/*032a*/ 0xffffffffU,
-/*032b*/ 0xffffffffU,
-/*032c*/ 0x00040279U,
-/*032d*/ 0x08050279U,
-/*032e*/ 0x10070279U,
-/*032f*/ 0x18080279U,
-/*0330*/ 0x0010027aU,
-/*0331*/ 0x1008027aU,
-/*0332*/ 0x0010027bU,
-/*0333*/ 0x1008027bU,
-/*0334*/ 0x0010027cU,
-/*0335*/ 0x1008027cU,
-/*0336*/ 0x1808027cU,
-/*0337*/ 0x0001027dU,
-/*0338*/ 0x0801027dU,
-/*0339*/ 0x1006027dU,
-/*033a*/ 0x1806027dU,
-/*033b*/ 0x0006027eU,
-/*033c*/ 0x0801027eU,
-/*033d*/ 0x1001027eU,
-/*033e*/ 0x1803027eU,
-/*033f*/ 0x000a027fU,
-/*0340*/ 0x100a027fU,
-/*0341*/ 0x000a0280U,
-/*0342*/ 0xffffffffU,
-/*0343*/ 0x100a0280U,
-/*0344*/ 0x00040281U,
-/*0345*/ 0x08010281U,
-/*0346*/ 0x10040281U,
-/*0347*/ 0xffffffffU,
-/*0348*/ 0xffffffffU,
-/*0349*/ 0xffffffffU,
-/*034a*/ 0xffffffffU,
-/*034b*/ 0xffffffffU,
-/*034c*/ 0xffffffffU,
-/*034d*/ 0x18070281U,
-/*034e*/ 0x00070282U,
-/*034f*/ 0x08050282U,
-/*0350*/ 0x10050282U,
-/*0351*/ 0xffffffffU,
-/*0352*/ 0xffffffffU,
-/*0353*/ 0xffffffffU,
-/*0354*/ 0x18040282U,
-/*0355*/ 0x00010283U,
-/*0356*/ 0x08010283U,
-/*0357*/ 0x10020283U,
-/*0358*/ 0x18080283U,
-/*0359*/ 0x00200284U,
-/*035a*/ 0x00200285U,
-/*035b*/ 0x00100286U,
-/*035c*/ 0x10020286U,
-/*035d*/ 0x18020286U,
-/*035e*/ 0x00020287U,
-/*035f*/ 0xffffffffU,
-/*0360*/ 0x08010287U,
-/*0361*/ 0x10010287U,
-/*0362*/ 0x18020287U,
-/*0363*/ 0x00080288U,
-/*0364*/ 0x08080288U,
-/*0365*/ 0x10080288U,
-/*0366*/ 0x18080288U,
-/*0367*/ 0x00080289U,
-/*0368*/ 0x08080289U,
-/*0369*/ 0xffffffffU,
-/*036a*/ 0x10080289U,
-/*036b*/ 0x18080289U,
-/*036c*/ 0x0008028aU,
-/*036d*/ 0x0808028aU,
-/*036e*/ 0x1008028aU,
-/*036f*/ 0x1808028aU,
-/*0370*/ 0xffffffffU,
-/*0371*/ 0x0008028bU,
-/*0372*/ 0x0808028bU,
-/*0373*/ 0x1008028bU,
-/*0374*/ 0x1808028bU,
-/*0375*/ 0x0008028cU,
-/*0376*/ 0x0808028cU,
-/*0377*/ 0xffffffffU,
-/*0378*/ 0x1008028cU,
-/*0379*/ 0x1808028cU,
-/*037a*/ 0x0008028dU,
-/*037b*/ 0x0808028dU,
-/*037c*/ 0x1008028dU,
-/*037d*/ 0x1808028dU,
-/*037e*/ 0x0008028eU,
-/*037f*/ 0xffffffffU,
-/*0380*/ 0x0808028eU,
-/*0381*/ 0x1008028eU,
-/*0382*/ 0x1808028eU,
-/*0383*/ 0x0008028fU,
-/*0384*/ 0x0808028fU,
-/*0385*/ 0x1008028fU,
-/*0386*/ 0xffffffffU,
-/*0387*/ 0x1808028fU,
-/*0388*/ 0x00080290U,
-/*0389*/ 0x08080290U,
-/*038a*/ 0x10080290U,
-/*038b*/ 0x18080290U,
-/*038c*/ 0x00080291U,
-/*038d*/ 0xffffffffU,
-/*038e*/ 0x08080291U,
-/*038f*/ 0x10080291U,
-/*0390*/ 0x18080291U,
-/*0391*/ 0x00080292U,
-/*0392*/ 0x08080292U,
-/*0393*/ 0x10080292U,
-/*0394*/ 0x18080292U,
-/*0395*/ 0xffffffffU,
-/*0396*/ 0x00080293U,
-/*0397*/ 0x08080293U,
-/*0398*/ 0x10080293U,
-/*0399*/ 0x18080293U,
-/*039a*/ 0x00080294U,
-/*039b*/ 0x08080294U,
-/*039c*/ 0xffffffffU,
-/*039d*/ 0x10080294U,
-/*039e*/ 0x18080294U,
-/*039f*/ 0x00080295U,
-/*03a0*/ 0x08080295U,
-/*03a1*/ 0x10080295U,
-/*03a2*/ 0x18080295U,
-/*03a3*/ 0xffffffffU,
-/*03a4*/ 0x00080296U,
-/*03a5*/ 0x08080296U,
-/*03a6*/ 0x10080296U,
-/*03a7*/ 0x18080296U,
-/*03a8*/ 0x00080297U,
-/*03a9*/ 0x08080297U,
-/*03aa*/ 0x10080297U,
-/*03ab*/ 0xffffffffU,
-/*03ac*/ 0x18080297U,
-/*03ad*/ 0x00080298U,
-/*03ae*/ 0x08080298U,
-/*03af*/ 0x10080298U,
-/*03b0*/ 0x18080298U,
-/*03b1*/ 0x00080299U,
-/*03b2*/ 0xffffffffU,
-/*03b3*/ 0x08080299U,
-/*03b4*/ 0x10080299U,
-/*03b5*/ 0x18080299U,
-/*03b6*/ 0x0008029aU,
-/*03b7*/ 0x0808029aU,
-/*03b8*/ 0x1008029aU,
-/*03b9*/ 0xffffffffU,
-/*03ba*/ 0x1808029aU,
-/*03bb*/ 0x0002029bU,
-/*03bc*/ 0x0803029bU,
-/*03bd*/ 0x100a029bU,
-/*03be*/ 0x000a029cU,
-/*03bf*/ 0x100a029cU,
-/*03c0*/ 0x0005029dU,
-/*03c1*/ 0x0808029dU,
-/*03c2*/ 0x1008029dU,
-/*03c3*/ 0x1808029dU,
-/*03c4*/ 0x0006029eU,
-/*03c5*/ 0x0806029eU,
-/*03c6*/ 0x0011029fU,
-/*03c7*/ 0x1808029fU,
-/*03c8*/ 0x000402a0U,
-/*03c9*/ 0x080602a0U,
-/*03ca*/ 0xffffffffU,
-/*03cb*/ 0x100602a0U,
-/*03cc*/ 0x180802a0U,
-/*03cd*/ 0xffffffffU,
-/*03ce*/ 0x000802a1U,
-/*03cf*/ 0x080802a1U,
-/*03d0*/ 0x100802a1U,
-/*03d1*/ 0x180602a1U,
-/*03d2*/ 0x000602a2U,
-/*03d3*/ 0x081102a2U,
-/*03d4*/ 0x000802a3U,
-/*03d5*/ 0x080402a3U,
-/*03d6*/ 0x100602a3U,
-/*03d7*/ 0xffffffffU,
-/*03d8*/ 0x180602a3U,
-/*03d9*/ 0x000802a4U,
-/*03da*/ 0xffffffffU,
-/*03db*/ 0x080802a4U,
-/*03dc*/ 0x100802a4U,
-/*03dd*/ 0x180802a4U,
-/*03de*/ 0x000602a5U,
-/*03df*/ 0x080602a5U,
-/*03e0*/ 0x001102a6U,
-/*03e1*/ 0x180802a6U,
-/*03e2*/ 0x000402a7U,
-/*03e3*/ 0x080602a7U,
-/*03e4*/ 0xffffffffU,
-/*03e5*/ 0x100602a7U,
-/*03e6*/ 0x180802a7U,
-/*03e7*/ 0xffffffffU,
-/*03e8*/ 0x000402a8U,
-/*03e9*/ 0x080402a8U,
-/*03ea*/ 0x100402a8U,
-/*03eb*/ 0x180402a8U,
-/*03ec*/ 0x000402a9U,
-/*03ed*/ 0x080402a9U,
-/*03ee*/ 0x100402a9U,
-/*03ef*/ 0x180402a9U,
-/*03f0*/ 0x000402aaU,
-/*03f1*/ 0x080402aaU,
-/*03f2*/ 0x100402aaU,
-/*03f3*/ 0x180402aaU,
-/*03f4*/ 0x000402abU,
-/*03f5*/ 0x080402abU,
-/*03f6*/ 0x100402abU,
-/*03f7*/ 0x180402abU,
-/*03f8*/ 0x000402acU,
-/*03f9*/ 0x080402acU,
-/*03fa*/ 0x100402acU,
-/*03fb*/ 0x180402acU,
-/*03fc*/ 0x001202adU,
-/*03fd*/ 0x001102aeU,
-/*03fe*/ 0x001202afU,
-/*03ff*/ 0x002002b0U,
-/*0400*/ 0x002002b1U,
-/*0401*/ 0x002002b2U,
-/*0402*/ 0x002002b3U,
-/*0403*/ 0x002002b4U,
-/*0404*/ 0x002002b5U,
-/*0405*/ 0x002002b6U,
-/*0406*/ 0x002002b7U,
-/*0407*/ 0x002002b8U,
-/*0408*/ 0x000202b9U,
-/*0409*/ 0x080502b9U,
-/*040a*/ 0x100502b9U,
-/*040b*/ 0x180102b9U,
-/*040c*/ 0x000402baU,
-/*040d*/ 0x080402baU,
-/*040e*/ 0x100402baU,
-/*040f*/ 0x180402baU,
-/*0410*/ 0x000402bbU,
-/*0411*/ 0x080402bbU,
-/*0412*/ 0x100402bbU,
-/*0413*/ 0x180402bbU,
-/*0414*/ 0xffffffffU,
-/*0415*/ 0xffffffffU,
-/*0416*/ 0xffffffffU,
-/*0417*/ 0xffffffffU,
-/*0418*/ 0xffffffffU,
-/*0419*/ 0xffffffffU,
-/*041a*/ 0x000402bcU,
-/*041b*/ 0x080402bcU,
-/*041c*/ 0x100402bcU,
-/*041d*/ 0x180402bcU,
-/*041e*/ 0x000402bdU,
-/*041f*/ 0x080402bdU,
-/*0420*/ 0x100402bdU,
-/*0421*/ 0x180402bdU,
-/*0422*/ 0x000102beU,
-/*0423*/ 0x080202beU,
-/*0424*/ 0x100202beU,
-/*0425*/ 0x180202beU,
-/*0426*/ 0x000202bfU,
-/*0427*/ 0x080102bfU,
-/*0428*/ 0x100402bfU,
-/*0429*/ 0x001002c0U,
-/*042a*/ 0x002002c1U,
-/*042b*/ 0x001002c2U,
-/*042c*/ 0x002002c3U,
-/*042d*/ 0x001002c4U,
-/*042e*/ 0x002002c5U,
-/*042f*/ 0x000702c6U,
-/*0430*/ 0x080102c6U,
-/*0431*/ 0x100202c6U,
-/*0432*/ 0x180602c6U,
-/*0433*/ 0x000102c7U,
-/*0434*/ 0x080102c7U,
-/*0435*/ 0x002002c8U,
-/*0436*/ 0x000202c9U,
-/*0437*/ 0x002002caU,
-/*0438*/ 0x002002cbU,
-/*0439*/ 0x000c02ccU,
-/*043a*/ 0x100c02ccU,
-/*043b*/ 0x002002cdU,
-/*043c*/ 0x000302ceU,
-/*043d*/ 0x002002cfU,
-/*043e*/ 0x000302d0U,
-/*043f*/ 0x002002d1U,
-/*0440*/ 0x000302d2U,
-/*0441*/ 0x002002d3U,
-/*0442*/ 0x000302d4U,
-/*0443*/ 0x002002d5U,
-/*0444*/ 0x000302d6U,
-/*0445*/ 0x002002d7U,
-/*0446*/ 0x000302d8U,
-/*0447*/ 0x002002d9U,
-/*0448*/ 0x000302daU,
-/*0449*/ 0x002002dbU,
-/*044a*/ 0x000302dcU,
-/*044b*/ 0x002002ddU,
-/*044c*/ 0x000302deU,
-/*044d*/ 0x002002dfU,
-/*044e*/ 0x000302e0U,
-/*044f*/ 0x080302e0U,
-/*0450*/ 0x100202e0U,
-/*0451*/ 0x180202e0U,
-/*0452*/ 0x002002e1U,
-/*0453*/ 0x002002e2U,
-/*0454*/ 0x002002e3U,
-/*0455*/ 0x002002e4U,
-/*0456*/ 0x000402e5U,
-/*0457*/ 0x001e02e6U,
-/*0458*/ 0x001e02e7U,
-/*0459*/ 0x001e02e8U,
-/*045a*/ 0x001e02e9U,
-/*045b*/ 0x001e02eaU,
-/*045c*/ 0x001e02ebU,
-/*045d*/ 0x001e02ecU,
-/*045e*/ 0x001e02edU,
-/*045f*/ 0x000402eeU,
-/*0460*/ 0xffffffffU,
-/*0461*/ 0xffffffffU,
-/*0462*/ 0xffffffffU,
-/*0463*/ 0xffffffffU,
-/*0464*/ 0x080402eeU,
-/*0465*/ 0x100102eeU,
-/*0466*/ 0x180802eeU,
-/*0467*/ 0x000402efU,
-/*0468*/ 0x080102efU,
-/*0469*/ 0x100802efU,
-/*046a*/ 0x180402efU,
-/*046b*/ 0x000102f0U,
-/*046c*/ 0x080802f0U,
-/*046d*/ 0x100402f0U,
-/*046e*/ 0x180102f0U,
-/*046f*/ 0x000802f1U,
-/*0470*/ 0x080402f1U,
-/*0471*/ 0x100102f1U,
-/*0472*/ 0x180802f1U,
-/*0473*/ 0x000402f2U,
-/*0474*/ 0x080102f2U,
-/*0475*/ 0x100802f2U,
-/*0476*/ 0x180402f2U,
-/*0477*/ 0x000102f3U,
-/*0478*/ 0x080802f3U,
-/*0479*/ 0x100402f3U,
-/*047a*/ 0x180102f3U,
-/*047b*/ 0x000802f4U,
-/*047c*/ 0x080802f4U,
-/*047d*/ 0x100102f4U,
-/*047e*/ 0x180502f4U,
-/*047f*/ 0xffffffffU,
-/*0480*/ 0xffffffffU,
-/*0481*/ 0xffffffffU,
-/*0482*/ 0xffffffffU,
-/*0483*/ 0xffffffffU,
-/*0484*/ 0xffffffffU,
-/*0485*/ 0xffffffffU,
-/*0486*/ 0xffffffffU,
-/*0487*/ 0xffffffffU,
-/*0488*/ 0xffffffffU,
-/*0489*/ 0xffffffffU,
-/*048a*/ 0xffffffffU,
-/*048b*/ 0xffffffffU,
-/*048c*/ 0xffffffffU,
-/*048d*/ 0xffffffffU,
-/*048e*/ 0xffffffffU,
-/*048f*/ 0xffffffffU,
-/*0490*/ 0xffffffffU,
-/*0491*/ 0xffffffffU,
-/*0492*/ 0xffffffffU,
-/*0493*/ 0xffffffffU,
-/*0494*/ 0xffffffffU,
-	 },
-	{
-/*0000*/ 0x00200800U,
-/*0001*/ 0x00040801U,
-/*0002*/ 0x080b0801U,
-/*0003*/ 0x000a0802U,
-/*0004*/ 0x10020802U,
-/*0005*/ 0x18010802U,
-/*0006*/ 0x00060803U,
-/*0007*/ 0x08060803U,
-/*0008*/ 0x10060803U,
-/*0009*/ 0x18060803U,
-/*000a*/ 0x00060804U,
-/*000b*/ 0x08060804U,
-/*000c*/ 0x10050804U,
-/*000d*/ 0x18060804U,
-/*000e*/ 0x00060805U,
-/*000f*/ 0x08040805U,
-/*0010*/ 0x10030805U,
-/*0011*/ 0x00180806U,
-/*0012*/ 0x18030806U,
-/*0013*/ 0x00180807U,
-/*0014*/ 0x18020807U,
-/*0015*/ 0x0801085eU,
-/*0016*/ 0x00020808U,
-/*0017*/ 0x08010808U,
-/*0018*/ 0x10010808U,
-/*0019*/ 0x18020808U,
-/*001a*/ 0x00050809U,
-/*001b*/ 0x08050809U,
-/*001c*/ 0x10040809U,
-/*001d*/ 0xffffffffU,
-/*001e*/ 0x18040809U,
-/*001f*/ 0x0002080aU,
-/*0020*/ 0x0805080aU,
-/*0021*/ 0x1009080aU,
-/*0022*/ 0x0001080bU,
-/*0023*/ 0x0020080cU,
-/*0024*/ 0x001c080dU,
-/*0025*/ 0x0001080eU,
-/*0026*/ 0x0807080eU,
-/*0027*/ 0x1009080eU,
-/*0028*/ 0x000a080fU,
-/*0029*/ 0x1005080fU,
-/*002a*/ 0x1801080fU,
-/*002b*/ 0x10010810U,
-/*002c*/ 0x18020810U,
-/*002d*/ 0x00090810U,
-/*002e*/ 0x00090811U,
-/*002f*/ 0x10020811U,
-/*0030*/ 0x00200812U,
-/*0031*/ 0x00010813U,
-/*0032*/ 0x08020813U,
-/*0033*/ 0x00200814U,
-/*0034*/ 0x00200815U,
-/*0035*/ 0x00200816U,
-/*0036*/ 0x00200817U,
-/*0037*/ 0xffffffffU,
-/*0038*/ 0xffffffffU,
-/*0039*/ 0xffffffffU,
-/*003a*/ 0xffffffffU,
-/*003b*/ 0x00030818U,
-/*003c*/ 0x08010818U,
-/*003d*/ 0x10040818U,
-/*003e*/ 0x18030818U,
-/*003f*/ 0x00040819U,
-/*0040*/ 0x08040819U,
-/*0041*/ 0x10040819U,
-/*0042*/ 0x18040819U,
-/*0043*/ 0x0001081aU,
-/*0044*/ 0x0801081aU,
-/*0045*/ 0x1006081aU,
-/*0046*/ 0x1804081aU,
-/*0047*/ 0x0008081bU,
-/*0048*/ 0x0806081bU,
-/*0049*/ 0x1004081bU,
-/*004a*/ 0x1806081bU,
-/*004b*/ 0x0004081cU,
-/*004c*/ 0x0802081cU,
-/*004d*/ 0x1005081cU,
-/*004e*/ 0x1808081cU,
-/*004f*/ 0xffffffffU,
-/*0050*/ 0x0006081dU,
-/*0051*/ 0x0803081dU,
-/*0052*/ 0x100b081dU,
-/*0053*/ 0x0004081eU,
-/*0054*/ 0x0804081eU,
-/*0055*/ 0x1004081eU,
-/*0056*/ 0x1801081eU,
-/*0057*/ 0xffffffffU,
-/*0058*/ 0x0009081fU,
-/*0059*/ 0x00200820U,
-/*005a*/ 0x00200821U,
-/*005b*/ 0x00200822U,
-/*005c*/ 0x00200823U,
-/*005d*/ 0x00100824U,
-/*005e*/ 0xffffffffU,
-/*005f*/ 0x10010824U,
-/*0060*/ 0x18060824U,
-/*0061*/ 0x00080825U,
-/*0062*/ 0x00200826U,
-/*0063*/ 0x00100827U,
-/*0064*/ 0x100b0827U,
-/*0065*/ 0x00070828U,
-/*0066*/ 0x08070828U,
-/*0067*/ 0x10090828U,
-/*0068*/ 0x00090829U,
-/*0069*/ 0x100b0829U,
-/*006a*/ 0x0007082aU,
-/*006b*/ 0x0808082aU,
-/*006c*/ 0x1009082aU,
-/*006d*/ 0x0003082bU,
-/*006e*/ 0x080a082bU,
-/*006f*/ 0x000a082cU,
-/*0070*/ 0x0011082dU,
-/*0071*/ 0x000a082eU,
-/*0072*/ 0x100a082eU,
-/*0073*/ 0x0010082fU,
-/*0074*/ 0x100e082fU,
-/*0075*/ 0x000e0830U,
-/*0076*/ 0x00120831U,
-/*0077*/ 0x000a0832U,
-/*0078*/ 0x100a0832U,
-/*0079*/ 0x00020833U,
-/*007a*/ 0x00200834U,
-/*007b*/ 0x000b0835U,
-/*007c*/ 0x100b0835U,
-/*007d*/ 0x00200836U,
-/*007e*/ 0x00130837U,
-/*007f*/ 0x00200838U,
-/*0080*/ 0x00200839U,
-/*0081*/ 0x0008083aU,
-/*0082*/ 0x0801083aU,
-/*0083*/ 0x1001083aU,
-/*0084*/ 0x1801083aU,
-/*0085*/ 0x0008083bU,
-/*0086*/ 0x080c083bU,
-/*0087*/ 0x000c083cU,
-/*0088*/ 0x100c083cU,
-/*0089*/ 0x000c083dU,
-/*008a*/ 0x100c083dU,
-/*008b*/ 0x000c083eU,
-/*008c*/ 0x100c083eU,
-/*008d*/ 0x000c083fU,
-/*008e*/ 0x100c083fU,
-/*008f*/ 0x000c0840U,
-/*0090*/ 0x100c0840U,
-/*0091*/ 0x000b0841U,
-/*0092*/ 0x10090841U,
-/*0093*/ 0x00010842U,
-/*0094*/ 0x000b0843U,
-/*0095*/ 0x100b0843U,
-/*0096*/ 0x000b0844U,
-/*0097*/ 0x100b0844U,
-/*0098*/ 0x000b0845U,
-/*0099*/ 0x100b0845U,
-/*009a*/ 0x000b0846U,
-/*009b*/ 0x100b0846U,
-/*009c*/ 0x000b0847U,
-/*009d*/ 0x100a0847U,
-/*009e*/ 0x00020848U,
-/*009f*/ 0x080a0848U,
-/*00a0*/ 0x000a0849U,
-/*00a1*/ 0x100a0849U,
-/*00a2*/ 0x000a084aU,
-/*00a3*/ 0x100a084aU,
-/*00a4*/ 0x000a084bU,
-/*00a5*/ 0x100a084bU,
-/*00a6*/ 0x000a084cU,
-/*00a7*/ 0x100a084cU,
-/*00a8*/ 0x000a084dU,
-/*00a9*/ 0x100a084dU,
-/*00aa*/ 0x000a084eU,
-/*00ab*/ 0x100a084eU,
-/*00ac*/ 0x000a084fU,
-/*00ad*/ 0x100a084fU,
-/*00ae*/ 0x000a0850U,
-/*00af*/ 0x100a0850U,
-/*00b0*/ 0x000a0851U,
-/*00b1*/ 0x100a0851U,
-/*00b2*/ 0x000a0852U,
-/*00b3*/ 0x100a0852U,
-/*00b4*/ 0x000a0853U,
-/*00b5*/ 0x100a0853U,
-/*00b6*/ 0x000a0854U,
-/*00b7*/ 0x100a0854U,
-/*00b8*/ 0x000a0855U,
-/*00b9*/ 0x100a0855U,
-/*00ba*/ 0x000a0856U,
-/*00bb*/ 0x10040856U,
-/*00bc*/ 0x18030856U,
-/*00bd*/ 0x000a0857U,
-/*00be*/ 0x100a0857U,
-/*00bf*/ 0x00010858U,
-/*00c0*/ 0x080a0858U,
-/*00c1*/ 0x18040858U,
-/*00c2*/ 0x000b0859U,
-/*00c3*/ 0x100a0859U,
-/*00c4*/ 0x0003085aU,
-/*00c5*/ 0x0008085bU,
-/*00c6*/ 0x0808085bU,
-/*00c7*/ 0x1008085bU,
-/*00c8*/ 0x1808085bU,
-/*00c9*/ 0x0008085cU,
-/*00ca*/ 0x0808085cU,
-/*00cb*/ 0x1008085cU,
-/*00cc*/ 0x1801085cU,
-/*00cd*/ 0x0008085dU,
-/*00ce*/ 0x0808085dU,
-/*00cf*/ 0x1002085dU,
-/*00d0*/ 0x1802085dU,
-/*00d1*/ 0x0005085eU,
-/*00d2*/ 0x1005085eU,
-/*00d3*/ 0x1805085eU,
-/*00d4*/ 0x0004085fU,
-/*00d5*/ 0x080b085fU,
-/*00d6*/ 0x1806085fU,
-/*00d7*/ 0x00080860U,
-/*00d8*/ 0x08080860U,
-/*00d9*/ 0x10040860U,
-/*00da*/ 0x18040860U,
-/*00db*/ 0x00060861U,
-/*00dc*/ 0x08040861U,
-/*00dd*/ 0x10050861U,
-/*00de*/ 0x000a0862U,
-/*00df*/ 0x100a0862U,
-/*00e0*/ 0x00080863U,
-/*00e1*/ 0x08010863U,
-/*00e2*/ 0x10040863U,
-/*00e3*/ 0x00020864U,
-/*00e4*/ 0x08030864U,
-/*00e5*/ 0x00050a00U,
-/*00e6*/ 0x08050a00U,
-/*00e7*/ 0x10050a00U,
-/*00e8*/ 0x18050a00U,
-/*00e9*/ 0x00050a01U,
-/*00ea*/ 0x08050a01U,
-/*00eb*/ 0x100b0a01U,
-/*00ec*/ 0x00010a02U,
-/*00ed*/ 0x08030a02U,
-/*00ee*/ 0x00200a03U,
-/*00ef*/ 0x00100a04U,
-/*00f0*/ 0x10040a04U,
-/*00f1*/ 0x000b0a05U,
-/*00f2*/ 0x10070a05U,
-/*00f3*/ 0x00090a06U,
-/*00f4*/ 0x10030a06U,
-/*00f5*/ 0x18030a06U,
-/*00f6*/ 0x00010a07U,
-/*00f7*/ 0x08010a07U,
-/*00f8*/ 0x10070a07U,
-/*00f9*/ 0x18070a07U,
-/*00fa*/ 0x00050a08U,
-/*00fb*/ 0x08010a08U,
-/*00fc*/ 0x10020a08U,
-/*00fd*/ 0x18030a08U,
-/*00fe*/ 0x00010a09U,
-/*00ff*/ 0x080f0a09U,
-/*0100*/ 0x00200a0aU,
-/*0101*/ 0x00200a0bU,
-/*0102*/ 0x000b0a0cU,
-/*0103*/ 0x100b0a0cU,
-/*0104*/ 0x000b0a0dU,
-/*0105*/ 0x00180a0eU,
-/*0106*/ 0x00180a0fU,
-/*0107*/ 0xffffffffU,
-/*0108*/ 0xffffffffU,
-/*0109*/ 0xffffffffU,
-/*010a*/ 0xffffffffU,
-/*010b*/ 0xffffffffU,
-/*010c*/ 0x18020a0fU,
-/*010d*/ 0x00020a10U,
-/*010e*/ 0x08040a10U,
-/*010f*/ 0x10040a10U,
-/*0110*/ 0x18010a10U,
-/*0111*/ 0x00010a11U,
-/*0112*/ 0x08010a11U,
-/*0113*/ 0x10030a11U,
-/*0114*/ 0x00200a12U,
-/*0115*/ 0x00200a13U,
-/*0116*/ 0xffffffffU,
-/*0117*/ 0x00140a14U,
-/*0118*/ 0x00140a15U,
-/*0119*/ 0x00140a16U,
-/*011a*/ 0x00140a17U,
-/*011b*/ 0x00140a18U,
-/*011c*/ 0x00140a19U,
-/*011d*/ 0x00140a1aU,
-/*011e*/ 0x00140a1bU,
-/*011f*/ 0x001e0a1cU,
-/*0120*/ 0x000a0a1dU,
-/*0121*/ 0x10060a1dU,
-/*0122*/ 0x18060a1dU,
-/*0123*/ 0x00060a1eU,
-/*0124*/ 0x08060a1eU,
-/*0125*/ 0x10060a1eU,
-/*0126*/ 0x00080a1fU,
-/*0127*/ 0x080b0a1fU,
-/*0128*/ 0x000b0a20U,
-/*0129*/ 0x100b0a20U,
-/*012a*/ 0x000b0a21U,
-/*012b*/ 0x100b0a21U,
-/*012c*/ 0x000b0a22U,
-/*012d*/ 0x10040a22U,
-/*012e*/ 0x000b0a23U,
-/*012f*/ 0x10060a23U,
-/*0130*/ 0x18080a23U,
-/*0131*/ 0x00080a24U,
-/*0132*/ 0x08040a24U,
-/*0133*/ 0x00020b80U,
-/*0134*/ 0x00010b81U,
-/*0135*/ 0x08010b81U,
-/*0136*/ 0x10020b81U,
-/*0137*/ 0x18050b81U,
-/*0138*/ 0x00050b82U,
-/*0139*/ 0x08050b82U,
-/*013a*/ 0x10050b82U,
-/*013b*/ 0x000b0b83U,
-/*013c*/ 0x10050b83U,
-/*013d*/ 0x18010b83U,
-/*013e*/ 0x00010b84U,
-/*013f*/ 0x08010b84U,
-/*0140*/ 0x10010b84U,
-/*0141*/ 0x18010b84U,
-/*0142*/ 0x00040b85U,
-/*0143*/ 0x080b0b85U,
-/*0144*/ 0x000b0b86U,
-/*0145*/ 0x100b0b86U,
-/*0146*/ 0x00040b87U,
-/*0147*/ 0x080b0b87U,
-/*0148*/ 0x18040b87U,
-/*0149*/ 0x00010b88U,
-/*014a*/ 0x08010b88U,
-/*014b*/ 0x10010b88U,
-/*014c*/ 0x00200b89U,
-/*014d*/ 0x00200b8aU,
-/*014e*/ 0x00080b8bU,
-/*014f*/ 0x080a0b8bU,
-/*0150*/ 0x18050b8bU,
-/*0151*/ 0x000b0b8cU,
-/*0152*/ 0x10030b8cU,
-/*0153*/ 0x18030b8cU,
-/*0154*/ 0x00010b8dU,
-/*0155*/ 0x08020b8dU,
-/*0156*/ 0x10010b8dU,
-/*0157*/ 0x18010b8dU,
-/*0158*/ 0x00010b8eU,
-/*0159*/ 0xffffffffU,
-/*015a*/ 0x08010b8eU,
-/*015b*/ 0x18040b8eU,
-/*015c*/ 0x00040b8fU,
-/*015d*/ 0x08040b8fU,
-/*015e*/ 0x10040b8fU,
-/*015f*/ 0x18010b8fU,
-/*0160*/ 0x00010b90U,
-/*0161*/ 0x08010b90U,
-/*0162*/ 0x00200b91U,
-/*0163*/ 0x00200b92U,
-/*0164*/ 0x00200b93U,
-/*0165*/ 0x00200b94U,
-/*0166*/ 0xffffffffU,
-/*0167*/ 0x10010b8eU,
-/*0168*/ 0x000d0b96U,
-/*0169*/ 0x100d0b96U,
-/*016a*/ 0x000d0b97U,
-/*016b*/ 0x00050b98U,
-/*016c*/ 0x00010b99U,
-/*016d*/ 0x080e0b99U,
-/*016e*/ 0x000e0b9aU,
-/*016f*/ 0x100e0b9aU,
-/*0170*/ 0x000e0b9bU,
-/*0171*/ 0x100e0b9bU,
-/*0172*/ 0x00040b9cU,
-/*0173*/ 0x08040b9cU,
-/*0174*/ 0x10040b9cU,
-/*0175*/ 0x18040b9cU,
-/*0176*/ 0x00040b9dU,
-/*0177*/ 0x080b0b9dU,
-/*0178*/ 0x000b0b9eU,
-/*0179*/ 0x100b0b9eU,
-/*017a*/ 0x000b0b9fU,
-/*017b*/ 0x00040ba0U,
-/*017c*/ 0x08040ba0U,
-/*017d*/ 0x10040ba0U,
-/*017e*/ 0x18040ba0U,
-/*017f*/ 0x000d0ba1U,
-/*0180*/ 0x100d0ba1U,
-/*0181*/ 0x000d0ba2U,
-/*0182*/ 0x10100ba2U,
-/*0183*/ 0x00080b95U,
-/*0184*/ 0x08080b95U,
-/*0185*/ 0x00100ba3U,
-/*0186*/ 0x10100ba3U,
-/*0187*/ 0x00100ba4U,
-/*0188*/ 0x10100ba4U,
-/*0189*/ 0x00100ba5U,
-/*018a*/ 0x10030ba5U,
-/*018b*/ 0x18040ba5U,
-/*018c*/ 0x00010ba6U,
-/*018d*/ 0x08080ba6U,
-/*018e*/ 0x10010ba6U,
-/*018f*/ 0x000a0ba7U,
-/*0190*/ 0x10010ba7U,
-/*0191*/ 0x00140ba8U,
-/*0192*/ 0x000b0ba9U,
-/*0193*/ 0x100c0ba9U,
-/*0194*/ 0x00120baaU,
-/*0195*/ 0x00140babU,
-/*0196*/ 0x00120bacU,
-/*0197*/ 0x00110badU,
-/*0198*/ 0x00110baeU,
-/*0199*/ 0x00120bafU,
-/*019a*/ 0x00120bb0U,
-/*019b*/ 0x00120bb1U,
-/*019c*/ 0x00120bb2U,
-/*019d*/ 0x00120bb3U,
-/*019e*/ 0x00120bb4U,
-/*019f*/ 0x00120bb5U,
-/*01a0*/ 0x00120bb6U,
-/*01a1*/ 0x00120bb7U,
-/*01a2*/ 0x00120bb8U,
-/*01a3*/ 0x000e0bb9U,
-/*01a4*/ 0x100d0bb9U,
-/*01a5*/ 0x00200bbaU,
-/*01a6*/ 0x00170bbbU,
-/*01a7*/ 0x000d0bbcU,
-/*01a8*/ 0x10010bbcU,
-/*01a9*/ 0x18010bbcU,
-/*01aa*/ 0x00200bbdU,
-/*01ab*/ 0x00080bbeU,
-/*01ac*/ 0x08030bbeU,
-/*01ad*/ 0x10030bbeU,
-/*01ae*/ 0x00180bbfU,
-/*01af*/ 0x00180bc0U,
-/*01b0*/ 0x18070bc0U,
-/*01b1*/ 0x00070bc1U,
-/*01b2*/ 0x08080bc1U,
-/*01b3*/ 0x10080bc1U,
-/*01b4*/ 0x18080bc1U,
-/*01b5*/ 0x00010bc2U,
-/*01b6*/ 0x08010bc2U,
-/*01b7*/ 0x00200bc3U,
-/*01b8*/ 0x00070bc4U,
-/*01b9*/ 0x08140bc4U,
-/*01ba*/ 0x00140bc5U,
-/*01bb*/ 0x00190bc6U,
-/*01bc*/ 0x00170bc7U,
-/*01bd*/ 0x00110bc8U,
-/*01be*/ 0x00110bc9U,
-/*01bf*/ 0x00100bcaU,
-/*01c0*/ 0x10010bcaU,
-/*01c1*/ 0x18010bcaU,
-/*01c2*/ 0x00020bcbU,
-/*01c3*/ 0x08040bcbU,
-/*01c4*/ 0x10090bcbU,
-/*01c5*/ 0x00070bccU,
-/*01c6*/ 0x08040bccU,
-/*01c7*/ 0x00200bcdU,
-/*01c8*/ 0x00010bceU,
-/*01c9*/ 0x08020bceU,
-/*01ca*/ 0x10060bceU,
-/*01cb*/ 0x00100bcfU,
-/*01cc*/ 0x10010bcfU,
-/*01cd*/ 0x00200bd0U,
-/*01ce*/ 0x00080bd1U,
-/*01cf*/ 0x08010bd1U,
-/*01d0*/ 0x10050bd1U,
-/*01d1*/ 0x18030bd1U,
-/*01d2*/ 0x00020bd2U,
-/*01d3*/ 0xffffffffU,
-/*01d4*/ 0x00200bd3U,
-/*01d5*/ 0x000b0bd4U,
-/*01d6*/ 0xffffffffU,
-/*01d7*/ 0x10030bd4U,
-/*01d8*/ 0x18080bd4U,
-/*01d9*/ 0x00020bd5U,
-/*01da*/ 0x080c0bd5U,
-/*01db*/ 0x18040bd5U,
-/*01dc*/ 0x00010bd6U,
-/*01dd*/ 0x08050bd6U,
-/*01de*/ 0x00010200U,
-/*01df*/ 0x08040200U,
-/*01e0*/ 0x10100200U,
-/*01e1*/ 0x00010201U,
-/*01e2*/ 0x08010201U,
-/*01e3*/ 0x10010201U,
-/*01e4*/ 0x18010201U,
-/*01e5*/ 0x00100202U,
-/*01e6*/ 0x10080202U,
-/*01e7*/ 0x18010202U,
-/*01e8*/ 0x00200203U,
-/*01e9*/ 0x00200204U,
-/*01ea*/ 0x00200205U,
-/*01eb*/ 0x00200206U,
-/*01ec*/ 0x00020207U,
-/*01ed*/ 0x08010207U,
-/*01ee*/ 0x10010207U,
-/*01ef*/ 0x00200208U,
-/*01f0*/ 0x00140209U,
-/*01f1*/ 0x0020020aU,
-/*01f2*/ 0x0014020bU,
-/*01f3*/ 0x0020020cU,
-/*01f4*/ 0x0014020dU,
-/*01f5*/ 0x0014020eU,
-/*01f6*/ 0x0020020fU,
-/*01f7*/ 0x00200210U,
-/*01f8*/ 0x00200211U,
-/*01f9*/ 0x00200212U,
-/*01fa*/ 0x00140213U,
-/*01fb*/ 0x00200214U,
-/*01fc*/ 0x00200215U,
-/*01fd*/ 0x00200216U,
-/*01fe*/ 0x00200217U,
-/*01ff*/ 0x00140218U,
-/*0200*/ 0x00200219U,
-/*0201*/ 0x0020021aU,
-/*0202*/ 0x0020021bU,
-/*0203*/ 0x0020021cU,
-/*0204*/ 0x0009021dU,
-/*0205*/ 0x1001021dU,
-/*0206*/ 0x0020021eU,
-/*0207*/ 0x0005021fU,
-/*0208*/ 0x0801021fU,
-/*0209*/ 0x1008021fU,
-/*020a*/ 0x1808021fU,
-/*020b*/ 0x001e0220U,
-/*020c*/ 0x001e0221U,
-/*020d*/ 0x001e0222U,
-/*020e*/ 0x001e0223U,
-/*020f*/ 0x001e0224U,
-/*0210*/ 0x001e0225U,
-/*0211*/ 0x001e0226U,
-/*0212*/ 0x001e0227U,
-/*0213*/ 0x001e0228U,
-/*0214*/ 0x001e0229U,
-/*0215*/ 0x001e022aU,
-/*0216*/ 0x001e022bU,
-/*0217*/ 0x001e022cU,
-/*0218*/ 0x001e022dU,
-/*0219*/ 0x001e022eU,
-/*021a*/ 0x001e022fU,
-/*021b*/ 0x00010230U,
-/*021c*/ 0x08010230U,
-/*021d*/ 0x10010230U,
-/*021e*/ 0x18040230U,
-/*021f*/ 0x00080231U,
-/*0220*/ 0x08080231U,
-/*0221*/ 0x10080231U,
-/*0222*/ 0x18040231U,
-/*0223*/ 0x00070232U,
-/*0224*/ 0x08060232U,
-/*0225*/ 0x10070232U,
-/*0226*/ 0x18070232U,
-/*0227*/ 0x00060233U,
-/*0228*/ 0x08070233U,
-/*0229*/ 0x10070233U,
-/*022a*/ 0x18060233U,
-/*022b*/ 0x00070234U,
-/*022c*/ 0x08020234U,
-/*022d*/ 0x10010234U,
-/*022e*/ 0x18010234U,
-/*022f*/ 0x000a0235U,
-/*0230*/ 0x00140236U,
-/*0231*/ 0x000a0237U,
-/*0232*/ 0x00140238U,
-/*0233*/ 0x000a0239U,
-/*0234*/ 0x0014023aU,
-/*0235*/ 0xffffffffU,
-/*0236*/ 0xffffffffU,
-/*0237*/ 0x0005023bU,
-/*0238*/ 0x0001023cU,
-/*0239*/ 0x1001023cU,
-/*023a*/ 0x1801023cU,
-/*023b*/ 0x0001023dU,
-/*023c*/ 0x0801023dU,
-/*023d*/ 0x1001023dU,
-/*023e*/ 0x1801023dU,
-/*023f*/ 0x0002023eU,
-/*0240*/ 0x0802023eU,
-/*0241*/ 0x1002023eU,
-/*0242*/ 0x1802023eU,
-/*0243*/ 0x0002023fU,
-/*0244*/ 0x0803023fU,
-/*0245*/ 0x1001023fU,
-/*0246*/ 0x1801023fU,
-/*0247*/ 0x00010240U,
-/*0248*/ 0x08010240U,
-/*0249*/ 0x10010240U,
-/*024a*/ 0x18020240U,
-/*024b*/ 0x00010241U,
-/*024c*/ 0x08010241U,
-/*024d*/ 0x10010241U,
-/*024e*/ 0x18020241U,
-/*024f*/ 0x00010242U,
-/*0250*/ 0x08010242U,
-/*0251*/ 0x10010242U,
-/*0252*/ 0x18020242U,
-/*0253*/ 0x00010243U,
-/*0254*/ 0x08010243U,
-/*0255*/ 0x10010243U,
-/*0256*/ 0x18020243U,
-/*0257*/ 0xffffffffU,
-/*0258*/ 0x00010244U,
-/*0259*/ 0x08010244U,
-/*025a*/ 0x10010244U,
-/*025b*/ 0x18010244U,
-/*025c*/ 0x00010245U,
-/*025d*/ 0x08010245U,
-/*025e*/ 0x10010245U,
-/*025f*/ 0x18010245U,
-/*0260*/ 0x00040246U,
-/*0261*/ 0x08040246U,
-/*0262*/ 0x10040246U,
-/*0263*/ 0x18010246U,
-/*0264*/ 0x00020247U,
-/*0265*/ 0x08060247U,
-/*0266*/ 0x10060247U,
-/*0267*/ 0x18020247U,
-/*0268*/ 0x00020248U,
-/*0269*/ 0x08020248U,
-/*026a*/ 0xffffffffU,
-/*026b*/ 0x10100248U,
-/*026c*/ 0x00010249U,
-/*026d*/ 0x08010249U,
-/*026e*/ 0x10010249U,
-/*026f*/ 0x18040249U,
-/*0270*/ 0x0001024aU,
-/*0271*/ 0x0804024aU,
-/*0272*/ 0x1003024aU,
-/*0273*/ 0x1808024aU,
-/*0274*/ 0x000a024bU,
-/*0275*/ 0x100a024bU,
-/*0276*/ 0x000a024cU,
-/*0277*/ 0xffffffffU,
-/*0278*/ 0x0020024dU,
-/*0279*/ 0x0020024eU,
-/*027a*/ 0x0005024fU,
-/*027b*/ 0x1801023aU,
-/*027c*/ 0x0805023cU,
-/*027d*/ 0x0808024fU,
-/*027e*/ 0x1001024fU,
-/*027f*/ 0x1808024fU,
-/*0280*/ 0x00010250U,
-/*0281*/ 0x08080250U,
-/*0282*/ 0x10010250U,
-/*0283*/ 0x18040250U,
-/*0284*/ 0x00040251U,
-/*0285*/ 0x08040251U,
-/*0286*/ 0x10040251U,
-/*0287*/ 0x18040251U,
-/*0288*/ 0x00040252U,
-/*0289*/ 0x08040252U,
-/*028a*/ 0x10040252U,
-/*028b*/ 0x18040252U,
-/*028c*/ 0x00040253U,
-/*028d*/ 0x08010253U,
-/*028e*/ 0x10040253U,
-/*028f*/ 0x18040253U,
-/*0290*/ 0x00040254U,
-/*0291*/ 0x08040254U,
-/*0292*/ 0x10040254U,
-/*0293*/ 0x18040254U,
-/*0294*/ 0x00060255U,
-/*0295*/ 0x08060255U,
-/*0296*/ 0x10060255U,
-/*0297*/ 0x18060255U,
-/*0298*/ 0x00060256U,
-/*0299*/ 0x08060256U,
-/*029a*/ 0x10040256U,
-/*029b*/ 0x18010256U,
-/*029c*/ 0x00010257U,
-/*029d*/ 0x08020257U,
-/*029e*/ 0x00200258U,
-/*029f*/ 0x00200259U,
-/*02a0*/ 0x0020025aU,
-/*02a1*/ 0x0020025bU,
-/*02a2*/ 0x0020025cU,
-/*02a3*/ 0x0020025dU,
-/*02a4*/ 0x0020025eU,
-/*02a5*/ 0x0020025fU,
-/*02a6*/ 0x00040260U,
-/*02a7*/ 0x08040260U,
-/*02a8*/ 0x10010260U,
-/*02a9*/ 0x18010260U,
-/*02aa*/ 0x00010261U,
-/*02ab*/ 0x08010261U,
-/*02ac*/ 0x10010261U,
-/*02ad*/ 0x18010261U,
-/*02ae*/ 0x00010262U,
-/*02af*/ 0x08010262U,
-/*02b0*/ 0x10010262U,
-/*02b1*/ 0x18040262U,
-/*02b2*/ 0x00040263U,
-/*02b3*/ 0x080a0263U,
-/*02b4*/ 0x00200264U,
-/*02b5*/ 0x00040265U,
-/*02b6*/ 0x08080265U,
-/*02b7*/ 0x10020265U,
-/*02b8*/ 0x18020265U,
-/*02b9*/ 0x00020266U,
-/*02ba*/ 0x08020266U,
-/*02bb*/ 0x10020266U,
-/*02bc*/ 0x18020266U,
-/*02bd*/ 0xffffffffU,
-/*02be*/ 0xffffffffU,
-/*02bf*/ 0x00200267U,
-/*02c0*/ 0x00030268U,
-/*02c1*/ 0x08100268U,
-/*02c2*/ 0x00100269U,
-/*02c3*/ 0x10040269U,
-/*02c4*/ 0x18040269U,
-/*02c5*/ 0x0005026aU,
-/*02c6*/ 0x0805026aU,
-/*02c7*/ 0xffffffffU,
-/*02c8*/ 0xffffffffU,
-/*02c9*/ 0xffffffffU,
-/*02ca*/ 0xffffffffU,
-/*02cb*/ 0x1001026aU,
-/*02cc*/ 0x1801026aU,
-/*02cd*/ 0x0008026bU,
-/*02ce*/ 0x0808026bU,
-/*02cf*/ 0x1008026bU,
-/*02d0*/ 0x1808026bU,
-/*02d1*/ 0x0008026cU,
-/*02d2*/ 0x0808026cU,
-/*02d3*/ 0x1008026cU,
-/*02d4*/ 0x1808026cU,
-/*02d5*/ 0x0008026dU,
-/*02d6*/ 0x0808026dU,
-/*02d7*/ 0x1008026dU,
-/*02d8*/ 0x1808026dU,
-/*02d9*/ 0x0008026eU,
-/*02da*/ 0x0808026eU,
-/*02db*/ 0x1003026eU,
-/*02dc*/ 0x1803026eU,
-/*02dd*/ 0x0003026fU,
-/*02de*/ 0xffffffffU,
-/*02df*/ 0x0801026fU,
-/*02e0*/ 0x1002026fU,
-/*02e1*/ 0x1801026fU,
-/*02e2*/ 0x00040270U,
-/*02e3*/ 0x08020270U,
-/*02e4*/ 0x10010270U,
-/*02e5*/ 0x18010270U,
-/*02e6*/ 0x00010271U,
-/*02e7*/ 0x08010271U,
-/*02e8*/ 0x10040271U,
-/*02e9*/ 0x18080271U,
-/*02ea*/ 0x000a0272U,
-/*02eb*/ 0x100a0272U,
-/*02ec*/ 0x000a0273U,
-/*02ed*/ 0x100a0273U,
-/*02ee*/ 0x000a0274U,
-/*02ef*/ 0x100a0274U,
-/*02f0*/ 0x00200275U,
-/*02f1*/ 0x00200276U,
-/*02f2*/ 0x00010277U,
-/*02f3*/ 0x08020277U,
-/*02f4*/ 0x10020277U,
-/*02f5*/ 0x18020277U,
-/*02f6*/ 0xffffffffU,
-/*02f7*/ 0x00020278U,
-/*02f8*/ 0x08100278U,
-/*02f9*/ 0x18050278U,
-/*02fa*/ 0x00060279U,
-/*02fb*/ 0x08050279U,
-/*02fc*/ 0x10050279U,
-/*02fd*/ 0x000e027aU,
-/*02fe*/ 0x1005027aU,
-/*02ff*/ 0x000e027bU,
-/*0300*/ 0x1005027bU,
-/*0301*/ 0x000e027cU,
-/*0302*/ 0x1005027cU,
-/*0303*/ 0x1801027cU,
-/*0304*/ 0x0005027dU,
-/*0305*/ 0x0805027dU,
-/*0306*/ 0x100a027dU,
-/*0307*/ 0x000a027eU,
-/*0308*/ 0x1005027eU,
-/*0309*/ 0x1805027eU,
-/*030a*/ 0x000a027fU,
-/*030b*/ 0x100a027fU,
-/*030c*/ 0x00050280U,
-/*030d*/ 0x08050280U,
-/*030e*/ 0x100a0280U,
-/*030f*/ 0x000a0281U,
-/*0310*/ 0x10070281U,
-/*0311*/ 0x18070281U,
-/*0312*/ 0x00070282U,
-/*0313*/ 0x08070282U,
-/*0314*/ 0x10070282U,
-/*0315*/ 0x18070282U,
-/*0316*/ 0xffffffffU,
-/*0317*/ 0xffffffffU,
-/*0318*/ 0x00040283U,
-/*0319*/ 0x08040283U,
-/*031a*/ 0x10040283U,
-/*031b*/ 0x18040283U,
-/*031c*/ 0x00040284U,
-/*031d*/ 0xffffffffU,
-/*031e*/ 0x08080284U,
-/*031f*/ 0x10080284U,
-/*0320*/ 0x18040284U,
-/*0321*/ 0x00050285U,
-/*0322*/ 0x08080285U,
-/*0323*/ 0x10050285U,
-/*0324*/ 0x18040285U,
-/*0325*/ 0x00050286U,
-/*0326*/ 0x08080286U,
-/*0327*/ 0x10050286U,
-/*0328*/ 0x18040286U,
-/*0329*/ 0x00050287U,
-/*032a*/ 0x08080287U,
-/*032b*/ 0x10050287U,
-/*032c*/ 0x18040287U,
-/*032d*/ 0x00050288U,
-/*032e*/ 0x08070288U,
-/*032f*/ 0x10080288U,
-/*0330*/ 0x00100289U,
-/*0331*/ 0x10080289U,
-/*0332*/ 0x0010028aU,
-/*0333*/ 0x1008028aU,
-/*0334*/ 0x0010028bU,
-/*0335*/ 0x1008028bU,
-/*0336*/ 0x1808028bU,
-/*0337*/ 0x0001028cU,
-/*0338*/ 0x0801028cU,
-/*0339*/ 0x1006028cU,
-/*033a*/ 0x1806028cU,
-/*033b*/ 0x0006028dU,
-/*033c*/ 0x0801028dU,
-/*033d*/ 0x1001028dU,
-/*033e*/ 0x1803028dU,
-/*033f*/ 0x000a028eU,
-/*0340*/ 0x100a028eU,
-/*0341*/ 0x000a028fU,
-/*0342*/ 0xffffffffU,
-/*0343*/ 0x100a028fU,
-/*0344*/ 0x00040290U,
-/*0345*/ 0x08010290U,
-/*0346*/ 0x10040290U,
-/*0347*/ 0x18070290U,
-/*0348*/ 0x00070291U,
-/*0349*/ 0x08070291U,
-/*034a*/ 0x10070291U,
-/*034b*/ 0x18070291U,
-/*034c*/ 0x00070292U,
-/*034d*/ 0xffffffffU,
-/*034e*/ 0xffffffffU,
-/*034f*/ 0x08050292U,
-/*0350*/ 0x10050292U,
-/*0351*/ 0x18040292U,
-/*0352*/ 0x00040293U,
-/*0353*/ 0x08040293U,
-/*0354*/ 0xffffffffU,
-/*0355*/ 0x10010293U,
-/*0356*/ 0x18010293U,
-/*0357*/ 0x00020294U,
-/*0358*/ 0x08080294U,
-/*0359*/ 0x00200295U,
-/*035a*/ 0x00200296U,
-/*035b*/ 0x00100297U,
-/*035c*/ 0x10020297U,
-/*035d*/ 0x18020297U,
-/*035e*/ 0x00020298U,
-/*035f*/ 0xffffffffU,
-/*0360*/ 0x08010298U,
-/*0361*/ 0x10010298U,
-/*0362*/ 0x18020298U,
-/*0363*/ 0x00100299U,
-/*0364*/ 0x10100299U,
-/*0365*/ 0x0010029aU,
-/*0366*/ 0x1008029aU,
-/*0367*/ 0x1808029aU,
-/*0368*/ 0x0008029bU,
-/*0369*/ 0x0808029bU,
-/*036a*/ 0x1010029bU,
-/*036b*/ 0x0010029cU,
-/*036c*/ 0x1010029cU,
-/*036d*/ 0x0008029dU,
-/*036e*/ 0x0808029dU,
-/*036f*/ 0x1008029dU,
-/*0370*/ 0x1808029dU,
-/*0371*/ 0x0010029eU,
-/*0372*/ 0x1010029eU,
-/*0373*/ 0x0010029fU,
-/*0374*/ 0x1008029fU,
-/*0375*/ 0x1808029fU,
-/*0376*/ 0x000802a0U,
-/*0377*/ 0x080802a0U,
-/*0378*/ 0x100802a0U,
-/*0379*/ 0x001002a1U,
-/*037a*/ 0x101002a1U,
-/*037b*/ 0x001002a2U,
-/*037c*/ 0x100802a2U,
-/*037d*/ 0x180802a2U,
-/*037e*/ 0x000802a3U,
-/*037f*/ 0x080802a3U,
-/*0380*/ 0x101002a3U,
-/*0381*/ 0x001002a4U,
-/*0382*/ 0x101002a4U,
-/*0383*/ 0x000802a5U,
-/*0384*/ 0x080802a5U,
-/*0385*/ 0x100802a5U,
-/*0386*/ 0x180802a5U,
-/*0387*/ 0x001002a6U,
-/*0388*/ 0x101002a6U,
-/*0389*/ 0x001002a7U,
-/*038a*/ 0x100802a7U,
-/*038b*/ 0x180802a7U,
-/*038c*/ 0x000802a8U,
-/*038d*/ 0x080802a8U,
-/*038e*/ 0x100802a8U,
-/*038f*/ 0x001002a9U,
-/*0390*/ 0x101002a9U,
-/*0391*/ 0x001002aaU,
-/*0392*/ 0x100802aaU,
-/*0393*/ 0x180802aaU,
-/*0394*/ 0x000802abU,
-/*0395*/ 0x080802abU,
-/*0396*/ 0x101002abU,
-/*0397*/ 0x001002acU,
-/*0398*/ 0x101002acU,
-/*0399*/ 0x000802adU,
-/*039a*/ 0x080802adU,
-/*039b*/ 0x100802adU,
-/*039c*/ 0x180802adU,
-/*039d*/ 0x001002aeU,
-/*039e*/ 0x101002aeU,
-/*039f*/ 0x001002afU,
-/*03a0*/ 0x100802afU,
-/*03a1*/ 0x180802afU,
-/*03a2*/ 0x000802b0U,
-/*03a3*/ 0x080802b0U,
-/*03a4*/ 0x100802b0U,
-/*03a5*/ 0x001002b1U,
-/*03a6*/ 0x101002b1U,
-/*03a7*/ 0x001002b2U,
-/*03a8*/ 0x100802b2U,
-/*03a9*/ 0x180802b2U,
-/*03aa*/ 0x000802b3U,
-/*03ab*/ 0x080802b3U,
-/*03ac*/ 0x101002b3U,
-/*03ad*/ 0x001002b4U,
-/*03ae*/ 0x101002b4U,
-/*03af*/ 0x000802b5U,
-/*03b0*/ 0x080802b5U,
-/*03b1*/ 0x100802b5U,
-/*03b2*/ 0x180802b5U,
-/*03b3*/ 0x001002b6U,
-/*03b4*/ 0x101002b6U,
-/*03b5*/ 0x001002b7U,
-/*03b6*/ 0x100802b7U,
-/*03b7*/ 0x180802b7U,
-/*03b8*/ 0x000802b8U,
-/*03b9*/ 0x080802b8U,
-/*03ba*/ 0x100802b8U,
-/*03bb*/ 0x180202b8U,
-/*03bc*/ 0x000302b9U,
-/*03bd*/ 0x080a02b9U,
-/*03be*/ 0x000a02baU,
-/*03bf*/ 0x100a02baU,
-/*03c0*/ 0x000502bbU,
-/*03c1*/ 0x080802bbU,
-/*03c2*/ 0x100802bbU,
-/*03c3*/ 0x180802bbU,
-/*03c4*/ 0x000602bcU,
-/*03c5*/ 0x080602bcU,
-/*03c6*/ 0x001102bdU,
-/*03c7*/ 0x180802bdU,
-/*03c8*/ 0x000402beU,
-/*03c9*/ 0x080602beU,
-/*03ca*/ 0x100802beU,
-/*03cb*/ 0x180802beU,
-/*03cc*/ 0x000802bfU,
-/*03cd*/ 0x080802bfU,
-/*03ce*/ 0x100802bfU,
-/*03cf*/ 0x180802bfU,
-/*03d0*/ 0x000802c0U,
-/*03d1*/ 0x080602c0U,
-/*03d2*/ 0x100602c0U,
-/*03d3*/ 0x001102c1U,
-/*03d4*/ 0x180802c1U,
-/*03d5*/ 0x000402c2U,
-/*03d6*/ 0x080602c2U,
-/*03d7*/ 0x100802c2U,
-/*03d8*/ 0x180802c2U,
-/*03d9*/ 0x000802c3U,
-/*03da*/ 0x080802c3U,
-/*03db*/ 0x100802c3U,
-/*03dc*/ 0x180802c3U,
-/*03dd*/ 0x000802c4U,
-/*03de*/ 0x080602c4U,
-/*03df*/ 0x100602c4U,
-/*03e0*/ 0x001102c5U,
-/*03e1*/ 0x180802c5U,
-/*03e2*/ 0x000402c6U,
-/*03e3*/ 0x080602c6U,
-/*03e4*/ 0x100802c6U,
-/*03e5*/ 0x180802c6U,
-/*03e6*/ 0x000802c7U,
-/*03e7*/ 0x080802c7U,
-/*03e8*/ 0x100402c7U,
-/*03e9*/ 0x180402c7U,
-/*03ea*/ 0x000402c8U,
-/*03eb*/ 0x080402c8U,
-/*03ec*/ 0x100402c8U,
-/*03ed*/ 0x180402c8U,
-/*03ee*/ 0x000402c9U,
-/*03ef*/ 0x080402c9U,
-/*03f0*/ 0x100402c9U,
-/*03f1*/ 0x180402c9U,
-/*03f2*/ 0x000402caU,
-/*03f3*/ 0x080402caU,
-/*03f4*/ 0x100402caU,
-/*03f5*/ 0x180402caU,
-/*03f6*/ 0x000402cbU,
-/*03f7*/ 0x080402cbU,
-/*03f8*/ 0x100402cbU,
-/*03f9*/ 0x180402cbU,
-/*03fa*/ 0x000402ccU,
-/*03fb*/ 0x080402ccU,
-/*03fc*/ 0x001702cdU,
-/*03fd*/ 0x001602ceU,
-/*03fe*/ 0x001702cfU,
-/*03ff*/ 0x002002d0U,
-/*0400*/ 0x002002d1U,
-/*0401*/ 0x002002d2U,
-/*0402*/ 0x002002d3U,
-/*0403*/ 0x002002d4U,
-/*0404*/ 0x002002d5U,
-/*0405*/ 0x002002d6U,
-/*0406*/ 0x002002d7U,
-/*0407*/ 0x002002d8U,
-/*0408*/ 0x000202d9U,
-/*0409*/ 0x080502d9U,
-/*040a*/ 0x100502d9U,
-/*040b*/ 0x180102d9U,
-/*040c*/ 0x000502daU,
-/*040d*/ 0x080502daU,
-/*040e*/ 0x100502daU,
-/*040f*/ 0x180502daU,
-/*0410*/ 0x000502dbU,
-/*0411*/ 0x080502dbU,
-/*0412*/ 0x100502dbU,
-/*0413*/ 0x180502dbU,
-/*0414*/ 0x000502dcU,
-/*0415*/ 0x080502dcU,
-/*0416*/ 0x100502dcU,
-/*0417*/ 0x180502dcU,
-/*0418*/ 0x000502ddU,
-/*0419*/ 0x080502ddU,
-/*041a*/ 0x100502ddU,
-/*041b*/ 0x180502ddU,
-/*041c*/ 0x000502deU,
-/*041d*/ 0x080502deU,
-/*041e*/ 0x100502deU,
-/*041f*/ 0x180502deU,
-/*0420*/ 0x000502dfU,
-/*0421*/ 0x080502dfU,
-/*0422*/ 0x100102dfU,
-/*0423*/ 0x180202dfU,
-/*0424*/ 0x000202e0U,
-/*0425*/ 0x080202e0U,
-/*0426*/ 0x100202e0U,
-/*0427*/ 0x180102e0U,
-/*0428*/ 0x000802e1U,
-/*0429*/ 0x081502e1U,
-/*042a*/ 0x002002e2U,
-/*042b*/ 0x001502e3U,
-/*042c*/ 0x002002e4U,
-/*042d*/ 0x001502e5U,
-/*042e*/ 0x002002e6U,
-/*042f*/ 0x000702e7U,
-/*0430*/ 0x080102e7U,
-/*0431*/ 0x100202e7U,
-/*0432*/ 0x180602e7U,
-/*0433*/ 0x000102e8U,
-/*0434*/ 0x080102e8U,
-/*0435*/ 0x002002e9U,
-/*0436*/ 0x000202eaU,
-/*0437*/ 0x002002ebU,
-/*0438*/ 0x002002ecU,
-/*0439*/ 0x000c02edU,
-/*043a*/ 0x100c02edU,
-/*043b*/ 0x002002eeU,
-/*043c*/ 0x000302efU,
-/*043d*/ 0x002002f0U,
-/*043e*/ 0x000302f1U,
-/*043f*/ 0x002002f2U,
-/*0440*/ 0x000302f3U,
-/*0441*/ 0x002002f4U,
-/*0442*/ 0x000302f5U,
-/*0443*/ 0x002002f6U,
-/*0444*/ 0x000302f7U,
-/*0445*/ 0x002002f8U,
-/*0446*/ 0x000302f9U,
-/*0447*/ 0x002002faU,
-/*0448*/ 0x000302fbU,
-/*0449*/ 0x002002fcU,
-/*044a*/ 0x000302fdU,
-/*044b*/ 0x002002feU,
-/*044c*/ 0x000302ffU,
-/*044d*/ 0x00200300U,
-/*044e*/ 0x00030301U,
-/*044f*/ 0x08030301U,
-/*0450*/ 0x10020301U,
-/*0451*/ 0x18020301U,
-/*0452*/ 0x00200302U,
-/*0453*/ 0x00200303U,
-/*0454*/ 0x00200304U,
-/*0455*/ 0x00200305U,
-/*0456*/ 0x00040306U,
-/*0457*/ 0x001e0307U,
-/*0458*/ 0x001e0308U,
-/*0459*/ 0x001e0309U,
-/*045a*/ 0x001e030aU,
-/*045b*/ 0x001e030bU,
-/*045c*/ 0x001e030cU,
-/*045d*/ 0x001e030dU,
-/*045e*/ 0x001e030eU,
-/*045f*/ 0x0004030fU,
-/*0460*/ 0x0801030fU,
-/*0461*/ 0x1010030fU,
-/*0462*/ 0x00100310U,
-/*0463*/ 0x10100310U,
-/*0464*/ 0x00040311U,
-/*0465*/ 0x08010311U,
-/*0466*/ 0x10080311U,
-/*0467*/ 0x18040311U,
-/*0468*/ 0x00010312U,
-/*0469*/ 0x08080312U,
-/*046a*/ 0x10040312U,
-/*046b*/ 0x18010312U,
-/*046c*/ 0x00080313U,
-/*046d*/ 0x08040313U,
-/*046e*/ 0x10010313U,
-/*046f*/ 0x18080313U,
-/*0470*/ 0x00040314U,
-/*0471*/ 0x08010314U,
-/*0472*/ 0x10080314U,
-/*0473*/ 0x18040314U,
-/*0474*/ 0x00010315U,
-/*0475*/ 0x08080315U,
-/*0476*/ 0x10040315U,
-/*0477*/ 0x18010315U,
-/*0478*/ 0x00080316U,
-/*0479*/ 0x08040316U,
-/*047a*/ 0x10010316U,
-/*047b*/ 0x18080316U,
-/*047c*/ 0x00080317U,
-/*047d*/ 0x00010318U,
-/*047e*/ 0x08050318U,
-/*047f*/ 0x10010318U,
-/*0480*/ 0x18020318U,
-/*0481*/ 0x00010319U,
-/*0482*/ 0x08010319U,
-/*0483*/ 0x10010319U,
-/*0484*/ 0x18010319U,
-/*0485*/ 0x0001031aU,
-/*0486*/ 0x0801031aU,
-/*0487*/ 0x1001031aU,
-/*0488*/ 0x1801031aU,
-/*0489*/ 0x0001031bU,
-/*048a*/ 0x0801031bU,
-/*048b*/ 0x1001031bU,
-/*048c*/ 0x1801031bU,
-/*048d*/ 0x0001031cU,
-/*048e*/ 0x0801031cU,
-/*048f*/ 0x1001031cU,
-/*0490*/ 0x1801031cU,
-/*0491*/ 0x0008031dU,
-/*0492*/ 0x0808031dU,
-/*0493*/ 0x1008031dU,
-/*0494*/ 0x1808031dU,
-	}
-};
-
-#endif /* RZG_DDR_REGDEF_H */
diff --git a/drivers/renesas/rzg/ddr/ddr_b/init_dram_tbl_g2m.h b/drivers/renesas/rzg/ddr/ddr_b/init_dram_tbl_g2m.h
deleted file mode 100644
index e10162a..0000000
--- a/drivers/renesas/rzg/ddr/ddr_b/init_dram_tbl_g2m.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/*
- * Copyright (c) 2020U, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef RZG_INIT_DRAM_TABLE_G2M_H
-#define RZG_INIT_DRAM_TABLE_G2M_H
-
-#define DDR_PHY_SLICE_REGSET_OFS_G2M  0x0800U
-#define DDR_PHY_ADR_V_REGSET_OFS_G2M  0x0a00U
-#define DDR_PHY_ADR_I_REGSET_OFS_G2M  0x0a80U
-#define DDR_PHY_ADR_G_REGSET_OFS_G2M  0x0b80U
-#define DDR_PI_REGSET_OFS_G2M         0x0200U
-
-#define DDR_PHY_SLICE_REGSET_SIZE_G2M 0x80U
-#define DDR_PHY_ADR_V_REGSET_SIZE_G2M 0x80U
-#define DDR_PHY_ADR_I_REGSET_SIZE_G2M 0x80U
-#define DDR_PHY_ADR_G_REGSET_SIZE_G2M 0x80U
-#define DDR_PI_REGSET_SIZE_G2M        0x100U
-
-#define DDR_PHY_SLICE_REGSET_NUM_G2M  89
-#define DDR_PHY_ADR_V_REGSET_NUM_G2M  37
-#define DDR_PHY_ADR_I_REGSET_NUM_G2M  37
-#define DDR_PHY_ADR_G_REGSET_NUM_G2M  64
-#define DDR_PI_REGSET_NUM_G2M         202
-
-static const uint32_t DDR_PHY_SLICE_REGSET_G2M[DDR_PHY_SLICE_REGSET_NUM_G2M] = {
-	/*0800*/ 0x76543210U,
-	/*0801*/ 0x0004f008U,
-	/*0802*/ 0x00000000U,
-	/*0803*/ 0x00000000U,
-	/*0804*/ 0x00010000U,
-	/*0805*/ 0x036e6e0eU,
-	/*0806*/ 0x026e6e0eU,
-	/*0807*/ 0x00010300U,
-	/*0808*/ 0x04000100U,
-	/*0809*/ 0x00000300U,
-	/*080a*/ 0x001700c0U,
-	/*080b*/ 0x00b00201U,
-	/*080c*/ 0x00030020U,
-	/*080d*/ 0x00000000U,
-	/*080e*/ 0x00000000U,
-	/*080f*/ 0x00000000U,
-	/*0810*/ 0x00000000U,
-	/*0811*/ 0x00000000U,
-	/*0812*/ 0x00000000U,
-	/*0813*/ 0x00000000U,
-	/*0814*/ 0x09000000U,
-	/*0815*/ 0x04080000U,
-	/*0816*/ 0x04080400U,
-	/*0817*/ 0x00000000U,
-	/*0818*/ 0x32103210U,
-	/*0819*/ 0x00800708U,
-	/*081a*/ 0x000f000cU,
-	/*081b*/ 0x00000100U,
-	/*081c*/ 0x55aa55aaU,
-	/*081d*/ 0x33cc33ccU,
-	/*081e*/ 0x0ff00ff0U,
-	/*081f*/ 0x0f0ff0f0U,
-	/*0820*/ 0x00018e38U,
-	/*0821*/ 0x00000000U,
-	/*0822*/ 0x00000000U,
-	/*0823*/ 0x00000000U,
-	/*0824*/ 0x00000000U,
-	/*0825*/ 0x00000000U,
-	/*0826*/ 0x00000000U,
-	/*0827*/ 0x00000000U,
-	/*0828*/ 0x00000000U,
-	/*0829*/ 0x00000000U,
-	/*082a*/ 0x00000000U,
-	/*082b*/ 0x00000000U,
-	/*082c*/ 0x00000000U,
-	/*082d*/ 0x00000000U,
-	/*082e*/ 0x00000000U,
-	/*082f*/ 0x00000000U,
-	/*0830*/ 0x00000000U,
-	/*0831*/ 0x00000000U,
-	/*0832*/ 0x00000000U,
-	/*0833*/ 0x00200000U,
-	/*0834*/ 0x08200820U,
-	/*0835*/ 0x08200820U,
-	/*0836*/ 0x08200820U,
-	/*0837*/ 0x08200820U,
-	/*0838*/ 0x08200820U,
-	/*0839*/ 0x00000820U,
-	/*083a*/ 0x03000300U,
-	/*083b*/ 0x03000300U,
-	/*083c*/ 0x03000300U,
-	/*083d*/ 0x03000300U,
-	/*083e*/ 0x00000300U,
-	/*083f*/ 0x00000000U,
-	/*0840*/ 0x00000000U,
-	/*0841*/ 0x00000000U,
-	/*0842*/ 0x00000000U,
-	/*0843*/ 0x00a00000U,
-	/*0844*/ 0x00a000a0U,
-	/*0845*/ 0x00a000a0U,
-	/*0846*/ 0x00a000a0U,
-	/*0847*/ 0x00a000a0U,
-	/*0848*/ 0x00a000a0U,
-	/*0849*/ 0x00a000a0U,
-	/*084a*/ 0x00a000a0U,
-	/*084b*/ 0x00a000a0U,
-	/*084c*/ 0x010900a0U,
-	/*084d*/ 0x02000104U,
-	/*084e*/ 0x00000000U,
-	/*084f*/ 0x00010000U,
-	/*0850*/ 0x00000200U,
-	/*0851*/ 0x4041a151U,
-	/*0852*/ 0xc00141a0U,
-	/*0853*/ 0x0e0100c0U,
-	/*0854*/ 0x0010000cU,
-	/*0855*/ 0x0c064208U,
-	/*0856*/ 0x000f0c18U,
-	/*0857*/ 0x00e00140U,
-	/*0858*/ 0x00000c20U
-};
-
-static const uint32_t DDR_PHY_ADR_V_REGSET_G2M[DDR_PHY_ADR_V_REGSET_NUM_G2M] = {
-	/*0a00*/ 0x00000000U,
-	/*0a01*/ 0x00000000U,
-	/*0a02*/ 0x00000000U,
-	/*0a03*/ 0x00000000U,
-	/*0a04*/ 0x00000000U,
-	/*0a05*/ 0x00000000U,
-	/*0a06*/ 0x00000002U,
-	/*0a07*/ 0x00000000U,
-	/*0a08*/ 0x00000000U,
-	/*0a09*/ 0x00000000U,
-	/*0a0a*/ 0x00400320U,
-	/*0a0b*/ 0x00000040U,
-	/*0a0c*/ 0x00dcba98U,
-	/*0a0d*/ 0x00000000U,
-	/*0a0e*/ 0x00dcba98U,
-	/*0a0f*/ 0x01000000U,
-	/*0a10*/ 0x00020003U,
-	/*0a11*/ 0x00000000U,
-	/*0a12*/ 0x00000000U,
-	/*0a13*/ 0x00000000U,
-	/*0a14*/ 0x0000002aU,
-	/*0a15*/ 0x00000015U,
-	/*0a16*/ 0x00000015U,
-	/*0a17*/ 0x0000002aU,
-	/*0a18*/ 0x00000033U,
-	/*0a19*/ 0x0000000cU,
-	/*0a1a*/ 0x0000000cU,
-	/*0a1b*/ 0x00000033U,
-	/*0a1c*/ 0x0a418820U,
-	/*0a1d*/ 0x003f0000U,
-	/*0a1e*/ 0x0000003fU,
-	/*0a1f*/ 0x0002c06eU,
-	/*0a20*/ 0x02c002c0U,
-	/*0a21*/ 0x02c002c0U,
-	/*0a22*/ 0x000002c0U,
-	/*0a23*/ 0x42080010U,
-	/*0a24*/ 0x00000003U
-};
-
-static const uint32_t DDR_PHY_ADR_I_REGSET_G2M[DDR_PHY_ADR_I_REGSET_NUM_G2M] = {
-	/*0a80*/ 0x04040404U,
-	/*0a81*/ 0x00000404U,
-	/*0a82*/ 0x00000000U,
-	/*0a83*/ 0x00000000U,
-	/*0a84*/ 0x00000000U,
-	/*0a85*/ 0x00000000U,
-	/*0a86*/ 0x00000002U,
-	/*0a87*/ 0x00000000U,
-	/*0a88*/ 0x00000000U,
-	/*0a89*/ 0x00000000U,
-	/*0a8a*/ 0x00400320U,
-	/*0a8b*/ 0x00000040U,
-	/*0a8c*/ 0x00000000U,
-	/*0a8d*/ 0x00000000U,
-	/*0a8e*/ 0x00000000U,
-	/*0a8f*/ 0x01000000U,
-	/*0a90*/ 0x00020003U,
-	/*0a91*/ 0x00000000U,
-	/*0a92*/ 0x00000000U,
-	/*0a93*/ 0x00000000U,
-	/*0a94*/ 0x0000002aU,
-	/*0a95*/ 0x00000015U,
-	/*0a96*/ 0x00000015U,
-	/*0a97*/ 0x0000002aU,
-	/*0a98*/ 0x00000033U,
-	/*0a99*/ 0x0000000cU,
-	/*0a9a*/ 0x0000000cU,
-	/*0a9b*/ 0x00000033U,
-	/*0a9c*/ 0x00000000U,
-	/*0a9d*/ 0x00000000U,
-	/*0a9e*/ 0x00000000U,
-	/*0a9f*/ 0x0002c06eU,
-	/*0aa0*/ 0x02c002c0U,
-	/*0aa1*/ 0x02c002c0U,
-	/*0aa2*/ 0x000002c0U,
-	/*0aa3*/ 0x42080010U,
-	/*0aa4*/ 0x00000003U
-};
-
-static const uint32_t DDR_PHY_ADR_G_REGSET_G2M[DDR_PHY_ADR_G_REGSET_NUM_G2M] = {
-	/*0b80*/ 0x00000001U,
-	/*0b81*/ 0x00000000U,
-	/*0b82*/ 0x00000005U,
-	/*0b83*/ 0x04000f00U,
-	/*0b84*/ 0x00020080U,
-	/*0b85*/ 0x00020055U,
-	/*0b86*/ 0x00000000U,
-	/*0b87*/ 0x00000000U,
-	/*0b88*/ 0x00000000U,
-	/*0b89*/ 0x00000050U,
-	/*0b8a*/ 0x00000000U,
-	/*0b8b*/ 0x01010100U,
-	/*0b8c*/ 0x00000600U,
-	/*0b8d*/ 0x50640000U,
-	/*0b8e*/ 0x01421142U,
-	/*0b8f*/ 0x00000142U,
-	/*0b90*/ 0x00000000U,
-	/*0b91*/ 0x000f1600U,
-	/*0b92*/ 0x0f160f16U,
-	/*0b93*/ 0x0f160f16U,
-	/*0b94*/ 0x00000003U,
-	/*0b95*/ 0x0002c000U,
-	/*0b96*/ 0x02c002c0U,
-	/*0b97*/ 0x000002c0U,
-	/*0b98*/ 0x03421342U,
-	/*0b99*/ 0x00000342U,
-	/*0b9a*/ 0x00000000U,
-	/*0b9b*/ 0x00000000U,
-	/*0b9c*/ 0x05020000U,
-	/*0b9d*/ 0x00000000U,
-	/*0b9e*/ 0x00027f6eU,
-	/*0b9f*/ 0x047f027fU,
-	/*0ba0*/ 0x00027f6eU,
-	/*0ba1*/ 0x00047f6eU,
-	/*0ba2*/ 0x0003554fU,
-	/*0ba3*/ 0x0001554fU,
-	/*0ba4*/ 0x0001554fU,
-	/*0ba5*/ 0x0001554fU,
-	/*0ba6*/ 0x0001554fU,
-	/*0ba7*/ 0x00003feeU,
-	/*0ba8*/ 0x0001554fU,
-	/*0ba9*/ 0x00003feeU,
-	/*0baa*/ 0x0001554fU,
-	/*0bab*/ 0x00027f6eU,
-	/*0bac*/ 0x0001554fU,
-	/*0bad*/ 0x00000000U,
-	/*0bae*/ 0x00000000U,
-	/*0baf*/ 0x00000000U,
-	/*0bb0*/ 0x65000000U,
-	/*0bb1*/ 0x00000000U,
-	/*0bb2*/ 0x00000000U,
-	/*0bb3*/ 0x00000201U,
-	/*0bb4*/ 0x00000000U,
-	/*0bb5*/ 0x00000000U,
-	/*0bb6*/ 0x00000000U,
-	/*0bb7*/ 0x00000000U,
-	/*0bb8*/ 0x00000000U,
-	/*0bb9*/ 0x00000000U,
-	/*0bba*/ 0x00000000U,
-	/*0bbb*/ 0x00000000U,
-	/*0bbc*/ 0x06e40000U,
-	/*0bbd*/ 0x00000000U,
-	/*0bbe*/ 0x00000000U,
-	/*0bbf*/ 0x00010000U
-};
-
-static const uint32_t DDR_PI_REGSET_G2M[DDR_PI_REGSET_NUM_G2M] = {
-	/*0200*/ 0x00000b00U,
-	/*0201*/ 0x00000100U,
-	/*0202*/ 0x00000000U,
-	/*0203*/ 0x0000ffffU,
-	/*0204*/ 0x00000000U,
-	/*0205*/ 0x0000ffffU,
-	/*0206*/ 0x00000000U,
-	/*0207*/ 0x304cffffU,
-	/*0208*/ 0x00000200U,
-	/*0209*/ 0x00000200U,
-	/*020a*/ 0x00000200U,
-	/*020b*/ 0x00000200U,
-	/*020c*/ 0x0000304cU,
-	/*020d*/ 0x00000200U,
-	/*020e*/ 0x00000200U,
-	/*020f*/ 0x00000200U,
-	/*0210*/ 0x00000200U,
-	/*0211*/ 0x0000304cU,
-	/*0212*/ 0x00000200U,
-	/*0213*/ 0x00000200U,
-	/*0214*/ 0x00000200U,
-	/*0215*/ 0x00000200U,
-	/*0216*/ 0x00010000U,
-	/*0217*/ 0x00000003U,
-	/*0218*/ 0x01000001U,
-	/*0219*/ 0x00000000U,
-	/*021a*/ 0x00000000U,
-	/*021b*/ 0x00000000U,
-	/*021c*/ 0x00000000U,
-	/*021d*/ 0x00000000U,
-	/*021e*/ 0x00000000U,
-	/*021f*/ 0x00000000U,
-	/*0220*/ 0x00000000U,
-	/*0221*/ 0x00000000U,
-	/*0222*/ 0x00000000U,
-	/*0223*/ 0x00000000U,
-	/*0224*/ 0x00000000U,
-	/*0225*/ 0x00000000U,
-	/*0226*/ 0x00000000U,
-	/*0227*/ 0x00000000U,
-	/*0228*/ 0x00000000U,
-	/*0229*/ 0x0f000101U,
-	/*022a*/ 0x08492d25U,
-	/*022b*/ 0x0e0c0004U,
-	/*022c*/ 0x000e5000U,
-	/*022d*/ 0x00000250U,
-	/*022e*/ 0x00460003U,
-	/*022f*/ 0x182600cfU,
-	/*0230*/ 0x182600cfU,
-	/*0231*/ 0x00000005U,
-	/*0232*/ 0x00000000U,
-	/*0233*/ 0x00000000U,
-	/*0234*/ 0x00000000U,
-	/*0235*/ 0x00000000U,
-	/*0236*/ 0x00000000U,
-	/*0237*/ 0x00000000U,
-	/*0238*/ 0x00000000U,
-	/*0239*/ 0x01000000U,
-	/*023a*/ 0x00040404U,
-	/*023b*/ 0x01280a00U,
-	/*023c*/ 0x00000000U,
-	/*023d*/ 0x000f0000U,
-	/*023e*/ 0x00001803U,
-	/*023f*/ 0x00000000U,
-	/*0240*/ 0x00000000U,
-	/*0241*/ 0x00060002U,
-	/*0242*/ 0x00010001U,
-	/*0243*/ 0x01000101U,
-	/*0244*/ 0x04020201U,
-	/*0245*/ 0x00080804U,
-	/*0246*/ 0x00000000U,
-	/*0247*/ 0x08030000U,
-	/*0248*/ 0x15150408U,
-	/*0249*/ 0x00000000U,
-	/*024a*/ 0x00000000U,
-	/*024b*/ 0x00000000U,
-	/*024c*/ 0x000f0f00U,
-	/*024d*/ 0x0000001eU,
-	/*024e*/ 0x00000000U,
-	/*024f*/ 0x01000300U,
-	/*0250*/ 0x00000000U,
-	/*0251*/ 0x00000000U,
-	/*0252*/ 0x01000000U,
-	/*0253*/ 0x00010101U,
-	/*0254*/ 0x000e0e0eU,
-	/*0255*/ 0x000c0c0cU,
-	/*0256*/ 0x02060601U,
-	/*0257*/ 0x00000000U,
-	/*0258*/ 0x00000003U,
-	/*0259*/ 0x00181703U,
-	/*025a*/ 0x00280006U,
-	/*025b*/ 0x00280016U,
-	/*025c*/ 0x00000016U,
-	/*025d*/ 0x00000000U,
-	/*025e*/ 0x00000000U,
-	/*025f*/ 0x00000000U,
-	/*0260*/ 0x140a0000U,
-	/*0261*/ 0x0005010aU,
-	/*0262*/ 0x03018d03U,
-	/*0263*/ 0x000a018dU,
-	/*0264*/ 0x00060100U,
-	/*0265*/ 0x01000006U,
-	/*0266*/ 0x018e018eU,
-	/*0267*/ 0x018e0100U,
-	/*0268*/ 0x1111018eU,
-	/*0269*/ 0x10010204U,
-	/*026a*/ 0x09090650U,
-	/*026b*/ 0x20110202U,
-	/*026c*/ 0x00201000U,
-	/*026d*/ 0x00201000U,
-	/*026e*/ 0x04041000U,
-	/*026f*/ 0x18020100U,
-	/*0270*/ 0x00010118U,
-	/*0271*/ 0x004b004aU,
-	/*0272*/ 0x050f0000U,
-	/*0273*/ 0x0c01021eU,
-	/*0274*/ 0x34000000U,
-	/*0275*/ 0x00000000U,
-	/*0276*/ 0x00000000U,
-	/*0277*/ 0x00000000U,
-	/*0278*/ 0x0000d400U,
-	/*0279*/ 0x0031002eU,
-	/*027a*/ 0x00111136U,
-	/*027b*/ 0x002e00d4U,
-	/*027c*/ 0x11360031U,
-	/*027d*/ 0x0000d411U,
-	/*027e*/ 0x0031002eU,
-	/*027f*/ 0x00111136U,
-	/*0280*/ 0x002e00d4U,
-	/*0281*/ 0x11360031U,
-	/*0282*/ 0x0000d411U,
-	/*0283*/ 0x0031002eU,
-	/*0284*/ 0x00111136U,
-	/*0285*/ 0x002e00d4U,
-	/*0286*/ 0x11360031U,
-	/*0287*/ 0x00d40011U,
-	/*0288*/ 0x0031002eU,
-	/*0289*/ 0x00111136U,
-	/*028a*/ 0x002e00d4U,
-	/*028b*/ 0x11360031U,
-	/*028c*/ 0x0000d411U,
-	/*028d*/ 0x0031002eU,
-	/*028e*/ 0x00111136U,
-	/*028f*/ 0x002e00d4U,
-	/*0290*/ 0x11360031U,
-	/*0291*/ 0x0000d411U,
-	/*0292*/ 0x0031002eU,
-	/*0293*/ 0x00111136U,
-	/*0294*/ 0x002e00d4U,
-	/*0295*/ 0x11360031U,
-	/*0296*/ 0x02000011U,
-	/*0297*/ 0x018d018dU,
-	/*0298*/ 0x0c08018dU,
-	/*0299*/ 0x1f121d22U,
-	/*029a*/ 0x4301b344U,
-	/*029b*/ 0x10172006U,
-	/*029c*/ 0x1d220c10U,
-	/*029d*/ 0x00001f12U,
-	/*029e*/ 0x4301b344U,
-	/*029f*/ 0x10172006U,
-	/*02a0*/ 0x1d220c10U,
-	/*02a1*/ 0x00001f12U,
-	/*02a2*/ 0x4301b344U,
-	/*02a3*/ 0x10172006U,
-	/*02a4*/ 0x02000210U,
-	/*02a5*/ 0x02000200U,
-	/*02a6*/ 0x02000200U,
-	/*02a7*/ 0x02000200U,
-	/*02a8*/ 0x02000200U,
-	/*02a9*/ 0x00000000U,
-	/*02aa*/ 0x00000000U,
-	/*02ab*/ 0x00000000U,
-	/*02ac*/ 0x00000000U,
-	/*02ad*/ 0x00000000U,
-	/*02ae*/ 0x00000000U,
-	/*02af*/ 0x00000000U,
-	/*02b0*/ 0x00000000U,
-	/*02b1*/ 0x00000000U,
-	/*02b2*/ 0x00000000U,
-	/*02b3*/ 0x00000000U,
-	/*02b4*/ 0x00000000U,
-	/*02b5*/ 0x00000400U,
-	/*02b6*/ 0x15141312U,
-	/*02b7*/ 0x11100f0eU,
-	/*02b8*/ 0x080b0c0dU,
-	/*02b9*/ 0x05040a09U,
-	/*02ba*/ 0x01000706U,
-	/*02bb*/ 0x00000302U,
-	/*02bc*/ 0x01030201U,
-	/*02bd*/ 0x00304c00U,
-	/*02be*/ 0x0001e2f8U,
-	/*02bf*/ 0x0000304cU,
-	/*02c0*/ 0x0001e2f8U,
-	/*02c1*/ 0x0000304cU,
-	/*02c2*/ 0x0001e2f8U,
-	/*02c3*/ 0x08000000U,
-	/*02c4*/ 0x00000100U,
-	/*02c5*/ 0x00000000U,
-	/*02c6*/ 0x00000000U,
-	/*02c7*/ 0x00000000U,
-	/*02c8*/ 0x00000000U,
-	/*02c9*/ 0x00000002U
-};
-
-#endif /* RZG_INIT_DRAM_TABLE_G2M_H */
diff --git a/drivers/renesas/rzg/ddr/dram_sub_func.h b/drivers/renesas/rzg/ddr/dram_sub_func.h
deleted file mode 100644
index 7affb61..0000000
--- a/drivers/renesas/rzg/ddr/dram_sub_func.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef DRAM_SUB_FUNC_H
-#define DRAM_SUB_FUNC_H
-
-#define DRAM_UPDATE_STATUS_ERR	-1
-#define DRAM_BOOT_STATUS_COLD	0
-#define DRAM_BOOT_STATUS_WARM	1
-
-#endif /* DRAM_SUB_FUNC_H */
diff --git a/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c b/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c
new file mode 100644
index 0000000..663df50
--- /dev/null
+++ b/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c
@@ -0,0 +1,700 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <lib/mmio.h>
+
+#include "pfc_init_g2e.h"
+#include "rcar_def.h"
+
+#include "../pfc_regs.h"
+
+/* PFC */
+#define GPSR0_SDA4		BIT(17)
+#define GPSR0_SCL4		BIT(16)
+#define GPSR0_D15		BIT(15)
+#define GPSR0_D14		BIT(14)
+#define GPSR0_D13		BIT(13)
+#define GPSR0_D12		BIT(12)
+#define GPSR0_D11		BIT(11)
+#define GPSR0_D10		BIT(10)
+#define GPSR0_D9		BIT(9)
+#define GPSR0_D8		BIT(8)
+#define GPSR0_D7		BIT(7)
+#define GPSR0_D6		BIT(6)
+#define GPSR0_D5		BIT(5)
+#define GPSR0_D4		BIT(4)
+#define GPSR0_D3		BIT(3)
+#define GPSR0_D2		BIT(2)
+#define GPSR0_D1		BIT(1)
+#define GPSR0_D0		BIT(0)
+#define GPSR1_WE0		BIT(22)
+#define GPSR1_CS0		BIT(21)
+#define GPSR1_CLKOUT		BIT(20)
+#define GPSR1_A19		BIT(19)
+#define GPSR1_A18		BIT(18)
+#define GPSR1_A17		BIT(17)
+#define GPSR1_A16		BIT(16)
+#define GPSR1_A15		BIT(15)
+#define GPSR1_A14		BIT(14)
+#define GPSR1_A13		BIT(13)
+#define GPSR1_A12		BIT(12)
+#define GPSR1_A11		BIT(11)
+#define GPSR1_A10		BIT(10)
+#define GPSR1_A9		BIT(9)
+#define GPSR1_A8		BIT(8)
+#define GPSR1_A7		BIT(7)
+#define GPSR1_A6		BIT(6)
+#define GPSR1_A5		BIT(5)
+#define GPSR1_A4		BIT(4)
+#define GPSR1_A3		BIT(3)
+#define GPSR1_A2		BIT(2)
+#define GPSR1_A1		BIT(1)
+#define GPSR1_A0		BIT(0)
+#define GPSR2_BIT27_REVERSED	BIT(27)
+#define GPSR2_BIT26_REVERSED	BIT(26)
+#define GPSR2_EX_WAIT0		BIT(25)
+#define GPSR2_RD_WR		BIT(24)
+#define GPSR2_RD		BIT(23)
+#define GPSR2_BS		BIT(22)
+#define GPSR2_AVB_PHY_INT	BIT(21)
+#define GPSR2_AVB_TXCREFCLK	BIT(20)
+#define GPSR2_AVB_RD3		BIT(19)
+#define GPSR2_AVB_RD2		BIT(18)
+#define GPSR2_AVB_RD1		BIT(17)
+#define GPSR2_AVB_RD0		BIT(16)
+#define GPSR2_AVB_RXC		BIT(15)
+#define GPSR2_AVB_RX_CTL	BIT(14)
+#define GPSR2_RPC_RESET		BIT(13)
+#define GPSR2_RPC_RPC_INT	BIT(12)
+#define GPSR2_QSPI1_SSL		BIT(11)
+#define GPSR2_QSPI1_IO3		BIT(10)
+#define GPSR2_QSPI1_IO2		BIT(9)
+#define GPSR2_QSPI1_MISO_IO1	BIT(8)
+#define GPSR2_QSPI1_MOSI_IO0	BIT(7)
+#define GPSR2_QSPI1_SPCLK	BIT(6)
+#define GPSR2_QSPI0_SSL		BIT(5)
+#define GPSR2_QSPI0_IO3		BIT(4)
+#define GPSR2_QSPI0_IO2		BIT(3)
+#define GPSR2_QSPI0_MISO_IO1	BIT(2)
+#define GPSR2_QSPI0_MOSI_IO0	BIT(1)
+#define GPSR2_QSPI0_SPCLK	BIT(0)
+#define GPSR3_SD1_WP		BIT(15)
+#define GPSR3_SD1_CD		BIT(14)
+#define GPSR3_SD0_WP		BIT(13)
+#define GPSR3_SD0_CD		BIT(12)
+#define GPSR3_SD1_DAT3		BIT(11)
+#define GPSR3_SD1_DAT2		BIT(10)
+#define GPSR3_SD1_DAT1		BIT(9)
+#define GPSR3_SD1_DAT0		BIT(8)
+#define GPSR3_SD1_CMD		BIT(7)
+#define GPSR3_SD1_CLK		BIT(6)
+#define GPSR3_SD0_DAT3		BIT(5)
+#define GPSR3_SD0_DAT2		BIT(4)
+#define GPSR3_SD0_DAT1		BIT(3)
+#define GPSR3_SD0_DAT0		BIT(2)
+#define GPSR3_SD0_CMD		BIT(1)
+#define GPSR3_SD0_CLK		BIT(0)
+#define GPSR4_SD3_DS		BIT(10)
+#define GPSR4_SD3_DAT7		BIT(9)
+#define GPSR4_SD3_DAT6		BIT(8)
+#define GPSR4_SD3_DAT5		BIT(7)
+#define GPSR4_SD3_DAT4		BIT(6)
+#define GPSR4_SD3_DAT3		BIT(5)
+#define GPSR4_SD3_DAT2		BIT(4)
+#define GPSR4_SD3_DAT1		BIT(3)
+#define GPSR4_SD3_DAT0		BIT(2)
+#define GPSR4_SD3_CMD		BIT(1)
+#define GPSR4_SD3_CLK		BIT(0)
+#define GPSR5_MLB_DAT		BIT(19)
+#define GPSR5_MLB_SIG		BIT(18)
+#define GPSR5_MLB_CLK		BIT(17)
+#define GPSR5_SSI_SDATA9	BIT(16)
+#define GPSR5_MSIOF0_SS2	BIT(15)
+#define GPSR5_MSIOF0_SS1	BIT(14)
+#define GPSR5_MSIOF0_SYNC	BIT(13)
+#define GPSR5_MSIOF0_TXD	BIT(12)
+#define GPSR5_MSIOF0_RXD	BIT(11)
+#define GPSR5_MSIOF0_SCK	BIT(10)
+#define GPSR5_RX2_A		BIT(9)
+#define GPSR5_TX2_A		BIT(8)
+#define GPSR5_SCK2_A		BIT(7)
+#define GPSR5_TX1		BIT(6)
+#define GPSR5_RX1		BIT(5)
+#define GPSR5_RTS0_A		BIT(4)
+#define GPSR5_CTS0_A		BIT(3)
+#define GPSR5_TX0_A		BIT(2)
+#define GPSR5_RX0_A		BIT(1)
+#define GPSR5_SCK0_A		BIT(0)
+#define GPSR6_USB30_PWEN	BIT(17)
+#define GPSR6_SSI_SDATA6	BIT(16)
+#define GPSR6_SSI_WS6		BIT(15)
+#define GPSR6_SSI_SCK6		BIT(14)
+#define GPSR6_SSI_SDATA5	BIT(13)
+#define GPSR6_SSI_WS5		BIT(12)
+#define GPSR6_SSI_SCK5		BIT(11)
+#define GPSR6_SSI_SDATA4	BIT(10)
+#define GPSR6_USB30_OVC		BIT(9)
+#define GPSR6_AUDIO_CLKA	BIT(8)
+#define GPSR6_SSI_SDATA3	BIT(7)
+#define GPSR6_SSI_WS349		BIT(6)
+#define GPSR6_SSI_SCK349	BIT(5)
+#define GPSR6_SSI_SDATA2	BIT(4)
+#define GPSR6_SSI_SDATA1	BIT(3)
+#define GPSR6_SSI_SDATA0	BIT(2)
+#define GPSR6_SSI_WS01239	BIT(1)
+#define GPSR6_SSI_SCK01239	BIT(0)
+
+#define IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
+
+#define POCCTRL0_MASK		(0x0007F000U)
+#define POC_SD3_DS_33V		BIT(29)
+#define POC_SD3_DAT7_33V	BIT(28)
+#define POC_SD3_DAT6_33V	BIT(27)
+#define POC_SD3_DAT5_33V	BIT(26)
+#define POC_SD3_DAT4_33V	BIT(25)
+#define POC_SD3_DAT3_33V	BIT(24)
+#define POC_SD3_DAT2_33V	BIT(23)
+#define POC_SD3_DAT1_33V	BIT(22)
+#define POC_SD3_DAT0_33V	BIT(21)
+#define POC_SD3_CMD_33V		BIT(20)
+#define POC_SD3_CLK_33V		BIT(19)
+#define POC_SD1_DAT3_33V	BIT(11)
+#define POC_SD1_DAT2_33V	BIT(10)
+#define POC_SD1_DAT1_33V	BIT(9)
+#define POC_SD1_DAT0_33V	BIT(8)
+#define POC_SD1_CMD_33V		BIT(7)
+#define POC_SD1_CLK_33V		BIT(6)
+#define POC_SD0_DAT3_33V	BIT(5)
+#define POC_SD0_DAT2_33V	BIT(4)
+#define POC_SD0_DAT1_33V	BIT(3)
+#define POC_SD0_DAT0_33V	BIT(2)
+#define POC_SD0_CMD_33V		BIT(1)
+#define POC_SD0_CLK_33V		BIT(0)
+
+#define POCCTRL2_MASK		(0xFFFFFFFEU)
+#define POC2_VREF_33V		BIT(0)
+
+#define MOD_SEL0_ADGB_A			((uint32_t)0U << 29U)
+#define MOD_SEL0_ADGB_B			((uint32_t)1U << 29U)
+#define MOD_SEL0_ADGB_C			((uint32_t)2U << 29U)
+#define MOD_SEL0_DRIF0_A		((uint32_t)0U << 28U)
+#define MOD_SEL0_DRIF0_B		((uint32_t)1U << 28U)
+#define MOD_SEL0_FM_A			((uint32_t)0U << 26U)
+#define MOD_SEL0_FM_B			((uint32_t)1U << 26U)
+#define MOD_SEL0_FM_C			((uint32_t)2U << 26U)
+#define MOD_SEL0_FSO_A			((uint32_t)0U << 25U)
+#define MOD_SEL0_FSO_B			((uint32_t)1U << 25U)
+#define MOD_SEL0_HSCIF0_A		((uint32_t)0U << 24U)
+#define MOD_SEL0_HSCIF0_B		((uint32_t)1U << 24U)
+#define MOD_SEL0_HSCIF1_A		((uint32_t)0U << 23U)
+#define MOD_SEL0_HSCIF1_B		((uint32_t)1U << 23U)
+#define MOD_SEL0_HSCIF2_A		((uint32_t)0U << 22U)
+#define MOD_SEL0_HSCIF2_B		((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C1_A			((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B			((uint32_t)1U << 20U)
+#define MOD_SEL0_I2C1_C			((uint32_t)2U << 20U)
+#define MOD_SEL0_I2C1_D			((uint32_t)3U << 20U)
+#define MOD_SEL0_I2C2_A			((uint32_t)0U << 17U)
+#define MOD_SEL0_I2C2_B			((uint32_t)1U << 17U)
+#define MOD_SEL0_I2C2_C			((uint32_t)2U << 17U)
+#define MOD_SEL0_I2C2_D			((uint32_t)3U << 17U)
+#define MOD_SEL0_I2C2_E			((uint32_t)4U << 17U)
+#define MOD_SEL0_NDFC_A			((uint32_t)0U << 16U)
+#define MOD_SEL0_NDFC_B			((uint32_t)1U << 16U)
+#define MOD_SEL0_PWM0_A			((uint32_t)0U << 15U)
+#define MOD_SEL0_PWM0_B			((uint32_t)1U << 15U)
+#define MOD_SEL0_PWM1_A			((uint32_t)0U << 14U)
+#define MOD_SEL0_PWM1_B			((uint32_t)1U << 14U)
+#define MOD_SEL0_PWM2_A			((uint32_t)0U << 12U)
+#define MOD_SEL0_PWM2_B			((uint32_t)1U << 12U)
+#define MOD_SEL0_PWM2_C			((uint32_t)2U << 12U)
+#define MOD_SEL0_PWM3_A			((uint32_t)0U << 10U)
+#define MOD_SEL0_PWM3_B			((uint32_t)1U << 10U)
+#define MOD_SEL0_PWM3_C			((uint32_t)2U << 10U)
+#define MOD_SEL0_PWM4_A			((uint32_t)0U << 9U)
+#define MOD_SEL0_PWM4_B			((uint32_t)1U << 9U)
+#define MOD_SEL0_PWM5_A			((uint32_t)0U << 8U)
+#define MOD_SEL0_PWM5_B			((uint32_t)1U << 8U)
+#define MOD_SEL0_PWM6_A			((uint32_t)0U << 7U)
+#define MOD_SEL0_PWM6_B			((uint32_t)1U << 7U)
+#define MOD_SEL0_REMOCON_A		((uint32_t)0U << 5U)
+#define MOD_SEL0_REMOCON_B		((uint32_t)1U << 5U)
+#define MOD_SEL0_REMOCON_C		((uint32_t)2U << 5U)
+#define MOD_SEL0_SCIF_A			((uint32_t)0U << 4U)
+#define MOD_SEL0_SCIF_B			((uint32_t)1U << 4U)
+#define MOD_SEL0_SCIF0_A		((uint32_t)0U << 3U)
+#define MOD_SEL0_SCIF0_B		((uint32_t)1U << 3U)
+#define MOD_SEL0_SCIF2_A		((uint32_t)0U << 2U)
+#define MOD_SEL0_SCIF2_B		((uint32_t)1U << 2U)
+#define MOD_SEL0_SPEED_PULSE_IF_A	((uint32_t)0U << 0U)
+#define MOD_SEL0_SPEED_PULSE_IF_B	((uint32_t)1U << 0U)
+#define MOD_SEL0_SPEED_PULSE_IF_C	((uint32_t)2U << 0U)
+#define MOD_SEL1_SIMCARD_A		((uint32_t)0U << 31U)
+#define MOD_SEL1_SIMCARD_B		((uint32_t)1U << 31U)
+#define MOD_SEL1_SSI2_A			((uint32_t)0U << 30U)
+#define MOD_SEL1_SSI2_B			((uint32_t)1U << 30U)
+#define MOD_SEL1_TIMER_TMU_A		((uint32_t)0U << 29U)
+#define MOD_SEL1_TIMER_TMU_B		((uint32_t)1U << 29U)
+#define MOD_SEL1_USB20_CH0_A		((uint32_t)0U << 28U)
+#define MOD_SEL1_USB20_CH0_B		((uint32_t)1U << 28U)
+#define MOD_SEL1_DRIF2_A		((uint32_t)0U << 26U)
+#define MOD_SEL1_DRIF2_B		((uint32_t)1U << 26U)
+#define MOD_SEL1_DRIF3_A		((uint32_t)0U << 25U)
+#define MOD_SEL1_DRIF3_B		((uint32_t)1U << 25U)
+#define MOD_SEL1_HSCIF3_A		((uint32_t)0U << 22U)
+#define MOD_SEL1_HSCIF3_B		((uint32_t)1U << 22U)
+#define MOD_SEL1_HSCIF3_C		((uint32_t)2U << 22U)
+#define MOD_SEL1_HSCIF3_D		((uint32_t)3U << 22U)
+#define MOD_SEL1_HSCIF3_E		((uint32_t)4U << 22U)
+#define MOD_SEL1_HSCIF4_A		((uint32_t)0U << 19U)
+#define MOD_SEL1_HSCIF4_B		((uint32_t)1U << 19U)
+#define MOD_SEL1_HSCIF4_C		((uint32_t)2U << 19U)
+#define MOD_SEL1_HSCIF4_D		((uint32_t)3U << 19U)
+#define MOD_SEL1_HSCIF4_E		((uint32_t)4U << 19U)
+#define MOD_SEL1_I2C6_A			((uint32_t)0U << 18U)
+#define MOD_SEL1_I2C6_B			((uint32_t)1U << 18U)
+#define MOD_SEL1_I2C7_A			((uint32_t)0U << 17U)
+#define MOD_SEL1_I2C7_B			((uint32_t)1U << 17U)
+#define MOD_SEL1_MSIOF2_A		((uint32_t)0U << 16U)
+#define MOD_SEL1_MSIOF2_B		((uint32_t)1U << 16U)
+#define MOD_SEL1_MSIOF3_A		((uint32_t)0U << 15U)
+#define MOD_SEL1_MSIOF3_B		((uint32_t)1U << 15U)
+#define MOD_SEL1_SCIF3_A		((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B		((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF3_C		((uint32_t)2U << 13U)
+#define MOD_SEL1_SCIF4_A		((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF4_B		((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF4_C		((uint32_t)2U << 11U)
+#define MOD_SEL1_SCIF5_A		((uint32_t)0U << 9U)
+#define MOD_SEL1_SCIF5_B		((uint32_t)1U << 9U)
+#define MOD_SEL1_SCIF5_C		((uint32_t)2U << 9U)
+#define MOD_SEL1_VIN4_A			((uint32_t)0U << 8U)
+#define MOD_SEL1_VIN4_B			((uint32_t)1U << 8U)
+#define MOD_SEL1_VIN5_A			((uint32_t)0U << 7U)
+#define MOD_SEL1_VIN5_B			((uint32_t)1U << 7U)
+#define MOD_SEL1_ADGC_A			((uint32_t)0U << 5U)
+#define MOD_SEL1_ADGC_B			((uint32_t)1U << 5U)
+#define MOD_SEL1_ADGC_C			((uint32_t)2U << 5U)
+#define MOD_SEL1_SSI9_A			((uint32_t)0U << 4U)
+#define MOD_SEL1_SSI9_B			((uint32_t)1U << 4U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	mmio_write_32(PFC_PMMR, ~data);
+	mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_g2e(void)
+{
+	uint32_t reg;
+
+	/* initialize module select */
+	pfc_reg_write(PFC_MOD_SEL0,
+		      MOD_SEL0_ADGB_A |
+		      MOD_SEL0_DRIF0_A |
+		      MOD_SEL0_FM_A |
+		      MOD_SEL0_FSO_A |
+		      MOD_SEL0_HSCIF0_A |
+		      MOD_SEL0_HSCIF1_A |
+		      MOD_SEL0_HSCIF2_A |
+		      MOD_SEL0_I2C1_A |
+		      MOD_SEL0_I2C2_A |
+		      MOD_SEL0_NDFC_A |
+		      MOD_SEL0_PWM0_A |
+		      MOD_SEL0_PWM1_A |
+		      MOD_SEL0_PWM2_A |
+		      MOD_SEL0_PWM3_A |
+		      MOD_SEL0_PWM4_A |
+		      MOD_SEL0_PWM5_A |
+		      MOD_SEL0_PWM6_A |
+		      MOD_SEL0_REMOCON_A |
+		      MOD_SEL0_SCIF_A |
+		      MOD_SEL0_SCIF0_A |
+		      MOD_SEL0_SCIF2_A |
+		      MOD_SEL0_SPEED_PULSE_IF_A);
+
+	pfc_reg_write(PFC_MOD_SEL1,
+		      MOD_SEL1_SIMCARD_A |
+		      MOD_SEL1_SSI2_A |
+		      MOD_SEL1_TIMER_TMU_A |
+		      MOD_SEL1_USB20_CH0_B |
+		      MOD_SEL1_DRIF2_A |
+		      MOD_SEL1_DRIF3_A |
+		      MOD_SEL1_HSCIF3_C |
+		      MOD_SEL1_HSCIF4_B |
+		      MOD_SEL1_I2C6_A |
+		      MOD_SEL1_I2C7_A |
+		      MOD_SEL1_MSIOF2_A |
+		      MOD_SEL1_MSIOF3_A |
+		      MOD_SEL1_SCIF3_A |
+		      MOD_SEL1_SCIF4_A |
+		      MOD_SEL1_SCIF5_A |
+		      MOD_SEL1_VIN4_A |
+		      MOD_SEL1_VIN5_A |
+		      MOD_SEL1_ADGC_A |
+		      MOD_SEL1_SSI9_A);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0,
+		      IPSR_28_FUNC(2) |	/* HRX4_B */
+		      IPSR_24_FUNC(2) |	/* HTX4_B */
+		      IPSR_20_FUNC(0) |	/* QSPI1_SPCLK */
+		      IPSR_16_FUNC(0) |	/* QSPI0_IO3 */
+		      IPSR_12_FUNC(0) |	/* QSPI0_IO2 */
+		      IPSR_8_FUNC(0) |	/* QSPI0_MISO/IO1 */
+		      IPSR_4_FUNC(0) |	/* QSPI0_MOSI/IO0 */
+		      IPSR_0_FUNC(0));	/* QSPI0_SPCLK */
+
+	pfc_reg_write(PFC_IPSR1,
+		      IPSR_28_FUNC(0) |	/* AVB_RD2 */
+		      IPSR_24_FUNC(0) |	/* AVB_RD1 */
+		      IPSR_20_FUNC(0) |	/* AVB_RD0 */
+		      IPSR_16_FUNC(0) |	/* RPC_RESET# */
+		      IPSR_12_FUNC(0) |	/* RPC_INT# */
+		      IPSR_8_FUNC(0) |	/* QSPI1_SSL */
+		      IPSR_4_FUNC(2) |	/* HRX3_C */
+		      IPSR_0_FUNC(2));	/* HTX3_C */
+
+	pfc_reg_write(PFC_IPSR2,
+		      IPSR_28_FUNC(1) |	/* IRQ0 */
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(2) |	/* AVB_LINK */
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |	/* AVB_MDC */
+		      IPSR_4_FUNC(0) |	/* AVB_MDIO */
+		      IPSR_0_FUNC(0));	/* AVB_TXCREFCLK */
+
+	pfc_reg_write(PFC_IPSR3,
+		      IPSR_28_FUNC(5) |	/* DU_HSYNC */
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(5) |	/* DU_DG4 */
+		      IPSR_8_FUNC(5) |	/* DU_DOTCLKOUT0 */
+		      IPSR_4_FUNC(5) |	/* DU_DISP */
+		      IPSR_0_FUNC(1));	/* IRQ1 */
+
+	pfc_reg_write(PFC_IPSR4,
+		      IPSR_28_FUNC(5) |	/* DU_DB5 */
+		      IPSR_24_FUNC(5) |	/* DU_DB4 */
+		      IPSR_20_FUNC(5) |	/* DU_DB3 */
+		      IPSR_16_FUNC(5) |	/* DU_DB2 */
+		      IPSR_12_FUNC(5) |	/* DU_DG6 */
+		      IPSR_8_FUNC(5) |	/* DU_VSYNC */
+		      IPSR_4_FUNC(5) |	/* DU_DG5 */
+		      IPSR_0_FUNC(5));	/* DU_DG7 */
+
+	pfc_reg_write(PFC_IPSR5,
+		      IPSR_28_FUNC(5) |	/* DU_DR3 */
+		      IPSR_24_FUNC(5) |	/* DU_DB7 */
+		      IPSR_20_FUNC(5) |	/* DU_DR2 */
+		      IPSR_16_FUNC(5) |	/* DU_DR1 */
+		      IPSR_12_FUNC(5) |	/* DU_DR0 */
+		      IPSR_8_FUNC(5) |	/* DU_DB1 */
+		      IPSR_4_FUNC(5) |	/* DU_DB0 */
+		      IPSR_0_FUNC(5));	/* DU_DB6 */
+
+	pfc_reg_write(PFC_IPSR6,
+		      IPSR_28_FUNC(5) |	/* DU_DG1 */
+		      IPSR_24_FUNC(5) |	/* DU_DG0 */
+		      IPSR_20_FUNC(5) |	/* DU_DR7 */
+		      IPSR_16_FUNC(1) |	/* CANFD1_RX */
+		      IPSR_12_FUNC(5) |	/* DU_DR6 */
+		      IPSR_8_FUNC(5) |	/* DU_DR5 */
+		      IPSR_4_FUNC(1) |	/* CANFD1_TX */
+		      IPSR_0_FUNC(5));	/* DU_DR4 */
+
+	pfc_reg_write(PFC_IPSR7,
+		      IPSR_28_FUNC(0) |	/* SD0_CLK */
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(5) |	/* DU_DOTCLKIN0 */
+		      IPSR_16_FUNC(5) |	/* DU_DG3 */
+		      IPSR_12_FUNC(1) |	/* CAN_CLK */
+		      IPSR_8_FUNC(1) |	/* CANFD0_RX */
+		      IPSR_4_FUNC(1) |	/* CANFD0_TX */
+		      IPSR_0_FUNC(5));	/* DU_DG2 */
+
+	pfc_reg_write(PFC_IPSR8,
+		      IPSR_28_FUNC(0) |	/* SD1_DAT0 */
+		      IPSR_24_FUNC(0) |	/* SD1_CMD */
+		      IPSR_20_FUNC(0) |	/* SD1_CLK */
+		      IPSR_16_FUNC(0) |	/* SD0_DAT3 */
+		      IPSR_12_FUNC(0) |	/* SD0_DAT2 */
+		      IPSR_8_FUNC(0) |	/* SD0_DAT1 */
+		      IPSR_4_FUNC(0) |	/* SD0_DAT0 */
+		      IPSR_0_FUNC(0));	/* SD0_CMD */
+
+	pfc_reg_write(PFC_IPSR9,
+		      IPSR_28_FUNC(0) |	/* SD3_DAT2 */
+		      IPSR_24_FUNC(0) |	/* SD3_DAT1 */
+		      IPSR_20_FUNC(0) |	/* SD3_DAT0 */
+		      IPSR_16_FUNC(0) |	/* SD3_CMD */
+		      IPSR_12_FUNC(0) |	/* SD3_CLK */
+		      IPSR_8_FUNC(0) |	/* SD1_DAT3 */
+		      IPSR_4_FUNC(0) |	/* SD1_DAT2 */
+		      IPSR_0_FUNC(0));	/* SD1_DAT1 */
+
+	pfc_reg_write(PFC_IPSR10,
+		      IPSR_24_FUNC(0) |	/* SD0_CD */
+		      IPSR_20_FUNC(0) |	/* SD3_DS */
+		      IPSR_16_FUNC(0) |	/* SD3_DAT7 */
+		      IPSR_12_FUNC(0) |	/* SD3_DAT6 */
+		      IPSR_8_FUNC(0) |	/* SD3_DAT5 */
+		      IPSR_4_FUNC(0) |	/* SD3_DAT4 */
+		      IPSR_0_FUNC(0));	/* SD3_DAT3 */
+
+	pfc_reg_write(PFC_IPSR11,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(8) |	/* USB0_ID */
+		      IPSR_20_FUNC(2) |	/* AUDIO_CLKOUT1_A */
+		      IPSR_16_FUNC(0) |	/* CTS0#_A */
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |	/* SD1_WP */
+		      IPSR_0_FUNC(0));	/* SD1_CD */
+
+	pfc_reg_write(PFC_IPSR12,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |	/* RX2_A */
+		      IPSR_8_FUNC(0) |	/* TX2_A */
+		      IPSR_4_FUNC(0) |	/* SCK2_A */
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR13,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(4) |	/* SDA1_B */
+		      IPSR_12_FUNC(4) |	/* SCL1_B */
+		      IPSR_8_FUNC(0) |	/* SSI_SDATA9 */
+		      IPSR_4_FUNC(1) |	/* HTX2_A */
+		      IPSR_0_FUNC(1));	/* HRX2_A */
+
+	pfc_reg_write(PFC_IPSR14,
+		      IPSR_28_FUNC(0) |	/* SSI_SCK5 */
+		      IPSR_24_FUNC(0) |	/* SSI_SDATA4 */
+		      IPSR_20_FUNC(0) |	/* SSI_SDATA3 */
+		      IPSR_16_FUNC(0) |	/* SSI_WS349 */
+		      IPSR_12_FUNC(0) |	/* SSI_SCK349 */
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |	/* SSI_SDATA1 */
+		      IPSR_0_FUNC(0));/* SSI_SDATA0 */
+
+	pfc_reg_write(PFC_IPSR15,
+		      IPSR_28_FUNC(0) |	/* USB30_OVC */
+		      IPSR_24_FUNC(0) |	/* USB30_PWEN */
+		      IPSR_20_FUNC(0) |	/* AUDIO_CLKA */
+		      IPSR_16_FUNC(1) |	/* HRTS2#_A */
+		      IPSR_12_FUNC(1) |	/* HCTS2#_A */
+		      IPSR_8_FUNC(3) |	/* TPU0TO1 */
+		      IPSR_4_FUNC(3) |	/* TPU0TO0 */
+		      IPSR_0_FUNC(0));	/* SSI_WS5 */
+
+	/* initialize GPIO/peripheral function select */
+	pfc_reg_write(PFC_GPSR0,
+		      GPSR0_SCL4 |
+		      GPSR0_D15 |
+		      GPSR0_D14 |
+		      GPSR0_D13 |
+		      GPSR0_D12 |
+		      GPSR0_D11 |
+		      GPSR0_D10 |
+		      GPSR0_D9 |
+		      GPSR0_D8 |
+		      GPSR0_D7 |
+		      GPSR0_D6 |
+		      GPSR0_D5 |
+		      GPSR0_D4 |
+		      GPSR0_D3 |
+		      GPSR0_D2 |
+		      GPSR0_D1 |
+		      GPSR0_D0);
+
+	pfc_reg_write(PFC_GPSR1,
+		      GPSR1_WE0 |
+		      GPSR1_CS0 |
+		      GPSR1_A19 |
+		      GPSR1_A18 |
+		      GPSR1_A17 |
+		      GPSR1_A16 |
+		      GPSR1_A15 |
+		      GPSR1_A14 |
+		      GPSR1_A13 |
+		      GPSR1_A12 |
+		      GPSR1_A11 |
+		      GPSR1_A10 |
+		      GPSR1_A9 |
+		      GPSR1_A8 |
+		      GPSR1_A4 |
+		      GPSR1_A3 |
+		      GPSR1_A2 |
+		      GPSR1_A1 |
+		      GPSR1_A0);
+
+	pfc_reg_write(PFC_GPSR2,
+		      GPSR2_BIT27_REVERSED |
+		      GPSR2_BIT26_REVERSED |
+		      GPSR2_AVB_PHY_INT |
+		      GPSR2_AVB_TXCREFCLK |
+		      GPSR2_AVB_RD3 |
+		      GPSR2_AVB_RD2 |
+		      GPSR2_AVB_RD1 |
+		      GPSR2_AVB_RD0 |
+		      GPSR2_AVB_RXC |
+		      GPSR2_AVB_RX_CTL |
+		      GPSR2_RPC_RESET |
+		      GPSR2_RPC_RPC_INT |
+		      GPSR2_QSPI1_IO3 |
+		      GPSR2_QSPI1_IO2 |
+		      GPSR2_QSPI1_MISO_IO1 |
+		      GPSR2_QSPI1_MOSI_IO0 |
+		      GPSR2_QSPI0_SSL |
+		      GPSR2_QSPI0_IO3 |
+		      GPSR2_QSPI0_IO2 |
+		      GPSR2_QSPI0_MISO_IO1 |
+		      GPSR2_QSPI0_MOSI_IO0 |
+		      GPSR2_QSPI0_SPCLK);
+
+	pfc_reg_write(PFC_GPSR3,
+		      GPSR3_SD0_CD |
+		      GPSR3_SD1_DAT3 |
+		      GPSR3_SD1_DAT2 |
+		      GPSR3_SD1_DAT1 |
+		      GPSR3_SD1_DAT0 |
+		      GPSR3_SD1_CMD |
+		      GPSR3_SD1_CLK |
+		      GPSR3_SD0_DAT3 |
+		      GPSR3_SD0_DAT2 |
+		      GPSR3_SD0_DAT1 |
+		      GPSR3_SD0_DAT0 |
+		      GPSR3_SD0_CMD |
+		      GPSR3_SD0_CLK);
+
+	pfc_reg_write(PFC_GPSR4,
+		      GPSR4_SD3_DAT3 |
+		      GPSR4_SD3_DAT2 |
+		      GPSR4_SD3_DAT1 |
+		      GPSR4_SD3_DAT0 |
+		      GPSR4_SD3_CMD |
+		      GPSR4_SD3_CLK);
+
+	pfc_reg_write(PFC_GPSR5,
+		      GPSR5_MLB_SIG |
+		      GPSR5_MLB_CLK |
+		      GPSR5_SSI_SDATA9 |
+		      GPSR5_MSIOF0_SS2 |
+		      GPSR5_MSIOF0_SS1 |
+		      GPSR5_MSIOF0_SYNC |
+		      GPSR5_MSIOF0_TXD |
+		      GPSR5_MSIOF0_RXD |
+		      GPSR5_MSIOF0_SCK |
+		      GPSR5_RX2_A |
+		      GPSR5_TX2_A |
+		      GPSR5_RTS0_A |
+		      GPSR5_SCK0_A);
+
+	pfc_reg_write(PFC_GPSR6,
+		      GPSR6_USB30_PWEN |
+		      GPSR6_SSI_SDATA6 |
+		      GPSR6_SSI_WS6 |
+		      GPSR6_SSI_SCK6 |
+		      GPSR6_SSI_SDATA5 |
+		      GPSR6_SSI_SCK5 |
+		      GPSR6_SSI_SDATA4 |
+		      GPSR6_USB30_OVC |
+		      GPSR6_AUDIO_CLKA |
+		      GPSR6_SSI_SDATA3 |
+		      GPSR6_SSI_WS349 |
+		      GPSR6_SSI_SCK349 |
+		      GPSR6_SSI_SDATA0 |
+		      GPSR6_SSI_WS01239 |
+		      GPSR6_SSI_SCK01239);
+
+	/* initialize POC control */
+	reg = mmio_read_32(PFC_POCCTRL0);
+	reg = (reg & POCCTRL0_MASK) |
+	      POC_SD1_DAT3_33V |
+	      POC_SD1_DAT2_33V |
+	      POC_SD1_DAT1_33V |
+	      POC_SD1_DAT0_33V |
+	      POC_SD1_CMD_33V |
+	      POC_SD1_CLK_33V |
+	      POC_SD0_DAT3_33V |
+	      POC_SD0_DAT2_33V |
+	      POC_SD0_DAT1_33V |
+	      POC_SD0_DAT0_33V |
+	      POC_SD0_CMD_33V |
+	      POC_SD0_CLK_33V;
+	pfc_reg_write(PFC_POCCTRL0, reg);
+
+	reg = mmio_read_32(PFC_POCCTRL2);
+	reg = ((reg & POCCTRL2_MASK) & ~POC2_VREF_33V);
+	pfc_reg_write(PFC_POCCTRL2, reg);
+
+	/* initialize LSI pin pull-up/down control */
+	pfc_reg_write(PFC_PUD0, 0x00080000U);
+	pfc_reg_write(PFC_PUD1, 0xCE398464U);
+	pfc_reg_write(PFC_PUD2, 0xA4C380F4U);
+	pfc_reg_write(PFC_PUD3, 0x0000079FU);
+	pfc_reg_write(PFC_PUD4, 0xFFF0FFFFU);
+	pfc_reg_write(PFC_PUD5, 0x40000000U);
+
+	/* initialize LSI pin pull-enable register */
+	pfc_reg_write(PFC_PUEN0, 0x00000000U);
+	pfc_reg_write(PFC_PUEN1, 0x00300000U);
+	pfc_reg_write(PFC_PUEN2, 0x00400074U);
+	pfc_reg_write(PFC_PUEN3, 0x00000000U);
+	pfc_reg_write(PFC_PUEN4, 0x07900600U);
+	pfc_reg_write(PFC_PUEN5, 0x00000000U);
+
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT0, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT3, 0x00006000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT6, 0x00000000U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00020000U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x00100000U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x03000000U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x0000E000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00000440U);
+	mmio_write_32(GPIO_INOUTSEL5, 0x00080000U);
+	mmio_write_32(GPIO_INOUTSEL6, 0x00000010U);
+}
diff --git a/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.h b/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.h
new file mode 100644
index 0000000..677591a
--- /dev/null
+++ b/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_G2E_H
+#define PFC_INIT_G2E_H
+
+void pfc_init_g2e(void);
+
+#endif /* PFC_INIT_G2E_H */
diff --git a/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c b/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c
new file mode 100644
index 0000000..90a1c99
--- /dev/null
+++ b/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c
@@ -0,0 +1,1310 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <lib/mmio.h>
+
+#include "pfc_init_g2h.h"
+#include "rcar_def.h"
+#include "../pfc_regs.h"
+
+#define GPSR0_D15			BIT(15)
+#define GPSR0_D14			BIT(14)
+#define GPSR0_D13			BIT(13)
+#define GPSR0_D12			BIT(12)
+#define GPSR0_D11			BIT(11)
+#define GPSR0_D10			BIT(10)
+#define GPSR0_D9			BIT(9)
+#define GPSR0_D8			BIT(8)
+#define GPSR0_D7			BIT(7)
+#define GPSR0_D6			BIT(6)
+#define GPSR0_D5			BIT(5)
+#define GPSR0_D4			BIT(4)
+#define GPSR0_D3			BIT(3)
+#define GPSR0_D2			BIT(2)
+#define GPSR0_D1			BIT(1)
+#define GPSR0_D0			BIT(0)
+#define GPSR1_CLKOUT			BIT(28)
+#define GPSR1_EX_WAIT0_A		BIT(27)
+#define GPSR1_WE1			BIT(26)
+#define GPSR1_WE0			BIT(25)
+#define GPSR1_RD_WR			BIT(24)
+#define GPSR1_RD			BIT(23)
+#define GPSR1_BS			BIT(22)
+#define GPSR1_CS1_A26			BIT(21)
+#define GPSR1_CS0			BIT(20)
+#define GPSR1_A19			BIT(19)
+#define GPSR1_A18			BIT(18)
+#define GPSR1_A17			BIT(17)
+#define GPSR1_A16			BIT(16)
+#define GPSR1_A15			BIT(15)
+#define GPSR1_A14			BIT(14)
+#define GPSR1_A13			BIT(13)
+#define GPSR1_A12			BIT(12)
+#define GPSR1_A11			BIT(11)
+#define GPSR1_A10			BIT(10)
+#define GPSR1_A9			BIT(9)
+#define GPSR1_A8			BIT(8)
+#define GPSR1_A7			BIT(7)
+#define GPSR1_A6			BIT(6)
+#define GPSR1_A5			BIT(5)
+#define GPSR1_A4			BIT(4)
+#define GPSR1_A3			BIT(3)
+#define GPSR1_A2			BIT(2)
+#define GPSR1_A1			BIT(1)
+#define GPSR1_A0			BIT(0)
+#define GPSR2_AVB_AVTP_CAPTURE_A	BIT(14)
+#define GPSR2_AVB_AVTP_MATCH_A		BIT(13)
+#define GPSR2_AVB_LINK			BIT(12)
+#define GPSR2_AVB_PHY_INT		BIT(11)
+#define GPSR2_AVB_MAGIC			BIT(10)
+#define GPSR2_AVB_MDC			BIT(9)
+#define GPSR2_PWM2_A			BIT(8)
+#define GPSR2_PWM1_A			BIT(7)
+#define GPSR2_PWM0			BIT(6)
+#define GPSR2_IRQ5			BIT(5)
+#define GPSR2_IRQ4			BIT(4)
+#define GPSR2_IRQ3			BIT(3)
+#define GPSR2_IRQ2			BIT(2)
+#define GPSR2_IRQ1			BIT(1)
+#define GPSR2_IRQ0			BIT(0)
+#define GPSR3_SD1_WP			BIT(15)
+#define GPSR3_SD1_CD			BIT(14)
+#define GPSR3_SD0_WP			BIT(13)
+#define GPSR3_SD0_CD			BIT(12)
+#define GPSR3_SD1_DAT3			BIT(11)
+#define GPSR3_SD1_DAT2			BIT(10)
+#define GPSR3_SD1_DAT1			BIT(9)
+#define GPSR3_SD1_DAT0			BIT(8)
+#define GPSR3_SD1_CMD			BIT(7)
+#define GPSR3_SD1_CLK			BIT(6)
+#define GPSR3_SD0_DAT3			BIT(5)
+#define GPSR3_SD0_DAT2			BIT(4)
+#define GPSR3_SD0_DAT1			BIT(3)
+#define GPSR3_SD0_DAT0			BIT(2)
+#define GPSR3_SD0_CMD			BIT(1)
+#define GPSR3_SD0_CLK			BIT(0)
+#define GPSR4_SD3_DS			BIT(17)
+#define GPSR4_SD3_DAT7			BIT(16)
+#define GPSR4_SD3_DAT6			BIT(15)
+#define GPSR4_SD3_DAT5			BIT(14)
+#define GPSR4_SD3_DAT4			BIT(13)
+#define GPSR4_SD3_DAT3			BIT(12)
+#define GPSR4_SD3_DAT2			BIT(11)
+#define GPSR4_SD3_DAT1			BIT(10)
+#define GPSR4_SD3_DAT0			BIT(9)
+#define GPSR4_SD3_CMD			BIT(8)
+#define GPSR4_SD3_CLK			BIT(7)
+#define GPSR4_SD2_DS			BIT(6)
+#define GPSR4_SD2_DAT3			BIT(5)
+#define GPSR4_SD2_DAT2			BIT(4)
+#define GPSR4_SD2_DAT1			BIT(3)
+#define GPSR4_SD2_DAT0			BIT(2)
+#define GPSR4_SD2_CMD			BIT(1)
+#define GPSR4_SD2_CLK			BIT(0)
+#define GPSR5_MLB_DAT			BIT(25)
+#define GPSR5_MLB_SIG			BIT(24)
+#define GPSR5_MLB_CLK			BIT(23)
+#define GPSR5_MSIOF0_RXD		BIT(22)
+#define GPSR5_MSIOF0_SS2		BIT(21)
+#define GPSR5_MSIOF0_TXD		BIT(20)
+#define GPSR5_MSIOF0_SS1		BIT(19)
+#define GPSR5_MSIOF0_SYNC		BIT(18)
+#define GPSR5_MSIOF0_SCK		BIT(17)
+#define GPSR5_HRTS0			BIT(16)
+#define GPSR5_HCTS0			BIT(15)
+#define GPSR5_HTX0			BIT(14)
+#define GPSR5_HRX0			BIT(13)
+#define GPSR5_HSCK0			BIT(12)
+#define GPSR5_RX2_A			BIT(11)
+#define GPSR5_TX2_A			BIT(10)
+#define GPSR5_SCK2			BIT(9)
+#define GPSR5_RTS1			BIT(8)
+#define GPSR5_CTS1			BIT(7)
+#define GPSR5_TX1_A			BIT(6)
+#define GPSR5_RX1_A			BIT(5)
+#define GPSR5_RTS0			BIT(4)
+#define GPSR5_CTS0			BIT(3)
+#define GPSR5_TX0			BIT(2)
+#define GPSR5_RX0			BIT(1)
+#define GPSR5_SCK0			BIT(0)
+#define GPSR6_USB31_OVC			BIT(31)
+#define GPSR6_USB31_PWEN		BIT(30)
+#define GPSR6_USB30_OVC			BIT(29)
+#define GPSR6_USB30_PWEN		BIT(28)
+#define GPSR6_USB1_OVC			BIT(27)
+#define GPSR6_USB1_PWEN			BIT(26)
+#define GPSR6_USB0_OVC			BIT(25)
+#define GPSR6_USB0_PWEN			BIT(24)
+#define GPSR6_AUDIO_CLKB_B		BIT(23)
+#define GPSR6_AUDIO_CLKA_A		BIT(22)
+#define GPSR6_SSI_SDATA9_A		BIT(21)
+#define GPSR6_SSI_SDATA8		BIT(20)
+#define GPSR6_SSI_SDATA7		BIT(19)
+#define GPSR6_SSI_WS78			BIT(18)
+#define GPSR6_SSI_SCK78			BIT(17)
+#define GPSR6_SSI_SDATA6		BIT(16)
+#define GPSR6_SSI_WS6			BIT(15)
+#define GPSR6_SSI_SCK6			BIT(14)
+#define GPSR6_SSI_SDATA5		BIT(13)
+#define GPSR6_SSI_WS5			BIT(12)
+#define GPSR6_SSI_SCK5			BIT(11)
+#define GPSR6_SSI_SDATA4		BIT(10)
+#define GPSR6_SSI_WS4			BIT(9)
+#define GPSR6_SSI_SCK4			BIT(8)
+#define GPSR6_SSI_SDATA3		BIT(7)
+#define GPSR6_SSI_WS34			BIT(6)
+#define GPSR6_SSI_SCK34			BIT(5)
+#define GPSR6_SSI_SDATA2_A		BIT(4)
+#define GPSR6_SSI_SDATA1_A		BIT(3)
+#define GPSR6_SSI_SDATA0		BIT(2)
+#define GPSR6_SSI_WS0129		BIT(1)
+#define GPSR6_SSI_SCK0129		BIT(0)
+#define GPSR7_AVS2			BIT(1)
+#define GPSR7_AVS1			BIT(0)
+
+#define IPSR_28_FUNC(x)			((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x)			((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x)			((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x)			((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x)			((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x)			((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x)			((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x)			((uint32_t)(x) << 0U)
+
+#define POC_SD3_DS_33V			BIT(29)
+#define POC_SD3_DAT7_33V		BIT(28)
+#define POC_SD3_DAT6_33V		BIT(27)
+#define POC_SD3_DAT5_33V		BIT(26)
+#define POC_SD3_DAT4_33V		BIT(25)
+#define POC_SD3_DAT3_33V		BIT(24)
+#define POC_SD3_DAT2_33V		BIT(23)
+#define POC_SD3_DAT1_33V		BIT(22)
+#define POC_SD3_DAT0_33V		BIT(21)
+#define POC_SD3_CMD_33V			BIT(20)
+#define POC_SD3_CLK_33V			BIT(19)
+#define POC_SD2_DS_33V			BIT(18)
+#define POC_SD2_DAT3_33V		BIT(17)
+#define POC_SD2_DAT2_33V		BIT(16)
+#define POC_SD2_DAT1_33V		BIT(15)
+#define POC_SD2_DAT0_33V		BIT(14)
+#define POC_SD2_CMD_33V			BIT(13)
+#define POC_SD2_CLK_33V			BIT(12)
+#define POC_SD1_DAT3_33V		BIT(11)
+#define POC_SD1_DAT2_33V		BIT(10)
+#define POC_SD1_DAT1_33V		BIT(9)
+#define POC_SD1_DAT0_33V		BIT(8)
+#define POC_SD1_CMD_33V			BIT(7)
+#define POC_SD1_CLK_33V			BIT(6)
+#define POC_SD0_DAT3_33V		BIT(5)
+#define POC_SD0_DAT2_33V		BIT(4)
+#define POC_SD0_DAT1_33V		BIT(3)
+#define POC_SD0_DAT0_33V		BIT(2)
+#define POC_SD0_CMD_33V			BIT(1)
+#define POC_SD0_CLK_33V			BIT(0)
+
+#define DRVCTRL0_MASK			(0xCCCCCCCCU)
+#define DRVCTRL1_MASK			(0xCCCCCCC8U)
+#define DRVCTRL2_MASK			(0x88888888U)
+#define DRVCTRL3_MASK			(0x88888888U)
+#define DRVCTRL4_MASK			(0x88888888U)
+#define DRVCTRL5_MASK			(0x88888888U)
+#define DRVCTRL6_MASK			(0x88888888U)
+#define DRVCTRL7_MASK			(0x88888888U)
+#define DRVCTRL8_MASK			(0x88888888U)
+#define DRVCTRL9_MASK			(0x88888888U)
+#define DRVCTRL10_MASK			(0x88888888U)
+#define DRVCTRL11_MASK			(0x888888CCU)
+#define DRVCTRL12_MASK			(0xCCCFFFCFU)
+#define DRVCTRL13_MASK			(0xCC888888U)
+#define DRVCTRL14_MASK			(0x88888888U)
+#define DRVCTRL15_MASK			(0x88888888U)
+#define DRVCTRL16_MASK			(0x88888888U)
+#define DRVCTRL17_MASK			(0x88888888U)
+#define DRVCTRL18_MASK			(0x88888888U)
+#define DRVCTRL19_MASK			(0x88888888U)
+#define DRVCTRL20_MASK			(0x88888888U)
+#define DRVCTRL21_MASK			(0x88888888U)
+#define DRVCTRL22_MASK			(0x88888888U)
+#define DRVCTRL23_MASK			(0x88888888U)
+#define DRVCTRL24_MASK			(0x8888888FU)
+
+#define DRVCTRL0_QSPI0_SPCLK(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL0_QSPI0_IO2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL0_QSPI0_IO3(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL0_QSPI0_SSL(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL0_QSPI1_SPCLK(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL1_QSPI1_IO2(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL1_QSPI1_IO3(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL1_QSPI1_SS(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL1_RPC_INT(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL1_RPC_WP(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL1_RPC_RESET(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL1_AVB_RX_CTL(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL2_AVB_RXC(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL2_AVB_RD0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL2_AVB_RD1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL2_AVB_RD2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL2_AVB_RD3(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL2_AVB_TX_CTL(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL2_AVB_TXC(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL2_AVB_TD0(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL3_AVB_TD1(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL3_AVB_TD2(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL3_AVB_TD3(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL3_AVB_MDIO(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL3_AVB_MDC(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL3_AVB_MAGIC(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL3_AVB_PHY_INT(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL4_AVB_LINK(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL4_IRQ0(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL4_IRQ1(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL4_IRQ2(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL4_IRQ3(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL4_IRQ4(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL5_IRQ5(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL5_PWM0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL5_PWM1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL5_PWM2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL5_A0(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL5_A1(x)			((uint32_t)(x) << 8U)
+#define DRVCTRL5_A2(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL5_A3(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL6_A4(x)			((uint32_t)(x) << 28U)
+#define DRVCTRL6_A5(x)			((uint32_t)(x) << 24U)
+#define DRVCTRL6_A6(x)			((uint32_t)(x) << 20U)
+#define DRVCTRL6_A7(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL6_A8(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL6_A9(x)			((uint32_t)(x) << 8U)
+#define DRVCTRL6_A10(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL6_A11(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL7_A12(x)			((uint32_t)(x) << 28U)
+#define DRVCTRL7_A13(x)			((uint32_t)(x) << 24U)
+#define DRVCTRL7_A14(x)			((uint32_t)(x) << 20U)
+#define DRVCTRL7_A15(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL7_A16(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL7_A17(x)			((uint32_t)(x) << 8U)
+#define DRVCTRL7_A18(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL7_A19(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL8_CLKOUT(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL8_CS0(x)			((uint32_t)(x) << 24U)
+#define DRVCTRL8_CS1_A2(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL8_BS(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL8_RD(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL8_RD_W(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL8_WE0(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL8_WE1(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL9_EX_WAIT0(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL9_PRESETOU(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL9_D0(x)			((uint32_t)(x) << 20U)
+#define DRVCTRL9_D1(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL9_D2(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL9_D3(x)			((uint32_t)(x) << 8U)
+#define DRVCTRL9_D4(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL9_D5(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL10_D6(x)			((uint32_t)(x) << 28U)
+#define DRVCTRL10_D7(x)			((uint32_t)(x) << 24U)
+#define DRVCTRL10_D8(x)			((uint32_t)(x) << 20U)
+#define DRVCTRL10_D9(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL10_D10(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL10_D11(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL10_D12(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL10_D13(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL11_D14(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL11_D15(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL11_AVS1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL11_AVS2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL11_GP7_02(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL11_GP7_03(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL12_DU_FSCLKST(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL12_DU_TMS(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL13_TDO(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL13_ASEBRK(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL13_SD0_CLK(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL13_SD0_CMD(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL13_SD0_DAT0(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL13_SD0_DAT1(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL13_SD0_DAT2(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL13_SD0_DAT3(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL14_SD1_CLK(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL14_SD1_CMD(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL14_SD1_DAT0(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL14_SD1_DAT1(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL14_SD1_DAT2(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL14_SD1_DAT3(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL14_SD2_CLK(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL14_SD2_CMD(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL15_SD2_DAT0(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL15_SD2_DAT1(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL15_SD2_DAT2(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL15_SD2_DAT3(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL15_SD2_DS(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL15_SD3_CLK(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL15_SD3_CMD(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL15_SD3_DAT0(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL16_SD3_DAT1(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL16_SD3_DAT2(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL16_SD3_DAT3(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL16_SD3_DAT4(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL16_SD3_DAT5(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL16_SD3_DAT6(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL16_SD3_DAT7(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL16_SD3_DS(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL17_SD0_CD(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL17_SD0_WP(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL17_SD1_CD(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL17_SD1_WP(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL17_SCK0(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL17_RX0(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL17_TX0(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL17_CTS0(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL18_RTS0_TANS(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL18_RX1(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL18_TX1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL18_CTS1(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL18_RTS1_TANS(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL18_SCK2(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL18_TX2(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL18_RX2(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL19_HSCK0(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL19_HRX0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL19_HTX0(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL19_HCTS0(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL19_HRTS0(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL19_MSIOF0_SCK(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL19_MSIOF0_SS1(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL20_MSIOF0_TXD(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL20_MSIOF0_SS2(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL20_MSIOF0_RXD(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL20_MLB_CLK(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL20_MLB_SIG(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL20_MLB_DAT(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL20_MLB_REF(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL21_SSI_WS0129(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL21_SSI_SDATA0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL21_SSI_SDATA1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL21_SSI_SDATA2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL21_SSI_SCK34(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL21_SSI_WS34(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL21_SSI_SDATA3(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL21_SSI_SCK4(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL22_SSI_WS4(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL22_SSI_SDATA4(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL22_SSI_SCK5(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL22_SSI_WS5(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL22_SSI_SDATA5(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL22_SSI_SCK6(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL22_SSI_WS6(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL22_SSI_SDATA6(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL23_SSI_SCK78(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL23_SSI_WS78(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL23_SSI_SDATA7(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL23_SSI_SDATA8(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL23_SSI_SDATA9(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL23_AUDIO_CLKA(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL23_AUDIO_CLKB(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL23_USB0_PWEN(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL24_USB0_OVC(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL24_USB1_PWEN(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL24_USB1_OVC(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL24_USB30_PWEN(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL24_USB30_OVC(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL24_USB31_PWEN(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL24_USB31_OVC(x)		((uint32_t)(x) << 4U)
+
+#define MOD_SEL0_MSIOF3_A		((uint32_t)0U << 29U)
+#define MOD_SEL0_MSIOF3_B		((uint32_t)1U << 29U)
+#define MOD_SEL0_MSIOF3_C		((uint32_t)2U << 29U)
+#define MOD_SEL0_MSIOF3_D		((uint32_t)3U << 29U)
+#define MOD_SEL0_MSIOF3_E		((uint32_t)4U << 29U)
+#define MOD_SEL0_MSIOF2_A		((uint32_t)0U << 27U)
+#define MOD_SEL0_MSIOF2_B		((uint32_t)1U << 27U)
+#define MOD_SEL0_MSIOF2_C		((uint32_t)2U << 27U)
+#define MOD_SEL0_MSIOF2_D		((uint32_t)3U << 27U)
+#define MOD_SEL0_MSIOF1_A		((uint32_t)0U << 24U)
+#define MOD_SEL0_MSIOF1_B		((uint32_t)1U << 24U)
+#define MOD_SEL0_MSIOF1_C		((uint32_t)2U << 24U)
+#define MOD_SEL0_MSIOF1_D		((uint32_t)3U << 24U)
+#define MOD_SEL0_MSIOF1_E		((uint32_t)4U << 24U)
+#define MOD_SEL0_MSIOF1_F		((uint32_t)5U << 24U)
+#define MOD_SEL0_MSIOF1_G		((uint32_t)6U << 24U)
+#define MOD_SEL0_LBSC_A			((uint32_t)0U << 23U)
+#define MOD_SEL0_LBSC_B			((uint32_t)1U << 23U)
+#define MOD_SEL0_IEBUS_A		((uint32_t)0U << 22U)
+#define MOD_SEL0_IEBUS_B		((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C2_A			((uint32_t)0U << 21U)
+#define MOD_SEL0_I2C2_B			((uint32_t)1U << 21U)
+#define MOD_SEL0_I2C1_A			((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B			((uint32_t)1U << 20U)
+#define MOD_SEL0_HSCIF4_A		((uint32_t)0U << 19U)
+#define MOD_SEL0_HSCIF4_B		((uint32_t)1U << 19U)
+#define MOD_SEL0_HSCIF3_A		((uint32_t)0U << 17U)
+#define MOD_SEL0_HSCIF3_B		((uint32_t)1U << 17U)
+#define MOD_SEL0_HSCIF3_C		((uint32_t)2U << 17U)
+#define MOD_SEL0_HSCIF3_D		((uint32_t)3U << 17U)
+#define MOD_SEL0_HSCIF1_A		((uint32_t)0U << 16U)
+#define MOD_SEL0_HSCIF1_B		((uint32_t)1U << 16U)
+#define MOD_SEL0_FSO_A			((uint32_t)0U << 15U)
+#define MOD_SEL0_FSO_B			((uint32_t)1U << 15U)
+#define MOD_SEL0_HSCIF2_A		((uint32_t)0U << 13U)
+#define MOD_SEL0_HSCIF2_B		((uint32_t)1U << 13U)
+#define MOD_SEL0_HSCIF2_C		((uint32_t)2U << 13U)
+#define MOD_SEL0_ETHERAVB_A		((uint32_t)0U << 12U)
+#define MOD_SEL0_ETHERAVB_B		((uint32_t)1U << 12U)
+#define MOD_SEL0_DRIF3_A		((uint32_t)0U << 11U)
+#define MOD_SEL0_DRIF3_B		((uint32_t)1U << 11U)
+#define MOD_SEL0_DRIF2_A		((uint32_t)0U << 10U)
+#define MOD_SEL0_DRIF2_B		((uint32_t)1U << 10U)
+#define MOD_SEL0_DRIF1_A		((uint32_t)0U << 8U)
+#define MOD_SEL0_DRIF1_B		((uint32_t)1U << 8U)
+#define MOD_SEL0_DRIF1_C		((uint32_t)2U << 8U)
+#define MOD_SEL0_DRIF0_A		((uint32_t)0U << 6U)
+#define MOD_SEL0_DRIF0_B		((uint32_t)1U << 6U)
+#define MOD_SEL0_DRIF0_C		((uint32_t)2U << 6U)
+#define MOD_SEL0_CANFD0_A		((uint32_t)0U << 5U)
+#define MOD_SEL0_CANFD0_B		((uint32_t)1U << 5U)
+#define MOD_SEL0_ADG_A_A		((uint32_t)0U << 3U)
+#define MOD_SEL0_ADG_A_B		((uint32_t)1U << 3U)
+#define MOD_SEL0_ADG_A_C		((uint32_t)2U << 3U)
+#define MOD_SEL1_TSIF1_A		((uint32_t)0U << 30U)
+#define MOD_SEL1_TSIF1_B		((uint32_t)1U << 30U)
+#define MOD_SEL1_TSIF1_C		((uint32_t)2U << 30U)
+#define MOD_SEL1_TSIF1_D		((uint32_t)3U << 30U)
+#define MOD_SEL1_TSIF0_A		((uint32_t)0U << 27U)
+#define MOD_SEL1_TSIF0_B		((uint32_t)1U << 27U)
+#define MOD_SEL1_TSIF0_C		((uint32_t)2U << 27U)
+#define MOD_SEL1_TSIF0_D		((uint32_t)3U << 27U)
+#define MOD_SEL1_TSIF0_E		((uint32_t)4U << 27U)
+#define MOD_SEL1_TIMER_TMU_A		((uint32_t)0U << 26U)
+#define MOD_SEL1_TIMER_TMU_B		((uint32_t)1U << 26U)
+#define MOD_SEL1_SSP1_1_A		((uint32_t)0U << 24U)
+#define MOD_SEL1_SSP1_1_B		((uint32_t)1U << 24U)
+#define MOD_SEL1_SSP1_1_C		((uint32_t)2U << 24U)
+#define MOD_SEL1_SSP1_1_D		((uint32_t)3U << 24U)
+#define MOD_SEL1_SSP1_0_A		((uint32_t)0U << 21U)
+#define MOD_SEL1_SSP1_0_B		((uint32_t)1U << 21U)
+#define MOD_SEL1_SSP1_0_C		((uint32_t)2U << 21U)
+#define MOD_SEL1_SSP1_0_D		((uint32_t)3U << 21U)
+#define MOD_SEL1_SSP1_0_E		((uint32_t)4U << 21U)
+#define MOD_SEL1_SSI_A			((uint32_t)0U << 20U)
+#define MOD_SEL1_SSI_B			((uint32_t)1U << 20U)
+#define MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
+#define MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
+#define MOD_SEL1_SIMCARD_A		((uint32_t)0U << 17U)
+#define MOD_SEL1_SIMCARD_B		((uint32_t)1U << 17U)
+#define MOD_SEL1_SIMCARD_C		((uint32_t)2U << 17U)
+#define MOD_SEL1_SIMCARD_D		((uint32_t)3U << 17U)
+#define MOD_SEL1_SDHI2_A		((uint32_t)0U << 16U)
+#define MOD_SEL1_SDHI2_B		((uint32_t)1U << 16U)
+#define MOD_SEL1_SCIF4_A		((uint32_t)0U << 14U)
+#define MOD_SEL1_SCIF4_B		((uint32_t)1U << 14U)
+#define MOD_SEL1_SCIF4_C		((uint32_t)2U << 14U)
+#define MOD_SEL1_SCIF3_A		((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B		((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF2_A		((uint32_t)0U << 12U)
+#define MOD_SEL1_SCIF2_B		((uint32_t)1U << 12U)
+#define MOD_SEL1_SCIF1_A		((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF1_B		((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF_A			((uint32_t)0U << 10U)
+#define MOD_SEL1_SCIF_B			((uint32_t)1U << 10U)
+#define MOD_SEL1_REMOCON_A		((uint32_t)0U << 9U)
+#define MOD_SEL1_REMOCON_B		((uint32_t)1U << 9U)
+#define MOD_SEL1_RCAN0_A		((uint32_t)0U << 6U)
+#define MOD_SEL1_RCAN0_B		((uint32_t)1U << 6U)
+#define MOD_SEL1_PWM6_A			((uint32_t)0U << 5U)
+#define MOD_SEL1_PWM6_B			((uint32_t)1U << 5U)
+#define MOD_SEL1_PWM5_A			((uint32_t)0U << 4U)
+#define MOD_SEL1_PWM5_B			((uint32_t)1U << 4U)
+#define MOD_SEL1_PWM4_A			((uint32_t)0U << 3U)
+#define MOD_SEL1_PWM4_B			((uint32_t)1U << 3U)
+#define MOD_SEL1_PWM3_A			((uint32_t)0U << 2U)
+#define MOD_SEL1_PWM3_B			((uint32_t)1U << 2U)
+#define MOD_SEL1_PWM2_A			((uint32_t)0U << 1U)
+#define MOD_SEL1_PWM2_B			((uint32_t)1U << 1U)
+#define MOD_SEL1_PWM1_A			((uint32_t)0U << 0U)
+#define MOD_SEL1_PWM1_B			((uint32_t)1U << 0U)
+#define MOD_SEL2_I2C_5_A		((uint32_t)0U << 31U)
+#define MOD_SEL2_I2C_5_B		((uint32_t)1U << 31U)
+#define MOD_SEL2_I2C_3_A		((uint32_t)0U << 30U)
+#define MOD_SEL2_I2C_3_B		((uint32_t)1U << 30U)
+#define MOD_SEL2_I2C_0_A		((uint32_t)0U << 29U)
+#define MOD_SEL2_I2C_0_B		((uint32_t)1U << 29U)
+#define MOD_SEL2_FM_A			((uint32_t)0U << 27U)
+#define MOD_SEL2_FM_B			((uint32_t)1U << 27U)
+#define MOD_SEL2_FM_C			((uint32_t)2U << 27U)
+#define MOD_SEL2_FM_D			((uint32_t)3U << 27U)
+#define MOD_SEL2_SCIF5_A		((uint32_t)0U << 26U)
+#define MOD_SEL2_SCIF5_B		((uint32_t)1U << 26U)
+#define MOD_SEL2_I2C6_A			((uint32_t)0U << 23U)
+#define MOD_SEL2_I2C6_B			((uint32_t)1U << 23U)
+#define MOD_SEL2_I2C6_C			((uint32_t)2U << 23U)
+#define MOD_SEL2_NDF_A			((uint32_t)0U << 22U)
+#define MOD_SEL2_NDF_B			((uint32_t)1U << 22U)
+#define MOD_SEL2_SSI2_A			((uint32_t)0U << 21U)
+#define MOD_SEL2_SSI2_B			((uint32_t)1U << 21U)
+#define MOD_SEL2_SSI9_A			((uint32_t)0U << 20U)
+#define MOD_SEL2_SSI9_B			((uint32_t)1U << 20U)
+#define MOD_SEL2_TIMER_TMU2_A		((uint32_t)0U << 19U)
+#define MOD_SEL2_TIMER_TMU2_B		((uint32_t)1U << 19U)
+#define MOD_SEL2_ADG_B_A		((uint32_t)0U << 18U)
+#define MOD_SEL2_ADG_B_B		((uint32_t)1U << 18U)
+#define MOD_SEL2_ADG_C_A		((uint32_t)0U << 17U)
+#define MOD_SEL2_ADG_C_B		((uint32_t)1U << 17U)
+#define MOD_SEL2_VIN4_A			((uint32_t)0U << 0U)
+#define MOD_SEL2_VIN4_B			((uint32_t)1U << 0U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	mmio_write_32(PFC_PMMR, ~data);
+	mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_g2h(void)
+{
+	uint32_t reg;
+
+	/* initialize module select */
+	pfc_reg_write(PFC_MOD_SEL0,
+		      MOD_SEL0_MSIOF3_A |
+		      MOD_SEL0_MSIOF2_A |
+		      MOD_SEL0_MSIOF1_A |
+		      MOD_SEL0_LBSC_A |
+		      MOD_SEL0_IEBUS_A |
+		      MOD_SEL0_I2C2_A |
+		      MOD_SEL0_I2C1_A |
+		      MOD_SEL0_HSCIF4_A |
+		      MOD_SEL0_HSCIF3_A |
+		      MOD_SEL0_HSCIF1_A |
+		      MOD_SEL0_FSO_A |
+		      MOD_SEL0_HSCIF2_A |
+		      MOD_SEL0_ETHERAVB_A |
+		      MOD_SEL0_DRIF3_A |
+		      MOD_SEL0_DRIF2_A |
+		      MOD_SEL0_DRIF1_A |
+		      MOD_SEL0_DRIF0_A |
+		      MOD_SEL0_CANFD0_A |
+		      MOD_SEL0_ADG_A_A);
+
+	pfc_reg_write(PFC_MOD_SEL1,
+		      MOD_SEL1_TSIF1_A |
+		      MOD_SEL1_TSIF0_A |
+		      MOD_SEL1_TIMER_TMU_A |
+		      MOD_SEL1_SSP1_1_A |
+		      MOD_SEL1_SSP1_0_A |
+		      MOD_SEL1_SSI_A |
+		      MOD_SEL1_SPEED_PULSE_IF_A |
+		      MOD_SEL1_SIMCARD_A |
+		      MOD_SEL1_SDHI2_A |
+		      MOD_SEL1_SCIF4_A |
+		      MOD_SEL1_SCIF3_A |
+		      MOD_SEL1_SCIF2_A |
+		      MOD_SEL1_SCIF1_A |
+		      MOD_SEL1_SCIF_A |
+		      MOD_SEL1_REMOCON_A |
+		      MOD_SEL1_RCAN0_A |
+		      MOD_SEL1_PWM6_A |
+		      MOD_SEL1_PWM5_A |
+		      MOD_SEL1_PWM4_A |
+		      MOD_SEL1_PWM3_A |
+		      MOD_SEL1_PWM2_A |
+		      MOD_SEL1_PWM1_A);
+
+	pfc_reg_write(PFC_MOD_SEL2,
+		      MOD_SEL2_I2C_5_B |
+		      MOD_SEL2_I2C_3_B |
+		      MOD_SEL2_I2C_0_B |
+		      MOD_SEL2_FM_A |
+		      MOD_SEL2_SCIF5_A |
+		      MOD_SEL2_I2C6_A |
+		      MOD_SEL2_NDF_A |
+		      MOD_SEL2_SSI2_A |
+		      MOD_SEL2_SSI9_A |
+		      MOD_SEL2_TIMER_TMU2_A |
+		      MOD_SEL2_ADG_B_A |
+		      MOD_SEL2_ADG_C_A |
+		      MOD_SEL2_VIN4_A);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR1,
+		      IPSR_28_FUNC(6) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(3) |
+		      IPSR_8_FUNC(3) |
+		      IPSR_4_FUNC(3) |
+		      IPSR_0_FUNC(3));
+
+	pfc_reg_write(PFC_IPSR2,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(6) |
+		      IPSR_20_FUNC(6) |
+		      IPSR_16_FUNC(6) |
+		      IPSR_12_FUNC(6) |
+		      IPSR_8_FUNC(6) |
+		      IPSR_4_FUNC(6) |
+		      IPSR_0_FUNC(6));
+
+	pfc_reg_write(PFC_IPSR3,
+		      IPSR_28_FUNC(6) |
+		      IPSR_24_FUNC(6) |
+		      IPSR_20_FUNC(6) |
+		      IPSR_16_FUNC(6) |
+		      IPSR_12_FUNC(6) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR4,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(6) |
+		      IPSR_4_FUNC(6) |
+		      IPSR_0_FUNC(6));
+
+	pfc_reg_write(PFC_IPSR5,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(6) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR6,
+		      IPSR_28_FUNC(6) |
+		      IPSR_24_FUNC(6) |
+		      IPSR_20_FUNC(6) |
+		      IPSR_16_FUNC(6) |
+		      IPSR_12_FUNC(6) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR7,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(6) |
+		      IPSR_4_FUNC(6) |
+		      IPSR_0_FUNC(6));
+
+	pfc_reg_write(PFC_IPSR8,
+		      IPSR_28_FUNC(1) |
+		      IPSR_24_FUNC(1) |
+		      IPSR_20_FUNC(1) |
+		      IPSR_16_FUNC(1) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR9,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR10,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR11,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(4) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR12,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(4) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR13,
+		      IPSR_28_FUNC(8) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(3) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR14,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(3) |
+		      IPSR_0_FUNC(8));
+
+	pfc_reg_write(PFC_IPSR15,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR16,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR17,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(1) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR18,
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	/* initialize GPIO/peripheral function select */
+	pfc_reg_write(PFC_GPSR0,
+		      GPSR0_D15 |
+		      GPSR0_D14 |
+		      GPSR0_D13 |
+		      GPSR0_D12 |
+		      GPSR0_D11 |
+		      GPSR0_D10 |
+		      GPSR0_D9 |
+		      GPSR0_D8 |
+		      GPSR0_D7 |
+		      GPSR0_D6 |
+		      GPSR0_D5 |
+		      GPSR0_D4 |
+		      GPSR0_D3 |
+		      GPSR0_D2 |
+		      GPSR0_D0);
+
+	pfc_reg_write(PFC_GPSR1,
+		      GPSR1_CLKOUT |
+		      GPSR1_EX_WAIT0_A |
+		      GPSR1_WE1 |
+		      GPSR1_RD |
+		      GPSR1_RD_WR |
+		      GPSR1_CS0 |
+		      GPSR1_A19 |
+		      GPSR1_A18 |
+		      GPSR1_A17 |
+		      GPSR1_A16 |
+		      GPSR1_A15 |
+		      GPSR1_A14 |
+		      GPSR1_A13 |
+		      GPSR1_A12 |
+		      GPSR1_A7 |
+		      GPSR1_A6 |
+		      GPSR1_A5 |
+		      GPSR1_A4 |
+		      GPSR1_A3 |
+		      GPSR1_A2 |
+		      GPSR1_A1 |
+		      GPSR1_A0);
+
+	pfc_reg_write(PFC_GPSR2,
+		      GPSR2_AVB_AVTP_CAPTURE_A |
+		      GPSR2_AVB_AVTP_MATCH_A |
+		      GPSR2_AVB_LINK |
+		      GPSR2_AVB_PHY_INT |
+		      GPSR2_AVB_MDC |
+		      GPSR2_PWM2_A |
+		      GPSR2_PWM1_A |
+		      GPSR2_IRQ4 |
+		      GPSR2_IRQ3 |
+		      GPSR2_IRQ2 |
+		      GPSR2_IRQ1 |
+		      GPSR2_IRQ0);
+
+	pfc_reg_write(PFC_GPSR3,
+		      GPSR3_SD0_CD |
+		      GPSR3_SD1_DAT3 |
+		      GPSR3_SD1_DAT2 |
+		      GPSR3_SD1_DAT1 |
+		      GPSR3_SD1_DAT0 |
+		      GPSR3_SD0_DAT3 |
+		      GPSR3_SD0_DAT2 |
+		      GPSR3_SD0_DAT1 |
+		      GPSR3_SD0_DAT0 |
+		      GPSR3_SD0_CMD |
+		      GPSR3_SD0_CLK);
+
+	pfc_reg_write(PFC_GPSR4,
+		      GPSR4_SD3_DS |
+		      GPSR4_SD3_DAT7 |
+		      GPSR4_SD3_DAT6 |
+		      GPSR4_SD3_DAT5 |
+		      GPSR4_SD3_DAT4 |
+		      GPSR4_SD3_DAT3 |
+		      GPSR4_SD3_DAT2 |
+		      GPSR4_SD3_DAT1 |
+		      GPSR4_SD3_DAT0 |
+		      GPSR4_SD3_CMD |
+		      GPSR4_SD3_CLK |
+		      GPSR4_SD2_DAT3 |
+		      GPSR4_SD2_DAT2 |
+		      GPSR4_SD2_DAT1 |
+		      GPSR4_SD2_DAT0 |
+		      GPSR4_SD2_CMD |
+		      GPSR4_SD2_CLK);
+
+	pfc_reg_write(PFC_GPSR5,
+		      GPSR5_MSIOF0_RXD |
+		      GPSR5_MSIOF0_TXD |
+		      GPSR5_MSIOF0_SYNC |
+		      GPSR5_MSIOF0_SCK |
+		      GPSR5_RX2_A |
+		      GPSR5_TX2_A |
+		      GPSR5_RTS1 |
+		      GPSR5_CTS1 |
+		      GPSR5_TX1_A |
+		      GPSR5_RX1_A |
+		      GPSR5_RTS0 |
+		      GPSR5_SCK0);
+
+	pfc_reg_write(PFC_GPSR6,
+		      GPSR6_AUDIO_CLKB_B |
+		      GPSR6_AUDIO_CLKA_A |
+		      GPSR6_SSI_WS6 |
+		      GPSR6_SSI_SCK6 |
+		      GPSR6_SSI_SDATA4 |
+		      GPSR6_SSI_WS4 |
+		      GPSR6_SSI_SCK4 |
+		      GPSR6_SSI_SDATA1_A |
+		      GPSR6_SSI_SDATA0 |
+		      GPSR6_SSI_WS0129 |
+		      GPSR6_SSI_SCK0129);
+
+	pfc_reg_write(PFC_GPSR7,
+		      GPSR7_AVS2 |
+		      GPSR7_AVS1);
+
+	/* initialize POC control register */
+	pfc_reg_write(PFC_POCCTRL0,
+		      POC_SD0_DAT3_33V |
+		      POC_SD0_DAT2_33V |
+		      POC_SD0_DAT1_33V |
+		      POC_SD0_DAT0_33V |
+		      POC_SD0_CMD_33V |
+		      POC_SD0_CLK_33V);
+
+	/* initialize DRV control register */
+	reg = mmio_read_32(PFC_DRVCTRL0);
+	reg = (reg & DRVCTRL0_MASK) |
+	      DRVCTRL0_QSPI0_SPCLK(3) |
+	      DRVCTRL0_QSPI0_MOSI_IO0(3) |
+	      DRVCTRL0_QSPI0_MISO_IO1(3) |
+	      DRVCTRL0_QSPI0_IO2(3) |
+	      DRVCTRL0_QSPI0_IO3(3) |
+	      DRVCTRL0_QSPI0_SSL(3) |
+	      DRVCTRL0_QSPI1_SPCLK(3) |
+	      DRVCTRL0_QSPI1_MOSI_IO0(3);
+	pfc_reg_write(PFC_DRVCTRL0, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL1);
+	reg = (reg & DRVCTRL1_MASK) |
+	      DRVCTRL1_QSPI1_MISO_IO1(3) |
+	      DRVCTRL1_QSPI1_IO2(3) |
+	      DRVCTRL1_QSPI1_IO3(3) |
+	      DRVCTRL1_QSPI1_SS(3) |
+	      DRVCTRL1_RPC_INT(3) |
+	      DRVCTRL1_RPC_WP(3) |
+	      DRVCTRL1_RPC_RESET(3) |
+	      DRVCTRL1_AVB_RX_CTL(7);
+	pfc_reg_write(PFC_DRVCTRL1, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL2);
+	reg = (reg & DRVCTRL2_MASK) |
+	      DRVCTRL2_AVB_RXC(7) |
+	      DRVCTRL2_AVB_RD0(7) |
+	      DRVCTRL2_AVB_RD1(7) |
+	      DRVCTRL2_AVB_RD2(7) |
+	      DRVCTRL2_AVB_RD3(7) |
+	      DRVCTRL2_AVB_TX_CTL(3) |
+	      DRVCTRL2_AVB_TXC(3) |
+	      DRVCTRL2_AVB_TD0(3);
+	pfc_reg_write(PFC_DRVCTRL2, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL3);
+	reg = (reg & DRVCTRL3_MASK) |
+	      DRVCTRL3_AVB_TD1(3) |
+	      DRVCTRL3_AVB_TD2(3) |
+	      DRVCTRL3_AVB_TD3(3) |
+	      DRVCTRL3_AVB_TXCREFCLK(7) |
+	      DRVCTRL3_AVB_MDIO(7) |
+	      DRVCTRL3_AVB_MDC(7) |
+	      DRVCTRL3_AVB_MAGIC(7) |
+	      DRVCTRL3_AVB_PHY_INT(7);
+	pfc_reg_write(PFC_DRVCTRL3, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL4);
+	reg = (reg & DRVCTRL4_MASK) |
+	      DRVCTRL4_AVB_LINK(7) |
+	      DRVCTRL4_AVB_AVTP_MATCH(7) |
+	      DRVCTRL4_AVB_AVTP_CAPTURE(7) |
+	      DRVCTRL4_IRQ0(7) |
+	      DRVCTRL4_IRQ1(7) |
+	      DRVCTRL4_IRQ2(7) |
+	      DRVCTRL4_IRQ3(7) |
+	      DRVCTRL4_IRQ4(7);
+	pfc_reg_write(PFC_DRVCTRL4, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL5);
+	reg = (reg & DRVCTRL5_MASK) |
+	      DRVCTRL5_IRQ5(7) |
+	      DRVCTRL5_PWM0(7) |
+	      DRVCTRL5_PWM1(7) |
+	      DRVCTRL5_PWM2(7) |
+	      DRVCTRL5_A0(3) |
+	      DRVCTRL5_A1(3) |
+	      DRVCTRL5_A2(3) |
+	      DRVCTRL5_A3(3);
+	pfc_reg_write(PFC_DRVCTRL5, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL6);
+	reg = (reg & DRVCTRL6_MASK) |
+	      DRVCTRL6_A4(3) |
+	      DRVCTRL6_A5(3) |
+	      DRVCTRL6_A6(3) |
+	      DRVCTRL6_A7(3) |
+	      DRVCTRL6_A8(7) |
+	      DRVCTRL6_A9(7) |
+	      DRVCTRL6_A10(7) |
+	      DRVCTRL6_A11(7);
+	pfc_reg_write(PFC_DRVCTRL6, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL7);
+	reg = (reg & DRVCTRL7_MASK) |
+	      DRVCTRL7_A12(3) |
+	      DRVCTRL7_A13(3) |
+	      DRVCTRL7_A14(3) |
+	      DRVCTRL7_A15(3) |
+	      DRVCTRL7_A16(3) |
+	      DRVCTRL7_A17(3) |
+	      DRVCTRL7_A18(3) |
+	      DRVCTRL7_A19(3);
+	pfc_reg_write(PFC_DRVCTRL7, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL8);
+	reg = (reg & DRVCTRL8_MASK) |
+	      DRVCTRL8_CLKOUT(7) |
+	      DRVCTRL8_CS0(7) |
+	      DRVCTRL8_CS1_A2(7) |
+	      DRVCTRL8_BS(7) |
+	      DRVCTRL8_RD(7) |
+	      DRVCTRL8_RD_W(7) |
+	      DRVCTRL8_WE0(7) |
+	      DRVCTRL8_WE1(7);
+	pfc_reg_write(PFC_DRVCTRL8, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL9);
+	reg = (reg & DRVCTRL9_MASK) |
+	      DRVCTRL9_EX_WAIT0(7) |
+	      DRVCTRL9_PRESETOU(7) |
+	      DRVCTRL9_D0(7) |
+	      DRVCTRL9_D1(7) |
+	      DRVCTRL9_D2(7) |
+	      DRVCTRL9_D3(7) |
+	      DRVCTRL9_D4(7) |
+	      DRVCTRL9_D5(7);
+	pfc_reg_write(PFC_DRVCTRL9, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL10);
+	reg = (reg & DRVCTRL10_MASK) |
+	      DRVCTRL10_D6(7) |
+	      DRVCTRL10_D7(7) |
+	      DRVCTRL10_D8(3) |
+	      DRVCTRL10_D9(3) |
+	      DRVCTRL10_D10(3) |
+	      DRVCTRL10_D11(3) |
+	      DRVCTRL10_D12(3) |
+	      DRVCTRL10_D13(3);
+	pfc_reg_write(PFC_DRVCTRL10, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL11);
+	reg = (reg & DRVCTRL11_MASK) |
+	      DRVCTRL11_D14(3) |
+	      DRVCTRL11_D15(3) |
+	      DRVCTRL11_AVS1(7) |
+	      DRVCTRL11_AVS2(7) |
+	      DRVCTRL11_GP7_02(7) |
+	      DRVCTRL11_GP7_03(7) |
+	      DRVCTRL11_DU_DOTCLKIN0(3) |
+	      DRVCTRL11_DU_DOTCLKIN1(3);
+	pfc_reg_write(PFC_DRVCTRL11, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL12);
+	reg = (reg & DRVCTRL12_MASK) |
+	      DRVCTRL12_DU_DOTCLKIN2(3) |
+	      DRVCTRL12_DU_DOTCLKIN3(3) |
+	      DRVCTRL12_DU_FSCLKST(3) |
+	      DRVCTRL12_DU_TMS(3);
+	pfc_reg_write(PFC_DRVCTRL12, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL13);
+	reg = (reg & DRVCTRL13_MASK) |
+	      DRVCTRL13_TDO(3) |
+	      DRVCTRL13_ASEBRK(3) |
+	      DRVCTRL13_SD0_CLK(7) |
+	      DRVCTRL13_SD0_CMD(7) |
+	      DRVCTRL13_SD0_DAT0(7) |
+	      DRVCTRL13_SD0_DAT1(7) |
+	      DRVCTRL13_SD0_DAT2(7) |
+	      DRVCTRL13_SD0_DAT3(7);
+	pfc_reg_write(PFC_DRVCTRL13, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL14);
+	reg = (reg & DRVCTRL14_MASK) |
+	      DRVCTRL14_SD1_CLK(7) |
+	      DRVCTRL14_SD1_CMD(7) |
+	      DRVCTRL14_SD1_DAT0(5) |
+	      DRVCTRL14_SD1_DAT1(5) |
+	      DRVCTRL14_SD1_DAT2(5) |
+	      DRVCTRL14_SD1_DAT3(5) |
+	      DRVCTRL14_SD2_CLK(5) |
+	      DRVCTRL14_SD2_CMD(5);
+	pfc_reg_write(PFC_DRVCTRL14, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL15);
+	reg = (reg & DRVCTRL15_MASK) |
+	      DRVCTRL15_SD2_DAT0(5) |
+	      DRVCTRL15_SD2_DAT1(5) |
+	      DRVCTRL15_SD2_DAT2(5) |
+	      DRVCTRL15_SD2_DAT3(5) |
+	      DRVCTRL15_SD2_DS(5) |
+	      DRVCTRL15_SD3_CLK(7) |
+	      DRVCTRL15_SD3_CMD(7) |
+	      DRVCTRL15_SD3_DAT0(7);
+	pfc_reg_write(PFC_DRVCTRL15, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL16);
+	reg = (reg & DRVCTRL16_MASK) |
+	      DRVCTRL16_SD3_DAT1(7) |
+	      DRVCTRL16_SD3_DAT2(7) |
+	      DRVCTRL16_SD3_DAT3(7) |
+	      DRVCTRL16_SD3_DAT4(7) |
+	      DRVCTRL16_SD3_DAT5(7) |
+	      DRVCTRL16_SD3_DAT6(7) |
+	      DRVCTRL16_SD3_DAT7(7) |
+	      DRVCTRL16_SD3_DS(7);
+	pfc_reg_write(PFC_DRVCTRL16, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL17);
+	reg = (reg & DRVCTRL17_MASK) |
+	      DRVCTRL17_SD0_CD(7) |
+	      DRVCTRL17_SD0_WP(7) |
+	      DRVCTRL17_SD1_CD(7) |
+	      DRVCTRL17_SD1_WP(7) |
+	      DRVCTRL17_SCK0(7) |
+	      DRVCTRL17_RX0(7) |
+	      DRVCTRL17_TX0(7) |
+	      DRVCTRL17_CTS0(7);
+	pfc_reg_write(PFC_DRVCTRL17, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL18);
+	reg = (reg & DRVCTRL18_MASK) |
+	      DRVCTRL18_RTS0_TANS(7) |
+	      DRVCTRL18_RX1(7) |
+	      DRVCTRL18_TX1(7) |
+	      DRVCTRL18_CTS1(7) |
+	      DRVCTRL18_RTS1_TANS(7) |
+	      DRVCTRL18_SCK2(7) |
+	      DRVCTRL18_TX2(7) |
+	      DRVCTRL18_RX2(7);
+	pfc_reg_write(PFC_DRVCTRL18, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL19);
+	reg = (reg & DRVCTRL19_MASK) |
+	      DRVCTRL19_HSCK0(7) |
+	      DRVCTRL19_HRX0(7) |
+	      DRVCTRL19_HTX0(7) |
+	      DRVCTRL19_HCTS0(7) |
+	      DRVCTRL19_HRTS0(7) |
+	      DRVCTRL19_MSIOF0_SCK(7) |
+	      DRVCTRL19_MSIOF0_SYNC(7) |
+	      DRVCTRL19_MSIOF0_SS1(7);
+	pfc_reg_write(PFC_DRVCTRL19, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL20);
+	reg = (reg & DRVCTRL20_MASK) |
+	      DRVCTRL20_MSIOF0_TXD(7) |
+	      DRVCTRL20_MSIOF0_SS2(7) |
+	      DRVCTRL20_MSIOF0_RXD(7) |
+	      DRVCTRL20_MLB_CLK(7) |
+	      DRVCTRL20_MLB_SIG(7) |
+	      DRVCTRL20_MLB_DAT(7) |
+	      DRVCTRL20_MLB_REF(7) |
+	      DRVCTRL20_SSI_SCK0129(7);
+	pfc_reg_write(PFC_DRVCTRL20, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL21);
+	reg = (reg & DRVCTRL21_MASK) |
+	      DRVCTRL21_SSI_WS0129(7) |
+	      DRVCTRL21_SSI_SDATA0(7) |
+	      DRVCTRL21_SSI_SDATA1(7) |
+	      DRVCTRL21_SSI_SDATA2(7) |
+	      DRVCTRL21_SSI_SCK34(7) |
+	      DRVCTRL21_SSI_WS34(7) |
+	      DRVCTRL21_SSI_SDATA3(7) |
+	      DRVCTRL21_SSI_SCK4(7);
+	pfc_reg_write(PFC_DRVCTRL21, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL22);
+	reg = (reg & DRVCTRL22_MASK) |
+	      DRVCTRL22_SSI_WS4(7) |
+	      DRVCTRL22_SSI_SDATA4(7) |
+	      DRVCTRL22_SSI_SCK5(7) |
+	      DRVCTRL22_SSI_WS5(7) |
+	      DRVCTRL22_SSI_SDATA5(7) |
+	      DRVCTRL22_SSI_SCK6(7) |
+	      DRVCTRL22_SSI_WS6(7) |
+	      DRVCTRL22_SSI_SDATA6(7);
+	pfc_reg_write(PFC_DRVCTRL22, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL23);
+	reg = (reg & DRVCTRL23_MASK) |
+	      DRVCTRL23_SSI_SCK78(7) |
+	      DRVCTRL23_SSI_WS78(7) |
+	      DRVCTRL23_SSI_SDATA7(7) |
+	      DRVCTRL23_SSI_SDATA8(7) |
+	      DRVCTRL23_SSI_SDATA9(7) |
+	      DRVCTRL23_AUDIO_CLKA(7) |
+	      DRVCTRL23_AUDIO_CLKB(7) |
+	      DRVCTRL23_USB0_PWEN(7);
+	pfc_reg_write(PFC_DRVCTRL23, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL24);
+	reg = (reg & DRVCTRL24_MASK) |
+	      DRVCTRL24_USB0_OVC(7) |
+	      DRVCTRL24_USB1_PWEN(7) |
+	      DRVCTRL24_USB1_OVC(7) |
+	      DRVCTRL24_USB30_PWEN(7) |
+	      DRVCTRL24_USB30_OVC(7) |
+	      DRVCTRL24_USB31_PWEN(7) |
+	      DRVCTRL24_USB31_OVC(7);
+	pfc_reg_write(PFC_DRVCTRL24, reg);
+
+	/* initialize LSI pin pull-up/down control */
+	pfc_reg_write(PFC_PUD0, 0x00005FBFU);
+	pfc_reg_write(PFC_PUD1, 0x00300EFEU);
+	pfc_reg_write(PFC_PUD2, 0x330001E6U);
+	pfc_reg_write(PFC_PUD3, 0x000002E0U);
+	pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
+	pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
+	pfc_reg_write(PFC_PUD6, 0x00000055U);
+
+	/* initialize LSI pin pull-enable register */
+	pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
+	pfc_reg_write(PFC_PUEN1, 0x00100234U);
+	pfc_reg_write(PFC_PUEN2, 0x000004C4U);
+	pfc_reg_write(PFC_PUEN3, 0x00000200U);
+	pfc_reg_write(PFC_PUEN4, 0x3E000000U);
+	pfc_reg_write(PFC_PUEN5, 0x1F000805U);
+	pfc_reg_write(PFC_PUEN6, 0x00000006U);
+
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG7, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT0, 0x00000001U);
+	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+	mmio_write_32(GPIO_OUTDT3, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT4, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT6, 0x00003800U);
+	mmio_write_32(GPIO_OUTDT7, 0x00000003U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00000001U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x00100B00U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x00000418U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x00002000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00000040U);
+	mmio_write_32(GPIO_INOUTSEL5, 0x00000208U);
+	mmio_write_32(GPIO_INOUTSEL6, 0x00013F00U);
+	mmio_write_32(GPIO_INOUTSEL7, 0x00000003U);
+}
diff --git a/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.h b/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.h
new file mode 100644
index 0000000..5efce45
--- /dev/null
+++ b/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_G2H_H
+#define PFC_INIT_G2H_H
+
+void pfc_init_g2h(void);
+
+#endif /* PFC_INIT_G2H_H */
diff --git a/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c b/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c
new file mode 100644
index 0000000..c951e0a
--- /dev/null
+++ b/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c
@@ -0,0 +1,1306 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <lib/mmio.h>
+
+#include "pfc_init_g2n.h"
+#include "rcar_def.h"
+#include "../pfc_regs.h"
+
+#define GPSR0_D15			BIT(15)
+#define GPSR0_D14			BIT(14)
+#define GPSR0_D13			BIT(13)
+#define GPSR0_D12			BIT(12)
+#define GPSR0_D11			BIT(11)
+#define GPSR0_D10			BIT(10)
+#define GPSR0_D9			BIT(9)
+#define GPSR0_D8			BIT(8)
+#define GPSR0_D7			BIT(7)
+#define GPSR0_D6			BIT(6)
+#define GPSR0_D5			BIT(5)
+#define GPSR0_D4			BIT(4)
+#define GPSR0_D3			BIT(3)
+#define GPSR0_D2			BIT(2)
+#define GPSR0_D1			BIT(1)
+#define GPSR0_D0			BIT(0)
+#define GPSR1_CLKOUT			BIT(28)
+#define GPSR1_EX_WAIT0_A		BIT(27)
+#define GPSR1_WE1			BIT(26)
+#define GPSR1_WE0			BIT(25)
+#define GPSR1_RD_WR			BIT(24)
+#define GPSR1_RD			BIT(23)
+#define GPSR1_BS			BIT(22)
+#define GPSR1_CS1_A26			BIT(21)
+#define GPSR1_CS0			BIT(20)
+#define GPSR1_A19			BIT(19)
+#define GPSR1_A18			BIT(18)
+#define GPSR1_A17			BIT(17)
+#define GPSR1_A16			BIT(16)
+#define GPSR1_A15			BIT(15)
+#define GPSR1_A14			BIT(14)
+#define GPSR1_A13			BIT(13)
+#define GPSR1_A12			BIT(12)
+#define GPSR1_A11			BIT(11)
+#define GPSR1_A10			BIT(10)
+#define GPSR1_A9			BIT(9)
+#define GPSR1_A8			BIT(8)
+#define GPSR1_A7			BIT(7)
+#define GPSR1_A6			BIT(6)
+#define GPSR1_A5			BIT(5)
+#define GPSR1_A4			BIT(4)
+#define GPSR1_A3			BIT(3)
+#define GPSR1_A2			BIT(2)
+#define GPSR1_A1			BIT(1)
+#define GPSR1_A0			BIT(0)
+#define GPSR2_AVB_AVTP_CAPTURE_A	BIT(14)
+#define GPSR2_AVB_AVTP_MATCH_A		BIT(13)
+#define GPSR2_AVB_LINK			BIT(12)
+#define GPSR2_AVB_PHY_INT		BIT(11)
+#define GPSR2_AVB_MAGIC			BIT(10)
+#define GPSR2_AVB_MDC			BIT(9)
+#define GPSR2_PWM2_A			BIT(8)
+#define GPSR2_PWM1_A			BIT(7)
+#define GPSR2_PWM0			BIT(6)
+#define GPSR2_IRQ5			BIT(5)
+#define GPSR2_IRQ4			BIT(4)
+#define GPSR2_IRQ3			BIT(3)
+#define GPSR2_IRQ2			BIT(2)
+#define GPSR2_IRQ1			BIT(1)
+#define GPSR2_IRQ0			BIT(0)
+#define GPSR3_SD1_WP			BIT(15)
+#define GPSR3_SD1_CD			BIT(14)
+#define GPSR3_SD0_WP			BIT(13)
+#define GPSR3_SD0_CD			BIT(12)
+#define GPSR3_SD1_DAT3			BIT(11)
+#define GPSR3_SD1_DAT2			BIT(10)
+#define GPSR3_SD1_DAT1			BIT(9)
+#define GPSR3_SD1_DAT0			BIT(8)
+#define GPSR3_SD1_CMD			BIT(7)
+#define GPSR3_SD1_CLK			BIT(6)
+#define GPSR3_SD0_DAT3			BIT(5)
+#define GPSR3_SD0_DAT2			BIT(4)
+#define GPSR3_SD0_DAT1			BIT(3)
+#define GPSR3_SD0_DAT0			BIT(2)
+#define GPSR3_SD0_CMD			BIT(1)
+#define GPSR3_SD0_CLK			BIT(0)
+#define GPSR4_SD3_DS			BIT(17)
+#define GPSR4_SD3_DAT7			BIT(16)
+#define GPSR4_SD3_DAT6			BIT(15)
+#define GPSR4_SD3_DAT5			BIT(14)
+#define GPSR4_SD3_DAT4			BIT(13)
+#define GPSR4_SD3_DAT3			BIT(12)
+#define GPSR4_SD3_DAT2			BIT(11)
+#define GPSR4_SD3_DAT1			BIT(10)
+#define GPSR4_SD3_DAT0			BIT(9)
+#define GPSR4_SD3_CMD			BIT(8)
+#define GPSR4_SD3_CLK			BIT(7)
+#define GPSR4_SD2_DS			BIT(6)
+#define GPSR4_SD2_DAT3			BIT(5)
+#define GPSR4_SD2_DAT2			BIT(4)
+#define GPSR4_SD2_DAT1			BIT(3)
+#define GPSR4_SD2_DAT0			BIT(2)
+#define GPSR4_SD2_CMD			BIT(1)
+#define GPSR4_SD2_CLK			BIT(0)
+#define GPSR5_MLB_DAT			BIT(25)
+#define GPSR5_MLB_SIG			BIT(24)
+#define GPSR5_MLB_CLK			BIT(23)
+#define GPSR5_MSIOF0_RXD		BIT(22)
+#define GPSR5_MSIOF0_SS2		BIT(21)
+#define GPSR5_MSIOF0_TXD		BIT(20)
+#define GPSR5_MSIOF0_SS1		BIT(19)
+#define GPSR5_MSIOF0_SYNC		BIT(18)
+#define GPSR5_MSIOF0_SCK		BIT(17)
+#define GPSR5_HRTS0			BIT(16)
+#define GPSR5_HCTS0			BIT(15)
+#define GPSR5_HTX0			BIT(14)
+#define GPSR5_HRX0			BIT(13)
+#define GPSR5_HSCK0			BIT(12)
+#define GPSR5_RX2_A			BIT(11)
+#define GPSR5_TX2_A			BIT(10)
+#define GPSR5_SCK2			BIT(9)
+#define GPSR5_RTS1			BIT(8)
+#define GPSR5_CTS1			BIT(7)
+#define GPSR5_TX1_A			BIT(6)
+#define GPSR5_RX1_A			BIT(5)
+#define GPSR5_RTS0			BIT(4)
+#define GPSR5_CTS0			BIT(3)
+#define GPSR5_TX0			BIT(2)
+#define GPSR5_RX0			BIT(1)
+#define GPSR5_SCK0			BIT(0)
+#define GPSR6_USB31_OVC			BIT(31)
+#define GPSR6_USB31_PWEN		BIT(30)
+#define GPSR6_USB30_OVC			BIT(29)
+#define GPSR6_USB30_PWEN		BIT(28)
+#define GPSR6_USB1_OVC			BIT(27)
+#define GPSR6_USB1_PWEN			BIT(26)
+#define GPSR6_USB0_OVC			BIT(25)
+#define GPSR6_USB0_PWEN			BIT(24)
+#define GPSR6_AUDIO_CLKB_B		BIT(23)
+#define GPSR6_AUDIO_CLKA_A		BIT(22)
+#define GPSR6_SSI_SDATA9_A		BIT(21)
+#define GPSR6_SSI_SDATA8		BIT(20)
+#define GPSR6_SSI_SDATA7		BIT(19)
+#define GPSR6_SSI_WS78			BIT(18)
+#define GPSR6_SSI_SCK78			BIT(17)
+#define GPSR6_SSI_SDATA6		BIT(16)
+#define GPSR6_SSI_WS6			BIT(15)
+#define GPSR6_SSI_SCK6			BIT(14)
+#define GPSR6_SSI_SDATA5		BIT(13)
+#define GPSR6_SSI_WS5			BIT(12)
+#define GPSR6_SSI_SCK5			BIT(11)
+#define GPSR6_SSI_SDATA4		BIT(10)
+#define GPSR6_SSI_WS4			BIT(9)
+#define GPSR6_SSI_SCK4			BIT(8)
+#define GPSR6_SSI_SDATA3		BIT(7)
+#define GPSR6_SSI_WS34			BIT(6)
+#define GPSR6_SSI_SCK34			BIT(5)
+#define GPSR6_SSI_SDATA2_A		BIT(4)
+#define GPSR6_SSI_SDATA1_A		BIT(3)
+#define GPSR6_SSI_SDATA0		BIT(2)
+#define GPSR6_SSI_WS0129		BIT(1)
+#define GPSR6_SSI_SCK0129		BIT(0)
+#define GPSR7_AVS2			BIT(1)
+#define GPSR7_AVS1			BIT(0)
+
+#define IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
+
+#define POC_SD3_DS_33V		BIT(29)
+#define POC_SD3_DAT7_33V	BIT(28)
+#define POC_SD3_DAT6_33V	BIT(27)
+#define POC_SD3_DAT5_33V	BIT(26)
+#define POC_SD3_DAT4_33V	BIT(25)
+#define POC_SD3_DAT3_33V	BIT(24)
+#define POC_SD3_DAT2_33V	BIT(23)
+#define POC_SD3_DAT1_33V	BIT(22)
+#define POC_SD3_DAT0_33V	BIT(21)
+#define POC_SD3_CMD_33V		BIT(20)
+#define POC_SD3_CLK_33V		BIT(19)
+#define POC_SD2_DS_33V		BIT(18)
+#define POC_SD2_DAT3_33V	BIT(17)
+#define POC_SD2_DAT2_33V	BIT(16)
+#define POC_SD2_DAT1_33V	BIT(15)
+#define POC_SD2_DAT0_33V	BIT(14)
+#define POC_SD2_CMD_33V		BIT(13)
+#define POC_SD2_CLK_33V		BIT(12)
+#define POC_SD1_DAT3_33V	BIT(11)
+#define POC_SD1_DAT2_33V	BIT(10)
+#define POC_SD1_DAT1_33V	BIT(9)
+#define POC_SD1_DAT0_33V	BIT(8)
+#define POC_SD1_CMD_33V		BIT(7)
+#define POC_SD1_CLK_33V		BIT(6)
+#define POC_SD0_DAT3_33V	BIT(5)
+#define POC_SD0_DAT2_33V	BIT(4)
+#define POC_SD0_DAT1_33V	BIT(3)
+#define POC_SD0_DAT0_33V	BIT(2)
+#define POC_SD0_CMD_33V		BIT(1)
+#define POC_SD0_CLK_33V		BIT(0)
+
+#define DRVCTRL0_MASK		(0xCCCCCCCCU)
+#define DRVCTRL1_MASK		(0xCCCCCCC8U)
+#define DRVCTRL2_MASK		(0x88888888U)
+#define DRVCTRL3_MASK		(0x88888888U)
+#define DRVCTRL4_MASK		(0x88888888U)
+#define DRVCTRL5_MASK		(0x88888888U)
+#define DRVCTRL6_MASK		(0x88888888U)
+#define DRVCTRL7_MASK		(0x88888888U)
+#define DRVCTRL8_MASK		(0x88888888U)
+#define DRVCTRL9_MASK		(0x88888888U)
+#define DRVCTRL10_MASK		(0x88888888U)
+#define DRVCTRL11_MASK		(0x888888CCU)
+#define DRVCTRL12_MASK		(0xCCCFFFCFU)
+#define DRVCTRL13_MASK		(0xCC888888U)
+#define DRVCTRL14_MASK		(0x88888888U)
+#define DRVCTRL15_MASK		(0x88888888U)
+#define DRVCTRL16_MASK		(0x88888888U)
+#define DRVCTRL17_MASK		(0x88888888U)
+#define DRVCTRL18_MASK		(0x88888888U)
+#define DRVCTRL19_MASK		(0x88888888U)
+#define DRVCTRL20_MASK		(0x88888888U)
+#define DRVCTRL21_MASK		(0x88888888U)
+#define DRVCTRL22_MASK		(0x88888888U)
+#define DRVCTRL23_MASK		(0x88888888U)
+#define DRVCTRL24_MASK		(0x8888888FU)
+
+#define DRVCTRL0_QSPI0_SPCLK(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL0_QSPI0_IO2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL0_QSPI0_IO3(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL0_QSPI0_SSL(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL0_QSPI1_SPCLK(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL1_QSPI1_IO2(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL1_QSPI1_IO3(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL1_QSPI1_SS(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL1_RPC_INT(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL1_RPC_WP(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL1_RPC_RESET(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL1_AVB_RX_CTL(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL2_AVB_RXC(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL2_AVB_RD0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL2_AVB_RD1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL2_AVB_RD2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL2_AVB_RD3(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL2_AVB_TX_CTL(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL2_AVB_TXC(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL2_AVB_TD0(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL3_AVB_TD1(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL3_AVB_TD2(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL3_AVB_TD3(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL3_AVB_MDIO(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL3_AVB_MDC(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL3_AVB_MAGIC(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL3_AVB_PHY_INT(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL4_AVB_LINK(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL4_IRQ0(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL4_IRQ1(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL4_IRQ2(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL4_IRQ3(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL4_IRQ4(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL5_IRQ5(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL5_PWM0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL5_PWM1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL5_PWM2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL5_A0(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL5_A1(x)			((uint32_t)(x) << 8U)
+#define DRVCTRL5_A2(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL5_A3(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL6_A4(x)			((uint32_t)(x) << 28U)
+#define DRVCTRL6_A5(x)			((uint32_t)(x) << 24U)
+#define DRVCTRL6_A6(x)			((uint32_t)(x) << 20U)
+#define DRVCTRL6_A7(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL6_A8(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL6_A9(x)			((uint32_t)(x) << 8U)
+#define DRVCTRL6_A10(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL6_A11(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL7_A12(x)			((uint32_t)(x) << 28U)
+#define DRVCTRL7_A13(x)			((uint32_t)(x) << 24U)
+#define DRVCTRL7_A14(x)			((uint32_t)(x) << 20U)
+#define DRVCTRL7_A15(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL7_A16(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL7_A17(x)			((uint32_t)(x) << 8U)
+#define DRVCTRL7_A18(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL7_A19(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL8_CLKOUT(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL8_CS0(x)			((uint32_t)(x) << 24U)
+#define DRVCTRL8_CS1_A2(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL8_BS(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL8_RD(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL8_RD_W(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL8_WE0(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL8_WE1(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL9_EX_WAIT0(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL9_PRESETOU(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL9_D0(x)			((uint32_t)(x) << 20U)
+#define DRVCTRL9_D1(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL9_D2(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL9_D3(x)			((uint32_t)(x) << 8U)
+#define DRVCTRL9_D4(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL9_D5(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL10_D6(x)			((uint32_t)(x) << 28U)
+#define DRVCTRL10_D7(x)			((uint32_t)(x) << 24U)
+#define DRVCTRL10_D8(x)			((uint32_t)(x) << 20U)
+#define DRVCTRL10_D9(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL10_D10(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL10_D11(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL10_D12(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL10_D13(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL11_D14(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL11_D15(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL11_AVS1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL11_AVS2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL11_GP7_02(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL11_GP7_03(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL12_DU_FSCLKST(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL12_DU_TMS(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL13_TDO(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL13_ASEBRK(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL13_SD0_CLK(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL13_SD0_CMD(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL13_SD0_DAT0(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL13_SD0_DAT1(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL13_SD0_DAT2(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL13_SD0_DAT3(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL14_SD1_CLK(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL14_SD1_CMD(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL14_SD1_DAT0(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL14_SD1_DAT1(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL14_SD1_DAT2(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL14_SD1_DAT3(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL14_SD2_CLK(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL14_SD2_CMD(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL15_SD2_DAT0(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL15_SD2_DAT1(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL15_SD2_DAT2(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL15_SD2_DAT3(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL15_SD2_DS(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL15_SD3_CLK(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL15_SD3_CMD(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL15_SD3_DAT0(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL16_SD3_DAT1(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL16_SD3_DAT2(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL16_SD3_DAT3(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL16_SD3_DAT4(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL16_SD3_DAT5(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL16_SD3_DAT6(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL16_SD3_DAT7(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL16_SD3_DS(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL17_SD0_CD(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL17_SD0_WP(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL17_SD1_CD(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL17_SD1_WP(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL17_SCK0(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL17_RX0(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL17_TX0(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL17_CTS0(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL18_RTS0_TANS(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL18_RX1(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL18_TX1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL18_CTS1(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL18_RTS1_TANS(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL18_SCK2(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL18_TX2(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL18_RX2(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL19_HSCK0(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL19_HRX0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL19_HTX0(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL19_HCTS0(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL19_HRTS0(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL19_MSIOF0_SCK(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL19_MSIOF0_SS1(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL20_MSIOF0_TXD(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL20_MSIOF0_SS2(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL20_MSIOF0_RXD(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL20_MLB_CLK(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL20_MLB_SIG(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL20_MLB_DAT(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL20_MLB_REF(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL21_SSI_WS0129(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL21_SSI_SDATA0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL21_SSI_SDATA1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL21_SSI_SDATA2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL21_SSI_SCK34(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL21_SSI_WS34(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL21_SSI_SDATA3(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL21_SSI_SCK4(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL22_SSI_WS4(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL22_SSI_SDATA4(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL22_SSI_SCK5(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL22_SSI_WS5(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL22_SSI_SDATA5(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL22_SSI_SCK6(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL22_SSI_WS6(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL22_SSI_SDATA6(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL23_SSI_SCK78(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL23_SSI_WS78(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL23_SSI_SDATA7(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL23_SSI_SDATA8(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL23_SSI_SDATA9(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL23_AUDIO_CLKA(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL23_AUDIO_CLKB(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL23_USB0_PWEN(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL24_USB0_OVC(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL24_USB1_PWEN(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL24_USB1_OVC(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL24_USB30_PWEN(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL24_USB30_OVC(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL24_USB31_PWEN(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL24_USB31_OVC(x)		((uint32_t)(x) << 4U)
+
+#define MOD_SEL0_MSIOF3_A		((uint32_t)0U << 29U)
+#define MOD_SEL0_MSIOF3_B		((uint32_t)1U << 29U)
+#define MOD_SEL0_MSIOF3_C		((uint32_t)2U << 29U)
+#define MOD_SEL0_MSIOF3_D		((uint32_t)3U << 29U)
+#define MOD_SEL0_MSIOF3_E		((uint32_t)4U << 29U)
+#define MOD_SEL0_MSIOF2_A		((uint32_t)0U << 27U)
+#define MOD_SEL0_MSIOF2_B		((uint32_t)1U << 27U)
+#define MOD_SEL0_MSIOF2_C		((uint32_t)2U << 27U)
+#define MOD_SEL0_MSIOF2_D		((uint32_t)3U << 27U)
+#define MOD_SEL0_MSIOF1_A		((uint32_t)0U << 24U)
+#define MOD_SEL0_MSIOF1_B		((uint32_t)1U << 24U)
+#define MOD_SEL0_MSIOF1_C		((uint32_t)2U << 24U)
+#define MOD_SEL0_MSIOF1_D		((uint32_t)3U << 24U)
+#define MOD_SEL0_MSIOF1_E		((uint32_t)4U << 24U)
+#define MOD_SEL0_MSIOF1_F		((uint32_t)5U << 24U)
+#define MOD_SEL0_MSIOF1_G		((uint32_t)6U << 24U)
+#define MOD_SEL0_LBSC_A			((uint32_t)0U << 23U)
+#define MOD_SEL0_LBSC_B			((uint32_t)1U << 23U)
+#define MOD_SEL0_IEBUS_A		((uint32_t)0U << 22U)
+#define MOD_SEL0_IEBUS_B		((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C2_A			((uint32_t)0U << 21U)
+#define MOD_SEL0_I2C2_B			((uint32_t)1U << 21U)
+#define MOD_SEL0_I2C1_A			((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B			((uint32_t)1U << 20U)
+#define MOD_SEL0_HSCIF4_A		((uint32_t)0U << 19U)
+#define MOD_SEL0_HSCIF4_B		((uint32_t)1U << 19U)
+#define MOD_SEL0_HSCIF3_A		((uint32_t)0U << 17U)
+#define MOD_SEL0_HSCIF3_B		((uint32_t)1U << 17U)
+#define MOD_SEL0_HSCIF3_C		((uint32_t)2U << 17U)
+#define MOD_SEL0_HSCIF3_D		((uint32_t)3U << 17U)
+#define MOD_SEL0_HSCIF1_A		((uint32_t)0U << 16U)
+#define MOD_SEL0_HSCIF1_B		((uint32_t)1U << 16U)
+#define MOD_SEL0_FSO_A			((uint32_t)0U << 15U)
+#define MOD_SEL0_FSO_B			((uint32_t)1U << 15U)
+#define MOD_SEL0_HSCIF2_A		((uint32_t)0U << 13U)
+#define MOD_SEL0_HSCIF2_B		((uint32_t)1U << 13U)
+#define MOD_SEL0_HSCIF2_C		((uint32_t)2U << 13U)
+#define MOD_SEL0_ETHERAVB_A		((uint32_t)0U << 12U)
+#define MOD_SEL0_ETHERAVB_B		((uint32_t)1U << 12U)
+#define MOD_SEL0_DRIF3_A		((uint32_t)0U << 11U)
+#define MOD_SEL0_DRIF3_B		((uint32_t)1U << 11U)
+#define MOD_SEL0_DRIF2_A		((uint32_t)0U << 10U)
+#define MOD_SEL0_DRIF2_B		((uint32_t)1U << 10U)
+#define MOD_SEL0_DRIF1_A		((uint32_t)0U << 8U)
+#define MOD_SEL0_DRIF1_B		((uint32_t)1U << 8U)
+#define MOD_SEL0_DRIF1_C		((uint32_t)2U << 8U)
+#define MOD_SEL0_DRIF0_A		((uint32_t)0U << 6U)
+#define MOD_SEL0_DRIF0_B		((uint32_t)1U << 6U)
+#define MOD_SEL0_DRIF0_C		((uint32_t)2U << 6U)
+#define MOD_SEL0_CANFD0_A		((uint32_t)0U << 5U)
+#define MOD_SEL0_CANFD0_B		((uint32_t)1U << 5U)
+#define MOD_SEL0_ADG_A_A		((uint32_t)0U << 3U)
+#define MOD_SEL0_ADG_A_B		((uint32_t)1U << 3U)
+#define MOD_SEL0_ADG_A_C		((uint32_t)2U << 3U)
+#define MOD_SEL1_TSIF1_A		((uint32_t)0U << 30U)
+#define MOD_SEL1_TSIF1_B		((uint32_t)1U << 30U)
+#define MOD_SEL1_TSIF1_C		((uint32_t)2U << 30U)
+#define MOD_SEL1_TSIF1_D		((uint32_t)3U << 30U)
+#define MOD_SEL1_TSIF0_A		((uint32_t)0U << 27U)
+#define MOD_SEL1_TSIF0_B		((uint32_t)1U << 27U)
+#define MOD_SEL1_TSIF0_C		((uint32_t)2U << 27U)
+#define MOD_SEL1_TSIF0_D		((uint32_t)3U << 27U)
+#define MOD_SEL1_TSIF0_E		((uint32_t)4U << 27U)
+#define MOD_SEL1_TIMER_TMU_A		((uint32_t)0U << 26U)
+#define MOD_SEL1_TIMER_TMU_B		((uint32_t)1U << 26U)
+#define MOD_SEL1_SSP1_1_A		((uint32_t)0U << 24U)
+#define MOD_SEL1_SSP1_1_B		((uint32_t)1U << 24U)
+#define MOD_SEL1_SSP1_1_C		((uint32_t)2U << 24U)
+#define MOD_SEL1_SSP1_1_D		((uint32_t)3U << 24U)
+#define MOD_SEL1_SSP1_0_A		((uint32_t)0U << 21U)
+#define MOD_SEL1_SSP1_0_B		((uint32_t)1U << 21U)
+#define MOD_SEL1_SSP1_0_C		((uint32_t)2U << 21U)
+#define MOD_SEL1_SSP1_0_D		((uint32_t)3U << 21U)
+#define MOD_SEL1_SSP1_0_E		((uint32_t)4U << 21U)
+#define MOD_SEL1_SSI_A			((uint32_t)0U << 20U)
+#define MOD_SEL1_SSI_B			((uint32_t)1U << 20U)
+#define MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
+#define MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
+#define MOD_SEL1_SIMCARD_A		((uint32_t)0U << 17U)
+#define MOD_SEL1_SIMCARD_B		((uint32_t)1U << 17U)
+#define MOD_SEL1_SIMCARD_C		((uint32_t)2U << 17U)
+#define MOD_SEL1_SIMCARD_D		((uint32_t)3U << 17U)
+#define MOD_SEL1_SDHI2_A		((uint32_t)0U << 16U)
+#define MOD_SEL1_SDHI2_B		((uint32_t)1U << 16U)
+#define MOD_SEL1_SCIF4_A		((uint32_t)0U << 14U)
+#define MOD_SEL1_SCIF4_B		((uint32_t)1U << 14U)
+#define MOD_SEL1_SCIF4_C		((uint32_t)2U << 14U)
+#define MOD_SEL1_SCIF3_A		((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B		((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF2_A		((uint32_t)0U << 12U)
+#define MOD_SEL1_SCIF2_B		((uint32_t)1U << 12U)
+#define MOD_SEL1_SCIF1_A		((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF1_B		((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF_A			((uint32_t)0U << 10U)
+#define MOD_SEL1_SCIF_B			((uint32_t)1U << 10U)
+#define MOD_SEL1_REMOCON_A		((uint32_t)0U << 9U)
+#define MOD_SEL1_REMOCON_B		((uint32_t)1U << 9U)
+#define MOD_SEL1_RCAN0_A		((uint32_t)0U << 6U)
+#define MOD_SEL1_RCAN0_B		((uint32_t)1U << 6U)
+#define MOD_SEL1_PWM6_A			((uint32_t)0U << 5U)
+#define MOD_SEL1_PWM6_B			((uint32_t)1U << 5U)
+#define MOD_SEL1_PWM5_A			((uint32_t)0U << 4U)
+#define MOD_SEL1_PWM5_B			((uint32_t)1U << 4U)
+#define MOD_SEL1_PWM4_A			((uint32_t)0U << 3U)
+#define MOD_SEL1_PWM4_B			((uint32_t)1U << 3U)
+#define MOD_SEL1_PWM3_A			((uint32_t)0U << 2U)
+#define MOD_SEL1_PWM3_B			((uint32_t)1U << 2U)
+#define MOD_SEL1_PWM2_A			((uint32_t)0U << 1U)
+#define MOD_SEL1_PWM2_B			((uint32_t)1U << 1U)
+#define MOD_SEL1_PWM1_A			((uint32_t)0U << 0U)
+#define MOD_SEL1_PWM1_B			((uint32_t)1U << 0U)
+#define MOD_SEL2_I2C_5_A		((uint32_t)0U << 31U)
+#define MOD_SEL2_I2C_5_B		((uint32_t)1U << 31U)
+#define MOD_SEL2_I2C_3_A		((uint32_t)0U << 30U)
+#define MOD_SEL2_I2C_3_B		((uint32_t)1U << 30U)
+#define MOD_SEL2_I2C_0_A		((uint32_t)0U << 29U)
+#define MOD_SEL2_I2C_0_B		((uint32_t)1U << 29U)
+#define MOD_SEL2_FM_A			((uint32_t)0U << 27U)
+#define MOD_SEL2_FM_B			((uint32_t)1U << 27U)
+#define MOD_SEL2_FM_C			((uint32_t)2U << 27U)
+#define MOD_SEL2_FM_D			((uint32_t)3U << 27U)
+#define MOD_SEL2_SCIF5_A		((uint32_t)0U << 26U)
+#define MOD_SEL2_SCIF5_B		((uint32_t)1U << 26U)
+#define MOD_SEL2_I2C6_A			((uint32_t)0U << 23U)
+#define MOD_SEL2_I2C6_B			((uint32_t)1U << 23U)
+#define MOD_SEL2_I2C6_C			((uint32_t)2U << 23U)
+#define MOD_SEL2_NDF_A			((uint32_t)0U << 22U)
+#define MOD_SEL2_NDF_B			((uint32_t)1U << 22U)
+#define MOD_SEL2_SSI2_A			((uint32_t)0U << 21U)
+#define MOD_SEL2_SSI2_B			((uint32_t)1U << 21U)
+#define MOD_SEL2_SSI9_A			((uint32_t)0U << 20U)
+#define MOD_SEL2_SSI9_B			((uint32_t)1U << 20U)
+#define MOD_SEL2_TIMER_TMU2_A		((uint32_t)0U << 19U)
+#define MOD_SEL2_TIMER_TMU2_B		((uint32_t)1U << 19U)
+#define MOD_SEL2_ADG_B_A		((uint32_t)0U << 18U)
+#define MOD_SEL2_ADG_B_B		((uint32_t)1U << 18U)
+#define MOD_SEL2_ADG_C_A		((uint32_t)0U << 17U)
+#define MOD_SEL2_ADG_C_B		((uint32_t)1U << 17U)
+#define MOD_SEL2_VIN4_A			((uint32_t)0U << 0U)
+#define MOD_SEL2_VIN4_B			((uint32_t)1U << 0U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	mmio_write_32(PFC_PMMR, ~data);
+	mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_g2n(void)
+{
+	uint32_t reg;
+
+	/* initialize module select */
+	pfc_reg_write(PFC_MOD_SEL0,
+		      MOD_SEL0_MSIOF3_A |
+		      MOD_SEL0_MSIOF2_A |
+		      MOD_SEL0_MSIOF1_A |
+		      MOD_SEL0_LBSC_A |
+		      MOD_SEL0_IEBUS_A |
+		      MOD_SEL0_I2C2_A |
+		      MOD_SEL0_I2C1_A |
+		      MOD_SEL0_HSCIF4_A |
+		      MOD_SEL0_HSCIF3_A |
+		      MOD_SEL0_HSCIF1_A |
+		      MOD_SEL0_FSO_A |
+		      MOD_SEL0_HSCIF2_A |
+		      MOD_SEL0_ETHERAVB_A |
+		      MOD_SEL0_DRIF3_A |
+		      MOD_SEL0_DRIF2_A |
+		      MOD_SEL0_DRIF1_A |
+		      MOD_SEL0_DRIF0_A |
+		      MOD_SEL0_CANFD0_A |
+		      MOD_SEL0_ADG_A_A);
+
+	pfc_reg_write(PFC_MOD_SEL1,
+		      MOD_SEL1_TSIF1_A |
+		      MOD_SEL1_TSIF0_A |
+		      MOD_SEL1_TIMER_TMU_A |
+		      MOD_SEL1_SSP1_1_A |
+		      MOD_SEL1_SSP1_0_A |
+		      MOD_SEL1_SSI_A |
+		      MOD_SEL1_SPEED_PULSE_IF_A |
+		      MOD_SEL1_SIMCARD_A |
+		      MOD_SEL1_SDHI2_A |
+		      MOD_SEL1_SCIF4_A |
+		      MOD_SEL1_SCIF3_A |
+		      MOD_SEL1_SCIF2_A |
+		      MOD_SEL1_SCIF1_A |
+		      MOD_SEL1_SCIF_A |
+		      MOD_SEL1_REMOCON_A |
+		      MOD_SEL1_RCAN0_A |
+		      MOD_SEL1_PWM6_A |
+		      MOD_SEL1_PWM5_A |
+		      MOD_SEL1_PWM4_A |
+		      MOD_SEL1_PWM3_A |
+		      MOD_SEL1_PWM2_A |
+		      MOD_SEL1_PWM1_A);
+
+	pfc_reg_write(PFC_MOD_SEL2,
+		      MOD_SEL2_I2C_5_B |
+		      MOD_SEL2_I2C_3_B |
+		      MOD_SEL2_I2C_0_B |
+		      MOD_SEL2_FM_A |
+		      MOD_SEL2_SCIF5_A |
+		      MOD_SEL2_I2C6_A |
+		      MOD_SEL2_NDF_A |
+		      MOD_SEL2_SSI2_A |
+		      MOD_SEL2_SSI9_A |
+		      MOD_SEL2_TIMER_TMU2_A |
+		      MOD_SEL2_ADG_B_A |
+		      MOD_SEL2_ADG_C_A |
+		      MOD_SEL2_VIN4_A);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR1,
+		      IPSR_28_FUNC(6) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(3) |
+		      IPSR_8_FUNC(3) |
+		      IPSR_4_FUNC(3) |
+		      IPSR_0_FUNC(3));
+
+	pfc_reg_write(PFC_IPSR2,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(6) |
+		      IPSR_20_FUNC(6) |
+		      IPSR_16_FUNC(6) |
+		      IPSR_12_FUNC(6) |
+		      IPSR_8_FUNC(6) |
+		      IPSR_4_FUNC(6) |
+		      IPSR_0_FUNC(6));
+
+	pfc_reg_write(PFC_IPSR3,
+		      IPSR_28_FUNC(6) |
+		      IPSR_24_FUNC(6) |
+		      IPSR_20_FUNC(6) |
+		      IPSR_16_FUNC(6) |
+		      IPSR_12_FUNC(6) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR4,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(6) |
+		      IPSR_4_FUNC(6) |
+		      IPSR_0_FUNC(6));
+
+	pfc_reg_write(PFC_IPSR5,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(6) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR6,
+		      IPSR_28_FUNC(6) |
+		      IPSR_24_FUNC(6) |
+		      IPSR_20_FUNC(6) |
+		      IPSR_16_FUNC(6) |
+		      IPSR_12_FUNC(6) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR7,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(6) |
+		      IPSR_4_FUNC(6) |
+		      IPSR_0_FUNC(6));
+
+	pfc_reg_write(PFC_IPSR8,
+		      IPSR_28_FUNC(1) |
+		      IPSR_24_FUNC(1) |
+		      IPSR_20_FUNC(1) |
+		      IPSR_16_FUNC(1) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR9,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR10,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR11,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(4) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR12,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(4) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR13,
+		      IPSR_28_FUNC(8) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(3) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR14,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(3) |
+		      IPSR_0_FUNC(8));
+
+	pfc_reg_write(PFC_IPSR15,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR16,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR17,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(1) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0) | IPSR_0_FUNC(0));
+
+	/* initialize GPIO/peripheral function select */
+	pfc_reg_write(PFC_GPSR0,
+		      GPSR0_D15 |
+		      GPSR0_D14 |
+		      GPSR0_D13 |
+		      GPSR0_D12 |
+		      GPSR0_D11 |
+		      GPSR0_D10 |
+		      GPSR0_D9 |
+		      GPSR0_D8 |
+		      GPSR0_D7 |
+		      GPSR0_D6 |
+		      GPSR0_D5 |
+		      GPSR0_D4 |
+		      GPSR0_D3 |
+		      GPSR0_D2 |
+		      GPSR0_D0);
+
+	pfc_reg_write(PFC_GPSR1,
+		      GPSR1_CLKOUT |
+		      GPSR1_EX_WAIT0_A |
+		      GPSR1_WE1 |
+		      GPSR1_RD |
+		      GPSR1_RD_WR |
+		      GPSR1_CS0 |
+		      GPSR1_A19 |
+		      GPSR1_A18 |
+		      GPSR1_A17 |
+		      GPSR1_A16 |
+		      GPSR1_A15 |
+		      GPSR1_A14 |
+		      GPSR1_A13 |
+		      GPSR1_A12 |
+		      GPSR1_A7 |
+		      GPSR1_A6 |
+		      GPSR1_A5 |
+		      GPSR1_A4 |
+		      GPSR1_A3 |
+		      GPSR1_A2 |
+		      GPSR1_A1 |
+		      GPSR1_A0);
+
+	pfc_reg_write(PFC_GPSR2,
+		      GPSR2_AVB_AVTP_CAPTURE_A |
+		      GPSR2_AVB_AVTP_MATCH_A |
+		      GPSR2_AVB_LINK |
+		      GPSR2_AVB_PHY_INT |
+		      GPSR2_AVB_MDC |
+		      GPSR2_PWM2_A |
+		      GPSR2_PWM1_A |
+		      GPSR2_IRQ4 |
+		      GPSR2_IRQ3 |
+		      GPSR2_IRQ2 |
+		      GPSR2_IRQ1 |
+		      GPSR2_IRQ0);
+
+	pfc_reg_write(PFC_GPSR3,
+		      GPSR3_SD0_CD |
+		      GPSR3_SD1_DAT3 |
+		      GPSR3_SD1_DAT2 |
+		      GPSR3_SD1_DAT1 |
+		      GPSR3_SD1_DAT0 |
+		      GPSR3_SD0_DAT3 |
+		      GPSR3_SD0_DAT2 |
+		      GPSR3_SD0_DAT1 |
+		      GPSR3_SD0_DAT0 |
+		      GPSR3_SD0_CMD |
+		      GPSR3_SD0_CLK);
+
+	pfc_reg_write(PFC_GPSR4,
+		      GPSR4_SD3_DS |
+		      GPSR4_SD3_DAT7 |
+		      GPSR4_SD3_DAT6 |
+		      GPSR4_SD3_DAT5 |
+		      GPSR4_SD3_DAT4 |
+		      GPSR4_SD3_DAT3 |
+		      GPSR4_SD3_DAT2 |
+		      GPSR4_SD3_DAT1 |
+		      GPSR4_SD3_DAT0 |
+		      GPSR4_SD3_CMD |
+		      GPSR4_SD3_CLK |
+		      GPSR4_SD2_DAT3 |
+		      GPSR4_SD2_DAT2 |
+		      GPSR4_SD2_DAT1 |
+		      GPSR4_SD2_DAT0 |
+		      GPSR4_SD2_CMD |
+		      GPSR4_SD2_CLK);
+
+	pfc_reg_write(PFC_GPSR5,
+		      GPSR5_MSIOF0_RXD |
+		      GPSR5_MSIOF0_TXD |
+		      GPSR5_MSIOF0_SYNC |
+		      GPSR5_MSIOF0_SCK |
+		      GPSR5_RX2_A |
+		      GPSR5_TX2_A |
+		      GPSR5_RTS1 |
+		      GPSR5_CTS1 |
+		      GPSR5_TX1_A |
+		      GPSR5_RX1_A |
+		      GPSR5_RTS0 |
+		      GPSR5_SCK0);
+
+	pfc_reg_write(PFC_GPSR6,
+		      GPSR6_AUDIO_CLKB_B |
+		      GPSR6_AUDIO_CLKA_A |
+		      GPSR6_SSI_WS6 |
+		      GPSR6_SSI_SCK6 |
+		      GPSR6_SSI_SDATA4 |
+		      GPSR6_SSI_WS4 |
+		      GPSR6_SSI_SCK4 |
+		      GPSR6_SSI_SDATA1_A |
+		      GPSR6_SSI_SDATA0 |
+		      GPSR6_SSI_WS0129 |
+		      GPSR6_SSI_SCK0129);
+
+	pfc_reg_write(PFC_GPSR7, GPSR7_AVS2 | GPSR7_AVS1);
+
+	/* initialize POC control register */
+	pfc_reg_write(PFC_POCCTRL0,
+		      POC_SD0_DAT3_33V |
+		      POC_SD0_DAT2_33V |
+		      POC_SD0_DAT1_33V |
+		      POC_SD0_DAT0_33V |
+		      POC_SD0_CMD_33V |
+		      POC_SD0_CLK_33V);
+
+	/* initialize DRV control register */
+	reg = mmio_read_32(PFC_DRVCTRL0);
+	reg = (reg & DRVCTRL0_MASK) |
+	      DRVCTRL0_QSPI0_SPCLK(3) |
+	      DRVCTRL0_QSPI0_MOSI_IO0(3) |
+	      DRVCTRL0_QSPI0_MISO_IO1(3) |
+	      DRVCTRL0_QSPI0_IO2(3) |
+	      DRVCTRL0_QSPI0_IO3(3) |
+	      DRVCTRL0_QSPI0_SSL(3) |
+	      DRVCTRL0_QSPI1_SPCLK(3) |
+	      DRVCTRL0_QSPI1_MOSI_IO0(3);
+	pfc_reg_write(PFC_DRVCTRL0, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL1);
+	reg = (reg & DRVCTRL1_MASK) |
+	      DRVCTRL1_QSPI1_MISO_IO1(3) |
+	      DRVCTRL1_QSPI1_IO2(3) |
+	      DRVCTRL1_QSPI1_IO3(3) |
+	      DRVCTRL1_QSPI1_SS(3) |
+	      DRVCTRL1_RPC_INT(3) |
+	      DRVCTRL1_RPC_WP(3) |
+	      DRVCTRL1_RPC_RESET(3) |
+	      DRVCTRL1_AVB_RX_CTL(7);
+	pfc_reg_write(PFC_DRVCTRL1, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL2);
+	reg = (reg & DRVCTRL2_MASK) |
+	      DRVCTRL2_AVB_RXC(7) |
+	      DRVCTRL2_AVB_RD0(7) |
+	      DRVCTRL2_AVB_RD1(7) |
+	      DRVCTRL2_AVB_RD2(7) |
+	      DRVCTRL2_AVB_RD3(7) |
+	      DRVCTRL2_AVB_TX_CTL(3) |
+	      DRVCTRL2_AVB_TXC(3) |
+	      DRVCTRL2_AVB_TD0(3);
+	pfc_reg_write(PFC_DRVCTRL2, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL3);
+	reg = (reg & DRVCTRL3_MASK) |
+	      DRVCTRL3_AVB_TD1(3) |
+	      DRVCTRL3_AVB_TD2(3) |
+	      DRVCTRL3_AVB_TD3(3) |
+	      DRVCTRL3_AVB_TXCREFCLK(7) |
+	      DRVCTRL3_AVB_MDIO(7) |
+	      DRVCTRL3_AVB_MDC(7) |
+	      DRVCTRL3_AVB_MAGIC(7) |
+	      DRVCTRL3_AVB_PHY_INT(7);
+	pfc_reg_write(PFC_DRVCTRL3, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL4);
+	reg = (reg & DRVCTRL4_MASK) |
+	      DRVCTRL4_AVB_LINK(7) |
+	      DRVCTRL4_AVB_AVTP_MATCH(7) |
+	      DRVCTRL4_AVB_AVTP_CAPTURE(7) |
+	      DRVCTRL4_IRQ0(7) |
+	      DRVCTRL4_IRQ1(7) |
+	      DRVCTRL4_IRQ2(7) |
+	      DRVCTRL4_IRQ3(7) |
+	      DRVCTRL4_IRQ4(7);
+	pfc_reg_write(PFC_DRVCTRL4, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL5);
+	reg = (reg & DRVCTRL5_MASK) |
+	      DRVCTRL5_IRQ5(7) |
+	      DRVCTRL5_PWM0(7) |
+	      DRVCTRL5_PWM1(7) |
+	      DRVCTRL5_PWM2(7) |
+	      DRVCTRL5_A0(3) |
+	      DRVCTRL5_A1(3) |
+	      DRVCTRL5_A2(3) |
+	      DRVCTRL5_A3(3);
+	pfc_reg_write(PFC_DRVCTRL5, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL6);
+	reg = (reg & DRVCTRL6_MASK) |
+	      DRVCTRL6_A4(3) |
+	      DRVCTRL6_A5(3) |
+	      DRVCTRL6_A6(3) |
+	      DRVCTRL6_A7(3) |
+	      DRVCTRL6_A8(7) |
+	      DRVCTRL6_A9(7) |
+	      DRVCTRL6_A10(7) |
+	      DRVCTRL6_A11(7);
+	pfc_reg_write(PFC_DRVCTRL6, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL7);
+	reg = (reg & DRVCTRL7_MASK) |
+	      DRVCTRL7_A12(3) |
+	      DRVCTRL7_A13(3) |
+	      DRVCTRL7_A14(3) |
+	      DRVCTRL7_A15(3) |
+	      DRVCTRL7_A16(3) |
+	      DRVCTRL7_A17(3) |
+	      DRVCTRL7_A18(3) |
+	      DRVCTRL7_A19(3);
+	pfc_reg_write(PFC_DRVCTRL7, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL8);
+	reg = (reg & DRVCTRL8_MASK) |
+	      DRVCTRL8_CLKOUT(7) |
+	      DRVCTRL8_CS0(7) |
+	      DRVCTRL8_CS1_A2(7) |
+	      DRVCTRL8_BS(7) |
+	      DRVCTRL8_RD(7) |
+	      DRVCTRL8_RD_W(7) |
+	      DRVCTRL8_WE0(7) |
+	      DRVCTRL8_WE1(7);
+	pfc_reg_write(PFC_DRVCTRL8, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL9);
+	reg = (reg & DRVCTRL9_MASK) |
+	      DRVCTRL9_EX_WAIT0(7) |
+	      DRVCTRL9_PRESETOU(7) |
+	      DRVCTRL9_D0(7) |
+	      DRVCTRL9_D1(7) |
+	      DRVCTRL9_D2(7) |
+	      DRVCTRL9_D3(7) |
+	      DRVCTRL9_D4(7) |
+	      DRVCTRL9_D5(7);
+	pfc_reg_write(PFC_DRVCTRL9, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL10);
+	reg = (reg & DRVCTRL10_MASK) |
+	      DRVCTRL10_D6(7) |
+	      DRVCTRL10_D7(7) |
+	      DRVCTRL10_D8(3) |
+	      DRVCTRL10_D9(3) |
+	      DRVCTRL10_D10(3) |
+	      DRVCTRL10_D11(3) |
+	      DRVCTRL10_D12(3) |
+	      DRVCTRL10_D13(3);
+	pfc_reg_write(PFC_DRVCTRL10, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL11);
+	reg = (reg & DRVCTRL11_MASK) |
+	      DRVCTRL11_D14(3) |
+	      DRVCTRL11_D15(3) |
+	      DRVCTRL11_AVS1(7) |
+	      DRVCTRL11_AVS2(7) |
+	      DRVCTRL11_GP7_02(7) |
+	      DRVCTRL11_GP7_03(7) |
+	      DRVCTRL11_DU_DOTCLKIN0(3) |
+	      DRVCTRL11_DU_DOTCLKIN1(3);
+	pfc_reg_write(PFC_DRVCTRL11, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL12);
+	reg = (reg & DRVCTRL12_MASK) |
+	      DRVCTRL12_DU_DOTCLKIN2(3) |
+	      DRVCTRL12_DU_DOTCLKIN3(3) |
+	      DRVCTRL12_DU_FSCLKST(3) |
+	      DRVCTRL12_DU_TMS(3);
+	pfc_reg_write(PFC_DRVCTRL12, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL13);
+	reg = (reg & DRVCTRL13_MASK) |
+	      DRVCTRL13_TDO(3) |
+	      DRVCTRL13_ASEBRK(3) |
+	      DRVCTRL13_SD0_CLK(7) |
+	      DRVCTRL13_SD0_CMD(7) |
+	      DRVCTRL13_SD0_DAT0(7) |
+	      DRVCTRL13_SD0_DAT1(7) |
+	      DRVCTRL13_SD0_DAT2(7) |
+	      DRVCTRL13_SD0_DAT3(7);
+	pfc_reg_write(PFC_DRVCTRL13, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL14);
+	reg = (reg & DRVCTRL14_MASK) |
+	      DRVCTRL14_SD1_CLK(7) |
+	      DRVCTRL14_SD1_CMD(7) |
+	      DRVCTRL14_SD1_DAT0(5) |
+	      DRVCTRL14_SD1_DAT1(5) |
+	      DRVCTRL14_SD1_DAT2(5) |
+	      DRVCTRL14_SD1_DAT3(5) |
+	      DRVCTRL14_SD2_CLK(5) |
+	      DRVCTRL14_SD2_CMD(5);
+	pfc_reg_write(PFC_DRVCTRL14, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL15);
+	reg = (reg & DRVCTRL15_MASK) |
+	      DRVCTRL15_SD2_DAT0(5) |
+	      DRVCTRL15_SD2_DAT1(5) |
+	      DRVCTRL15_SD2_DAT2(5) |
+	      DRVCTRL15_SD2_DAT3(5) |
+	      DRVCTRL15_SD2_DS(5) |
+	      DRVCTRL15_SD3_CLK(7) |
+	      DRVCTRL15_SD3_CMD(7) |
+	      DRVCTRL15_SD3_DAT0(7);
+	pfc_reg_write(PFC_DRVCTRL15, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL16);
+	reg = (reg & DRVCTRL16_MASK) |
+	      DRVCTRL16_SD3_DAT1(7) |
+	      DRVCTRL16_SD3_DAT2(7) |
+	      DRVCTRL16_SD3_DAT3(7) |
+	      DRVCTRL16_SD3_DAT4(7) |
+	      DRVCTRL16_SD3_DAT5(7) |
+	      DRVCTRL16_SD3_DAT6(7) |
+	      DRVCTRL16_SD3_DAT7(7) |
+	      DRVCTRL16_SD3_DS(7);
+	pfc_reg_write(PFC_DRVCTRL16, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL17);
+	reg = (reg & DRVCTRL17_MASK) |
+	      DRVCTRL17_SD0_CD(7) |
+	      DRVCTRL17_SD0_WP(7) |
+	      DRVCTRL17_SD1_CD(7) |
+	      DRVCTRL17_SD1_WP(7) |
+	      DRVCTRL17_SCK0(7) |
+	      DRVCTRL17_RX0(7) |
+	      DRVCTRL17_TX0(7) |
+	      DRVCTRL17_CTS0(7);
+	pfc_reg_write(PFC_DRVCTRL17, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL18);
+	reg = (reg & DRVCTRL18_MASK) |
+	      DRVCTRL18_RTS0_TANS(7) |
+	      DRVCTRL18_RX1(7) |
+	      DRVCTRL18_TX1(7) |
+	      DRVCTRL18_CTS1(7) |
+	      DRVCTRL18_RTS1_TANS(7) |
+	      DRVCTRL18_SCK2(7) |
+	      DRVCTRL18_TX2(7) |
+	      DRVCTRL18_RX2(7);
+	pfc_reg_write(PFC_DRVCTRL18, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL19);
+	reg = (reg & DRVCTRL19_MASK) |
+	      DRVCTRL19_HSCK0(7) |
+	      DRVCTRL19_HRX0(7) |
+	      DRVCTRL19_HTX0(7) |
+	      DRVCTRL19_HCTS0(7) |
+	      DRVCTRL19_HRTS0(7) |
+	      DRVCTRL19_MSIOF0_SCK(7) |
+	      DRVCTRL19_MSIOF0_SYNC(7) |
+	      DRVCTRL19_MSIOF0_SS1(7);
+	pfc_reg_write(PFC_DRVCTRL19, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL20);
+	reg = (reg & DRVCTRL20_MASK) |
+	      DRVCTRL20_MSIOF0_TXD(7) |
+	      DRVCTRL20_MSIOF0_SS2(7) |
+	      DRVCTRL20_MSIOF0_RXD(7) |
+	      DRVCTRL20_MLB_CLK(7) |
+	      DRVCTRL20_MLB_SIG(7) |
+	      DRVCTRL20_MLB_DAT(7) |
+	      DRVCTRL20_MLB_REF(7) |
+	      DRVCTRL20_SSI_SCK0129(7);
+	pfc_reg_write(PFC_DRVCTRL20, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL21);
+	reg = (reg & DRVCTRL21_MASK) |
+	      DRVCTRL21_SSI_WS0129(7) |
+	      DRVCTRL21_SSI_SDATA0(7) |
+	      DRVCTRL21_SSI_SDATA1(7) |
+	      DRVCTRL21_SSI_SDATA2(7) |
+	      DRVCTRL21_SSI_SCK34(7) |
+	      DRVCTRL21_SSI_WS34(7) |
+	      DRVCTRL21_SSI_SDATA3(7) |
+	      DRVCTRL21_SSI_SCK4(7);
+	pfc_reg_write(PFC_DRVCTRL21, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL22);
+	reg = (reg & DRVCTRL22_MASK) |
+	      DRVCTRL22_SSI_WS4(7) |
+	      DRVCTRL22_SSI_SDATA4(7) |
+	      DRVCTRL22_SSI_SCK5(7) |
+	      DRVCTRL22_SSI_WS5(7) |
+	      DRVCTRL22_SSI_SDATA5(7) |
+	      DRVCTRL22_SSI_SCK6(7) |
+	      DRVCTRL22_SSI_WS6(7) |
+	      DRVCTRL22_SSI_SDATA6(7);
+	pfc_reg_write(PFC_DRVCTRL22, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL23);
+	reg = (reg & DRVCTRL23_MASK) |
+	      DRVCTRL23_SSI_SCK78(7) |
+	      DRVCTRL23_SSI_WS78(7) |
+	      DRVCTRL23_SSI_SDATA7(7) |
+	      DRVCTRL23_SSI_SDATA8(7) |
+	      DRVCTRL23_SSI_SDATA9(7) |
+	      DRVCTRL23_AUDIO_CLKA(7) |
+	      DRVCTRL23_AUDIO_CLKB(7) |
+	      DRVCTRL23_USB0_PWEN(7);
+
+	pfc_reg_write(PFC_DRVCTRL23, reg);
+	reg = mmio_read_32(PFC_DRVCTRL24);
+	reg = (reg & DRVCTRL24_MASK) |
+	      DRVCTRL24_USB0_OVC(7) |
+	      DRVCTRL24_USB1_PWEN(7) |
+	      DRVCTRL24_USB1_OVC(7) |
+	      DRVCTRL24_USB30_PWEN(7) |
+	      DRVCTRL24_USB30_OVC(7) |
+	      DRVCTRL24_USB31_PWEN(7) |
+	      DRVCTRL24_USB31_OVC(7);
+	pfc_reg_write(PFC_DRVCTRL24, reg);
+
+	/* initialize LSI pin pull-up/down control */
+	pfc_reg_write(PFC_PUD0, 0x00005FBFU);
+	pfc_reg_write(PFC_PUD1, 0x00300EFEU);
+	pfc_reg_write(PFC_PUD2, 0x330001E6U);
+	pfc_reg_write(PFC_PUD3, 0x000002E0U);
+	pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
+	pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
+	pfc_reg_write(PFC_PUD6, 0x00000055U);
+
+	/* initialize LSI pin pull-enable register */
+	pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
+	pfc_reg_write(PFC_PUEN1, 0x00100234U);
+	pfc_reg_write(PFC_PUEN2, 0x000004C4U);
+	pfc_reg_write(PFC_PUEN3, 0x00000200U);
+	pfc_reg_write(PFC_PUEN4, 0x3E000000U);
+	pfc_reg_write(PFC_PUEN5, 0x1F000805U);
+	pfc_reg_write(PFC_PUEN6, 0x00000006U);
+
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG7, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT0, 0x00000001U);
+	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+	mmio_write_32(GPIO_OUTDT3, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT4, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT6, 0x00003800U);
+	mmio_write_32(GPIO_OUTDT7, 0x00000003U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00000001U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x00100B00U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x00000418U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x00002000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00000040U);
+	mmio_write_32(GPIO_INOUTSEL5, 0x00000208U);
+	mmio_write_32(GPIO_INOUTSEL6, 0x00013F00U);
+	mmio_write_32(GPIO_INOUTSEL7, 0x00000003U);
+}
diff --git a/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.h b/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.h
new file mode 100644
index 0000000..f0616b6
--- /dev/null
+++ b/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_G2N_H
+#define PFC_INIT_G2N_H
+
+void pfc_init_g2n(void);
+
+#endif /* PFC_INIT_G2N_H */
diff --git a/drivers/renesas/rzg/pfc/pfc.mk b/drivers/renesas/rzg/pfc/pfc.mk
index 5cae658..15d0e8d 100644
--- a/drivers/renesas/rzg/pfc/pfc.mk
+++ b/drivers/renesas/rzg/pfc/pfc.mk
@@ -1,20 +1,41 @@
 #
-# Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
 ifeq (${RCAR_LSI},${RCAR_AUTO})
     BL2_SOURCES += drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c
 
 else ifdef RCAR_LSI_CUT_COMPAT
   ifeq (${RCAR_LSI},${RZ_G2M})
     BL2_SOURCES += drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c
   endif
+  ifeq (${RCAR_LSI},${RZ_G2H})
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c
+  endif
+  ifeq (${RCAR_LSI},${RZ_G2N})
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c
+  endif
+  ifeq (${RCAR_LSI},${RZ_G2E})
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c
+  endif
 else
   ifeq (${RCAR_LSI},${RZ_G2M})
     BL2_SOURCES += drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c
   endif
+  ifeq (${RCAR_LSI},${RZ_G2H})
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c
+  endif
+  ifeq (${RCAR_LSI},${RZ_G2N})
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c
+  endif
+  ifeq (${RCAR_LSI},${RZ_G2E})
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c
+  endif
 endif
 
 BL2_SOURCES += drivers/renesas/rzg/pfc/pfc_init.c
diff --git a/drivers/renesas/rzg/pfc/pfc_init.c b/drivers/renesas/rzg/pfc/pfc_init.c
index f51992d..762450c 100644
--- a/drivers/renesas/rzg/pfc/pfc_init.c
+++ b/drivers/renesas/rzg/pfc/pfc_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,11 +9,23 @@
 #include <lib/mmio.h>
 
 #if RCAR_LSI == RCAR_AUTO
+#include "G2E/pfc_init_g2e.h"
+#include "G2H/pfc_init_g2h.h"
 #include "G2M/pfc_init_g2m.h"
+#include "G2N/pfc_init_g2n.h"
 #endif /* RCAR_LSI == RCAR_AUTO */
+#if (RCAR_LSI == RZ_G2E)
+#include "G2E/pfc_init_g2e.h"
+#endif /* RCAR_LSI == RZ_G2N */
+#if (RCAR_LSI == RZ_G2H)
+#include "G2H/pfc_init_g2h.h"
+#endif /* RCAR_LSI == RZ_G2H */
 #if (RCAR_LSI == RZ_G2M)
 #include "G2M/pfc_init_g2m.h"
 #endif /* RCAR_LSI == RZ_G2M */
+#if (RCAR_LSI == RZ_G2N)
+#include "G2N/pfc_init_g2n.h"
+#endif /* RCAR_LSI == RZ_G2N */
 #include "rcar_def.h"
 
 #define PRR_PRODUCT_ERR(reg)				\
@@ -40,6 +52,15 @@
 	case PRR_PRODUCT_M3:
 		pfc_init_g2m();
 		break;
+	case PRR_PRODUCT_H3:
+		pfc_init_g2h();
+		break;
+	case PRR_PRODUCT_M3N:
+		pfc_init_g2n();
+		break;
+	case PRR_PRODUCT_E3:
+		pfc_init_g2e();
+		break;
 	default:
 		PRR_PRODUCT_ERR(reg);
 		break;
@@ -54,6 +75,27 @@
 		pfc_init_g2m();
 #endif /* RCAR_LSI != RZ_G2M */
 		break;
+	case PRR_PRODUCT_H3:
+#if (RCAR_LSI != RZ_G2H)
+		PRR_PRODUCT_ERR(reg);
+#else /* RCAR_LSI != RZ_G2H */
+		pfc_init_g2h();
+#endif /* RCAR_LSI != RZ_G2H */
+		break;
+	case PRR_PRODUCT_M3N:
+#if RCAR_LSI != RZ_G2N
+		PRR_PRODUCT_ERR(reg);
+#else
+		pfc_init_g2n();
+#endif /* RCAR_LSI != RZ_G2N */
+		break;
+	case PRR_PRODUCT_E3:
+#if RCAR_LSI != RZ_G2E
+		PRR_PRODUCT_ERR(reg);
+#else
+		pfc_init_g2e();
+#endif
+		break;
 	default:
 		PRR_PRODUCT_ERR(reg);
 		break;
@@ -65,6 +107,21 @@
 		PRR_PRODUCT_ERR(reg);
 	}
 	pfc_init_m3();
+#elif (RCAR_LSI == RZ_G2H)
+	if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_H3) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	pfc_init_g2h();
+#elif (RCAR_LSI == RZ_G2N)	/* G2N */
+	if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_M3N) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	pfc_init_g2n();
+#elif (RCAR_LSI == RZ_G2E)
+	if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_E3) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	pfc_init_g2e();
 #else /* RCAR_LSI == RZ_G2M */
 #error "Don't have PFC initialize routine(unknown)."
 #endif /* RCAR_LSI == RZ_G2M */
diff --git a/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c
new file mode 100644
index 0000000..14ccc21
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "qos_init_g2e_v10.h"
+#include "../qos_common.h"
+#include "../qos_reg.h"
+
+#define RCAR_QOS_VERSION	"rev.0.05"
+
+#define REF_ARS_ARBSTOPCYCLE_G2E	(((SL_INIT_SSLOTCLK_G2E) - 5U) << 16U)
+
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_g2e_v10_mstat390.h"
+#else
+#include "qos_init_g2e_v10_mstat780.h"
+#endif /* RCAR_REF_INT == RCAR_REF_DEFAULT */
+#endif /* RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT */
+
+static const struct rcar_gen3_dbsc_qos_settings g2e_qos[] = {
+	/* BUFCAM settings */
+	{ DBSC_DBCAM0CNF1, 0x00043218U },
+	{ DBSC_DBCAM0CNF2, 0x000000F4U },
+	{ DBSC_DBSCHCNT0, 0x000F0037U },
+	{ DBSC_DBSCHSZ0, 0x00000001U },
+	{ DBSC_DBSCHRW0, 0x22421111U },
+
+	/* DDR3 */
+	{ DBSC_SCFCTST2, 0x012F1123U },
+
+	/* QoS Settings */
+	{ DBSC_DBSCHQOS00, 0x00000F00U },
+	{ DBSC_DBSCHQOS01, 0x00000B00U },
+	{ DBSC_DBSCHQOS02, 0x00000000U },
+	{ DBSC_DBSCHQOS03, 0x00000000U },
+	{ DBSC_DBSCHQOS40, 0x00000300U },
+	{ DBSC_DBSCHQOS41, 0x000002F0U },
+	{ DBSC_DBSCHQOS42, 0x00000200U },
+	{ DBSC_DBSCHQOS43, 0x00000100U },
+	{ DBSC_DBSCHQOS90, 0x00000100U },
+	{ DBSC_DBSCHQOS91, 0x000000F0U },
+	{ DBSC_DBSCHQOS92, 0x000000A0U },
+	{ DBSC_DBSCHQOS93, 0x00000040U },
+	{ DBSC_DBSCHQOS130, 0x00000100U },
+	{ DBSC_DBSCHQOS131, 0x000000F0U },
+	{ DBSC_DBSCHQOS132, 0x000000A0U },
+	{ DBSC_DBSCHQOS133, 0x00000040U },
+	{ DBSC_DBSCHQOS140, 0x000000C0U },
+	{ DBSC_DBSCHQOS141, 0x000000B0U },
+	{ DBSC_DBSCHQOS142, 0x00000080U },
+	{ DBSC_DBSCHQOS143, 0x00000040U },
+	{ DBSC_DBSCHQOS150, 0x00000040U },
+	{ DBSC_DBSCHQOS151, 0x00000030U },
+	{ DBSC_DBSCHQOS152, 0x00000020U },
+	{ DBSC_DBSCHQOS153, 0x00000010U },
+};
+
+void qos_init_g2e_v10(void)
+{
+	rzg_qos_dbsc_setting(g2e_qos, ARRAY_SIZE(g2e_qos), true);
+
+	/* DRAM Split Address mapping */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
+#if RCAR_LSI == RCAR_RZ_G2E
+#error "Don't set DRAM Split 4ch(G2E)"
+#else
+	ERROR("DRAM Split 4ch not supported.(G2E)");
+	panic();
+#endif
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
+#if RCAR_LSI == RCAR_RZ_G2E
+#error "Don't set DRAM Split 2ch(G2E)"
+#else
+	ERROR("DRAM Split 2ch not supported.(G2E)");
+	panic();
+#endif
+#else
+	NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+	NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+	NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#else
+	NOTICE("BL2: DRAM refresh interval 7.8 usec\n");
+#endif
+
+	mmio_write_32(QOSCTRL_RAS, 0x00000020U);
+	mmio_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
+	mmio_write_32(QOSCTRL_DANT, 0x00100804U);
+	mmio_write_32(QOSCTRL_FSS, 0x0000000AU);
+	mmio_write_32(QOSCTRL_INSFC, 0x06330001U);
+	mmio_write_32(QOSCTRL_EARLYR, 0x00000000U);
+	mmio_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+	mmio_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT |
+		      SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_G2E);
+	mmio_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_G2E);
+
+	/* QOSBW SRAM setting */
+	uint32_t i;
+
+	for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+		mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]);
+		mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]);
+	}
+	for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+		mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]);
+		mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]);
+	}
+
+	/* RT bus Leaf setting */
+	mmio_write_32(RT_ACT0, 0x00000000U);
+	mmio_write_32(RT_ACT1, 0x00000000U);
+
+	/* CCI bus Leaf setting */
+	mmio_write_32(CPU_ACT0, 0x00000003U);
+	mmio_write_32(CPU_ACT1, 0x00000003U);
+
+	mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+	mmio_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+	NOTICE("BL2: QoS is None\n");
+
+	mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif
+}
diff --git a/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.h b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.h
new file mode 100644
index 0000000..d27de1b
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2E_V10_H
+#define QOS_INIT_G2E_V10_H
+
+void qos_init_g2e_v10(void);
+
+#endif /* QOS_INIT_G2E_V10_H */
diff --git a/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat390.h b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat390.h
new file mode 100644
index 0000000..63b08c4
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat390.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2E_V10_MSTAT390_H
+#define QOS_INIT_G2E_V10_MSTAT390_H
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008620000FFFFUL,
+	/* 0x0038, */ 0x001008620000FFFFUL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x001415260000FFFFUL,
+	/* 0x0060, */ 0x001415260000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001414930000FFFFUL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C08380000FFFFUL,
+	/* 0x00a8, */ 0x000C04110000FFFFUL,
+	/* 0x00b0, */ 0x000C04150000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C08380000FFFFUL,
+	/* 0x00c8, */ 0x000C04110000FFFFUL,
+	/* 0x00d0, */ 0x000C04150000FFFFUL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x000C084F0000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x000C21E40000FFFFUL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x001008530000FFFFUL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x00100C960000FFFFUL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x001008530000FFFFUL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0010042A0000FFFFUL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x00101D8D0000FFFFUL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x001008530000FFFFUL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x001410040000FFFFUL,
+	/* 0x0270, */ 0x001404020000FFFFUL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410040000FFFFUL,
+	/* 0x0298, */ 0x001404020000FFFFUL,
+	/* 0x02a0, */ 0x000C04090000FFFFUL,
+	/* 0x02a8, */ 0x000C04090000FFFFUL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04090000FFFFUL,
+	/* 0x02d8, */ 0x000C04090000FFFFUL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x000C04020000FFFFUL,
+	/* 0x0378, */ 0x000C04020000FFFFUL,
+	/* 0x0380, */ 0x000C04090000FFFFUL,
+	/* 0x0388, */ 0x000C04090000FFFFUL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0012001005F03401UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0021060005FFFC01UL,
+	/* 0x01c8, */ 0x0021060005FFFC01UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0011010005F79801UL,
+	/* 0x0220, */ 0x0011010005F79801UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0011010005F79801UL,
+	/* 0x0238, */ 0x0011010005F79801UL,
+	/* 0x0240, */ 0x0012010005F79801UL,
+	/* 0x0248, */ 0x0011010005F79801UL,
+	/* 0x0250, */ 0x0012010005F79801UL,
+	/* 0x0258, */ 0x0011010005F79801UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0011060005FFFC01UL,
+	/* 0x02f8, */ 0x0011060005FFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0012001005F03401UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0012060005FFFC01UL,
+	/* 0x0360, */ 0x0012060005FFFC01UL,
+	/* 0x0368, */ 0x0012001005F03401UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0012001005F03401UL,
+};
+#endif /* QOS_INIT_G2E_V10_MSTAT390_H */
diff --git a/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat780.h b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat780.h
new file mode 100644
index 0000000..3b888ea
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat780.h
@@ -0,0 +1,246 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2E_V10_MSTAT780_H
+#define QOS_INIT_G2E_V10_MSTAT780_H
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001010C40000FFFFUL,
+	/* 0x0038, */ 0x001010C40000FFFFUL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x00142A4B0000FFFFUL,
+	/* 0x0060, */ 0x00142A4B0000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001429260000FFFFUL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C10700000FFFFUL,
+	/* 0x00a8, */ 0x000C08210000FFFFUL,
+	/* 0x00b0, */ 0x000C082A0000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C10700000FFFFUL,
+	/* 0x00c8, */ 0x000C08210000FFFFUL,
+	/* 0x00d0, */ 0x000C082A0000FFFFUL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x00102CAF0000FFFFUL,
+	/* 0x00f8, */ 0x000C0C9D0000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x00100CAF0000FFFFUL,
+	/* 0x0118, */ 0x000C43C80000FFFFUL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x00100CA50000FFFFUL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0010152C0000FFFFUL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x00100CA50000FFFFUL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x001008530000FFFFUL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x001037190000FFFFUL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x00100CA50000FFFFUL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04040000FFFFUL,
+	/* 0x01f0, */ 0x000C08110000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04110000FFFFUL,
+	/* 0x0210, */ 0x000C08110000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C18530000FFFFUL,
+	/* 0x0268, */ 0x00141C070000FFFFUL,
+	/* 0x0270, */ 0x001404040000FFFFUL,
+	/* 0x0278, */ 0x000C0C210000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x00141C070000FFFFUL,
+	/* 0x0298, */ 0x001404040000FFFFUL,
+	/* 0x02a0, */ 0x000C04110000FFFFUL,
+	/* 0x02a8, */ 0x000C04110000FFFFUL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x000C04040000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04110000FFFFUL,
+	/* 0x02d8, */ 0x000C04110000FFFFUL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x000C04040000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x000C04040000FFFFUL,
+	/* 0x0378, */ 0x000C04040000FFFFUL,
+	/* 0x0380, */ 0x000C04110000FFFFUL,
+	/* 0x0388, */ 0x000C04110000FFFFUL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0012001002F03401UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0021060002FFFC01UL,
+	/* 0x01c8, */ 0x0021060002FFFC01UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0021010002F3CC01UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0021010002F3CC01UL,
+	/* 0x0218, */ 0x0011010002F3CC01UL,
+	/* 0x0220, */ 0x0011010002F3CC01UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0011010002F3CC01UL,
+	/* 0x0238, */ 0x0011010002F3CC01UL,
+	/* 0x0240, */ 0x0012010002F3CC01UL,
+	/* 0x0248, */ 0x0011010002F3CC01UL,
+	/* 0x0250, */ 0x0012010002F3CC01UL,
+	/* 0x0258, */ 0x0011010002F3CC01UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0011060002FFFC01UL,
+	/* 0x02f8, */ 0x0011060002FFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0012001002F03401UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0012060002FFFC01UL,
+	/* 0x0360, */ 0x0012060002FFFC01UL,
+	/* 0x0368, */ 0x0012001002F03401UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0012001002F03401UL,
+};
+
+#endif /* QOS_INIT_G2E_V10_MSTAT780_H */
diff --git a/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat195.h b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat195.h
new file mode 100644
index 0000000..7bb34aa
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat195.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2H_MSTAT195_H
+#define QOS_INIT_G2H_MSTAT195_H
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001004040000FFFFUL,
+	/* 0x0038, */ 0x001008070000FFFFUL,
+	/* 0x0040, */ 0x001410070000FFFFUL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x001404010000FFFFUL,
+	/* 0x0058, */ 0x0014100D0000FFFFUL,
+	/* 0x0060, */ 0x0014100D0000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x001404010000FFFFUL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001410070000FFFFUL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C04020000FFFFUL,
+	/* 0x00a8, */ 0x000C04010000FFFFUL,
+	/* 0x00b0, */ 0x000C04010000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C04020000FFFFUL,
+	/* 0x00c8, */ 0x000C04010000FFFFUL,
+	/* 0x00d0, */ 0x000C04010000FFFFUL,
+	/* 0x00d8, */ 0x001024090000FFFFUL,
+	/* 0x00e0, */ 0x00100C090000FFFFUL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x001024090000FFFFUL,
+	/* 0x00f8, */ 0x000C100D0000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x00100C090000FFFFUL,
+	/* 0x0118, */ 0x000C1C1B0000FFFFUL,
+	/* 0x0120, */ 0x000C1C1B0000FFFFUL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x00100C0B0000FFFFUL,
+	/* 0x0140, */ 0x00100C0B0000FFFFUL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0010100D0000FFFFUL,
+	/* 0x0158, */ 0x0010100D0000FFFFUL,
+	/* 0x0160, */ 0x00100C0B0000FFFFUL,
+	/* 0x0168, */ 0x00100C0B0000FFFFUL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x001008060000FFFFUL,
+	/* 0x0180, */ 0x001008060000FFFFUL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x00102C2C0000FFFFUL,
+	/* 0x0198, */ 0x00102C2C0000FFFFUL,
+	/* 0x01a0, */ 0x00100C0B0000FFFFUL,
+	/* 0x01a8, */ 0x00100C0B0000FFFFUL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x000C04010000FFFFUL,
+	/* 0x01d8, */ 0x000C04010000FFFFUL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04010000FFFFUL,
+	/* 0x01f0, */ 0x000C04010000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04010000FFFFUL,
+	/* 0x0210, */ 0x000C04010000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C08020000FFFFUL,
+	/* 0x0268, */ 0x001408010000FFFFUL,
+	/* 0x0270, */ 0x001404010000FFFFUL,
+	/* 0x0278, */ 0x000C04010000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001408010000FFFFUL,
+	/* 0x0298, */ 0x001404010000FFFFUL,
+	/* 0x02a0, */ 0x000C04010000FFFFUL,
+	/* 0x02a8, */ 0x000C04010000FFFFUL,
+	/* 0x02b0, */ 0x001408010000FFFFUL,
+	/* 0x02b8, */ 0x000C04010000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04010000FFFFUL,
+	/* 0x02d8, */ 0x000C04010000FFFFUL,
+	/* 0x02e0, */ 0x001408010000FFFFUL,
+	/* 0x02e8, */ 0x000C04010000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x001200600BDFFC01UL,
+	/* 0x0008, */ 0x001200600BDFFC01UL,
+	/* 0x0010, */ 0x001200600BDFFC01UL,
+	/* 0x0018, */ 0x001200600BDFFC01UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x001200100BD0FC01UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x002100600BDFFC01UL,
+	/* 0x01c8, */ 0x002100600BDFFC01UL,
+	/* 0x01d0, */ 0x002100600BDFFC01UL,
+	/* 0x01d8, */ 0x002100600BDFFC01UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x002100100BDF2401UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x002100100BDF2401UL,
+	/* 0x0218, */ 0x001100100BDF2401UL,
+	/* 0x0220, */ 0x001100100BDF2401UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x001100100BDF2401UL,
+	/* 0x0238, */ 0x001100100BDF2401UL,
+	/* 0x0240, */ 0x001200100BDF2401UL,
+	/* 0x0248, */ 0x001100100BDF2401UL,
+	/* 0x0250, */ 0x001200100BDF2401UL,
+	/* 0x0258, */ 0x001100100BDF2401UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x001100600BDFFC01UL,
+	/* 0x02f8, */ 0x001100600BDFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x001100600BDFFC01UL,
+	/* 0x0310, */ 0x001100600BDFFC01UL,
+	/* 0x0318, */ 0x001200100BD03401UL,
+	/* 0x0320, */ 0x001100600BDFFC01UL,
+	/* 0x0328, */ 0x001100600BDFFC01UL,
+	/* 0x0330, */ 0x001100600BDFFC01UL,
+	/* 0x0338, */ 0x001100600BDFFC01UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x001200100BD0FC01UL,
+};
+
+#endif /* QOS_INIT_G2H_MSTAT195_H */
diff --git a/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat390.h b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat390.h
new file mode 100644
index 0000000..9696a40
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat390.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2H_MSTAT390_H
+#define QOS_INIT_G2H_MSTAT390_H
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008070000FFFFUL,
+	/* 0x0038, */ 0x0010100D0000FFFFUL,
+	/* 0x0040, */ 0x00141C0E0000FFFFUL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x001408010000FFFFUL,
+	/* 0x0058, */ 0x00141C190000FFFFUL,
+	/* 0x0060, */ 0x00141C190000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x001408010000FFFFUL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x00141C0E0000FFFFUL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C08040000FFFFUL,
+	/* 0x00a8, */ 0x000C04020000FFFFUL,
+	/* 0x00b0, */ 0x000C04020000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C08040000FFFFUL,
+	/* 0x00c8, */ 0x000C04020000FFFFUL,
+	/* 0x00d0, */ 0x000C04020000FFFFUL,
+	/* 0x00d8, */ 0x001044110000FFFFUL,
+	/* 0x00e0, */ 0x001014110000FFFFUL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x001044110000FFFFUL,
+	/* 0x00f8, */ 0x000C1C1A0000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x001014110000FFFFUL,
+	/* 0x0118, */ 0x000C38360000FFFFUL,
+	/* 0x0120, */ 0x000C38360000FFFFUL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x001018150000FFFFUL,
+	/* 0x0140, */ 0x001018150000FFFFUL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x00101C190000FFFFUL,
+	/* 0x0158, */ 0x00101C190000FFFFUL,
+	/* 0x0160, */ 0x001018150000FFFFUL,
+	/* 0x0168, */ 0x001018150000FFFFUL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x00100C0B0000FFFFUL,
+	/* 0x0180, */ 0x00100C0B0000FFFFUL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x001058570000FFFFUL,
+	/* 0x0198, */ 0x001058570000FFFFUL,
+	/* 0x01a0, */ 0x001018150000FFFFUL,
+	/* 0x01a8, */ 0x001018150000FFFFUL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x000C04010000FFFFUL,
+	/* 0x01d8, */ 0x000C04010000FFFFUL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04010000FFFFUL,
+	/* 0x01f0, */ 0x000C04010000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04010000FFFFUL,
+	/* 0x0210, */ 0x000C04010000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C030000FFFFUL,
+	/* 0x0268, */ 0x001410010000FFFFUL,
+	/* 0x0270, */ 0x001404010000FFFFUL,
+	/* 0x0278, */ 0x000C08020000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410010000FFFFUL,
+	/* 0x0298, */ 0x001404010000FFFFUL,
+	/* 0x02a0, */ 0x000C04010000FFFFUL,
+	/* 0x02a8, */ 0x000C04010000FFFFUL,
+	/* 0x02b0, */ 0x00140C010000FFFFUL,
+	/* 0x02b8, */ 0x000C04010000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04010000FFFFUL,
+	/* 0x02d8, */ 0x000C04010000FFFFUL,
+	/* 0x02e0, */ 0x00140C010000FFFFUL,
+	/* 0x02e8, */ 0x000C04010000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x0012006005EFFC01UL,
+	/* 0x0008, */ 0x0012006005EFFC01UL,
+	/* 0x0010, */ 0x0012006005EFFC01UL,
+	/* 0x0018, */ 0x0012006005EFFC01UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0012001005E0FC01UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0021006005EFFC01UL,
+	/* 0x01c8, */ 0x0021006005EFFC01UL,
+	/* 0x01d0, */ 0x0021006005EFFC01UL,
+	/* 0x01d8, */ 0x0021006005EFFC01UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0021001005E79401UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0021001005E79401UL,
+	/* 0x0218, */ 0x0011001005E79401UL,
+	/* 0x0220, */ 0x0011001005E79401UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0011001005E79401UL,
+	/* 0x0238, */ 0x0011001005E79401UL,
+	/* 0x0240, */ 0x0012001005E79401UL,
+	/* 0x0248, */ 0x0011001005E79401UL,
+	/* 0x0250, */ 0x0012001005E79401UL,
+	/* 0x0258, */ 0x0011001005E79401UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0011006005EFFC01UL,
+	/* 0x02f8, */ 0x0011006005EFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0011006005EFFC01UL,
+	/* 0x0310, */ 0x0011006005EFFC01UL,
+	/* 0x0318, */ 0x0012001005E03401UL,
+	/* 0x0320, */ 0x0011006005EFFC01UL,
+	/* 0x0328, */ 0x0011006005EFFC01UL,
+	/* 0x0330, */ 0x0011006005EFFC01UL,
+	/* 0x0338, */ 0x0011006005EFFC01UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0012001005E0FC01UL,
+};
+
+#endif /* QOS_INIT_G2H_MSTAT390_H */
diff --git a/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt195.h b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt195.h
new file mode 100644
index 0000000..044f246
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt195.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2H_QOSWT195_H
+#define QOS_INIT_G2H_QOSWT195_H
+
+static uint64_t qoswt_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001004040000C010UL,
+	/* 0x0038, */ 0x001008070000C010UL,
+	/* 0x0040, */ 0x001410070000FFF0UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0014100D0000C010UL,
+	/* 0x0060, */ 0x0014100D0000C010UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001410070000FFF0UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C08020000FFF0UL,
+	/* 0x0268, */ 0x001408010000FFF0UL,
+	/* 0x0270, */ 0x001404010000FFF0UL,
+	/* 0x0278, */ 0x000C04010000FFF0UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001408010000FFF0UL,
+	/* 0x0298, */ 0x001404010000FFF0UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+#endif /* QOS_INIT_G2H_QOSWT195_H */
diff --git a/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt390.h b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt390.h
new file mode 100644
index 0000000..2ae07ab
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt390.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2H_QOSWT390_H
+#define QOS_INIT_G2H_QOSWT390_H
+
+static uint64_t qoswt_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008070000C010UL,
+	/* 0x0038, */ 0x0010100D0000C010UL,
+	/* 0x0040, */ 0x00141C0E0000FFF0UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x00141C190000C010UL,
+	/* 0x0060, */ 0x00141C190000C010UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x00141C0E0000FFF0UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C030000FFF0UL,
+	/* 0x0268, */ 0x001410010000FFF0UL,
+	/* 0x0270, */ 0x001404010000FFF0UL,
+	/* 0x0278, */ 0x000C08020000FFF0UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410010000FFF0UL,
+	/* 0x0298, */ 0x001404010000FFF0UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+#endif /* QOS_INIT_G2H_QOSWT390_H */
diff --git a/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c
new file mode 100644
index 0000000..7f466c8
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "qos_init_g2h_v30.h"
+#include "../qos_common.h"
+#include "../qos_reg.h"
+
+#define RCAR_QOS_VERSION			"rev.0.07"
+
+#define QOSWT_TIME_BANK0			20000000U	/* unit:ns */
+#define QOSWT_WTEN_ENABLE			0x1U
+
+#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_G2H	(SL_INIT_SSLOTCLK_G2H - 0x5U)
+
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT		3U
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT		9U
+#define QOSWT_WTREF_SLOT0_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+						(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+						(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+
+#define QOSWT_WTSET0_REQ_SSLOT0			5U
+#define WT_BASE_SUB_SLOT_NUM0			12U
+#define QOSWT_WTSET0_PERIOD0_G2H		((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_G2H) - 1U)
+#define QOSWT_WTSET0_SSLOT0			(QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET0_SLOTSLOT0			(WT_BASE_SUB_SLOT_NUM0 - 1U)
+
+#define QOSWT_WTSET1_PERIOD1_G2H		(QOSWT_WTSET0_PERIOD0_G2H)
+#define QOSWT_WTSET1_SSLOT1			(QOSWT_WTSET0_SSLOT0)
+#define QOSWT_WTSET1_SLOTSLOT1			(QOSWT_WTSET0_SLOTSLOT0)
+
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_g2h_mstat195.h"
+#else
+#include "qos_init_g2h_mstat390.h"
+#endif /* RCAR_REF_INT == RCAR_REF_DEFAULT */
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_g2h_qoswt195.h"
+#else
+#include "qos_init_g2h_qoswt390.h"
+#endif /* RCAR_REF_INT == RCAR_REF_DEFAULT */
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+#endif /* RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT */
+
+static const struct rcar_gen3_dbsc_qos_settings g2h_v30_qos[] = {
+	/* BUFCAM settings */
+	{ DBSC_DBCAM0CNF1, 0x00043218U },
+	{ DBSC_DBCAM0CNF2, 0x000000F4U },
+	{ DBSC_DBCAM0CNF3, 0x00000000U },
+	{ DBSC_DBSCHCNT0, 0x000F0037U },
+	{ DBSC_DBSCHSZ0, 0x00000001U },
+	{ DBSC_DBSCHRW0, 0x22421111U },
+
+	/* DDR3 */
+	{ DBSC_SCFCTST2, 0x012F1123U },
+
+	/* QoS Settings */
+	{ DBSC_DBSCHQOS00, 0x00000F00U },
+	{ DBSC_DBSCHQOS01, 0x00000B00U },
+	{ DBSC_DBSCHQOS02, 0x00000000U },
+	{ DBSC_DBSCHQOS03, 0x00000000U },
+	{ DBSC_DBSCHQOS40, 0x00000300U },
+	{ DBSC_DBSCHQOS41, 0x000002F0U },
+	{ DBSC_DBSCHQOS42, 0x00000200U },
+	{ DBSC_DBSCHQOS43, 0x00000100U },
+	{ DBSC_DBSCHQOS90, 0x00000100U },
+	{ DBSC_DBSCHQOS91, 0x000000F0U },
+	{ DBSC_DBSCHQOS92, 0x000000A0U },
+	{ DBSC_DBSCHQOS93, 0x00000040U },
+	{ DBSC_DBSCHQOS120, 0x00000040U },
+	{ DBSC_DBSCHQOS121, 0x00000030U },
+	{ DBSC_DBSCHQOS122, 0x00000020U },
+	{ DBSC_DBSCHQOS123, 0x00000010U },
+	{ DBSC_DBSCHQOS130, 0x00000100U },
+	{ DBSC_DBSCHQOS131, 0x000000F0U },
+	{ DBSC_DBSCHQOS132, 0x000000A0U },
+	{ DBSC_DBSCHQOS133, 0x00000040U },
+	{ DBSC_DBSCHQOS140, 0x000000C0U },
+	{ DBSC_DBSCHQOS141, 0x000000B0U },
+	{ DBSC_DBSCHQOS142, 0x00000080U },
+	{ DBSC_DBSCHQOS143, 0x00000040U },
+	{ DBSC_DBSCHQOS150, 0x00000040U },
+	{ DBSC_DBSCHQOS151, 0x00000030U },
+	{ DBSC_DBSCHQOS152, 0x00000020U },
+	{ DBSC_DBSCHQOS153, 0x00000010U },
+};
+
+void qos_init_g2h_v30(void)
+{
+	unsigned int split_area;
+
+	rzg_qos_dbsc_setting(g2h_v30_qos, ARRAY_SIZE(g2h_v30_qos), true);
+
+	/* use 1(2GB) for RCAR_DRAM_LPDDR4_MEMCONF for G2H */
+	split_area = 0x1CU;
+
+	/* DRAM split address mapping */
+#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH)
+#if RCAR_LSI == RZ_G2H
+#error "Don't set DRAM Split 4ch(G2H)"
+#else /* RCAR_LSI == RZ_G2H */
+	ERROR("DRAM split 4ch not supported.(G2H)");
+	panic();
+#endif /* RCAR_LSI == RZ_G2H */
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
+	(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+	NOTICE("BL2: DRAM Split is 2ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
+
+	mmio_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
+	mmio_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT |
+		    ADSPLCR0_SPLITSEL(0xFFU) | ADSPLCR0_AREA(split_area) |
+		    ADSPLCR0_SWP);
+	mmio_write_32(AXI_ADSPLCR2, 0x00001004U);
+	mmio_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else /* RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH */
+	mmio_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
+	NOTICE("BL2: DRAM Split is OFF(DDR %x)\n", (int)qos_init_ddr_phyvalid);
+#endif /* RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH */
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+	NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+	NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
+#else
+	NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	NOTICE("BL2: Periodic Write DQ Training\n");
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	mmio_write_32(QOSCTRL_RAS, 0x00000044U);
+	mmio_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
+	mmio_write_32(QOSCTRL_DANT, 0x0020100AU);
+	mmio_write_32(QOSCTRL_FSS, 0x0000000AU);
+	mmio_write_32(QOSCTRL_INSFC, 0x06330001U);
+	mmio_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+	/* GPU Boost Mode */
+	mmio_write_32(QOSCTRL_STATGEN0, 0x00000001U);
+
+	mmio_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT |
+		      SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_G2H);
+	mmio_write_32(QOSCTRL_REF_ARS, ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_G2H << 16)));
+
+	uint32_t i;
+
+	for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+		mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]);
+		mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]);
+	}
+	for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+		mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]);
+		mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]);
+	}
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+		mmio_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8U, qoswt_fix[i]);
+		mmio_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8U, qoswt_fix[i]);
+	}
+	for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+		mmio_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8U, qoswt_be[i]);
+		mmio_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8U, qoswt_be[i]);
+	}
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	/* AXI setting */
+	mmio_write_32(AXI_MMCR, 0x00010008U);
+	mmio_write_32(AXI_TR3CR, 0x00010000U);
+	mmio_write_32(AXI_TR4CR, 0x00010000U);
+
+	/* RT bus Leaf setting */
+	mmio_write_32(RT_ACT0, 0x00000000U);
+	mmio_write_32(RT_ACT1, 0x00000000U);
+
+	/* CCI bus Leaf setting */
+	mmio_write_32(CPU_ACT0, 0x00000003U);
+	mmio_write_32(CPU_ACT1, 0x00000003U);
+	mmio_write_32(CPU_ACT2, 0x00000003U);
+	mmio_write_32(CPU_ACT3, 0x00000003U);
+
+	mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	/*  re-write training setting */
+	mmio_write_32(QOSWT_WTREF,
+		      ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
+	mmio_write_32(QOSWT_WTSET0,
+		      ((QOSWT_WTSET0_PERIOD0_G2H << 16) |
+		      (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
+	mmio_write_32(QOSWT_WTSET1,
+		      ((QOSWT_WTSET1_PERIOD1_G2H << 16) |
+		      (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
+
+	mmio_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	mmio_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+	NOTICE("BL2: QoS is None\n");
+
+	mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.h b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.h
new file mode 100644
index 0000000..acd9627
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2H_V30_H
+#define QOS_INIT_G2H_V30_H
+
+void qos_init_g2h_v30(void);
+
+#endif /* QOS_INIT_G2H_V30_H */
diff --git a/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c
new file mode 100644
index 0000000..00b0948
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "qos_init_g2n_v10.h"
+
+#include "../qos_common.h"
+#include "../qos_reg.h"
+
+#define RCAR_QOS_VERSION			"rev.0.09"
+
+#define REF_ARS_ARBSTOPCYCLE_G2N		(((SL_INIT_SSLOTCLK_G2N) - 5U) << 16U)
+
+#define QOSWT_TIME_BANK0			20000000U	/* unit:ns */
+
+#define	QOSWT_WTEN_ENABLE			0x1U
+
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT		3U
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT		9U
+#define QOSWT_WTREF_SLOT0_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+						(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN			QOSWT_WTREF_SLOT0_EN
+
+#define QOSWT_WTSET0_REQ_SSLOT0			5U
+#define WT_BASE_SUB_SLOT_NUM0			12U
+#define QOSWT_WTSET0_PERIOD0_G2N		((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_G2N) - 1U)
+#define QOSWT_WTSET0_SSLOT0			(QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET0_SLOTSLOT0			(WT_BASE_SUB_SLOT_NUM0 - 1U)
+
+#define QOSWT_WTSET1_PERIOD1_G2N		QOSWT_WTSET0_PERIOD0_G2N
+#define QOSWT_WTSET1_SSLOT1			QOSWT_WTSET0_SSLOT0
+#define QOSWT_WTSET1_SLOTSLOT1			QOSWT_WTSET0_SLOTSLOT0
+
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_g2n_v10_mstat195.h"
+#else
+#include "qos_init_g2n_v10_mstat390.h"
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_g2n_v10_qoswt195.h"
+#else
+#include "qos_init_g2n_v10_qoswt390.h"
+#endif
+
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+#endif
+
+static const struct rcar_gen3_dbsc_qos_settings g2n_v10_qos[] = {
+	/* BUFCAM settings */
+	{ DBSC_DBCAM0CNF1, 0x00043218U },
+	{ DBSC_DBCAM0CNF2, 0x000000F4U },
+	{ DBSC_DBSCHCNT0, 0x000F0037U },
+	{ DBSC_DBSCHSZ0, 0x00000001U },
+	{ DBSC_DBSCHRW0, 0x22421111U },
+
+	/* DDR3 */
+	{ DBSC_SCFCTST2, 0x012F1123U },
+
+	/* QoS Settings */
+	{ DBSC_DBSCHQOS00, 0x00000F00U },
+	{ DBSC_DBSCHQOS01, 0x00000B00U },
+	{ DBSC_DBSCHQOS02, 0x00000000U },
+	{ DBSC_DBSCHQOS03, 0x00000000U },
+	{ DBSC_DBSCHQOS40, 0x00000300U },
+	{ DBSC_DBSCHQOS41, 0x000002F0U },
+	{ DBSC_DBSCHQOS42, 0x00000200U },
+	{ DBSC_DBSCHQOS43, 0x00000100U },
+	{ DBSC_DBSCHQOS90, 0x00000100U },
+	{ DBSC_DBSCHQOS91, 0x000000F0U },
+	{ DBSC_DBSCHQOS92, 0x000000A0U },
+	{ DBSC_DBSCHQOS93, 0x00000040U },
+	{ DBSC_DBSCHQOS130, 0x00000100U },
+	{ DBSC_DBSCHQOS131, 0x000000F0U },
+	{ DBSC_DBSCHQOS132, 0x000000A0U },
+	{ DBSC_DBSCHQOS133, 0x00000040U },
+	{ DBSC_DBSCHQOS140, 0x000000C0U },
+	{ DBSC_DBSCHQOS141, 0x000000B0U },
+	{ DBSC_DBSCHQOS142, 0x00000080U },
+	{ DBSC_DBSCHQOS143, 0x00000040U },
+	{ DBSC_DBSCHQOS150, 0x00000040U },
+	{ DBSC_DBSCHQOS151, 0x00000030U },
+	{ DBSC_DBSCHQOS152, 0x00000020U },
+	{ DBSC_DBSCHQOS153, 0x00000010U },
+};
+
+void qos_init_g2n_v10(void)
+{
+	rzg_qos_dbsc_setting(g2n_v10_qos, ARRAY_SIZE(g2n_v10_qos), true);
+
+	/* DRAM Split Address mapping */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
+#if RCAR_LSI == RZ_G2N
+#error "Don't set DRAM Split 4ch(G2N)"
+#else
+	ERROR("DRAM Split 4ch not supported.(G2N)");
+	panic();
+#endif
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
+#if RCAR_LSI == RZ_G2N
+#error "Don't set DRAM Split 2ch(G2N)"
+#else
+	ERROR("DRAM Split 2ch not supported.(G2N)");
+	panic();
+#endif
+#else
+	NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+	NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+	NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
+#else
+	NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	NOTICE("BL2: Periodic Write DQ Training\n");
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	mmio_write_32(QOSCTRL_RAS, 0x00000028U);
+	mmio_write_64(QOSCTRL_DANN, 0x0402000002020201UL);
+	mmio_write_32(QOSCTRL_DANT, 0x00100804U);
+	mmio_write_32(QOSCTRL_FSS, 0x0000000AU);
+	mmio_write_32(QOSCTRL_INSFC, 0x06330001U);
+	mmio_write_32(QOSCTRL_EARLYR, 0x00000001U);
+	mmio_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+	mmio_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT |
+		      SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_G2N);
+	mmio_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_G2N);
+
+	uint32_t i;
+
+	for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+		mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]);
+		mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]);
+	}
+	for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+		mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]);
+		mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]);
+	}
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+		mmio_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8U, qoswt_fix[i]);
+		mmio_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8U, qoswt_fix[i]);
+	}
+	for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+		mmio_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8U, qoswt_be[i]);
+		mmio_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8U, qoswt_be[i]);
+	}
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	/* RT bus Leaf setting */
+	mmio_write_32(RT_ACT0, 0x00000000U);
+	mmio_write_32(RT_ACT1, 0x00000000U);
+
+	/* CCI bus Leaf setting */
+	mmio_write_32(CPU_ACT0, 0x00000003U);
+	mmio_write_32(CPU_ACT1, 0x00000003U);
+
+	mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	/*  re-write training setting */
+	mmio_write_32(QOSWT_WTREF, ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
+	mmio_write_32(QOSWT_WTSET0, ((QOSWT_WTSET0_PERIOD0_G2N << 16) |
+		      (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
+	mmio_write_32(QOSWT_WTSET1, ((QOSWT_WTSET1_PERIOD1_G2N << 16) |
+		      (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
+
+	mmio_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	mmio_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+	NOTICE("BL2: QoS is None\n");
+
+	mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.h b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.h
new file mode 100644
index 0000000..c7f02d9
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2N_V10_H
+#define QOS_INIT_G2N_V10_H
+
+void qos_init_g2n_v10(void);
+
+#endif /* QOS_INIT_G2N_V10_H */
diff --git a/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat195.h b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat195.h
new file mode 100644
index 0000000..6e304b0
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat195.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2N_MSTAT195_H
+#define QOS_INIT_G2N_MSTAT195_H
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001004320000FFFFUL,
+	/* 0x0038, */ 0x001004320000FFFFUL,
+	/* 0x0040, */ 0x00140C5D0000FFFFUL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x001404040000FFFFUL,
+	/* 0x0058, */ 0x00140C940000FFFFUL,
+	/* 0x0060, */ 0x00140C940000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x001404040000FFFFUL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0014041F0000FFFFUL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C041D0000FFFFUL,
+	/* 0x00a8, */ 0x000C04090000FFFFUL,
+	/* 0x00b0, */ 0x000C040B0000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C041D0000FFFFUL,
+	/* 0x00c8, */ 0x000C04090000FFFFUL,
+	/* 0x00d0, */ 0x000C040B0000FFFFUL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x000C084F0000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x000C21E60000FFFFUL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x00100CA50000FFFFUL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x001010C90000FFFFUL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x00100CA50000FFFFUL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x001008530000FFFFUL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x00101D9D0000FFFFUL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x00100CA50000FFFFUL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x001408020000FFFFUL,
+	/* 0x0270, */ 0x001404010000FFFFUL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001408020000FFFFUL,
+	/* 0x0298, */ 0x001404010000FFFFUL,
+	/* 0x02a0, */ 0x000C04050000FFFFUL,
+	/* 0x02a8, */ 0x000C04050000FFFFUL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04050000FFFFUL,
+	/* 0x02d8, */ 0x000C04050000FFFFUL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x000C04050000FFFFUL,
+	/* 0x0388, */ 0x000C04050000FFFFUL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x001200100BD03401UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x002106000BDFFC01UL,
+	/* 0x01c8, */ 0x002106000BDFFC01UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x001101000BDF2401UL,
+	/* 0x0220, */ 0x001101000BDF2401UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x001101000BDF2401UL,
+	/* 0x0238, */ 0x001101000BDF2401UL,
+	/* 0x0240, */ 0x001201000BDF2401UL,
+	/* 0x0248, */ 0x001101000BDF2401UL,
+	/* 0x0250, */ 0x001201000BDF2401UL,
+	/* 0x0258, */ 0x001101000BDF2401UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x001106000BDFFC01UL,
+	/* 0x02f8, */ 0x001106000BDFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x001200100BD03401UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x001206000BDFFC01UL,
+	/* 0x0360, */ 0x001206000BDFFC01UL,
+	/* 0x0368, */ 0x001200100BD03401UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x001200100BD03401UL,
+};
+#endif /* QOS_INIT_G2N_MSTAT195_H */
diff --git a/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat390.h b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat390.h
new file mode 100644
index 0000000..4632413
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat390.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2N_MSTAT390_H
+#define QOS_INIT_G2N_MSTAT390_H
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008630000FFFFUL,
+	/* 0x0038, */ 0x001008630000FFFFUL,
+	/* 0x0040, */ 0x001418BA0000FFFFUL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x001404070000FFFFUL,
+	/* 0x0058, */ 0x001415270000FFFFUL,
+	/* 0x0060, */ 0x001415270000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x001404070000FFFFUL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0014083E0000FFFFUL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C08390000FFFFUL,
+	/* 0x00a8, */ 0x000C04110000FFFFUL,
+	/* 0x00b0, */ 0x000C04150000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C08390000FFFFUL,
+	/* 0x00c8, */ 0x000C04110000FFFFUL,
+	/* 0x00d0, */ 0x000C04150000FFFFUL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x001045080000FFFFUL,
+	/* 0x00f8, */ 0x000C0C9E0000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x001015080000FFFFUL,
+	/* 0x0118, */ 0x000C43CB0000FFFFUL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0010194A0000FFFFUL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x00101D910000FFFFUL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0010194A0000FFFFUL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x00100CA50000FFFFUL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x001037390000FFFFUL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0010194A0000FFFFUL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04020000FFFFUL,
+	/* 0x01f0, */ 0x000C04090000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04090000FFFFUL,
+	/* 0x0210, */ 0x000C04090000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C2A0000FFFFUL,
+	/* 0x0268, */ 0x001410040000FFFFUL,
+	/* 0x0270, */ 0x001404020000FFFFUL,
+	/* 0x0278, */ 0x000C08110000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410040000FFFFUL,
+	/* 0x0298, */ 0x001404020000FFFFUL,
+	/* 0x02a0, */ 0x000C04090000FFFFUL,
+	/* 0x02a8, */ 0x000C04090000FFFFUL,
+	/* 0x02b0, */ 0x00140C090000FFFFUL,
+	/* 0x02b8, */ 0x000C04020000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04090000FFFFUL,
+	/* 0x02d8, */ 0x000C04090000FFFFUL,
+	/* 0x02e0, */ 0x00140C090000FFFFUL,
+	/* 0x02e8, */ 0x000C04020000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x000C04020000FFFFUL,
+	/* 0x0378, */ 0x000C04020000FFFFUL,
+	/* 0x0380, */ 0x000C04090000FFFFUL,
+	/* 0x0388, */ 0x000C04090000FFFFUL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0012001005E03401UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0021060005EFFC01UL,
+	/* 0x01c8, */ 0x0021060005EFFC01UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0021010005E79401UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0021010005E79401UL,
+	/* 0x0218, */ 0x0011010005E79401UL,
+	/* 0x0220, */ 0x0011010005E79401UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0011010005E79401UL,
+	/* 0x0238, */ 0x0011010005E79401UL,
+	/* 0x0240, */ 0x0012010005E79401UL,
+	/* 0x0248, */ 0x0011010005E79401UL,
+	/* 0x0250, */ 0x0012010005E79401UL,
+	/* 0x0258, */ 0x0011010005E79401UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0011060005EFFC01UL,
+	/* 0x02f8, */ 0x0011060005EFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0012001005E03401UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0012060005EFFC01UL,
+	/* 0x0360, */ 0x0012060005EFFC01UL,
+	/* 0x0368, */ 0x0012001005E03401UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0012001005E03401UL,
+};
+#endif /* QOS_INIT_G2N_MSTAT390_H */
diff --git a/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt195.h b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt195.h
new file mode 100644
index 0000000..eea1fce
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt195.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2N_QOSWT195_H
+#define QOS_INIT_G2N_QOSWT195_H
+
+static uint64_t qoswt_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001004320000C010UL,
+	/* 0x0038, */ 0x001004320000C010UL,
+	/* 0x0040, */ 0x00140C5D0000FFF0UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x00140C940000C010UL,
+	/* 0x0060, */ 0x00140C940000C010UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0014041F0000FFF0UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C08150000FFF0UL,
+	/* 0x0268, */ 0x001408020000FFF0UL,
+	/* 0x0270, */ 0x001404010000FFF0UL,
+	/* 0x0278, */ 0x000C04090000FFF0UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001408020000FFF0UL,
+	/* 0x0298, */ 0x001404010000FFF0UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+#endif /* QOS_INIT_G2N_QOSWT195_H */
diff --git a/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt390.h b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt390.h
new file mode 100644
index 0000000..7043303
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt390.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2N_QOSWT390_H
+#define QOS_INIT_G2N_QOSWT390_H
+
+static uint64_t qoswt_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008630000C010UL,
+	/* 0x0038, */ 0x001008630000C010UL,
+	/* 0x0040, */ 0x001418BA0000FFF0UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x001415270000C010UL,
+	/* 0x0060, */ 0x001415270000C010UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0014083E0000FFF0UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C2A0000FFF0UL,
+	/* 0x0268, */ 0x001410040000FFF0UL,
+	/* 0x0270, */ 0x001404020000FFF0UL,
+	/* 0x0278, */ 0x000C08110000FFF0UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410040000FFF0UL,
+	/* 0x0298, */ 0x001404020000FFF0UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+#endif /* QOS_INIT_G2N_QOSWT390_H */
diff --git a/drivers/renesas/rzg/qos/qos.mk b/drivers/renesas/rzg/qos/qos.mk
index f06c685..f05d126 100644
--- a/drivers/renesas/rzg/qos/qos.mk
+++ b/drivers/renesas/rzg/qos/qos.mk
@@ -1,19 +1,31 @@
 #
-# Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
 ifeq (${RCAR_LSI},${RCAR_AUTO})
+    BL2_SOURCES += drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c
+    BL2_SOURCES += drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c
     BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v10.c
     BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11.c
     BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30.c
+    BL2_SOURCES += drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c
 else ifeq (${RCAR_LSI_CUT_COMPAT},1)
   ifeq (${RCAR_LSI},${RZ_G2M})
     BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v10.c
     BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11.c
     BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30.c
   endif
+  ifeq (${RCAR_LSI},${RZ_G2H})
+    BL2_SOURCES += drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c
+  endif
+  ifeq (${RCAR_LSI},${RZ_G2N})
+    BL2_SOURCES += drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c
+  endif
+  ifeq (${RCAR_LSI},${RZ_G2E})
+    BL2_SOURCES += drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c
+  endif
 else
   ifeq (${RCAR_LSI},${RZ_G2M})
     ifeq (${LSI_CUT},10)
@@ -29,6 +41,20 @@
      BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30.c
     endif
   endif
+  ifeq (${RCAR_LSI},${RZ_G2H})
+     BL2_SOURCES += drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c
+  endif
+  ifeq (${RCAR_LSI},${RZ_G2N})
+    ifeq (${LSI_CUT},10)
+     BL2_SOURCES += drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c
+    else
+#    LSI_CUT 10 or later
+     BL2_SOURCES += drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c
+    endif
+  endif
+  ifeq (${RCAR_LSI},${RZ_G2E})
+    BL2_SOURCES += drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c
+  endif
 endif
 
 BL2_SOURCES += drivers/renesas/rzg/qos/qos_init.c
diff --git a/drivers/renesas/rzg/qos/qos_common.h b/drivers/renesas/rzg/qos/qos_common.h
index 6e0cf0e..535bf4c 100644
--- a/drivers/renesas/rzg/qos/qos_common.h
+++ b/drivers/renesas/rzg/qos/qos_common.h
@@ -37,6 +37,44 @@
 	((SUB_SLOT_CYCLE_G2M_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
 #endif
 
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2N)
+/* define used for G2N */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 1.95usec */
+#define SUB_SLOT_CYCLE_G2N		0x7EU	/* 126 */
+#else /* REF 3.9usec */
+#define SUB_SLOT_CYCLE_G2N		0xFCU	/* 252 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define SL_INIT_SSLOTCLK_G2N		(SUB_SLOT_CYCLE_G2N - 1U)
+#define QOSWT_WTSET0_CYCLE_G2N		/* unit:ns */	\
+	((SUB_SLOT_CYCLE_G2N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
+#endif /* (RCAR_LSI == RZ_G2N) */
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H)
+/* define used for G2H */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 1.95usec */
+#define SUB_SLOT_CYCLE_G2H		0x7EU	/* 126 */
+#else /* REF 3.9usec */
+#define SUB_SLOT_CYCLE_G2H		0xFCU	/* 252 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define SL_INIT_SSLOTCLK_G2H		(SUB_SLOT_CYCLE_G2H - 1U)
+#define QOSWT_WTSET0_CYCLE_G2H		/* unit:ns */	\
+	((SUB_SLOT_CYCLE_G2H * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2E)
+/* define used for G2E */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 3.9usec */
+#define SUB_SLOT_CYCLE_G2E		0xAFU	/* 175 */
+#else /* REF 7.8usec */
+#define SUB_SLOT_CYCLE_G2E		0x15EU	/* 350 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define OPERATING_FREQ_G2E		266U	/* MHz */
+#define SL_INIT_SSLOTCLK_G2E		(SUB_SLOT_CYCLE_G2E - 1U)
+#endif
+
 #define OPERATING_FREQ			400U	/* MHz */
 #define BASE_SUB_SLOT_NUM		0x6U
 #define SUB_SLOT_CYCLE			0x7EU	/* 126 */
diff --git a/drivers/renesas/rzg/qos/qos_init.c b/drivers/renesas/rzg/qos/qos_init.c
index 2d5aece..e527a61 100644
--- a/drivers/renesas/rzg/qos/qos_init.c
+++ b/drivers/renesas/rzg/qos/qos_init.c
@@ -10,23 +10,37 @@
 #include <lib/mmio.h>
 
 #if RCAR_LSI == RCAR_AUTO
+#include "G2E/qos_init_g2e_v10.h"
+#include "G2H/qos_init_g2h_v30.h"
 #include "G2M/qos_init_g2m_v10.h"
 #include "G2M/qos_init_g2m_v11.h"
 #include "G2M/qos_init_g2m_v30.h"
+#include "G2N/qos_init_g2n_v10.h"
 #endif /* RCAR_LSI == RCAR_AUTO */
 #if (RCAR_LSI == RZ_G2M)
 #include "G2M/qos_init_g2m_v10.h"
 #include "G2M/qos_init_g2m_v11.h"
 #include "G2M/qos_init_g2m_v30.h"
 #endif /* RCAR_LSI == RZ_G2M */
+#if RCAR_LSI == RZ_G2H
+#include "G2H/qos_init_g2h_v30.h"
+#endif /* RCAR_LSI == RZ_G2H */
+#if RCAR_LSI == RZ_G2N
+#include "G2N/qos_init_g2n_v10.h"
+#endif /* RCAR_LSI == RZ_G2N */
+#if RCAR_LSI == RZ_G2E
+#include "G2E/qos_init_g2e_v10.h"
+#endif /* RCAR_LSI == RZ_G2E */
 #include "qos_common.h"
 #include "qos_init.h"
 #include "qos_reg.h"
 #include "rcar_def.h"
 
+#if (RCAR_LSI != RZ_G2E)
 #define DRAM_CH_CNT	0x04U
 uint32_t qos_init_ddr_ch;
 uint8_t qos_init_ddr_phyvalid;
+#endif /* RCAR_LSI != RZ_G2E */
 
 #define PRR_PRODUCT_ERR(reg)				\
 	{						\
@@ -45,15 +59,17 @@
 void rzg_qos_init(void)
 {
 	uint32_t reg;
+#if (RCAR_LSI != RZ_G2E)
 	uint32_t i;
 
 	qos_init_ddr_ch = 0U;
-	qos_init_ddr_phyvalid = rzg_get_boardcnf_phyvalid();
+	qos_init_ddr_phyvalid = get_boardcnf_phyvalid();
 	for (i = 0U; i < DRAM_CH_CNT; i++) {
 		if ((qos_init_ddr_phyvalid & (1U << i))) {
 			qos_init_ddr_ch++;
 		}
 	}
+#endif /* RCAR_LSI != RZ_G2E */
 
 	reg = mmio_read_32(PRR);
 #if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT
@@ -76,6 +92,42 @@
 		PRR_PRODUCT_ERR(reg);
 #endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M) */
 		break;
+	case PRR_PRODUCT_H3:
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H)
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_30:
+		default:
+			qos_init_g2h_v30();
+			break;
+		}
+#else
+		PRR_PRODUCT_ERR(reg);
+#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H) */
+		break;
+	case PRR_PRODUCT_M3N:
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2N)
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_10:
+		default:
+			qos_init_g2n_v10();
+			break;
+		}
+#else
+		PRR_PRODUCT_ERR(reg);
+#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2N) */
+		break;
+	case PRR_PRODUCT_E3:
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2E)
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_10:
+		default:
+			qos_init_g2e_v10();
+			break;
+		}
+#else
+		PRR_PRODUCT_ERR(reg);
+#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2E) */
+		break;
 	default:
 		PRR_PRODUCT_ERR(reg);
 		break;
@@ -111,12 +163,31 @@
 	}
 	qos_init_g2m_v30();
 #endif /* RCAR_LSI_CUT == RCAR_CUT_10 */
+#elif (RCAR_LSI == RZ_G2H)
+	/* G2H Cut 30 or later */
+	if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_H3) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	qos_init_g2h_v30();
+#elif (RCAR_LSI == RZ_G2N)
+	/* G2N Cut 10 or later */
+	if ((reg & (PRR_PRODUCT_MASK)) != PRR_PRODUCT_M3N) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	qos_init_g2n_v10();
+#elif RCAR_LSI == RZ_G2E
+	/* G2E Cut 10 or later */
+	if ((reg & (PRR_PRODUCT_MASK)) != PRR_PRODUCT_E3) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	qos_init_g2e_v10();
 #else /* (RCAR_LSI == RZ_G2M) */
 #error "Don't have QoS initialize routine(Unknown chip)."
 #endif /* (RCAR_LSI == RZ_G2M) */
 #endif /* RCAR_LSI == RCAR_AUTO || RCAR_LSI_CUT_COMPAT */
 }
 
+#if (RCAR_LSI != RZ_G2E)
 uint32_t get_refperiod(void)
 {
 	uint32_t refperiod = QOSWT_WTSET0_CYCLE;
@@ -140,6 +211,21 @@
 		}
 		break;
 #endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M) */
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H)
+	case PRR_PRODUCT_H3:
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_30:
+		default:
+			refperiod = REFPERIOD_CYCLE;
+			break;
+		}
+		break;
+#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H) */
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2N)
+	case PRR_PRODUCT_M3N:
+		refperiod = REFPERIOD_CYCLE;
+		break;
+#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2N) */
 	default:
 		break;
 	}
@@ -150,9 +236,15 @@
 	/* G2M Cut 11|13|30 or later */
 	refperiod = REFPERIOD_CYCLE;
 #endif /* RCAR_LSI_CUT == RCAR_CUT_10 */
+#elif RCAR_LSI == RZ_G2N
+	refperiod = REFPERIOD_CYCLE;
+#elif RCAR_LSI == RZ_G2H
+	/* G2H Cut 30 or later */
+	refperiod = REFPERIOD_CYCLE;
 #endif /* RCAR_LSI == RCAR_AUTO || RCAR_LSI_CUT_COMPAT */
 	return refperiod;
 }
+#endif /* RCAR_LSI != RZ_G2E */
 
 void rzg_qos_dbsc_setting(const struct rcar_gen3_dbsc_qos_settings *qos,
 			  unsigned int qos_size, bool dbsc_wren)
diff --git a/drivers/renesas/rzg/qos/qos_init.h b/drivers/renesas/rzg/qos/qos_init.h
index 10f60e7..3d62744 100644
--- a/drivers/renesas/rzg/qos/qos_init.h
+++ b/drivers/renesas/rzg/qos/qos_init.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,6 @@
 #define RZG_QOS_INIT_H
 
 void rzg_qos_init(void);
-uint8_t rzg_get_boardcnf_phyvalid(void);
+uint8_t get_boardcnf_phyvalid(void);
 
 #endif /* RZG_QOS_INIT_H */
diff --git a/fdts/fvp-base-gicv2-psci-aarch32.dts b/fdts/fvp-base-gicv2-psci-aarch32.dts
index 591ec58..3a921f4 100644
--- a/fdts/fvp-base-gicv2-psci-aarch32.dts
+++ b/fdts/fvp-base-gicv2-psci-aarch32.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,6 +11,7 @@
 #define	AFF
 #define	REG_32
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "fvp-defs.dtsi"
 
 /memreserve/ 0x80000000 0x00010000;
@@ -100,10 +101,14 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <1 13 0xff01>,
-			     <1 14 0xff01>,
-			     <1 11 0xff01>,
-			     <1 10 0xff01>;
+		interrupts = <GIC_PPI 13
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <100000000>;
 	};
 
diff --git a/fdts/fvp-base-gicv2-psci.dts b/fdts/fvp-base-gicv2-psci.dts
index 4b3942e..e99719e 100644
--- a/fdts/fvp-base-gicv2-psci.dts
+++ b/fdts/fvp-base-gicv2-psci.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +10,7 @@
 
 #define	AFF
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "fvp-defs.dtsi"
 
 /memreserve/ 0x80000000 0x00010000;
@@ -99,10 +100,14 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <1 13 0xff01>,
-			     <1 14 0xff01>,
-			     <1 11 0xff01>,
-			     <1 10 0xff01>;
+		interrupts = <GIC_PPI 13
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <100000000>;
 	};
 
diff --git a/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi b/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi
index 1a1bd12..85988e9 100644
--- a/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi
+++ b/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi
@@ -1,9 +1,11 @@
 /*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 /memreserve/ 0x80000000 0x00010000;
 
 / {
@@ -100,10 +102,14 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <1 13 0xff01>,
-			     <1 14 0xff01>,
-			     <1 11 0xff01>,
-			     <1 10 0xff01>;
+		interrupts = <GIC_PPI 13
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <100000000>;
 	};
 
diff --git a/fdts/fvp-base-gicv3-psci-common.dtsi b/fdts/fvp-base-gicv3-psci-common.dtsi
index 192f574..b6753de 100644
--- a/fdts/fvp-base-gicv3-psci-common.dtsi
+++ b/fdts/fvp-base-gicv3-psci-common.dtsi
@@ -1,9 +1,10 @@
 /*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <services/sdei_flags.h>
 
 #define LEVEL	0
@@ -161,10 +162,14 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <1 13 0xff01>,
-			     <1 14 0xff01>,
-			     <1 11 0xff01>,
-			     <1 10 0xff01>;
+		interrupts = <GIC_PPI 13
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <100000000>;
 	};
 
diff --git a/fdts/fvp-foundation-gicv2-psci.dts b/fdts/fvp-foundation-gicv2-psci.dts
index 95a800e..5a82c46 100644
--- a/fdts/fvp-foundation-gicv2-psci.dts
+++ b/fdts/fvp-foundation-gicv2-psci.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,6 +11,7 @@
 #define	AFF
 #define	CLUSTER_COUNT	1
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "fvp-defs.dtsi"
 
 /memreserve/ 0x80000000 0x00010000;
@@ -100,10 +101,14 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <1 13 0xff01>,
-			     <1 14 0xff01>,
-			     <1 11 0xff01>,
-			     <1 10 0xff01>;
+		interrupts = <GIC_PPI 13
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <100000000>;
 	};
 
diff --git a/fdts/fvp-foundation-gicv3-psci.dts b/fdts/fvp-foundation-gicv3-psci.dts
index c295dc1..e1249d4 100644
--- a/fdts/fvp-foundation-gicv3-psci.dts
+++ b/fdts/fvp-foundation-gicv3-psci.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,6 +11,7 @@
 #define	AFF
 #define	CLUSTER_COUNT	1
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "fvp-defs.dtsi"
 
 /memreserve/ 0x80000000 0x00010000;
@@ -109,10 +110,14 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <1 13 0xff01>,
-			     <1 14 0xff01>,
-			     <1 11 0xff01>,
-			     <1 10 0xff01>;
+		interrupts = <GIC_PPI 13
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <100000000>;
 	};
 
diff --git a/fdts/stm32mp15-pinctrl.dtsi b/fdts/stm32mp15-pinctrl.dtsi
index d3d1744..058cde2 100644
--- a/fdts/stm32mp15-pinctrl.dtsi
+++ b/fdts/stm32mp15-pinctrl.dtsi
@@ -31,6 +31,16 @@
 		};
 	};
 
+	i2c2_pins_a: i2c2-0 {
+		pins {
+			pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
+				 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
+			bias-disable;
+			drive-open-drain;
+			slew-rate = <0>;
+		};
+	};
+
 	qspi_clk_pins_a: qspi-clk-0 {
 		pins {
 			pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
@@ -166,6 +176,15 @@
 		};
 	};
 
+	sdmmc2_d47_pins_d: sdmmc2-d47-3 {
+		pins {
+			pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+				 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+				 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
+				 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
+		};
+	};
+
 	uart4_pins_a: uart4-0 {
 		pins1 {
 			pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
diff --git a/fdts/stm32mp151.dtsi b/fdts/stm32mp151.dtsi
index 8f175a6..c350c66 100644
--- a/fdts/stm32mp151.dtsi
+++ b/fdts/stm32mp151.dtsi
@@ -121,6 +121,21 @@
 			status = "disabled";
 		};
 
+		i2c2: i2c@40013000 {
+			compatible = "st,stm32mp15-i2c";
+			reg = <0x40013000 0x400>;
+			interrupt-names = "event", "error";
+			interrupts = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
+				     <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc I2C2_K>;
+			resets = <&rcc I2C2_R>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			st,syscfg-fmp = <&syscfg 0x4 0x2>;
+			wakeup-source;
+			status = "disabled";
+		};
+
 		uart7: serial@40018000 {
 			compatible = "st,stm32h7-uart";
 			reg = <0x40018000 0x400>;
diff --git a/fdts/stm32mp157c-odyssey-som.dtsi b/fdts/stm32mp157c-odyssey-som.dtsi
new file mode 100644
index 0000000..6bed339
--- /dev/null
+++ b/fdts/stm32mp157c-odyssey-som.dtsi
@@ -0,0 +1,325 @@
+/*
+ * Copyright (C) 2019, STMicroelectronics. All Rights Reserved.
+ * Copyright (C) 2021, Grzegorz Szymaszek.
+ *
+ * SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+ */
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xc.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
+
+/ {
+	memory@c0000000 {
+		device_type = "memory";
+		reg = <0xc0000000 0x20000000>;
+	};
+
+	vin: vin {
+		compatible = "regulator-fixed";
+		regulator-name = "vin";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+};
+
+&bsec {
+	board_id: board_id@ec {
+		reg = <0xec 0x4>;
+		st,non-secure-otp;
+	};
+};
+
+&clk_hse {
+	st,digbypass;
+};
+
+&cpu0 {
+	cpu-supply = <&vddcore>;
+};
+
+&cpu1 {
+	cpu-supply = <&vddcore>;
+};
+
+&cryp1 {
+	status = "okay";
+};
+
+&hash1 {
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins_a>;
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <185>;
+	i2c-scl-falling-time-ns = <20>;
+	status = "okay";
+
+	pmic: stpmic@33 {
+		compatible = "st,stpmic1";
+		reg = <0x33>;
+		interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		status = "okay";
+
+		regulators {
+			compatible = "st,stpmic1-regulators";
+			buck1-supply = <&vin>;
+			buck2-supply = <&vin>;
+			buck3-supply = <&vin>;
+			buck4-supply = <&vin>;
+			ldo1-supply = <&v3v3>;
+			ldo2-supply = <&vin>;
+			ldo3-supply = <&vdd_ddr>;
+			ldo4-supply = <&vin>;
+			ldo5-supply = <&vin>;
+			ldo6-supply = <&v3v3>;
+			vref_ddr-supply = <&vin>;
+			boost-supply = <&vin>;
+			pwr_sw1-supply = <&bst_out>;
+			pwr_sw2-supply = <&bst_out>;
+
+			vddcore: buck1 {
+				regulator-name = "vddcore";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-always-on;
+				regulator-initial-mode = <0>;
+				regulator-over-current-protection;
+			};
+
+			vdd_ddr: buck2 {
+				regulator-name = "vdd_ddr";
+				regulator-min-microvolt = <1350000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-always-on;
+				regulator-initial-mode = <0>;
+				regulator-over-current-protection;
+			};
+
+			vdd: buck3 {
+				regulator-name = "vdd";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				st,mask-reset;
+				regulator-initial-mode = <0>;
+				regulator-over-current-protection;
+			};
+
+			v3v3: buck4 {
+				regulator-name = "v3v3";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-over-current-protection;
+				regulator-initial-mode = <0>;
+			};
+
+			v1v8_audio: ldo1 {
+				regulator-name = "v1v8_audio";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			v3v3_hdmi: ldo2 {
+				regulator-name = "v3v3_hdmi";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vtt_ddr: ldo3 {
+				regulator-name = "vtt_ddr";
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <750000>;
+				regulator-always-on;
+				regulator-over-current-protection;
+			};
+
+			vdd_usb: ldo4 {
+				regulator-name = "vdd_usb";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vdda: ldo5 {
+				regulator-name = "vdda";
+				regulator-min-microvolt = <2900000>;
+				regulator-max-microvolt = <2900000>;
+				regulator-boot-on;
+			};
+
+			v1v2_hdmi: ldo6 {
+				regulator-name = "v1v2_hdmi";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+			};
+
+			vref_ddr: vref_ddr {
+				regulator-name = "vref_ddr";
+				regulator-always-on;
+				regulator-over-current-protection;
+			};
+
+			bst_out: boost {
+				regulator-name = "bst_out";
+			};
+
+			vbus_otg: pwr_sw1 {
+				regulator-name = "vbus_otg";
+			};
+
+			vbus_sw: pwr_sw2 {
+				regulator-name = "vbus_sw";
+				regulator-active-discharge = <1>;
+			};
+		};
+
+		pmic_watchdog: watchdog {
+			compatible = "st,stpmic1-wdt";
+			status = "disabled";
+		};
+	};
+};
+
+&iwdg2 {
+	timeout-sec = <32>;
+	status = "okay";
+};
+
+&pwr_regulators {
+	vdd-supply = <&vdd>;
+	vdd_3v3_usbfs-supply = <&vdd_usb>;
+};
+
+&rcc {
+	secure-status = "disabled";
+	st,clksrc = <
+		CLK_MPU_PLL1P
+		CLK_AXI_PLL2P
+		CLK_MCU_PLL3P
+		CLK_PLL12_HSE
+		CLK_PLL3_HSE
+		CLK_PLL4_HSE
+		CLK_RTC_LSE
+		CLK_MCO1_DISABLED
+		CLK_MCO2_DISABLED
+	>;
+
+	st,clkdiv = <
+		1 /*MPU*/
+		0 /*AXI*/
+		0 /*MCU*/
+		1 /*APB1*/
+		1 /*APB2*/
+		1 /*APB3*/
+		1 /*APB4*/
+		2 /*APB5*/
+		23 /*RTC*/
+		0 /*MCO1*/
+		0 /*MCO2*/
+	>;
+
+	st,pkcs = <
+		CLK_CKPER_HSE
+		CLK_FMC_ACLK
+		CLK_QSPI_ACLK
+		CLK_ETH_PLL4P
+		CLK_SDMMC12_PLL4P
+		CLK_DSI_DSIPLL
+		CLK_STGEN_HSE
+		CLK_USBPHY_HSE
+		CLK_SPI2S1_PLL3Q
+		CLK_SPI2S23_PLL3Q
+		CLK_SPI45_HSI
+		CLK_SPI6_HSI
+		CLK_I2C46_HSI
+		CLK_SDMMC3_PLL4P
+		CLK_USBO_USBPHY
+		CLK_ADC_CKPER
+		CLK_CEC_LSE
+		CLK_I2C12_HSI
+		CLK_I2C35_HSI
+		CLK_UART1_HSI
+		CLK_UART24_HSI
+		CLK_UART35_HSI
+		CLK_UART6_HSI
+		CLK_UART78_HSI
+		CLK_SPDIF_PLL4P
+		CLK_FDCAN_PLL4R
+		CLK_SAI1_PLL3Q
+		CLK_SAI2_PLL3Q
+		CLK_SAI3_PLL3Q
+		CLK_SAI4_PLL3Q
+		CLK_RNG1_LSI
+		CLK_RNG2_LSI
+		CLK_LPTIM1_PCLK1
+		CLK_LPTIM23_PCLK3
+		CLK_LPTIM45_LSE
+	>;
+
+	/* VCO = 1300.0 MHz => P = 650 (CPU) */
+	pll1: st,pll@0 {
+		compatible = "st,stm32mp1-pll";
+		reg = <0>;
+		cfg = <2 80 0 0 0 PQR(1,0,0)>;
+		frac = <0x800>;
+	};
+
+	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
+	pll2: st,pll@1 {
+		compatible = "st,stm32mp1-pll";
+		reg = <1>;
+		cfg = <2 65 1 0 0 PQR(1,1,1)>;
+		frac = <0x1400>;
+	};
+
+	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
+	pll3: st,pll@2 {
+		compatible = "st,stm32mp1-pll";
+		reg = <2>;
+		cfg = <1 33 1 16 36 PQR(1,1,1)>;
+		frac = <0x1a04>;
+	};
+
+	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
+	pll4: st,pll@3 {
+		compatible = "st,stm32mp1-pll";
+		reg = <3>;
+		cfg = <3 98 5 7 7 PQR(1,1,1)>;
+	};
+};
+
+&rng1 {
+	status = "okay";
+};
+
+&rtc {
+	status = "okay";
+};
+
+&sdmmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>;
+	non-removable;
+	no-sd;
+	no-sdio;
+	st,neg-edge;
+	bus-width = <8>;
+	vmmc-supply = <&v3v3>;
+	vqmmc-supply = <&vdd>;
+	mmc-ddr-3_3v;
+	status = "okay";
+};
diff --git a/fdts/stm32mp157c-odyssey.dts b/fdts/stm32mp157c-odyssey.dts
new file mode 100644
index 0000000..03800f9
--- /dev/null
+++ b/fdts/stm32mp157c-odyssey.dts
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2019, STMicroelectronics. All Rights Reserved.
+ * Copyright (C) 2021, Grzegorz Szymaszek.
+ *
+ * SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+ */
+
+/dts-v1/;
+
+#include "stm32mp157c-odyssey-som.dtsi"
+
+/ {
+	model = "Seeed Studio Odyssey-STM32MP157C Board";
+	compatible = "seeed,stm32mp157c-odyssey",
+		     "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
+
+	aliases {
+		serial0 = &uart4;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&sdmmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_b4_pins_a>;
+	disable-wp;
+	st,neg-edge;
+	bus-width = <4>;
+	vmmc-supply = <&v3v3>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart4_pins_a>;
+	status = "okay";
+};
diff --git a/include/common/fdt_wrappers.h b/include/common/fdt_wrappers.h
index a571092..e8b3933 100644
--- a/include/common/fdt_wrappers.h
+++ b/include/common/fdt_wrappers.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -24,6 +24,8 @@
 			  unsigned int cells, uint32_t *value);
 int fdtw_read_string(const void *dtb, int node, const char *prop,
 		char *str, size_t size);
+int fdtw_read_uuid(const void *dtb, int node, const char *prop,
+		   unsigned int length, uint8_t *uuid);
 int fdtw_write_inplace_cells(void *dtb, int node, const char *prop,
 		unsigned int cells, void *value);
 int fdtw_read_bytes(const void *dtb, int node, const char *prop,
diff --git a/include/common/uuid.h b/include/common/uuid.h
new file mode 100644
index 0000000..5651d0d
--- /dev/null
+++ b/include/common/uuid.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef UUID_H
+#define UUID_H
+
+#define UUID_BYTES_LENGTH	16
+#define UUID_STRING_LENGTH	36
+
+int read_uuid(uint8_t *dest, char *uuid);
+
+#endif /* UUID_H */
diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h
index aa9158c..fbe07da 100644
--- a/include/dt-bindings/interrupt-controller/arm-gic.h
+++ b/include/dt-bindings/interrupt-controller/arm-gic.h
@@ -1,5 +1,8 @@
-/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
 /*
+ * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
  * This header provides constants for the ARM GIC.
  */
 
@@ -18,4 +21,9 @@
 #define IRQ_TYPE_LEVEL_HIGH	4
 #define IRQ_TYPE_LEVEL_LOW	8
 
+/*
+ * Interrupt specifier cell 2.
+ */
+#define GIC_CPU_MASK_RAW(x) ((x) << 8)
+
 #endif
diff --git a/include/lib/cpus/aarch64/cortex_makalu_elp.h b/include/lib/cpus/aarch64/cortex_makalu_elp_arm.h
similarity index 61%
rename from include/lib/cpus/aarch64/cortex_makalu_elp.h
rename to include/lib/cpus/aarch64/cortex_makalu_elp_arm.h
index 4a16996..a0d788e 100644
--- a/include/lib/cpus/aarch64/cortex_makalu_elp.h
+++ b/include/lib/cpus/aarch64/cortex_makalu_elp_arm.h
@@ -4,20 +4,20 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef CORTEX_MAKALU_ELP_H
-#define CORTEX_MAKALU_ELP_H
+#ifndef CORTEX_MAKALU_ELP_ARM_H
+#define CORTEX_MAKALU_ELP_ARM_H
 
-#define CORTEX_MAKALU_ELP_MIDR					U(0x410FD4E0)
+#define CORTEX_MAKALU_ELP_ARM_MIDR				U(0x410FD4E0)
 
 /*******************************************************************************
  * CPU Extended Control register specific definitions
  ******************************************************************************/
-#define CORTEX_MAKALU_ELP_CPUECTLR_EL1				S3_0_C15_C1_4
+#define CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1			S3_0_C15_C1_4
 
 /*******************************************************************************
  * CPU Power Control register specific definitions
  ******************************************************************************/
-#define CORTEX_MAKALU_ELP_CPUPWRCTLR_EL1			S3_0_C15_C2_7
-#define CORTEX_MAKALU_ELP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
+#define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1			S3_0_C15_C2_7
+#define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT	U(1)
 
-#endif /* CORTEX_MAKALU_ELP_H */
+#endif /* CORTEX_MAKALU_ELP_ARM_H */
diff --git a/include/lib/cpus/aarch64/qemu_max.h b/include/lib/cpus/aarch64/qemu_max.h
new file mode 100644
index 0000000..14da170
--- /dev/null
+++ b/include/lib/cpus/aarch64/qemu_max.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QEMU_MAX_H
+#define QEMU_MAX_H
+
+#include <lib/utils_def.h>
+
+/*
+ *  QEMU MAX midr for revision 0
+ *  00   - Reserved for software use
+ *  0    - Variant
+ *  F    - Architectural features identified in ID_* registers
+ *  051  - 'Q', in a 12-bit field.
+ *  0    - Revision
+ */
+#define QEMU_MAX_MIDR		U(0x000F0510)
+
+#endif /* QEMU_MAX_H */
diff --git a/include/plat/arm/board/common/board_css_def.h b/include/plat/arm/board/common/board_css_def.h
index b79e0d5..775d034 100644
--- a/include/plat/arm/board/common/board_css_def.h
+++ b/include/plat/arm/board/common/board_css_def.h
@@ -44,8 +44,8 @@
 #define MAX_IO_HANDLES			4
 
 /* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE		V2M_FLASH0_BASE
-#define PLAT_ARM_FIP_MAX_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_FLASH_IMAGE_BASE	V2M_FLASH0_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
 
 #define PLAT_ARM_NVM_BASE		V2M_FLASH0_BASE
 #define PLAT_ARM_NVM_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
diff --git a/include/tools_share/uuid.h b/include/tools_share/uuid.h
index a6891d1..2ced3a3 100644
--- a/include/tools_share/uuid.h
+++ b/include/tools_share/uuid.h
@@ -66,7 +66,6 @@
 union uuid_helper_t {
 	struct uuid uuid_struct;
 	struct efi_guid efi_guid;
-	uint32_t word[4];
 };
 
 /* XXX namespace pollution? */
diff --git a/lib/cpus/aarch64/cortex_makalu_elp.S b/lib/cpus/aarch64/cortex_makalu_elp_arm.S
similarity index 62%
rename from lib/cpus/aarch64/cortex_makalu_elp.S
rename to lib/cpus/aarch64/cortex_makalu_elp_arm.S
index e3a3e9d..fbbf205 100644
--- a/lib/cpus/aarch64/cortex_makalu_elp.S
+++ b/lib/cpus/aarch64/cortex_makalu_elp_arm.S
@@ -7,7 +7,7 @@
 #include <arch.h>
 #include <asm_macros.S>
 #include <common/bl_common.h>
-#include <cortex_makalu_elp.h>
+#include <cortex_makalu_elp_arm.h>
 #include <cpu_macros.S>
 #include <plat_macros.S>
 
@@ -25,33 +25,33 @@
 	 * HW will do the cache maintenance while powering down
 	 * ----------------------------------------------------
 	 */
-func cortex_makalu_elp_core_pwr_dwn
+func cortex_makalu_elp_arm_core_pwr_dwn
 	/* ---------------------------------------------------
 	 * Enable CPU power down bit in power control register
 	 * ---------------------------------------------------
 	 */
-	mrs	x0, CORTEX_MAKALU_ELP_CPUPWRCTLR_EL1
-	orr	x0, x0, #CORTEX_MAKALU_ELP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-	msr	CORTEX_MAKALU_ELP_CPUPWRCTLR_EL1, x0
+	mrs	x0, CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1
+	orr	x0, x0, #CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+	msr	CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1, x0
 	isb
 	ret
-endfunc cortex_makalu_elp_core_pwr_dwn
+endfunc cortex_makalu_elp_arm_core_pwr_dwn
 
 #if REPORT_ERRATA
 /*
  * Errata printing function for Cortex Makalu ELP. Must follow AAPCS.
  */
-func cortex_makalu_elp_errata_report
+func cortex_makalu_elp_arm_errata_report
 	ret
-endfunc cortex_makalu_elp_errata_report
+endfunc cortex_makalu_elp_arm_errata_report
 #endif
 
-func cortex_makalu_elp_reset_func
+func cortex_makalu_elp_arm_reset_func
 	/* Disable speculative loads */
 	msr	SSBS, xzr
 	isb
 	ret
-endfunc cortex_makalu_elp_reset_func
+endfunc cortex_makalu_elp_arm_reset_func
 
 	/* ---------------------------------------------
 	 * This function provides Cortex Makalu ELP-
@@ -62,16 +62,16 @@
 	 * reported.
 	 * ---------------------------------------------
 	 */
-.section .rodata.cortex_makalu_elp_regs, "aS"
-cortex_makalu_elp_regs:  /* The ascii list of register names to be reported */
+.section .rodata.cortex_makalu_elp_arm_regs, "aS"
+cortex_makalu_elp_arm_regs:  /* The ascii list of register names to be reported */
 	.asciz	"cpuectlr_el1", ""
 
-func cortex_makalu_elp_cpu_reg_dump
-	adr	x6, cortex_makalu_elp_regs
-	mrs	x8, CORTEX_MAKALU_ELP_CPUECTLR_EL1
+func cortex_makalu_elp_arm_cpu_reg_dump
+	adr	x6, cortex_makalu_elp_arm_regs
+	mrs	x8, CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1
 	ret
-endfunc cortex_makalu_elp_cpu_reg_dump
+endfunc cortex_makalu_elp_arm_cpu_reg_dump
 
-declare_cpu_ops cortex_makalu_elp, CORTEX_MAKALU_ELP_MIDR, \
-	cortex_makalu_elp_reset_func, \
-	cortex_makalu_elp_core_pwr_dwn
+declare_cpu_ops cortex_makalu_elp_arm, CORTEX_MAKALU_ELP_ARM_MIDR, \
+	cortex_makalu_elp_arm_reset_func, \
+	cortex_makalu_elp_arm_core_pwr_dwn
diff --git a/lib/cpus/aarch64/qemu_max.S b/lib/cpus/aarch64/qemu_max.S
new file mode 100644
index 0000000..8948fda
--- /dev/null
+++ b/lib/cpus/aarch64/qemu_max.S
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch.h>
+#include <asm_macros.S>
+#include <cpu_macros.S>
+#include <qemu_max.h>
+
+func qemu_max_core_pwr_dwn
+	/* ---------------------------------------------
+	 * Disable the Data Cache.
+	 * ---------------------------------------------
+	 */
+	mrs	x1, sctlr_el3
+	bic	x1, x1, #SCTLR_C_BIT
+	msr	sctlr_el3, x1
+	isb
+
+	/* ---------------------------------------------
+	 * Flush L1 cache to L2.
+	 * ---------------------------------------------
+	 */
+	mov	x18, lr
+	mov	x0, #DCCISW
+	bl	dcsw_op_level1
+	mov	lr, x18
+	ret
+endfunc qemu_max_core_pwr_dwn
+
+func qemu_max_cluster_pwr_dwn
+	/* ---------------------------------------------
+	 * Disable the Data Cache.
+	 * ---------------------------------------------
+	 */
+	mrs	x1, sctlr_el3
+	bic	x1, x1, #SCTLR_C_BIT
+	msr	sctlr_el3, x1
+	isb
+
+	/* ---------------------------------------------
+	 * Flush all caches to PoC.
+	 * ---------------------------------------------
+	 */
+	mov	x0, #DCCISW
+	b	dcsw_op_all
+endfunc qemu_max_cluster_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for QEMU "max". Must follow AAPCS.
+ */
+func qemu_max_errata_report
+	ret
+endfunc qemu_max_errata_report
+#endif
+
+	/* ---------------------------------------------
+	 * This function provides cpu specific
+	 * register information for crash reporting.
+	 * It needs to return with x6 pointing to
+	 * a list of register names in ascii and
+	 * x8 - x15 having values of registers to be
+	 * reported.
+	 * ---------------------------------------------
+	 */
+.section .rodata.qemu_max_regs, "aS"
+qemu_max_regs:  /* The ascii list of register names to be reported */
+	.asciz	"" /* no registers to report */
+
+func qemu_max_cpu_reg_dump
+	adr	x6, qemu_max_regs
+	ret
+endfunc qemu_max_cpu_reg_dump
+
+
+/* cpu_ops for QEMU MAX */
+declare_cpu_ops qemu_max, QEMU_MAX_MIDR, CPU_NO_RESET_FUNC, \
+	qemu_max_core_pwr_dwn, \
+	qemu_max_cluster_pwr_dwn
diff --git a/licenses/LICENSE.MIT b/licenses/LICENSE.MIT
new file mode 100644
index 0000000..8aa2645
--- /dev/null
+++ b/licenses/LICENSE.MIT
@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) [year] [fullname]
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/plat/arm/board/a5ds/include/platform_def.h b/plat/arm/board/a5ds/include/platform_def.h
index 792a754..9f3df1e 100644
--- a/plat/arm/board/a5ds/include/platform_def.h
+++ b/plat/arm/board/a5ds/include/platform_def.h
@@ -315,8 +315,8 @@
 #define MAX_IO_HANDLES			4
 
 /* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE		BOOT_BASE
-#define PLAT_ARM_FIP_MAX_SIZE		(BOOT_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_FLASH_IMAGE_BASE	BOOT_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	(BOOT_SIZE - V2M_FLASH_BLOCK_SIZE)
 
 #define PLAT_ARM_NVM_BASE		BOOT_BASE
 #define PLAT_ARM_NVM_SIZE		(BOOT_SIZE - V2M_FLASH_BLOCK_SIZE)
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index 7ce4ba3..4e38751 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -70,7 +70,7 @@
 				lib/cpus/aarch64/cortex_klein.S		\
 				lib/cpus/aarch64/cortex_matterhorn.S	\
 				lib/cpus/aarch64/cortex_makalu.S	\
-				lib/cpus/aarch64/cortex_makalu_elp.S    \
+				lib/cpus/aarch64/cortex_makalu_elp_arm.S \
 				lib/cpus/aarch64/cortex_a78c.S
 
 # AArch64/AArch32 cores
diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk
index 6db0c00..5cdf1bf 100644
--- a/plat/arm/board/common/board_common.mk
+++ b/plat/arm/board/common/board_common.mk
@@ -33,7 +33,7 @@
 $(warning Development keys support for FVP is deprecated. Use `regs` \
 option instead)
 else
-	$(error "Unsupported ARM_ROTPK_LOCATION value")
+$(error "Unsupported ARM_ROTPK_LOCATION value")
 endif
 
 $(eval $(call add_define,ARM_ROTPK_LOCATION_ID))
diff --git a/plat/arm/board/fvp/fdts/fvp_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
index 074a50a..cad888f 100644
--- a/plat/arm/board/fvp/fdts/fvp_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
@@ -36,11 +36,14 @@
 			id = <SOC_FW_CONFIG_ID>;
 		};
 
+/* If required, SPD should enable loading of trusted OS fw config */
+#if defined(SPD_tspd) || defined(SPD_spmd)
 		tos_fw-config {
 			load-address = <0x0 0x04001500>;
 			max-size = <0xB00>;
 			id = <TOS_FW_CONFIG_ID>;
 		};
+#endif
 
 #if !defined(SPD_spmd)
 		nt_fw-config {
diff --git a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
index fe154e9..14ad5f5 100644
--- a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -48,26 +48,26 @@
 	arm-io_policies {
 		fip-handles {
 			compatible = "arm,io-fip-handle";
-			scp_bl2_uuid = <0x9766fd3d 0x89bee849 0xae5d78a1 0x40608213>;
-			bl31_uuid = <0x47d4086d 0x4cfe9846 0x9b952950 0xcbbd5a00>;
-			bl32_uuid = <0x05d0e189 0x53dc1347 0x8d2b500a 0x4b7a3e38>;
-			bl32_extra1_uuid = <0x0b70c28b 0x2a5a7840 0x9f650a56 0x82738288>;
-			bl32_extra2_uuid = <0x8ea87bb1 0xcfa23f4d 0x85fde7bb 0xa50220d9>;
-			bl33_uuid = <0xd6d0eea7 0xfcead54b 0x97829934 0xf234b6e4>;
-			hw_cfg_uuid = <0x08b8f1d9 0xc9cf9349 0xa9626fbc 0x6b7265cc>;
-			soc_fw_cfg_uuid = <0x9979814b 0x0376fb46 0x8c8e8d26 0x7f7859e0>;
-			tos_fw_cfg_uuid = <0x26257c1a 0xdbc67f47 0x8d96c4c4 0xb0248021>;
-			nt_fw_cfg_uuid = <0x28da9815 0x93e87e44 0xac661aaf 0x801550f9>;
-			t_key_cert_uuid = <0x827ee890 0xf860e411 0xa1b477a7 0x21b4f94c>;
-			scp_fw_key_uuid = <0x024221a1 0xf860e411 0x8d9bf33c 0x0e15a014>;
-			soc_fw_key_uuid = <0x8ab8becc 0xf960e411 0x9ad0eb48 0x22d8dcf8>;
-			tos_fw_key_cert_uuid = <0x9477d603 0xfb60e411 0x85ddb710 0x5b8cee04>;
-			nt_fw_key_cert_uuid = <0x8ad5832a 0xfb60e411 0x8aafdf30 0xbbc49859>;
-			scp_fw_content_cert_uuid = <0x44be6f04 0x5e63e411 0xb28b73d8 0xeaae9656>;
-			soc_fw_content_cert_uuid = <0xe2b20c20 0x5e63e411 0x9ce8abcc 0xf92bb666>;
-			tos_fw_content_cert_uuid = <0xa49f4411 0x5e63e411 0x87283f05 0x722af33d>;
-			nt_fw_content_cert_uuid = <0x8ec4c1f3 0x5d63e411 0xa7a987ee 0x40b23fa7>;
-			sp_content_cert_uuid = <0x776dfd44 0x86974c3b 0x91ebc13e 0x025a2a6f>;
+			scp_bl2_uuid = "9766fd3d-89be-e849-ae5d-78a140608213";
+			bl31_uuid = "47d4086d-4cfe-9846-9b95-2950cbbd5a00";
+			bl32_uuid = "05d0e189-53dc-1347-8d2b-500a4b7a3e38";
+			bl32_extra1_uuid = "0b70c28b-2a5a-7840-9f65-0a5682738288";
+			bl32_extra2_uuid = "8ea87bb1-cfa2-3f4d-85fd-e7bba50220d9";
+			bl33_uuid = "d6d0eea7-fcea-d54b-9782-9934f234b6e4";
+			hw_cfg_uuid = "08b8f1d9-c9cf-9349-a962-6fbc6b7265cc";
+			soc_fw_cfg_uuid = "9979814b-0376-fb46-8c8e-8d267f7859e0";
+			tos_fw_cfg_uuid = "26257c1a-dbc6-7f47-8d96-c4c4b0248021";
+			nt_fw_cfg_uuid = "28da9815-93e8-7e44-ac66-1aaf801550f9";
+			t_key_cert_uuid = "827ee890-f860-e411-a1b4-77a721b4f94c";
+			scp_fw_key_uuid = "024221a1-f860-e411-8d9b-f33c0e15a014";
+			soc_fw_key_uuid = "8ab8becc-f960-e411-9ad0-eb4822d8dcf8";
+			tos_fw_key_cert_uuid = "9477d603-fb60-e411-85dd-b7105b8cee04";
+			nt_fw_key_cert_uuid = "8ad5832a-fb60-e411-8aaf-df30bbc49859";
+			scp_fw_content_cert_uuid = "44be6f04-5e63-e411-b28b-73d8eaae9656";
+			soc_fw_content_cert_uuid = "e2b20c20-5e63-e411-9ce8-abccf92bb666";
+			tos_fw_content_cert_uuid = "a49f4411-5e63-e411-8728-3f05722af33d";
+			nt_fw_content_cert_uuid = "8ec4c1f3-5d63-e411-a7a9-87ee40b23fa7";
+			sp_content_cert_uuid = "776dfd44-8697-4c3b-91eb-c13e025a2a6f";
 		};
 	};
 #endif /* ARM_IO_IN_DTB */
@@ -76,24 +76,24 @@
 		compatible = "arm,sp";
 #ifdef OPTEE_SP_FW_CONFIG
 		op-tee {
-			uuid = <0x486178e0 0xe7f811e3 0xbc5e0002 0xa5d5c51b>;
+			uuid = "486178e0-e7f8-11e3-bc5e-0002a5d5c51b";
 			load-address = <0x6280000>;
 		};
 #else
 		cactus-primary {
-			uuid = <0xb4b5671e 0x4a904fe1 0xb81ffb13 0xdae1dacb>;
+			uuid = "b4b5671e-4a90-4fe1-b81f-fb13dae1dacb";
 			load-address = <0x7000000>;
 			owner = "SiP";
 		};
 
 		cactus-secondary {
-			uuid = <0xd1582309 0xf02347b9 0x827c4464 0xf5578fc8>;
+			uuid = "d1582309-f023-47b9-827c-4464f5578fc8";
 			load-address = <0x7100000>;
 			owner = "Plat";
 		};
 
 		cactus-tertiary {
-			uuid = <0x79b55c73 0x1d8c44b9 0x859361e1 0x770ad8d2>;
+			uuid = "79b55c73-1d8c-44b9-8593-61e1770ad8d2";
 			load-address = <0x7200000>;
 		};
 #endif
diff --git a/plat/arm/board/fvp/fvp_err.c b/plat/arm/board/fvp/fvp_err.c
index c9b2090..2928b3a 100644
--- a/plat/arm/board/fvp/fvp_err.c
+++ b/plat/arm/board/fvp/fvp_err.c
@@ -24,8 +24,8 @@
 	case -EAUTH:
 		/* Image load or authentication error. Erase the ToC */
 		INFO("Erasing FIP ToC from flash...\n");
-		(void)nor_unlock(PLAT_ARM_FIP_BASE);
-		ret = nor_word_program(PLAT_ARM_FIP_BASE, 0);
+		(void)nor_unlock(PLAT_ARM_FLASH_IMAGE_BASE);
+		ret = nor_word_program(PLAT_ARM_FLASH_IMAGE_BASE, 0);
 		if (ret != 0) {
 			ERROR("Cannot erase ToC\n");
 		} else {
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 8defcf8..c95f27d 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -185,8 +185,8 @@
 #define MAX_IO_HANDLES			4
 
 /* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE		V2M_FLASH0_BASE
-#define PLAT_ARM_FIP_MAX_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_FLASH_IMAGE_BASE	V2M_FLASH0_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
 
 #define PLAT_ARM_NVM_BASE		V2M_FLASH0_BASE
 #define PLAT_ARM_NVM_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 20d80ed..b58a0d2 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -134,7 +134,7 @@
 					lib/cpus/aarch64/cortex_klein.S		\
 					lib/cpus/aarch64/cortex_matterhorn.S	\
 					lib/cpus/aarch64/cortex_makalu.S	\
-					lib/cpus/aarch64/cortex_makalu_elp.S	\
+					lib/cpus/aarch64/cortex_makalu_elp_arm.S \
 					lib/cpus/aarch64/cortex_a65.S		\
 					lib/cpus/aarch64/cortex_a65ae.S		\
 					lib/cpus/aarch64/cortex_a78c.S
diff --git a/plat/arm/board/fvp_ve/include/platform_def.h b/plat/arm/board/fvp_ve/include/platform_def.h
index 3f2fcee..bd8ef6a 100644
--- a/plat/arm/board/fvp_ve/include/platform_def.h
+++ b/plat/arm/board/fvp_ve/include/platform_def.h
@@ -303,8 +303,8 @@
 #define MAX_IO_HANDLES			4
 
 /* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE		V2M_FLASH1_BASE
-#define PLAT_ARM_FIP_MAX_SIZE		(V2M_FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_FLASH_IMAGE_BASE	V2M_FLASH1_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	(V2M_FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
 
 #define PLAT_ARM_NVM_BASE		V2M_FLASH1_BASE
 #define PLAT_ARM_NVM_SIZE		(V2M_FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
diff --git a/plat/arm/board/rde1edge/platform.mk b/plat/arm/board/rde1edge/platform.mk
index 53074f4..0f9dd49 100644
--- a/plat/arm/board/rde1edge/platform.mk
+++ b/plat/arm/board/rde1edge/platform.mk
@@ -58,4 +58,9 @@
    ${CSS_SGI_CHIP_COUNT}.")
 endif
 
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-E1-Edge should always be 0, \
+     currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
+
 override CTX_INCLUDE_AARCH32_REGS	:= 0
diff --git a/plat/arm/board/rdn1edge/platform.mk b/plat/arm/board/rdn1edge/platform.mk
index d65854f..22ab312 100644
--- a/plat/arm/board/rdn1edge/platform.mk
+++ b/plat/arm/board/rdn1edge/platform.mk
@@ -65,4 +65,9 @@
    set to ${CSS_SGI_CHIP_COUNT}.")
 endif
 
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-N1-Edge should always be 0, \
+     currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
+
 override CTX_INCLUDE_AARCH32_REGS	:= 0
diff --git a/plat/arm/board/rdn2/include/platform_def.h b/plat/arm/board/rdn2/include/platform_def.h
index 3f753f7..30a0c5c 100644
--- a/plat/arm/board/rdn2/include/platform_def.h
+++ b/plat/arm/board/rdn2/include/platform_def.h
@@ -11,7 +11,12 @@
 
 #include <sgi_soc_platform_def_v2.h>
 
+#if (CSS_SGI_PLATFORM_VARIANT == 1)
+#define PLAT_ARM_CLUSTER_COUNT		U(8)
+#else
 #define PLAT_ARM_CLUSTER_COUNT		U(16)
+#endif
+
 #define CSS_SGI_MAX_CPUS_PER_CLUSTER	U(1)
 #define CSS_SGI_MAX_PE_PER_CPU		U(1)
 
@@ -26,7 +31,12 @@
 #define PLAT_ARM_TZC_FILTERS		TZC_400_REGION_ATTR_FILTER_BIT(0)
 
 #define TZC400_OFFSET			UL(0x1000000)
+
+#if (CSS_SGI_PLATFORM_VARIANT == 1)
+#define TZC400_COUNT			U(2)
+#else
 #define TZC400_COUNT			U(8)
+#endif
 
 #define TZC400_BASE(n)			(PLAT_ARM_TZC_BASE + \
 						(n * TZC400_OFFSET))
@@ -60,6 +70,11 @@
 /* GIC related constants */
 #define PLAT_ARM_GICD_BASE		UL(0x30000000)
 #define PLAT_ARM_GICC_BASE		UL(0x2C000000)
+
+#if (CSS_SGI_PLATFORM_VARIANT == 1)
+#define PLAT_ARM_GICR_BASE		UL(0x30100000)
+#else
 #define PLAT_ARM_GICR_BASE		UL(0x301C0000)
+#endif
 
 #endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/rdn2/platform.mk b/plat/arm/board/rdn2/platform.mk
index 03771dc..794f897 100644
--- a/plat/arm/board/rdn2/platform.mk
+++ b/plat/arm/board/rdn2/platform.mk
@@ -58,3 +58,10 @@
 
 override CTX_INCLUDE_AARCH32_REGS	:= 0
 override ENABLE_AMU			:= 1
+
+RD_N2_VARIANTS	:= 0 1
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),\
+	$(filter $(CSS_SGI_PLATFORM_VARIANT),$(RD_N2_VARIANTS)))
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-N2 should be 0 or 1, currently set \
+     to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
diff --git a/plat/arm/board/rdn2/rdn2_topology.c b/plat/arm/board/rdn2/rdn2_topology.c
index 5c2e287..cad6c37 100644
--- a/plat/arm/board/rdn2/rdn2_topology.c
+++ b/plat/arm/board/rdn2/rdn2_topology.c
@@ -20,6 +20,7 @@
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+#if (CSS_SGI_PLATFORM_VARIANT == 0)
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
@@ -28,6 +29,7 @@
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+#endif
 };
 
 /*******************************************************************************
@@ -51,6 +53,7 @@
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
+#if (CSS_SGI_PLATFORM_VARIANT == 0)
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
@@ -59,4 +62,5 @@
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)),
+#endif
 };
diff --git a/plat/arm/board/rdv1/platform.mk b/plat/arm/board/rdv1/platform.mk
index 2ffd139..1ae85de 100644
--- a/plat/arm/board/rdv1/platform.mk
+++ b/plat/arm/board/rdv1/platform.mk
@@ -58,3 +58,8 @@
 
 override CTX_INCLUDE_AARCH32_REGS	:= 0
 override ENABLE_AMU			:= 1
+
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-V1 should always be 0, \
+     currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
diff --git a/plat/arm/board/rdv1mc/platform.mk b/plat/arm/board/rdv1mc/platform.mk
index fb05793..06a2047 100644
--- a/plat/arm/board/rdv1mc/platform.mk
+++ b/plat/arm/board/rdv1mc/platform.mk
@@ -68,3 +68,8 @@
 $(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
 
 override CTX_INCLUDE_AARCH32_REGS	:= 0
+
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-V1-MC should always be 0, \
+     currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
diff --git a/plat/arm/board/sgi575/platform.mk b/plat/arm/board/sgi575/platform.mk
index 89abcfe..0761b77 100644
--- a/plat/arm/board/sgi575/platform.mk
+++ b/plat/arm/board/sgi575/platform.mk
@@ -58,3 +58,8 @@
  $(error  "Chip count for SGI575 should be 1, currently set to \
    ${CSS_SGI_CHIP_COUNT}.")
 endif
+
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
+ $(error "CSS_SGI_PLATFORM_VARIANT for SGI575 should always be 0,\
+     currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
diff --git a/plat/arm/board/sgm775/platform.mk b/plat/arm/board/sgm775/platform.mk
index a649939..f8df1a7 100644
--- a/plat/arm/board/sgm775/platform.mk
+++ b/plat/arm/board/sgm775/platform.mk
@@ -4,6 +4,8 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
+$(warning Platform ${PLAT} is deprecated. Some of the features might not work as expected)
+
 include plat/arm/css/sgm/sgm-common.mk
 
 SGM775_BASE= plat/arm/board/sgm775
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 232d562..2ae26da 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -222,7 +222,8 @@
 
 DYN_CFG_SOURCES		+=	plat/arm/common/arm_dyn_cfg.c		\
 				plat/arm/common/arm_dyn_cfg_helpers.c	\
-				common/fdt_wrappers.c
+				common/fdt_wrappers.c			\
+				common/uuid.c
 
 BL1_SOURCES		+=	${DYN_CFG_SOURCES}
 BL2_SOURCES		+=	${DYN_CFG_SOURCES}
@@ -302,6 +303,7 @@
 ifeq (${SPD},spmd)
 BL31_SOURCES		+=	plat/common/plat_spmd_manifest.c	\
 				common/fdt_wrappers.c			\
+				common/uuid.c				\
 				${LIBFDT_SRCS}
 
 endif
diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c
index 6b3a611..30473be 100644
--- a/plat/arm/common/arm_dyn_cfg.c
+++ b/plat/arm/common/arm_dyn_cfg.c
@@ -208,10 +208,7 @@
 			HW_CONFIG_ID,
 			SOC_FW_CONFIG_ID,
 			NT_FW_CONFIG_ID,
-#if defined(SPD_tspd) || defined(SPD_spmd)
-			/* tos_fw_config is only present for TSPD/SPMD */
 			TOS_FW_CONFIG_ID
-#endif
 	};
 
 	const struct dyn_cfg_dtb_info_t *dtb_info;
diff --git a/plat/arm/common/fconf/arm_fconf_io.c b/plat/arm/common/fconf/arm_fconf_io.c
index 48286c2..4a64cb8 100644
--- a/plat/arm/common/fconf/arm_fconf_io.c
+++ b/plat/arm/common/fconf/arm_fconf_io.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -18,8 +18,8 @@
 #include <platform_def.h>
 
 const io_block_spec_t fip_block_spec = {
-	.offset = PLAT_ARM_FIP_BASE,
-	.length = PLAT_ARM_FIP_MAX_SIZE
+	.offset = PLAT_ARM_FLASH_IMAGE_BASE,
+	.length = PLAT_ARM_FLASH_IMAGE_MAX_SIZE
 };
 
 const io_uuid_spec_t arm_uuid_spec[MAX_NUMBER_IDS] = {
@@ -249,7 +249,6 @@
 {
 	int err, node;
 	unsigned int i;
-	unsigned int j;
 
 	union uuid_helper_t uuid_helper;
 	io_uuid_spec_t *uuid_ptr;
@@ -268,26 +267,26 @@
 	/* Locate the uuid cells and read the value for all the load info uuid */
 	for (i = 0; i < FCONF_ARM_IO_UUID_NUMBER; i++) {
 		uuid_ptr = pool_alloc(&fconf_arm_uuids_pool);
-		err = fdt_read_uint32_array(dtb, node, load_info[i].name,
-					    4, uuid_helper.word);
+		err = fdtw_read_uuid(dtb, node, load_info[i].name, 16,
+				     (uint8_t *)&uuid_helper);
 		if (err < 0) {
 			WARN("FCONF: Read cell failed for %s\n", load_info[i].name);
 			return err;
 		}
 
-		/* Convert uuid from big endian to little endian */
-		for (j = 0U; j < 4U; j++) {
-			uuid_helper.word[j] =
-				((uuid_helper.word[j] >> 24U) & 0xff) |
-				((uuid_helper.word[j] << 8U) & 0xff0000) |
-				((uuid_helper.word[j] >> 8U) & 0xff00) |
-				((uuid_helper.word[j] << 24U) & 0xff000000);
-		}
-
-		VERBOSE("FCONF: arm-io_policies.%s cell found with value = 0x%x 0x%x 0x%x 0x%x\n",
+		VERBOSE("FCONF: arm-io_policies.%s cell found with value = "
+			"%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x\n",
 			load_info[i].name,
-			uuid_helper.word[0], uuid_helper.word[1],
-			uuid_helper.word[2], uuid_helper.word[3]);
+			uuid_helper.uuid_struct.time_low[0], uuid_helper.uuid_struct.time_low[1],
+			uuid_helper.uuid_struct.time_low[2], uuid_helper.uuid_struct.time_low[3],
+			uuid_helper.uuid_struct.time_mid[0], uuid_helper.uuid_struct.time_mid[1],
+			uuid_helper.uuid_struct.time_hi_and_version[0],
+			uuid_helper.uuid_struct.time_hi_and_version[1],
+			uuid_helper.uuid_struct.clock_seq_hi_and_reserved,
+			uuid_helper.uuid_struct.clock_seq_low,
+			uuid_helper.uuid_struct.node[0], uuid_helper.uuid_struct.node[1],
+			uuid_helper.uuid_struct.node[2], uuid_helper.uuid_struct.node[3],
+			uuid_helper.uuid_struct.node[4], uuid_helper.uuid_struct.node[5]);
 
 		uuid_ptr->uuid = uuid_helper.uuid_struct;
 		policies[load_info[i].image_id].image_spec = (uintptr_t)uuid_ptr;
diff --git a/plat/arm/common/fconf/arm_fconf_sp.c b/plat/arm/common/fconf/arm_fconf_sp.c
index 7950e7f..552393c 100644
--- a/plat/arm/common/fconf/arm_fconf_sp.c
+++ b/plat/arm/common/fconf/arm_fconf_sp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -37,7 +37,6 @@
 	const unsigned int plat_start = SP_PKG5_ID;
 	unsigned int plat_index = plat_start;
 	const unsigned int plat_end = plat_start + MAX_SP_IDS / 2;
-	unsigned int j;
 
 	/* As libfdt use void *, we can't avoid this cast */
 	const void *dtb = (void *)config;
@@ -59,29 +58,28 @@
 		}
 
 		/* Read UUID */
-		err = fdt_read_uint32_array(dtb, sp_node, "uuid", 4,
-					    uuid_helper.word);
+		err = fdtw_read_uuid(dtb, sp_node, "uuid", 16,
+				     (uint8_t *)&uuid_helper);
 		if (err < 0) {
 			ERROR("FCONF: cannot read SP uuid\n");
 			return -1;
 		}
 
-		/* Convert uuid from big endian to little endian */
-		for (j = 0U; j < 4U; j++) {
-			uuid_helper.word[j] =
-				((uuid_helper.word[j] >> 24U) & 0xff) |
-				((uuid_helper.word[j] << 8U) & 0xff0000) |
-				((uuid_helper.word[j] >> 8U) & 0xff00) |
-				((uuid_helper.word[j] << 24U) & 0xff000000);
-		}
-
 		arm_sp.uuids[index] = uuid_helper;
-		VERBOSE("FCONF: %s UUID %x-%x-%x-%x load_addr=%lx\n",
+		VERBOSE("FCONF: %s UUID"
+			" %02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x"
+			" load_addr=%lx\n",
 			__func__,
-			uuid_helper.word[0],
-			uuid_helper.word[1],
-			uuid_helper.word[2],
-			uuid_helper.word[3],
+			uuid_helper.uuid_struct.time_low[0], uuid_helper.uuid_struct.time_low[1],
+			uuid_helper.uuid_struct.time_low[2], uuid_helper.uuid_struct.time_low[3],
+			uuid_helper.uuid_struct.time_mid[0], uuid_helper.uuid_struct.time_mid[1],
+			uuid_helper.uuid_struct.time_hi_and_version[0],
+			uuid_helper.uuid_struct.time_hi_and_version[1],
+			uuid_helper.uuid_struct.clock_seq_hi_and_reserved,
+			uuid_helper.uuid_struct.clock_seq_low,
+			uuid_helper.uuid_struct.node[0], uuid_helper.uuid_struct.node[1],
+			uuid_helper.uuid_struct.node[2], uuid_helper.uuid_struct.node[3],
+			uuid_helper.uuid_struct.node[4], uuid_helper.uuid_struct.node[5],
 			arm_sp.load_addr[index]);
 
 		/* Read Load address */
diff --git a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h
index 103dd9a..28916f8 100644
--- a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h
+++ b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h
@@ -184,8 +184,8 @@
 #define MAX_IO_HANDLES			U(4)
 
 /* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE		V2M_FLASH0_BASE
-#define PLAT_ARM_FIP_MAX_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_FLASH_IMAGE_BASE	V2M_FLASH0_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
 
 #define PLAT_ARM_NVM_BASE		V2M_FLASH0_BASE
 #define PLAT_ARM_NVM_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
diff --git a/plat/arm/css/sgi/include/sgi_variant.h b/plat/arm/css/sgi/include/sgi_variant.h
index ecf6d93..0062b97 100644
--- a/plat/arm/css/sgi/include/sgi_variant.h
+++ b/plat/arm/css/sgi/include/sgi_variant.h
@@ -20,6 +20,9 @@
 /* SID Version values for RD-N2 */
 #define RD_N2_SID_VER_PART_NUM			0x07B7
 
+/* SID Version values for RD-N2 variants */
+#define RD_N2_CFG1_SID_VER_PART_NUM		0x07B6
+
 /* Structure containing SGI platform variant information */
 typedef struct sgi_platform_info {
 	unsigned int platform_id;	/* Part Number of the platform */
diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk
index 615f53d..1e2054f 100644
--- a/plat/arm/css/sgi/sgi-common.mk
+++ b/plat/arm/css/sgi/sgi-common.mk
@@ -18,6 +18,8 @@
 
 CSS_SGI_CHIP_COUNT		:=	1
 
+CSS_SGI_PLATFORM_VARIANT	:=	0
+
 INTERCONNECT_SOURCES	:=	${CSS_ENT_BASE}/sgi_interconnect.c
 
 PLAT_INCLUDES		+=	-I${CSS_ENT_BASE}/include
@@ -57,6 +59,8 @@
 
 $(eval $(call add_define,CSS_SGI_CHIP_COUNT))
 
+$(eval $(call add_define,CSS_SGI_PLATFORM_VARIANT))
+
 override CSS_LOAD_SCP_IMAGES	:=	0
 override NEED_BL2U		:=	no
 override ARM_BL31_IN_DRAM	:=	1
diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c
index e8238ba..541689b 100644
--- a/plat/arm/css/sgi/sgi_bl31_setup.c
+++ b/plat/arm/css/sgi/sgi_bl31_setup.c
@@ -75,7 +75,8 @@
 {
 	if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
 		sgi_plat_info.platform_id == RD_V1_SID_VER_PART_NUM ||
-		sgi_plat_info.platform_id == RD_N2_SID_VER_PART_NUM) {
+		sgi_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
+		sgi_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM) {
 		if (channel_id >= ARRAY_SIZE(plat_rd_scmi_info))
 			panic();
 		return &plat_rd_scmi_info[channel_id];
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c
new file mode 100644
index 0000000..937774c
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2017-2021 NXP
+ * Copyright 2021 Arm
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <common/desc_image_load.h>
+#include <context.h>
+#include <drivers/console.h>
+#include <drivers/generic_delay_timer.h>
+#include <drivers/mmc.h>
+#include <lib/mmio.h>
+#include <lib/optee_utils.h>
+#include <lib/utils.h>
+#include <stdbool.h>
+#include <tbbr_img_def.h>
+
+#include <imx_aipstz.h>
+#include <imx_csu.h>
+#include <imx_uart.h>
+#include <imx_usdhc.h>
+#include <plat/common/platform.h>
+
+#include "imx8mm_private.h"
+#include "platform_def.h"
+
+static const struct aipstz_cfg aipstz[] = {
+	{IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+	{IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+	{IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+	{IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+	{0},
+};
+
+static void imx8mm_usdhc_setup(void)
+{
+	imx_usdhc_params_t params;
+	struct mmc_device_info info;
+
+	params.reg_base = PLAT_IMX8MM_BOOT_MMC_BASE;
+	/*
+	   The imx8mm SD Card Speed modes for USDHC2
+	   +--------------+--------------------+--------------+--------------+
+	   |Bus Speed Mode|Max. Clock Frequency|Max. Bus Speed|Signal Voltage|
+	   +--------------+--------------------+--------------+--------------+
+	   |Default Speed | 25 MHz             | 12.5 MB/s    | 3.3V         |
+	   |High Speed    | 50 MHz             | 25 MB/s      | 3.3V         |
+	   +--------------+--------------------+--------------+--------------+
+
+	   We pick 50 Mhz here for High Speed access.
+	*/
+	params.clk_rate = 50000000;
+	params.bus_width = MMC_BUS_WIDTH_1;
+	params.flags = 0;
+	info.mmc_dev_type = MMC_IS_SD;
+	info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
+	imx_usdhc_init(&params, &info);
+}
+
+void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
+				  u_register_t arg3, u_register_t arg4)
+{
+	int i;
+	static console_t console;
+
+	/* enable CSU NS access permission */
+	for (i = 0; i < MAX_CSU_NUM; i++) {
+		mmio_write_32(IMX_CSU_BASE + i * 4, CSU_CSL_OPEN_ACCESS);
+	}
+
+	/* config the aips access permission */
+	imx_aipstz_init(aipstz);
+
+	console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
+		IMX_CONSOLE_BAUDRATE, &console);
+
+	generic_delay_timer_init();
+
+	/* select the CKIL source to 32K OSC */
+	mmio_write_32(0x30360124, 0x1);
+
+	imx8mm_usdhc_setup();
+
+	/* Open handles to a FIP image */
+	plat_imx8mm_io_setup();
+}
+
+void bl2_el3_plat_arch_setup(void)
+{
+}
+
+void bl2_platform_setup(void)
+{
+}
+
+int bl2_plat_handle_post_image_load(unsigned int image_id)
+{
+	int err = 0;
+	bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
+	bl_mem_params_node_t *pager_mem_params = NULL;
+	bl_mem_params_node_t *paged_mem_params = NULL;
+
+	assert(bl_mem_params);
+
+	switch (image_id) {
+	case BL32_IMAGE_ID:
+		pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
+		assert(pager_mem_params);
+
+		paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
+		assert(paged_mem_params);
+
+		err = parse_optee_header(&bl_mem_params->ep_info,
+					 &pager_mem_params->image_info,
+					 &paged_mem_params->image_info);
+		if (err != 0) {
+			WARN("OPTEE header parse error.\n");
+		}
+
+		break;
+	default:
+		/* Do nothing in default case */
+		break;
+	}
+
+	return err;
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+	return COUNTER_FREQUENCY;
+}
+
+void bl2_plat_runtime_setup(void)
+{
+	return;
+}
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl2_mem_params_desc.c b/plat/imx/imx8m/imx8mm/imx8mm_bl2_mem_params_desc.c
new file mode 100644
index 0000000..e44345d
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl2_mem_params_desc.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <common/desc_image_load.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+static bl_mem_params_node_t bl2_mem_params_descs[] = {
+	{
+		.image_id = BL31_IMAGE_ID,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+				      entry_point_info_t,
+				      SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.pc = BL31_BASE,
+		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+					DISABLE_ALL_EXCEPTIONS),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t,
+				      IMAGE_ATTRIB_PLAT_SETUP),
+		.image_info.image_base = BL31_BASE,
+		.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
+	{
+		.image_id = BL32_IMAGE_ID,
+
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+				      entry_point_info_t,
+				      SECURE | EXECUTABLE),
+		.ep_info.pc = BL32_BASE,
+
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
+				      image_info_t, 0),
+
+		.image_info.image_base = BL32_BASE,
+		.image_info.image_max_size = BL32_SIZE,
+
+		.next_handoff_image_id = BL33_IMAGE_ID,
+	},
+	{
+		.image_id = BL32_EXTRA1_IMAGE_ID,
+
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+				      entry_point_info_t,
+				      SECURE | NON_EXECUTABLE),
+
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
+				      image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		.image_info.image_base = BL32_BASE,
+		.image_info.image_max_size =  BL32_SIZE,
+
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
+	{
+		/* This is a zero sized image so we don't set base or size */
+		.image_id = BL32_EXTRA2_IMAGE_ID,
+
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+				      VERSION_2, entry_point_info_t,
+				      SECURE | NON_EXECUTABLE),
+
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+				      VERSION_2, image_info_t,
+				      IMAGE_ATTRIB_SKIP_LOADING),
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
+	{
+		.image_id = BL33_IMAGE_ID,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+				      entry_point_info_t,
+				      NON_SECURE | EXECUTABLE),
+		# ifdef PRELOADED_BL33_BASE
+			.ep_info.pc = PLAT_NS_IMAGE_OFFSET,
+
+			SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+					      VERSION_2, image_info_t,
+					      IMAGE_ATTRIB_SKIP_LOADING),
+		# else
+			.ep_info.pc = PLAT_NS_IMAGE_OFFSET,
+
+			SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+					      VERSION_2, image_info_t, 0),
+			.image_info.image_base = PLAT_NS_IMAGE_OFFSET,
+			.image_info.image_max_size = PLAT_NS_IMAGE_SIZE,
+		# endif /* PRELOADED_BL33_BASE */
+
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	}
+};
+
+REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs);
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_rotpk.S b/plat/imx/imx8m/imx8mm/imx8mm_rotpk.S
new file mode 100644
index 0000000..544ee8a
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/imx8mm_rotpk.S
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+	.global imx8mm_rotpk_hash
+	.global imx8mm_rotpk_hash_end
+imx8mm_rotpk_hash:
+	/* DER header */
+	.byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48
+	.byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20
+	/* SHA256 */
+	.incbin ROTPK_HASH
+imx8mm_rotpk_hash_end:
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_trusted_boot.c b/plat/imx/imx8m/imx8mm/imx8mm_trusted_boot.c
new file mode 100644
index 0000000..a4384d7
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/imx8mm_trusted_boot.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/common/platform.h>
+
+extern char imx8mm_rotpk_hash[], imx8mm_rotpk_hash_end[];
+
+int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
+			unsigned int *flags)
+{
+	*key_ptr = imx8mm_rotpk_hash;
+	*key_len = imx8mm_rotpk_hash_end - imx8mm_rotpk_hash;
+	*flags = ROTPK_IS_HASH;
+
+	return 0;
+}
+
+int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
+{
+	*nv_ctr = 0;
+
+	return 0;
+}
+
+int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
+{
+	return 1;
+}
+
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+	return get_mbedtls_heap_helper(heap_addr, heap_size);
+}
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index ac636fa..1863233 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -6,7 +6,9 @@
 
 PLAT_INCLUDES		:=	-Iplat/imx/common/include		\
 				-Iplat/imx/imx8m/include		\
-				-Iplat/imx/imx8m/imx8mm/include
+				-Iplat/imx/imx8m/imx8mm/include		\
+				-Idrivers/imx/usdhc			\
+				-Iinclude/common/tbbr
 
 # Include GICv3 driver files
 include drivers/arm/gic/v3/gicv3.mk
@@ -39,6 +41,94 @@
 				drivers/delay_timer/generic_delay_timer.c	\
 				${IMX_GIC_SOURCES}
 
+ifeq (${NEED_BL2},yes)
+BL2_SOURCES		+=	common/desc_image_load.c			\
+				plat/imx/common/imx8_helpers.S			\
+				plat/imx/common/imx_uart_console.S		\
+				plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c	\
+				plat/imx/imx8m/imx8mm/gpc.c			\
+				plat/imx/imx8m/imx_aipstz.c			\
+				plat/common/plat_psci_common.c			\
+				lib/xlat_tables/aarch64/xlat_tables.c		\
+				lib/xlat_tables/xlat_tables_common.c		\
+				lib/cpus/aarch64/cortex_a53.S			\
+				drivers/delay_timer/delay_timer.c		\
+				drivers/delay_timer/generic_delay_timer.c	\
+				${PLAT_GIC_SOURCES}				\
+				${PLAT_DRAM_SOURCES}				\
+				drivers/mmc/mmc.c				\
+				drivers/io/io_block.c				\
+				drivers/io/io_fip.c				\
+				drivers/io/io_memmap.c				\
+				drivers/io/io_storage.c				\
+				drivers/imx/usdhc/imx_usdhc.c			\
+				plat/imx/imx8m/imx8mm/imx8mm_bl2_mem_params_desc.c	\
+				plat/imx/imx8m/imx8mm/imx8mm_io_storage.c		\
+				plat/imx/imx8m/imx8mm/imx8mm_image_load.c		\
+				lib/optee/optee_utils.c
+endif
+
+# Add the build options to pack BLx images and kernel device tree
+# in the FIP if the platform requires.
+ifneq ($(BL2),)
+RESET_TO_BL31		:=	0
+$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
+endif
+ifneq ($(BL32_EXTRA1),)
+$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
+endif
+ifneq ($(BL32_EXTRA2),)
+$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
+endif
+ifneq ($(HW_CONFIG),)
+$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config))
+endif
+
+ifeq (${NEED_BL2},yes)
+$(eval $(call add_define,NEED_BL2))
+LOAD_IMAGE_V2		:=	1
+# Non-TF Boot ROM
+BL2_AT_EL3		:=	1
+endif
+
+ifneq (${TRUSTED_BOARD_BOOT},0)
+
+include drivers/auth/mbedtls/mbedtls_crypto.mk
+include drivers/auth/mbedtls/mbedtls_x509.mk
+
+AUTH_SOURCES	:=	drivers/auth/auth_mod.c			\
+			drivers/auth/crypto_mod.c		\
+			drivers/auth/img_parser_mod.c		\
+			drivers/auth/tbbr/tbbr_cot_common.c     \
+			drivers/auth/tbbr/tbbr_cot_bl2.c
+
+BL2_SOURCES	+=	${AUTH_SOURCES}					\
+			plat/common/tbbr/plat_tbbr.c			\
+			plat/imx/imx8m/imx8mm/imx8mm_trusted_boot.c	\
+			plat/imx/imx8m/imx8mm/imx8mm_rotpk.S
+
+ROT_KEY             = $(BUILD_PLAT)/rot_key.pem
+ROTPK_HASH          = $(BUILD_PLAT)/rotpk_sha256.bin
+
+$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
+$(eval $(call MAKE_LIB_DIRS))
+
+$(BUILD_PLAT)/bl2/imx8mm_rotpk.o: $(ROTPK_HASH)
+
+certificates: $(ROT_KEY)
+
+$(ROT_KEY): | $(BUILD_PLAT)
+	@echo "  OPENSSL $@"
+	@if [ ! -f $(ROT_KEY) ]; then \
+		openssl genrsa 2048 > $@ 2>/dev/null; \
+	fi
+
+$(ROTPK_HASH): $(ROT_KEY)
+	@echo "  OPENSSL $@"
+	$(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+	openssl dgst -sha256 -binary > $@ 2>/dev/null
+endif
+
 USE_COHERENT_MEM	:=	1
 RESET_TO_BL31		:=	1
 A53_DISABLE_NON_TEMPORAL_HINT := 0
diff --git a/plat/marvell/armada/a3k/a3700/board/pm_src.c b/plat/marvell/armada/a3k/a3700/board/pm_src.c
index d6eca5d..247f73b 100644
--- a/plat/marvell/armada/a3k/a3700/board/pm_src.c
+++ b/plat/marvell/armada/a3k/a3700/board/pm_src.c
@@ -8,7 +8,7 @@
 #include <a3700_pm.h>
 #include <plat_marvell.h>
 
-/* This struct provides the PM wake up src configuration */
+/* This struct provides the PM wake up src configuration for A3720 Development Board */
 static struct pm_wake_up_src_config wake_up_src_cfg = {
 	.wake_up_src_num = 3,
 	.wake_up_src[0] = {
diff --git a/plat/marvell/armada/a3k/common/a3700_common.mk b/plat/marvell/armada/a3k/common/a3700_common.mk
index 8775e89..79097f3 100644
--- a/plat/marvell/armada/a3k/common/a3700_common.mk
+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
@@ -43,8 +43,6 @@
 BL1_SOURCES		+=	$(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
 				lib/cpus/aarch64/cortex_a53.S
 
-BL31_PORTING_SOURCES	:=	$(PLAT_FAMILY_BASE)/$(PLAT)/board/pm_src.c
-
 MARVELL_DRV		:=	$(MARVELL_DRV_BASE)/comphy/phy-comphy-3700.c
 
 BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a53.S		\
@@ -61,7 +59,6 @@
 				$(MARVELL_COMMON_BASE)/marvell_gicv3.c	\
 				$(MARVELL_GIC_SOURCES)			\
 				drivers/arm/cci/cci.c			\
-				$(BL31_PORTING_SOURCES)			\
 				$(PLAT_COMMON_BASE)/a3700_sip_svc.c	\
 				$(MARVELL_DRV)
 
@@ -69,6 +66,10 @@
 BL31_SOURCES		+=	$(PLAT_COMMON_BASE)/cm3_system_reset.c
 endif
 
+ifeq ($(A3720_DB_PM_WAKEUP_SRC),1)
+BL31_SOURCES		+=	$(PLAT_FAMILY_BASE)/$(PLAT)/board/pm_src.c
+endif
+
 ifdef WTP
 
 $(if $(wildcard $(value WTP)/*),,$(error "'WTP=$(value WTP)' was specified, but '$(value WTP)' directory does not exist"))
diff --git a/plat/marvell/armada/a3k/common/plat_pm.c b/plat/marvell/armada/a3k/common/plat_pm.c
index 2bae37e..e2d15ab 100644
--- a/plat/marvell/armada/a3k/common/plat_pm.c
+++ b/plat/marvell/armada/a3k/common/plat_pm.c
@@ -590,6 +590,13 @@
 	return NULL;
 }
 
+#pragma weak mv_wake_up_src_config_get
+struct pm_wake_up_src_config *mv_wake_up_src_config_get(void)
+{
+	static struct pm_wake_up_src_config wake_up_src_cfg = {};
+	return &wake_up_src_cfg;
+}
+
 static void a3700_set_wake_up_source(void)
 {
 	struct pm_wake_up_src_config *wake_up_src;
diff --git a/plat/mediatek/mt8192/plat_mt_gic.c b/plat/mediatek/common/drivers/gic600/mt_gic_v3.c
similarity index 100%
rename from plat/mediatek/mt8192/plat_mt_gic.c
rename to plat/mediatek/common/drivers/gic600/mt_gic_v3.c
diff --git a/plat/mediatek/mt8192/include/mt_gic_v3.h b/plat/mediatek/common/drivers/gic600/mt_gic_v3.h
similarity index 100%
rename from plat/mediatek/mt8192/include/mt_gic_v3.h
rename to plat/mediatek/common/drivers/gic600/mt_gic_v3.h
diff --git a/plat/mediatek/common/drivers/gpio/mtgpio_common.c b/plat/mediatek/common/drivers/gpio/mtgpio_common.c
new file mode 100644
index 0000000..89977a5
--- /dev/null
+++ b/plat/mediatek/common/drivers/gpio/mtgpio_common.c
@@ -0,0 +1,298 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/gpio.h>
+#include <lib/mmio.h>
+#include <mtgpio.h>
+#include <platform_def.h>
+
+/******************************************************************************
+ *Macro Definition
+ ******************************************************************************/
+#define GPIO_MODE_BITS		4
+#define MAX_GPIO_MODE_PER_REG	8
+#define MAX_GPIO_REG_BITS	32
+#define DIR_BASE		(GPIO_BASE + 0x000)
+#define DOUT_BASE		(GPIO_BASE + 0x100)
+#define DIN_BASE		(GPIO_BASE + 0x200)
+#define MODE_BASE		(GPIO_BASE + 0x300)
+#define SET			0x4
+#define CLR			0x8
+
+static void mt_set_gpio_dir_chip(uint32_t pin, int dir)
+{
+	uint32_t pos, bit;
+
+	assert(pin < MAX_GPIO_PIN);
+	assert(dir < MT_GPIO_DIR_MAX);
+
+	pos = pin / MAX_GPIO_REG_BITS;
+	bit = pin % MAX_GPIO_REG_BITS;
+
+	if (dir == MT_GPIO_DIR_IN) {
+		mmio_write_32(DIR_BASE + 0x10U * pos + CLR, 1U << bit);
+	} else {
+		mmio_write_32(DIR_BASE + 0x10U * pos + SET, 1U << bit);
+	}
+}
+
+static int mt_get_gpio_dir_chip(uint32_t pin)
+{
+	uint32_t pos, bit;
+	uint32_t reg;
+
+	assert(pin < MAX_GPIO_PIN);
+
+	pos = pin / MAX_GPIO_REG_BITS;
+	bit = pin % MAX_GPIO_REG_BITS;
+
+	reg = mmio_read_32(DIR_BASE + 0x10U * pos);
+	return (((reg & (1U << bit)) != 0U) ? MT_GPIO_DIR_OUT : MT_GPIO_DIR_IN);
+}
+
+static void mt_set_gpio_out_chip(uint32_t pin, int output)
+{
+	uint32_t pos, bit;
+
+	assert(pin < MAX_GPIO_PIN);
+	assert(output < MT_GPIO_OUT_MAX);
+
+	pos = pin / MAX_GPIO_REG_BITS;
+	bit = pin % MAX_GPIO_REG_BITS;
+
+	if (output == MT_GPIO_OUT_ZERO) {
+		mmio_write_32(DOUT_BASE + 0x10U * pos + CLR, 1U << bit);
+	} else {
+		mmio_write_32(DOUT_BASE + 0x10U * pos + SET, 1U << bit);
+	}
+}
+
+static int mt_get_gpio_in_chip(uint32_t pin)
+{
+	uint32_t pos, bit;
+	uint32_t reg;
+
+	assert(pin < MAX_GPIO_PIN);
+
+	pos = pin / MAX_GPIO_REG_BITS;
+	bit = pin % MAX_GPIO_REG_BITS;
+
+	reg = mmio_read_32(DIN_BASE + 0x10U * pos);
+	return (((reg & (1U << bit)) != 0U) ? 1 : 0);
+}
+
+static void mt_gpio_set_spec_pull_pupd(uint32_t pin, int enable,
+			       int select)
+{
+	uintptr_t reg1;
+	uintptr_t reg2;
+	struct mt_pin_info gpio_info;
+
+	gpio_info = mt_pin_infos[pin];
+	uint32_t bit = gpio_info.bit;
+
+	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+	reg2 = reg1 + (gpio_info.base & 0xf0);
+	if (enable == MT_GPIO_PULL_ENABLE) {
+		mmio_write_32(reg2 + SET, (1U << bit));
+		if (select == MT_GPIO_PULL_DOWN) {
+			mmio_write_32(reg1 + SET, (1U << bit));
+		} else {
+			mmio_write_32(reg1 + CLR, (1U << bit));
+		}
+	} else {
+		mmio_write_32(reg2 + CLR, (1U << bit));
+		mmio_write_32((reg2 + 0x010U) + CLR, (1U << bit));
+	}
+}
+
+static void mt_gpio_set_pull_pu_pd(uint32_t pin, int enable,
+				 int select)
+{
+	uintptr_t reg1;
+	uintptr_t reg2;
+	struct mt_pin_info gpio_info;
+
+	gpio_info = mt_pin_infos[pin];
+	uint32_t bit = gpio_info.bit;
+
+	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+	reg2 = reg1 - (gpio_info.base & 0xf0);
+
+	if (enable == MT_GPIO_PULL_ENABLE) {
+		if (select == MT_GPIO_PULL_DOWN) {
+			mmio_write_32(reg1 + CLR, (1U << bit));
+			mmio_write_32(reg2 + SET, (1U << bit));
+		} else {
+			mmio_write_32(reg2 + CLR, (1U << bit));
+			mmio_write_32(reg1 + SET, (1U << bit));
+		}
+	} else {
+		mmio_write_32(reg1 + CLR, (1U << bit));
+		mmio_write_32(reg2 + CLR, (1U << bit));
+	}
+}
+
+static void mt_gpio_set_pull_chip(uint32_t pin, int enable,
+		   int select)
+{
+	struct mt_pin_info gpio_info;
+
+	gpio_info = mt_pin_infos[pin];
+	if (gpio_info.flag) {
+		mt_gpio_set_spec_pull_pupd(pin, enable, select);
+	} else {
+		mt_gpio_set_pull_pu_pd(pin, enable, select);
+	}
+}
+
+static int mt_gpio_get_spec_pull_pupd(uint32_t pin)
+{
+	uintptr_t reg1;
+	uintptr_t reg2;
+	uint32_t r0;
+	uint32_t r1;
+
+	struct mt_pin_info gpio_info;
+
+	gpio_info = mt_pin_infos[pin];
+	uint32_t bit = gpio_info.bit;
+
+	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+	reg2 = reg1 + (gpio_info.base & 0xf0);
+
+	r0 = (mmio_read_32(reg2) >> bit) & 1U;
+	r1 = (mmio_read_32(reg2 + 0x010) >> bit) & 1U;
+	if (r0 == 0U && r1 == 0U) {
+		return MT_GPIO_PULL_NONE;
+	} else {
+		if (mmio_read_32(reg1) & (1U << bit)) {
+			return MT_GPIO_PULL_DOWN;
+		} else {
+			return MT_GPIO_PULL_UP;
+		}
+	}
+}
+
+static int mt_gpio_get_pull_pu_pd(uint32_t pin)
+{
+	uintptr_t reg1;
+	uintptr_t reg2;
+	uint32_t pu;
+	uint32_t pd;
+
+	struct mt_pin_info gpio_info;
+
+	gpio_info = mt_pin_infos[pin];
+	uint32_t bit = gpio_info.bit;
+
+	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+	reg2 = reg1 - (gpio_info.base & 0xf0);
+	pu = (mmio_read_32(reg1) >> bit) & 1U;
+	pd = (mmio_read_32(reg2) >> bit) & 1U;
+	if (pu == 1U) {
+		return MT_GPIO_PULL_UP;
+	} else if (pd == 1U) {
+		return MT_GPIO_PULL_DOWN;
+	} else {
+		return MT_GPIO_PULL_NONE;
+	}
+}
+
+static int mt_gpio_get_pull_chip(uint32_t pin)
+{
+	struct mt_pin_info gpio_info;
+
+	gpio_info = mt_pin_infos[pin];
+	if (gpio_info.flag) {
+		return mt_gpio_get_spec_pull_pupd(pin);
+	} else {
+		return mt_gpio_get_pull_pu_pd(pin);
+	}
+}
+
+static void mt_set_gpio_pull_select_chip(uint32_t pin, int sel)
+{
+	assert(pin < MAX_GPIO_PIN);
+
+	if (sel == MT_GPIO_PULL_NONE) {
+		mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_DISABLE, MT_GPIO_PULL_DOWN);
+	} else if (sel == MT_GPIO_PULL_UP) {
+		mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_UP);
+	} else if (sel == MT_GPIO_PULL_DOWN) {
+		mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_DOWN);
+	}
+}
+
+/* get pull-up or pull-down, regardless of resistor value */
+static int mt_get_gpio_pull_select_chip(uint32_t pin)
+{
+	assert(pin < MAX_GPIO_PIN);
+
+	return mt_gpio_get_pull_chip(pin);
+}
+
+static void mt_set_gpio_dir(int gpio, int direction)
+{
+	mt_set_gpio_dir_chip((uint32_t)gpio, direction);
+}
+
+static int mt_get_gpio_dir(int gpio)
+{
+	uint32_t pin;
+
+	pin = (uint32_t)gpio;
+	return mt_get_gpio_dir_chip(pin);
+}
+
+static void mt_set_gpio_pull(int gpio, int pull)
+{
+	uint32_t pin;
+
+	pin = (uint32_t)gpio;
+	mt_set_gpio_pull_select_chip(pin, pull);
+}
+
+static int mt_get_gpio_pull(int gpio)
+{
+	uint32_t pin;
+
+	pin = (uint32_t)gpio;
+	return mt_get_gpio_pull_select_chip(pin);
+}
+
+static void mt_set_gpio_out(int gpio, int value)
+{
+	uint32_t pin;
+
+	pin = (uint32_t)gpio;
+	mt_set_gpio_out_chip(pin, value);
+}
+
+static int mt_get_gpio_in(int gpio)
+{
+	uint32_t pin;
+
+	pin = (uint32_t)gpio;
+	return mt_get_gpio_in_chip(pin);
+}
+
+const gpio_ops_t mtgpio_ops = {
+	 .get_direction = mt_get_gpio_dir,
+	 .set_direction = mt_set_gpio_dir,
+	 .get_value = mt_get_gpio_in,
+	 .set_value = mt_set_gpio_out,
+	 .set_pull = mt_set_gpio_pull,
+	 .get_pull = mt_get_gpio_pull,
+};
+
+void mt_gpio_init(void)
+{
+	gpio_init(&mtgpio_ops);
+}
diff --git a/plat/mediatek/common/drivers/gpio/mtgpio_common.h b/plat/mediatek/common/drivers/gpio/mtgpio_common.h
new file mode 100644
index 0000000..bf51055
--- /dev/null
+++ b/plat/mediatek/common/drivers/gpio/mtgpio_common.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GPIO_COMMON_H
+#define MT_GPIO_COMMON_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <plat/common/common_def.h>
+
+/*  Error Code No. */
+#define RSUCCESS        0
+#define ERACCESS        1
+#define ERINVAL         2
+#define ERWRAPPER       3
+#define MAX_GPIO_PIN    MT_GPIO_BASE_MAX
+
+/* GPIO MODE CONTROL VALUE*/
+typedef enum {
+	GPIO_MODE_UNSUPPORTED = -1,
+	GPIO_MODE_GPIO  = 0,
+	GPIO_MODE_00    = 0,
+	GPIO_MODE_01,
+	GPIO_MODE_02,
+	GPIO_MODE_03,
+	GPIO_MODE_04,
+	GPIO_MODE_05,
+	GPIO_MODE_06,
+	GPIO_MODE_07,
+
+	GPIO_MODE_MAX,
+	GPIO_MODE_DEFAULT = GPIO_MODE_00,
+} GPIO_MODE;
+
+/* GPIO DIRECTION */
+typedef enum {
+	MT_GPIO_DIR_UNSUPPORTED = -1,
+	MT_GPIO_DIR_OUT    = 0,
+	MT_GPIO_DIR_IN     = 1,
+	MT_GPIO_DIR_MAX,
+	MT_GPIO_DIR_DEFAULT = MT_GPIO_DIR_IN,
+} GPIO_DIR;
+
+/* GPIO PULL ENABLE*/
+typedef enum {
+	MT_GPIO_PULL_EN_UNSUPPORTED = -1,
+	MT_GPIO_PULL_DISABLE   = 0,
+	MT_GPIO_PULL_ENABLE    = 1,
+	MT_GPIO_PULL_ENABLE_R0 = 2,
+	MT_GPIO_PULL_ENABLE_R1 = 3,
+	MT_GPIO_PULL_ENABLE_R0R1 = 4,
+
+	MT_GPIO_PULL_EN_MAX,
+	MT_GPIO_PULL_EN_DEFAULT = MT_GPIO_PULL_ENABLE,
+} GPIO_PULL_EN;
+
+/* GPIO PULL-UP/PULL-DOWN*/
+typedef enum {
+	MT_GPIO_PULL_UNSUPPORTED = -1,
+	MT_GPIO_PULL_NONE        = 0,
+	MT_GPIO_PULL_UP          = 1,
+	MT_GPIO_PULL_DOWN        = 2,
+	MT_GPIO_PULL_MAX,
+	MT_GPIO_PULL_DEFAULT = MT_GPIO_PULL_DOWN
+} GPIO_PULL;
+
+/* GPIO OUTPUT */
+typedef enum {
+	MT_GPIO_OUT_UNSUPPORTED = -1,
+	MT_GPIO_OUT_ZERO = 0,
+	MT_GPIO_OUT_ONE  = 1,
+
+	MT_GPIO_OUT_MAX,
+	MT_GPIO_OUT_DEFAULT = MT_GPIO_OUT_ZERO,
+	MT_GPIO_DATA_OUT_DEFAULT = MT_GPIO_OUT_ZERO,  /*compatible with DCT*/
+} GPIO_OUT;
+
+/* GPIO INPUT */
+typedef enum {
+	MT_GPIO_IN_UNSUPPORTED = -1,
+	MT_GPIO_IN_ZERO = 0,
+	MT_GPIO_IN_ONE  = 1,
+
+	MT_GPIO_IN_MAX,
+} GPIO_IN;
+
+#define PIN(_id, _flag, _bit, _base, _offset) {		\
+		.id = _id,				\
+		.flag = _flag,				\
+		.bit = _bit,				\
+		.base = _base,				\
+		.offset = _offset,			\
+	}
+
+struct mt_pin_info {
+	uint8_t id;
+	uint8_t flag;
+	uint8_t bit;
+	uint16_t base;
+	uint16_t offset;
+};
+
+void mt_gpio_init(void);
+uintptr_t mt_gpio_find_reg_addr(uint32_t pin);
+#endif /* MT_GPIO_COMMON_H */
diff --git a/plat/mediatek/mt8192/drivers/rtc/rtc.c b/plat/mediatek/common/drivers/rtc/rtc_mt6359p.c
similarity index 100%
rename from plat/mediatek/mt8192/drivers/rtc/rtc.c
rename to plat/mediatek/common/drivers/rtc/rtc_mt6359p.c
diff --git a/plat/mediatek/mt8192/drivers/rtc/rtc.h b/plat/mediatek/common/drivers/rtc/rtc_mt6359p.h
similarity index 97%
rename from plat/mediatek/mt8192/drivers/rtc/rtc.h
rename to plat/mediatek/common/drivers/rtc/rtc_mt6359p.h
index 419bfe4..04726e3 100644
--- a/plat/mediatek/mt8192/drivers/rtc/rtc.h
+++ b/plat/mediatek/common/drivers/rtc/rtc_mt6359p.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef RTC_H
-#define RTC_H
+#ifndef RTC_MT6359P_H
+#define RTC_MT6359P_H
 
 /* RTC registers */
 enum {
@@ -194,4 +194,4 @@
 int32_t Writeif_unlock(void);
 void rtc_power_off_sequence(void);
 
-#endif /* RTC_H */
+#endif /* RTC_MT6359P_H */
diff --git a/plat/mediatek/mt8192/drivers/timer/mt_timer.c b/plat/mediatek/common/drivers/timer/mt_timer.c
similarity index 100%
rename from plat/mediatek/mt8192/drivers/timer/mt_timer.c
rename to plat/mediatek/common/drivers/timer/mt_timer.c
diff --git a/plat/mediatek/mt8192/drivers/timer/mt_timer.h b/plat/mediatek/common/drivers/timer/mt_timer.h
similarity index 100%
rename from plat/mediatek/mt8192/drivers/timer/mt_timer.h
rename to plat/mediatek/common/drivers/timer/mt_timer.h
diff --git a/plat/mediatek/mt8192/plat_mt_cirq.c b/plat/mediatek/common/mtk_cirq.c
similarity index 99%
rename from plat/mediatek/mt8192/plat_mt_cirq.c
rename to plat/mediatek/common/mtk_cirq.c
index 9002b7e..de37986 100644
--- a/plat/mediatek/mt8192/plat_mt_cirq.c
+++ b/plat/mediatek/common/mtk_cirq.c
@@ -10,8 +10,7 @@
 #include <lib/mmio.h>
 
 #include <mt_gic_v3.h>
-#include <plat_mt_cirq.h>
-#include <platform_def.h>
+#include <mtk_cirq.h>
 
 static struct cirq_events cirq_all_events = {
 	.spi_start = CIRQ_SPI_START,
diff --git a/plat/mediatek/mt8192/include/plat_mt_cirq.h b/plat/mediatek/common/mtk_cirq.h
similarity index 93%
rename from plat/mediatek/mt8192/include/plat_mt_cirq.h
rename to plat/mediatek/common/mtk_cirq.h
index bb8b457..6e63bb8 100644
--- a/plat/mediatek/mt8192/include/plat_mt_cirq.h
+++ b/plat/mediatek/common/mtk_cirq.h
@@ -8,6 +8,7 @@
 #define PLAT_MT_CIRQ_H
 
 #include <stdint.h>
+#include <platform_def.h>
 
 enum {
 	IRQ_MASK_HEADER = 0xF1F1F1F1,
@@ -35,13 +36,6 @@
 /*
  * Define hardware register
  */
-
-#define  SYS_CIRQ_BASE         U(0x10204000)
-#define  CIRQ_REG_NUM          U(14)
-#define  CIRQ_IRQ_NUM          U(439)
-#define  CIRQ_SPI_START        U(64)
-#define  MD_WDT_IRQ_BIT_ID     U(110)
-
 #define  CIRQ_STA_BASE         (SYS_CIRQ_BASE + U(0x000))
 #define  CIRQ_ACK_BASE         (SYS_CIRQ_BASE + U(0x080))
 #define  CIRQ_MASK_BASE        (SYS_CIRQ_BASE + U(0x100))
diff --git a/plat/mediatek/mt8192/bl31_plat_setup.c b/plat/mediatek/mt8192/bl31_plat_setup.c
index 0040747..c3cb9a5 100644
--- a/plat/mediatek/mt8192/bl31_plat_setup.c
+++ b/plat/mediatek/mt8192/bl31_plat_setup.c
@@ -16,6 +16,7 @@
 #include <lib/coreboot.h>
 
 /* Platform Includes */
+#include <devapc/devapc.h>
 #include <emi_mpu/emi_mpu.h>
 #include <gpio/mtgpio.h>
 #include <mt_gic_v3.h>
@@ -94,11 +95,14 @@
 	/* MPU Init */
 	emi_mpu_init();
 
+	/* DAPC Init */
+	devapc_init();
+
 	/* Initialize the GIC driver, CPU and distributor interfaces */
 	mt_gic_driver_init();
 	mt_gic_init();
 
-	plat_mt8192_gpio_init();
+	mt_gpio_init();
 	mt_systimer_init();
 	generic_delay_timer_init();
 	spm_boot_init();
diff --git a/plat/mediatek/mt8192/drivers/devapc/devapc.c b/plat/mediatek/mt8192/drivers/devapc/devapc.c
new file mode 100644
index 0000000..c7dbbee
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/devapc/devapc.c
@@ -0,0 +1,2843 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <lib/mmio.h>
+
+#include <devapc.h>
+
+/* Infra_ao */
+static const struct APC_INFRA_PERI_DOM_16 INFRA_AO_SYS0_Devices[] = {
+
+/* 0 */
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-3",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-4",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-5",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-6",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-7",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-8",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("APU_S_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 10 */
+DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-3",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-4",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-5",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-1",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-2",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-3",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-4",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 20 */
+DAPC_INFRA_AO_SYS0_ATTR("L3C_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("L3C_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("PCIE_AXI_S",
+			NO_PROTECTION, NO_PROTECTION, FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+};
+
+static const struct APC_INFRA_PERI_DOM_4 INFRA_AO_SYS1_Devices[] = {
+
+/* 0 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-3",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-4",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-5",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-6",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-7",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-8",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-9",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 10 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-10",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-11",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-12",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-13",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-14",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-15",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-16",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-17",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-18",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-19",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 20 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-20",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-21",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-22",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-23",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-24",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-25",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-26",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-27",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-28",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-29",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 30 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-30",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-31",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-32",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-33",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-34",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-35",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-36",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-37",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-38",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-39",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 40 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-100",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-101",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-102",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-103",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-104",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-105",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-106",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-107",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-108",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-109",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 50 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-110",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-111",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-112",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-113",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-114",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-115",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-116",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-117",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-118",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-119",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 60 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-120",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-121",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-122",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-123",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-124",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-125",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-126",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-127",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-128",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-129",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 70 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-130",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-131",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-132",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-133",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-134",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-135",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-136",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-137",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-138",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-139",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 80 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-140",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-141",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-142",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-143",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-200",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     NO_PROTECTION),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-201",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     NO_PROTECTION),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-202",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-203",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     NO_PROTECTION),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-204",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-205",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 90 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-206",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-207",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-300",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-301",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-302",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     NO_PROTECTION),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-303",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-304",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-305",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-306",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-307",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 100 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-400",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-401",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-402",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-403",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-404",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-405",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-406",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-407",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-408",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-409",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 110 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-410",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-411",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-412",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-413",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-414",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-415",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-416",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-417",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-418",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-419",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 120 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-420",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-421",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-422",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-423",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-424",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-425",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-426",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-427",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-428",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-429",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 130 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-430",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-431",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-432",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-433",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-434",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-435",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-436",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-437",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-438",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-439",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 140 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-440",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-441",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-442",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-443",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-444",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-445",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-446",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-447",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-448",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-449",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 150 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-450",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-451",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-452",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-453",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-454",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-455",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-456",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-457",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-458",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-459",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 160 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-460",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-461",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-462",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-463",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-464",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-465",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-466",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-467",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-468",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-469",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 170 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-470",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-471",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-472",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-473",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-474",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-475",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-476",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-477",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-478",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-479",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 180 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-480",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-481",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-482",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-483",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-484",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-485",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-486",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-487",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-488",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-489",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 190 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-490",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-491",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-492",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-493",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-494",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-495",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-496",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-497",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-498",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-499",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 200 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-500",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-501",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-502",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-503",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-504",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-505",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-506",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-507",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-508",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-509",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 210 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-510",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-511",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-512",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-513",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-514",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-515",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-516",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-517",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-518",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-519",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 220 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-520",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-521",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-522",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-523",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-524",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-525",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-526",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-527",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-528",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-529",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 230 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-530",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-531",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-532",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-533",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-534",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-535",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-536",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-537",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-538",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-539",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 240 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-540",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-541",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-542",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-543",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-544",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-545",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-546",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-547",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-548",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-549",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 250 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-550",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-551",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-552",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-553",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-554",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-555",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+};
+
+static const struct APC_INFRA_PERI_DOM_4 INFRA_AO_SYS2_Devices[] = {
+
+/* 0 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-556",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-557",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-558",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-559",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-560",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-561",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-562",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-563",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-564",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-565",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 10 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-566",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-567",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-568",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-569",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-570",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-571",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-572",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-573",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-574",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-575",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 20 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-576",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-577",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-578",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-579",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-580",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-581",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-582",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-583",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-584",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-585",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 30 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-586",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-587",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-588",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-589",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-590",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-591",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-592",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-593",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-594",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-595",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 40 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-600",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-601",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-602",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-603",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-604",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-605",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-606",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-607",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-608",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-609",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 50 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-610",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-611",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-700",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-701",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-702",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-703",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-704",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-705",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-706",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-707",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 60 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-708",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-709",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-710",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-711",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-712",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-713",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-714",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-715",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-716",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-717",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+};
+
+/* Peri_ao */
+static const struct APC_INFRA_PERI_DOM_16 PERI_AO_SYS0_Devices[] = {
+
+/* 0 */
+DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S-3",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S-4",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("APMIXEDSYS_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, NO_PROTECTION,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("APMIXEDSYS_APB_S-1",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("TOPCKGEN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, NO_PROTECTION,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("INFRACFG_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("INFRACFG_AO_MEM_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 10 */
+DAPC_PERI_AO_SYS0_ATTR("PERICFG_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("GPIO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     NO_PROTECTION,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("TOPRGU_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("RESERVED_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_INFRA_AO_APB_S",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("BCRM_INFRA_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEBUG_CTRL_INFRA_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_PERI_AO_APB_S",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("BCRM_PERI_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEBUG_CTRL_PERI_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 20 */
+DAPC_PERI_AO_SYS0_ATTR("AP_CIRQ_EINT_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PMIC_WRAP_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_AO_MM_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("KP_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("TOP_MISC_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DVFSRC_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("MBIST_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DPMAIF_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEVICE_MPU_AO_APB_S",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SYS_TIMER_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 30 */
+DAPC_PERI_AO_SYS0_ATTR("MODEM_TEMP_SHARE_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_AO_MD_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PMIF1_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PMICSPI_MST_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("TIA_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("TOPCKGEN_INFRA_CFG_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRM_DEBUG_TOP_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 40 */
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-3",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-4",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-5",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-6",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-7",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-8",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-9",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-10",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("AUDIO_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("AUDIO_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 50 */
+DAPC_PERI_AO_SYS0_ATTR("SSUSB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SSUSB_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SSUSB_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("UFS_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("UFS_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("UFS_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("UFS_S-3",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEBUGSYS_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S-1",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 60 */
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("NOR_AXI_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PCIE_AHB_S",
+			NO_PROTECTION, NO_PROTECTION, FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP0_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP1_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP3_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP4_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP5_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 70 */
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP6_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP0_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP1_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP3_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP4_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP5_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP6_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP0_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP1_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 80 */
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP3_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP4_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP5_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP6_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP0_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP1_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP3_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP4_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 90 */
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP5_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP6_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF2_AP_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF2_MD_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF3_AP_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF3_MD_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF4_AP_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF4_MD_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("INFRA_BUS_TRACE_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF5_AP_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 100 */
+DAPC_PERI_AO_SYS0_ATTR("CCIF5_MD_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB0_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB1_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB2_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEVICE_MPU_ACP_APB_S",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+};
+
+static const struct APC_INFRA_PERI_DOM_8 PERI_AO_SYS1_Devices[] = {
+
+/* 0 */
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-3",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-4",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-5",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-6",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-7",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-8",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-9",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 10 */
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-10",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-11",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-12",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-13",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-14",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-15",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-16",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-17",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-18",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-19",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 20 */
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-20",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-21",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-22",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-3",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-4",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-5",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-6",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 30 */
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-7",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-8",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-9",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-10",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-11",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-12",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-13",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-14",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-15",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-16",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 40 */
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-17",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-18",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-19",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-20",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-21",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-22",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-23",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-24",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-25",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-26",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 50 */
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-27",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-28",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-29",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-30",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-31",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-32",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-33",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-34",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-35",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-36",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 60 */
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-37",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-38",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-39",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-40",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-41",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-42",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+};
+
+static const struct APC_INFRA_PERI_DOM_4 PERI_AO_SYS2_Devices[] = {
+
+/* 0 */
+DAPC_PERI_AO_SYS2_ATTR("CONN_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+};
+
+/* Peri_ao2 */
+static const struct APC_INFRA_PERI_DOM_16 PERI_AO2_SYS0_Devices[] = {
+
+/* 0 */
+DAPC_PERI_AO2_SYS0_ATTR("EFUSE_DEBUG_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("APXGPT_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SEJ_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("AES_TOP0_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SECURITY_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_PERI_AO2_APB_S",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BCRM_PERI_AO2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEBUG_CTRL_PERI_AO2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SPMI_MST_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEBUG_CTRL_FMEM_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 10 */
+DAPC_PERI_AO2_SYS0_ATTR("BCRM_FMEM_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_FMEM_AO_APB_S",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("PWM_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("GCE_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("GCE_APB_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("GCE_APB_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("GCE_APB_S-3",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DPMAIF_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DPMAIF_PDN_APB_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DPMAIF_PDN_APB_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 20 */
+DAPC_PERI_AO2_SYS0_ATTR("DPMAIF_PDN_APB_S-3",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB0_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB1_S",
+			NO_PROTECTION, FORBIDDEN,     SEC_RW_NS_R,   FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB2_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB3_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB4_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB5_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB6_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB7_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB8_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 30 */
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB9_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB10_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB11_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB12_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB13_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB14_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB15_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB0_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB1_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB2_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 40 */
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB3_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB4_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB5_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB6_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB7_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB0_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB1_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB2_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB3_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB4_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 50 */
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB5_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB6_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB7_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB8_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB9_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB10_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB11_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB12_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB13_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB14_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 60 */
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB15_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB0_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB1_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB2_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB3_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB4_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB5_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB6_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB7_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB8_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 70 */
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB9_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB10_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB11_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB12_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB13_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB14_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB15_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB0_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB1_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB2_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 80 */
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB3_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB4_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB5_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB6_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB7_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SYS_CIRQ_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("EFUSE_DEBUG_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_INFRA_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEBUG_TRACKER_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("CCIF0_AP_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 90 */
+DAPC_PERI_AO2_SYS0_ATTR("CCIF0_MD_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("CCIF1_AP_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("CCIF1_MD_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("MBIST_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("INFRACFG_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("TRNG_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DX_CC_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("CQ_DMA_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SRAMROM_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("INFRACFG_MEM_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 100 */
+DAPC_PERI_AO2_SYS0_ATTR("RESERVED_DVFS_PROC_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SYS_CIRQ1_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SYS_CIRQ2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEBUG_TRACKER_APB1_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("EMI_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("EMI_MPU_APB_S",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEVICE_MPU_PDN_APB_S",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("APDMA_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEBUG_TRACKER_APB2_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BCRM_INFRA_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 110 */
+DAPC_PERI_AO2_SYS0_ATTR("BCRM_PERI_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BCRM_PERI_PDN2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_PERI_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_PERI_PDN2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BCRM_FMEM_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+};
+
+/* Peri_par_ao */
+static const struct APC_INFRA_PERI_DOM_16 PERI_PAR_AO_SYS0_Devices[] = {
+
+/* 0 */
+DAPC_PERI_PAR_AO_SYS0_ATTR("AUXADC_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("UART0_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("UART1_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("UART2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB4_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI0_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("BTIF_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("DISP_PWM_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI1_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 10 */
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI3_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB0_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB1_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI4_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI5_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB2_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB3_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI6_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI7_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 20 */
+DAPC_PERI_PAR_AO_SYS0_ATTR("BCRM_PERI_PAR_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("DEVICE_APC_PERI_PAR_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("NOR_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("DEVICE_APC_PERI_PAR_AO_APB_S",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("DEBUG_CTRL_PERI_PAR_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("BCRM_PERI_PAR_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+};
+
+static void set_module_apc(enum DEVAPC_SLAVE_TYPE slave_type,
+		uint32_t module, enum DOMAIN_ID domain_id,
+		enum DEVAPC_PERM_TYPE perm)
+{
+	uint32_t apc_register_index;
+	uint32_t apc_set_index;
+	uintptr_t base = 0, reg;
+	uint32_t clr_bit;
+	uint32_t set_bit;
+
+	apc_register_index = module / MOD_NO_IN_1_DEVAPC;
+	apc_set_index = module % MOD_NO_IN_1_DEVAPC;
+
+	clr_bit = (0x3U << (apc_set_index * 2));
+	set_bit = (uint32_t)perm << (apc_set_index * 2);
+
+	/* infra_ao */
+	if ((slave_type == SLAVE_TYPE_INFRA_AO_SYS0) &&
+		(module < SLAVE_NUM_INFRA_AO_SYS0) &&
+		(domain_id < (uint32_t)DOM_NUM_INFRA_AO_SYS0)) {
+		base = DEVAPC_INFRA_AO_SYS0_D0_APC_0;
+
+	} else if ((slave_type == SLAVE_TYPE_INFRA_AO_SYS1) &&
+		(module < SLAVE_NUM_INFRA_AO_SYS1) &&
+		(domain_id < (uint32_t)DOM_NUM_INFRA_AO_SYS1)) {
+		base = DEVAPC_INFRA_AO_SYS1_D0_APC_0;
+
+	} else if ((slave_type == SLAVE_TYPE_INFRA_AO_SYS2) &&
+		(module < SLAVE_NUM_INFRA_AO_SYS2) &&
+		(domain_id < (uint32_t)DOM_NUM_INFRA_AO_SYS2)) {
+		base = DEVAPC_INFRA_AO_SYS2_D0_APC_0;
+	/* peri_ao */
+	} else if ((slave_type == SLAVE_TYPE_PERI_AO_SYS0) &&
+		(module < SLAVE_NUM_PERI_AO_SYS0) &&
+		(domain_id < (uint32_t)DOM_NUM_PERI_AO_SYS0)) {
+		base = DEVAPC_PERI_AO_SYS0_D0_APC_0;
+
+	} else if ((slave_type == SLAVE_TYPE_PERI_AO_SYS1) &&
+		(module < SLAVE_NUM_PERI_AO_SYS1) &&
+		(domain_id <= (uint32_t)DOM_NUM_PERI_AO_SYS1)) {
+		base = DEVAPC_PERI_AO_SYS1_D0_APC_0;
+
+	} else if ((slave_type == SLAVE_TYPE_PERI_AO_SYS2) &&
+		(module < SLAVE_NUM_PERI_AO_SYS2) &&
+		(domain_id < (uint32_t)DOM_NUM_PERI_AO_SYS2)) {
+		base = DEVAPC_PERI_AO_SYS2_D0_APC_0;
+	/* peri_ao2 */
+	} else if ((slave_type == SLAVE_TYPE_PERI_AO2_SYS0) &&
+		(module < SLAVE_NUM_PERI_AO2_SYS0) &&
+		(domain_id < (uint32_t)DOM_NUM_PERI_AO2_SYS0)) {
+		base = DEVAPC_PERI_AO2_SYS0_D0_APC_0;
+
+	/* peri_par_ao */
+	} else if ((slave_type == SLAVE_TYPE_PERI_PAR_AO_SYS0) &&
+		(module < SLAVE_NUM_PERI_PAR_AO_SYS0) &&
+		(domain_id < (uint32_t)DOM_NUM_PERI_PAR_AO_SYS0)) {
+		base = DEVAPC_PERI_PAR_AO_SYS0_D0_APC_0;
+
+	} else {
+		ERROR("[DEVAPC] %s: %s, %s:0x%x, %s:0x%x, %s:0x%x\n",
+				__func__, "out of boundary",
+				"slave_type", slave_type,
+				"module", module,
+				"domain_id", domain_id);
+	}
+
+	if (base != 0U) {
+		reg = base + domain_id * 0x40 + apc_register_index * 4;
+		mmio_clrsetbits_32(reg, clr_bit, set_bit);
+	}
+}
+
+static void dump_infra_ao_apc(void)
+{
+	int reg_num;
+	int d, i;
+
+	reg_num = (SLAVE_NUM_INFRA_AO_SYS0 - 1) / MOD_NO_IN_1_DEVAPC;
+	for (d = 0; d < DOM_NUM_INFRA_AO_SYS0; d++) {
+		for (i = 0; i <= reg_num; i++) {
+			INFO("[DEVAPC] (INFRA_AO_SYS0)D%d_APC_%d: 0x%x\n",
+					d, i, devapc_readl(
+					DEVAPC_INFRA_AO_SYS0_D0_APC_0 +
+					d * 0x40 + i * 4)
+			);
+		}
+	}
+
+	reg_num = (SLAVE_NUM_INFRA_AO_SYS1 - 1) / MOD_NO_IN_1_DEVAPC;
+	for (d = 0; d < DOM_NUM_INFRA_AO_SYS1; d++) {
+		for (i = 0; i <= reg_num; i++) {
+			INFO("[DEVAPC] (INFRA_AO_SYS1)D%d_APC_%d: 0x%x\n",
+					d, i, devapc_readl(
+					DEVAPC_INFRA_AO_SYS1_D0_APC_0 +
+					d * 0x40 + i * 4)
+			);
+		}
+	}
+
+	reg_num = (SLAVE_NUM_INFRA_AO_SYS2 - 1) / MOD_NO_IN_1_DEVAPC;
+	for (d = 0; d < DOM_NUM_INFRA_AO_SYS2; d++) {
+		for (i = 0; i <= reg_num; i++) {
+			INFO("[DEVAPC] (INFRA_AO_SYS2)D%d_APC_%d: 0x%x\n",
+					d, i, devapc_readl(
+					DEVAPC_INFRA_AO_SYS2_D0_APC_0 +
+					d * 0x40 + i * 4)
+			);
+		}
+	}
+
+	INFO("[DEVAPC] (INFRA_AO)MAS_SEC_0: 0x%x\n",
+		devapc_readl(DEVAPC_INFRA_AO_MAS_SEC_0));
+}
+
+static void dump_peri_ao_apc(void)
+{
+	int reg_num;
+	int d, i;
+
+	reg_num = (SLAVE_NUM_PERI_AO_SYS0 - 1) / MOD_NO_IN_1_DEVAPC;
+	for (d = 0; d < DOM_NUM_PERI_AO_SYS0; d++) {
+		for (i = 0; i <= reg_num; i++) {
+			INFO("[DEVAPC] (PERI_AO_SYS0)D%d_APC_%d: 0x%x\n",
+					d, i, devapc_readl(
+					DEVAPC_PERI_AO_SYS0_D0_APC_0 +
+					d * 0x40 + i * 4)
+			);
+		}
+	}
+
+	reg_num = (SLAVE_NUM_PERI_AO_SYS1 - 1) / MOD_NO_IN_1_DEVAPC;
+	for (d = 0; d < DOM_NUM_PERI_AO_SYS1; d++) {
+		for (i = 0; i <= reg_num; i++) {
+			INFO("[DEVAPC] (PERI_AO_SYS1)D%d_APC_%d: 0x%x\n",
+					d, i, devapc_readl(
+					DEVAPC_PERI_AO_SYS1_D0_APC_0 +
+					d * 0x40 + i * 4)
+			);
+		}
+	}
+
+	reg_num = (SLAVE_NUM_PERI_AO_SYS2 - 1) / MOD_NO_IN_1_DEVAPC;
+	for (d = 0; d < DOM_NUM_PERI_AO_SYS2; d++) {
+		for (i = 0; i <= reg_num; i++) {
+			INFO("[DEVAPC] (PERI_AO_SYS2)D%d_APC_%d: 0x%x\n",
+					d, i, devapc_readl(
+					DEVAPC_PERI_AO_SYS2_D0_APC_0 +
+					d * 0x40 + i * 4)
+			);
+		}
+	}
+
+	INFO("[DEVAPC] (PERI_AO)MAS_SEC_0: 0x%x\n",
+		devapc_readl(DEVAPC_PERI_AO_MAS_SEC_0));
+}
+
+static void dump_peri_ao2_apc(void)
+{
+	int reg_num;
+	int d, i;
+
+	reg_num = (SLAVE_NUM_PERI_AO2_SYS0 - 1) / MOD_NO_IN_1_DEVAPC;
+	for (d = 0; d < DOM_NUM_PERI_AO2_SYS0; d++) {
+		for (i = 0; i <= reg_num; i++) {
+			INFO("[DEVAPC] (PERI_AO2_SYS0)D%d_APC_%d: 0x%x\n",
+					d, i, devapc_readl(
+					DEVAPC_PERI_AO2_SYS0_D0_APC_0 +
+					d * 0x40 + i * 4)
+			);
+		}
+	}
+}
+
+static void dump_peri_par_ao_apc(void)
+{
+	int reg_num;
+	int d, i;
+
+	reg_num = (SLAVE_NUM_PERI_PAR_AO_SYS0 - 1) / MOD_NO_IN_1_DEVAPC;
+	for (d = 0; d < DOM_NUM_PERI_PAR_AO_SYS0; d++) {
+		for (i = 0; i <= reg_num; i++) {
+			INFO("[DEVAPC] (PERI_PAR_AO_SYS0)D%d_APC_%d: 0x%x\n",
+					d, i, devapc_readl(
+					DEVAPC_PERI_PAR_AO_SYS0_D0_APC_0 +
+					d * 0x40 + i * 4)
+			);
+		}
+	}
+
+	INFO("[DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x%x\n",
+		devapc_readl(DEVAPC_PERI_PAR_AO_MAS_SEC_0));
+}
+
+static void set_infra_ao_apc(void)
+{
+	uint32_t infra_ao_size;
+	uint32_t i;
+
+	infra_ao_size = ARRAY_SIZE(INFRA_AO_SYS0_Devices);
+
+	for (i = 0; i < infra_ao_size; i++) {
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_0,
+				INFRA_AO_SYS0_Devices[i].d0_permission);		/* APMCU */
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_1,
+				INFRA_AO_SYS0_Devices[i].d1_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_2,
+				INFRA_AO_SYS0_Devices[i].d2_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_3,
+				INFRA_AO_SYS0_Devices[i].d3_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_4,
+				INFRA_AO_SYS0_Devices[i].d4_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_5,
+				INFRA_AO_SYS0_Devices[i].d5_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_6,
+				INFRA_AO_SYS0_Devices[i].d6_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_7,
+				INFRA_AO_SYS0_Devices[i].d7_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_8,
+				INFRA_AO_SYS0_Devices[i].d8_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_9,
+				INFRA_AO_SYS0_Devices[i].d9_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_10,
+				INFRA_AO_SYS0_Devices[i].d10_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_11,
+				INFRA_AO_SYS0_Devices[i].d11_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_12,
+				INFRA_AO_SYS0_Devices[i].d12_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_13,
+				INFRA_AO_SYS0_Devices[i].d13_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_14,
+				INFRA_AO_SYS0_Devices[i].d14_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_15,
+				INFRA_AO_SYS0_Devices[i].d15_permission);
+	}
+
+	infra_ao_size = ARRAY_SIZE(INFRA_AO_SYS1_Devices);
+
+	for (i = 0; i < infra_ao_size; i++) {
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_0,
+				INFRA_AO_SYS1_Devices[i].d0_permission);		/* APMCU */
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_1,
+				INFRA_AO_SYS1_Devices[i].d1_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_2,
+				INFRA_AO_SYS1_Devices[i].d2_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_3,
+				INFRA_AO_SYS1_Devices[i].d3_permission);
+	}
+
+	infra_ao_size = ARRAY_SIZE(INFRA_AO_SYS2_Devices);
+
+	for (i = 0; i < infra_ao_size; i++) {
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_0,
+				INFRA_AO_SYS2_Devices[i].d0_permission);		/* APMCU */
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_1,
+				INFRA_AO_SYS2_Devices[i].d1_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_2,
+				INFRA_AO_SYS2_Devices[i].d2_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_3,
+				INFRA_AO_SYS2_Devices[i].d3_permission);
+	}
+}
+
+static void set_peri_ao_apc(void)
+{
+	uint32_t peri_ao_size;
+	uint32_t i;
+
+	peri_ao_size = ARRAY_SIZE(PERI_AO_SYS0_Devices);
+
+	for (i = 0; i < peri_ao_size; i++) {
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_0,
+				PERI_AO_SYS0_Devices[i].d0_permission);			/* APMCU */
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_1,
+				PERI_AO_SYS0_Devices[i].d1_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_2,
+				PERI_AO_SYS0_Devices[i].d2_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_3,
+				PERI_AO_SYS0_Devices[i].d3_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_4,
+				PERI_AO_SYS0_Devices[i].d4_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_5,
+				PERI_AO_SYS0_Devices[i].d5_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_6,
+				PERI_AO_SYS0_Devices[i].d6_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_7,
+				PERI_AO_SYS0_Devices[i].d7_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_8,
+				PERI_AO_SYS0_Devices[i].d8_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_9,
+				PERI_AO_SYS0_Devices[i].d9_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_10,
+				PERI_AO_SYS0_Devices[i].d10_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_11,
+				PERI_AO_SYS0_Devices[i].d11_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_12,
+				PERI_AO_SYS0_Devices[i].d12_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_13,
+				PERI_AO_SYS0_Devices[i].d13_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_14,
+				PERI_AO_SYS0_Devices[i].d14_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_15,
+				PERI_AO_SYS0_Devices[i].d15_permission);
+	}
+
+	peri_ao_size = ARRAY_SIZE(PERI_AO_SYS1_Devices);
+
+	for (i = 0; i < peri_ao_size; i++) {
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_0,
+				PERI_AO_SYS1_Devices[i].d0_permission);			/* APMCU */
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_1,
+				PERI_AO_SYS1_Devices[i].d1_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_2,
+				PERI_AO_SYS1_Devices[i].d2_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_3,
+				PERI_AO_SYS1_Devices[i].d3_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_4,
+				PERI_AO_SYS1_Devices[i].d4_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_5,
+				PERI_AO_SYS1_Devices[i].d5_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_6,
+				PERI_AO_SYS1_Devices[i].d6_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_7,
+				PERI_AO_SYS1_Devices[i].d7_permission);
+	}
+
+	peri_ao_size = ARRAY_SIZE(PERI_AO_SYS2_Devices);
+
+	for (i = 0; i < peri_ao_size; i++) {
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_0,
+				PERI_AO_SYS2_Devices[i].d0_permission);			/* APMCU */
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_1,
+				PERI_AO_SYS2_Devices[i].d1_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_2,
+				PERI_AO_SYS2_Devices[i].d2_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_3,
+				PERI_AO_SYS2_Devices[i].d3_permission);
+	}
+}
+
+static void set_peri_ao2_apc(void)
+{
+	uint32_t peri_ao2_size;
+	uint32_t i;
+
+	peri_ao2_size = ARRAY_SIZE(PERI_AO2_SYS0_Devices);
+
+	for (i = 0; i < peri_ao2_size; i++) {
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_0,
+				PERI_AO2_SYS0_Devices[i].d0_permission);		/* APMCU */
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_1,
+				PERI_AO2_SYS0_Devices[i].d1_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_2,
+				PERI_AO2_SYS0_Devices[i].d2_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_3,
+				PERI_AO2_SYS0_Devices[i].d3_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_4,
+				PERI_AO2_SYS0_Devices[i].d4_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_5,
+				PERI_AO2_SYS0_Devices[i].d5_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_6,
+				PERI_AO2_SYS0_Devices[i].d6_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_7,
+				PERI_AO2_SYS0_Devices[i].d7_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_8,
+				PERI_AO2_SYS0_Devices[i].d8_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_9,
+				PERI_AO2_SYS0_Devices[i].d9_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_10,
+				PERI_AO2_SYS0_Devices[i].d10_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_11,
+				PERI_AO2_SYS0_Devices[i].d11_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_12,
+				PERI_AO2_SYS0_Devices[i].d12_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_13,
+				PERI_AO2_SYS0_Devices[i].d13_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_14,
+				PERI_AO2_SYS0_Devices[i].d14_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_15,
+				PERI_AO2_SYS0_Devices[i].d15_permission);
+	}
+}
+
+static void set_peri_par_ao_apc(void)
+{
+	uint32_t peri_par_ao_size;
+	uint32_t i;
+
+	peri_par_ao_size = ARRAY_SIZE(PERI_PAR_AO_SYS0_Devices);
+
+	for (i = 0; i < peri_par_ao_size; i++) {
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_0,
+				PERI_PAR_AO_SYS0_Devices[i].d0_permission);		/* APMCU */
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_1,
+				PERI_PAR_AO_SYS0_Devices[i].d1_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_2,
+				PERI_PAR_AO_SYS0_Devices[i].d2_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_3,
+				PERI_PAR_AO_SYS0_Devices[i].d3_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_4,
+				PERI_PAR_AO_SYS0_Devices[i].d4_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_5,
+				PERI_PAR_AO_SYS0_Devices[i].d5_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_6,
+				PERI_PAR_AO_SYS0_Devices[i].d6_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_7,
+				PERI_PAR_AO_SYS0_Devices[i].d7_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_8,
+				PERI_PAR_AO_SYS0_Devices[i].d8_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_9,
+				PERI_PAR_AO_SYS0_Devices[i].d9_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_10,
+				PERI_PAR_AO_SYS0_Devices[i].d10_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_11,
+				PERI_PAR_AO_SYS0_Devices[i].d11_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_12,
+				PERI_PAR_AO_SYS0_Devices[i].d12_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_13,
+				PERI_PAR_AO_SYS0_Devices[i].d13_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_14,
+				PERI_PAR_AO_SYS0_Devices[i].d14_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_15,
+				PERI_PAR_AO_SYS0_Devices[i].d15_permission);
+	}
+}
+
+static void set_extra_apc(void)
+{
+#ifdef MTK_DEBUGSYS_LOCK
+	/* Block debugsys to avoid privilege escalation (user load only) */
+	set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, DEVAPC_DEBUGSYS_INDEX,
+			DOMAIN_0, SEC_RW_NS_R);
+#endif
+}
+
+void devapc_init(void)
+{
+	/* Initial Permission */
+	set_infra_ao_apc();
+	set_peri_ao_apc();
+	set_peri_ao2_apc();
+	set_peri_par_ao_apc();
+
+	/* Extra Permission */
+	set_extra_apc();
+
+	/* Dump Permission */
+	dump_infra_ao_apc();
+	dump_peri_ao_apc();
+	dump_peri_ao2_apc();
+	dump_peri_par_ao_apc();
+
+	INFO("[DEVAPC] %s done\n", __func__);
+}
diff --git a/plat/mediatek/mt8192/drivers/devapc/devapc.h b/plat/mediatek/mt8192/drivers/devapc/devapc.h
new file mode 100644
index 0000000..9033a0f
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/devapc/devapc.h
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DEVAPC_H
+#define DEVAPC_H
+
+#include <stdint.h>
+#include <platform_def.h>
+
+/******************************************************************************
+ * FUNCTION DEFINITION
+ ******************************************************************************/
+void devapc_init(void);
+
+/******************************************************************************
+ * STRUCTURE DEFINITION
+ ******************************************************************************/
+enum DEVAPC_PERM_TYPE {
+	NO_PROTECTION = 0,
+	SEC_RW_ONLY,
+	SEC_RW_NS_R,
+	FORBIDDEN,
+	PERM_NUM,
+};
+
+enum DOMAIN_ID {
+	DOMAIN_0 = 0,
+	DOMAIN_1,
+	DOMAIN_2,
+	DOMAIN_3,
+	DOMAIN_4,
+	DOMAIN_5,
+	DOMAIN_6,
+	DOMAIN_7,
+	DOMAIN_8,
+	DOMAIN_9,
+	DOMAIN_10,
+	DOMAIN_11,
+	DOMAIN_12,
+	DOMAIN_13,
+	DOMAIN_14,
+	DOMAIN_15,
+};
+
+/* Slave Type */
+enum DEVAPC_SLAVE_TYPE_SIMPLE {
+	SLAVE_TYPE_INFRA = 0,
+	SLAVE_TYPE_PERI,
+	SLAVE_TYPE_PERI2,
+	SLAVE_TYPE_PERI_PAR,
+};
+
+enum DEVAPC_SYS_INDEX {
+	DEVAPC_SYS0 = 0,
+	DEVAPC_SYS1,
+	DEVAPC_SYS2,
+};
+
+enum DEVAPC_SLAVE_TYPE {
+	SLAVE_TYPE_INFRA_AO_SYS0 = 0,
+	SLAVE_TYPE_INFRA_AO_SYS1,
+	SLAVE_TYPE_INFRA_AO_SYS2,
+	SLAVE_TYPE_PERI_AO_SYS0,
+	SLAVE_TYPE_PERI_AO_SYS1,
+	SLAVE_TYPE_PERI_AO_SYS2,
+	SLAVE_TYPE_PERI_AO2_SYS0,
+	SLAVE_TYPE_PERI_PAR_AO_SYS0,
+};
+
+/* Slave Num */
+enum DEVAPC_SLAVE_NUM {
+	SLAVE_NUM_INFRA_AO_SYS0 = 23,
+	SLAVE_NUM_INFRA_AO_SYS1 = 256,
+	SLAVE_NUM_INFRA_AO_SYS2 = 70,
+	SLAVE_NUM_PERI_AO_SYS0 = 105,
+	SLAVE_NUM_PERI_AO_SYS1 = 66,
+	SLAVE_NUM_PERI_AO_SYS2 = 1,
+	SLAVE_NUM_PERI_AO2_SYS0 = 115,
+	SLAVE_NUM_PERI_PAR_AO_SYS0 = 27,
+};
+
+enum DEVAPC_SYS_DOM_NUM {
+	DOM_NUM_INFRA_AO_SYS0 = 16,
+	DOM_NUM_INFRA_AO_SYS1 = 4,
+	DOM_NUM_INFRA_AO_SYS2 = 4,
+	DOM_NUM_PERI_AO_SYS0 = 16,
+	DOM_NUM_PERI_AO_SYS1 = 8,
+	DOM_NUM_PERI_AO_SYS2 = 4,
+	DOM_NUM_PERI_AO2_SYS0 = 16,
+	DOM_NUM_PERI_PAR_AO_SYS0 = 16,
+};
+
+enum DEVAPC_CFG_INDEX {
+	DEVAPC_DEBUGSYS_INDEX = 57,
+};
+
+struct APC_INFRA_PERI_DOM_16 {
+	unsigned char d0_permission;
+	unsigned char d1_permission;
+	unsigned char d2_permission;
+	unsigned char d3_permission;
+	unsigned char d4_permission;
+	unsigned char d5_permission;
+	unsigned char d6_permission;
+	unsigned char d7_permission;
+	unsigned char d8_permission;
+	unsigned char d9_permission;
+	unsigned char d10_permission;
+	unsigned char d11_permission;
+	unsigned char d12_permission;
+	unsigned char d13_permission;
+	unsigned char d14_permission;
+	unsigned char d15_permission;
+};
+
+struct APC_INFRA_PERI_DOM_8 {
+	unsigned char d0_permission;
+	unsigned char d1_permission;
+	unsigned char d2_permission;
+	unsigned char d3_permission;
+	unsigned char d4_permission;
+	unsigned char d5_permission;
+	unsigned char d6_permission;
+	unsigned char d7_permission;
+};
+
+struct APC_INFRA_PERI_DOM_4 {
+	unsigned char d0_permission;
+	unsigned char d1_permission;
+	unsigned char d2_permission;
+	unsigned char d3_permission;
+};
+
+#define DAPC_INFRA_AO_SYS0_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \
+		PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \
+		PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \
+		PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \
+		PERM_ATTR14, PERM_ATTR15) \
+	{(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \
+	(unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \
+	(unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \
+	(unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7, \
+	(unsigned char)PERM_ATTR8, (unsigned char)PERM_ATTR9, \
+	(unsigned char)PERM_ATTR10, (unsigned char)PERM_ATTR11, \
+	(unsigned char)PERM_ATTR12, (unsigned char)PERM_ATTR13, \
+	(unsigned char)PERM_ATTR14, (unsigned char)PERM_ATTR15}
+
+#define DAPC_INFRA_AO_SYS1_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \
+		PERM_ATTR2, PERM_ATTR3) \
+	{(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \
+	(unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3}
+
+#define DAPC_PERI_AO_SYS1_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \
+		PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \
+		PERM_ATTR6, PERM_ATTR7) \
+	{(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \
+	(unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \
+	(unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \
+	(unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7}
+
+#define DAPC_INFRA_AO_SYS2_ATTR(...)	DAPC_INFRA_AO_SYS1_ATTR(__VA_ARGS__)
+#define DAPC_PERI_AO_SYS0_ATTR(...)	DAPC_INFRA_AO_SYS0_ATTR(__VA_ARGS__)
+#define DAPC_PERI_AO_SYS2_ATTR(...)	DAPC_INFRA_AO_SYS1_ATTR(__VA_ARGS__)
+#define DAPC_PERI_AO2_SYS0_ATTR(...)	DAPC_INFRA_AO_SYS0_ATTR(__VA_ARGS__)
+#define DAPC_PERI_PAR_AO_SYS0_ATTR(...)	DAPC_INFRA_AO_SYS0_ATTR(__VA_ARGS__)
+
+/******************************************************************************
+ * UTILITY DEFINITION
+ ******************************************************************************/
+#define devapc_writel(VAL, REG)		mmio_write_32((uintptr_t)REG, VAL)
+#define devapc_readl(REG)		mmio_read_32((uintptr_t)REG)
+
+/******************************************************************************/
+/* Device APC AO for INFRA AO */
+#define DEVAPC_INFRA_AO_SYS0_D0_APC_0		(DEVAPC_INFRA_AO_BASE + 0x0000)
+#define DEVAPC_INFRA_AO_SYS1_D0_APC_0		(DEVAPC_INFRA_AO_BASE + 0x1000)
+#define DEVAPC_INFRA_AO_SYS2_D0_APC_0		(DEVAPC_INFRA_AO_BASE + 0x2000)
+
+#define DEVAPC_INFRA_AO_MAS_SEC_0		(DEVAPC_INFRA_AO_BASE + 0x0A00)
+
+/******************************************************************************/
+/* Device APC AO for PERI AO */
+#define DEVAPC_PERI_AO_SYS0_D0_APC_0		(DEVAPC_PERI_AO_BASE + 0x0000)
+#define DEVAPC_PERI_AO_SYS1_D0_APC_0		(DEVAPC_PERI_AO_BASE + 0x1000)
+#define DEVAPC_PERI_AO_SYS2_D0_APC_0		(DEVAPC_PERI_AO_BASE + 0x2000)
+
+#define DEVAPC_PERI_AO_MAS_SEC_0		(DEVAPC_PERI_AO_BASE + 0x0A00)
+
+/******************************************************************************/
+/* Device APC AO for PERI AO2 */
+#define DEVAPC_PERI_AO2_SYS0_D0_APC_0		(DEVAPC_PERI_AO2_BASE + 0x0000)
+
+/******************************************************************************/
+/* Device APC AO for PERI PAR AO */
+#define DEVAPC_PERI_PAR_AO_SYS0_D0_APC_0	(DEVAPC_PERI_PAR_AO_BASE + 0x0000)
+
+#define DEVAPC_PERI_PAR_AO_MAS_SEC_0		(DEVAPC_PERI_PAR_AO_BASE + 0x0A00)
+
+/******************************************************************************/
+
+
+/******************************************************************************
+ * Variable DEFINITION
+ ******************************************************************************/
+#define MOD_NO_IN_1_DEVAPC              16
+
+#endif /* DEVAPC_H */
+
diff --git a/plat/mediatek/mt8192/drivers/gpio/mtgpio.c b/plat/mediatek/mt8192/drivers/gpio/mtgpio.c
index e07b75a..c78332d 100644
--- a/plat/mediatek/mt8192/drivers/gpio/mtgpio.c
+++ b/plat/mediatek/mt8192/drivers/gpio/mtgpio.c
@@ -5,94 +5,17 @@
  */
 
 #include <assert.h>
-#include <common/debug.h>
-#include <drivers/delay_timer.h>
-#include <drivers/gpio.h>
-#include <lib/mmio.h>
 #include <mtgpio.h>
 #include <platform_def.h>
 
-/******************************************************************************
- *Macro Definition
- ******************************************************************************/
-#define GPIO_MODE_BITS		4
-#define MAX_GPIO_MODE_PER_REG	8
-#define MAX_GPIO_REG_BITS	32
-#define DIR_BASE		(GPIO_BASE + 0x000)
-#define DOUT_BASE		(GPIO_BASE + 0x100)
-#define DIN_BASE		(GPIO_BASE + 0x200)
-#define MODE_BASE		(GPIO_BASE + 0x300)
-#define SET			0x4
-#define CLR			0x8
-
-static void mt_set_gpio_dir_chip(uint32_t pin, int dir)
-{
-	uint32_t pos, bit;
-
-	assert(pin < MAX_GPIO_PIN);
-	assert(dir < MT_GPIO_DIR_MAX);
-
-	pos = pin / MAX_GPIO_REG_BITS;
-	bit = pin % MAX_GPIO_REG_BITS;
-
-	if (dir == MT_GPIO_DIR_IN) {
-		mmio_write_32(DIR_BASE + 0x10U * pos + CLR, 1U << bit);
-	} else {
-		mmio_write_32(DIR_BASE + 0x10U * pos + SET, 1U << bit);
-	}
-}
-
-static int mt_get_gpio_dir_chip(uint32_t pin)
-{
-	uint32_t pos, bit;
-	uint32_t reg;
-
-	assert(pin < MAX_GPIO_PIN);
-
-	pos = pin / MAX_GPIO_REG_BITS;
-	bit = pin % MAX_GPIO_REG_BITS;
-
-	reg = mmio_read_32(DIR_BASE + 0x10U * pos);
-	return (((reg & (1U << bit)) != 0U) ? MT_GPIO_DIR_OUT : MT_GPIO_DIR_IN);
-}
-
-static void mt_set_gpio_out_chip(uint32_t pin, int output)
-{
-	uint32_t pos, bit;
-
-	assert(pin < MAX_GPIO_PIN);
-	assert(output < MT_GPIO_OUT_MAX);
-
-	pos = pin / MAX_GPIO_REG_BITS;
-	bit = pin % MAX_GPIO_REG_BITS;
-
-	if (output == MT_GPIO_OUT_ZERO) {
-		mmio_write_32(DOUT_BASE + 0x10U * pos + CLR, 1U << bit);
-	} else {
-		mmio_write_32(DOUT_BASE + 0x10U * pos + SET, 1U << bit);
-	}
-}
-
-static int mt_get_gpio_in_chip(uint32_t pin)
-{
-	uint32_t pos, bit;
-	uint32_t reg;
-
-	assert(pin < MAX_GPIO_PIN);
-
-	pos = pin / MAX_GPIO_REG_BITS;
-	bit = pin % MAX_GPIO_REG_BITS;
-
-	reg = mmio_read_32(DIN_BASE + 0x10U * pos);
-	return (((reg & (1U << bit)) != 0U) ? 1 : 0);
-}
-
-static uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
+uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
 {
 	uintptr_t reg_addr = 0U;
 	struct mt_pin_info gpio_info;
 
-	gpio_info = mt8192_pin_infos[pin];
+	assert(pin < MAX_GPIO_PIN);
+
+	gpio_info = mt_pin_infos[pin];
 
 	switch (gpio_info.base & 0x0f) {
 	case 0:
@@ -128,213 +51,3 @@
 
 	return reg_addr;
 }
-
-static void mt_gpio_set_spec_pull_pupd(uint32_t pin, int enable,
-			       int select)
-{
-	uintptr_t reg1;
-	uintptr_t reg2;
-	struct mt_pin_info gpio_info;
-
-	gpio_info = mt8192_pin_infos[pin];
-	uint32_t bit = gpio_info.bit;
-
-	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
-	reg2 = reg1 + (gpio_info.base & 0xf0);
-	if (enable == MT_GPIO_PULL_ENABLE) {
-		mmio_write_32(reg2 + SET, (1U << bit));
-		if (select == MT_GPIO_PULL_DOWN) {
-			mmio_write_32(reg1 + SET, (1U << bit));
-		} else {
-			mmio_write_32(reg1 + CLR, (1U << bit));
-		}
-	} else {
-		mmio_write_32(reg2 + CLR, (1U << bit));
-		mmio_write_32((reg2 + 0x010U) + CLR, (1U << bit));
-	}
-}
-
-static void mt_gpio_set_pull_pu_pd(uint32_t pin, int enable,
-				 int select)
-{
-	uintptr_t reg1;
-	uintptr_t reg2;
-	struct mt_pin_info gpio_info;
-
-	gpio_info = mt8192_pin_infos[pin];
-	uint32_t bit = gpio_info.bit;
-
-	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
-	reg2 = reg1 - (gpio_info.base & 0xf0);
-
-	if (enable == MT_GPIO_PULL_ENABLE) {
-		if (select == MT_GPIO_PULL_DOWN) {
-			mmio_write_32(reg1 + CLR, (1U << bit));
-			mmio_write_32(reg2 + SET, (1U << bit));
-		} else {
-			mmio_write_32(reg2 + CLR, (1U << bit));
-			mmio_write_32(reg1 + SET, (1U << bit));
-		}
-	} else {
-		mmio_write_32(reg1 + CLR, (1U << bit));
-		mmio_write_32(reg2 + CLR, (1U << bit));
-	}
-}
-
-static void mt_gpio_set_pull_chip(uint32_t pin, int enable,
-		   int select)
-{
-	struct mt_pin_info gpio_info;
-
-	gpio_info = mt8192_pin_infos[pin];
-	if (gpio_info.flag) {
-		mt_gpio_set_spec_pull_pupd(pin, enable, select);
-	} else {
-		mt_gpio_set_pull_pu_pd(pin, enable, select);
-	}
-}
-
-static int mt_gpio_get_spec_pull_pupd(uint32_t pin)
-{
-	uintptr_t reg1;
-	uintptr_t reg2;
-	uint32_t r0;
-	uint32_t r1;
-
-	struct mt_pin_info gpio_info;
-
-	gpio_info = mt8192_pin_infos[pin];
-	uint32_t bit = gpio_info.bit;
-
-	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
-	reg2 = reg1 + (gpio_info.base & 0xf0);
-
-	r0 = (mmio_read_32(reg2) >> bit) & 1U;
-	r1 = (mmio_read_32(reg2 + 0x010) >> bit) & 1U;
-	if (r0 == 0U && r1 == 0U) {
-		return MT_GPIO_PULL_NONE;
-	} else {
-		if (mmio_read_32(reg1) & (1U << bit)) {
-			return MT_GPIO_PULL_DOWN;
-		} else {
-			return MT_GPIO_PULL_UP;
-		}
-	}
-}
-
-static int mt_gpio_get_pull_pu_pd(uint32_t pin)
-{
-	uintptr_t reg1;
-	uintptr_t reg2;
-	uint32_t pu;
-	uint32_t pd;
-
-	struct mt_pin_info gpio_info;
-
-	gpio_info = mt8192_pin_infos[pin];
-	uint32_t bit = gpio_info.bit;
-
-	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
-	reg2 = reg1 - (gpio_info.base & 0xf0);
-	pu = (mmio_read_32(reg1) >> bit) & 1U;
-	pd = (mmio_read_32(reg2) >> bit) & 1U;
-	if (pu == 1U) {
-		return MT_GPIO_PULL_UP;
-	} else if (pd == 1U) {
-		return MT_GPIO_PULL_DOWN;
-	} else {
-		return MT_GPIO_PULL_NONE;
-	}
-}
-
-static int mt_gpio_get_pull_chip(uint32_t pin)
-{
-	struct mt_pin_info gpio_info;
-
-	gpio_info = mt8192_pin_infos[pin];
-	if (gpio_info.flag) {
-		return mt_gpio_get_spec_pull_pupd(pin);
-	} else {
-		return mt_gpio_get_pull_pu_pd(pin);
-	}
-}
-
-static void mt_set_gpio_pull_select_chip(uint32_t pin, int sel)
-{
-	assert(pin < MAX_GPIO_PIN);
-
-	if (sel == MT_GPIO_PULL_NONE) {
-		mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_DISABLE, MT_GPIO_PULL_DOWN);
-	} else if (sel == MT_GPIO_PULL_UP) {
-		mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_UP);
-	} else if (sel == MT_GPIO_PULL_DOWN) {
-		mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_DOWN);
-	}
-}
-
-/* get pull-up or pull-down, regardless of resistor value */
-static int mt_get_gpio_pull_select_chip(uint32_t pin)
-{
-	assert(pin < MAX_GPIO_PIN);
-
-	return mt_gpio_get_pull_chip(pin);
-}
-
-static void mt_set_gpio_dir(int gpio, int direction)
-{
-	mt_set_gpio_dir_chip((uint32_t)gpio, direction);
-}
-
-static int mt_get_gpio_dir(int gpio)
-{
-	uint32_t pin;
-
-	pin = (uint32_t)gpio;
-	return mt_get_gpio_dir_chip(pin);
-}
-
-static void mt_set_gpio_pull(int gpio, int pull)
-{
-	uint32_t pin;
-
-	pin = (uint32_t)gpio;
-	mt_set_gpio_pull_select_chip(pin, pull);
-}
-
-static int mt_get_gpio_pull(int gpio)
-{
-	uint32_t pin;
-
-	pin = (uint32_t)gpio;
-	return mt_get_gpio_pull_select_chip(pin);
-}
-
-static void mt_set_gpio_out(int gpio, int value)
-{
-	uint32_t pin;
-
-	pin = (uint32_t)gpio;
-	mt_set_gpio_out_chip(pin, value);
-}
-
-static int mt_get_gpio_in(int gpio)
-{
-	uint32_t pin;
-
-	pin = (uint32_t)gpio;
-	return mt_get_gpio_in_chip(pin);
-}
-
-const gpio_ops_t mtgpio_ops = {
-	 .get_direction = mt_get_gpio_dir,
-	 .set_direction = mt_set_gpio_dir,
-	 .get_value = mt_get_gpio_in,
-	 .set_value = mt_set_gpio_out,
-	 .set_pull = mt_set_gpio_pull,
-	 .get_pull = mt_get_gpio_pull,
-};
-
-void plat_mt8192_gpio_init(void)
-{
-	gpio_init(&mtgpio_ops);
-}
diff --git a/plat/mediatek/mt8192/drivers/gpio/mtgpio.h b/plat/mediatek/mt8192/drivers/gpio/mtgpio.h
index ca0c964..d3aa24d 100644
--- a/plat/mediatek/mt8192/drivers/gpio/mtgpio.h
+++ b/plat/mediatek/mt8192/drivers/gpio/mtgpio.h
@@ -7,17 +7,7 @@
 #ifndef MT_GPIO_H
 #define MT_GPIO_H
 
-#include <stdbool.h>
-#include <stdint.h>
-
-#include <plat/common/common_def.h>
-
-/*  Error Code No. */
-#define RSUCCESS        0
-#define ERACCESS        1
-#define ERINVAL         2
-#define ERWRAPPER       3
-#define MAX_GPIO_PIN    MT_GPIO_BASE_MAX
+#include <mtgpio_common.h>
 
 /* Enumeration for GPIO pin */
 typedef enum GPIO_PIN {
@@ -54,110 +44,7 @@
 	MT_GPIO_BASE_MAX
 } GPIO_PIN;
 
-/* GPIO MODE CONTROL VALUE*/
-typedef enum {
-	GPIO_MODE_UNSUPPORTED = -1,
-	GPIO_MODE_GPIO  = 0,
-	GPIO_MODE_00    = 0,
-	GPIO_MODE_01,
-	GPIO_MODE_02,
-	GPIO_MODE_03,
-	GPIO_MODE_04,
-	GPIO_MODE_05,
-	GPIO_MODE_06,
-	GPIO_MODE_07,
-
-	GPIO_MODE_MAX,
-	GPIO_MODE_DEFAULT = GPIO_MODE_00,
-} GPIO_MODE;
-
-/* GPIO DIRECTION */
-typedef enum {
-	MT_GPIO_DIR_UNSUPPORTED = -1,
-	MT_GPIO_DIR_OUT    = 0,
-	MT_GPIO_DIR_IN     = 1,
-	MT_GPIO_DIR_MAX,
-	MT_GPIO_DIR_DEFAULT = MT_GPIO_DIR_IN,
-} GPIO_DIR;
-
-/* GPIO PULL ENABLE*/
-typedef enum {
-	MT_GPIO_PULL_EN_UNSUPPORTED = -1,
-	MT_GPIO_PULL_DISABLE   = 0,
-	MT_GPIO_PULL_ENABLE    = 1,
-	MT_GPIO_PULL_ENABLE_R0 = 2,
-	MT_GPIO_PULL_ENABLE_R1 = 3,
-	MT_GPIO_PULL_ENABLE_R0R1 = 4,
-
-	MT_GPIO_PULL_EN_MAX,
-	MT_GPIO_PULL_EN_DEFAULT = MT_GPIO_PULL_ENABLE,
-} GPIO_PULL_EN;
-
-/* GPIO PULL-UP/PULL-DOWN*/
-typedef enum {
-	MT_GPIO_PULL_UNSUPPORTED = -1,
-	MT_GPIO_PULL_NONE        = 0,
-	MT_GPIO_PULL_UP          = 1,
-	MT_GPIO_PULL_DOWN        = 2,
-	MT_GPIO_PULL_MAX,
-	MT_GPIO_PULL_DEFAULT = MT_GPIO_PULL_DOWN
-} GPIO_PULL;
-
-/* GPIO OUTPUT */
-typedef enum {
-	MT_GPIO_OUT_UNSUPPORTED = -1,
-	MT_GPIO_OUT_ZERO = 0,
-	MT_GPIO_OUT_ONE  = 1,
-
-	MT_GPIO_OUT_MAX,
-	MT_GPIO_OUT_DEFAULT = MT_GPIO_OUT_ZERO,
-	MT_GPIO_DATA_OUT_DEFAULT = MT_GPIO_OUT_ZERO,  /*compatible with DCT*/
-} GPIO_OUT;
-
-/* GPIO INPUT */
-typedef enum {
-	MT_GPIO_IN_UNSUPPORTED = -1,
-	MT_GPIO_IN_ZERO = 0,
-	MT_GPIO_IN_ONE  = 1,
-
-	MT_GPIO_IN_MAX,
-} GPIO_IN;
-
-typedef struct {
-	uint32_t val;
-	uint32_t set;
-	uint32_t rst;
-	uint32_t _align1;
-} VAL_REGS;
-
-typedef struct {
-	VAL_REGS dir[7];
-	uint8_t rsv00[144];
-	VAL_REGS dout[7];
-	uint8_t rsv01[144];
-	VAL_REGS din[7];
-	uint8_t rsv02[144];
-	VAL_REGS mode[28];
-} GPIO_REGS;
-
-
-#define PIN(_id, _flag, _bit, _base, _offset) {		\
-		.id = _id,				\
-		.flag = _flag,				\
-		.bit = _bit,				\
-		.base = _base,				\
-		.offset = _offset,			\
-	}
-
-struct mt_pin_info {
-	uint8_t id;
-	uint8_t flag;
-	uint8_t bit;
-	uint16_t base;
-	uint16_t offset;
-};
-
-static const struct mt_pin_info mt8192_pin_infos[] = {
+static const struct mt_pin_info mt_pin_infos[] = {
 	PIN(0, 0, 9, 0x23, 0xb0),
 	PIN(1, 0, 10, 0x23, 0xb0),
 	PIN(2, 0, 11, 0x23, 0xb0),
@@ -379,6 +266,4 @@
 	PIN(218, 0, 1, 0x14, 0x50),
 	PIN(219, 0, 2, 0x14, 0x50),
 };
-
-void plat_mt8192_gpio_init(void);
 #endif /* MT_GPIO_H */
diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c b/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c
index 809518f..e74d3e7 100644
--- a/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c
+++ b/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c
@@ -6,8 +6,8 @@
 
 #include <mt_lp_rm.h>
 #include <mt_lp_irqremain.h>
+#include <mtk_cirq.h>
 #include <plat_mtk_lpm.h>
-#include <plat_mt_cirq.h>
 
 #define EDMA0_IRQ_ID		U(448)
 #define MDLA_IRQ_ID		U(446)
diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c
index 92fd25f..f66b8ec 100644
--- a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c
+++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c
@@ -24,7 +24,7 @@
 
 #ifndef ATF_PLAT_CIRQ_UNSUPPORT
 #include <mt_gic_v3.h>
-#include <plat_mt_cirq.h>
+#include <mtk_cirq.h>
 #endif
 
 #define CONSTRAINT_BUS26M_ALLOW			\
diff --git a/plat/mediatek/mt8192/include/platform_def.h b/plat/mediatek/mt8192/include/platform_def.h
index 540463d..320124f 100644
--- a/plat/mediatek/mt8192/include/platform_def.h
+++ b/plat/mediatek/mt8192/include/platform_def.h
@@ -26,26 +26,30 @@
 #define MTK_MCDI_SRAM_BASE      0x11B000
 #define MTK_MCDI_SRAM_MAP_SIZE  0x1000
 
-#define TOPCKGEN_BASE    (IO_PHYS + 0x00000000)
-#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
-#define GPIO_BASE        (IO_PHYS + 0x00005000)
-#define SPM_BASE         (IO_PHYS + 0x00006000)
-#define APMIXEDSYS       (IO_PHYS + 0x0000C000)
-#define DVFSRC_BASE      (IO_PHYS + 0x00012000)
-#define PMIC_WRAP_BASE   (IO_PHYS + 0x00026000)
-#define EMI_BASE         (IO_PHYS + 0x00219000)
-#define EMI_MPU_BASE     (IO_PHYS + 0x00226000)
-#define SSPM_MBOX_BASE   (IO_PHYS + 0x00480000)
-#define IOCFG_RM_BASE    (IO_PHYS + 0x01C20000)
-#define IOCFG_BM_BASE    (IO_PHYS + 0x01D10000)
-#define IOCFG_BL_BASE    (IO_PHYS + 0x01D30000)
-#define IOCFG_BR_BASE    (IO_PHYS + 0x01D40000)
-#define IOCFG_LM_BASE    (IO_PHYS + 0x01E20000)
-#define IOCFG_LB_BASE    (IO_PHYS + 0x01E70000)
-#define IOCFG_RT_BASE    (IO_PHYS + 0x01EA0000)
-#define IOCFG_LT_BASE    (IO_PHYS + 0x01F20000)
-#define IOCFG_TL_BASE    (IO_PHYS + 0x01F30000)
-#define MMSYS_BASE       (IO_PHYS + 0x04000000)
+#define TOPCKGEN_BASE            (IO_PHYS + 0x00000000)
+#define INFRACFG_AO_BASE         (IO_PHYS + 0x00001000)
+#define GPIO_BASE                (IO_PHYS + 0x00005000)
+#define SPM_BASE                 (IO_PHYS + 0x00006000)
+#define APMIXEDSYS               (IO_PHYS + 0x0000C000)
+#define DVFSRC_BASE              (IO_PHYS + 0x00012000)
+#define PMIC_WRAP_BASE           (IO_PHYS + 0x00026000)
+#define DEVAPC_INFRA_AO_BASE     (IO_PHYS + 0x00030000)
+#define DEVAPC_PERI_AO_BASE      (IO_PHYS + 0x00034000)
+#define DEVAPC_PERI_AO2_BASE     (IO_PHYS + 0x00038000)
+#define DEVAPC_PERI_PAR_AO_BASE  (IO_PHYS + 0x0003C000)
+#define EMI_BASE                 (IO_PHYS + 0x00219000)
+#define EMI_MPU_BASE             (IO_PHYS + 0x00226000)
+#define SSPM_MBOX_BASE           (IO_PHYS + 0x00480000)
+#define IOCFG_RM_BASE            (IO_PHYS + 0x01C20000)
+#define IOCFG_BM_BASE            (IO_PHYS + 0x01D10000)
+#define IOCFG_BL_BASE            (IO_PHYS + 0x01D30000)
+#define IOCFG_BR_BASE            (IO_PHYS + 0x01D40000)
+#define IOCFG_LM_BASE            (IO_PHYS + 0x01E20000)
+#define IOCFG_LB_BASE            (IO_PHYS + 0x01E70000)
+#define IOCFG_RT_BASE            (IO_PHYS + 0x01EA0000)
+#define IOCFG_LT_BASE            (IO_PHYS + 0x01F20000)
+#define IOCFG_TL_BASE            (IO_PHYS + 0x01F30000)
+#define MMSYS_BASE               (IO_PHYS + 0x04000000)
 /*******************************************************************************
  * UART related constants
  ******************************************************************************/
@@ -61,13 +65,19 @@
 #define SYS_COUNTER_FREQ_IN_MHZ      13
 
 /*******************************************************************************
- * GIC-400 & interrupt handling related constants
+ * GIC-600 & interrupt handling related constants
  ******************************************************************************/
 
 /* Base MTK_platform compatible GIC memory map */
 #define BASE_GICD_BASE        MT_GIC_BASE
 #define MT_GIC_RDIST_BASE     (MT_GIC_BASE + 0x40000)
 
+#define SYS_CIRQ_BASE         (IO_PHYS + 0x204000)
+#define CIRQ_REG_NUM          14
+#define CIRQ_IRQ_NUM          439
+#define CIRQ_SPI_START        64
+#define MD_WDT_IRQ_BIT_ID     110
+
 /*******************************************************************************
  * Platform binary types for linking
  ******************************************************************************/
diff --git a/plat/mediatek/mt8192/include/rtc.h b/plat/mediatek/mt8192/include/rtc.h
new file mode 100644
index 0000000..a9c7bc8
--- /dev/null
+++ b/plat/mediatek/mt8192/include/rtc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RTC_H
+#define RTC_H
+
+#include <rtc_mt6359p.h>
+
+#endif  /* RTC_H */
diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk
index e45f649..1a57ea8 100644
--- a/plat/mediatek/mt8192/platform.mk
+++ b/plat/mediatek/mt8192/platform.mk
@@ -8,19 +8,22 @@
 MTK_PLAT_SOC  := ${MTK_PLAT}/${PLAT}
 
 PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
-                 -I${MTK_PLAT}/common/drivers/uart/                \
+                 -I${MTK_PLAT}/common/drivers/gic600/             \
+                 -I${MTK_PLAT}/common/drivers/gpio/               \
+                 -I${MTK_PLAT}/common/drivers/rtc/                \
+                 -I${MTK_PLAT}/common/drivers/timer/              \
+                 -I${MTK_PLAT}/common/drivers/uart/               \
                  -I${MTK_PLAT}/common/lpm/                        \
                  -I${MTK_PLAT_SOC}/include/                       \
                  -I${MTK_PLAT_SOC}/drivers/                       \
                  -I${MTK_PLAT_SOC}/drivers/dcm                    \
+                 -I${MTK_PLAT_SOC}/drivers/devapc                 \
                  -I${MTK_PLAT_SOC}/drivers/emi_mpu/               \
                  -I${MTK_PLAT_SOC}/drivers/gpio/                  \
                  -I${MTK_PLAT_SOC}/drivers/mcdi/                  \
                  -I${MTK_PLAT_SOC}/drivers/pmic/                  \
                  -I${MTK_PLAT_SOC}/drivers/ptp3/                  \
-                 -I${MTK_PLAT_SOC}/drivers/rtc/                   \
-                 -I${MTK_PLAT_SOC}/drivers/spmc/                  \
-                 -I${MTK_PLAT_SOC}/drivers/timer/
+                 -I${MTK_PLAT_SOC}/drivers/spmc/
 
 GICV3_SUPPORT_GIC600        :=      1
 include drivers/arm/gic/v3/gicv3.mk
@@ -40,10 +43,15 @@
                    lib/cpus/aarch64/cortex_a55.S                         \
                    lib/cpus/aarch64/cortex_a76.S                         \
                    plat/common/plat_gicv3.c                              \
+                   ${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c         \
+                   ${MTK_PLAT}/common/drivers/gpio/mtgpio_common.c       \
                    ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \
                    ${MTK_PLAT}/common/drivers/rtc/rtc_common.c           \
+                   ${MTK_PLAT}/common/drivers/rtc/rtc_mt6359p.c          \
+                   ${MTK_PLAT}/common/drivers/timer/mt_timer.c           \
                    ${MTK_PLAT}/common/drivers/uart/uart.c                \
                    ${MTK_PLAT}/common/lpm/mt_lp_rm.c                     \
+                   ${MTK_PLAT}/common/mtk_cirq.c                         \
                    ${MTK_PLAT}/common/mtk_plat_common.c                  \
                    ${MTK_PLAT}/common/mtk_sip_svc.c                      \
                    ${MTK_PLAT}/common/params_setup.c                     \
@@ -51,14 +59,12 @@
                    ${MTK_PLAT_SOC}/aarch64/plat_helpers.S                \
                    ${MTK_PLAT_SOC}/bl31_plat_setup.c                     \
                    ${MTK_PLAT_SOC}/drivers/pmic/pmic.c                   \
-                   ${MTK_PLAT_SOC}/drivers/rtc/rtc.c                     \
                    ${MTK_PLAT_SOC}/plat_pm.c                             \
                    ${MTK_PLAT_SOC}/plat_topology.c                       \
-                   ${MTK_PLAT_SOC}/plat_mt_gic.c                         \
-                   ${MTK_PLAT_SOC}/plat_mt_cirq.c                        \
                    ${MTK_PLAT_SOC}/plat_sip_calls.c                      \
                    ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c                 \
                    ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c           \
+                   ${MTK_PLAT_SOC}/drivers/devapc/devapc.c               \
                    ${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c             \
                    ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c                 \
                    ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c              \
@@ -66,8 +72,7 @@
                    ${MTK_PLAT_SOC}/drivers/mcdi/mt_lp_irqremain.c        \
                    ${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c                \
                    ${MTK_PLAT_SOC}/drivers/ptp3/mtk_ptp3_main.c          \
-                   ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c                 \
-                   ${MTK_PLAT_SOC}/drivers/timer/mt_timer.c
+                   ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c
 
 # Build SPM drivers
 include ${MTK_PLAT_SOC}/drivers/spm/build.mk
diff --git a/plat/mediatek/mt8195/aarch64/plat_helpers.S b/plat/mediatek/mt8195/aarch64/plat_helpers.S
new file mode 100644
index 0000000..a973f4d
--- /dev/null
+++ b/plat/mediatek/mt8195/aarch64/plat_helpers.S
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+	.globl plat_is_my_cpu_primary
+	.globl plat_my_core_pos
+	.globl plat_mediatek_calc_core_pos
+
+func plat_is_my_cpu_primary
+	mrs	x0, mpidr_el1
+	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
+	cmp	x0, #PLAT_PRIMARY_CPU
+	cset	x0, eq
+	ret
+endfunc plat_is_my_cpu_primary
+
+	/* -----------------------------------------------------
+	 *  unsigned int plat_my_core_pos(void)
+	 *  This function uses the plat_mediatek_calc_core_pos()
+	 *  definition to get the index of the calling CPU.
+	 * -----------------------------------------------------
+	 */
+func plat_my_core_pos
+	mrs	x0, mpidr_el1
+	b	plat_mediatek_calc_core_pos
+endfunc plat_my_core_pos
+
+	/* -----------------------------------------------------
+	 * unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr);
+	 *
+	 * In ARMv8.2, AFF2 is cluster id, AFF1 is core id and
+	 * AFF0 is thread id. There is only one cluster in ARMv8.2
+	 * and one thread in current implementation.
+	 *
+	 * With this function: CorePos = CoreID (AFF1)
+	 * we do it with x0 = (x0 >> 8) & 0xff
+	 * -----------------------------------------------------
+	 */
+func plat_mediatek_calc_core_pos
+	mov	x1, #MPIDR_AFFLVL_MASK
+	and	x0, x1, x0, lsr #MPIDR_AFF1_SHIFT
+	ret
+endfunc plat_mediatek_calc_core_pos
diff --git a/plat/mediatek/mt8195/aarch64/platform_common.c b/plat/mediatek/mt8195/aarch64/platform_common.c
new file mode 100644
index 0000000..745e547
--- /dev/null
+++ b/plat/mediatek/mt8195/aarch64/platform_common.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/xlat_tables/xlat_tables_v2.h>
+
+#include <platform_def.h>
+
+/* Table of regions to map using the MMU.  */
+const mmap_region_t plat_mmap[] = {
+	/* for TF text, RO, RW */
+	MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	{ 0 }
+};
+
+/*******************************************************************************
+ * Macro generating the code for the function setting up the pagetables as per
+ * the platform memory map & initialize the mmu, for the given exception level
+ ******************************************************************************/
+void plat_configure_mmu_el3(uintptr_t total_base,
+			    uintptr_t total_size,
+			    uintptr_t ro_start,
+			    uintptr_t ro_limit)
+{
+	mmap_add_region(total_base, total_base, total_size,
+			MT_RW_DATA | MT_SECURE);
+	mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
+			MT_CODE | MT_SECURE);
+	mmap_add(plat_mmap);
+	init_xlat_tables();
+	enable_mmu_el3(0);
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+	return SYS_COUNTER_FREQ_IN_TICKS;
+}
diff --git a/plat/mediatek/mt8195/bl31_plat_setup.c b/plat/mediatek/mt8195/bl31_plat_setup.c
new file mode 100644
index 0000000..eaff349
--- /dev/null
+++ b/plat/mediatek/mt8195/bl31_plat_setup.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* System Includes */
+#include <assert.h>
+
+/* Project Includes */
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <common/desc_image_load.h>
+#include <drivers/generic_delay_timer.h>
+#include <drivers/ti/uart/uart_16550.h>
+#include <lib/coreboot.h>
+
+/* Platform Includes */
+#include <mt_gic_v3.h>
+#include <mt_timer.h>
+#include <mtgpio.h>
+#include <plat_params.h>
+#include <plat_private.h>
+
+static entry_point_info_t bl32_ep_info;
+static entry_point_info_t bl33_ep_info;
+
+/*******************************************************************************
+ * Return a pointer to the 'entry_point_info' structure of the next image for
+ * the security state specified. BL33 corresponds to the non-secure image type
+ * while BL32 corresponds to the secure image type. A NULL pointer is returned
+ * if the image does not exist.
+ ******************************************************************************/
+entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
+{
+	entry_point_info_t *next_image_info;
+
+	next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
+	assert(next_image_info->h.type == PARAM_EP);
+
+	/* None of the images on this platform can have 0x0 as the entrypoint */
+	if (next_image_info->pc) {
+		return next_image_info;
+	} else {
+		return NULL;
+	}
+}
+
+/*******************************************************************************
+ * Perform any BL31 early platform setup. Here is an opportunity to copy
+ * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
+ * are lost (potentially). This needs to be done before the MMU is initialized
+ * so that the memory layout can be used while creating page tables.
+ * BL2 has flushed this information to memory, so we are guaranteed to pick up
+ * good data.
+ ******************************************************************************/
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+				u_register_t arg2, u_register_t arg3)
+{
+	static console_t console;
+
+	params_early_setup(arg1);
+
+#if COREBOOT
+	if (coreboot_serial.type) {
+		console_16550_register(coreboot_serial.baseaddr,
+				       coreboot_serial.input_hertz,
+				       coreboot_serial.baud,
+				       &console);
+	}
+#else
+	console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console);
+#endif
+
+	NOTICE("MT8195 bl31_setup\n");
+
+	bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
+}
+
+
+/*******************************************************************************
+ * Perform any BL31 platform setup code
+ ******************************************************************************/
+void bl31_platform_setup(void)
+{
+	/* Initialize the GIC driver, CPU and distributor interfaces */
+	mt_gic_driver_init();
+	mt_gic_init();
+
+	mt_gpio_init();
+	mt_systimer_init();
+	generic_delay_timer_init();
+}
+
+/*******************************************************************************
+ * Perform the very early platform specific architectural setup here. At the
+ * moment this is only intializes the mmu in a quick and dirty way.
+ ******************************************************************************/
+void bl31_plat_arch_setup(void)
+{
+	plat_configure_mmu_el3(BL31_START,
+			       BL31_END - BL31_START,
+			       BL_CODE_BASE,
+			       BL_CODE_END);
+}
diff --git a/plat/mediatek/mt8195/drivers/gpio/mtgpio.c b/plat/mediatek/mt8195/drivers/gpio/mtgpio.c
new file mode 100644
index 0000000..daab84c
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/gpio/mtgpio.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <mtgpio.h>
+#include <platform_def.h>
+
+uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
+{
+	uintptr_t reg_addr = 0U;
+	struct mt_pin_info gpio_info;
+
+	assert(pin < MAX_GPIO_PIN);
+
+	gpio_info = mt_pin_infos[pin];
+
+	switch (gpio_info.base & 0x0f) {
+	case 0:
+		reg_addr = IOCFG_BM_BASE;
+		break;
+	case 1:
+		reg_addr = IOCFG_BL_BASE;
+		break;
+	case 2:
+		reg_addr = IOCFG_BR_BASE;
+		break;
+	case 3:
+		reg_addr = IOCFG_LM_BASE;
+		break;
+	case 4:
+		reg_addr = IOCFG_RB_BASE;
+		break;
+	case 5:
+		reg_addr = IOCFG_TL_BASE;
+		break;
+	default:
+		break;
+	}
+
+	return reg_addr;
+}
diff --git a/plat/mediatek/mt8195/drivers/gpio/mtgpio.h b/plat/mediatek/mt8195/drivers/gpio/mtgpio.h
new file mode 100644
index 0000000..88b4706
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/gpio/mtgpio.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GPIO_H
+#define MT_GPIO_H
+
+#include <mtgpio_common.h>
+
+/* Enumeration for GPIO pin */
+typedef enum GPIO_PIN {
+	GPIO_UNSUPPORTED = -1,
+
+	GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7,
+	GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14, GPIO15,
+	GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22, GPIO23,
+	GPIO24, GPIO25, GPIO26, GPIO27, GPIO28, GPIO29, GPIO30, GPIO31,
+	GPIO32, GPIO33, GPIO34, GPIO35, GPIO36, GPIO37, GPIO38, GPIO39,
+	GPIO40, GPIO41, GPIO42, GPIO43, GPIO44, GPIO45, GPIO46, GPIO47,
+	GPIO48, GPIO49, GPIO50, GPIO51, GPIO52, GPIO53, GPIO54, GPIO55,
+	GPIO56, GPIO57, GPIO58, GPIO59, GPIO60, GPIO61, GPIO62, GPIO63,
+	GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70, GPIO71,
+	GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78, GPIO79,
+	GPIO80, GPIO81, GPIO82, GPIO83, GPIO84, GPIO85, GPIO86, GPIO87,
+	GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94, GPIO95,
+	GPIO96, GPIO97, GPIO98, GPIO99, GPIO100, GPIO101, GPIO102, GPIO103,
+	GPIO104, GPIO105, GPIO106, GPIO107, GPIO108, GPIO109, GPIO110, GPIO111,
+	GPIO112, GPIO113, GPIO114, GPIO115, GPIO116, GPIO117, GPIO118, GPIO119,
+	GPIO120, GPIO121, GPIO122, GPIO123, GPIO124, GPIO125, GPIO126, GPIO127,
+	GPIO128, GPIO129, GPIO130, GPIO131, GPIO132, GPIO133, GPIO134, GPIO135,
+	GPIO136, GPIO137, GPIO138, GPIO139, GPIO140, GPIO141, GPIO142, GPIO143,
+	MT_GPIO_BASE_MAX
+} GPIO_PIN;
+
+static const struct mt_pin_info mt_pin_infos[] = {
+	PIN(0, 1, 0, 0x23, 0x60),
+	PIN(1, 1, 1, 0x23, 0x60),
+	PIN(2, 1, 2, 0x23, 0x60),
+	PIN(3, 1, 3, 0x23, 0x60),
+	PIN(4, 1, 4, 0x23, 0x60),
+	PIN(5, 1, 5, 0x23, 0x60),
+	PIN(6, 0, 6, 0x23, 0x70),
+	PIN(7, 0, 7, 0x23, 0x70),
+	PIN(8, 0, 13, 0x23, 0x70),
+	PIN(9, 0, 8, 0x23, 0x70),
+	PIN(10, 0, 14, 0x23, 0x70),
+	PIN(11, 0, 9, 0x23, 0x70),
+	PIN(12, 0, 15, 0x23, 0x70),
+	PIN(13, 0, 10, 0x23, 0x70),
+	PIN(14, 0, 16, 0x23, 0x70),
+	PIN(15, 0, 11, 0x23, 0x70),
+	PIN(16, 0, 17, 0x23, 0x70),
+	PIN(17, 0, 12, 0x23, 0x70),
+	PIN(18, 0, 5, 0x10, 0x60),
+	PIN(19, 0, 12, 0x10, 0x60),
+	PIN(20, 0, 11, 0x10, 0x60),
+	PIN(21, 0, 10, 0x10, 0x60),
+	PIN(22, 0, 0, 0x10, 0x60),
+	PIN(23, 0, 1, 0x10, 0x60),
+	PIN(24, 0, 2, 0x10, 0x60),
+	PIN(25, 0, 4, 0x10, 0x60),
+	PIN(26, 0, 3, 0x10, 0x60),
+	PIN(27, 0, 6, 0x10, 0x60),
+	PIN(28, 0, 7, 0x10, 0x60),
+	PIN(29, 0, 8, 0x10, 0x60),
+	PIN(30, 0, 9, 0x10, 0x60),
+	PIN(31, 0, 13, 0x21, 0xa0),
+	PIN(32, 0, 12, 0x21, 0xa0),
+	PIN(33, 0, 11, 0x21, 0xa0),
+	PIN(34, 0, 14, 0x21, 0xa0),
+	PIN(35, 0, 15, 0x21, 0xa0),
+	PIN(36, 0, 3, 0x21, 0xb0),
+	PIN(37, 0, 6, 0x21, 0xb0),
+	PIN(38, 0, 4, 0x21, 0xb0),
+	PIN(39, 0, 5, 0x21, 0xb0),
+	PIN(40, 0, 8, 0x21, 0xb0),
+	PIN(41, 0, 7, 0x21, 0xb0),
+	PIN(42, 0, 10, 0x21, 0xb0),
+	PIN(43, 0, 9, 0x21, 0xb0),
+	PIN(44, 0, 20, 0x21, 0xb0),
+	PIN(45, 0, 21, 0x21, 0xb0),
+	PIN(46, 0, 18, 0x21, 0xa0),
+	PIN(47, 0, 16, 0x21, 0xa0),
+	PIN(48, 0, 19, 0x21, 0xa0),
+	PIN(49, 0, 17, 0x21, 0xa0),
+	PIN(50, 0, 25, 0x21, 0xa0),
+	PIN(51, 0, 20, 0x21, 0xa0),
+	PIN(52, 0, 26, 0x21, 0xa0),
+	PIN(53, 0, 21, 0x21, 0xa0),
+	PIN(54, 0, 22, 0x21, 0xa0),
+	PIN(55, 0, 23, 0x21, 0xa0),
+	PIN(56, 0, 24, 0x21, 0xa0),
+	PIN(57, 0, 29, 0x21, 0xa0),
+	PIN(58, 0, 27, 0x21, 0xa0),
+	PIN(59, 0, 30, 0x21, 0xa0),
+	PIN(60, 0, 28, 0x21, 0xa0),
+	PIN(61, 0, 8, 0x21, 0xa0),
+	PIN(62, 0, 7, 0x21, 0xa0),
+	PIN(63, 0, 10, 0x21, 0xa0),
+	PIN(64, 0, 9, 0x21, 0xa0),
+	PIN(65, 0, 1, 0x21, 0xb0),
+	PIN(66, 0, 31, 0x21, 0xa0),
+	PIN(67, 0, 0, 0x21, 0xb0),
+	PIN(68, 0, 2, 0x21, 0xb0),
+	PIN(69, 0, 0, 0x21, 0xa0),
+	PIN(70, 0, 6, 0x21, 0xa0),
+	PIN(71, 0, 4, 0x21, 0xa0),
+	PIN(72, 0, 5, 0x21, 0xa0),
+	PIN(73, 0, 1, 0x21, 0xa0),
+	PIN(74, 0, 2, 0x21, 0xa0),
+	PIN(75, 0, 3, 0x21, 0xa0),
+	PIN(76, 0, 11, 0x21, 0xb0),
+	PIN(77, 1, 1, 0x22, 0x60),
+	PIN(78, 1, 2, 0x22, 0x60),
+	PIN(79, 1, 9, 0x22, 0x60),
+	PIN(80, 1, 10, 0x22, 0x60),
+	PIN(81, 1, 11, 0x22, 0x60),
+	PIN(82, 1, 12, 0x22, 0x60),
+	PIN(83, 1, 13, 0x22, 0x60),
+	PIN(84, 1, 14, 0x22, 0x60),
+	PIN(85, 1, 15, 0x22, 0x60),
+	PIN(86, 1, 16, 0x22, 0x60),
+	PIN(87, 1, 3, 0x22, 0x60),
+	PIN(88, 1, 4, 0x22, 0x60),
+	PIN(89, 1, 5, 0x22, 0x60),
+	PIN(90, 1, 6, 0x22, 0x60),
+	PIN(91, 1, 7, 0x22, 0x60),
+	PIN(92, 1, 8, 0x22, 0x60),
+	PIN(93, 1, 18, 0x22, 0x60),
+	PIN(94, 1, 19, 0x22, 0x60),
+	PIN(95, 1, 17, 0x22, 0x60),
+	PIN(96, 1, 0, 0x22, 0x60),
+	PIN(97, 0, 20, 0x22, 0x70),
+	PIN(98, 0, 28, 0x22, 0x70),
+	PIN(99, 0, 27, 0x22, 0x70),
+	PIN(100, 0, 30, 0x22, 0x70),
+	PIN(101, 0, 29, 0x22, 0x70),
+	PIN(102, 0, 0, 0x22, 0x70),
+	PIN(103, 0, 31, 0x22, 0x70),
+	PIN(104, 1, 25, 0x22, 0x60),
+	PIN(105, 1, 26, 0x22, 0x60),
+	PIN(106, 1, 23, 0x22, 0x60),
+	PIN(107, 1, 24, 0x22, 0x60),
+	PIN(108, 0, 22, 0x22, 0x70),
+	PIN(109, 0, 21, 0x22, 0x70),
+	PIN(110, 1, 1, 0x14, 0x20),
+	PIN(111, 1, 0, 0x14, 0x20),
+	PIN(112, 1, 2, 0x14, 0x20),
+	PIN(113, 1, 3, 0x14, 0x20),
+	PIN(114, 1, 4, 0x14, 0x20),
+	PIN(115, 1, 5, 0x14, 0x20),
+	PIN(116, 1, 9, 0x25, 0x50),
+	PIN(117, 1, 8, 0x25, 0x50),
+	PIN(118, 1, 7, 0x25, 0x50),
+	PIN(119, 1, 6, 0x25, 0x50),
+	PIN(120, 1, 11, 0x25, 0x50),
+	PIN(121, 1, 1, 0x25, 0x50),
+	PIN(122, 1, 0, 0x25, 0x50),
+	PIN(123, 1, 5, 0x25, 0x50),
+	PIN(124, 1, 4, 0x25, 0x50),
+	PIN(125, 1, 3, 0x25, 0x50),
+	PIN(126, 1, 2, 0x25, 0x50),
+	PIN(127, 1, 10, 0x25, 0x50),
+	PIN(128, 0, 3, 0x22, 0x70),
+	PIN(129, 0, 1, 0x22, 0x70),
+	PIN(130, 0, 4, 0x22, 0x70),
+	PIN(131, 0, 2, 0x22, 0x70),
+	PIN(132, 0, 13, 0x25, 0x60),
+	PIN(133, 0, 12, 0x25, 0x60),
+	PIN(134, 0, 15, 0x25, 0x60),
+	PIN(135, 0, 14, 0x25, 0x60),
+	PIN(136, 0, 13, 0x21, 0xb0),
+	PIN(137, 0, 12, 0x21, 0xb0),
+	PIN(138, 0, 15, 0x21, 0xb0),
+	PIN(139, 0, 14, 0x21, 0xb0),
+	PIN(140, 0, 17, 0x21, 0xb0),
+	PIN(141, 0, 16, 0x21, 0xb0),
+	PIN(142, 0, 19, 0x21, 0xb0),
+	PIN(143, 0, 18, 0x21, 0xb0),
+};
+#endif /* MT_GPIO_H */
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm.c b/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm.c
new file mode 100644
index 0000000..d6d4af7
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdint.h>
+
+#include <arch_helpers.h>
+#include <lib/psci/psci.h>
+#include <lib/spinlock.h>
+
+#include <mt_cpu_pm_cpc.h>
+#include <mt_mcdi.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+
+DEFINE_SYSREG_RW_FUNCS(dbgprcr_el1);
+
+static int plat_mt_lp_cpu_rc;
+
+static int pwr_state_prompt(unsigned int cpu, const psci_power_state_t *state)
+{
+	return 0;
+}
+
+static int pwr_state_reflect(unsigned int cpu, const psci_power_state_t *state)
+{
+	mtk_cpc_core_on_hint_clr(cpu);
+
+	if (IS_SYSTEM_SUSPEND_STATE(state)) {
+		mtk_cpc_time_sync();
+	}
+
+	return 0;
+}
+
+static int pwr_cpu_pwron(unsigned int cpu, const psci_power_state_t *state)
+{
+	return 0;
+}
+
+static int pwr_cpu_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
+{
+	/* clear DBGPRCR.CORENPDRQ to allow CPU power down  */
+	write_dbgprcr_el1(0ULL);
+
+	return 0;
+}
+
+static int pwr_cluster_pwron(unsigned int cpu, const psci_power_state_t *state)
+{
+	return 0;
+}
+
+static int pwr_cluster_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
+{
+	return 0;
+}
+
+static int pwr_mcusys_pwron(unsigned int cpu, const psci_power_state_t *state)
+{
+	if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) {
+		return -1;
+	}
+
+	mtk_cpc_mcusys_off_reflect();
+
+	return 0;
+}
+
+static int pwr_mcusys_pwron_finished(unsigned int cpu,
+					const psci_power_state_t *state)
+{
+	if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) {
+		return -1;
+	}
+
+	return 0;
+}
+
+static int pwr_mcusys_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
+{
+	if (!IS_MCUSYS_OFF_STATE(state)) {
+		goto mt_pwr_mcusysoff_break;
+	}
+
+	if (mcdi_try_init() != 0) { /* not ready to process mcusys-off */
+		goto mt_pwr_mcusysoff_break;
+	}
+
+	return 0;
+
+mt_pwr_mcusysoff_break:
+
+	plat_mt_lp_cpu_rc = -1;
+
+	return -1;
+}
+
+static const struct mt_lpm_tz plat_pm = {
+	.pwr_prompt			= pwr_state_prompt,
+	.pwr_reflect			= pwr_state_reflect,
+	.pwr_cpu_on			= pwr_cpu_pwron,
+	.pwr_cpu_dwn			= pwr_cpu_pwrdwn,
+	.pwr_cluster_on			= pwr_cluster_pwron,
+	.pwr_cluster_dwn		= pwr_cluster_pwrdwn,
+	.pwr_mcusys_dwn			= pwr_mcusys_pwrdwn,
+	.pwr_mcusys_on			= pwr_mcusys_pwron,
+	.pwr_mcusys_on_finished		= pwr_mcusys_pwron_finished
+};
+
+const struct mt_lpm_tz *mt_plat_cpu_pm_init(void)
+{
+	mtk_cpc_init();
+
+	if (mcdi_try_init() == 0) {
+		INFO("MCDI init done.\n");
+	}
+
+	return &plat_pm;
+}
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.c b/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.c
new file mode 100644
index 0000000..f8c51a1
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <drivers/delay_timer.h>
+
+#include <mt_cpu_pm_cpc.h>
+#include <mt_timer.h>
+
+struct mtk_cpc_dev {
+	int auto_off;
+	unsigned int auto_thres_tick;
+};
+
+static struct mtk_cpc_dev cpc;
+
+static int mtk_cpc_last_core_prot(uint32_t prot_req,
+				uint32_t resp_reg, uint32_t resp_ofs)
+{
+	uint32_t sta, retry;
+
+	retry = 0U;
+
+	while (retry++ < RETRY_CNT_MAX) {
+
+		mmio_write_32(CPC_MCUSYS_LAST_CORE_REQ, prot_req);
+
+		udelay(1U);
+
+		sta = (mmio_read_32(resp_reg) >> resp_ofs) & CPC_PROT_RESP_MASK;
+
+		if (sta == PROT_SUCCESS) {
+			return CPC_SUCCESS;
+		} else if (sta == PROT_GIVEUP) {
+			return CPC_ERR_FAIL;
+		}
+	}
+
+	return CPC_ERR_TIMEOUT;
+}
+
+int mtk_cpu_pm_mcusys_prot_aquire(void)
+{
+	return mtk_cpc_last_core_prot(
+			MCUSYS_PROT_SET,
+			CPC_MCUSYS_LAST_CORE_RESP,
+			MCUSYS_RESP_OFS);
+}
+
+void mtk_cpu_pm_mcusys_prot_release(void)
+{
+	mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, MCUSYS_PROT_CLR);
+}
+
+int mtk_cpu_pm_cluster_prot_aquire(unsigned int cluster)
+{
+	return mtk_cpc_last_core_prot(
+			CPUSYS_PROT_SET,
+			CPC_MCUSYS_MP_LAST_CORE_RESP,
+			CPUSYS_RESP_OFS);
+}
+
+void mtk_cpu_pm_cluster_prot_release(unsigned int cluster)
+{
+	mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, CPUSYS_PROT_CLR);
+}
+
+static void mtk_cpc_cluster_cnt_backup(void)
+{
+	uint32_t backup_cnt;
+	uint32_t curr_cnt;
+	uint32_t cnt_mask = GENMASK(14, 0);
+	uint32_t clr_mask = GENMASK(1, 0);
+
+	/* Single Cluster */
+	backup_cnt = mmio_read_32(CPC_CLUSTER_CNT_BACKUP);
+	curr_cnt = mmio_read_32(CPC_MCUSYS_CLUSTER_COUNTER);
+
+	/* Get off count if dormant count is 0 */
+	if ((curr_cnt & cnt_mask) == 0U) {
+		curr_cnt = (curr_cnt >> 16) & cnt_mask;
+	} else {
+		curr_cnt = curr_cnt & cnt_mask;
+	}
+
+	mmio_write_32(CPC_CLUSTER_CNT_BACKUP, backup_cnt + curr_cnt);
+	mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, clr_mask);
+}
+
+static inline void mtk_cpc_mcusys_off_en(void)
+{
+	mmio_write_32(CPC_MCUSYS_PWR_CTRL, 1U);
+}
+
+static inline void mtk_cpc_mcusys_off_dis(void)
+{
+	mmio_write_32(CPC_MCUSYS_PWR_CTRL, 0U);
+}
+
+void mtk_cpc_mcusys_off_reflect(void)
+{
+	mtk_cpc_mcusys_off_dis();
+	mtk_cpu_pm_mcusys_prot_release();
+}
+
+int mtk_cpc_mcusys_off_prepare(void)
+{
+	if (mtk_cpu_pm_mcusys_prot_aquire() != CPC_SUCCESS) {
+		return CPC_ERR_FAIL;
+	}
+
+	mtk_cpc_cluster_cnt_backup();
+	mtk_cpc_mcusys_off_en();
+
+	return CPC_SUCCESS;
+}
+
+void mtk_cpc_core_on_hint_set(unsigned int cpu)
+{
+	mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_SET, BIT(cpu));
+}
+
+void mtk_cpc_core_on_hint_clr(unsigned int cpu)
+{
+	mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_CLR, BIT(cpu));
+}
+
+static void mtk_cpc_dump_timestamp(void)
+{
+	uint32_t id;
+
+	for (id = 0U; id < CPC_TRACE_ID_NUM; id++) {
+		mmio_write_32(CPC_MCUSYS_TRACE_SEL, id);
+
+		memcpy((void *)(uintptr_t)CPC_TRACE_SRAM(id),
+				(const void *)(uintptr_t)CPC_MCUSYS_TRACE_DATA,
+				CPC_TRACE_SIZE);
+	}
+}
+
+void mtk_cpc_time_sync(void)
+{
+	uint64_t kt;
+	uint32_t systime_l, systime_h;
+
+	kt = sched_clock();
+	systime_l = mmio_read_32(CNTSYS_L_REG);
+	systime_h = mmio_read_32(CNTSYS_H_REG);
+
+	/* sync kernel timer to cpc */
+	mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE, (uint32_t)kt);
+	mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE, (uint32_t)(kt >> 32));
+	/* sync system timer to cpc */
+	mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE, systime_l);
+	mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE, systime_h);
+}
+
+static void mtk_cpc_config(uint32_t cfg, uint32_t data)
+{
+	uint32_t val;
+	uint32_t reg = 0U;
+
+	switch (cfg) {
+	case CPC_SMC_CONFIG_PROF:
+		reg = CPC_MCUSYS_CPC_DBG_SETTING;
+		val = mmio_read_32(reg);
+		val = (data != 0U) ? (val | CPC_PROF_EN) : (val & ~CPC_PROF_EN);
+		break;
+	case CPC_SMC_CONFIG_AUTO_OFF:
+		reg = CPC_MCUSYS_CPC_FLOW_CTRL_CFG;
+		val = mmio_read_32(reg);
+		if (data != 0U) {
+			val |= CPC_AUTO_OFF_EN;
+			cpc.auto_off = 1;
+		} else {
+			val &= ~CPC_AUTO_OFF_EN;
+			cpc.auto_off = 0;
+		}
+		break;
+	case CPC_SMC_CONFIG_AUTO_OFF_THRES:
+		reg = CPC_MCUSYS_CPC_OFF_THRES;
+		cpc.auto_thres_tick = us_to_ticks(data);
+		val = cpc.auto_thres_tick;
+		break;
+	case CPC_SMC_CONFIG_CNT_CLR:
+		reg = CPC_MCUSYS_CLUSTER_COUNTER_CLR;
+		val = GENMASK(1, 0);	/* clr_mask */
+		break;
+	case CPC_SMC_CONFIG_TIME_SYNC:
+		mtk_cpc_time_sync();
+		break;
+	default:
+		break;
+	}
+
+	if (reg != 0U) {
+		mmio_write_32(reg, val);
+	}
+}
+
+static uint32_t mtk_cpc_read_config(uint32_t cfg)
+{
+	uint32_t res = 0U;
+
+	switch (cfg) {
+	case CPC_SMC_CONFIG_PROF:
+		res = (mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) & CPC_PROF_EN) ?
+			1U : 0U;
+		break;
+	case CPC_SMC_CONFIG_AUTO_OFF:
+		res = cpc.auto_off;
+		break;
+	case CPC_SMC_CONFIG_AUTO_OFF_THRES:
+		res = ticks_to_us(cpc.auto_thres_tick);
+		break;
+	case CPC_SMC_CONFIG_CNT_CLR:
+		break;
+	default:
+		break;
+	}
+
+	return res;
+}
+
+uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2)
+{
+	uint64_t res = 0ULL;
+
+	switch (act) {
+	case CPC_SMC_EVENT_DUMP_TRACE_DATA:
+		mtk_cpc_dump_timestamp();
+		break;
+	case CPC_SMC_EVENT_GIC_DPG_SET:
+		/* isolated_status = x2; */
+		break;
+	case CPC_SMC_EVENT_CPC_CONFIG:
+		mtk_cpc_config((uint32_t)arg1, (uint32_t)arg2);
+		break;
+	case CPC_SMC_EVENT_READ_CONFIG:
+		res = mtk_cpc_read_config((uint32_t)arg1);
+		break;
+	default:
+		break;
+	}
+
+	return res;
+}
+
+void mtk_cpc_init(void)
+{
+	mmio_write_32(CPC_MCUSYS_CPC_DBG_SETTING,
+			mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING)
+			| CPC_DBG_EN
+			| CPC_CALC_EN);
+
+	cpc.auto_off = 1;
+	cpc.auto_thres_tick = us_to_ticks(8000);
+
+	mmio_write_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG,
+			mmio_read_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG)
+			| CPC_OFF_PRE_EN
+			| (cpc.auto_off ? CPC_AUTO_OFF_EN : 0U));
+
+	mmio_write_32(CPC_MCUSYS_CPC_OFF_THRES, cpc.auto_thres_tick);
+}
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.h b/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.h
new file mode 100644
index 0000000..19dd6a2
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_CPU_PM_CPC_H
+#define MT_CPU_PM_CPC_H
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <mcucfg.h>
+#include <platform_def.h>
+
+#define NEED_CPUSYS_PROT_WORKAROUND	1
+
+/* system sram registers */
+#define CPUIDLE_SRAM_REG(r)	(uint32_t)(MTK_MCDI_SRAM_BASE + (r))
+
+/* db dump */
+#define CPC_TRACE_SIZE		U(0x20)
+#define CPC_TRACE_ID_NUM	U(10)
+#define CPC_TRACE_SRAM(id)	(CPUIDLE_SRAM_REG(0x10) + (id) * CPC_TRACE_SIZE)
+
+/* buckup off count */
+#define CPC_CLUSTER_CNT_BACKUP	CPUIDLE_SRAM_REG(0x1F0)
+#define CPC_MCUSYS_CNT		CPUIDLE_SRAM_REG(0x1F4)
+
+/* CPC_MCUSYS_CPC_FLOW_CTRL_CFG(0xA814): debug setting */
+#define CPC_PWR_ON_SEQ_DIS	BIT(1)
+#define CPC_PWR_ON_PRIORITY	BIT(2)
+#define CPC_AUTO_OFF_EN		BIT(5)
+#define CPC_DORMANT_WAIT_EN	BIT(14)
+#define CPC_CTRL_EN		BIT(16)
+#define CPC_OFF_PRE_EN		BIT(29)
+
+/* CPC_MCUSYS_LAST_CORE_REQ(0xA818) : last core protection */
+#define CPUSYS_PROT_SET		BIT(0)
+#define MCUSYS_PROT_SET		BIT(8)
+#define CPUSYS_PROT_CLR		BIT(8)
+#define MCUSYS_PROT_CLR		BIT(9)
+
+#define CPC_PROT_RESP_MASK	U(0x3)
+#define CPUSYS_RESP_OFS		U(16)
+#define MCUSYS_RESP_OFS		U(30)
+
+#define cpusys_resp(r)		(((r) >> CPUSYS_RESP_OFS) & CPC_PROT_RESP_MASK)
+#define mcusys_resp(r)		(((r) >> MCUSYS_RESP_OFS) & CPC_PROT_RESP_MASK)
+
+#define RETRY_CNT_MAX		U(1000)
+
+#define PROT_RETRY		U(0)
+#define PROT_SUCCESS		U(1)
+#define PROT_GIVEUP		U(2)
+
+/* CPC_MCUSYS_CPC_DBG_SETTING(0xAB00): debug setting */
+#define CPC_PROF_EN		BIT(0)
+#define CPC_DBG_EN		BIT(1)
+#define CPC_FREEZE		BIT(2)
+#define CPC_CALC_EN		BIT(3)
+
+enum {
+	CPC_SUCCESS = 0,
+
+	CPC_ERR_FAIL,
+	CPC_ERR_TIMEOUT,
+
+	NF_CPC_ERR
+};
+
+enum {
+	CPC_SMC_EVENT_DUMP_TRACE_DATA,
+	CPC_SMC_EVENT_GIC_DPG_SET,
+	CPC_SMC_EVENT_CPC_CONFIG,
+	CPC_SMC_EVENT_READ_CONFIG,
+
+	NF_CPC_SMC_EVENT
+};
+
+enum {
+	CPC_SMC_CONFIG_PROF,
+	CPC_SMC_CONFIG_AUTO_OFF,
+	CPC_SMC_CONFIG_AUTO_OFF_THRES,
+	CPC_SMC_CONFIG_CNT_CLR,
+	CPC_SMC_CONFIG_TIME_SYNC,
+
+	NF_CPC_SMC_CONFIG
+};
+
+#define us_to_ticks(us)		((us) * 13)
+#define ticks_to_us(tick)	((tick) / 13)
+
+int mtk_cpu_pm_cluster_prot_aquire(unsigned int cluster);
+void mtk_cpu_pm_cluster_prot_release(unsigned int cluster);
+
+void mtk_cpc_mcusys_off_reflect(void);
+int mtk_cpc_mcusys_off_prepare(void);
+
+void mtk_cpc_core_on_hint_set(unsigned int cpu);
+void mtk_cpc_core_on_hint_clr(unsigned int cpu);
+void mtk_cpc_time_sync(void);
+
+uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2);
+void mtk_cpc_init(void);
+
+#endif /* MT_CPU_PM_CPC_H */
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.c b/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.c
new file mode 100644
index 0000000..df74122
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <cdefs.h>
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <mt_mcdi.h>
+
+/* Read/Write */
+#define APMCU_MCUPM_MBOX_AP_READY	U(0)
+#define APMCU_MCUPM_MBOX_RESERVED_1	U(1)
+#define APMCU_MCUPM_MBOX_RESERVED_2	U(2)
+#define APMCU_MCUPM_MBOX_RESERVED_3	U(3)
+#define APMCU_MCUPM_MBOX_PWR_CTRL_EN	U(4)
+#define APMCU_MCUPM_MBOX_L3_CACHE_MODE	U(5)
+#define APMCU_MCUPM_MBOX_BUCK_MODE	U(6)
+#define APMCU_MCUPM_MBOX_ARMPLL_MODE	U(7)
+/* Read only */
+#define APMCU_MCUPM_MBOX_TASK_STA	U(8)
+#define APMCU_MCUPM_MBOX_RESERVED_9	U(9)
+#define APMCU_MCUPM_MBOX_RESERVED_10	U(10)
+#define APMCU_MCUPM_MBOX_RESERVED_11	U(11)
+
+/* CPC mode - Read/Write */
+#define APMCU_MCUPM_MBOX_WAKEUP_CPU	U(12)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_PWR_CTRL_EN */
+#define MCUPM_MCUSYS_CTRL		BIT(0)
+#define MCUPM_BUCK_CTRL			BIT(1)
+#define MCUPM_ARMPLL_CTRL		BIT(2)
+#define MCUPM_CM_CTRL			BIT(3)
+#define MCUPM_PWR_CTRL_MASK		GENMASK(3, 0)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_BUCK_MODE */
+#define MCUPM_BUCK_NORMAL_MODE		U(0) /* default */
+#define MCUPM_BUCK_LP_MODE		U(1)
+#define MCUPM_BUCK_OFF_MODE		U(2)
+#define NF_MCUPM_BUCK_MODE		U(3)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_ARMPLL_MODE */
+#define MCUPM_ARMPLL_ON			U(0) /* default */
+#define MCUPM_ARMPLL_GATING		U(1)
+#define MCUPM_ARMPLL_OFF		U(2)
+#define NF_MCUPM_ARMPLL_MODE		U(3)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_TASK_STA */
+#define MCUPM_TASK_UNINIT		U(0)
+#define MCUPM_TASK_INIT			U(1)
+#define MCUPM_TASK_INIT_FINISH		U(2)
+#define MCUPM_TASK_WAIT			U(3)
+#define MCUPM_TASK_RUN			U(4)
+#define MCUPM_TASK_PAUSE		U(5)
+
+#define SSPM_MBOX_3_BASE		U(0x0c55fce0)
+
+#define MCDI_NOT_INIT			0
+#define MCDI_INIT_1			1
+#define MCDI_INIT_2			2
+#define MCDI_INIT_DONE			3
+
+static int mcdi_init_status __section("tzfw_coherent_mem");
+
+static inline uint32_t mcdi_mbox_read(uint32_t id)
+{
+	return mmio_read_32(SSPM_MBOX_3_BASE + (id << 2));
+}
+
+static inline void mcdi_mbox_write(uint32_t id, uint32_t val)
+{
+	mmio_write_32(SSPM_MBOX_3_BASE + (id << 2), val);
+}
+
+static void mtk_mcupm_pwr_ctrl_setting(uint32_t dev)
+{
+	mcdi_mbox_write(APMCU_MCUPM_MBOX_PWR_CTRL_EN, dev);
+}
+
+static void mtk_set_mcupm_pll_mode(uint32_t mode)
+{
+	if (mode < NF_MCUPM_ARMPLL_MODE) {
+		mcdi_mbox_write(APMCU_MCUPM_MBOX_ARMPLL_MODE, mode);
+	}
+}
+
+static void mtk_set_mcupm_buck_mode(uint32_t mode)
+{
+	if (mode < NF_MCUPM_BUCK_MODE) {
+		mcdi_mbox_write(APMCU_MCUPM_MBOX_BUCK_MODE, mode);
+	}
+}
+
+static int mtk_mcupm_is_ready(void)
+{
+	unsigned int sta = mcdi_mbox_read(APMCU_MCUPM_MBOX_TASK_STA);
+
+	return (sta == MCUPM_TASK_WAIT) || (sta == MCUPM_TASK_INIT_FINISH);
+}
+
+static int mcdi_init_1(void)
+{
+	unsigned int sta = mcdi_mbox_read(APMCU_MCUPM_MBOX_TASK_STA);
+
+	if (sta != MCUPM_TASK_INIT) {
+		return -1;
+	}
+
+	mtk_set_mcupm_pll_mode(MCUPM_ARMPLL_OFF);
+	mtk_set_mcupm_buck_mode(MCUPM_BUCK_OFF_MODE);
+
+	mtk_mcupm_pwr_ctrl_setting(
+			 MCUPM_MCUSYS_CTRL |
+			 MCUPM_BUCK_CTRL |
+			 MCUPM_ARMPLL_CTRL);
+
+	mcdi_mbox_write(APMCU_MCUPM_MBOX_AP_READY, 1);
+
+	return 0;
+}
+
+static int mcdi_init_2(void)
+{
+	return mtk_mcupm_is_ready() ? 0 : -1;
+}
+
+int mcdi_try_init(void)
+{
+	if (mcdi_init_status == MCDI_INIT_DONE) {
+		return 0;
+	}
+
+	if (mcdi_init_status == MCDI_NOT_INIT) {
+		mcdi_init_status = MCDI_INIT_1;
+	}
+
+	if (mcdi_init_status == MCDI_INIT_1 && mcdi_init_1() == 0) {
+		mcdi_init_status = MCDI_INIT_2;
+	}
+
+	if (mcdi_init_status == MCDI_INIT_2 && mcdi_init_2() == 0) {
+		mcdi_init_status = MCDI_INIT_DONE;
+	}
+
+	return (mcdi_init_status == MCDI_INIT_DONE) ? 0 : mcdi_init_status;
+}
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.h b/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.h
new file mode 100644
index 0000000..f3545aa
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_MCDI_H
+#define MT_MCDI_H
+
+int mcdi_try_init(void);
+
+#endif /* MT_MCDI_H */
diff --git a/plat/mediatek/mt8195/drivers/pmic/pmic.c b/plat/mediatek/mt8195/drivers/pmic/pmic.c
new file mode 100644
index 0000000..cca4413
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/pmic/pmic.c
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <pmic.h>
+#include <pmic_wrap_init.h>
+
+void pmic_power_off(void)
+{
+	pwrap_write(PMIC_PWRHOLD, 0x0);
+}
diff --git a/plat/mediatek/mt8195/drivers/pmic/pmic.h b/plat/mediatek/mt8195/drivers/pmic/pmic.h
new file mode 100644
index 0000000..aac22af
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/pmic/pmic.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_H
+#define PMIC_H
+
+#define PMIC_PWRHOLD 0xa08
+
+/* external API */
+void pmic_power_off(void);
+
+#endif /* PMIC_H */
diff --git a/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h
new file mode 100644
index 0000000..39e78f5
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_WRAP_INIT_H
+#define PMIC_WRAP_INIT_H
+
+#include <stdint.h>
+
+#include "platform_def.h"
+
+/* external API */
+int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
+int32_t pwrap_write(uint32_t adr, uint32_t wdata);
+
+static struct mt8195_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE;
+
+/* PMIC_WRAP registers */
+struct mt8195_pmic_wrap_regs {
+	uint32_t init_done;
+	uint32_t reserved[543];
+	uint32_t wacs2_cmd;
+	uint32_t wacs2_wdata;
+	uint32_t reserved1[3];
+	uint32_t wacs2_rdata;
+	uint32_t reserved2[3];
+	uint32_t wacs2_vldclr;
+	uint32_t wacs2_sta;
+};
+
+#define GET_WACS_FSM(x)	((x >> 1) & 0x7)
+
+/* macro for SWINF_FSM */
+#define SWINF_FSM_IDLE		(0x00)
+#define SWINF_FSM_REQ		(0x02)
+#define SWINF_FSM_WFDLE		(0x04)
+#define SWINF_FSM_WFVLDCLR	(0x06)
+#define SWINF_INIT_DONE		(0x01)
+
+/* timeout setting */
+#define PWRAP_READ_US	1000
+#define PWRAP_WAIT_IDLE_US	1000
+
+/* error information flag */
+enum pwrap_errno {
+	E_PWR_INVALID_ARG             = 1,
+	E_PWR_INVALID_RW              = 2,
+	E_PWR_INVALID_ADDR            = 3,
+	E_PWR_INVALID_WDAT            = 4,
+	E_PWR_INVALID_OP_MANUAL       = 5,
+	E_PWR_NOT_IDLE_STATE          = 6,
+	E_PWR_NOT_INIT_DONE           = 7,
+	E_PWR_NOT_INIT_DONE_READ      = 8,
+	E_PWR_WAIT_IDLE_TIMEOUT       = 9,
+	E_PWR_WAIT_IDLE_TIMEOUT_READ  = 10,
+	E_PWR_INIT_SIDLY_FAIL         = 11,
+	E_PWR_RESET_TIMEOUT           = 12,
+	E_PWR_TIMEOUT                 = 13,
+	E_PWR_INIT_RESET_SPI          = 20,
+	E_PWR_INIT_SIDLY              = 21,
+	E_PWR_INIT_REG_CLOCK          = 22,
+	E_PWR_INIT_ENABLE_PMIC        = 23,
+	E_PWR_INIT_DIO                = 24,
+	E_PWR_INIT_CIPHER             = 25,
+	E_PWR_INIT_WRITE_TEST         = 26,
+	E_PWR_INIT_ENABLE_CRC         = 27,
+	E_PWR_INIT_ENABLE_DEWRAP      = 28,
+	E_PWR_INIT_ENABLE_EVENT       = 29,
+	E_PWR_READ_TEST_FAIL          = 30,
+	E_PWR_WRITE_TEST_FAIL         = 31,
+	E_PWR_SWITCH_DIO              = 32
+};
+
+#endif /* PMIC_WRAP_INIT_H */
diff --git a/plat/mediatek/mt8195/drivers/spmc/mtspmc.c b/plat/mediatek/mt8195/drivers/spmc/mtspmc.c
new file mode 100644
index 0000000..9b332a0
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spmc/mtspmc.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <mcucfg.h>
+#include <mtspmc.h>
+#include <mtspmc_private.h>
+
+
+void mcucfg_disable_gic_wakeup(unsigned int cluster, unsigned int cpu)
+{
+	mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu));
+}
+
+void mcucfg_enable_gic_wakeup(unsigned int cluster, unsigned int cpu)
+{
+	mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu));
+}
+
+void mcucfg_set_bootaddr(unsigned int cluster, unsigned int cpu, uintptr_t bootaddr)
+{
+	assert(cluster == 0U);
+
+	mmio_write_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR), bootaddr);
+}
+
+uintptr_t mcucfg_get_bootaddr(unsigned int cluster, unsigned int cpu)
+{
+	assert(cluster == 0U);
+
+	return (uintptr_t)mmio_read_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR));
+}
+
+void mcucfg_init_archstate(unsigned int cluster, unsigned int cpu, bool arm64)
+{
+	uint32_t reg;
+
+	assert(cluster == 0U);
+
+	reg = per_cluster(cluster, MCUCFG_INITARCH);
+
+	if (arm64) {
+		mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu));
+	} else {
+		mmio_clrbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu));
+	}
+}
+
+/**
+ * Return subsystem's power state.
+ *
+ * @mask: mask to MCUCFG_CPC_SPMC_PWR_STATUS to query the power state
+ *        of one subsystem.
+ * RETURNS:
+ * 0 (the subsys was powered off)
+ * 1 (the subsys was powered on)
+ */
+bool spm_get_powerstate(uint32_t mask)
+{
+	return (mmio_read_32(MCUCFG_CPC_SPMC_PWR_STATUS) & mask) != 0U;
+}
+
+bool spm_get_cluster_powerstate(unsigned int cluster)
+{
+	assert(cluster == 0U);
+
+	return spm_get_powerstate(BIT(14));
+}
+
+bool spm_get_cpu_powerstate(unsigned int cluster, unsigned int cpu)
+{
+	uint32_t mask = BIT(cpu);
+
+	assert(cluster == 0U);
+
+	return spm_get_powerstate(mask);
+}
+
+int spmc_init(void)
+{
+	INFO("SPM: enable CPC mode\n");
+
+	mmio_write_32(SPM_POWERON_CONFIG_EN, PROJECT_CODE | BCLK_CG_EN);
+
+	mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B);
+	mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B);
+	mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B);
+	mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B);
+	mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B);
+	mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B);
+	mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B);
+
+	mmio_clrbits_32(SPM_MCUSYS_PWR_CON, RESETPWRON_CONFIG);
+	mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG);
+	mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG);
+
+	mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE);
+	mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, SSPM_CORE_PWR_ON_EN);
+
+	return 0;
+}
+
+/**
+ * Power on a core with specified cluster and core index
+ *
+ * @cluster: the cluster ID of the CPU which to be powered on
+ * @cpu: the CPU ID of the CPU which to be powered on
+ */
+void spm_poweron_cpu(unsigned int cluster, unsigned int cpu)
+{
+	uintptr_t cpu_pwr_con = per_cpu(cluster, cpu, SPM_CPU_PWR);
+
+	/* set to 0 after BIG VPROC bulk on & before B-core power on seq. */
+	if (cpu >= 4U) {
+		mmio_write_32(DREQ20_BIG_VPROC_ISO, 0U);
+	}
+
+	mmio_setbits_32(cpu_pwr_con, PWR_ON);
+
+	while (!spm_get_cpu_powerstate(cluster, cpu)) {
+		mmio_clrbits_32(cpu_pwr_con, PWR_ON);
+		mmio_setbits_32(cpu_pwr_con, PWR_ON);
+	}
+}
+
+/**
+ * Power off a core with specified cluster and core index
+ *
+ * @cluster: the cluster ID of the CPU which to be powered off
+ * @cpu: the CPU ID of the CPU which to be powered off
+ */
+void spm_poweroff_cpu(unsigned int cluster, unsigned int cpu)
+{
+	/* Set mp0_spmc_pwr_on_cpuX = 0 */
+	mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON);
+}
+
+/**
+ * Power off a cluster with specified index
+ *
+ * @cluster: the cluster index which to be powered off
+ */
+void spm_poweroff_cluster(unsigned int cluster)
+{
+	/* No need to power on/off cluster on single cluster platform */
+	assert(false);
+}
+
+/**
+ * Power on a cluster with specified index
+ *
+ * @cluster: the cluster index which to be powered on
+ */
+void spm_poweron_cluster(unsigned int cluster)
+{
+	/* No need to power on/off cluster on single cluster platform */
+	assert(false);
+}
diff --git a/plat/mediatek/mt8195/drivers/spmc/mtspmc.h b/plat/mediatek/mt8195/drivers/spmc/mtspmc.h
new file mode 100644
index 0000000..34e93d0
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spmc/mtspmc.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTSPMC_H
+#define MTSPMC_H
+
+#include <stdint.h>
+
+int spmc_init(void);
+
+void spm_poweron_cpu(unsigned int cluster, unsigned int cpu);
+void spm_poweroff_cpu(unsigned int cluster, unsigned int cpu);
+
+void spm_poweroff_cluster(unsigned int cluster);
+void spm_poweron_cluster(unsigned int cluster);
+
+bool spm_get_cpu_powerstate(unsigned int cluster, unsigned int cpu);
+bool spm_get_cluster_powerstate(unsigned int cluster);
+bool spm_get_powerstate(uint32_t mask);
+
+void mcucfg_init_archstate(unsigned int cluster, unsigned int cpu, bool arm64);
+void mcucfg_set_bootaddr(unsigned int cluster, unsigned int cpu, uintptr_t bootaddr);
+uintptr_t mcucfg_get_bootaddr(unsigned int cluster, unsigned int cpu);
+
+void mcucfg_disable_gic_wakeup(unsigned int cluster, unsigned int cpu);
+void mcucfg_enable_gic_wakeup(unsigned int cluster, unsigned int cpu);
+
+#endif /* MTSPMC_H */
diff --git a/plat/mediatek/mt8195/drivers/spmc/mtspmc_private.h b/plat/mediatek/mt8195/drivers/spmc/mtspmc_private.h
new file mode 100644
index 0000000..bf4092e
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spmc/mtspmc_private.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTSPMC_PRIVATE_H
+#define MTSPMC_PRIVATE_H
+
+#include <lib/utils_def.h>
+#include <platform_def.h>
+
+unsigned long read_cpuectlr(void);
+void write_cpuectlr(unsigned long cpuectlr);
+
+unsigned long read_cpupwrctlr_el1(void);
+void write_cpupwrctlr_el1(unsigned long cpuectlr);
+
+/*
+ * per_cpu/cluster helper
+ */
+struct per_cpu_reg {
+	unsigned int cluster_addr;
+	unsigned int cpu_stride;
+};
+
+#define per_cpu(cluster, cpu, reg)	\
+	(reg[cluster].cluster_addr + (cpu << reg[cluster].cpu_stride))
+
+#define per_cluster(cluster, reg)	(reg[cluster].cluster_addr)
+
+#define SPM_REG(ofs)			(uint32_t)(SPM_BASE + (ofs))
+#define MCUCFG_REG(ofs)			(uint32_t)(MCUCFG_BASE + (ofs))
+#define INFRACFG_AO_REG(ofs)		(uint32_t)(INFRACFG_AO_BASE + (ofs))
+
+/* === SPMC related registers */
+#define SPM_POWERON_CONFIG_EN		SPM_REG(0x000)
+/* bit-fields of SPM_POWERON_CONFIG_EN */
+#define PROJECT_CODE			(U(0xb16) << 16)
+#define BCLK_CG_EN			BIT(0)
+
+#define SPM_PWR_STATUS			SPM_REG(0x16c)
+#define SPM_PWR_STATUS_2ND		SPM_REG(0x170)
+#define SPM_CPU_PWR_STATUS		SPM_REG(0x174)
+
+/* bit-fields of SPM_PWR_STATUS */
+#define MD				BIT(0)
+#define CONN				BIT(1)
+#define DDRPHY				BIT(2)
+#define DISP				BIT(3)
+#define MFG				BIT(4)
+#define ISP				BIT(5)
+#define INFRA				BIT(6)
+#define VDEC				BIT(7)
+#define MP0_CPUTOP			BIT(8)
+#define MP0_CPU0			BIT(9)
+#define MP0_CPU1			BIT(10)
+#define MP0_CPU2			BIT(11)
+#define MP0_CPU3			BIT(12)
+#define MCUSYS				BIT(14)
+#define MP0_CPU4			BIT(15)
+#define MP0_CPU5			BIT(16)
+#define MP0_CPU6			BIT(17)
+#define MP0_CPU7			BIT(18)
+#define VEN				BIT(21)
+
+/* === SPMC related registers */
+#define SPM_MCUSYS_PWR_CON		MCUCFG_REG(0xd200)
+#define SPM_MP0_CPUTOP_PWR_CON		MCUCFG_REG(0xd204)
+#define SPM_MP0_CPU0_PWR_CON		MCUCFG_REG(0xd208)
+#define SPM_MP0_CPU1_PWR_CON		MCUCFG_REG(0xd20c)
+#define SPM_MP0_CPU2_PWR_CON		MCUCFG_REG(0xd210)
+#define SPM_MP0_CPU3_PWR_CON		MCUCFG_REG(0xd214)
+#define SPM_MP0_CPU4_PWR_CON		MCUCFG_REG(0xd218)
+#define SPM_MP0_CPU5_PWR_CON		MCUCFG_REG(0xd21c)
+#define SPM_MP0_CPU6_PWR_CON		MCUCFG_REG(0xd220)
+#define SPM_MP0_CPU7_PWR_CON		MCUCFG_REG(0xd224)
+
+/* bit fields of SPM_*_PWR_CON */
+#define PWR_ON_ACK			BIT(31)
+#define VPROC_EXT_OFF			BIT(7)
+#define DORMANT_EN			BIT(6)
+#define RESETPWRON_CONFIG		BIT(5)
+#define PWR_CLK_DIS			BIT(4)
+#define PWR_ON				BIT(2)
+#define PWR_RST_B			BIT(0)
+
+/**** per_cpu registers for SPM_MP0_CPU?_PWR_CON */
+static const struct per_cpu_reg SPM_CPU_PWR[] = {
+	{ .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2U }
+};
+
+/**** per_cluster registers for SPM_MP0_CPUTOP_PWR_CON */
+static const struct per_cpu_reg SPM_CLUSTER_PWR[] = {
+	{ .cluster_addr = SPM_MP0_CPUTOP_PWR_CON, .cpu_stride = 0U }
+};
+
+/* === MCUCFG related registers */
+/* aa64naa32 */
+#define MCUCFG_MP0_CLUSTER_CFG5		MCUCFG_REG(0xc8e4)
+/* reset vectors */
+#define MCUCFG_MP0_CLUSTER_CFG8		MCUCFG_REG(0xc900)
+#define MCUCFG_MP0_CLUSTER_CFG10	MCUCFG_REG(0xc908)
+#define MCUCFG_MP0_CLUSTER_CFG12	MCUCFG_REG(0xc910)
+#define MCUCFG_MP0_CLUSTER_CFG14	MCUCFG_REG(0xc918)
+#define MCUCFG_MP0_CLUSTER_CFG16	MCUCFG_REG(0xc920)
+#define MCUCFG_MP0_CLUSTER_CFG18	MCUCFG_REG(0xc928)
+#define MCUCFG_MP0_CLUSTER_CFG20	MCUCFG_REG(0xc930)
+#define MCUCFG_MP0_CLUSTER_CFG22	MCUCFG_REG(0xc938)
+
+/* MCUSYS DREQ BIG VPROC ISO control */
+#define DREQ20_BIG_VPROC_ISO		MCUCFG_REG(0xad8c)
+
+/**** per_cpu registers for MCUCFG_MP0_CLUSTER_CFG? */
+static const struct per_cpu_reg MCUCFG_BOOTADDR[] = {
+	{ .cluster_addr = MCUCFG_MP0_CLUSTER_CFG8, .cpu_stride = 3U }
+};
+
+/**** per_cpu registers for MCUCFG_MP0_CLUSTER_CFG5 */
+static const struct per_cpu_reg MCUCFG_INITARCH[] = {
+	{ .cluster_addr = MCUCFG_MP0_CLUSTER_CFG5, .cpu_stride = 0U }
+};
+
+#define MCUCFG_INITARCH_CPU_BIT(cpu)	BIT(16U + cpu)
+/* === CPC control */
+#define MCUCFG_CPC_FLOW_CTRL_CFG	MCUCFG_REG(0xa814)
+#define MCUCFG_CPC_SPMC_PWR_STATUS	MCUCFG_REG(0xa840)
+
+/* bit fields of CPC_FLOW_CTRL_CFG */
+#define CPC_CTRL_ENABLE			BIT(16)
+#define SSPM_CORE_PWR_ON_EN		BIT(7) /* for cpu-hotplug */
+#define SSPM_ALL_PWR_CTRL_EN		BIT(13) /* for cpu-hotplug */
+#define GIC_WAKEUP_IGNORE(cpu)		BIT(21 + cpu)
+
+/* bit fields of CPC_SPMC_PWR_STATUS */
+#define CORE_SPMC_PWR_ON_ACK		GENMASK(11, 0)
+
+/* === APB Module infracfg_ao */
+#define INFRA_TOPAXI_PROTECTEN		INFRACFG_AO_REG(0x0220)
+#define INFRA_TOPAXI_PROTECTEN_STA0	INFRACFG_AO_REG(0x0224)
+#define INFRA_TOPAXI_PROTECTEN_STA1	INFRACFG_AO_REG(0x0228)
+#define INFRA_TOPAXI_PROTECTEN_SET	INFRACFG_AO_REG(0x02a0)
+#define INFRA_TOPAXI_PROTECTEN_CLR	INFRACFG_AO_REG(0x02a4)
+#define INFRA_TOPAXI_PROTECTEN_1	INFRACFG_AO_REG(0x0250)
+#define INFRA_TOPAXI_PROTECTEN_STA0_1	INFRACFG_AO_REG(0x0254)
+#define INFRA_TOPAXI_PROTECTEN_STA1_1	INFRACFG_AO_REG(0x0258)
+#define INFRA_TOPAXI_PROTECTEN_1_SET	INFRACFG_AO_REG(0x02a8)
+#define INFRA_TOPAXI_PROTECTEN_1_CLR	INFRACFG_AO_REG(0x02ac)
+
+/* bit fields of INFRA_TOPAXI_PROTECTEN */
+#define MP0_SPMC_PROT_STEP1_0_MASK	BIT(12)
+#define MP0_SPMC_PROT_STEP1_1_MASK	(BIT(26) | BIT(12))
+
+/* === SPARK */
+#define VOLTAGE_04			U(0x40)
+#define VOLTAGE_05			U(0x60)
+
+#define PTP3_CPU0_SPMC_SW_CFG		MCUCFG_REG(0x200)
+#define CPU0_ILDO_CONTROL5		MCUCFG_REG(0x334)
+#define CPU0_ILDO_CONTROL8		MCUCFG_REG(0x340)
+
+/* bit fields of CPU0_ILDO_CONTROL5 */
+#define ILDO_RET_VOSEL			GENMASK(7, 0)
+
+/* bit fields of PTP3_CPU_SPMC_SW_CFG */
+#define SW_SPARK_EN			BIT(0)
+
+/* bit fields of CPU0_ILDO_CONTROL8 */
+#define ILDO_BYPASS_B			BIT(0)
+
+static const struct per_cpu_reg MCUCFG_SPARK[] = {
+	{ .cluster_addr = PTP3_CPU0_SPMC_SW_CFG, .cpu_stride = 11U }
+};
+
+static const struct per_cpu_reg ILDO_CONTROL5[] = {
+	{ .cluster_addr = CPU0_ILDO_CONTROL5, .cpu_stride = 11U }
+};
+
+static const struct per_cpu_reg ILDO_CONTROL8[] = {
+	{ .cluster_addr = CPU0_ILDO_CONTROL8, .cpu_stride = 11U }
+};
+
+#endif /* MTSPMC_PRIVATE_H */
diff --git a/plat/mediatek/mt8195/include/mcucfg.h b/plat/mediatek/mt8195/include/mcucfg.h
new file mode 100644
index 0000000..046cf73
--- /dev/null
+++ b/plat/mediatek/mt8195/include/mcucfg.h
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MCUCFG_H
+#define MCUCFG_H
+
+#ifndef __ASSEMBLER__
+#include <stdint.h>
+#endif /* __ASSEMBLER__ */
+
+#include <platform_def.h>
+
+#define MCUCFG_REG(ofs)			(uint32_t)(MCUCFG_BASE + (ofs))
+
+#define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) (MCUCFG_REG(0x2290) + ((cpu) * 8))
+#define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) (MCUCFG_REG(0x2294) + ((cpu) * 8))
+
+#define MP2_CPUCFG			MCUCFG_REG(0x2208)
+
+#define MP2_CPU0_STANDBYWFE		BIT(4)
+#define MP2_CPU1_STANDBYWFE		BIT(5)
+
+#define MP0_CPUTOP_SPMC_CTL		MCUCFG_REG(0x788)
+#define MP1_CPUTOP_SPMC_CTL		MCUCFG_REG(0x78C)
+#define MP1_CPUTOP_SPMC_SRAM_CTL	MCUCFG_REG(0x790)
+
+#define sw_spark_en			BIT(0)
+#define sw_no_wait_for_q_channel	BIT(1)
+#define sw_fsm_override			BIT(2)
+#define sw_logic_pre1_pdb		BIT(3)
+#define sw_logic_pre2_pdb		BIT(4)
+#define sw_logic_pdb			BIT(5)
+#define sw_iso				BIT(6)
+#define sw_sram_sleepb			(U(0x3F) << 7)
+#define sw_sram_isointb			BIT(13)
+#define sw_clk_dis			BIT(14)
+#define sw_ckiso			BIT(15)
+#define sw_pd				(U(0x3F) << 16)
+#define sw_hot_plug_reset		BIT(22)
+#define sw_pwr_on_override_en		BIT(23)
+#define sw_pwr_on			BIT(24)
+#define sw_coq_dis			BIT(25)
+#define logic_pdbo_all_off_ack		BIT(26)
+#define logic_pdbo_all_on_ack		BIT(27)
+#define logic_pre2_pdbo_all_on_ack	BIT(28)
+#define logic_pre1_pdbo_all_on_ack	BIT(29)
+
+
+#define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) \
+	(MCUCFG_REG(0x1c30) + cluster * 0x2000 + cpu * 4)
+
+#define CPUSYS0_CPU0_SPMC_CTL		MCUCFG_REG(0x1c30)
+#define CPUSYS0_CPU1_SPMC_CTL		MCUCFG_REG(0x1c34)
+#define CPUSYS0_CPU2_SPMC_CTL		MCUCFG_REG(0x1c38)
+#define CPUSYS0_CPU3_SPMC_CTL		MCUCFG_REG(0x1c3C)
+
+#define CPUSYS1_CPU0_SPMC_CTL		MCUCFG_REG(0x3c30)
+#define CPUSYS1_CPU1_SPMC_CTL		MCUCFG_REG(0x3c34)
+#define CPUSYS1_CPU2_SPMC_CTL		MCUCFG_REG(0x3c38)
+#define CPUSYS1_CPU3_SPMC_CTL		MCUCFG_REG(0x3c3C)
+
+#define cpu_sw_spark_en			BIT(0)
+#define cpu_sw_no_wait_for_q_channel	BIT(1)
+#define cpu_sw_fsm_override		BIT(2)
+#define cpu_sw_logic_pre1_pdb		BIT(3)
+#define cpu_sw_logic_pre2_pdb		BIT(4)
+#define cpu_sw_logic_pdb		BIT(5)
+#define cpu_sw_iso			BIT(6)
+#define cpu_sw_sram_sleepb		BIT(7)
+#define cpu_sw_sram_isointb		BIT(8)
+#define cpu_sw_clk_dis			BIT(9)
+#define cpu_sw_ckiso			BIT(10)
+#define cpu_sw_pd			(U(0x1F) << 11)
+#define cpu_sw_hot_plug_reset		BIT(16)
+#define cpu_sw_powr_on_override_en	BIT(17)
+#define cpu_sw_pwr_on			BIT(18)
+#define cpu_spark2ldo_allswoff		BIT(19)
+#define cpu_pdbo_all_on_ack		BIT(20)
+#define cpu_pre2_pdbo_allon_ack		BIT(21)
+#define cpu_pre1_pdbo_allon_ack		BIT(22)
+
+/* CPC related registers */
+#define CPC_MCUSYS_CPC_OFF_THRES	MCUCFG_REG(0xa714)
+#define CPC_MCUSYS_PWR_CTRL		MCUCFG_REG(0xa804)
+#define CPC_MCUSYS_CPC_FLOW_CTRL_CFG	MCUCFG_REG(0xa814)
+#define CPC_MCUSYS_LAST_CORE_REQ	MCUCFG_REG(0xa818)
+#define CPC_MCUSYS_MP_LAST_CORE_RESP	MCUCFG_REG(0xa81c)
+#define CPC_MCUSYS_LAST_CORE_RESP	MCUCFG_REG(0xa824)
+#define CPC_MCUSYS_PWR_ON_MASK		MCUCFG_REG(0xa828)
+#define CPC_MCUSYS_CPU_ON_SW_HINT_SET	MCUCFG_REG(0xa8a8)
+#define CPC_MCUSYS_CPU_ON_SW_HINT_CLR	MCUCFG_REG(0xa8ac)
+#define CPC_MCUSYS_CPC_DBG_SETTING	MCUCFG_REG(0xab00)
+#define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE	MCUCFG_REG(0xab04)
+#define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE	MCUCFG_REG(0xab08)
+#define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE	MCUCFG_REG(0xab0c)
+#define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE	MCUCFG_REG(0xab10)
+#define CPC_MCUSYS_TRACE_SEL		MCUCFG_REG(0xab14)
+#define CPC_MCUSYS_TRACE_DATA		MCUCFG_REG(0xab20)
+#define CPC_MCUSYS_CLUSTER_COUNTER	MCUCFG_REG(0xab70)
+#define CPC_MCUSYS_CLUSTER_COUNTER_CLR	MCUCFG_REG(0xab74)
+
+#define SPARK2LDO			MCUCFG_REG(0x2700)
+/* APB Module mcucfg */
+#define MP0_CA7_CACHE_CONFIG		MCUCFG_REG(0x000)
+#define MP0_AXI_CONFIG			MCUCFG_REG(0x02C)
+#define MP0_MISC_CONFIG0		MCUCFG_REG(0x030)
+#define MP0_MISC_CONFIG1		MCUCFG_REG(0x034)
+#define MP0_MISC_CONFIG2		MCUCFG_REG(0x038)
+#define MP0_MISC_CONFIG_BOOT_ADDR(cpu)	(MP0_MISC_CONFIG2 + ((cpu) * 8))
+#define MP0_MISC_CONFIG3		MCUCFG_REG(0x03C)
+#define MP0_MISC_CONFIG9		MCUCFG_REG(0x054)
+#define MP0_CA7_MISC_CONFIG		MCUCFG_REG(0x064)
+
+#define MP0_RW_RSVD0			MCUCFG_REG(0x06C)
+
+
+#define MP1_CA7_CACHE_CONFIG		MCUCFG_REG(0x200)
+#define MP1_AXI_CONFIG			MCUCFG_REG(0x22C)
+#define MP1_MISC_CONFIG0		MCUCFG_REG(0x230)
+#define MP1_MISC_CONFIG1		MCUCFG_REG(0x234)
+#define MP1_MISC_CONFIG2		MCUCFG_REG(0x238)
+#define MP1_MISC_CONFIG_BOOT_ADDR(cpu)	(MP1_MISC_CONFIG2 + ((cpu) * 8))
+#define MP1_MISC_CONFIG3		MCUCFG_REG(0x23C)
+#define MP1_MISC_CONFIG9		MCUCFG_REG(0x254)
+#define MP1_CA7_MISC_CONFIG		MCUCFG_REG(0x264)
+
+#define CCI_ADB400_DCM_CONFIG		MCUCFG_REG(0x740)
+#define SYNC_DCM_CONFIG			MCUCFG_REG(0x744)
+
+#define MP0_CLUSTER_CFG0		MCUCFG_REG(0xC8D0)
+
+#define MP0_SPMC			MCUCFG_REG(0x788)
+#define MP1_SPMC			MCUCFG_REG(0x78C)
+#define MP2_AXI_CONFIG			MCUCFG_REG(0x220C)
+#define MP2_AXI_CONFIG_ACINACTM		BIT(0)
+#define MP2_AXI_CONFIG_AINACTS		BIT(4)
+
+#define MPx_AXI_CONFIG_ACINACTM		BIT(4)
+#define MPx_AXI_CONFIG_AINACTS		BIT(5)
+
+#define MPx_CA7_MISC_CONFIG_standbywfil2	BIT(28)
+
+#define MP0_CPU0_STANDBYWFE		BIT(20)
+#define MP0_CPU1_STANDBYWFE		BIT(21)
+#define MP0_CPU2_STANDBYWFE		BIT(22)
+#define MP0_CPU3_STANDBYWFE		BIT(23)
+
+#define MP1_CPU0_STANDBYWFE		BIT(20)
+#define MP1_CPU1_STANDBYWFE		BIT(21)
+#define MP1_CPU2_STANDBYWFE		BIT(22)
+#define MP1_CPU3_STANDBYWFE		BIT(23)
+
+#define CPUSYS0_SPARKVRETCNTRL		MCUCFG_REG(0x1c00)
+#define CPUSYS0_SPARKEN			MCUCFG_REG(0x1c04)
+#define CPUSYS0_AMUXSEL			MCUCFG_REG(0x1c08)
+#define CPUSYS1_SPARKVRETCNTRL		MCUCFG_REG(0x3c00)
+#define CPUSYS1_SPARKEN			MCUCFG_REG(0x3c04)
+#define CPUSYS1_AMUXSEL			MCUCFG_REG(0x3c08)
+
+#define MP2_PWR_RST_CTL			MCUCFG_REG(0x2008)
+#define MP2_PTP3_CPUTOP_SPMC0		MCUCFG_REG(0x22A0)
+#define MP2_PTP3_CPUTOP_SPMC1		MCUCFG_REG(0x22A4)
+
+#define MP2_COQ				MCUCFG_REG(0x22BC)
+#define MP2_COQ_SW_DIS			BIT(0)
+
+#define MP2_CA15M_MON_SEL		MCUCFG_REG(0x2400)
+#define MP2_CA15M_MON_L			MCUCFG_REG(0x2404)
+
+#define CPUSYS2_CPU0_SPMC_CTL		MCUCFG_REG(0x2430)
+#define CPUSYS2_CPU1_SPMC_CTL		MCUCFG_REG(0x2438)
+#define CPUSYS2_CPU0_SPMC_STA		MCUCFG_REG(0x2434)
+#define CPUSYS2_CPU1_SPMC_STA		MCUCFG_REG(0x243C)
+
+#define MP0_CA7L_DBG_PWR_CTRL		MCUCFG_REG(0x068)
+#define MP1_CA7L_DBG_PWR_CTRL		MCUCFG_REG(0x268)
+#define BIG_DBG_PWR_CTRL		MCUCFG_REG(0x75C)
+
+#define MP2_SW_RST_B			BIT(0)
+#define MP2_TOPAON_APB_MASK		BIT(1)
+
+#define B_SW_HOT_PLUG_RESET		BIT(30)
+
+#define B_SW_PD_OFFSET			18U
+#define B_SW_PD				(U(0x3f) << B_SW_PD_OFFSET)
+
+#define B_SW_SRAM_SLEEPB_OFFSET		12U
+#define B_SW_SRAM_SLEEPB		(U(0x3f) << B_SW_SRAM_SLEEPB_OFFSET)
+
+#define B_SW_SRAM_ISOINTB		BIT(9)
+#define B_SW_ISO			BIT(8)
+#define B_SW_LOGIC_PDB			BIT(7)
+#define B_SW_LOGIC_PRE2_PDB		BIT(6)
+#define B_SW_LOGIC_PRE1_PDB		BIT(5)
+#define B_SW_FSM_OVERRIDE		BIT(4)
+#define B_SW_PWR_ON			BIT(3)
+#define B_SW_PWR_ON_OVERRIDE_EN		BIT(2)
+
+#define B_FSM_STATE_OUT_OFFSET		(6U)
+#define B_FSM_STATE_OUT_MASK		(U(0x1f) << B_FSM_STATE_OUT_OFFSET)
+#define B_SW_LOGIC_PDBO_ALL_OFF_ACK	BIT(5)
+#define B_SW_LOGIC_PDBO_ALL_ON_ACK	BIT(4)
+#define B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK	BIT(3)
+#define B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK	BIT(2)
+
+#define B_FSM_OFF			(0U << B_FSM_STATE_OUT_OFFSET)
+#define B_FSM_ON			(1U << B_FSM_STATE_OUT_OFFSET)
+#define B_FSM_RET			(2U << B_FSM_STATE_OUT_OFFSET)
+
+#ifndef __ASSEMBLER__
+/* cpu boot mode */
+enum {
+	MP0_CPUCFG_64BIT_SHIFT = 12U,
+	MP1_CPUCFG_64BIT_SHIFT = 28U,
+	MP0_CPUCFG_64BIT = U(0xf) << MP0_CPUCFG_64BIT_SHIFT,
+	MP1_CPUCFG_64BIT = U(0xf) << MP1_CPUCFG_64BIT_SHIFT
+};
+
+enum {
+	MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0U,
+	MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4U,
+	MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8U,
+	MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12U,
+	MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16U,
+
+	MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
+		U(0xf) << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
+	MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
+		U(0xf) << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
+	MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
+		U(0xf) << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
+	MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
+		U(0xf) << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
+	MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
+		U(0xf) << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
+};
+
+enum {
+	MP1_AINACTS_SHIFT = 4U,
+	MP1_AINACTS = 1U << MP1_AINACTS_SHIFT
+};
+
+enum {
+	MP1_SW_CG_GEN_SHIFT = 12U,
+	MP1_SW_CG_GEN = 1U << MP1_SW_CG_GEN_SHIFT
+};
+
+enum {
+	MP1_L2RSTDISABLE_SHIFT = 14U,
+	MP1_L2RSTDISABLE = 1U << MP1_L2RSTDISABLE_SHIFT
+};
+#endif /* __ASSEMBLER__ */
+
+#endif  /* MCUCFG_H */
diff --git a/plat/mediatek/mt8195/include/plat_helpers.h b/plat/mediatek/mt8195/include/plat_helpers.h
new file mode 100644
index 0000000..ebc9fa0
--- /dev/null
+++ b/plat/mediatek/mt8195/include/plat_helpers.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PLAT_HELPERS_H__
+#define __PLAT_HELPERS_H__
+
+unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr);
+
+#endif /* __PLAT_HELPERS_H__ */
diff --git a/plat/mediatek/mt8195/include/plat_macros.S b/plat/mediatek/mt8195/include/plat_macros.S
new file mode 100644
index 0000000..39727ea
--- /dev/null
+++ b/plat/mediatek/mt8195/include/plat_macros.S
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+#include <platform_def.h>
+
+.section .rodata.gic_reg_name, "aS"
+gicc_regs:
+	.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
+gicd_pend_reg:
+	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n"	\
+		" Offset:\t\t\tvalue\n"
+newline:
+	.asciz "\n"
+spacer:
+	.asciz ":\t\t0x"
+
+.section .rodata.cci_reg_name, "aS"
+cci_iface_regs:
+	.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
+
+	/* ---------------------------------------------
+	 * The below macro prints out relevant GIC
+	 * registers whenever an unhandled exception
+	 * is taken in BL31.
+	 * Clobbers: x0 - x10, x26, x27, sp
+	 * ---------------------------------------------
+	 */
+	.macro plat_crash_print_regs
+	/* TODO: leave implementation to GIC owner */
+	.endm
+
+#endif /* PLAT_MACROS_S */
diff --git a/plat/mediatek/mt8195/include/plat_mtk_lpm.h b/plat/mediatek/mt8195/include/plat_mtk_lpm.h
new file mode 100644
index 0000000..8ba8b93
--- /dev/null
+++ b/plat/mediatek/mt8195/include/plat_mtk_lpm.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MTK_LPM_H
+#define PLAT_MTK_LPM_H
+
+#include <lib/psci/psci.h>
+#include <lib/utils_def.h>
+
+#define MT_IRQ_REMAIN_MAX	U(8)
+#define MT_IRQ_REMAIN_CAT_LOG	BIT(31)
+
+struct mt_irqremain {
+	unsigned int count;
+	unsigned int irqs[MT_IRQ_REMAIN_MAX];
+	unsigned int wakeupsrc_cat[MT_IRQ_REMAIN_MAX];
+	unsigned int wakeupsrc[MT_IRQ_REMAIN_MAX];
+};
+
+#define PLAT_RC_STATUS_READY		BIT(0)
+#define PLAT_RC_STATUS_FEATURE_EN	BIT(1)
+#define PLAT_RC_STATUS_UART_NONSLEEP	BIT(31)
+
+struct mt_lpm_tz {
+	int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state);
+	int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state);
+
+	int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state);
+	int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state);
+
+	int (*pwr_cluster_on)(unsigned int cpu,
+					const psci_power_state_t *state);
+	int (*pwr_cluster_dwn)(unsigned int cpu,
+					const psci_power_state_t *state);
+
+	int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state);
+	int (*pwr_mcusys_on_finished)(unsigned int cpu,
+					const psci_power_state_t *state);
+	int (*pwr_mcusys_dwn)(unsigned int cpu,
+					const psci_power_state_t *state);
+};
+
+const struct mt_lpm_tz *mt_plat_cpu_pm_init(void);
+
+#endif /* PLAT_MTK_LPM_H */
diff --git a/plat/mediatek/mt8195/include/plat_pm.h b/plat/mediatek/mt8195/include/plat_pm.h
new file mode 100644
index 0000000..a2881ce
--- /dev/null
+++ b/plat/mediatek/mt8195/include/plat_pm.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_PM_H
+#define PLAT_PM_H
+
+#include <lib/utils_def.h>
+
+#define MT_PLAT_PWR_STATE_CPU			U(1)
+#define MT_PLAT_PWR_STATE_CLUSTER		U(2)
+#define MT_PLAT_PWR_STATE_MCUSYS		U(3)
+#define MT_PLAT_PWR_STATE_SUSPEND2IDLE		U(8)
+#define MT_PLAT_PWR_STATE_SYSTEM_SUSPEND	U(9)
+
+#define MTK_LOCAL_STATE_RUN			U(0)
+#define MTK_LOCAL_STATE_RET			U(1)
+#define MTK_LOCAL_STATE_OFF			U(2)
+
+#define MTK_AFFLVL_CPU				U(0)
+#define MTK_AFFLVL_CLUSTER			U(1)
+#define MTK_AFFLVL_MCUSYS			U(2)
+#define MTK_AFFLVL_SYSTEM			U(3)
+
+#define IS_CLUSTER_OFF_STATE(s)		\
+		is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_CLUSTER])
+#define IS_MCUSYS_OFF_STATE(s)		\
+		is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_MCUSYS])
+#define IS_SYSTEM_SUSPEND_STATE(s)	\
+		is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_SYSTEM])
+
+#define IS_PLAT_SUSPEND_ID(stateid)\
+		((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE)	\
+		|| (stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND))
+
+#endif /* PLAT_PM_H */
diff --git a/plat/mediatek/mt8195/include/plat_private.h b/plat/mediatek/mt8195/include/plat_private.h
new file mode 100644
index 0000000..7ef2b85
--- /dev/null
+++ b/plat/mediatek/mt8195/include/plat_private.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_PRIVATE_H
+#define PLAT_PRIVATE_H
+
+/*******************************************************************************
+ * Function and variable prototypes
+ ******************************************************************************/
+void plat_configure_mmu_el3(uintptr_t total_base,
+			    uintptr_t total_size,
+			    uintptr_t ro_start,
+			    uintptr_t ro_limit);
+
+#endif /* PLAT_PRIVATE_H */
diff --git a/plat/mediatek/mt8195/include/plat_sip_calls.h b/plat/mediatek/mt8195/include/plat_sip_calls.h
new file mode 100644
index 0000000..0e42322
--- /dev/null
+++ b/plat/mediatek/mt8195/include/plat_sip_calls.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_SIP_CALLS_H
+#define PLAT_SIP_CALLS_H
+
+/*******************************************************************************
+ * Plat SiP function constants
+ ******************************************************************************/
+#define MTK_PLAT_SIP_NUM_CALLS    0
+
+#endif /* PLAT_SIP_CALLS_H */
diff --git a/plat/mediatek/mt8195/include/platform_def.h b/plat/mediatek/mt8195/include/platform_def.h
new file mode 100644
index 0000000..f6eb742
--- /dev/null
+++ b/plat/mediatek/mt8195/include/platform_def.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#define PLAT_PRIMARY_CPU	0x0
+
+#define MT_GIC_BASE		(0x0C000000)
+#define MCUCFG_BASE		(0x0C530000)
+#define IO_PHYS			(0x10000000)
+
+/* Aggregate of all devices for MMU mapping */
+#define MTK_DEV_RNG0_BASE	IO_PHYS
+#define MTK_DEV_RNG0_SIZE	0x400000
+#define MTK_DEV_RNG1_BASE	(IO_PHYS + 0x1000000)
+#define MTK_DEV_RNG1_SIZE	0xa110000
+#define MTK_DEV_RNG2_BASE	MT_GIC_BASE
+#define MTK_DEV_RNG2_SIZE	0x600000
+#define MTK_MCDI_SRAM_BASE	0x11B000
+#define MTK_MCDI_SRAM_MAP_SIZE	0x1000
+
+#define SPM_BASE		(IO_PHYS + 0x00006000)
+
+/*******************************************************************************
+ * GPIO related constants
+ ******************************************************************************/
+#define GPIO_BASE		(IO_PHYS + 0x00005000)
+#define IOCFG_BM_BASE		(IO_PHYS + 0x01D10000)
+#define IOCFG_BL_BASE		(IO_PHYS + 0x01D30000)
+#define IOCFG_BR_BASE		(IO_PHYS + 0x01D40000)
+#define IOCFG_LM_BASE		(IO_PHYS + 0x01E20000)
+#define IOCFG_RB_BASE		(IO_PHYS + 0x01EB0000)
+#define IOCFG_TL_BASE		(IO_PHYS + 0x01F40000)
+
+/*******************************************************************************
+ * UART related constants
+ ******************************************************************************/
+#define UART0_BASE			(IO_PHYS + 0x01001100)
+#define UART1_BASE			(IO_PHYS + 0x01001200)
+
+#define UART_BAUDRATE			115200
+
+/*******************************************************************************
+ * PMIC related constants
+ ******************************************************************************/
+#define PMIC_WRAP_BASE			(IO_PHYS + 0x00024000)
+
+/*******************************************************************************
+ * System counter frequency related constants
+ ******************************************************************************/
+#define SYS_COUNTER_FREQ_IN_TICKS	13000000
+#define SYS_COUNTER_FREQ_IN_MHZ		13
+
+/*******************************************************************************
+ * GIC-600 & interrupt handling related constants
+ ******************************************************************************/
+/* Base MTK_platform compatible GIC memory map */
+#define BASE_GICD_BASE			MT_GIC_BASE
+#define MT_GIC_RDIST_BASE		(MT_GIC_BASE + 0x40000)
+
+#define SYS_CIRQ_BASE			(IO_PHYS + 0x204000)
+#define CIRQ_REG_NUM			23
+#define CIRQ_IRQ_NUM			730
+#define CIRQ_SPI_START			96
+#define MD_WDT_IRQ_BIT_ID		141
+/*******************************************************************************
+ * Platform binary types for linking
+ ******************************************************************************/
+#define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH		aarch64
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+#define PLATFORM_STACK_SIZE		0x800
+
+#define FIRMWARE_WELCOME_STR		"Booting Trusted Firmware\n"
+
+#define PLAT_MAX_PWR_LVL		U(3)
+#define PLAT_MAX_RET_STATE		U(1)
+#define PLAT_MAX_OFF_STATE		U(9)
+
+#define PLATFORM_SYSTEM_COUNT		U(1)
+#define PLATFORM_MCUSYS_COUNT		U(1)
+#define PLATFORM_CLUSTER_COUNT		U(1)
+#define PLATFORM_CLUSTER0_CORE_COUNT	U(8)
+#define PLATFORM_CLUSTER1_CORE_COUNT	U(0)
+
+#define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER0_CORE_COUNT)
+#define PLATFORM_MAX_CPUS_PER_CLUSTER	U(8)
+
+#define SOC_CHIP_ID			U(0x8195)
+
+/*******************************************************************************
+ * Platform memory map related constants
+ ******************************************************************************/
+#define TZRAM_BASE			0x54600000
+#define TZRAM_SIZE			0x00030000
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+/*
+ * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
+ * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
+ * little space for growth.
+ */
+#define BL31_BASE			(TZRAM_BASE + 0x1000)
+#define BL31_LIMIT			(TZRAM_BASE + TZRAM_SIZE)
+
+/*******************************************************************************
+ * Platform specific page table and MMU setup constants
+ ******************************************************************************/
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+#define MAX_XLAT_TABLES			16
+#define MAX_MMAP_REGIONS		16
+
+/*******************************************************************************
+ * Declarations and constants to access the mailboxes safely. Each mailbox is
+ * aligned on the biggest cache line size in the platform. This is known only
+ * to the platform as it might have a combination of integrated and external
+ * caches. Such alignment ensures that two maiboxes do not sit on the same cache
+ * line at any cache level. They could belong to different cpus/clusters &
+ * get written while being protected by different locks causing corruption of
+ * a valid mailbox address.
+ ******************************************************************************/
+#define CACHE_WRITEBACK_SHIFT		6
+#define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/mediatek/mt8195/include/rtc.h b/plat/mediatek/mt8195/include/rtc.h
new file mode 100644
index 0000000..a9c7bc8
--- /dev/null
+++ b/plat/mediatek/mt8195/include/rtc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RTC_H
+#define RTC_H
+
+#include <rtc_mt6359p.h>
+
+#endif  /* RTC_H */
diff --git a/plat/mediatek/mt8195/plat_pm.c b/plat/mediatek/mt8195/plat_pm.c
new file mode 100644
index 0000000..522d443
--- /dev/null
+++ b/plat/mediatek/mt8195/plat_pm.c
@@ -0,0 +1,398 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* common headers */
+#include <assert.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/gpio.h>
+#include <lib/psci/psci.h>
+
+/* platform specific headers */
+#include <mt_gic_v3.h>
+#include <mtspmc.h>
+#include <plat/common/platform.h>
+#include <plat_mtk_lpm.h>
+#include <plat_params.h>
+#include <plat_pm.h>
+#include <pmic.h>
+#include <rtc.h>
+
+/*
+ * Cluster state request:
+ * [0] : The CPU requires cluster power down
+ * [1] : The CPU requires cluster power on
+ */
+#define coordinate_cluster(onoff)	write_clusterpwrdn_el1(onoff)
+#define coordinate_cluster_pwron()	coordinate_cluster(1)
+#define coordinate_cluster_pwroff()	coordinate_cluster(0)
+
+/* platform secure entry point */
+static uintptr_t secure_entrypoint;
+/* per-CPU power state */
+static unsigned int plat_power_state[PLATFORM_CORE_COUNT];
+
+/* platform CPU power domain - ops */
+static const struct mt_lpm_tz *plat_mt_pm;
+
+#define plat_mt_pm_invoke(_name, _cpu, _state) ({ \
+	int ret = -1; \
+	if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \
+		ret = plat_mt_pm->_name(_cpu, _state); \
+	} \
+	ret; })
+
+#define plat_mt_pm_invoke_no_check(_name, _cpu, _state) ({ \
+	if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \
+		(void) plat_mt_pm->_name(_cpu, _state); \
+	} \
+	})
+
+/*
+ * Common MTK_platform operations to power on/off a
+ * CPU in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
+ */
+
+static void plat_cpu_pwrdwn_common(unsigned int cpu,
+		const psci_power_state_t *state, unsigned int req_pstate)
+{
+	assert(cpu == plat_my_core_pos());
+
+	plat_mt_pm_invoke_no_check(pwr_cpu_dwn, cpu, state);
+
+	if ((psci_get_pstate_pwrlvl(req_pstate) >= MTK_AFFLVL_CLUSTER) ||
+			(req_pstate == 0U)) { /* hotplug off */
+		coordinate_cluster_pwroff();
+	}
+
+	/* Prevent interrupts from spuriously waking up this CPU */
+	mt_gic_rdistif_save();
+	gicv3_cpuif_disable(cpu);
+	gicv3_rdistif_off(cpu);
+}
+
+static void plat_cpu_pwron_common(unsigned int cpu,
+		const psci_power_state_t *state, unsigned int req_pstate)
+{
+	assert(cpu == plat_my_core_pos());
+
+	plat_mt_pm_invoke_no_check(pwr_cpu_on, cpu, state);
+
+	coordinate_cluster_pwron();
+
+	/* Enable the GIC CPU interface */
+	gicv3_rdistif_on(cpu);
+	gicv3_cpuif_enable(cpu);
+	mt_gic_rdistif_init();
+
+	/*
+	 * If mcusys does power down before then restore
+	 * all CPUs' GIC Redistributors
+	 */
+	if (IS_MCUSYS_OFF_STATE(state)) {
+		mt_gic_rdistif_restore_all();
+	} else {
+		mt_gic_rdistif_restore();
+	}
+}
+
+/*
+ * Common MTK_platform operations to power on/off a
+ * cluster in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
+ */
+
+static void plat_cluster_pwrdwn_common(unsigned int cpu,
+		const psci_power_state_t *state, unsigned int req_pstate)
+{
+	assert(cpu == plat_my_core_pos());
+
+	if (plat_mt_pm_invoke(pwr_cluster_dwn, cpu, state) != 0) {
+		coordinate_cluster_pwron();
+
+		/* TODO: return on fail.
+		 *       Add a 'return' here before adding any code following
+		 *       the if-block.
+		 */
+	}
+}
+
+static void plat_cluster_pwron_common(unsigned int cpu,
+		const psci_power_state_t *state, unsigned int req_pstate)
+{
+	assert(cpu == plat_my_core_pos());
+
+	if (plat_mt_pm_invoke(pwr_cluster_on, cpu, state) != 0) {
+		/* TODO: return on fail.
+		 *       Add a 'return' here before adding any code following
+		 *       the if-block.
+		 */
+	}
+}
+
+/*
+ * Common MTK_platform operations to power on/off a
+ * mcusys in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
+ */
+
+static void plat_mcusys_pwrdwn_common(unsigned int cpu,
+		const psci_power_state_t *state, unsigned int req_pstate)
+{
+	assert(cpu == plat_my_core_pos());
+
+	if (plat_mt_pm_invoke(pwr_mcusys_dwn, cpu, state) != 0) {
+		return;		/* return on fail */
+	}
+
+	mt_gic_distif_save();
+	gic_sgi_save_all();
+}
+
+static void plat_mcusys_pwron_common(unsigned int cpu,
+		const psci_power_state_t *state, unsigned int req_pstate)
+{
+	assert(cpu == plat_my_core_pos());
+
+	if (plat_mt_pm_invoke(pwr_mcusys_on, cpu, state) != 0) {
+		return;		/* return on fail */
+	}
+
+	mt_gic_init();
+	mt_gic_distif_restore();
+	gic_sgi_restore_all();
+
+	plat_mt_pm_invoke_no_check(pwr_mcusys_on_finished, cpu, state);
+}
+
+/*
+ * plat_psci_ops implementation
+ */
+
+static void plat_cpu_standby(plat_local_state_t cpu_state)
+{
+	uint64_t scr;
+
+	scr = read_scr_el3();
+	write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
+
+	isb();
+	dsb();
+	wfi();
+
+	write_scr_el3(scr);
+}
+
+static int plat_power_domain_on(u_register_t mpidr)
+{
+	unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
+	unsigned int cluster = 0U;
+
+	if (cpu >= PLATFORM_CORE_COUNT) {
+		return PSCI_E_INVALID_PARAMS;
+	}
+
+	if (!spm_get_cluster_powerstate(cluster)) {
+		spm_poweron_cluster(cluster);
+	}
+
+	/* init CPU reset arch as AARCH64 */
+	mcucfg_init_archstate(cluster, cpu, true);
+	mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
+	spm_poweron_cpu(cluster, cpu);
+
+	return PSCI_E_SUCCESS;
+}
+
+static void plat_power_domain_on_finish(const psci_power_state_t *state)
+{
+	unsigned long mpidr = read_mpidr_el1();
+	unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
+
+	assert(cpu < PLATFORM_CORE_COUNT);
+
+	/* Allow IRQs to wakeup this core in IDLE flow */
+	mcucfg_enable_gic_wakeup(0U, cpu);
+
+	if (IS_CLUSTER_OFF_STATE(state)) {
+		plat_cluster_pwron_common(cpu, state, 0U);
+	}
+
+	plat_cpu_pwron_common(cpu, state, 0U);
+}
+
+static void plat_power_domain_off(const psci_power_state_t *state)
+{
+	unsigned long mpidr = read_mpidr_el1();
+	unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
+
+	assert(cpu < PLATFORM_CORE_COUNT);
+
+	plat_cpu_pwrdwn_common(cpu, state, 0U);
+	spm_poweroff_cpu(0U, cpu);
+
+	/* prevent unintended IRQs from waking up the hot-unplugged core */
+	mcucfg_disable_gic_wakeup(0U, cpu);
+
+	if (IS_CLUSTER_OFF_STATE(state)) {
+		plat_cluster_pwrdwn_common(cpu, state, 0U);
+	}
+}
+
+static void plat_power_domain_suspend(const psci_power_state_t *state)
+{
+	unsigned int cpu = plat_my_core_pos();
+
+	assert(cpu < PLATFORM_CORE_COUNT);
+
+	plat_mt_pm_invoke_no_check(pwr_prompt, cpu, state);
+
+	/* Perform the common CPU specific operations */
+	plat_cpu_pwrdwn_common(cpu, state, plat_power_state[cpu]);
+
+	if (IS_CLUSTER_OFF_STATE(state)) {
+		/* Perform the common cluster specific operations */
+		plat_cluster_pwrdwn_common(cpu, state, plat_power_state[cpu]);
+	}
+
+	if (IS_MCUSYS_OFF_STATE(state)) {
+		/* Perform the common mcusys specific operations */
+		plat_mcusys_pwrdwn_common(cpu, state, plat_power_state[cpu]);
+	}
+}
+
+static void plat_power_domain_suspend_finish(const psci_power_state_t *state)
+{
+	unsigned int cpu = plat_my_core_pos();
+
+	assert(cpu < PLATFORM_CORE_COUNT);
+
+	if (IS_MCUSYS_OFF_STATE(state)) {
+		/* Perform the common mcusys specific operations */
+		plat_mcusys_pwron_common(cpu, state, plat_power_state[cpu]);
+	}
+
+	if (IS_CLUSTER_OFF_STATE(state)) {
+		/* Perform the common cluster specific operations */
+		plat_cluster_pwron_common(cpu, state, plat_power_state[cpu]);
+	}
+
+	/* Perform the common CPU specific operations */
+	plat_cpu_pwron_common(cpu, state, plat_power_state[cpu]);
+
+	plat_mt_pm_invoke_no_check(pwr_reflect, cpu, state);
+}
+
+static int plat_validate_power_state(unsigned int power_state,
+					psci_power_state_t *req_state)
+{
+	unsigned int pstate = psci_get_pstate_type(power_state);
+	unsigned int aff_lvl = psci_get_pstate_pwrlvl(power_state);
+	unsigned int cpu = plat_my_core_pos();
+
+	if (aff_lvl > PLAT_MAX_PWR_LVL) {
+		return PSCI_E_INVALID_PARAMS;
+	}
+
+	if (pstate == PSTATE_TYPE_STANDBY) {
+		req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE;
+	} else {
+		unsigned int i;
+		unsigned int pstate_id = psci_get_pstate_id(power_state);
+		plat_local_state_t s = MTK_LOCAL_STATE_OFF;
+
+		/* Use pstate_id to be power domain state */
+		if (pstate_id > s) {
+			s = (plat_local_state_t)pstate_id;
+		}
+
+		for (i = 0U; i <= aff_lvl; i++) {
+			req_state->pwr_domain_state[i] = s;
+		}
+	}
+
+	plat_power_state[cpu] = power_state;
+	return PSCI_E_SUCCESS;
+}
+
+static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
+{
+	unsigned int lv;
+	unsigned int cpu = plat_my_core_pos();
+
+	for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) {
+		req_state->pwr_domain_state[lv] = PLAT_MAX_OFF_STATE;
+	}
+
+	plat_power_state[cpu] =
+			psci_make_powerstate(
+				MT_PLAT_PWR_STATE_SYSTEM_SUSPEND,
+				PSTATE_TYPE_POWERDOWN, PLAT_MAX_PWR_LVL);
+
+	flush_dcache_range((uintptr_t)
+			&plat_power_state[cpu],
+			sizeof(plat_power_state[cpu]));
+}
+
+/*******************************************************************************
+ * MTK handlers to shutdown/reboot the system
+ ******************************************************************************/
+static void __dead2 plat_mtk_system_reset(void)
+{
+	struct bl_aux_gpio_info *gpio_reset = plat_get_mtk_gpio_reset();
+
+	INFO("MTK System Reset\n");
+
+	gpio_set_value(gpio_reset->index, gpio_reset->polarity);
+
+	wfi();
+	ERROR("MTK System Reset: operation not handled.\n");
+	panic();
+}
+
+static void __dead2 plat_mtk_system_off(void)
+{
+	INFO("MTK System Off\n");
+
+	rtc_power_off_sequence();
+	pmic_power_off();
+
+	wfi();
+	ERROR("MTK System Off: operation not handled.\n");
+	panic();
+}
+
+static const plat_psci_ops_t plat_psci_ops = {
+	.system_reset			= plat_mtk_system_reset,
+	.system_off			= plat_mtk_system_off,
+	.cpu_standby			= plat_cpu_standby,
+	.pwr_domain_on			= plat_power_domain_on,
+	.pwr_domain_on_finish		= plat_power_domain_on_finish,
+	.pwr_domain_off			= plat_power_domain_off,
+	.pwr_domain_suspend		= plat_power_domain_suspend,
+	.pwr_domain_suspend_finish	= plat_power_domain_suspend_finish,
+	.validate_power_state		= plat_validate_power_state,
+	.get_sys_suspend_power_state	= plat_get_sys_suspend_power_state
+};
+
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+			const plat_psci_ops_t **psci_ops)
+{
+	*psci_ops = &plat_psci_ops;
+	secure_entrypoint = sec_entrypoint;
+
+	/*
+	 * init the warm reset config for boot CPU
+	 * reset arch as AARCH64
+	 * reset addr as function bl31_warm_entrypoint()
+	 */
+	mcucfg_init_archstate(0U, 0U, true);
+	mcucfg_set_bootaddr(0U, 0U, secure_entrypoint);
+
+	spmc_init();
+	plat_mt_pm = mt_plat_cpu_pm_init();
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8195/plat_sip_calls.c b/plat/mediatek/mt8195/plat_sip_calls.c
new file mode 100644
index 0000000..a1e3c36
--- /dev/null
+++ b/plat/mediatek/mt8195/plat_sip_calls.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+
+uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
+				u_register_t x1,
+				u_register_t x2,
+				u_register_t x3,
+				u_register_t x4,
+				void *cookie,
+				void *handle,
+				u_register_t flags)
+{
+	switch (smc_fid) {
+	default:
+		ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
+		break;
+	}
+
+	SMC_RET1(handle, SMC_UNK);
+}
diff --git a/plat/mediatek/mt8195/plat_topology.c b/plat/mediatek/mt8195/plat_topology.c
new file mode 100644
index 0000000..bc95c64
--- /dev/null
+++ b/plat/mediatek/mt8195/plat_topology.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <lib/psci/psci.h>
+
+#include <plat_helpers.h>
+#include <platform_def.h>
+
+const unsigned char mtk_power_domain_tree_desc[] = {
+	/* Number of root nodes */
+	PLATFORM_SYSTEM_COUNT,
+	/* Number of children for the root node */
+	PLATFORM_MCUSYS_COUNT,
+	/* Number of children for the mcusys node */
+	PLATFORM_CLUSTER_COUNT,
+	/* Number of children for the first cluster node */
+	PLATFORM_CLUSTER0_CORE_COUNT,
+};
+
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+	return mtk_power_domain_tree_desc;
+}
+
+/*******************************************************************************
+ * This function implements a part of the critical interface between the psci
+ * generic layer and the platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error code (-1) is returned
+ * in case the MPIDR is invalid.
+ ******************************************************************************/
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+	unsigned int cluster_id, cpu_id;
+
+	if ((read_mpidr() & MPIDR_MT_MASK) != 0) {
+		/* ARMv8.2 arch */
+		if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0) {
+			return -1;
+		}
+		return plat_mediatek_calc_core_pos(mpidr);
+	}
+
+	mpidr &= MPIDR_AFFINITY_MASK;
+
+	if ((mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0) {
+		return -1;
+	}
+
+	cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+	cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
+
+	if (cluster_id >= PLATFORM_CLUSTER_COUNT) {
+		return -1;
+	}
+
+	/*
+	 * Validate cpu_id by checking whether it represents a CPU in
+	 * one of the two clusters present on the platform.
+	 */
+	if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) {
+		return -1;
+	}
+
+	return (cpu_id + (cluster_id * 8));
+}
diff --git a/plat/mediatek/mt8195/platform.mk b/plat/mediatek/mt8195/platform.mk
new file mode 100644
index 0000000..4d3ad59
--- /dev/null
+++ b/plat/mediatek/mt8195/platform.mk
@@ -0,0 +1,78 @@
+#
+# Copyright (c) 2021, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+MTK_PLAT     := plat/mediatek
+MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
+
+PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
+                 -I${MTK_PLAT}/common/drivers/gic600/             \
+                 -I${MTK_PLAT}/common/drivers/gpio/               \
+                 -I${MTK_PLAT}/common/drivers/rtc/                \
+                 -I${MTK_PLAT}/common/drivers/timer/              \
+                 -I${MTK_PLAT_SOC}/drivers/gpio/                  \
+                 -I${MTK_PLAT_SOC}/drivers/mcdi/                  \
+                 -I${MTK_PLAT_SOC}/drivers/pmic/                  \
+                 -I${MTK_PLAT_SOC}/drivers/spmc/                  \
+                 -I${MTK_PLAT_SOC}/include/
+
+GICV3_SUPPORT_GIC600        :=      1
+include drivers/arm/gic/v3/gicv3.mk
+include lib/xlat_tables_v2/xlat_tables.mk
+
+PLAT_BL_COMMON_SOURCES := ${GICV3_SOURCES}                              \
+                          ${XLAT_TABLES_LIB_SRCS}                       \
+                          plat/common/aarch64/crash_console_helpers.S   \
+                          plat/common/plat_psci_common.c
+
+
+BL31_SOURCES += common/desc_image_load.c                              \
+                drivers/delay_timer/delay_timer.c                     \
+                drivers/gpio/gpio.c                                   \
+                drivers/delay_timer/generic_delay_timer.c             \
+                drivers/ti/uart/aarch64/16550_console.S               \
+                lib/bl_aux_params/bl_aux_params.c                     \
+                lib/cpus/aarch64/cortex_a55.S                         \
+                lib/cpus/aarch64/cortex_a78.S                         \
+                plat/common/plat_gicv3.c                              \
+                ${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c         \
+                ${MTK_PLAT}/common/drivers/gpio/mtgpio_common.c       \
+                ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \
+                ${MTK_PLAT}/common/drivers/rtc/rtc_common.c           \
+                ${MTK_PLAT}/common/drivers/rtc/rtc_mt6359p.c          \
+                ${MTK_PLAT}/common/drivers/timer/mt_timer.c           \
+                ${MTK_PLAT}/common/mtk_cirq.c                         \
+                ${MTK_PLAT}/common/mtk_plat_common.c                  \
+                ${MTK_PLAT}/common/mtk_sip_svc.c                      \
+                ${MTK_PLAT}/common/params_setup.c                     \
+                ${MTK_PLAT_SOC}/aarch64/platform_common.c             \
+                ${MTK_PLAT_SOC}/aarch64/plat_helpers.S                \
+                ${MTK_PLAT_SOC}/bl31_plat_setup.c                     \
+                ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c                 \
+                ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c              \
+                ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c          \
+                ${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c                \
+                ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c                 \
+                ${MTK_PLAT_SOC}/drivers/pmic/pmic.c                   \
+                ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c                 \
+                ${MTK_PLAT_SOC}/plat_pm.c                             \
+                ${MTK_PLAT_SOC}/plat_sip_calls.c                      \
+                ${MTK_PLAT_SOC}/plat_topology.c
+
+# Configs for A78 and A55
+HW_ASSISTED_COHERENCY := 1
+USE_COHERENT_MEM := 0
+CTX_INCLUDE_AARCH32_REGS := 0
+ERRATA_A55_1530923 := 1
+
+# indicate the reset vector address can be programmed
+PROGRAMMABLE_RESET_ADDRESS := 1
+
+COLD_BOOT_SINGLE_CPU := 1
+
+MACH_MT8195 := 1
+$(eval $(call add_define,MACH_MT8195))
+
+include lib/coreboot/coreboot.mk
diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index 88a95c8..a3b353f 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk
@@ -107,7 +107,10 @@
 ifeq (${ARM_ARCH_MAJOR},8)
 BL1_SOURCES		+=	lib/cpus/aarch64/aem_generic.S		\
 				lib/cpus/aarch64/cortex_a53.S		\
-				lib/cpus/aarch64/cortex_a57.S
+				lib/cpus/aarch64/cortex_a57.S		\
+				lib/cpus/aarch64/cortex_a72.S		\
+				lib/cpus/aarch64/qemu_max.S		\
+
 else
 BL1_SOURCES		+=	lib/cpus/${ARCH}/cortex_a15.S
 endif
@@ -135,9 +138,9 @@
 BL2_SOURCES		+=	drivers/io/io_encrypted.c
 endif
 
-QEMU_GICV2_SOURCES	:=	drivers/arm/gic/v2/gicv2_helpers.c	\
-				drivers/arm/gic/v2/gicv2_main.c		\
-				drivers/arm/gic/common/gic_common.c	\
+# Include GICv2 driver files
+include drivers/arm/gic/v2/gicv2.mk
+QEMU_GICV2_SOURCES	:=	${GICV2_SOURCES}			\
 				plat/common/plat_gicv2.c		\
 				${PLAT_QEMU_COMMON_PATH}/qemu_gicv2.c
 
@@ -160,6 +163,8 @@
 BL31_SOURCES		+=	lib/cpus/aarch64/aem_generic.S		\
 				lib/cpus/aarch64/cortex_a53.S		\
 				lib/cpus/aarch64/cortex_a57.S		\
+				lib/cpus/aarch64/cortex_a72.S		\
+				lib/cpus/aarch64/qemu_max.S		\
 				lib/semihosting/semihosting.c		\
 				lib/semihosting/${ARCH}/semihosting_call.S \
 				plat/common/plat_psci_common.c		\
diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk
index d45f3f1..9fb30ad 100644
--- a/plat/qemu/qemu_sbsa/platform.mk
+++ b/plat/qemu/qemu_sbsa/platform.mk
@@ -48,7 +48,8 @@
 				${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c
 
 BL1_SOURCES		+=	lib/cpus/aarch64/cortex_a57.S			\
-				lib/cpus/aarch64/cortex_a72.S
+				lib/cpus/aarch64/cortex_a72.S			\
+				lib/cpus/aarch64/qemu_max.S			\
 
 BL2_SOURCES		+=	drivers/io/io_semihosting.c			\
 				drivers/io/io_storage.c				\
@@ -76,6 +77,7 @@
 
 BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a57.S			\
 				lib/cpus/aarch64/cortex_a72.S			\
+				lib/cpus/aarch64/qemu_max.S			\
 				lib/semihosting/semihosting.c			\
 				lib/semihosting/${ARCH}/semihosting_call.S	\
 				plat/common/plat_psci_common.c			\
diff --git a/plat/renesas/common/bl2_cpg_init.c b/plat/renesas/common/bl2_cpg_init.c
index 677a57d..ba8e53b 100644
--- a/plat/renesas/common/bl2_cpg_init.c
+++ b/plat/renesas/common/bl2_cpg_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,7 +13,8 @@
 
 static void bl2_secure_cpg_init(void);
 
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || \
+	(RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
 static void bl2_realtime_cpg_init_h3(void);
 static void bl2_system_cpg_init_h3(void);
 #endif
@@ -23,7 +24,7 @@
 static void bl2_system_cpg_init_m3(void);
 #endif
 
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N) || (RCAR_LSI == RZ_G2N)
 static void bl2_realtime_cpg_init_m3n(void);
 static void bl2_system_cpg_init_m3n(void);
 #endif
@@ -33,7 +34,7 @@
 static void bl2_system_cpg_init_v3m(void);
 #endif
 
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
 static void bl2_realtime_cpg_init_e3(void);
 static void bl2_system_cpg_init_e3(void);
 #endif
@@ -57,7 +58,7 @@
 #if (RCAR_LSI == RCAR_D3)
 	reset_cr2 = 0x00000000U;
 	stop_cr2 = 0xFFFFFFFFU;
-#elif (RCAR_LSI == RCAR_E3)
+#elif (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
 	reset_cr2 = 0x10000000U;
 	stop_cr2 = 0xEFFFFFFFU;
 #else
@@ -106,7 +107,8 @@
 	cpg_write(SCSRSTECR11, 0x00000000U);
 }
 
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || \
+	(RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
 static void bl2_realtime_cpg_init_h3(void)
 {
 	uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
@@ -185,7 +187,7 @@
 }
 #endif
 
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)  || (RCAR_LSI == RZ_G2N)
 static void bl2_realtime_cpg_init_m3n(void)
 {
 	/* Realtime Module Stop Control Registers */
@@ -253,7 +255,7 @@
 }
 #endif
 
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
 static void bl2_realtime_cpg_init_e3(void)
 {
 	/* Realtime Module Stop Control Registers */
@@ -360,15 +362,15 @@
 			panic();
 			break;
 		}
-#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
 		bl2_realtime_cpg_init_h3();
 #elif (RCAR_LSI == RCAR_M3) || (RCAR_LSI == RZ_G2M)
 		bl2_realtime_cpg_init_m3();
-#elif RCAR_LSI == RCAR_M3N
+#elif RCAR_LSI == RCAR_M3N || (RCAR_LSI == RZ_G2N)
 		bl2_realtime_cpg_init_m3n();
 #elif RCAR_LSI == RCAR_V3M
 		bl2_realtime_cpg_init_v3m();
-#elif RCAR_LSI == RCAR_E3
+#elif RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2E
 		bl2_realtime_cpg_init_e3();
 #elif RCAR_LSI == RCAR_D3
 		bl2_realtime_cpg_init_d3();
@@ -406,15 +408,15 @@
 		panic();
 		break;
 	}
-#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
 	bl2_system_cpg_init_h3();
 #elif (RCAR_LSI == RCAR_M3) || (RCAR_LSI == RZ_G2M)
 	bl2_system_cpg_init_m3();
-#elif RCAR_LSI == RCAR_M3N
+#elif RCAR_LSI == RCAR_M3N  || (RCAR_LSI == RZ_G2N)
 	bl2_system_cpg_init_m3n();
 #elif RCAR_LSI == RCAR_V3M
 	bl2_system_cpg_init_v3m();
-#elif RCAR_LSI == RCAR_E3
+#elif RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2E
 	bl2_system_cpg_init_e3();
 #elif RCAR_LSI == RCAR_D3
 	bl2_system_cpg_init_d3();
diff --git a/plat/renesas/common/common.mk b/plat/renesas/common/common.mk
index 984ab5b..fafce98 100644
--- a/plat/renesas/common/common.mk
+++ b/plat/renesas/common/common.mk
@@ -34,6 +34,9 @@
 RCAR_V3M:=6
 RCAR_AUTO:=99
 RZ_G2M:=100
+RZ_G2H:=101
+RZ_G2N:=102
+RZ_G2E:=103
 $(eval $(call add_define,RCAR_H3))
 $(eval $(call add_define,RCAR_M3))
 $(eval $(call add_define,RCAR_M3N))
@@ -43,6 +46,9 @@
 $(eval $(call add_define,RCAR_V3M))
 $(eval $(call add_define,RCAR_AUTO))
 $(eval $(call add_define,RZ_G2M))
+$(eval $(call add_define,RZ_G2H))
+$(eval $(call add_define,RZ_G2N))
+$(eval $(call add_define,RZ_G2E))
 
 RCAR_CUT_10:=0
 RCAR_CUT_11:=1
diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
index 5e4978c..7a7a56c 100644
--- a/plat/renesas/rcar/platform.mk
+++ b/plat/renesas/rcar/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -293,12 +293,12 @@
   endif
 endif
 
-include drivers/renesas/rcar/ddr/ddr.mk
+include drivers/renesas/common/ddr/ddr.mk
 include drivers/renesas/rcar/qos/qos.mk
 include drivers/renesas/rcar/pfc/pfc.mk
 include lib/libfdt/libfdt.mk
 
-PLAT_INCLUDES	+=	-Idrivers/renesas/rcar/ddr		\
+PLAT_INCLUDES	+=	-Idrivers/renesas/common/ddr		\
 			-Idrivers/renesas/rcar/qos		\
 			-Idrivers/renesas/rcar/board		\
 			-Idrivers/renesas/rcar/cpld/		\
diff --git a/plat/renesas/rzg/bl2_plat_setup.c b/plat/renesas/rzg/bl2_plat_setup.c
index 13f413b..ccc2562 100644
--- a/plat/renesas/rzg/bl2_plat_setup.c
+++ b/plat/renesas/rzg/bl2_plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -78,12 +78,26 @@
 #if RCAR_LSI == RZ_G2M
 #define TARGET_PRODUCT			PRR_PRODUCT_M3
 #define TARGET_NAME			"RZ/G2M"
+#elif RCAR_LSI == RZ_G2H
+#define TARGET_PRODUCT			PRR_PRODUCT_H3
+#define TARGET_NAME			"RZ/G2H"
+#elif RCAR_LSI == RZ_G2N
+#define TARGET_PRODUCT			PRR_PRODUCT_M3N
+#define TARGET_NAME			"RZ/G2N"
+#elif RCAR_LSI == RZ_G2E
+#define TARGET_PRODUCT			PRR_PRODUCT_E3
+#define TARGET_NAME			"RZ/G2E"
 #elif RCAR_LSI == RCAR_AUTO
 #define TARGET_NAME			"RZ/G2M"
 #endif /* RCAR_LSI == RZ_G2M */
 
+#if (RCAR_LSI == RZ_G2E)
+#define GPIO_INDT			(GPIO_INDT6)
+#define GPIO_BKUP_TRG_SHIFT		((uint32_t)1U << 13U)
+#else
 #define GPIO_INDT			(GPIO_INDT1)
 #define GPIO_BKUP_TRG_SHIFT		(1U << 8U)
+#endif /* RCAR_LSI == RZ_G2E */
 
 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100)
 	 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE),
@@ -424,6 +438,18 @@
 		ret = fdt_setprop_string(dt, 0, "compatible",
 					 "hoperun,hihope-rzg2m");
 		break;
+	case BOARD_HIHOPE_RZ_G2H:
+		ret = fdt_setprop_string(dt, 0, "compatible",
+					 "hoperun,hihope-rzg2h");
+		break;
+	case BOARD_HIHOPE_RZ_G2N:
+		ret = fdt_setprop_string(dt, 0, "compatible",
+					 "hoperun,hihope-rzg2n");
+		break;
+	case BOARD_EK874_RZ_G2E:
+		ret = fdt_setprop_string(dt, 0, "compatible",
+					 "si-linux,cat874");
+		break;
 	default:
 		NOTICE("BL2: Cannot set compatible string, board unsupported\n");
 		panic();
@@ -441,6 +467,18 @@
 		ret = fdt_appendprop_string(dt, 0, "compatible",
 					    "renesas,r8a774a1");
 		break;
+	case PRR_PRODUCT_H3:
+		ret = fdt_appendprop_string(dt, 0, "compatible",
+					    "renesas,r8a774e1");
+		break;
+	case PRR_PRODUCT_M3N:
+		ret = fdt_appendprop_string(dt, 0, "compatible",
+					    "renesas,r8a774b1");
+		break;
+	case PRR_PRODUCT_E3:
+		ret = fdt_appendprop_string(dt, 0, "compatible",
+					    "renesas,r8a774c0");
+		break;
 	default:
 		NOTICE("BL2: Cannot set compatible string, SoC unsupported\n");
 		panic();
@@ -560,6 +598,42 @@
 		dram_config[1] = 0x80000000ULL;
 		dram_config[5] = 0x80000000ULL;
 		break;
+	case PRR_PRODUCT_H3:
+#if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
+		/* 4GB(1GBx4) */
+		dram_config[1] = 0x40000000ULL;
+		dram_config[3] = 0x40000000ULL;
+		dram_config[5] = 0x40000000ULL;
+		dram_config[7] = 0x40000000ULL;
+#elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 5) && \
+	(RCAR_DRAM_SPLIT == 2)
+		/* 4GB(2GBx2 2ch split) */
+		dram_config[1] = 0x80000000ULL;
+		dram_config[3] = 0x80000000ULL;
+#elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15)
+		/* 8GB(2GBx4: default) */
+		dram_config[1] = 0x80000000ULL;
+		dram_config[3] = 0x80000000ULL;
+		dram_config[5] = 0x80000000ULL;
+		dram_config[7] = 0x80000000ULL;
+#endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */
+		break;
+	case PRR_PRODUCT_M3N:
+		/* 4GB(4GBx1) */
+		dram_config[1] = 0x100000000ULL;
+		break;
+	case PRR_PRODUCT_E3:
+#if (RCAR_DRAM_DDR3L_MEMCONF == 0)
+		/* 1GB(512MBx2) */
+		dram_config[1] = 0x40000000ULL;
+#elif (RCAR_DRAM_DDR3L_MEMCONF == 1)
+		/* 2GB(512MBx4) */
+		dram_config[1] = 0x80000000ULL;
+#elif (RCAR_DRAM_DDR3L_MEMCONF == 2)
+		/* 4GB(1GBx4) */
+		dram_config[1] = 0x100000000ULL;
+#endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */
+		break;
 	default:
 		NOTICE("BL2: Detected invalid DRAM entries\n");
 		break;
@@ -578,13 +652,23 @@
 	const char *unknown = "unknown";
 	const char *cpu_ca57 = "CA57";
 	const char *cpu_ca53 = "CA53";
+	const char *product_g2e = "G2E";
+	const char *product_g2h = "G2H";
 	const char *product_g2m = "G2M";
+	const char *product_g2n = "G2N";
 	const char *boot_hyper80 = "HyperFlash(80MHz)";
 	const char *boot_qspi40 = "QSPI Flash(40MHz)";
 	const char *boot_qspi80 = "QSPI Flash(80MHz)";
 	const char *boot_emmc25x1 = "eMMC(25MHz x1)";
 	const char *boot_emmc50x8 = "eMMC(50MHz x8)";
+#if (RCAR_LSI == RZ_G2E)
+	uint32_t sscg;
+	const char *sscg_on = "PLL1 SSCG Clock select";
+	const char *sscg_off = "PLL1 nonSSCG Clock select";
+	const char *boot_hyper160 = "HyperFlash(150MHz)";
+#else
 	const char *boot_hyper160 = "HyperFlash(160MHz)";
+#endif /* RCAR_LSI == RZ_G2E */
 #if RZG_LCS_STATE_DETECTION_ENABLE
 	uint32_t lcs;
 	const char *lcs_secure = "SE";
@@ -646,6 +730,15 @@
 	case PRR_PRODUCT_M3:
 		str = product_g2m;
 		break;
+	case PRR_PRODUCT_H3:
+		str = product_g2h;
+		break;
+	case PRR_PRODUCT_M3N:
+		str = product_g2n;
+		break;
+	case PRR_PRODUCT_E3:
+		str = product_g2e;
+		break;
 	default:
 		str = unknown;
 		break;
@@ -667,10 +760,22 @@
 		NOTICE("BL2: PRR is RZ/%s Ver.%d.%d\n", str, major, minor);
 	}
 
+#if (RCAR_LSI == RZ_G2E)
+	if (product == PRR_PRODUCT_E3) {
+		reg = mmio_read_32(RCAR_MODEMR);
+		sscg = reg & RCAR_SSCG_MASK;
+		str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;
+		NOTICE("BL2: %s\n", str);
+	}
+#endif /* RCAR_LSI == RZ_G2E */
+
 	rzg_get_board_type(&type, &rev);
 
 	switch (type) {
 	case BOARD_HIHOPE_RZ_G2M:
+	case BOARD_HIHOPE_RZ_G2H:
+	case BOARD_HIHOPE_RZ_G2N:
+	case BOARD_EK874_RZ_G2E:
 		break;
 	default:
 		type = BOARD_UNKNOWN;
@@ -762,7 +867,7 @@
 
 	if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
 	    boot_cpu == MODEMR_BOOT_CPU_CA53) {
-		ret = rzg_dram_init();
+		ret = rcar_dram_init();
 		if (ret != 0) {
 			NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret);
 			panic();
@@ -884,6 +989,9 @@
 
 static void bl2_init_generic_timer(void)
 {
+#if RCAR_LSI == RZ_G2E
+	uint32_t reg_cntfid = EXTAL_EBISU;
+#else
 	uint32_t reg_cntfid;
 	uint32_t modemr;
 	uint32_t modemr_pll;
@@ -899,6 +1007,7 @@
 
 	/* Set frequency data in CNTFID0 */
 	reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT];
+#endif /* RCAR_LSI == RZ_G2E */
 
 	/* Update memory mapped and register based frequency */
 	write_cntfrq_el0((u_register_t)reg_cntfid);
diff --git a/plat/renesas/rzg/platform.mk b/plat/renesas/rzg/platform.mk
index 421cbbe..f37d7d0 100644
--- a/plat/renesas/rzg/platform.mk
+++ b/plat/renesas/rzg/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -32,6 +32,55 @@
       endif
       $(eval $(call add_define,RCAR_LSI_CUT))
     endif
+  else ifeq (${LSI},G2H)
+    RCAR_LSI:=${RZ_G2H}
+    ifndef LSI_CUT
+      # enable compatible function.
+      RCAR_LSI_CUT_COMPAT := 1
+      $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+    else
+      # disable compatible function.
+      ifeq (${LSI_CUT},30)
+        RCAR_LSI_CUT:=20
+      else
+        $(error "Error: ${LSI_CUT} is not supported.")
+      endif
+      $(eval $(call add_define,RCAR_LSI_CUT))
+    endif
+  else ifeq (${LSI},G2N)
+    RCAR_LSI:=${RZ_G2N}
+    ifndef LSI_CUT
+      # enable compatible function.
+      RCAR_LSI_CUT_COMPAT := 1
+      $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+    else
+      # disable compatible function.
+      ifeq (${LSI_CUT},10)
+        RCAR_LSI_CUT:=0
+      else ifeq (${LSI_CUT},11)
+        RCAR_LSI_CUT:=1
+      else
+        $(error "Error: ${LSI_CUT} is not supported.")
+      endif
+      $(eval $(call add_define,RCAR_LSI_CUT))
+    endif
+  else ifeq (${LSI},G2E)
+    RCAR_LSI:=${RZ_G2E}
+    ifndef LSI_CUT
+      # enable compatible function.
+      RCAR_LSI_CUT_COMPAT := 1
+      $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+    else
+      # disable compatible function.
+      ifeq (${LSI_CUT},10)
+        RCAR_LSI_CUT:=0
+      else ifeq (${LSI_CUT},11)
+        RCAR_LSI_CUT:=1
+      else
+        $(error "Error: ${LSI_CUT} is not supported.")
+      endif
+      $(eval $(call add_define,RCAR_LSI_CUT))
+    endif
   else
     $(error "Error: ${LSI} is not supported.")
   endif
@@ -168,12 +217,15 @@
 endif
 $(eval $(call add_define,RCAR_SYSTEM_RESET_KEEPON_DDR))
 
-include drivers/renesas/rzg/ddr/ddr.mk
+RZG_SOC :=1
+$(eval $(call add_define,RZG_SOC))
+
+include drivers/renesas/common/ddr/ddr.mk
 include drivers/renesas/rzg/qos/qos.mk
 include drivers/renesas/rzg/pfc/pfc.mk
 include lib/libfdt/libfdt.mk
 
-PLAT_INCLUDES	+=	-Idrivers/renesas/rzg/ddr		\
+PLAT_INCLUDES	+=	-Idrivers/renesas/common/ddr		\
 			-Idrivers/renesas/rzg/qos		\
 			-Idrivers/renesas/rzg/board		\
 			-Idrivers/renesas/common		\
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index de36efc..8b8714c 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -117,6 +117,40 @@
 	NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
 }
 
+static interrupt_type_handler_t type_el3_interrupt_handler;
+
+int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
+{
+	/* Validate 'handler'*/
+	if (!handler) {
+		return -EINVAL;
+	}
+
+	type_el3_interrupt_handler = handler;
+
+	return 0;
+}
+
+static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
+					  void *handle, void *cookie)
+{
+	uint32_t intr_id;
+	interrupt_type_handler_t handler;
+
+	intr_id = plat_ic_get_pending_interrupt_id();
+	/* Currently we support one interrupt */
+	if (intr_id != PLAT_VERSAL_IPI_IRQ) {
+		WARN("Unexpected interrupt call: 0x%x\n", intr_id);
+		return 0;
+	}
+
+	handler = type_el3_interrupt_handler;
+	if (handler) {
+		return handler(intr_id, flags, handle, cookie);
+	}
+
+	return 0;
+}
 void bl31_platform_setup(void)
 {
 	/* Initialize the gic cpu and distributor interfaces */
@@ -126,6 +160,15 @@
 
 void bl31_plat_runtime_setup(void)
 {
+	uint64_t flags = 0;
+	uint64_t rc;
+
+	set_interrupt_rm_flag(flags, NON_SECURE);
+	rc = register_interrupt_type_handler(INTR_TYPE_EL3,
+					     rdo_el3_interrupt_handler, flags);
+	if (rc) {
+		panic();
+	}
 }
 
 /*
diff --git a/plat/xilinx/versal/include/plat_private.h b/plat/xilinx/versal/include/plat_private.h
index e302096..d12d13a 100644
--- a/plat/xilinx/versal/include/plat_private.h
+++ b/plat/xilinx/versal/include/plat_private.h
@@ -8,6 +8,7 @@
 #define PLAT_PRIVATE_H
 
 #include <lib/xlat_tables/xlat_tables.h>
+#include <bl31/interrupt_mgmt.h>
 
 void versal_config_setup(void);
 
@@ -22,5 +23,10 @@
 void plat_versal_gic_resume(void);
 
 unsigned int versal_calc_core_pos(u_register_t mpidr);
+/*
+ * Register handler to specific GIC entrance
+ * for INTR_TYPE_EL3 type of interrupt
+ */
+int request_intr_type_el3(uint32_t irq, interrupt_type_handler_t fiq_handler);
 
 #endif /* PLAT_PRIVATE_H */
diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h
index 4cdaea2..8b513ef 100644
--- a/plat/xilinx/versal/include/platform_def.h
+++ b/plat/xilinx/versal/include/platform_def.h
@@ -91,11 +91,14 @@
  */
 #define PLAT_VERSAL_G1S_IRQS	VERSAL_IRQ_SEC_PHY_TIMER
 #define PLAT_VERSAL_G0_IRQS	VERSAL_IRQ_SEC_PHY_TIMER
+#define PLAT_VERSAL_IPI_IRQ	62
 
 #define PLAT_VERSAL_G1S_IRQ_PROPS(grp) \
 	INTR_PROP_DESC(VERSAL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
 			GIC_INTR_CFG_LEVEL)
 
-#define PLAT_VERSAL_G0_IRQ_PROPS(grp)
+#define PLAT_VERSAL_G0_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE), \
 
 #endif /* PLATFORM_DEF_H */
diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c
index a578543..15fe187 100644
--- a/plat/xilinx/versal/pm_service/pm_api_sys.c
+++ b/plat/xilinx/versal/pm_service/pm_api_sys.c
@@ -15,6 +15,8 @@
 #include "pm_api_sys.h"
 #include "pm_client.h"
 #include "pm_defs.h"
+#include "pm_svc_main.h"
+#include "../drivers/arm/gic/v3/gicv3_private.h"
 
 /*********************************************************************
  * Target module IDs macros
@@ -22,6 +24,7 @@
 #define LIBPM_MODULE_ID		0x2
 #define LOADER_MODULE_ID	0x7
 
+#define  MODE	0x80000000
 /* default shutdown/reboot scope is system(2) */
 static unsigned int pm_shutdown_scope = XPM_SHUTDOWN_SUBTYPE_RST_SYSTEM;
 
@@ -861,6 +864,7 @@
 				uint32_t flag)
 {
 	uint32_t payload[PAYLOAD_ARG_CNT];
+	int ret;
 
 	switch (ioctl_id) {
 	case IOCTL_SET_PLL_FRAC_MODE:
@@ -871,6 +875,15 @@
 		return pm_pll_set_param(arg1, PM_PLL_PARAM_DATA, arg2, flag);
 	case IOCTL_GET_PLL_FRAC_DATA:
 		return pm_pll_get_param(arg1, PM_PLL_PARAM_DATA, value, flag);
+	case IOCTL_SET_SGI:
+		/* Get the sgi number */
+		ret = pm_register_sgi(arg1);
+		if (ret) {
+			return PM_RET_ERROR_ARGS;
+		}
+		gicd_write_irouter(gicv3_driver_data->gicd_base,
+				PLAT_VERSAL_IPI_IRQ, MODE);
+		return PM_RET_SUCCESS;
 	default:
 		/* Send request to the PMC */
 		PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, flag, PM_IOCTL,
diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h
index 793f750..ccb2617 100644
--- a/plat/xilinx/versal/pm_service/pm_defs.h
+++ b/plat/xilinx/versal/pm_service/pm_defs.h
@@ -92,6 +92,7 @@
 #define	IOCTL_GET_PLL_FRAC_MODE		9
 #define	IOCTL_SET_PLL_FRAC_DATA		10
 #define	IOCTL_GET_PLL_FRAC_DATA		11
+#define	IOCTL_SET_SGI			25
 
 /* Parameter ID for PLL IOCTLs */
 /* Fractional data portion for PLL */
diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c
index 55a0956..87ba732 100644
--- a/plat/xilinx/versal/pm_service/pm_svc_main.c
+++ b/plat/xilinx/versal/pm_service/pm_svc_main.c
@@ -13,12 +13,64 @@
 #include <plat_private.h>
 #include <stdbool.h>
 #include <common/runtime_svc.h>
+#include <plat/common/platform.h>
 #include "pm_api_sys.h"
 #include "pm_client.h"
 #include "pm_ipi.h"
+#include <drivers/arm/gicv3.h>
+
+#define XSCUGIC_SGIR_EL1_INITID_SHIFT    24U
+#define INVALID_SGI    0xFF
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_asgi1r_el1, S3_0_C12_C11_6)
 
 /* pm_up = true - UP, pm_up = false - DOWN */
 static bool pm_up;
+static unsigned int sgi = INVALID_SGI;
+
+static uint64_t ipi_fiq_handler(uint32_t id, uint32_t flags, void *handle,
+				void *cookie)
+{
+	int cpu;
+	unsigned int reg;
+
+	(void)plat_ic_acknowledge_interrupt();
+	cpu = plat_my_core_pos() + 1;
+
+	if (sgi != INVALID_SGI) {
+		reg = (cpu | (sgi << XSCUGIC_SGIR_EL1_INITID_SHIFT));
+		write_icc_asgi1r_el1(reg);
+	}
+
+	/* Clear FIQ */
+	plat_ic_end_of_interrupt(id);
+
+	return 0;
+}
+
+/**
+ * pm_register_sgi() - PM register the IPI interrupt
+ *
+ * @sgi -  SGI number to be used for communication.
+ * @return	On success, the initialization function must return 0.
+ *		Any other return value will cause the framework to ignore
+ *		the service
+ *
+ * Update the SGI number to be used.
+ *
+ */
+int pm_register_sgi(unsigned int sgi_num)
+{
+	if (sgi != INVALID_SGI) {
+		return -EBUSY;
+	}
+
+	if (sgi_num >= GICV3_MAX_SGI_TARGETS) {
+		return -EINVAL;
+	}
+
+	sgi = sgi_num;
+	return 0;
+}
 
 /**
  * pm_setup() - PM service setup
@@ -46,6 +98,18 @@
 		pm_up = true;
 	}
 
+	/*
+	 * Enable IPI IRQ
+	 * assume the rich OS is OK to handle callback IRQs now.
+	 * Even if we were wrong, it would not enable the IRQ in
+	 * the GIC.
+	 */
+	pm_ipi_irq_enable(primary_proc);
+
+	ret = request_intr_type_el3(PLAT_VERSAL_IPI_IRQ, ipi_fiq_handler);
+	if (ret) {
+		WARN("BL31: registering IPI interrupt failed\n");
+	}
 	return ret;
 }
 
diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.h b/plat/xilinx/versal/pm_service/pm_svc_main.h
index 71329ca..4f8dc2b 100644
--- a/plat/xilinx/versal/pm_service/pm_svc_main.h
+++ b/plat/xilinx/versal/pm_service/pm_svc_main.h
@@ -14,4 +14,5 @@
 			uint64_t x4, void *cookie, void *handle,
 			uint64_t flags);
 
+int pm_register_sgi(unsigned int sgi_num);
 #endif /* PM_SVC_MAIN_H */
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index 339967c..b3365d9 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -350,10 +350,19 @@
 
 void zynqmp_config_setup(void)
 {
+	uint64_t counter_freq;
+
 	/* Configure IPI data for ZynqMP */
 	zynqmp_ipi_config_table_init();
 
 	zynqmp_print_platform_name();
+
+	/* Configure counter frequency */
+	counter_freq = read_cntfrq_el0();
+	if (counter_freq == ZYNQMP_DEFAULT_COUNTER_FREQ) {
+		write_cntfrq_el0(plat_get_syscnt_freq2());
+	}
+
 	generic_delay_timer_init();
 }
 
diff --git a/plat/xilinx/zynqmp/include/zynqmp_def.h b/plat/xilinx/zynqmp/include/zynqmp_def.h
index f474630..7e58391 100644
--- a/plat/xilinx/zynqmp/include/zynqmp_def.h
+++ b/plat/xilinx/zynqmp/include/zynqmp_def.h
@@ -17,6 +17,9 @@
 
 #define ZYNQMP_CONSOLE_IS(con)	(ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE)
 
+/* Default counter frequency */
+#define ZYNQMP_DEFAULT_COUNTER_FREQ	0U
+
 /* Firmware Image Package */
 #define ZYNQMP_PRIMARY_CPU		0