feat(nxp-clk): enable UART clock
Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.
Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h
index b2c01af..de633ae 100644
--- a/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h
+++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h
@@ -91,4 +91,8 @@
#define S32CC_CLK_PERIPH_PLL_MUX S32CC_ARCH_CLK(13)
#define S32CC_CLK_PERIPH_PLL_VCO S32CC_ARCH_CLK(14)
+#define S32CC_CLK_MC_CGM0_MUX8 S32CC_ARCH_CLK(15)
+#define S32CC_CLK_LINFLEX_BAUD S32CC_ARCH_CLK(16)
+#define S32CC_CLK_LINFLEX S32CC_ARCH_CLK(17)
+
#endif /* S32CC_CLK_IDS_H */