feat(nxp-clk): enable UART clock
Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.
Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
index 496724f..8c4a9e8 100644
--- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c
+++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
@@ -4,6 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <drivers/clk.h>
+#include <platform_def.h>
#include <s32cc-clk-drv.h>
#include <s32cc-clk-ids.h>
#include <s32cc-clk-utils.h>
@@ -14,7 +15,7 @@
#define S32CC_A53_FREQ (1U * GHZ)
#define S32CC_XBAR_2X_FREQ (800U * MHZ)
#define S32CC_PERIPH_PLL_VCO_FREQ (2U * GHZ)
-#define S32CC_PERIPH_PLL_PHI3_FREQ (125U * MHZ)
+#define S32CC_PERIPH_PLL_PHI3_FREQ UART_CLOCK_HZ
static int enable_fxosc_clk(void)
{
@@ -146,6 +147,23 @@
return ret;
}
+static int enable_uart_clk(void)
+{
+ int ret;
+
+ ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX8, S32CC_CLK_PERIPH_PLL_PHI3);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_enable(S32CC_CLK_LINFLEX_BAUD);
+ if (ret != 0) {
+ return ret;
+ }
+
+ return ret;
+}
+
int s32cc_init_early_clks(void)
{
int ret;
@@ -177,5 +195,10 @@
return ret;
}
+ ret = enable_uart_clk();
+ if (ret != 0) {
+ return ret;
+ }
+
return ret;
}