fix(cpus): workaround for Cortex-X2 erratum 1927200
Cortex-X2 erratum 1927200 is a Cat B erratum that applies to
revisions r0p0 and r1p0 and is fixed in r2p0.
The workaround is to use instruction patching to insert a DMB ST
before acquire atomic instructions without release semantics.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest
Change-Id: I8d9038df1907888b3c5b2520d06bc150665e74a1
Signed-off-by: John Powell <john.powell@arm.com>
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 3c36c93..0e93aa6 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -752,6 +752,10 @@
CPU. This needs to be enabled for revisions r0p0 and r1p0, it is fixed in
r2p0.
+- ``ERRATA_X2_1927200``: This applies errata 1927200 workaround to Cortex-X2
+ CPU. This needs to be enabled for revisions r0p0 and r1p0, it is fixed in
+ r2p0.
+
- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2
CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
it is still open.
diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S
index df7a220..0a65942 100644
--- a/lib/cpus/aarch64/cortex_x2.S
+++ b/lib/cpus/aarch64/cortex_x2.S
@@ -49,6 +49,37 @@
check_erratum_ls cortex_x2, ERRATUM(1917258), CPU_REV(1, 0)
+workaround_reset_start cortex_x2, ERRATUM(1927200), ERRATA_X2_1927200
+ mov x0, #0
+ msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
+ ldr x0, =0x10E3900002
+ msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */
+ ldr x0, =0x10FFF00083
+ msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */
+
+ mov x0, #1
+ msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
+ ldr x0, =0x10E3800082
+ msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */
+ ldr x0, =0x10FFF00083
+ msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */
+
+ mov x0, #2
+ msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
+ ldr x0, =0x10E3800200
+ msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */
+ ldr x0, =0x10FFF003E0
+ msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */
+workaround_reset_end cortex_x2, ERRATUM(1927200)
+
+check_erratum_ls cortex_x2, ERRATUM(1927200), CPU_REV(1, 0)
+
workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765
ldr x0, =0x6
msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 8629dbd..a233ef1 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -754,6 +754,10 @@
# to revisions r0p0 and r1p0 of the Cortex-X2 cpu, it is fixed in r2p0.
CPU_FLAG_LIST += ERRATA_X2_1917258
+# Flag to apply erratum 1927200 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the Cortex-X2 cpu, it is fixed in r2p0.
+CPU_FLAG_LIST += ERRATA_X2_1927200
+
# Flag to apply erratum 2002765 workaround during reset. This erratum applies
# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
CPU_FLAG_LIST += ERRATA_X2_2002765