refactor(st-clock): driver size optimization
Re-ordering structures to avoid gaps and minimize data.
Reduce type of gate_refcounts[], uint8_t is enough.
Re-ordering structures to avoid gaps and minimize data.
Use an unsigned char to define a clock ops type.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: I6b793dc34abdd6ef013609fc0f122da5d1824a34
diff --git a/drivers/st/clk/clk-stm32mp13.c b/drivers/st/clk/clk-stm32mp13.c
index 332c7d9..6a6ee5d 100644
--- a/drivers/st/clk/clk-stm32mp13.c
+++ b/drivers/st/clk/clk-stm32mp13.c
@@ -889,7 +889,7 @@
#endif
/* RCC clock device driver private */
-static unsigned int refcounts_mp13[CK_LAST];
+static uint8_t refcounts_mp13[CK_LAST];
static const struct stm32_clk_pll *clk_st32_pll_data(unsigned int idx);
@@ -1693,7 +1693,7 @@
}
struct stm32_pll_cfg {
- int pll_id;
+ uint8_t pll_id;
};
static unsigned long clk_stm32_pll_recalc_rate(struct stm32_clk_priv *priv, int id,
@@ -1775,12 +1775,12 @@
.clock_cfg = &(struct stm32_pll_cfg) {\
.pll_id = _pll_id,\
},\
- .ops = &clk_stm32_pll_ops,\
+ .ops = STM32_PLL_OPS,\
}
struct clk_stm32_composite_cfg {
- int gate_id;
- int div_id;
+ uint8_t gate_id;
+ uint8_t div_id;
};
static unsigned long clk_stm32_composite_recalc_rate(struct stm32_clk_priv *priv,
@@ -1832,9 +1832,32 @@
.gate_id = (_gate_id),\
.div_id = (_div_id),\
},\
- .ops = &clk_stm32_composite_ops,\
+ .ops = STM32_COMPOSITE_OPS,\
}
+enum {
+ STM32_PLL_OPS = STM32_LAST_OPS,
+ STM32_COMPOSITE_OPS,
+
+ MP13_LAST_OPS
+};
+
+static const struct stm32_clk_ops *ops_array_mp13[MP13_LAST_OPS] = {
+ [NO_OPS] = NULL,
+ [FIXED_FACTOR_OPS] = &clk_fixed_factor_ops,
+ [GATE_OPS] = &clk_gate_ops,
+ [STM32_MUX_OPS] = &clk_mux_ops,
+ [STM32_DIVIDER_OPS] = &clk_stm32_divider_ops,
+ [STM32_GATE_OPS] = &clk_stm32_gate_ops,
+ [STM32_TIMER_OPS] = &clk_timer_ops,
+ [STM32_FIXED_RATE_OPS] = &clk_stm32_fixed_rate_ops,
+ [STM32_OSC_OPS] = &clk_stm32_osc_ops,
+ [STM32_OSC_NOGATE_OPS] = &clk_stm32_osc_nogate_ops,
+
+ [STM32_PLL_OPS] = &clk_stm32_pll_ops,
+ [STM32_COMPOSITE_OPS] = &clk_stm32_composite_ops
+};
+
static const struct clk_stm32 stm32mp13_clk[CK_LAST] = {
/* ROOT CLOCKS */
CLK_FIXED_RATE(_CK_OFF, _NO_ID, 0),
@@ -1994,6 +2017,7 @@
.nb_osci_data = ARRAY_SIZE(stm32mp13_osc_data),
.gate_refcounts = refcounts_mp13,
.pdata = &stm32mp13_clock_pdata,
+ .ops_array = ops_array_mp13,
};
static int stm32mp1_init_clock_tree(void)