feat(fvp): add a GICv5 device tree
Tested with Linux v6.17-rc1, it boots as long as cpu idle is disabled.
Change-Id: Iadeb157e9d911c4228dc62c5610676f4c07f6c11
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Co-developed-by: Lorenzo Pieralisi <lorenzo.pieralisi2@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
diff --git a/docs/plat/arm/fvp/fvp-specific-configs.rst b/docs/plat/arm/fvp/fvp-specific-configs.rst
index 9608969..240700f 100644
--- a/docs/plat/arm/fvp/fvp-specific-configs.rst
+++ b/docs/plat/arm/fvp/fvp-specific-configs.rst
@@ -252,8 +252,7 @@
- The support is **not production-ready** and is intended to assist with
upstream kernel development and validation.
-- The device tree bindings are **not finalized**; support has been validated
- only with a **custom device tree**.
+- The device tree bindings are **not finalized**
- Use this configuration at your own discretion, understanding that the design
and register usage may change in future revisions.
@@ -271,4 +270,4 @@
--------------
-*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2025, Arm Limited. All rights reserved.*
diff --git a/fdts/fvp-base-gicv5-psci.dts b/fdts/fvp-base-gicv5-psci.dts
new file mode 100644
index 0000000..190f721
--- /dev/null
+++ b/fdts/fvp-base-gicv5-psci.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifdef FVP_MAX_PE_PER_CPU
+#define PE_PER_CPU FVP_MAX_PE_PER_CPU
+#else
+#define PE_PER_CPU 1
+#endif
+
+#define AFF 00
+#include "fvp-defs.dtsi"
+
+/dts-v1/;
+
+/memreserve/ 0x80000000 0x00010000;
+
+#include "fvp-base-gicv5.dtsi"
+#include "fvp-base-psci-common.dtsi"
diff --git a/fdts/fvp-base-gicv5.dtsi b/fdts/fvp-base-gicv5.dtsi
new file mode 100644
index 0000000..7a2c2fb
--- /dev/null
+++ b/fdts/fvp-base-gicv5.dtsi
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gicv5.h>
+
+/* TODO: rtsm_ve-motherboard.dtsi definitons */
+
+/ {
+ gic: interrupt-controller {
+ compatible = "arm,gic-v5";
+
+ #interrupt-cells = <3>;
+ interrupt-controller;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ interrupts = <GIC_PPI 25 IRQ_TYPE_LEVEL_HIGH>;
+
+ irs0: irs@2f1a0000 {
+ compatible = "arm,gic-v5-irs";
+ reg = <0x0 0x2f1a0000 0x0 0x10000>; /* NS IRS_CONFIG_FRAME */
+ reg-names = "ns-config";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cpus = <&CPU0
+ &CPU1
+ &CPU2
+ &CPU3
+ &CPU4
+ &CPU5
+ &CPU6
+ &CPU7>;
+ arm,iaffids = /bits/ 16 <0 1 2 3 4 5 6 7>;
+
+ its@2f120000 {
+ compatible = "arm,gic-v5-its";
+ reg = <0x0 0x2f120000 0x0 0x10000>; /* NS ITS_CONFIG_FRAME */
+ reg-names = "ns-config";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges;
+
+ its0: msi-controller@2f130000 {
+ reg = <0x0 0x2f130000 0x0 0x10000>; /* ITS_TRANSLATE_FRAME */
+ reg-names = "ns-translate";
+
+ #msi-cells = <1>;
+ msi-controller;
+ };
+ };
+ };
+ };
+
+ iwb0: interrupt-controller@2f000000 {
+ compatible = "arm,gic-v5-iwb";
+ reg = <0x0 0x2f000000 0x0 0x10000>;
+
+ #address-cells = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ msi-parent = <&its0 64>;
+ };
+
+ timer {
+ interrupts = <GIC_PPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer@2a810000 {
+ frame@2a830000 {
+ /* Formerly GIC_LPI 58, now wire 26 as SPI. */
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ pmu {
+ interrupts = <GIC_PPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ /*
+ * Previously these were mapped to SPIs 32-74. We now explicitly describe
+ * the wires on the IWB to which the interrupts are connected. All of the
+ * below are signalled as SPIs.
+ */
+ bus@8000000 {
+ interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 42 &iwb0 42 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 46 &iwb0 46 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+#if (ENABLE_RME == 1)
+ pci: pci@40000000 {
+ interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic 0 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic 0 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic 0 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+ msi-map = <0x0 &its0 0x0 0x10000>;
+ };
+ smmu: iommu@2b400000 {
+ interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 111 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 107 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 109 IRQ_TYPE_EDGE_RISING>;
+ msi-parent = <&its0 0x10000>;
+ };
+#endif /* ENABLE_RME */
+};
diff --git a/include/dt-bindings/interrupt-controller/arm-gicv5.h b/include/dt-bindings/interrupt-controller/arm-gicv5.h
new file mode 100644
index 0000000..80d0cb6
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/arm-gicv5.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GICV5_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GICV5_H
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/* interrupt specifier cell 0 - matches the values in the GICv5 specification */
+
+#define GIC_PPI 1
+#define GIC_LPI 2
+#define GIC_SPI 3
+
+#endif
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 17949e7..af4862c 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -148,7 +148,7 @@
USE_GIC_DRIVER := 5
ENABLE_FEAT_GCIE := 1
BL31_SOURCES += plat/arm/board/fvp/fvp_gicv5.c
-FVP_DT_PREFIX := "FVP does not provide a GICv5 dts yet"
+FVP_DT_PREFIX := fvp-base-gicv5-psci
ifneq ($(SPD),none)
$(error Error: GICv5 is not compatible with SPDs)
endif