Merge changes from topic "for-lts-v2.10.19" into lts-v2.10
* changes:
fix(imx8mp): remove ERR050463 VPUMIX workaround
fix(zynqmp): workaround issue around cntpct_el0
fix(cpus): workaround for Cortex-A710 erratum 1927200
fix(cpus): workaround for Cortex-A710 erratum 1917258
fix(cpus): workaround for Cortex-A710 erratum 1916945
fix(cpus): workaround for Cortex-A710 erratum 1901946
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 4ecdf6f..5941922 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -573,6 +573,22 @@
For Cortex-A710, the following errata build flags are defined :
+- ``ERRATA_A710_1901946``: This applies errata 1901946 workaround to
+ Cortex-A710 CPU. This needs to be enabled only for revision r1p0. It has
+ been fixed in r2p0.
+
+- ``ERRATA_A710_1916945``: This applies errata 1916945 workaround to
+ Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0.
+ It has been fixed in r2p0.
+
+- ``ERRATA_A710_1917258``: This applies errata 1917258 workaround to
+ Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0.
+ It has been fixed in r2p0.
+
+- ``ERRATA_A710_1927200``: This applies errata 1927200 workaround to
+ Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0.
+ It has been fixed in r2p0.
+
- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
r2p0 of the CPU. It is still open.
diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h
index a47a47e..ccd35f9 100644
--- a/include/lib/cpus/aarch64/cortex_a710.h
+++ b/include/lib/cpus/aarch64/cortex_a710.h
@@ -44,6 +44,11 @@
#define CORTEX_A710_CPUACTLR3_EL1 S3_0_C15_C1_2
/*******************************************************************************
+ * CPU Auxiliary Control register 4 specific definitions.
+ ******************************************************************************/
+#define CORTEX_A710_CPUACTLR4_EL1 S3_0_C15_C1_3
+
+/*******************************************************************************
* CPU Auxiliary Control register 5 specific definitions.
******************************************************************************/
#define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
index 40e777a..a6495ee 100644
--- a/lib/cpus/aarch64/cortex_a710.S
+++ b/lib/cpus/aarch64/cortex_a710.S
@@ -31,6 +31,55 @@
cpu_reset_prologue cortex_a710
+workaround_reset_start cortex_a710, ERRATUM(1901946), ERRATA_A710_1901946
+ sysreg_bit_set CORTEX_A710_CPUACTLR4_EL1, BIT(15)
+workaround_reset_end cortex_a710, ERRATUM(1901946)
+
+check_erratum_range cortex_a710, ERRATUM(1901946), CPU_REV(1, 0), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(1916945), ERRATA_A710_1916945
+ sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(8)
+workaround_reset_end cortex_a710, ERRATUM(1916945)
+
+check_erratum_ls cortex_a710, ERRATUM(1916945), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(1917258), ERRATA_A710_1917258
+ sysreg_bit_set CORTEX_A710_CPUACTLR4_EL1, BIT(43)
+workaround_reset_end cortex_a710, ERRATUM(1917258)
+
+check_erratum_ls cortex_a710, ERRATUM(1917258), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(1927200), ERRATA_A710_1927200
+ mov x0, #0
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0x10E3900002
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0x10FFF00083
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0
+
+ mov x0, #1
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0x10E3800082
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0x10FFF00083
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0
+
+ mov x0, #2
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0x10E3800200
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0x10FFF003E0
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0
+workaround_reset_end cortex_a710, ERRATUM(1927200)
+
+check_erratum_ls cortex_a710, ERRATUM(1927200), CPU_REV(1, 0)
+
workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031
ldr x0,=0x6
msr S3_6_c15_c8_0,x0
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index ebe8958..c1ed704 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -560,6 +560,22 @@
# the Neoverse V3 cpu and is still open.
CPU_FLAG_LIST += ERRATA_V3_3701767
+# Flag to apply erratum 1901946 workaround during reset. This erratum applies
+# to revision r1p0 and is fixed in r2p0.
+CPU_FLAG_LIST += ERRATA_A710_1901946
+
+# Flag to apply erratum 1916945 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the Cortex-A710 CPU and is fixed in r2p0.
+CPU_FLAG_LIST += ERRATA_A710_1916945
+
+# Flag to apply erratum 1917258 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the Cortex-A710 CPU and is fixed in r2p0.
+CPU_FLAG_LIST += ERRATA_A710_1917258
+
+# Flag to apply erratum 1927200 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the Cortex-A710 CPU and is fixed in r2p0.
+CPU_FLAG_LIST += ERRATA_A710_1927200
+
# Flag to apply erratum 1987031 workaround during reset. This erratum applies
# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
CPU_FLAG_LIST += ERRATA_A710_1987031
diff --git a/plat/imx/imx8m/imx8mp/gpc.c b/plat/imx/imx8m/imx8mp/gpc.c
index 956b508..ff1a849 100644
--- a/plat/imx/imx8m/imx8mp/gpc.c
+++ b/plat/imx/imx8m/imx8mp/gpc.c
@@ -268,23 +268,6 @@
/* set the PGC bit */
mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);
- /*
- * leave the G1, G2, H1 power domain on until VPUMIX power off,
- * otherwise system will hang due to VPUMIX ACK
- */
- if (domain_id == VPU_H1 || domain_id == VPU_G1 || domain_id == VPU_G2) {
- return;
- }
-
- if (domain_id == VPUMIX) {
- mmio_write_32(IMX_GPC_BASE + PU_PGC_DN_TRG, VPU_G1_PWR_REQ |
- VPU_G2_PWR_REQ | VPU_H1_PWR_REQ);
-
- while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & (VPU_G1_PWR_REQ |
- VPU_G2_PWR_REQ | VPU_H1_PWR_REQ))
- ;
- }
-
/* power down the domain */
mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req);
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index baf6717..67d8479 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -62,6 +62,26 @@
DISABLE_ALL_EXCEPTIONS);
}
+static inline uint64_t read_cntvct_el0(void)
+{
+ uint64_t val;
+
+ asm volatile("mrs %0, cntvct_el0" : "=r" (val));
+ return val;
+}
+
+static inline void reset_cntvct_el0_to_zero(void)
+{
+ asm volatile(
+ "mrs x0, cntpct_el0\n" /* Read physical counter into x0 */
+ "neg x0, x0\n" /* Negate it: x0 = -x0 */
+ "msr cntvoff_el2, x0\n" /* Write offset to virtual counter */
+ :
+ :
+ : "x0", "memory"
+ );
+}
+
/*
* Perform any BL31 specific platform actions. Here is an opportunity to copy
* parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they
@@ -78,6 +98,10 @@
/* Initialize the platform config for future decision making */
zynqmp_config_setup();
+ INFO("Counter TICK 0x%lx\n", read_cntvct_el0());
+ reset_cntvct_el0_to_zero();
+ INFO("Counter TICK after reset 0x%lx\n", read_cntvct_el0());
+
/*
* Do initial security configuration to allow DRAM/device access. On
* Base ZYNQMP only DRAM security is programmable (via TrustZone), but