fix(imx8mp): remove ERR050463 VPUMIX workaround
Errata ERR050463 has been fixed in A1 silicon.
Change-Id: I263531c6eef44a679002cd048e71fb50c63d9030
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
diff --git a/plat/imx/imx8m/imx8mp/gpc.c b/plat/imx/imx8m/imx8mp/gpc.c
index 956b508..ff1a849 100644
--- a/plat/imx/imx8m/imx8mp/gpc.c
+++ b/plat/imx/imx8m/imx8mp/gpc.c
@@ -268,23 +268,6 @@
/* set the PGC bit */
mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);
- /*
- * leave the G1, G2, H1 power domain on until VPUMIX power off,
- * otherwise system will hang due to VPUMIX ACK
- */
- if (domain_id == VPU_H1 || domain_id == VPU_G1 || domain_id == VPU_G2) {
- return;
- }
-
- if (domain_id == VPUMIX) {
- mmio_write_32(IMX_GPC_BASE + PU_PGC_DN_TRG, VPU_G1_PWR_REQ |
- VPU_G2_PWR_REQ | VPU_H1_PWR_REQ);
-
- while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & (VPU_G1_PWR_REQ |
- VPU_G2_PWR_REQ | VPU_H1_PWR_REQ))
- ;
- }
-
/* power down the domain */
mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req);