commit b0ce4024576e4d0ab8f7346d54e78db620af4c8a
author Yann Gautier <yann.gautier@st.com> Mon Aug 31 15:00:19 2020 +0200
committer Yann Gautier <yann.gautier@st.com> Fri Sep 08 10:56:49 2023 +0200
tree a001c6ed29fc88276358b4241ade904248822bc7
parent d2b66cc87e1f5507d309c973de4bd2100cac532c

refactor(st): rename QSPI macros

To have a more generic code, remove the Q from the *QSPI macros.

Change-Id: I2fa94b54054036c2175df3dfddcb76eec1119ad2
Signed-off-by: Yann Gautier <yann.gautier@st.com>

plat/st/common/bl2_io_storage.c

diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c
index 5b0a171..0bcfece 100644
--- a/plat/st/common/bl2_io_storage.c
+++ b/plat/st/common/bl2_io_storage.c
@@ -191,13 +191,13 @@
 	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
 		INFO("Using EMMC\n");
 		break;
-	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
-		INFO("Using QSPI NOR\n");
+	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
+		INFO("Using SPI NOR\n");
 		break;
 	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
 		INFO("Using FMC NAND\n");
 		break;
-	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
+	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI:
 		INFO("Using SPI NAND\n");
 		break;
 	case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART:
@@ -433,7 +433,7 @@
 		break;
 #endif
 #if STM32MP_SPI_NOR
-	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
+	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
 		dmbsy();
 		boot_spi_nor(boot_context);
 		break;
@@ -445,7 +445,7 @@
 		break;
 #endif
 #if STM32MP_SPI_NAND
-	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
+	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI:
 		dmbsy();
 		boot_spi_nand(boot_context);
 		break;
@@ -530,14 +530,14 @@
 	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
 #endif
 #if STM32MP_SPI_NAND
-	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
+	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI:
 #endif
 		image_block_spec.offset = STM32MP_NAND_FIP_OFFSET;
 		break;
 #endif
 
 #if STM32MP_SPI_NOR
-	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
+	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
 /*
  * With FWU Multi Bank feature enabled, the selection of
  * the image to boot will be done by fwu_init calling the
@@ -694,7 +694,7 @@
 			break;
 #endif
 #if STM32MP_SPI_NOR
-		case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
+		case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
 			if (guidcmp(img_uuid, &STM32MP_NOR_FIP_A_GUID) == 0) {
 				image_spec->offset = STM32MP_NOR_FIP_A_OFFSET;
 			} else if (guidcmp(img_uuid, &STM32MP_NOR_FIP_B_GUID) == 0) {
@@ -747,7 +747,7 @@
 #endif
 
 #if STM32MP_SPI_NOR
-	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
+	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
 		if (image_id == FWU_METADATA_IMAGE_ID) {
 			spec->offset = STM32MP_NOR_METADATA1_OFFSET;
 		} else {