feat(mt8196): enable apusys security control
Remap the request from domain 5, 7, 14 to domain 6 and setup security
sideband
Change-Id: I06d377f4bcc542bf22e0a04ffb45cf52b7528a75
Signed-off-by: Karl Li <karl.li@mediatek.com>
diff --git a/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c b/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c
new file mode 100644
index 0000000..208c1a9
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2024, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+
+#include <apusys_security_ctrl_plat.h>
+
+#define bits_clr(x, m, o) (x & (~(m << o)))
+#define bits_set(x, v, m, o) ((bits_clr(x, m, o)) | ((v & m) << o))
+
+static void sec_sideband_init(void)
+{
+ uint32_t value = mmio_read_32(SEC_CTRL_SIDE_BAND);
+
+ value = bits_set(value, SEC_CTRL_NARE_DOMAIN, SEC_CTRL_DOMAIN_MASK,
+ SEC_CTRL_NARE_DOMAIN_SHF);
+ value = bits_set(value, SEC_CTRL_NARE_NS, SEC_CTRL_NS_MASK, SEC_CTRL_NARE_NS_SHF);
+ value = bits_set(value, SEC_CTRL_SARE0_DOMAIN, SEC_CTRL_DOMAIN_MASK,
+ SEC_CTRL_SARE0_DOMAIN_SHF);
+ value = bits_set(value, SEC_CTRL_SARE0_NS, SEC_CTRL_NS_MASK, SEC_CTRL_SARE0_NS_SHF);
+ value = bits_set(value, SEC_CTRL_SARE1_DOMAIN, SEC_CTRL_DOMAIN_MASK,
+ SEC_CTRL_SARE1_DOMAIN_SHF);
+ value = bits_set(value, SEC_CTRL_SARE1_NS, SEC_CTRL_NS_MASK, SEC_CTRL_SARE1_NS_SHF);
+
+ mmio_write_32(SEC_CTRL_SIDE_BAND, value);
+}
+
+static void domain_remap_init(void)
+{
+ const uint32_t remap_domains[] = {
+ D0_REMAP_DOMAIN, D1_REMAP_DOMAIN, D2_REMAP_DOMAIN, D3_REMAP_DOMAIN,
+ D4_REMAP_DOMAIN, D5_REMAP_DOMAIN, D6_REMAP_DOMAIN, D7_REMAP_DOMAIN,
+ D8_REMAP_DOMAIN, D9_REMAP_DOMAIN, D10_REMAP_DOMAIN, D11_REMAP_DOMAIN,
+ D12_REMAP_DOMAIN, D13_REMAP_DOMAIN, D14_REMAP_DOMAIN, D15_REMAP_DOMAIN,
+ };
+ uint32_t lower_domain = 0;
+ uint32_t higher_domain = 0;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(remap_domains); i++) {
+ if (i < SEC_CTRL_REG_DOMAIN_NUM)
+ lower_domain |= (remap_domains[i] << (i * REG_DOMAIN_BITS));
+ else
+ higher_domain |= (remap_domains[i] <<
+ ((i - SEC_CTRL_REG_DOMAIN_NUM) * REG_DOMAIN_BITS));
+ }
+
+ mmio_write_32(SEC_CTRL_SOC2APU_SET1_0, lower_domain);
+ mmio_write_32(SEC_CTRL_SOC2APU_SET1_1, higher_domain);
+ mmio_setbits_32(APU_SEC_CON, SEC_CTRL_DOMAIN_REMAP_SEL);
+}
+
+void apusys_security_ctrl_init(void)
+{
+ domain_remap_init();
+ sec_sideband_init();
+}
diff --git a/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.h b/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.h
new file mode 100644
index 0000000..5e69777
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2024, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef APUSYS_SECURITY_CTRL_PLAT_H
+#define APUSYS_SECURITY_CTRL_PLAT_H
+
+#include <lib/utils_def.h>
+#include <platform_def.h>
+
+#define SEC_CTRL_SOC2APU_SET1_0 (APU_SEC_CON + 0xC)
+#define SEC_CTRL_SOC2APU_SET1_1 (APU_SEC_CON + 0x10)
+#define SEC_CTRL_SIDE_BAND (APU_SEC_CON + 0x24)
+
+#define SEC_CTRL_REG_DOMAIN_NUM (8)
+#define SEC_CTRL_DOMAIN_REMAP_SEL BIT(6)
+#define SEC_CTRL_DOMAIN_MASK (0xF)
+#define SEC_CTRL_NS_MASK (0x1)
+
+#define SEC_CTRL_NARE_DOMAIN (5)
+#define SEC_CTRL_NARE_NS (0)
+#define SEC_CTRL_NARE_DOMAIN_SHF (0)
+#define SEC_CTRL_NARE_NS_SHF (4)
+
+#define SEC_CTRL_SARE0_DOMAIN (5)
+#define SEC_CTRL_SARE0_NS (0)
+#define SEC_CTRL_SARE0_DOMAIN_SHF (5)
+#define SEC_CTRL_SARE0_NS_SHF (9)
+
+#define SEC_CTRL_SARE1_DOMAIN (5)
+#define SEC_CTRL_SARE1_NS (0)
+#define SEC_CTRL_SARE1_DOMAIN_SHF (10)
+#define SEC_CTRL_SARE1_NS_SHF (14)
+
+#define REG_DOMAIN_BITS (4)
+
+#define D0_REMAP_DOMAIN (0)
+#define D1_REMAP_DOMAIN (1)
+#define D2_REMAP_DOMAIN (2)
+#define D3_REMAP_DOMAIN (3)
+#define D4_REMAP_DOMAIN (4)
+#define D5_REMAP_DOMAIN (6)
+#define D6_REMAP_DOMAIN (6)
+#define D7_REMAP_DOMAIN (6)
+#define D8_REMAP_DOMAIN (8)
+#define D9_REMAP_DOMAIN (9)
+#define D10_REMAP_DOMAIN (10)
+#define D11_REMAP_DOMAIN (11)
+#define D12_REMAP_DOMAIN (12)
+#define D13_REMAP_DOMAIN (13)
+#define D14_REMAP_DOMAIN (6)
+#define D15_REMAP_DOMAIN (15)
+
+void apusys_security_ctrl_init(void);
+int apusys_plat_setup_sec_mem(void);
+
+#endif /* APUSYS_SECURITY_CTRL_PLAT_H */
diff --git a/plat/mediatek/drivers/apusys/mt8196/rules.mk b/plat/mediatek/drivers/apusys/mt8196/rules.mk
index 03a7c29..44c294d 100644
--- a/plat/mediatek/drivers/apusys/mt8196/rules.mk
+++ b/plat/mediatek/drivers/apusys/mt8196/rules.mk
@@ -8,7 +8,13 @@
MODULE := apusys_${MTK_SOC}
+ifeq (${CONFIG_MTK_APUSYS_EMI_SUPPORT}, y)
+PLAT_INCLUDES += -I${MTK_PLAT}/drivers/emi/common
+PLAT_INCLUDES += -I${MTK_PLAT}/drivers/emi/${MTK_SOC}
+endif
+
LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_devapc.c
LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_power.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_security_ctrl_plat.c
$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/apusys/rules.mk b/plat/mediatek/drivers/apusys/rules.mk
index 498925c..3c2fd2a 100644
--- a/plat/mediatek/drivers/apusys/rules.mk
+++ b/plat/mediatek/drivers/apusys/rules.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2023, MediaTek Inc. All rights reserved.
+# Copyright (c) 2023-2024, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -12,6 +12,8 @@
PLAT_INCLUDES += -I${LOCAL_DIR} -I${LOCAL_DIR}/${MTK_SOC} -I${LOCAL_DIR}/apusys_rv/2.0
+$(eval $(call add_defined_option,CONFIG_MTK_APUSYS_EMI_SUPPORT))
+
$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
SUB_RULES-y := ${LOCAL_DIR}/${MTK_SOC}
diff --git a/plat/mediatek/mt8196/include/platform_def.h b/plat/mediatek/mt8196/include/platform_def.h
index d17d637..402d23e 100644
--- a/plat/mediatek/mt8196/include/platform_def.h
+++ b/plat/mediatek/mt8196/include/platform_def.h
@@ -35,6 +35,7 @@
******************************************************************************/
#define APUSYS_BASE (IO_PHYS + 0x09000000)
#define APUSYS_CE_BASE (IO_PHYS + 0x090B0000)
+#define APU_SEC_CON (IO_PHYS + 0x090F5000)
#define APUSYS_CTRL_DAPC_AO_BASE (IO_PHYS + 0x090FC000)
#define APU_MBOX0 (0x4C200000)
diff --git a/plat/mediatek/mt8196/plat_config.mk b/plat/mediatek/mt8196/plat_config.mk
index dd83b9a..92c7c48 100644
--- a/plat/mediatek/mt8196/plat_config.mk
+++ b/plat/mediatek/mt8196/plat_config.mk
@@ -26,6 +26,7 @@
CTX_INCLUDE_AARCH32_REGS := 0
CONFIG_ARCH_ARM_V9 := y
+CONFIG_MTK_APUSYS_EMI_SUPPORT := n
CONFIG_MTK_MCUSYS := y
MCUSYS_VERSION := v1
CONFIG_MTK_PM_SUPPORT := y