Merge changes from topic "hm/handoff-cot" into integration
* changes:
docs(fconf): streamline TB_FW_CONFIG bindings
refactor(fconf): use macro to set image info
diff --git a/.commitlintrc.js b/.commitlintrc.js
index 53e3a63..51493ea 100644
--- a/.commitlintrc.js
+++ b/.commitlintrc.js
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -67,6 +67,6 @@
"type-enum": [2, "always", types], /* Error */
"scope-case": [2, "always", "lower-case"], /* Error */
- "scope-enum": [1, "always", scopes] /* Warning */
+ "scope-enum": [2, "always", scopes] /* Error */
},
};
diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..858e0c1
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,4 @@
+[submodule "libtl"]
+ path = contrib/libtl
+ url = https://review.trustedfirmware.org/shared/transfer-list-library
+ shallow = true
diff --git a/Makefile b/Makefile
index 530e6e0..125d587 100644
--- a/Makefile
+++ b/Makefile
@@ -99,15 +99,15 @@
# Variables for use with Certificate Generation Tool
CRTTOOLPATH ?= tools/cert_create
-CRTTOOL ?= ${CRTTOOLPATH}/cert_create$(.exe)
+CRTTOOL ?= ${BUILD_PLAT}/${CRTTOOLPATH}/cert_create$(.exe)
# Variables for use with Firmware Encryption Tool
ENCTOOLPATH ?= tools/encrypt_fw
-ENCTOOL ?= ${ENCTOOLPATH}/encrypt_fw$(.exe)
+ENCTOOL ?= ${BUILD_PLAT}/${ENCTOOLPATH}/encrypt_fw$(.exe)
# Variables for use with Firmware Image Package
FIPTOOLPATH ?= tools/fiptool
-FIPTOOL ?= ${FIPTOOLPATH}/fiptool$(.exe)
+FIPTOOL ?= ${BUILD_PLAT}/${FIPTOOLPATH}/fiptool$(.exe)
# Variables for use with sptool
SPTOOLPATH ?= tools/sptool
@@ -127,44 +127,9 @@
# Variables for use with documentation build using Sphinx tool
DOCS_PATH ?= docs
-################################################################################
-# Compiler Configuration based on ARCH_MAJOR and ARCH_MINOR flags
-################################################################################
-ifeq (${ARM_ARCH_MAJOR},7)
- target32-directive = -target arm-none-eabi
-# Will set march-directive from platform configuration
-else
- target32-directive = -target armv8a-none-eabi
-endif #(ARM_ARCH_MAJOR)
-
-################################################################################
-# Get Architecture Feature Modifiers
-################################################################################
-arch-features = ${ARM_ARCH_FEATURE}
-
-ifneq ($(filter %-clang,$($(ARCH)-cc-id)),)
- ifeq ($($(ARCH)-cc-id),arm-clang)
- TF_CFLAGS_aarch32 := -target arm-arm-none-eabi
- TF_CFLAGS_aarch64 := -target aarch64-arm-none-eabi
- else
- TF_CFLAGS_aarch32 = $(target32-directive)
- TF_CFLAGS_aarch64 := -target aarch64-unknown-none-elf
- endif
-
-else ifeq ($($(ARCH)-cc-id),gnu-gcc)
- # Enable LTO only for aarch64
- ifeq (${ARCH},aarch64)
- LTO_CFLAGS = $(if $(filter-out 0,$(ENABLE_LTO)),-flto)
- endif
-endif #(clang)
-
# Process Debug flag
-$(eval $(call add_define,DEBUG))
ifneq (${DEBUG}, 0)
BUILD_TYPE := debug
- TF_CFLAGS += -g -gdwarf-4
- ASFLAGS += -g -Wa,-gdwarf-4
-
# Use LOG_LEVEL_INFO by default for debug builds
LOG_LEVEL := 40
else
@@ -179,61 +144,6 @@
endif
VERSION_STRING := v${VERSION}(${BUILD_TYPE}):${BUILD_STRING}
-ifeq (${AARCH32_INSTRUCTION_SET},A32)
- TF_CFLAGS_aarch32 += -marm
-else ifeq (${AARCH32_INSTRUCTION_SET},T32)
- TF_CFLAGS_aarch32 += -mthumb
-else
- $(error Error: Unknown AArch32 instruction set ${AARCH32_INSTRUCTION_SET})
-endif #(AARCH32_INSTRUCTION_SET)
-
-TF_CFLAGS_aarch32 += -mno-unaligned-access
-TF_CFLAGS_aarch64 += -mgeneral-regs-only -mstrict-align
-
-##############################################################################
-# WARNINGS Configuration
-###############################################################################
-# General warnings
-WARNINGS := -Wall -Wmissing-include-dirs -Wunused \
- -Wdisabled-optimization -Wvla -Wshadow \
- -Wredundant-decls
-# stricter warnings
-WARNINGS += -Wextra -Wno-trigraphs
-# too verbose for generic build
-WARNINGS += -Wno-missing-field-initializers \
- -Wno-type-limits -Wno-sign-compare \
-# on clang this flag gets reset if -Wextra is set after it. No difference on gcc
-WARNINGS += -Wno-unused-parameter
-
-# Additional warnings
-# Level 1 - infrequent warnings we should have none of
-# full -Wextra
-WARNING1 += -Wsign-compare
-WARNING1 += -Wtype-limits
-WARNING1 += -Wmissing-field-initializers
-
-# Level 2 - problematic warnings that we want
-# zlib, compiler-rt, coreboot, and mbdedtls blow up with these
-# TODO: disable just for them and move into default build
-WARNING2 += -Wold-style-definition
-WARNING2 += -Wmissing-prototypes
-WARNING2 += -Wmissing-format-attribute
-# TF-A aims to comply with this eventually. Effort too large at present
-WARNING2 += -Wundef
-# currently very involved and many platforms set this off
-WARNING2 += -Wunused-const-variable=2
-
-# Level 3 - very pedantic, frequently ignored
-WARNING3 := -Wbad-function-cast
-WARNING3 += -Waggregate-return
-WARNING3 += -Wnested-externs
-WARNING3 += -Wcast-align
-WARNING3 += -Wcast-qual
-WARNING3 += -Wconversion
-WARNING3 += -Wpacked
-WARNING3 += -Wpointer-arith
-WARNING3 += -Wswitch-default
-
# Setting W is quite verbose and most warnings will be pre-existing issues
# outside of the contributor's control. Don't fail the build on them so warnings
# can be seen and hopefully addressed
@@ -243,121 +153,6 @@
endif
endif
-ifeq (${W},1)
- WARNINGS += $(WARNING1)
-else ifeq (${W},2)
- WARNINGS += $(WARNING1) $(WARNING2)
-else ifeq (${W},3)
- WARNINGS += $(WARNING1) $(WARNING2) $(WARNING3)
-endif #(W)
-
-# Compiler specific warnings
-ifeq ($(filter %-clang,$($(ARCH)-cc-id)),)
-# not using clang
-WARNINGS += -Wunused-but-set-variable -Wmaybe-uninitialized \
- -Wpacked-bitfield-compat -Wshift-overflow=2 \
- -Wlogical-op
-
-# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105523
-TF_CFLAGS_MIN_PAGE_SIZE := $(call cc_option, --param=min-pagesize=0)
-TF_CFLAGS += $(TF_CFLAGS_MIN_PAGE_SIZE)
-
-ifeq ($(HARDEN_SLS), 1)
- TF_CFLAGS_MHARDEN_SLS := $(call cc_option, -mharden-sls=all)
- TF_CFLAGS_aarch64 += $(TF_CFLAGS_MHARDEN_SLS)
-endif
-
-else
-# using clang
-WARNINGS += -Wshift-overflow -Wshift-sign-overflow \
- -Wlogical-op-parentheses
-endif #(Clang Warning)
-
-ifneq (${E},0)
- ERRORS := -Werror
-endif #(E)
-
-################################################################################
-# Compiler and Linker Directives
-################################################################################
-CPPFLAGS = ${DEFINES} ${INCLUDES} ${MBEDTLS_INC} -nostdinc \
- $(ERRORS) $(WARNINGS)
-ASFLAGS += $(CPPFLAGS) \
- -ffreestanding -Wa,--fatal-warnings
-TF_CFLAGS += $(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) \
- -ffunction-sections -fdata-sections \
- -ffreestanding -fno-common \
- -Os -std=gnu99
-
-ifeq (${SANITIZE_UB},on)
- TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover
-endif #(${SANITIZE_UB},on)
-
-ifeq (${SANITIZE_UB},trap)
- TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover \
- -fsanitize-undefined-trap-on-error
-endif #(${SANITIZE_UB},trap)
-
-GCC_V_OUTPUT := $(if $($(ARCH)-cc),$(shell $($(ARCH)-cc) -v 2>&1))
-
-TF_LDFLAGS += -z noexecstack
-
-# LD = armlink
-ifeq ($($(ARCH)-ld-id),arm-link)
- TF_LDFLAGS += --diag_error=warning --lto_level=O1
- TF_LDFLAGS += --remove --info=unused,unusedsymbols
- TF_LDFLAGS += $(TF_LDFLAGS_$(ARCH))
-
-# LD = gcc (used when GCC LTO is enabled)
-else ifeq ($($(ARCH)-ld-id),gnu-gcc)
- # Pass ld options with Wl or Xlinker switches
- TF_LDFLAGS += $(call ld_option,-Xlinker --no-warn-rwx-segments)
- TF_LDFLAGS += -Wl,--fatal-warnings -O1
- TF_LDFLAGS += -Wl,--gc-sections
-
- TF_LDFLAGS += -Wl,-z,common-page-size=4096 #Configure page size constants
- TF_LDFLAGS += -Wl,-z,max-page-size=4096
- TF_LDFLAGS += -Wl,--build-id=none
-
- ifeq ($(ENABLE_LTO),1)
- ifeq (${ARCH},aarch64)
- TF_LDFLAGS += -flto -fuse-linker-plugin
- TF_LDFLAGS += -flto-partition=one
- endif
- endif #(ENABLE_LTO)
-
-# GCC automatically adds fix-cortex-a53-843419 flag when used to link
-# which breaks some builds, so disable if errata fix is not explicitly enabled
- ifeq (${ARCH},aarch64)
- ifneq (${ERRATA_A53_843419},1)
- TF_LDFLAGS += -mno-fix-cortex-a53-843419
- endif
- endif
- TF_LDFLAGS += -nostdlib
- TF_LDFLAGS += $(subst --,-Xlinker --,$(TF_LDFLAGS_$(ARCH)))
-
-# LD = gcc-ld (ld) or llvm-ld (ld.lld) or other
-else
-# With ld.bfd version 2.39 and newer new warnings are added. Skip those since we
-# are not loaded by a elf loader.
- TF_LDFLAGS += $(call ld_option, --no-warn-rwx-segments)
- TF_LDFLAGS += -O1
- TF_LDFLAGS += --gc-sections
-
- TF_LDFLAGS += -z common-page-size=4096 # Configure page size constants
- TF_LDFLAGS += -z max-page-size=4096
- TF_LDFLAGS += --build-id=none
-
-# ld.lld doesn't recognize the errata flags,
-# therefore don't add those in that case.
-# ld.lld reports section type mismatch warnings,
-# therefore don't add --fatal-warnings to it.
- ifneq ($($(ARCH)-ld-id),llvm-lld)
- TF_LDFLAGS += $(TF_LDFLAGS_$(ARCH)) --fatal-warnings
- endif
-
-endif #(LD = armlink)
-
################################################################################
# Setup ARCH_MAJOR/MINOR before parsing arch_features.
################################################################################
@@ -408,10 +203,6 @@
${PLAT_INCLUDES} \
${SPD_INCLUDES}
-DTC_FLAGS += -I dts -O dtb
-DTC_CPPFLAGS += -P -nostdinc $(INCLUDES) -Ifdts -undef \
- -x assembler-with-cpp $(DEFINES)
-
include common/backtrace/backtrace.mk
################################################################################
@@ -441,22 +232,6 @@
CTX_INCLUDE_EL2_REGS := 1
endif
- ifeq ($(findstring optee_sp,$(ARM_SPMC_MANIFEST_DTS)),optee_sp)
- DTC_CPPFLAGS += -DOPTEE_SP_FW_CONFIG
- endif
-
- ifeq ($(findstring trusty_sp,$(ARM_SPMC_MANIFEST_DTS)),trusty_sp)
- DTC_CPPFLAGS += -DTRUSTY_SP_FW_CONFIG
- endif
-
- ifeq ($(TS_SP_FW_CONFIG),1)
- DTC_CPPFLAGS += -DTS_SP_FW_CONFIG
- endif
-
- ifneq ($(ARM_BL2_SP_LIST_DTS),)
- DTC_CPPFLAGS += -DARM_BL2_SP_LIST_DTS=$(ARM_BL2_SP_LIST_DTS)
- endif
-
ifneq ($(SP_LAYOUT_FILE),)
BL2_ENABLE_SP_LOAD := 1
endif
@@ -535,9 +310,6 @@
ifneq ($(ENABLE_PAUTH),0)
CTX_INCLUDE_PAUTH_REGS := ${ENABLE_PAUTH}
endif
-ifneq (${BP_OPTION},none)
- TF_CFLAGS_aarch64 += -mbranch-protection=${BP_OPTION}
-endif #(BP_OPTION)
# Pointer Authentication sources
ifneq (${ENABLE_PAUTH},0)
@@ -545,42 +317,22 @@
# Pauth support. As it's not secure, it must be reimplemented for real platforms
BL_COMMON_SOURCES += lib/extensions/pauth/pauth.c
endif
-
-####################################################
-# Enable required options for Memory Stack Tagging.
-####################################################
-
-# Currently, these options are enabled only for clang and armclang compiler.
-ifeq (${SUPPORT_STACK_MEMTAG},yes)
- ifdef mem_tag_arch_support
- # Check for armclang and clang compilers
- ifneq ($(filter %-clang,$($(ARCH)-cc-id)),)
- # Add "memtag" architecture feature modifier if not specified
- ifeq ( ,$(findstring memtag,$(arch-features)))
- arch-features := $(arch-features)+memtag
- endif # memtag
- ifeq ($($(ARCH)-cc-id),arm-clang)
- TF_CFLAGS += -mmemtag-stack
- else ifeq ($($(ARCH)-cc-id),llvm-clang)
- TF_CFLAGS += -fsanitize=memtag
- endif # armclang
- endif
- else
- $(error "Error: stack memory tagging is not supported for \
- architecture ${ARCH},armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a")
- endif #(mem_tag_arch_support)
-endif #(SUPPORT_STACK_MEMTAG)
+#
+ifneq (${ENABLE_FEAT_PAUTH_LR},0)
+# Currently, FEAT_PAUTH_LR is only supported by arm/clang compilers
+# TODO implement for GCC when support is added
+ifeq ($($(ARCH)-cc-id),arm-clang)
+ arch-features := $(arch-features)+pauth-lr
+else
+ $(error Error: ENABLE_FEAT_PAUTH_LR not supported for GCC compiler)
+endif
+endif
################################################################################
# RME dependent flags configuration, Enable optional features for RME.
################################################################################
# FEAT_RME
ifeq (${ENABLE_RME},1)
- # RME requires AARCH64
- ifneq (${ARCH},aarch64)
- $(error ENABLE_RME requires AArch64)
- endif
-
# RME requires el2 context to be saved for now.
CTX_INCLUDE_EL2_REGS := 1
CTX_INCLUDE_AARCH32_REGS := 0
@@ -598,47 +350,10 @@
# Include rmmd Makefile if RME is enabled
################################################################################
ifneq (${ENABLE_RME},0)
- ifneq (${ARCH},aarch64)
- $(error ENABLE_RME requires AArch64)
- endif
- ifeq ($(SPMC_AT_EL3),1)
- $(error SPMC_AT_EL3 and ENABLE_RME cannot both be enabled.)
- endif
-
- ifneq (${SPD}, none)
- ifneq (${SPD}, spmd)
- $(error ENABLE_RME is incompatible with SPD=${SPD}. Use SPD=spmd)
- endif
- endif
include services/std_svc/rmmd/rmmd.mk
$(warning "RME is an experimental feature")
endif
-ifeq (${CTX_INCLUDE_EL2_REGS}, 1)
- ifeq (${SPD},none)
- ifeq (${ENABLE_RME},0)
- $(error CTX_INCLUDE_EL2_REGS is available only when SPD \
- or RME is enabled)
- endif
- endif
-endif
-
-################################################################################
-# Verify FEAT_RME, FEAT_SCTLR2 and FEAT_TCR2 are enabled if FEAT_MEC is enabled.
-################################################################################
-
-ifneq (${ENABLE_FEAT_MEC},0)
- ifeq (${ENABLE_RME},0)
- $(error FEAT_RME must be enabled when FEAT_MEC is enabled.)
- endif
- ifeq (${ENABLE_FEAT_TCR2},0)
- $(error FEAT_TCR2 must be enabled when FEAT_MEC is enabled.)
- endif
- ifeq (${ENABLE_FEAT_SCTLR2},0)
- $(error FEAT_SCTLR2 must be enabled when FEAT_MEC is enabled.)
- endif
-endif
-
################################################################################
# Make 128-Bit sysreg read/writes availabe when FEAT_D128 is enabled.
################################################################################
@@ -646,15 +361,6 @@
BL_COMMON_SOURCES += lib/extensions/sysreg128/sysreg128.S
endif
-################################################################################
-# Platform specific Makefile might provide us ARCH_MAJOR/MINOR use that to come
-# up with appropriate march values for compiler.
-################################################################################
-include ${MAKE_HELPERS_DIRECTORY}march.mk
-
-TF_CFLAGS += $(march-directive)
-ASFLAGS += $(march-directive)
-
# This internal flag is common option which is set to 1 for scenarios
# when the BL2 is running in EL3 level. This occurs in two scenarios -
# 4 world system running BL2 at EL3 and two world system without BL1 running
@@ -680,60 +386,6 @@
FFH_SUPPORT := 0
endif
-ifeq (${ARM_ARCH_MAJOR},7)
-include make_helpers/armv7-a-cpus.mk
-endif
-
-PIE_FOUND := $(findstring --enable-default-pie,${GCC_V_OUTPUT})
-ifneq ($(PIE_FOUND),)
- TF_CFLAGS += -fno-PIE
-ifeq ($($(ARCH)-ld-id),gnu-gcc)
- TF_LDFLAGS += -no-pie
-endif
-endif #(PIE_FOUND)
-
-ifeq ($($(ARCH)-ld-id),gnu-gcc)
- PIE_LDFLAGS += -Wl,-pie -Wl,--no-dynamic-linker
-else
- PIE_LDFLAGS += -pie --no-dynamic-linker
-endif
-
-ifeq ($(ENABLE_PIE),1)
- ifeq ($(RESET_TO_BL2),1)
- ifneq ($(BL2_IN_XIP_MEM),1)
- BL2_CPPFLAGS += -fpie
- BL2_CFLAGS += -fpie
- BL2_LDFLAGS += $(PIE_LDFLAGS)
- endif #(BL2_IN_XIP_MEM)
- endif #(RESET_TO_BL2)
- BL31_CPPFLAGS += -fpie
- BL31_CFLAGS += -fpie
- BL31_LDFLAGS += $(PIE_LDFLAGS)
-
- BL32_CPPFLAGS += -fpie
- BL32_CFLAGS += -fpie
- BL32_LDFLAGS += $(PIE_LDFLAGS)
-endif #(ENABLE_PIE)
-
-BL1_CPPFLAGS += -DREPORT_ERRATA=${DEBUG}
-BL31_CPPFLAGS += -DREPORT_ERRATA=${DEBUG}
-BL32_CPPFLAGS += -DREPORT_ERRATA=${DEBUG}
-
-BL1_CPPFLAGS += -DIMAGE_AT_EL3
-ifeq ($(RESET_TO_BL2),1)
- BL2_CPPFLAGS += -DIMAGE_AT_EL3
-else
- BL2_CPPFLAGS += -DIMAGE_AT_EL1
-endif #(RESET_TO_BL2)
-
-ifeq (${ARCH},aarch64)
- BL2U_CPPFLAGS += -DIMAGE_AT_EL1
- BL31_CPPFLAGS += -DIMAGE_AT_EL3
- BL32_CPPFLAGS += -DIMAGE_AT_EL1
-else
- BL32_CPPFLAGS += -DIMAGE_AT_EL3
-endif
-
# Include the CPU specific operations makefile, which provides default
# values for all CPU errata workarounds and CPU specific optimisations.
# This can be overridden by the platform.
@@ -771,58 +423,7 @@
################################################################################
# Check incompatible options and dependencies
################################################################################
-
-# Handle all invalid build configurations with SPMD usage.
-ifeq (${ENABLE_SPMD_LP}, 1)
-ifneq (${SPD},spmd)
- $(error Error: ENABLE_SPMD_LP requires SPD=spmd.)
-endif
-ifeq ($(SPMC_AT_EL3),1)
- $(error SPMC at EL3 not supported when enabling SPMD Logical partitions.)
-endif
-endif
-
-ifneq (${SPD},none)
-ifeq (${ARCH},aarch32)
- $(error "Error: SPD is incompatible with AArch32.")
-endif
-ifdef EL3_PAYLOAD_BASE
- $(warning "SPD and EL3_PAYLOAD_BASE are incompatible build options.")
- $(warning "The SPD and its BL32 companion will be present but ignored.")
-endif
-ifeq (${SPD},spmd)
-ifeq ($(SPMD_SPM_AT_SEL2),1)
- ifeq ($(SPMC_AT_EL3),1)
- $(error SPM cannot be enabled in both S-EL2 and EL3.)
- endif
- ifeq ($(CTX_INCLUDE_SVE_REGS),1)
- $(error SVE context management not needed with Hafnium SPMC.)
- endif
-endif
-
-ifeq ($(SPMC_AT_EL3_SEL0_SP),1)
- ifneq ($(SPMC_AT_EL3),1)
- $(error SEL0 SP cannot be enabled without SPMC at EL3)
- endif
-endif
-endif #(SPD=spmd)
-endif #(SPD!=none)
-
-# USE_DEBUGFS experimental feature recommended only in debug builds
-ifeq (${USE_DEBUGFS},1)
- ifeq (${DEBUG},1)
- $(warning DEBUGFS experimental feature is enabled.)
- else
- $(warning DEBUGFS experimental, recommended in DEBUG builds ONLY)
- endif
-endif #(USE_DEBUGFS)
-
-# USE_SPINLOCK_CAS requires AArch64 build
-ifeq (${USE_SPINLOCK_CAS},1)
- ifneq (${ARCH},aarch64)
- $(error USE_SPINLOCK_CAS requires AArch64)
- endif
-endif #(USE_SPINLOCK_CAS)
+include ${MAKE_HELPERS_DIRECTORY}constraints.mk
# The cert_create tool cannot generate certificates individually, so we use the
# target 'certificates' to create them all
@@ -839,65 +440,6 @@
FWU_FIP_DEPS += enctool
endif #(DECRYPTION_SUPPORT)
-ifdef EL3_PAYLOAD_BASE
- ifdef PRELOADED_BL33_BASE
- $(warning "PRELOADED_BL33_BASE and EL3_PAYLOAD_BASE are \
- incompatible build options. EL3_PAYLOAD_BASE has priority.")
- endif
- ifneq (${GENERATE_COT},0)
- $(error "GENERATE_COT and EL3_PAYLOAD_BASE are incompatible \
- build options.")
- endif
- ifneq (${TRUSTED_BOARD_BOOT},0)
- $(error "TRUSTED_BOARD_BOOT and EL3_PAYLOAD_BASE are \
- incompatible \ build options.")
- endif
-endif #(EL3_PAYLOAD_BASE)
-
-ifeq (${NEED_BL33},yes)
- ifdef EL3_PAYLOAD_BASE
- $(warning "BL33 image is not needed when option \
- BL33_PAYLOAD_BASE is used and won't be added to the FIP file.")
- endif
- ifdef PRELOADED_BL33_BASE
- $(warning "BL33 image is not needed when option \
- PRELOADED_BL33_BASE is used and won't be added to the FIP file.")
- endif
-endif #(NEED_BL33)
-
-# When building for systems with hardware-assisted coherency, there's no need to
-# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
-ifeq ($(HW_ASSISTED_COHERENCY)-$(USE_COHERENT_MEM),1-1)
- $(error USE_COHERENT_MEM cannot be enabled with HW_ASSISTED_COHERENCY)
-endif
-
-#For now, BL2_IN_XIP_MEM is only supported when RESET_TO_BL2 is 1.
-ifeq ($(RESET_TO_BL2)-$(BL2_IN_XIP_MEM),0-1)
- $(error "BL2_IN_XIP_MEM is only supported when RESET_TO_BL2 is enabled")
-endif
-
-# RAS_EXTENSION is deprecated, provide alternate build options
-ifeq ($(RAS_EXTENSION),1)
- $(error "RAS_EXTENSION is now deprecated, please use ENABLE_FEAT_RAS \
- and HANDLE_EA_EL3_FIRST_NS instead")
-endif
-
-
-# When FAULT_INJECTION_SUPPORT is used, require that FEAT_RAS is enabled
-ifeq ($(FAULT_INJECTION_SUPPORT),1)
- ifeq ($(ENABLE_FEAT_RAS),0)
- $(error For FAULT_INJECTION_SUPPORT, ENABLE_FEAT_RAS must not be 0)
- endif
-endif #(FAULT_INJECTION_SUPPORT)
-
-# DYN_DISABLE_AUTH can be set only when TRUSTED_BOARD_BOOT=1
-ifeq ($(DYN_DISABLE_AUTH), 1)
- ifeq (${TRUSTED_BOARD_BOOT}, 0)
- $(error "TRUSTED_BOARD_BOOT must be enabled for DYN_DISABLE_AUTH \
- to be set.")
- endif
-endif #(DYN_DISABLE_AUTH)
-
ifeq ($(MEASURED_BOOT)-$(TRUSTED_BOARD_BOOT),1-1)
# Support authentication verification and hash calculation
CRYPTO_SUPPORT := 3
@@ -918,224 +460,6 @@
CRYPTO_LIB := $(BUILD_PLAT)/lib/libmbedtls.a
endif
-# SDEI_IN_FCONF is only supported when SDEI_SUPPORT is enabled.
-ifeq ($(SDEI_SUPPORT)-$(SDEI_IN_FCONF),0-1)
- $(error "SDEI_IN_FCONF is only supported when SDEI_SUPPORT is enabled")
-endif
-
-# If pointer authentication is used in the firmware, make sure that all the
-# registers associated to it are also saved and restored.
-# Not doing it would leak the value of the keys used by EL3 to EL1 and S-EL1.
-ifneq ($(ENABLE_PAUTH),0)
- ifeq ($(CTX_INCLUDE_PAUTH_REGS),0)
- $(error Pointer Authentication requires CTX_INCLUDE_PAUTH_REGS to be enabled)
- endif
-endif #(ENABLE_PAUTH)
-
-ifneq ($(CTX_INCLUDE_PAUTH_REGS),0)
- ifneq (${ARCH},aarch64)
- $(error CTX_INCLUDE_PAUTH_REGS requires AArch64)
- endif
-endif #(CTX_INCLUDE_PAUTH_REGS)
-
-# Check ENABLE_FEAT_PAUTH_LR
-ifneq (${ENABLE_FEAT_PAUTH_LR},0)
-
-# Make sure PAUTH is enabled
-ifeq (${ENABLE_PAUTH},0)
- $(error Error: PAUTH_LR cannot be used without PAUTH (see BRANCH_PROTECTION))
-endif
-
-# Make sure SCTLR2 is enabled
-ifeq (${ENABLE_FEAT_SCTLR2},0)
- $(error Error: PAUTH_LR cannot be used without ENABLE_FEAT_SCTLR2)
-endif
-
-# FEAT_PAUTH_LR is only supported in aarch64 state
-ifneq (${ARCH},aarch64)
- $(error ENABLE_FEAT_PAUTH_LR requires AArch64)
-endif
-
-# Currently, FEAT_PAUTH_LR is only supported by arm/clang compilers
-# TODO implement for GCC when support is added
-ifeq ($($(ARCH)-cc-id),arm-clang)
- arch-features := $(arch-features)+pauth-lr
-else
- $(error Error: ENABLE_FEAT_PAUTH_LR not supported for GCC compiler)
-endif
-
-endif # ${ENABLE_FEAT_PAUTH_LR}
-
-ifeq ($(FEATURE_DETECTION),1)
- $(info FEATURE_DETECTION is an experimental feature)
-endif #(FEATURE_DETECTION)
-
-ifneq ($(ENABLE_SME2_FOR_NS), 0)
- ifeq (${ENABLE_SME_FOR_NS}, 0)
- $(warning "ENABLE_SME2_FOR_NS requires ENABLE_SME_FOR_NS also \
- to be set")
- $(warning "Forced ENABLE_SME_FOR_NS=1")
- override ENABLE_SME_FOR_NS := 1
- endif
-endif #(ENABLE_SME2_FOR_NS)
-
-ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1)
- ifeq (${ALLOW_RO_XLAT_TABLES}, 1)
- $(error "ALLOW_RO_XLAT_TABLES requires translation tables \
- library v2")
- endif
-endif #(ARM_XLAT_TABLES_LIB_V1)
-
-ifneq (${DECRYPTION_SUPPORT},none)
- ifeq (${TRUSTED_BOARD_BOOT}, 0)
- $(error TRUSTED_BOARD_BOOT must be enabled for DECRYPTION_SUPPORT \
- to be set)
- endif
-endif #(DECRYPTION_SUPPORT)
-
-# Ensure that no Aarch64-only features are enabled in Aarch32 build
-ifeq (${ARCH},aarch32)
-
- # SME/SVE only supported on AArch64
- ifneq (${ENABLE_SME_FOR_NS},0)
- $(error "ENABLE_SME_FOR_NS cannot be used with ARCH=aarch32")
- endif
-
- ifeq (${ENABLE_SVE_FOR_NS},1)
- # Warning instead of error due to CI dependency on this
- $(error "ENABLE_SVE_FOR_NS cannot be used with ARCH=aarch32")
- endif
-
- # BRBE is not supported in AArch32
- ifeq (${ENABLE_BRBE_FOR_NS},1)
- $(error "ENABLE_BRBE_FOR_NS cannot be used with ARCH=aarch32")
- endif
-
- # FEAT_RNG_TRAP is not supported in AArch32
- ifneq (${ENABLE_FEAT_RNG_TRAP},0)
- $(error "ENABLE_FEAT_RNG_TRAP cannot be used with ARCH=aarch32")
- endif
-
- ifneq (${ENABLE_FEAT_FPMR},0)
- $(error "ENABLE_FEAT_FPMR cannot be used with ARCH=aarch32")
- endif
-
- ifeq (${ARCH_FEATURE_AVAILABILITY},1)
- $(error "ARCH_FEATURE_AVAILABILITY cannot be used with ARCH=aarch32")
- endif
- # FEAT_MOPS is only supported on AArch64
- ifneq (${ENABLE_FEAT_MOPS},0)
- $(error "ENABLE_FEAT_MOPS cannot be used with ARCH=aarch32")
- endif
-endif #(ARCH=aarch32)
-
-ifneq (${ENABLE_FEAT_FPMR},0)
- ifeq (${ENABLE_FEAT_FGT},0)
- $(error "ENABLE_FEAT_FPMR requires ENABLE_FEAT_FGT")
- endif
- ifeq (${ENABLE_FEAT_HCX},0)
- $(error "ENABLE_FEAT_FPMR requires ENABLE_FEAT_HCX")
- endif
-endif #(ENABLE_FEAT_FPMR)
-
-ifneq (${ENABLE_SME_FOR_NS},0)
- ifeq (${ENABLE_SVE_FOR_NS},0)
- $(error "ENABLE_SME_FOR_NS requires ENABLE_SVE_FOR_NS")
- endif
-endif #(ENABLE_SME_FOR_NS)
-
-# Secure SME/SVE requires the non-secure component as well
-ifeq (${ENABLE_SME_FOR_SWD},1)
- ifeq (${ENABLE_SME_FOR_NS},0)
- $(error "ENABLE_SME_FOR_SWD requires ENABLE_SME_FOR_NS")
- endif
- ifeq (${ENABLE_SVE_FOR_SWD},0)
- $(error "ENABLE_SME_FOR_SWD requires ENABLE_SVE_FOR_SWD")
- endif
-endif #(ENABLE_SME_FOR_SWD)
-
-# Enabling SVE for SWD requires enabling SVE for NWD due to ENABLE_FEAT
-# mechanism.
-ifeq (${ENABLE_SVE_FOR_SWD},1)
- ifeq (${ENABLE_SVE_FOR_NS},0)
- $(error "ENABLE_SVE_FOR_SWD requires ENABLE_SVE_FOR_NS")
- endif
-endif
-
-# Enabling FEAT_MOPS requires access to hcrx_el2 registers which is
-# available only when FEAT_HCX is enabled.
-ifneq (${ENABLE_FEAT_MOPS},0)
- ifeq (${ENABLE_FEAT_HCX},0)
- $(error "ENABLE_FEAT_MOPS requires ENABLE_FEAT_HCX")
- endif
-endif
-
-# Enabling SVE for both the worlds typically requires the context
-# management of SVE registers. The only exception being SPMC at S-EL2.
-ifeq (${ENABLE_SVE_FOR_SWD}, 1)
- ifneq (${ENABLE_SVE_FOR_NS}, 0)
- ifeq (${CTX_INCLUDE_SVE_REGS}-$(SPMD_SPM_AT_SEL2),0-0)
- $(warning "ENABLE_SVE_FOR_SWD and ENABLE_SVE_FOR_NS together require CTX_INCLUDE_SVE_REGS")
- endif
- endif
-endif
-
-# Enabling SVE in either world while enabling CTX_INCLUDE_FPREGS requires
-# CTX_INCLUDE_SVE_REGS to be enabled due to architectural dependency between FP
-# and SVE registers.
-ifeq (${CTX_INCLUDE_FPREGS}, 1)
- ifneq (${ENABLE_SVE_FOR_NS},0)
- ifeq (${CTX_INCLUDE_SVE_REGS},0)
- # Warning instead of error due to CI dependency on this
- $(warning "CTX_INCLUDE_FPREGS and ENABLE_SVE_FOR_NS together require CTX_INCLUDE_SVE_REGS")
- $(warning "Forced ENABLE_SVE_FOR_NS=0")
- override ENABLE_SVE_FOR_NS := 0
- endif
- endif
-endif #(CTX_INCLUDE_FPREGS)
-
-# SVE context management is only required if secure world has access to SVE/FP
-# functionality.
-ifeq (${CTX_INCLUDE_SVE_REGS},1)
- ifeq (${ENABLE_SVE_FOR_SWD},0)
- $(error "CTX_INCLUDE_SVE_REGS requires ENABLE_SVE_FOR_SWD to also be enabled")
- endif
-endif
-
-# SME cannot be used with CTX_INCLUDE_FPREGS since SPM does its own context
-# management including FPU registers.
-ifeq (${CTX_INCLUDE_FPREGS},1)
- ifneq (${ENABLE_SME_FOR_NS},0)
- $(error "ENABLE_SME_FOR_NS cannot be used with CTX_INCLUDE_FPREGS")
- endif
-endif #(CTX_INCLUDE_FPREGS)
-
-ifeq ($(DRTM_SUPPORT),1)
- $(info DRTM_SUPPORT is an experimental feature)
-endif
-
-ifeq (${HOB_LIST},1)
- $(warning HOB_LIST is an experimental feature)
-endif
-
-ifeq (${TRANSFER_LIST},1)
- $(info TRANSFER_LIST is an experimental feature)
-endif
-
-ifeq (${ENABLE_RME},1)
- ifneq (${SEPARATE_CODE_AND_RODATA},1)
- $(error `ENABLE_RME=1` requires `SEPARATE_CODE_AND_RODATA=1`)
- endif
-endif
-
-ifeq ($(PSA_CRYPTO),1)
- $(info PSA_CRYPTO is an experimental feature)
-endif
-
-ifeq ($(DICE_PROTECTION_ENVIRONMENT),1)
- $(info DICE_PROTECTION_ENVIRONMENT is an experimental feature)
-endif
-
################################################################################
# Process platform overrideable behaviour
################################################################################
@@ -1263,6 +587,7 @@
ENABLE_RUNTIME_INSTRUMENTATION \
ENABLE_SME_FOR_SWD \
ENABLE_SVE_FOR_SWD \
+ ENABLE_FEAT_GCIE \
ENABLE_FEAT_RAS \
FFH_SUPPORT \
ERROR_DEPRECATED \
@@ -1322,7 +647,6 @@
PSA_FWU_SUPPORT \
PSA_FWU_METADATA_FW_STORE_DESC \
ENABLE_MPMM \
- FEAT_PABANDON \
FEATURE_DETECTION \
TRNG_SUPPORT \
ENABLE_ERRATA_ALL \
@@ -1336,6 +660,7 @@
EARLY_CONSOLE \
PRESERVE_DSU_PMU_REGS \
HOB_LIST \
+ LFA_SUPPORT \
)))
# Numeric_Flags
@@ -1362,6 +687,7 @@
ENABLE_FEAT_ECV \
ENABLE_FEAT_FGT \
ENABLE_FEAT_FGT2 \
+ ENABLE_FEAT_FGWTE3 \
ENABLE_FEAT_FPMR \
ENABLE_FEAT_HCX \
ENABLE_FEAT_LS64_ACCDATA \
@@ -1398,6 +724,7 @@
ENABLE_FEAT_TWED \
SVE_VECTOR_LEN \
IMPDEF_SYSREG_TRAP \
+ W \
)))
ifdef KEY_SIZE
@@ -1429,6 +756,7 @@
EL3_EXCEPTION_HANDLING \
CTX_INCLUDE_EL2_REGS \
CTX_INCLUDE_NEVE_REGS \
+ DEBUG \
DECRYPTION_SUPPORT_${DECRYPTION_SUPPORT} \
DISABLE_MTPMU \
ENABLE_FEAT_AMU \
@@ -1527,9 +855,9 @@
ENABLE_TRF_FOR_NS \
ENABLE_FEAT_HCX \
ENABLE_MPMM \
- FEAT_PABANDON \
ENABLE_FEAT_FGT \
ENABLE_FEAT_FGT2 \
+ ENABLE_FEAT_FGWTE3 \
ENABLE_FEAT_FPMR \
ENABLE_FEAT_ECV \
ENABLE_FEAT_AMUv1p1 \
@@ -1550,6 +878,7 @@
ENABLE_FEAT_D128 \
ENABLE_FEAT_GCS \
ENABLE_FEAT_MOPS \
+ ENABLE_FEAT_GCIE \
ENABLE_FEAT_MTE2 \
FEATURE_DETECTION \
TWED_DELAY \
@@ -1565,6 +894,7 @@
EARLY_CONSOLE \
PRESERVE_DSU_PMU_REGS \
HOB_LIST \
+ LFA_SUPPORT \
)))
ifeq (${PLATFORM_REPORT_CTX_MEM_USE}, 1)
@@ -1613,6 +943,11 @@
endif #(SPD)
################################################################################
+# Configure the flags for the specified compiler and linker
+################################################################################
+include ${MAKE_HELPERS_DIRECTORY}cflags.mk
+
+################################################################################
# Build targets
################################################################################
@@ -1623,15 +958,6 @@
msg_start:
$(s)echo "Building ${PLAT}"
-ifeq (${ERROR_DEPRECATED},0)
-# Check if deprecated declarations and cpp warnings should be treated as error or not.
-ifneq ($(filter %-clang,$($(ARCH)-cc-id)),)
- CPPFLAGS += -Wno-error=deprecated-declarations
-else
- CPPFLAGS += -Wno-error=deprecated-declarations -Wno-error=cpp
-endif
-endif #(!ERROR_DEPRECATED)
-
$(eval $(call MAKE_LIB,c))
# Expand build macros for the different images
@@ -1751,18 +1077,22 @@
clean:
$(s)echo " CLEAN"
$(q)rm -rf $(BUILD_PLAT)
- $(q)${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
- $(q)${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean
- $(q)${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} clean
+ $(q)${MAKE} PLAT=${PLAT} BUILD_PLAT=${BUILD_PLAT} --no-print-directory -C ${FIPTOOLPATH} clean
+ $(q)rm -rf ${FIPTOOLPATH}/fiptool
+ $(q)${MAKE} PLAT=${PLAT} BUILD_PLAT=${BUILD_PLAT} --no-print-directory -C ${CRTTOOLPATH} clean
+ $(q)rm -rf ${CRTTOOLPATH}/cert_create
+ $(q)${MAKE} PLAT=${PLAT} BUILD_PLAT=${BUILD_PLAT} --no-print-directory -C ${ENCTOOLPATH} clean
$(q)${MAKE} --no-print-directory -C ${ROMLIBPATH} clean
realclean distclean:
$(s)echo " REALCLEAN"
$(q)rm -rf $(BUILD_BASE)
$(q)rm -rf $(CURDIR)/cscope.*
- $(q)${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
- $(q)${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} realclean
- $(q)${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} realclean
+ $(q)${MAKE} PLAT=${PLAT} BUILD_PLAT=${BUILD_PLAT} --no-print-directory -C ${FIPTOOLPATH} clean
+ $(q)rm -rf ${FIPTOOLPATH}/fiptool
+ $(q)${MAKE} PLAT=${PLAT} BUILD_PLAT=${BUILD_PLAT} --no-print-directory -C ${CRTTOOLPATH} clean
+ $(q)rm -rf ${CRTTOOLPATH}/cert_create
+ $(q)${MAKE} PLAT=${PLAT} BUILD_PLAT=${BUILD_PLAT} --no-print-directory -C ${ENCTOOLPATH} clean
$(q)${MAKE} --no-print-directory -C ${ROMLIBPATH} clean
checkcodebase: locate-checkpatch
@@ -1801,13 +1131,14 @@
certtool: ${CRTTOOL}
${CRTTOOL}: FORCE
- $(q)${MAKE} PLAT=${PLAT} USE_TBBR_DEFS=${USE_TBBR_DEFS} COT=${COT} OPENSSL_DIR=${OPENSSL_DIR} CRTTOOL=${CRTTOOL} DEBUG=${DEBUG} --no-print-directory -C ${CRTTOOLPATH} all
+ $(q)${MAKE} PLAT=${PLAT} BUILD_PLAT=$(abspath ${BUILD_PLAT}) USE_TBBR_DEFS=${USE_TBBR_DEFS} COT=${COT} OPENSSL_DIR=${OPENSSL_DIR} DEBUG=${DEBUG} --no-print-directory -C ${CRTTOOLPATH} all
+ $(q)ln -sf ${CRTTOOL} ${CRTTOOLPATH}/cert_create
$(s)echo
$(s)echo "Built $@ successfully"
$(s)echo
ifneq (${GENERATE_COT},0)
-certificates: ${CRT_DEPS} ${CRTTOOL}
+certificates: ${CRT_DEPS} ${CRTTOOL} ${DTBS}
$(q)${CRTTOOL} ${CRT_ARGS}
$(s)echo
$(s)echo "Built $@ successfully"
@@ -1844,15 +1175,17 @@
fip: ${BUILD_PLAT}/${FIP_NAME}
fwu_fip: ${BUILD_PLAT}/${FWU_FIP_NAME}
+# symlink for compatibility before tools were in the build directory
${FIPTOOL}: FORCE
- $(q)${MAKE} PLAT=${PLAT} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} OPENSSL_DIR=${OPENSSL_DIR} DEBUG=${DEBUG} --no-print-directory -C ${FIPTOOLPATH} all
+ $(q)${MAKE} PLAT=${PLAT} BUILD_PLAT=$(abspath ${BUILD_PLAT}) CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" OPENSSL_DIR=${OPENSSL_DIR} DEBUG=${DEBUG} --no-print-directory -C ${FIPTOOLPATH} all
+ $(q)ln -sf ${FIPTOOL} ${FIPTOOLPATH}/fiptool
$(BUILD_PLAT)/romlib/romlib.bin $(BUILD_PLAT)/lib/libwrappers.a $&: $(BUILD_PLAT)/lib/libfdt.a $(BUILD_PLAT)/lib/libc.a $(CRYPTO_LIB)
$(q)${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} ENABLE_BTI=${ENABLE_BTI} CRYPTO_SUPPORT=${CRYPTO_SUPPORT} ARM_ARCH_MINOR=${ARM_ARCH_MINOR} INCLUDES=$(call escape-shell,$(INCLUDES)) DEFINES=$(call escape-shell,$(DEFINES)) --no-print-directory -C ${ROMLIBPATH} all
memmap: all
$(if $(host-poetry),$(q)poetry -q install --no-root)
- $(q)$(if $(host-poetry),poetry run )memory -sr ${BUILD_PLAT}
+ $(q)$(if $(host-poetry),poetry run )memory symbols --root ${BUILD_PLAT}
tl: ${BUILD_PLAT}/tl.bin
${BUILD_PLAT}/tl.bin: ${HW_CONFIG}
@@ -1861,12 +1194,13 @@
doc:
$(s)echo " BUILD DOCUMENTATION"
- $(q)${MAKE} --no-print-directory -C ${DOCS_PATH} html
+ $(if $(host-poetry),$(q)poetry -q install --with docs --no-root)
+ $(q)$(if $(host-poetry),poetry run )${MAKE} --no-print-directory -C ${DOCS_PATH} html
enctool: ${ENCTOOL}
${ENCTOOL}: FORCE
- $(q)${MAKE} PLAT=${PLAT} BUILD_INFO=0 OPENSSL_DIR=${OPENSSL_DIR} ENCTOOL=${ENCTOOL} DEBUG=${DEBUG} --no-print-directory -C ${ENCTOOLPATH} all
+ $(q)${MAKE} PLAT=${PLAT} BUILD_PLAT=$(abspath ${BUILD_PLAT}) BUILD_INFO=0 OPENSSL_DIR=${OPENSSL_DIR} DEBUG=${DEBUG} --no-print-directory -C ${ENCTOOLPATH} all
$(s)echo
$(s)echo "Built $@ successfully"
$(s)echo
diff --git a/bl1/aarch32/bl1_context_mgmt.c b/bl1/aarch32/bl1_context_mgmt.c
index 85d35a7..1d7770c 100644
--- a/bl1/aarch32/bl1_context_mgmt.c
+++ b/bl1/aarch32/bl1_context_mgmt.c
@@ -47,7 +47,7 @@
}
/* Following functions are used for CPU context handling */
-void *cm_get_context(uint32_t security_state)
+void *cm_get_context(size_t security_state)
{
assert(sec_state_is_valid(security_state));
return &bl1_cpu_context[security_state];
diff --git a/bl1/aarch64/bl1_context_mgmt.c b/bl1/aarch64/bl1_context_mgmt.c
index b9a7e5b..98d2ac1 100644
--- a/bl1/aarch64/bl1_context_mgmt.c
+++ b/bl1/aarch64/bl1_context_mgmt.c
@@ -19,7 +19,7 @@
entry_point_info_t *bl2_ep_info;
-void *cm_get_context(uint32_t security_state)
+void *cm_get_context(size_t security_state)
{
assert(sec_state_is_valid(security_state));
return bl1_cpu_context_ptr[security_state];
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index e390915..d267b11 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -164,6 +164,10 @@
${RMMD_SOURCES}
endif
+ifeq (${USE_DSU_DRIVER},1)
+BL31_SOURCES += drivers/arm/dsu/dsu.c
+endif
+
ifeq ($(FEATURE_DETECTION),1)
BL31_SOURCES += common/feat_detect.c
endif
@@ -177,6 +181,11 @@
${MBEDTLS_SOURCES}
endif
+ifeq (${LFA_SUPPORT},1)
+include services/std_svc/lfa/lfa.mk
+BL31_SOURCES += ${LFA_SOURCES}
+endif
+
ifeq ($(CROS_WIDEVINE_SMC),1)
BL31_SOURCES += services/oem/chromeos/widevine_smc_handlers.c
endif
@@ -200,11 +209,13 @@
CRASH_REPORTING \
EL3_EXCEPTION_HANDLING \
SDEI_SUPPORT \
+ USE_DSU_DRIVER \
)))
$(eval $(call add_defines,\
$(sort \
- CRASH_REPORTING \
- EL3_EXCEPTION_HANDLING \
- SDEI_SUPPORT \
+ CRASH_REPORTING \
+ EL3_EXCEPTION_HANDLING \
+ SDEI_SUPPORT \
+ USE_DSU_DRIVER \
)))
diff --git a/bl31/bl31_context_mgmt.c b/bl31/bl31_context_mgmt.c
index 34f69ad..1fe2ddb 100644
--- a/bl31/bl31_context_mgmt.c
+++ b/bl31/bl31_context_mgmt.c
@@ -17,7 +17,7 @@
* for the calling CPU that was set as the context for the specified security
* state. NULL is returned if no such structure has been specified.
******************************************************************************/
-void *cm_get_context(uint32_t security_state)
+void *cm_get_context(size_t security_state)
{
assert(sec_state_is_valid(security_state));
@@ -43,7 +43,7 @@
* specified.
******************************************************************************/
void *cm_get_context_by_index(unsigned int cpu_idx,
- unsigned int security_state)
+ size_t security_state)
{
assert(sec_state_is_valid(security_state));
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index a9f89fc..b8c915a 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -17,6 +17,7 @@
#include <common/debug.h>
#include <common/feat_detect.h>
#include <common/runtime_svc.h>
+#include <drivers/arm/dsu.h>
#include <drivers/arm/gic.h>
#include <drivers/console.h>
#include <lib/bootmarker_capture.h>
@@ -56,7 +57,7 @@
* Variable to indicate whether next image to execute after BL31 is BL33
* (non-secure & default) or BL32 (secure).
******************************************************************************/
-static uint32_t next_image_type = NON_SECURE;
+static uint32_t next_image_type = (uint32_t)NON_SECURE;
#ifdef SUPPORT_UNKNOWN_MPID
/*
@@ -96,6 +97,11 @@
void bl31_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
u_register_t arg3)
{
+#if FEATURE_DETECTION
+ /* Detect if features enabled during compilation are supported by PE. */
+ detect_arch_features(plat_my_core_pos());
+#endif /* FEATURE_DETECTION */
+
/* Enable early console if EARLY_CONSOLE flag is enabled */
plat_setup_early_console();
@@ -119,20 +125,17 @@
******************************************************************************/
void bl31_main(void)
{
- /* Init registers that never change for the lifetime of TF-A */
- cm_manage_extensions_el3(plat_my_core_pos());
+ unsigned int core_pos = plat_my_core_pos();
- /* Init per-world context registers for non-secure world */
- manage_extensions_nonsecure_per_world();
+ /* Init registers that never change for the lifetime of TF-A */
+ cm_manage_extensions_el3(core_pos);
+
+ /* Init per-world context registers */
+ cm_manage_extensions_per_world();
NOTICE("BL31: %s\n", build_version_string);
NOTICE("BL31: %s\n", build_message);
-#if FEATURE_DETECTION
- /* Detect if features enabled during compilation are supported by PE. */
- detect_arch_features();
-#endif /* FEATURE_DETECTION */
-
#if ENABLE_RUNTIME_INSTRUMENTATION
PMF_CAPTURE_TIMESTAMP(bl_svc, BL31_ENTRY, PMF_CACHE_MAINT);
#endif
@@ -146,13 +149,15 @@
/* Perform platform setup in BL31 */
bl31_platform_setup();
+#if USE_DSU_DRIVER
+ dsu_driver_init(&plat_dsu_data);
+#endif
+
#if USE_GIC_DRIVER
/*
* Initialize the GIC driver as well as per-cpu and global interfaces.
* Platform has had an opportunity to initialise specifics.
*/
- unsigned int core_pos = plat_my_core_pos();
-
gic_init(core_pos);
gic_pcpu_init(core_pos);
gic_cpuif_enable(core_pos);
diff --git a/bl31/interrupt_mgmt.c b/bl31/interrupt_mgmt.c
index 1a1cbc4..641d66a 100644
--- a/bl31/interrupt_mgmt.c
+++ b/bl31/interrupt_mgmt.c
@@ -78,7 +78,7 @@
* routing model (expressed through the IRQ and FIQ bits) for a security state
* which was stored through a call to 'set_routing_model()' earlier.
******************************************************************************/
-u_register_t get_scr_el3_from_routing_model(uint32_t security_state)
+u_register_t get_scr_el3_from_routing_model(size_t security_state)
{
u_register_t scr_el3;
diff --git a/bl32/sp_min/sp_min_main.c b/bl32/sp_min/sp_min_main.c
index 9add239..57d737d 100644
--- a/bl32/sp_min/sp_min_main.c
+++ b/bl32/sp_min/sp_min_main.c
@@ -67,7 +67,7 @@
* for the calling CPU that was set as the context for the specified security
* state. NULL is returned if no such structure has been specified.
******************************************************************************/
-void *cm_get_context(uint32_t security_state)
+void *cm_get_context(size_t security_state)
{
assert(security_state == NON_SECURE);
return sp_min_cpu_ctx_ptr[plat_my_core_pos()];
@@ -90,7 +90,7 @@
* specified.
******************************************************************************/
void *cm_get_context_by_index(unsigned int cpu_idx,
- unsigned int security_state)
+ size_t security_state)
{
assert(security_state == NON_SECURE);
return sp_min_cpu_ctx_ptr[cpu_idx];
diff --git a/changelog.yaml b/changelog.yaml
index e5d43d9..e0a4f42 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -621,6 +621,12 @@
scope: stm32mp2
subsections:
+ - title: STM32MP21
+ scope: stm32mp21
+
+ - title: STM32MP23
+ scope: stm32mp23
+
- title: STM32MP25
scope: stm32mp25
@@ -769,6 +775,9 @@
- title: ChromeOS
scope: cros
+ - title: Live Firmware Activation
+ scope: lfa
+
- title: Secure Payload Dispatcher
scope: spd
@@ -834,7 +843,7 @@
- title: ROMlib
scope: romlib
- - title: GPT
+ - title: Granule Protection Tables
scope: gpt
deprecated:
@@ -990,6 +999,9 @@
scope: gic
subsections:
+ - title: GICv5
+ scope: gicv5
+
- title: GICv3
scope: gicv3
@@ -1175,6 +1187,9 @@
- title: Clock
scope: nxp-clk
+ - title: uSDHC
+ scope: nxp-mmc
+
- title: Renesas
scope: renesas-drivers
@@ -1352,6 +1367,12 @@
scope: stm32mp2-fdts
subsections:
+ - title: STM32MP21
+ scope: stm32mp21-fdts
+
+ - title: STM32MP23
+ scope: stm32mp23-fdts
+
- title: STM32MP25
scope: stm32mp25-fdts
diff --git a/common/feat_detect.c b/common/feat_detect.c
index 2d80b42..5f70397 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -7,8 +7,9 @@
#include <arch_features.h>
#include <common/debug.h>
#include <common/feat_detect.h>
+#include <plat/common/platform.h>
-static bool tainted;
+static bool detection_done[PLATFORM_CORE_COUNT] = { false };
/*******************************************************************************
* This section lists the wrapper modules for each feature to evaluate the
@@ -45,29 +46,21 @@
* We force inlining here to let the compiler optimise away the whole check
* if the feature is disabled at build time (FEAT_STATE_DISABLED).
******************************************************************************/
-static inline void __attribute((__always_inline__))
+static inline bool __attribute((__always_inline__))
check_feature(int state, unsigned long field, const char *feat_name,
unsigned int min, unsigned int max)
{
if (state == FEAT_STATE_ALWAYS && field < min) {
ERROR("FEAT_%s not supported by the PE\n", feat_name);
- tainted = true;
+ return true;
}
if (state >= FEAT_STATE_ALWAYS && field > max) {
ERROR("FEAT_%s is version %ld, but is only known up to version %d\n",
feat_name, field, max);
- tainted = true;
+ return true;
}
-}
-/************************************************
- * Feature : FEAT_PAUTH (Pointer Authentication)
- ***********************************************/
-static void read_feat_pauth(void)
-{
-#if (ENABLE_PAUTH == FEAT_STATE_ALWAYS) || (CTX_INCLUDE_PAUTH_REGS == FEAT_STATE_ALWAYS)
- feat_detect_panic(is_feat_pauth_present(), "PAUTH");
-#endif
+ return false;
}
static unsigned int read_feat_rng_trap_id_field(void)
@@ -279,6 +272,11 @@
return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_D128_SHIFT,
ID_AA64MMFR3_EL1_D128_MASK);
}
+static unsigned int read_feat_gcie_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_GCIE_SHIFT,
+ ID_AA64PFR2_EL1_GCIE_MASK);
+}
static unsigned int read_feat_fpmr_id_field(void)
{
@@ -292,6 +290,12 @@
ID_AA64ISAR2_EL1_MOPS_MASK);
}
+static unsigned int read_feat_fgwte3_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr4_el1(), ID_AA64MMFR4_EL1_FGWTE3_SHIFT,
+ ID_AA64MMFR4_EL1_FGWTE3_MASK);
+}
+
/***********************************************************************************
* TF-A supports many Arm architectural features starting from arch version
* (8.0 till 8.7+). These features are mostly enabled through build flags. This
@@ -315,123 +319,151 @@
* { FEAT_STATE_DISABLED, FEAT_STATE_ALWAYS, FEAT_STATE_CHECK }, taking values
* { 0, 1, 2 }, respectively, as their naming.
**********************************************************************************/
-void detect_arch_features(void)
+void detect_arch_features(unsigned int core_pos)
{
- tainted = false;
+ /* No need to keep checking after the first time for each core. */
+ if (detection_done[core_pos]) {
+ return;
+ }
+
+ bool tainted = false;
/* v8.0 features */
- check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(), "SB", 1, 1);
- check_feature(ENABLE_FEAT_CSV2_2, read_feat_csv2_id_field(),
- "CSV2_2", 2, 3);
+ tainted |= check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(),
+ "SB", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_CSV2_2, read_feat_csv2_id_field(),
+ "CSV2_2", 2, 3);
/*
* Even though the PMUv3 is an OPTIONAL feature, it is always
* implemented and Arm prescribes so. So assume it will be there and do
* away with a flag for it. This is used to check minor PMUv3px
* revisions so that we catch them as they come along
*/
- check_feature(FEAT_STATE_ALWAYS, read_feat_pmuv3_id_field(),
- "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P9);
+ tainted |= check_feature(FEAT_STATE_ALWAYS, read_feat_pmuv3_id_field(),
+ "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P9);
/* v8.1 features */
- check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(), "PAN", 1, 3);
- check_feature(ENABLE_FEAT_VHE, read_feat_vhe_id_field(), "VHE", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(),
+ "PAN", 1, 3);
+ tainted |= check_feature(ENABLE_FEAT_VHE, read_feat_vhe_id_field(),
+ "VHE", 1, 1);
/* v8.2 features */
- check_feature(ENABLE_SVE_FOR_NS, read_feat_sve_id_field(),
- "SVE", 1, 1);
- check_feature(ENABLE_FEAT_RAS, read_feat_ras_id_field(), "RAS", 1, 2);
+ tainted |= check_feature(ENABLE_SVE_FOR_NS, read_feat_sve_id_field(),
+ "SVE", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_RAS, read_feat_ras_id_field(),
+ "RAS", 1, 2);
/* v8.3 features */
- /* TODO: Pauth yet to convert to tri-state feat detect logic */
- read_feat_pauth();
+ /* the PAuth fields are very complicated, no min/max is checked */
+ tainted |= check_feature(ENABLE_PAUTH, is_feat_pauth_present(),
+ "PAUTH", 1, 1);
/* v8.4 features */
- check_feature(ENABLE_FEAT_DIT, read_feat_dit_id_field(), "DIT", 1, 1);
- check_feature(ENABLE_FEAT_AMU, read_feat_amu_id_field(),
- "AMUv1", 1, 2);
- check_feature(ENABLE_FEAT_MOPS, read_feat_mops_id_field(),
- "MOPS", 1, 1);
- check_feature(ENABLE_FEAT_MPAM, read_feat_mpam_version(),
- "MPAM", 1, 17);
- check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(),
- "NV2", 2, 2);
- check_feature(ENABLE_FEAT_SEL2, read_feat_sel2_id_field(),
- "SEL2", 1, 1);
- check_feature(ENABLE_TRF_FOR_NS, read_feat_trf_id_field(),
- "TRF", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_DIT, read_feat_dit_id_field(),
+ "DIT", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_AMU, read_feat_amu_id_field(),
+ "AMUv1", 1, 2);
+ tainted |= check_feature(ENABLE_FEAT_MOPS, read_feat_mops_id_field(),
+ "MOPS", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_MPAM, read_feat_mpam_version(),
+ "MPAM", 1, 17);
+ tainted |= check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(),
+ "NV2", 2, 2);
+ tainted |= check_feature(ENABLE_FEAT_SEL2, read_feat_sel2_id_field(),
+ "SEL2", 1, 1);
+ tainted |= check_feature(ENABLE_TRF_FOR_NS, read_feat_trf_id_field(),
+ "TRF", 1, 1);
/* v8.5 features */
- check_feature(ENABLE_FEAT_MTE2, get_armv8_5_mte_support(), "MTE2",
- MTE_IMPLEMENTED_ELX, MTE_IMPLEMENTED_ASY);
- check_feature(ENABLE_FEAT_RNG, read_feat_rng_id_field(), "RNG", 1, 1);
- check_feature(ENABLE_BTI, read_feat_bti_id_field(), "BTI", 1, 1);
- check_feature(ENABLE_FEAT_RNG_TRAP, read_feat_rng_trap_id_field(),
- "RNG_TRAP", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_MTE2, get_armv8_5_mte_support(),
+ "MTE2", MTE_IMPLEMENTED_ELX, MTE_IMPLEMENTED_ASY);
+ tainted |= check_feature(ENABLE_FEAT_RNG, read_feat_rng_id_field(),
+ "RNG", 1, 1);
+ tainted |= check_feature(ENABLE_BTI, read_feat_bti_id_field(),
+ "BTI", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_RNG_TRAP, read_feat_rng_trap_id_field(),
+ "RNG_TRAP", 1, 1);
/* v8.6 features */
- check_feature(ENABLE_FEAT_AMUv1p1, read_feat_amu_id_field(),
- "AMUv1p1", 2, 2);
- check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(), "FGT", 1, 2);
- check_feature(ENABLE_FEAT_FGT2, read_feat_fgt_id_field(), "FGT2", 2, 2);
- check_feature(ENABLE_FEAT_ECV, read_feat_ecv_id_field(), "ECV", 1, 2);
- check_feature(ENABLE_FEAT_TWED, read_feat_twed_id_field(),
- "TWED", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_AMUv1p1, read_feat_amu_id_field(),
+ "AMUv1p1", 2, 2);
+ tainted |= check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(),
+ "FGT", 1, 2);
+ tainted |= check_feature(ENABLE_FEAT_FGT2, read_feat_fgt_id_field(),
+ "FGT2", 2, 2);
+ tainted |= check_feature(ENABLE_FEAT_ECV, read_feat_ecv_id_field(),
+ "ECV", 1, 2);
+ tainted |= check_feature(ENABLE_FEAT_TWED, read_feat_twed_id_field(),
+ "TWED", 1, 1);
/*
* even though this is a "DISABLE" it does confusingly perform feature
* enablement duties like all other flags here. Check it against the HW
* feature when we intend to diverge from the default behaviour
*/
- check_feature(DISABLE_MTPMU, read_feat_mtpmu_id_field(), "MTPMU", 1, 1);
+ tainted |= check_feature(DISABLE_MTPMU, read_feat_mtpmu_id_field(),
+ "MTPMU", 1, 1);
/* v8.7 features */
- check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), "HCX", 1, 1);
- check_feature(ENABLE_FEAT_LS64_ACCDATA, read_feat_ls64_id_field(), "LS64", 1, 3);
+ tainted |= check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(),
+ "HCX", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_LS64_ACCDATA, read_feat_ls64_id_field(),
+ "LS64", 1, 3);
/* v8.9 features */
- check_feature(ENABLE_FEAT_TCR2, read_feat_tcr2_id_field(),
- "TCR2", 1, 1);
- check_feature(ENABLE_FEAT_S2PIE, read_feat_s2pie_id_field(),
- "S2PIE", 1, 1);
- check_feature(ENABLE_FEAT_S1PIE, read_feat_s1pie_id_field(),
- "S1PIE", 1, 1);
- check_feature(ENABLE_FEAT_S2POE, read_feat_s2poe_id_field(),
- "S2POE", 1, 1);
- check_feature(ENABLE_FEAT_S1POE, read_feat_s1poe_id_field(),
- "S1POE", 1, 1);
- check_feature(ENABLE_FEAT_CSV2_3, read_feat_csv2_id_field(),
- "CSV2_3", 3, 3);
- check_feature(ENABLE_FEAT_DEBUGV8P9, read_feat_debugv8p9_id_field(),
- "DEBUGV8P9", 11, 11);
- check_feature(ENABLE_FEAT_THE, read_feat_the_id_field(),
- "THE", 1, 1);
- check_feature(ENABLE_FEAT_SCTLR2, read_feat_sctlr2_id_field(),
- "SCTLR2", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_TCR2, read_feat_tcr2_id_field(),
+ "TCR2", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_S2PIE, read_feat_s2pie_id_field(),
+ "S2PIE", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_S1PIE, read_feat_s1pie_id_field(),
+ "S1PIE", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_S2POE, read_feat_s2poe_id_field(),
+ "S2POE", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_S1POE, read_feat_s1poe_id_field(),
+ "S1POE", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_CSV2_3, read_feat_csv2_id_field(),
+ "CSV2_3", 3, 3);
+ tainted |= check_feature(ENABLE_FEAT_DEBUGV8P9, read_feat_debugv8p9_id_field(),
+ "DEBUGV8P9", 11, 11);
+ tainted |= check_feature(ENABLE_FEAT_THE, read_feat_the_id_field(),
+ "THE", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_SCTLR2, read_feat_sctlr2_id_field(),
+ "SCTLR2", 1, 1);
/* v9.0 features */
- check_feature(ENABLE_BRBE_FOR_NS, read_feat_brbe_id_field(),
- "BRBE", 1, 2);
- check_feature(ENABLE_TRBE_FOR_NS, read_feat_trbe_id_field(),
- "TRBE", 1, 1);
+ tainted |= check_feature(ENABLE_BRBE_FOR_NS, read_feat_brbe_id_field(),
+ "BRBE", 1, 2);
+ tainted |= check_feature(ENABLE_TRBE_FOR_NS, read_feat_trbe_id_field(),
+ "TRBE", 1, 1);
/* v9.2 features */
- check_feature(ENABLE_SME_FOR_NS, read_feat_sme_id_field(),
- "SME", 1, 2);
- check_feature(ENABLE_SME2_FOR_NS, read_feat_sme_id_field(),
- "SME2", 2, 2);
- check_feature(ENABLE_FEAT_FPMR, read_feat_fpmr_id_field(),
- "FPMR", 1, 1);
+ tainted |= check_feature(ENABLE_SME_FOR_NS, read_feat_sme_id_field(),
+ "SME", 1, 2);
+ tainted |= check_feature(ENABLE_SME2_FOR_NS, read_feat_sme_id_field(),
+ "SME2", 2, 2);
+ tainted |= check_feature(ENABLE_FEAT_FPMR, read_feat_fpmr_id_field(),
+ "FPMR", 1, 1);
/* v9.3 features */
- check_feature(ENABLE_FEAT_D128, read_feat_d128_id_field(),
- "D128", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_D128, read_feat_d128_id_field(),
+ "D128", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_GCIE, read_feat_gcie_id_field(),
+ "GCIE", 1, 1);
/* v9.4 features */
- check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), "GCS", 1, 1);
- check_feature(ENABLE_RME, read_feat_rme_id_field(), "RME", 1, 1);
- check_feature(ENABLE_FEAT_PAUTH_LR, is_feat_pauth_lr_present(), "PAUTH_LR", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(),
+ "GCS", 1, 1);
+ tainted |= check_feature(ENABLE_RME, read_feat_rme_id_field(),
+ "RME", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_PAUTH_LR, is_feat_pauth_lr_present(),
+ "PAUTH_LR", 1, 1);
+ tainted |= check_feature(ENABLE_FEAT_FGWTE3, read_feat_fgwte3_id_field(),
+ "FGWTE3", 1, 1);
if (tainted) {
panic();
}
+
+ detection_done[core_pos] = true;
}
diff --git a/common/tf_log.c b/common/tf_log.c
index bef1739..f678975 100644
--- a/common/tf_log.c
+++ b/common/tf_log.c
@@ -12,7 +12,7 @@
#include <plat/common/platform.h>
/* Set the default maximum log level to the `LOG_LEVEL` build flag */
-static unsigned int max_log_level = LOG_LEVEL;
+static uint32_t max_log_level = LOG_LEVEL;
/*
* The common log function which is invoked by TF-A code.
@@ -23,12 +23,12 @@
*/
void tf_log(const char *fmt, ...)
{
- unsigned int log_level;
+ uint32_t log_level;
va_list args;
const char *prefix_str;
/* We expect the LOG_MARKER_* macro as the first character */
- log_level = fmt[0];
+ log_level = (uint32_t)fmt[0];
/* Verify that log_level is one of LOG_MARKER_* macro defined in debug.h */
assert((log_level > 0U) && (log_level <= LOG_LEVEL_VERBOSE));
@@ -40,7 +40,7 @@
prefix_str = plat_log_get_prefix(log_level);
while (*prefix_str != '\0') {
- (void)putchar(*prefix_str);
+ (void)putchar((int)*prefix_str);
prefix_str++;
}
@@ -51,7 +51,7 @@
void tf_log_newline(const char log_fmt[2])
{
- unsigned int log_level = log_fmt[0];
+ uint32_t log_level = (uint32_t)log_fmt[0];
/* Verify that log_level is one of LOG_MARKER_* macro defined in debug.h */
assert((log_level > 0U) && (log_level <= LOG_LEVEL_VERBOSE));
@@ -69,12 +69,12 @@
* maximum log level is determined by `LOG_LEVEL` build flag at compile time
* and this helper can set a lower (or equal) log level than the one at compile.
*/
-void tf_log_set_max_level(unsigned int log_level)
+void tf_log_set_max_level(uint32_t log_level)
{
assert(log_level <= LOG_LEVEL_VERBOSE);
assert((log_level % 10U) == 0U);
/* Cap log_level to the compile time maximum. */
- if (log_level <= (unsigned int)LOG_LEVEL)
+ if (log_level <= (uint32_t)LOG_LEVEL)
max_log_level = log_level;
}
diff --git a/contrib/libtl b/contrib/libtl
new file mode 160000
index 0000000..67d85f1
--- /dev/null
+++ b/contrib/libtl
@@ -0,0 +1 @@
+Subproject commit 67d85f181b726d2823eea43e8bb4ffb97559d348
diff --git a/docs/about/features.rst b/docs/about/features.rst
index f15144a..78f5ff3 100644
--- a/docs/about/features.rst
+++ b/docs/about/features.rst
@@ -128,6 +128,7 @@
in a platform:
- RSE comms driver ``drivers/arm/rse``
+- GICv5 driver ``drivers/arm/gicv5`` via ``USE_GIC_DRIVER=5``
Still to come
-------------
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 10b5c16..569f932 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -507,6 +507,14 @@
:|F|: include/services/arm_arch_svc.h
:|F|: include/services/std_svc.h
+Live Firmware Activation Service
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
+:|G|: `ManishVB-Arm`_
+:|F|: services/std_svc/lfa
+:|F|: include/plat/common/plat_lfa.h
+:|F|: include/services/lfa_svc.h
+
Platform Ports
~~~~~~~~~~~~~~
diff --git a/docs/components/secure-partition-manager-mm.rst b/docs/components/secure-partition-manager-mm.rst
index d9b2b1b..589a362 100644
--- a/docs/components/secure-partition-manager-mm.rst
+++ b/docs/components/secure-partition-manager-mm.rst
@@ -652,6 +652,13 @@
There are no alignment restrictions on the Base Address. The permission
attributes of the translation granule it lies in are returned.
+ - **uint32** Input Page Count
+
+ This parameter is the number of translation granule size pages from
+ *Base Address* whose permission should be returned.
+ This is calculated as *Input Page count + 1*.
+ (i.e. If Input Page Count is 0, then it is calculated as 1).
+
- Return parameters
- **int32** - Memory Attributes/Return Code
@@ -687,6 +694,16 @@
See `Error Codes`_ for integer values that are associated with each return
code.
+ - **uint32** - Output Page Count
+
+ On success, the number of translation granule size pages from
+ the *Base address* whose permissions match those returned in the
+ *Memory Attributes* output parameter.
+ This is calculated as *Output Page count + 1*.
+ (i.e. If Output Page Count is 0, It is calculated as 1).
+
+ On failure, It must be zero:
+
- Usage
This function is used to request the permission attributes for S-EL0 on a
diff --git a/docs/components/ven-el3-service.rst b/docs/components/ven-el3-service.rst
index 8be1b39..3c35948 100644
--- a/docs/components/ven-el3-service.rst
+++ b/docs/components/ven-el3-service.rst
@@ -36,9 +36,13 @@
+-----------------------------------+ Compliance Suite) SMC | | 1 - 15 are reserved for future expansion. |
| 0xC7000030 - 0xC700003F (SMC64) | handler | |
+-----------------------------------+-----------------------+---------------------------------------------+
-| 0x87000040 - 0x8700FFFF (SMC32) | Reserved | | reserved for future expansion |
+| 0x87000040 - 0x8700004F (SMC32) | TPM Start method | | 0 is in use. |
++-----------------------------------+ | | 1 - 15 are reserved for future expansion. |
+| 0xC7000040 - 0xC700004F (SMC64) | | |
++-----------------------------------+-----------------------+---------------------------------------------+
+| 0x87000050 - 0x8700FFFF (SMC32) | Reserved | | reserved for future expansion |
+-----------------------------------+ | |
-| 0xC7000040 - 0xC700FFFF (SMC64) | | |
+| 0xC7000050 - 0xC700FFFF (SMC64) | | |
+-----------------------------------+-----------------------+---------------------------------------------+
Source definitions for vendor-specific EL3 Monitor Service Calls used by TF-A are located in
@@ -50,6 +54,8 @@
| 1 | 0 | Added Debugfs and PMF services.|
+----------------------------+----------------------------+--------------------------------+
| 1 | 1 | Added ACS SMC handler services.|
++------------------------------------------------------------------------------------------+
+| 1 | 2 | Added TPM Start method. |
+----------------------------+----------------------------+--------------------------------+
*Table 1: Showing different versions of Vendor-specific service and changes done with each version*
@@ -84,9 +90,15 @@
to their ACS EL3 code based on their respective use-cases.
For more details on System ACS, `System ACS`_.
+TPM Start method
+----------------
+
+TPM start method as mentioned in `TCG ACPI specification`_ section 3.3.1.
+
--------------
*Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.*
.. _System ACS: https://developer.arm.com/Architectures/Architectural%20Compliance%20Suite
.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
+.. _TCG ACPI specification: https://trustedcomputinggroup.org/wp-content/uploads/TCG-ACPI-Specification-Version-1.4-Revision-15_pub.pdf
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 117372f..0d6a5dd 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -573,6 +573,22 @@
For Cortex-A710, the following errata build flags are defined :
+- ``ERRATA_A710_1901946``: This applies errata 1901946 workaround to
+ Cortex-A710 CPU. This needs to be enabled only for revision r1p0. It has
+ been fixed in r2p0.
+
+- ``ERRATA_A710_1916945``: This applies errata 1916945 workaround to
+ Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0.
+ It has been fixed in r2p0.
+
+- ``ERRATA_A710_1917258``: This applies errata 1917258 workaround to
+ Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0.
+ It has been fixed in r2p0.
+
+- ``ERRATA_A710_1927200``: This applies errata 1927200 workaround to
+ Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0.
+ It has been fixed in r2p0.
+
- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
r2p0 of the CPU. It is still open.
@@ -820,10 +836,22 @@
CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
CPU. It is fixed in r1p2.
+- ``ERRATA_X3_3213672``: This applies errata 3213672 workaround to Cortex-X3
+ CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2
+ of the CPU. It is still open.
+
+- ``ERRATA_X3_3692984``: This applies errata 3692984 workaround to Cortex-X3
+ CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2
+ of the CPU. It is still open.
+
- ``ERRATA_X3_3701769``: This applies errata 3701769 workaround to Cortex-X3
CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2
of the CPU and it is still open.
+- ``ERRATA_X3_3827463``: This applies errata 3827463 workaround to Cortex-X3
+ CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of
+ the CPU. It is fixed in r1p2.
+
For Cortex-X4, the following errata build flags are defined :
- ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4
@@ -1049,6 +1077,12 @@
please note that this workaround results in increased DSU power consumption
on idle.
+- ``ERRATA_DSU_2900952``: This applies errata 2900952 workaround for the
+ affected DSU-120 configurations. This erratum applies to some r2p0
+ implementations and is fixed in r2p1. The affected r2p0 implementations
+ are determined by reading the IMP_CLUSTERREVIDR_EL1[1] register bit
+ and making sure it's clear.
+
CPU Specific optimizations
--------------------------
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index 1306ecb..669bd96 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -1056,6 +1056,18 @@
integrating PSCI library with AArch32 EL3 Runtime Software can be found
at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
+DSU driver
+----------
+
+Platforms that include a DSU (DynamIQ Shared Unit) can define
+the ``USE_DSU_DRIVER`` build flag to enable the DSU driver.
+This driver is responsible for configuring DSU-related powerdown
+and power feature settings using ``dsu_driver_init()`` and for
+preserving the context of DSU PMU system registers.
+
+To support the DSU driver, platforms must define the ``plat_dsu_data``
+structure.
+
.. _firmware_design_sel1_spd:
Secure-EL1 Payloads and Dispatchers
diff --git a/docs/design/interrupt-framework-design.rst b/docs/design/interrupt-framework-design.rst
index dfb2eac..515cf5e 100644
--- a/docs/design/interrupt-framework-design.rst
+++ b/docs/design/interrupt-framework-design.rst
@@ -649,7 +649,7 @@
.. code:: c
- uint32_t plat_ic_get_interrupt_type(void);
+ uint32_t plat_ic_get_pending_interrupt_type(void);
It should return either ``INTR_TYPE_S_EL1`` or ``INTR_TYPE_NS``.
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 1b3568e..e2fba99 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -375,6 +375,23 @@
This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
mechanism. Default value is ``0``.
+- ``ENABLE_FEAT_FGWTE3``: Numeric value to enable support for
+ Fine Grained Write Trap EL3 (FEAT_FGWTE3), a feature that allows EL3 to
+ restrict overwriting certain EL3 registers after boot.
+ This lockdown is established by setting individual trap bits for
+ system registers that are not expected to be overwritten after boot.
+ This feature is an optional architectural feature and is available from
+ Armv9.4 onwards. This flag can take values from 0 to 2, aligning with
+ the ``ENABLE_FEAT`` mechanism. The default value is 0.
+
+ .. note::
+ This feature currently traps access to all EL3 registers in
+ ``FGWTE3_EL3``, except for ``MDCR_EL3``, ``MPAM3_EL3``,
+ ``TPIDR_EL3``(when ``CRASH_REPORTING=1``), and
+ ``SCTLR_EL3``(when ``HW_ASSISTED_COHERENCY=0``).
+ If additional traps need to be disabled for specific platforms,
+ please contact the Arm team on `TF-A public mailing list`_.
+
- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to
allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as
well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a
@@ -481,6 +498,11 @@
the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism.
Default value is ``0``.
+ - ``ENABLE_FEAT_GCIE``: Boolean value to enable support for the GICv5 CPU
+ interface (see ``USE_GIC_DRIVER`` for the IRI). GICv5 and GICv3 are mutually
+ exclusive, so the ``ENABLE_FEAT`` mechanism is currently not supported.
+ Default value is ``0``.
+
- ``ENABLE_FEAT_THE``: Numeric value to enable support for FEAT_THE
(Translation Hardening Extension) at EL2 and below, setting the bit
SCR_EL3.RCWMASKEn in EL3 to allow access to RCWMASK_EL1 and RCWSMASK_EL1
@@ -536,12 +558,6 @@
power domain dynamic power budgeting and limit the triggering of whole-rail
(i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``.
- - ``FEAT_PABANDON``: Boolean option to enable support for powerdown abandon on
- Arm cores that support it (currently Gelas and Travis). Extends the PSCI
- implementation to expect waking up after the terminal ``wfi``. Currently,
- introduces a performance penalty. Once this is removed, this option will be
- removed and the feature will be enabled by default. Defaults to ``0``.
-
- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
support within generic code in TF-A. This option is currently only supported
in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and
@@ -1114,6 +1130,11 @@
(Coherent memory region is included) or 0 (Coherent memory region is
excluded). Default is 1.
+- ``USE_DSU_DRIVER``: This flag enables DSU (DynamIQ Shared Unit) driver.
+ The DSU driver allows save/restore of DSU PMU registers through
+ ``PRESERVE_DSU_PMU_REGS`` build option and allows platforms to
+ configure powerdown and power settings of DSU.
+
- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the
firmware configuration framework. This will move the io_policies into a
configuration device tree, instead of static structure in the code base.
@@ -1196,11 +1217,6 @@
cluster platforms). If this option is enabled, then warm boot path
enables D-caches immediately after enabling MMU. This option defaults to 0.
-- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory
- tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The
- default value of this flag is ``no``. Note this option must be enabled only
- for ARM architecture greater than Armv8.5-A.
-
- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT``
speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``.
The default value of this flag is ``0``.
@@ -1313,6 +1329,7 @@
- ``3``: use the GICv3 driver. See the next section on how to further configure
it. Use this option for GICv4 implementations.
+ - ``5``: use the EXPERIMENTAL GICv5 driver. Requires ``ENABLE_FEAT_GCIE=1``.
For GIC driver versions other than ``1``, deciding when to save and restore GIC
context on a power domain state transition, as well as any GIC actions outside
@@ -1496,6 +1513,9 @@
per the `PSA Crypto API specification`_. This feature is only supported if
using MbedTLS 3.x version. It is disabled (``0``) by default.
+- ``LFA_SUPPORT``: Boolean flag to enable support for Live Firmware
+ activation as per the specification. This option defaults to 0.
+
- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware
Handoff using Transfer List defined in `Firmware Handoff specification`_.
This defaults to ``0``. Current implementation follows the Firmware Handoff
@@ -1558,3 +1578,4 @@
.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9
.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/
.. _Platform Initialization specification: https://uefi.org/specs/PI/1.8/index.html
+.. _TF-A public mailing list: https://lists.trustedfirmware.org/mailman3/lists/tf-a.lists.trustedfirmware.org/
diff --git a/docs/getting_started/docs-build.rst b/docs/getting_started/docs-build.rst
index 54e29dd..e11da77 100644
--- a/docs/getting_started/docs-build.rst
+++ b/docs/getting_started/docs-build.rst
@@ -42,7 +42,7 @@
.. code:: shell
- poetry run make doc
+ make doc
Output from the build process will be placed in: ``docs/build/html``.
@@ -55,7 +55,7 @@
.. code:: shell
- poetry run make -C docs help
+ make -C docs help
To build the documentation in PDF format, additionally ensure that the following
packages are installed:
@@ -80,9 +80,10 @@
Building rendered documentation from Poetry's virtual environment
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-The command ``poetry run`` used in the steps above executes the input command
-from inside the project's virtual environment. The easiest way to activate this
-virtual environment is with the ``poetry shell`` command.
+If Poetry is installed, the ``doc`` target wraps its build steps with ``poetry
+run``, which runs the specified command within the project's virtual
+environment. The easiest way to activate this environment manually is by using
+the ``poetry shell`` command.
Running ``poetry shell`` from the directory containing this project, activates
the same virtual environment. This creates a sub-shell through which you can
@@ -91,7 +92,7 @@
.. code:: shell
poetry shell
- make doc
+ make -C docs html
Type ``exit`` to deactivate the virtual environment and exit this new shell. For
other use cases, please see the official `Poetry`_ documentation.
@@ -121,7 +122,7 @@
--------------
-*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2025, Arm Limited. All rights reserved.*
.. _Sphinx: http://www.sphinx-doc.org/en/master/
.. _Poetry: https://python-poetry.org/docs/
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index da7a2c3..66c278e 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -182,6 +182,44 @@
You can read more about Git hooks in the *githooks* page of the Git
documentation, available `here <https://git-scm.com/docs/githooks>`_.
+.. _git_submodules:
+
+Cloning Additional Git Submodules
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Some dependencies in TF-A, such as Transfer List Library ``libtl``, are managed
+using Git submodules. Submodules allow external repositories to be included
+within the main project while maintaining their own commit history.
+
+Initial Clone with Submodules
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+If you're cloning the repository for the first time, run the following commands
+to initialize and fetch all submodules:
+
+.. code-block:: bash
+
+ git clone --recurse-submodules "https://git.trustedfirmware.org/TF-A/trusted-firmware-a"
+
+This ensures all submodules (including ``libtl``) are correctly checked out.
+
+Updating Submodules
+^^^^^^^^^^^^^^^^^^^
+
+If the project updates the reference to a submodule (e.g., points to a new
+commit of ``libtl``), you can update your local copy by running:
+
+.. code-block:: bash
+
+ git pull
+ git submodule update --init --recursive
+
+To fetch the latest commits from all submodules, you can use:
+
+.. code-block:: bash
+
+ git submodule update --remote
+
--------------
*Copyright (c) 2021-2025, Arm Limited. All rights reserved.*
diff --git a/docs/license.rst b/docs/license.rst
index e35b9bb..05458b9 100644
--- a/docs/license.rst
+++ b/docs/license.rst
@@ -119,6 +119,15 @@
- ``include/lib/hob/mmram.h``
- ``include/lib/hob/mpinfo.h``
+- Some source files originating from the `mbed OS`_ project.
+ These files are licensed under the Apache License, Version 2.0, which is a
+ permissive license compatible with BSD-3-Clause. Any contributions to this
+ code must also be made under the terms of `Apache License 2.0`_.
+ These files are:
+
+ - ``tools/memory/memory/mapsummary.py``
+ - ``tools/memory/memory/mapsummary_flamegraph.hmtl``
+
.. _FreeBSD: http://www.freebsd.org
.. _Linux MIT license: https://raw.githubusercontent.com/torvalds/linux/master/LICENSES/preferred/MIT
.. _SCC: http://www.simple-cc.org/
@@ -126,3 +135,4 @@
.. _Apache License 2.0: https://www.apache.org/licenses/LICENSE-2.0.txt
.. _pydevicetree: https://pypi.org/project/pydevicetree/
.. _edk2: https://github.com/tianocore/edk2
+.. _mbed OS: https://github.com/ARMmbed/mbed-os/
diff --git a/docs/plat/arm/fvp/fvp-build-options.rst b/docs/plat/arm/fvp/fvp-build-options.rst
index 79dc0dc..3d87494 100644
--- a/docs/plat/arm/fvp/fvp-build-options.rst
+++ b/docs/plat/arm/fvp/fvp-build-options.rst
@@ -27,6 +27,7 @@
- ``FVP_GICV2`` : The GICv2 only driver is selected
- ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
+ - ``FVP_GICV5`` : The GICv5 only driver is selected
- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for
@@ -41,6 +42,9 @@
HW_CONFIG blob instead of the DTS file. This option is useful to override
the default HW_CONFIG selected by the build system.
+- ``FVP_HW_CONFIG_ADDR`` : Specify the memory address in which to load the
+ HW_CONFIG. The default value is ``0x82000000``.
+
- ``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of
inactive/fused CPU cores as read-only. The default value of this option
is ``0``, which means the redistributor pages of all CPU cores are marked
diff --git a/docs/plat/arm/fvp/fvp-specific-configs.rst b/docs/plat/arm/fvp/fvp-specific-configs.rst
index 0f51e4b..9608969 100644
--- a/docs/plat/arm/fvp/fvp-specific-configs.rst
+++ b/docs/plat/arm/fvp/fvp-specific-configs.rst
@@ -241,6 +241,34 @@
(Default) For use with Foundation FVP with Base memory map configuration
and Linux GICv3 support.
+GICv5 Support
+^^^^^^^^^^^^^
+
+GICv5 support in TF-A is currently **experimental** and provided only for early
+development and testing purposes. A simplified build configuration is available
+to allow booting the Linux kernel as a BL33 payload on the FVP platform.
+
+Key notes:
+
+- The support is **not production-ready** and is intended to assist with
+ upstream kernel development and validation.
+- The device tree bindings are **not finalized**; support has been validated
+ only with a **custom device tree**.
+- Use this configuration at your own discretion, understanding that the design
+ and register usage may change in future revisions.
+
+This configuration is **temporary** and may be removed once full GICv5 support
+is integrated upstream.
+
+.. code:: shell
+
+ make PLAT=fvp DEBUG=1 \
+ CTX_INCLUDE_AARCH32_REGS=0 \
+ FVP_USE_GIC_DRIVER=FVP_GICV5 \
+ ARM_LINUX_KERNEL_AS_BL33=1 \
+ PRELOADED_BL33_BASE=0x84000000 \
+ FVP_HW_CONFIG_DTS=<PROVIDE_YOUR_OWN_DT> \
+
--------------
*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
diff --git a/docs/plat/st/stm32mp2.rst b/docs/plat/st/stm32mp2.rst
index 87bb6a5..e64b989 100644
--- a/docs/plat/st/stm32mp2.rst
+++ b/docs/plat/st/stm32mp2.rst
@@ -12,6 +12,43 @@
STM32MP2 Versions
-----------------
+Here are the variants for STM32MP2:
+- STM32MP21
+- STM32MP23
+- STM32MP25
+
+STM32MP21 Versions
+~~~~~~~~~~~~~~~~~~
+The STM32MP21 series is available in 3 different lines which are pin-to-pin compatible:
+
+- STM32MP215: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD - CSI - LTDC
+- STM32MP213: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
+- STM32MP211: Single Cortex-A35 + Cortex-M33 - 1x Ethernet
+
+Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
+
+- A Basic + Cortex-A35 @ 1.2GHz
+- C Secure Boot + HW Crypto + Cortex-A35 @ 1.2GHz
+- D Basic + Cortex-A35 @ 1.5GHz
+- F Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz
+
+STM32MP23 Versions
+~~~~~~~~~~~~~~~~~~
+The STM32MP23 series is available in 3 different lines which are pin-to-pin compatible:
+
+- STM32MP235: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD - H264 - 3D GPU - AI / NN - LVDS / DSI
+- STM32MP233: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
+- STM32MP231: Single Cortex-A35 + Cortex-M33 - 1x Ethernet
+
+Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
+
+- A Basic + Cortex-A35 @ 1.2GHz
+- C Secure Boot + HW Crypto + Cortex-A35 @ 1.2GHz
+- D Basic + Cortex-A35 @ 1.5GHz
+- F Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz
+
+STM32MP25 Versions
+~~~~~~~~~~~~~~~~~~
The STM32MP25 series is available in 4 different lines which are pin-to-pin compatible:
- STM32MP257: Dual Cortex-A35 cores, Cortex-M33 core - 3x Ethernet (2+1 switch) - 3x CAN FD – H264 - 3D GPU – AI / NN - LVDS
@@ -70,6 +107,10 @@
- | ``STM32MP_DDR_FIP_IO_STORAGE``: to store DDR firmware in FIP.
| Default: 1
+- | ``STM32MP21``: to select STM32MP21 variant configuration.
+ | Default: 0
+- | ``STM32MP23``: to select STM32MP23 variant configuration.
+ | Default: 0
- | ``STM32MP25``: to select STM32MP25 variant configuration.
| Default: 1
@@ -154,4 +195,4 @@
.. _STM32MP2 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP25_microprocessor#Part_number_codification
.. _STMicroelectronics DDR PHY github: https://github.com/STMicroelectronics/stm32-ddr-phy-binary
-*Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved*
+*Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved*
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index 7e40e47..81999fc 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -1511,6 +1511,23 @@
soc_revision[0:30] = SOC revision of specific SOC
+Function : plat_get_soc_name()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ Argument : char **
+ Return : int32_t
+
+The plat_get_soc_name() function allows a platform to expose the SoC name to
+the firmware. It takes a pointer to a character pointer as an argument, which
+must be set to point to a static, null-terminated SoC name string. The string
+must be encoded in UTF-8 and should use only printable ASCII characters for
+compatibility. It must not exceed 136 bytes, including the null terminator. On
+success, the function returns SMC_ARCH_CALL_SUCCESS. If the platform does not
+support SoC name retrieval, it returns SMC_ARCH_CALL_NOT_SUPPORTED. This API
+allows platforms to support SoC name queries via SMCCC_ARCH_SOC_ID.
+
Function : plat_is_smccc_feature_available()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -3107,13 +3124,14 @@
the CPU power domain and its parent power domain levels.
It is preferred that this function returns. The caller will invoke
-``psci_power_down_wfi()`` to powerdown the CPU, mitigate any powerdown errata,
+``wfi()`` to powerdown the CPU, mitigate any powerdown errata,
and handle any wakeups that may arise. Previously, this function did not return
and instead called ``wfi`` (in an infinite loop) directly. This is still
possible on platforms where this is guaranteed to be terminal, however, it is
strongly discouraged going forward.
-Previously this function was called ``pwr_domain_pwr_down_wfi()``.
+Previously this function was called ``pwr_domain_pwr_down_wfi()`` and invoked
+``psci_power_down_wfi()`` (now removed).
plat_psci_ops.pwr_domain_on_finish()
....................................
@@ -3634,8 +3652,8 @@
External Abort handling and RAS Support
---------------------------------------
-If any cores on the platform support powerdown abandon (i.e. ``FEAT_PABANDON``
-is set, check the "Core powerup and powerdown sequence" in their TRMs), then
+If any cores on the platform support powerdown abandon (check the "Core powerup
+and powerdown sequence" in their TRMs), then
these functions should be able to handle being called with power domains off and
after the powerdown ``wfi``. In other words it may run after a call to
``pwr_domain_suspend()`` and before a call to ``pwr_domain_suspend_finish()``
@@ -3928,6 +3946,58 @@
Enabling the MEASURED_BOOT flag adds extra platform requirements. Please refer
to :ref:`Measured Boot Design` for more details.
+Live Firmware Activation Interface
+----------------------------------
+
+Function : plat_lfa_get_components()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ Argument : plat_lfa_component_info_t **
+ Return : int
+
+This platform API provides the list of LFA components available for activation.
+It populates a pointer to an array of ``plat_lfa_component_info_t`` structures,
+which contain information about each component (like UUID, ID, etc.). It returns
+0 on success, or a standard error code on failure.
+
+Function : is_plat_lfa_activation_pending()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ Argument : uint32_t
+ Return : bool
+
+This platform API checks if the specified LFA component, identified
+by its ``lfa_component_id``, is available for activation. It returns
+true if available, otherwise false.
+
+Function : plat_lfa_cancel()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ Argument : uint32_t
+ Return : int
+
+This platform API allows the platform to cancel an ongoing update or activation
+process for the specified ``lfa_component_id``. It returns 0 on success or
+a standard error code on failure.
+
+Function : plat_lfa_load_auth_image()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ Argument : uint32_t
+ Return : int
+
+The platform uses this API to load, authenticate and measure the component
+specified by ``lfa_component_id``. It should return 0 on success or appropriate
+error codes for load/authentication failures.
+
--------------
*Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/process/commit-style.rst b/docs/process/commit-style.rst
index c287599..97b4b44 100644
--- a/docs/process/commit-style.rst
+++ b/docs/process/commit-style.rst
@@ -36,6 +36,9 @@
[optional footer(s)]
+Note that the type, the scope and the first letter of the description (also
+called subject by the commitlint checker) must be lower case.
+
The following example commit message demonstrates the use of the
``refactor`` type and the ``amu`` scope:
@@ -144,7 +147,7 @@
--------------
-*Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.*
.. _Conventional Commits: https://www.conventionalcommits.org/en/v1.0.0
.. _Gerrit Change-Ids documentation: https://review.trustedfirmware.org/Documentation/user-changeid.html
diff --git a/docs/security_advisories/index.rst b/docs/security_advisories/index.rst
index ad55546..a6fed96 100644
--- a/docs/security_advisories/index.rst
+++ b/docs/security_advisories/index.rst
@@ -16,3 +16,5 @@
security-advisory-tfv-9.rst
security-advisory-tfv-10.rst
security-advisory-tfv-11.rst
+ security-advisory-tfv-12.rst
+ security-advisory-tfv-13.rst
diff --git a/docs/security_advisories/security-advisory-tfv-10.rst b/docs/security_advisories/security-advisory-tfv-10.rst
index f53bae1..6067b52 100644
--- a/docs/security_advisories/security-advisory-tfv-10.rst
+++ b/docs/security_advisories/security-advisory-tfv-10.rst
@@ -98,7 +98,7 @@
``drivers/auth/``) require that the certificate's signature has already been
validated prior to calling ``get_ext()``, or any function that calls ``get_ext()``.
Platforms taking their chain of trust from a dynamic configuration file (such as
-``fdts/tbbr_cot_descriptors.dtsi``) are also safe, as signature verification will
+``fdts/tbbr_cot_descriptors.dts``) are also safe, as signature verification will
always be done prior to any calls to ``get_ext()`` or ``auth_nvctr()`` in this
case, no matter the order of the properties in the file. Therefore, it is not
possible to exploit this vulnerability pre-authentication in upstream TF-A.
diff --git a/docs/security_advisories/security-advisory-tfv-12.rst b/docs/security_advisories/security-advisory-tfv-12.rst
new file mode 100644
index 0000000..48d2cb8
--- /dev/null
+++ b/docs/security_advisories/security-advisory-tfv-12.rst
@@ -0,0 +1,86 @@
+Advisory TFV-12 (CVE-2024-5660)
+================================
+
++----------------+--------------------------------------------------------------+
+| Title | When Hardware Page Aggregation (HPA) is enabled memory |
+| | accesses may be translated incorrectly. |
++================+==============================================================+
+| CVE ID | `CVE-2024-5660`_ |
++----------------+--------------------------------------------------------------+
+| Date | Reported on 26 Jan 2024 |
++----------------+--------------------------------------------------------------+
+| Versions | TF-A version from v2.2 to v2.12 |
+| Affected | LTS releases lts-v2.8.0 to lts-v2.8.26 |
+| | LTS releases lts-v2.10.0 to lts-v2.10.10 |
++----------------+--------------------------------------------------------------+
+| Configurations | Arm CPUs with Hardware Page Aggregation (HPA) running in |
+| Affected | environments where a modified, untrusted guest OS may |
+| | operate, especially with specific hypervisors. |
++----------------+--------------------------------------------------------------+
+| Impact | Potential for a compromised guest OS to attack the host via |
+| | HPA mechanism, resulting in possible information disclosure. |
++----------------+--------------------------------------------------------------+
+| Fix Version | `Gerrit-Patches`_ |
++----------------+--------------------------------------------------------------+
+| Credit | Arm |
++----------------+--------------------------------------------------------------+
+
+Description
+-----------
+
+A vulnerability has been identified in certain Arm CPUs implementing the
+Hardware Page Aggregation (HPA) feature. In environments utilizing virtualization,
+a specially crafted or compromised guest operating system could exploit this
+vulnerability to affect the host system. This could potentially lead to information
+disclosure depending on the deployment scenario and hypervisor configuration.
+
+The below table lists the CPUs that mitigate against this vulnerability in TF-A.
+
++---------------+
+| **Core** |
++---------------+
+| Cortex-A77 |
++---------------+
+| Cortex-A78 |
++---------------+
+| Cortex-A78C |
++---------------+
+| Cortex-A78AE |
++---------------+
+| Cortex-A710 |
++---------------+
+| Cortex-X1 |
++---------------+
+| Cortex-X2 |
++---------------+
+| Cortex-X3 |
++---------------+
+| Cortex-X4 |
++---------------+
+| Cortex-X925 |
++---------------+
+| Neoverse-V1 |
++---------------+
+| Neoverse-V2 |
++---------------+
+| Neoverse-V3 |
++---------------+
+| Neoverse-N2 |
++---------------+
+
+Mitigation and Recommendations
+------------------------------
+
+Arm recommends following the mitigation steps and configuration changes described in the
+official advisory. The issue is avoided by setting CPUECTLR_EL1[46] to 1 which will
+disable hardware page aggregation.
+
+Users should refer to the latest firmware updates as provided by vendors
+and ensure that HPA-related security mitigations are enabled where applicable.
+
+For further technical information, affected CPUs, and detailed guidance, refer to the
+full `Official Arm Advisory`_.
+
+.. _CVE-2024-5660: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2024-5660
+.. _Gerrit-Patches: https://review.trustedfirmware.org/q/topic:%22sm/fix_erratum%22
+.. _Official Arm Advisory: https://developer.arm.com/documentation/110324/latest
diff --git a/docs/security_advisories/security-advisory-tfv-13.rst b/docs/security_advisories/security-advisory-tfv-13.rst
new file mode 100644
index 0000000..929e9b8
--- /dev/null
+++ b/docs/security_advisories/security-advisory-tfv-13.rst
@@ -0,0 +1,82 @@
+Advisory TFV-13 (CVE-2024-7881)
+================================
+
++----------------+-----------------------------------------------------------------+
+| Title | An unprivileged context can trigger a data memory-dependent |
+| | prefetch engine to fetch the contents of a privileged location |
+| | and consume those contents as an address that is |
+| | also dereferenced. |
+| | |
++================+=================================================================+
+| CVE ID | `CVE-2024-7881`_ |
++----------------+-----------------------------------------------------------------+
+| Date | Reported on 16 August 2024 |
++----------------+-----------------------------------------------------------------+
+| Versions | TF-A version from v2.2 to v2.12 |
+| Affected | LTS releases lts-v2.8.0 to lts-v2.8.28 |
+| | LTS releases lts-v2.10.0 to lts-v2.10.12 |
++----------------+-----------------------------------------------------------------+
+| Configurations | All |
+| Affected | |
++----------------+-----------------------------------------------------------------+
+| Impact | Potential leakage of secure world data to normal world. |
++----------------+-----------------------------------------------------------------+
+| Fix Version | `Gerrit topic #ar/smccc_arch_wa_4`_ |
+| | Also see mitigation guidance in the `Official Arm Advisory`_ |
++----------------+-----------------------------------------------------------------+
+| Credit | Arm |
++----------------+-----------------------------------------------------------------+
+
+Description
+-----------
+
+An issue has been identified in some Arm-based CPUs that may allow
+an unprivileged context to trigger a data memory-dependent prefetch engine
+to fetch the contents of a privileged location (for which it
+does not have read permission) and consume those contents as an address
+that is also dereferenced.
+
+The below table lists all the CPUs impacted by this vulnerability and have
+mitigation in TF-A.
+
++----------------------+
+| Core |
++----------------------+
+| Cortex-X3 |
++----------------------+
+| Cortex-X4 |
++----------------------+
+| Cortex-X925 |
++----------------------+
+| Neoverse-V2 |
++----------------------+
+| Neoverse-V3 |
++----------------------+
+| Neoverse-V3AE |
++----------------------+
+
+Mitigation and Recommendations
+------------------------------
+
+Arm recommends following the mitigation steps and configuration changes
+described in the official advisory. The mitigation for CVE-2024-7881 is
+implemented at EL3 and addresses vulnerabilities caused by memory-dependant
+speculative prefetching. This issue is avoided by setting CPUACTLR6_EL1[41]
+to 1, this disables the affected prefetcher.
+
+Arm has updated the SMC Calling Convention spec so that privileged normal world
+software can identify when the issue has been mitigated in
+firmware (SMCCC_ARCH_WORKAROUND_4). Refer to the `SMC Calling Convention
+Specification`_ for more details.
+
+The above workaround is enabled by default (on vulnerable CPUs only).
+Platforms can choose to disable them at compile time if
+they do not require them.
+
+For further technical information, affected CPUs, and detailed guidance,
+refer to the full `Official Arm Advisory`_.
+
+.. _CVE-2024-7881: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2024-7881
+.. _Gerrit topic #ar/smccc_arch_wa_4: https://review.trustedfirmware.org/q/topic:%22ar/smccc_arch_wa_4%22
+.. _SMC Calling Convention specification: https://developer.arm.com/documentation/den0028/latest
+.. _Official Arm Advisory: https://developer.arm.com/documentation/110326/latest
diff --git a/docs/tools/cot-dt2c.rst b/docs/tools/cot-dt2c.rst
index e8bb1ac..64f92b6 100644
--- a/docs/tools/cot-dt2c.rst
+++ b/docs/tools/cot-dt2c.rst
@@ -58,7 +58,7 @@
.. code::
cot-dt2c convert-to-c [INPUT DTS PATH] [OUTPUT C PATH]
- cot-dt2c convert-to-c fdts/tbbr_cot_descriptors.dtsi test.c
+ cot-dt2c convert-to-c fdts/tbbr_cot_descriptors.dts test.c
Validate CoT descriptors
@@ -81,7 +81,7 @@
.. code::
cot-dt2c validate-cot [INPUT DTS PATH]
- cot-dt2c validate-cot fdts/tbbr_cot_descriptors.dtsi
+ cot-dt2c validate-cot fdts/tbbr_cot_descriptors.dts
Visualize CoT descriptors
@@ -93,7 +93,7 @@
.. code::
cot-dt2c visualize-cot [INPUT DTS PATH]
- cot-dt2c visualize-cot fdts/tbbr_cot_descriptors.dtsi
+ cot-dt2c visualize-cot fdts/tbbr_cot_descriptors.dts
Validate Other DT files
@@ -113,7 +113,7 @@
--------------
-*Copyright (c) 2024, Arm Limited. All rights reserved.*
+*Copyright (c) 2024-2025, Arm Limited. All rights reserved.*
.. _tools/cot_dt2c/pyproject.toml: https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/heads/integration/tools/cot_dt2c/pyproject.toml
.. _Poetry: https://python-poetry.org/docs/
diff --git a/docs/tools/memory-layout-tool.rst b/docs/tools/memory-layout-tool.rst
index d9c358d..0a447c5 100644
--- a/docs/tools/memory-layout-tool.rst
+++ b/docs/tools/memory-layout-tool.rst
@@ -41,7 +41,7 @@
.. code:: shell
- $ poetry run memory -s
+ $ poetry run memory symbols
build-path: build/fvp/release
Virtual Address Map:
+------------__BL1_RAM_END__------------+---------------------------------------+
@@ -116,14 +116,14 @@
Memory Footprint
~~~~~~~~~~~~~~~~
-The tool enables users to view static memory consumption. When the options
-``-f``, or ``--footprint`` are provided, the script analyses the ELF binaries in
-the build path to generate a table (per memory type), showing memory allocation
-and usage. This is the default output generated by the tool.
+The tool enables users to view static memory consumption. When the ``footprint``
+command is provided, the script analyses the ELF binaries in the build path to
+generate a table (per memory type), showing memory allocation and usage. This is
+the default output generated by the tool.
.. code:: shell
- $ poetry run memory -f
+ $ poetry run memory footprint
build-path: build/fvp/release
+----------------------------------------------------------------------------+
| Memory Usage (bytes) [RAM] |
@@ -150,13 +150,13 @@
Memory Tree
~~~~~~~~~~~
-A hierarchical view of the memory layout can be produced by passing the option
-``-t`` or ``--tree`` to the tool. This gives the start, end, and size of each
-module, their ELF segments as well as sections.
+A hierarchical view of the memory layout can be produced by passing the ``tree``
+command to the tool. This gives the start, end, and size of each module, their
+ELF segments as well as sections.
.. code:: shell
- $ poetry run memory -t
+ $ poetry run memory tree
build-path: build/fvp/release
name start end size
bl1 0 400c000 400c000
@@ -209,7 +209,7 @@
.. code::
- $ poetry run memory -t --depth 2
+ $ poetry run memory tree --depth 2
build-path: build/fvp/release
name start end size
bl1 0 400c000 400c000
@@ -229,6 +229,169 @@
├── 00 4003000 4010000 d000
└── 01 4010000 4021000 11000
+Memory Summary
+~~~~~~~~~~~~~~
+
+The tool provides a by-translation-unit summary of the sizes (``text``, ``bss``,
+``data``) contributed by each translation unit or group of translation units.
+For example, to print a table of an FVP build, with a path depth of 3:
+
+.. code::
+
+ $ poetry run memory summary build/fvp/debug/bl1/bl1.map -d 3
+ | Module | .text | .data | .bss |
+ |----------------------------------------|---------------|-------------|---------------|
+ | [fill] | 3204(+3204) | 0(+0) | 97(+97) |
+ | bl1/aem_generic.o | 0(+0) | 0(+0) | 0(+0) |
+ | bl1/arm_bl1_fwu.o | 224(+224) | 80(+80) | 0(+0) |
+ | bl1/arm_bl1_setup.o | 608(+608) | 0(+0) | 17(+17) |
+ | bl1/arm_common.o | 116(+116) | 0(+0) | 0(+0) |
+ | bl1/arm_console.o | 116(+116) | 0(+0) | 40(+40) |
+ | bl1/arm_dev_rotpk.o | 0(+0) | 0(+0) | 0(+0) |
+ | bl1/arm_dyn_cfg.o | 276(+276) | 0(+0) | 7184(+7184) |
+ | bl1/arm_dyn_cfg_helpers.o | 364(+364) | 0(+0) | 0(+0) |
+ | bl1/arm_err.o | 12(+12) | 0(+0) | 0(+0) |
+ | bl1/arm_fconf_io.o | 0(+0) | 952(+952) | 0(+0) |
+ | bl1/arm_helpers.o | 44(+44) | 0(+0) | 0(+0) |
+ | bl1/arm_io_storage.o | 480(+480) | 0(+0) | 32(+32) |
+ | bl1/auth_mod.o | 1288(+1288) | 0(+0) | 0(+0) |
+ | bl1/backtrace.o | 444(+444) | 0(+0) | 0(+0) |
+ | bl1/bl1_arch_setup.o | 16(+16) | 0(+0) | 0(+0) |
+ | bl1/bl1_context_mgmt.o | 340(+340) | 0(+0) | 1392(+1392) |
+ | bl1/bl1_entrypoint.o | 236(+236) | 0(+0) | 0(+0) |
+ | bl1/bl1_exceptions.o | 2240(+2240) | 0(+0) | 0(+0) |
+ | bl1/bl1_fwu.o | 2188(+2188) | 44(+44) | 0(+0) |
+ | bl1/bl1_main.o | 620(+620) | 0(+0) | 0(+0) |
+ | bl1/bl_common.o | 772(+772) | 0(+0) | 4(+4) |
+ | bl1/board_arm_helpers.o | 44(+44) | 0(+0) | 0(+0) |
+ | bl1/board_arm_trusted_boot.o | 44(+44) | 16(+16) | 0(+0) |
+ | bl1/cache_helpers.o | 112(+112) | 0(+0) | 0(+0) |
+ | bl1/cci.o | 408(+408) | 0(+0) | 24(+24) |
+ | bl1/context.o | 348(+348) | 0(+0) | 0(+0) |
+ | bl1/context_mgmt.o | 1692(+1692) | 0(+0) | 48(+48) |
+ | bl1/cortex_a35.o | 96(+96) | 0(+0) | 0(+0) |
+ | bl1/cortex_a53.o | 248(+248) | 0(+0) | 0(+0) |
+ | bl1/cortex_a57.o | 384(+384) | 0(+0) | 0(+0) |
+ | bl1/cortex_a72.o | 356(+356) | 0(+0) | 0(+0) |
+ | bl1/cortex_a73.o | 304(+304) | 0(+0) | 0(+0) |
+ | bl1/cpu_helpers.o | 200(+200) | 0(+0) | 0(+0) |
+ | bl1/crypto_mod.o | 380(+380) | 0(+0) | 0(+0) |
+ | bl1/debug.o | 224(+224) | 0(+0) | 0(+0) |
+ | bl1/delay_timer.o | 64(+64) | 0(+0) | 8(+8) |
+ | bl1/enable_mmu.o | 112(+112) | 0(+0) | 0(+0) |
+ | bl1/errata_report.o | 564(+564) | 0(+0) | 0(+0) |
+ | bl1/fconf.o | 148(+148) | 0(+0) | 0(+0) |
+ | bl1/fconf_dyn_cfg_getter.o | 656(+656) | 32(+32) | 144(+144) |
+ | bl1/fconf_tbbr_getter.o | 332(+332) | 0(+0) | 24(+24) |
+ | bl1/fdt_wrappers.o | 452(+452) | 0(+0) | 0(+0) |
+ | bl1/fvp_bl1_setup.o | 168(+168) | 0(+0) | 0(+0) |
+ | bl1/fvp_common.o | 512(+512) | 0(+0) | 8(+8) |
+ | bl1/fvp_cpu_pwr.o | 136(+136) | 0(+0) | 0(+0) |
+ | bl1/fvp_err.o | 44(+44) | 0(+0) | 0(+0) |
+ | bl1/fvp_helpers.o | 148(+148) | 0(+0) | 0(+0) |
+ | bl1/fvp_io_storage.o | 228(+228) | 0(+0) | 16(+16) |
+ | bl1/fvp_trusted_boot.o | 292(+292) | 0(+0) | 0(+0) |
+ | bl1/generic_delay_timer.o | 136(+136) | 0(+0) | 16(+16) |
+ | bl1/img_parser_mod.o | 588(+588) | 0(+0) | 20(+20) |
+ | bl1/io_fip.o | 1332(+1332) | 0(+0) | 100(+100) |
+ | bl1/io_memmap.o | 736(+736) | 16(+16) | 32(+32) |
+ | bl1/io_semihosting.o | 648(+648) | 16(+16) | 0(+0) |
+ | bl1/io_storage.o | 1268(+1268) | 0(+0) | 104(+104) |
+ | bl1/mbedtls_common.o | 208(+208) | 0(+0) | 4(+4) |
+ | bl1/mbedtls_crypto.o | 636(+636) | 0(+0) | 0(+0) |
+ | bl1/mbedtls_x509_parser.o | 1588(+1588) | 0(+0) | 120(+120) |
+ | bl1/misc_helpers.o | 392(+392) | 0(+0) | 0(+0) |
+ | bl1/multi_console.o | 528(+528) | 1(+1) | 8(+8) |
+ | bl1/pl011_console.o | 308(+308) | 0(+0) | 0(+0) |
+ | bl1/plat_bl1_common.o | 208(+208) | 0(+0) | 0(+0) |
+ | bl1/plat_bl_common.o | 40(+40) | 0(+0) | 0(+0) |
+ | bl1/plat_common.o | 48(+48) | 0(+0) | 8(+8) |
+ | bl1/plat_log_common.o | 48(+48) | 0(+0) | 0(+0) |
+ | bl1/plat_tbbr.o | 128(+128) | 0(+0) | 0(+0) |
+ | bl1/platform_helpers.o | 12(+12) | 0(+0) | 0(+0) |
+ | bl1/platform_up_stack.o | 16(+16) | 0(+0) | 0(+0) |
+ | bl1/semihosting.o | 352(+352) | 0(+0) | 0(+0) |
+ | bl1/semihosting_call.o | 8(+8) | 0(+0) | 0(+0) |
+ | bl1/smmu_v3.o | 296(+296) | 0(+0) | 0(+0) |
+ | bl1/sp805.o | 64(+64) | 0(+0) | 0(+0) |
+ | bl1/tbbr_cot_bl1.o | 0(+0) | 48(+48) | 156(+156) |
+ | bl1/tbbr_cot_common.o | 0(+0) | 144(+144) | 306(+306) |
+ | bl1/tbbr_img_desc.o | 0(+0) | 768(+768) | 0(+0) |
+ | bl1/tf_log.o | 200(+200) | 4(+4) | 0(+0) |
+ | bl1/xlat_tables_arch.o | 736(+736) | 0(+0) | 0(+0) |
+ | bl1/xlat_tables_context.o | 192(+192) | 96(+96) | 1296(+1296) |
+ | bl1/xlat_tables_core.o | 2112(+2112) | 0(+0) | 0(+0) |
+ | bl1/xlat_tables_utils.o | 8(+8) | 0(+0) | 0(+0) |
+ | lib/libc.a/assert.o | 48(+48) | 0(+0) | 0(+0) |
+ | lib/libc.a/exit.o | 64(+64) | 0(+0) | 8(+8) |
+ | lib/libc.a/memchr.o | 44(+44) | 0(+0) | 0(+0) |
+ | lib/libc.a/memcmp.o | 52(+52) | 0(+0) | 0(+0) |
+ | lib/libc.a/memcpy.o | 32(+32) | 0(+0) | 0(+0) |
+ | lib/libc.a/memmove.o | 52(+52) | 0(+0) | 0(+0) |
+ | lib/libc.a/memset.o | 140(+140) | 0(+0) | 0(+0) |
+ | lib/libc.a/printf.o | 1532(+1532) | 0(+0) | 0(+0) |
+ | lib/libc.a/snprintf.o | 1748(+1748) | 0(+0) | 0(+0) |
+ | lib/libc.a/strcmp.o | 44(+44) | 0(+0) | 0(+0) |
+ | lib/libc.a/strlen.o | 28(+28) | 0(+0) | 0(+0) |
+ | lib/libfdt.a/fdt.o | 1460(+1460) | 0(+0) | 0(+0) |
+ | lib/libfdt.a/fdt_ro.o | 1392(+1392) | 0(+0) | 0(+0) |
+ | lib/libfdt.a/fdt_wip.o | 244(+244) | 0(+0) | 0(+0) |
+ | lib/libmbedtls.a/asn1parse.o | 956(+956) | 0(+0) | 0(+0) |
+ | lib/libmbedtls.a/bignum.o | 6796(+6796) | 0(+0) | 0(+0) |
+ | lib/libmbedtls.a/bignum_core.o | 3252(+3252) | 0(+0) | 0(+0) |
+ | lib/libmbedtls.a/constant_time.o | 280(+280) | 0(+0) | 8(+8) |
+ | lib/libmbedtls.a/md.o | 504(+504) | 0(+0) | 0(+0) |
+ | lib/libmbedtls.a/memory_buffer_alloc.o | 1264(+1264) | 0(+0) | 40(+40) |
+ | lib/libmbedtls.a/oid.o | 752(+752) | 0(+0) | 0(+0) |
+ | lib/libmbedtls.a/pk.o | 872(+872) | 0(+0) | 0(+0) |
+ | lib/libmbedtls.a/pk_wrap.o | 848(+848) | 0(+0) | 0(+0) |
+ | lib/libmbedtls.a/pkparse.o | 516(+516) | 0(+0) | 0(+0) |
+ | lib/libmbedtls.a/platform.o | 92(+92) | 24(+24) | 0(+0) |
+ | lib/libmbedtls.a/platform_util.o | 96(+96) | 0(+0) | 0(+0) |
+ | lib/libmbedtls.a/rsa.o | 6588(+6588) | 0(+0) | 0(+0) |
+ | lib/libmbedtls.a/rsa_alt_helpers.o | 2340(+2340) | 0(+0) | 0(+0) |
+ | lib/libmbedtls.a/sha256.o | 1448(+1448) | 0(+0) | 0(+0) |
+ | lib/libmbedtls.a/x509.o | 1028(+1028) | 0(+0) | 0(+0) |
+ | Subtotals | 69632(+69632) | 2241(+2241) | 11264(+11264) |
+ Total Static RAM memory (data + bss): 13505(+13505) bytes
+ Total Flash memory (text + data): 71873(+71873) bytes
+
+A delta between two images can be generated by passing the ``--old`` option with
+a path to the previous map file.
+
+For example:
+
+.. code::
+
+ $ poetry run memory summary ../maps/fvp-tbb-mbedtls/bl1.map --old ../maps/fvp-tbb-mbedtls/bl1.map.old -d 1
+ | Module | .text | .data | .bss |
+ |-----------|---------------|----------|--------------|
+ | [fill] | 780(-2424) | 0(+0) | 321(+224) |
+ | bl1 | 32024(+108) | 2217(+0) | 11111(+0) |
+ | lib | 45020(+10508) | 24(+0) | 1880(+1824) |
+ | Subtotals | 77824(+8192) | 2241(+0) | 13312(+2048) |
+ Total Static RAM memory (data + bss): 15553(+2048) bytes
+ Total Flash memory (text + data): 80065(+8192) bytes
+
+Note that since the old map file includes the required suffix, specifying the
+``--old`` argument is optional here.
+
+Under some circumstances, some executables are padded to meet certain
+alignments, such as a 4KB page boundary, and excluding that padding can provide
+more helpful diffs. Taking the last example, and adding the ``-e`` argument
+yields such a summary:
+
+.. code::
+
+ $ poetry run memory summary ../maps/fvp-tbb-mbedtls/bl1.map --old ../maps/fvp-tbb-mbedtls/bl1.map.old -d 1 -e
+ | Module | .text | .data | .bss |
+ |-----------|---------------|----------|--------------|
+ | bl1 | 32024(+108) | 2217(+0) | 11111(+0) |
+ | lib | 45020(+10508) | 24(+0) | 1880(+1824) |
+ | Subtotals | 77044(+10616) | 2241(+0) | 12991(+1824) |
+ Total Static RAM memory (data + bss): 15232(+1824) bytes
+ Total Flash memory (text + data): 79285(+10616) bytes
+
--------------
*Copyright (c) 2023-2025, Arm Limited. All rights reserved.*
diff --git a/drivers/arm/cci/cci.c b/drivers/arm/cci/cci.c
index ae2b9bb..8381c0d 100644
--- a/drivers/arm/cci/cci.c
+++ b/drivers/arm/cci/cci.c
@@ -31,14 +31,14 @@
static const int *cci_slave_if_map;
#if ENABLE_ASSERTIONS
-static unsigned int max_master_id;
+static size_t max_master_id;
static int cci_num_slave_ports;
static bool validate_cci_map(const int *map)
{
unsigned int valid_cci_map = 0U;
int slave_if_id;
- unsigned int i;
+ size_t i;
/* Validate the map */
for (i = 0U; i <= max_master_id; i++) {
@@ -109,7 +109,7 @@
#endif /* ENABLE_ASSERTIONS */
void __init cci_init(uintptr_t base, const int *map,
- unsigned int num_cci_masters)
+ size_t num_cci_masters)
{
assert(map != NULL);
assert(base != 0U);
@@ -130,7 +130,7 @@
assert(validate_cci_map(map));
}
-void cci_enable_snoop_dvm_reqs(unsigned int master_id)
+void cci_enable_snoop_dvm_reqs(size_t master_id)
{
int slave_if_id = cci_slave_if_map[master_id];
@@ -158,7 +158,7 @@
}
}
-void cci_disable_snoop_dvm_reqs(unsigned int master_id)
+void cci_disable_snoop_dvm_reqs(size_t master_id)
{
int slave_if_id = cci_slave_if_map[master_id];
diff --git a/drivers/arm/css/dsu/dsu.c b/drivers/arm/dsu/dsu.c
similarity index 83%
rename from drivers/arm/css/dsu/dsu.c
rename to drivers/arm/dsu/dsu.c
index f0e8df1..dea89c5 100644
--- a/drivers/arm/css/dsu/dsu.c
+++ b/drivers/arm/dsu/dsu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,7 +10,9 @@
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
-#include <drivers/arm/css/dsu.h>
+#include <drivers/arm/dsu.h>
+#include <dsu_def.h>
+#include <lib/utils_def.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
@@ -133,3 +135,30 @@
restore_dsu_pmu_state(&cluster_pmu_context[cluster_pos]);
}
+void dsu_driver_init(const dsu_driver_data_t *plat_driver_data)
+{
+ uint64_t actlr_el3 = read_actlr_el3();
+ uint64_t pwrctlr = read_clusterpwrctlr_el1();
+ uint64_t pwrdn = read_clusterpwrdn_el1();
+
+ /* enable access to power control registers. */
+ actlr_el3 |= ACTLR_EL3_PWREN_BIT;
+ write_actlr_el3(actlr_el3);
+
+ UPDATE_REG_FIELD(CLUSTERPWRCTLR_FUNCRET, pwrctlr,
+ plat_driver_data->clusterpwrctlr_funcret);
+
+ UPDATE_REG_FIELD(CLUSTERPWRCTLR_CACHEPWR, pwrctlr,
+ plat_driver_data->clusterpwrctlr_cachepwr);
+
+ write_clusterpwrctlr_el1(pwrctlr);
+
+ UPDATE_REG_FIELD(CLUSTERPWRDN_PWRDN, pwrdn,
+ plat_driver_data->clusterpwrdwn_pwrdn);
+
+ UPDATE_REG_FIELD(CLUSTERPWRDN_MEMRET, pwrdn,
+ plat_driver_data->clusterpwrdwn_memret);
+
+ write_clusterpwrdn_el1(pwrdn);
+}
+
diff --git a/drivers/arm/gic/gic.mk b/drivers/arm/gic/gic.mk
index ad30984..8b28f21 100644
--- a/drivers/arm/gic/gic.mk
+++ b/drivers/arm/gic/gic.mk
@@ -4,7 +4,7 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-GIC_REVISIONS_ := 1 2 3
+GIC_REVISIONS_ := 1 2 3 5
ifeq ($(filter $(USE_GIC_DRIVER),$(GIC_REVISIONS_)),)
$(error USE_GIC_DRIVER can only be one of $(GIC_REVISIONS_))
endif
@@ -19,6 +19,18 @@
GIC_SOURCES := ${GICV3_SOURCES} \
drivers/arm/gic/v3/gicv3_base.c \
plat/common/plat_gicv3.c
+else ifeq (${USE_GIC_DRIVER},5)
+ifneq (${ENABLE_FEAT_GCIE},1)
+$(error USE_GIC_DRIVER=5 requires ENABLE_FEAT_GCIE=1)
+endif
+$(warning GICv5 support is experimental!)
+GIC_SOURCES := drivers/arm/gicv5/gicv5_iri.c \
+ plat/common/plat_gicv5.c
+endif
+
+ifneq (${ENABLE_FEAT_GCIE},0)
+GIC_SOURCES += drivers/arm/gicv5/gicv5_cpuif.c \
+ drivers/arm/gicv5/gicv5_main.c
endif
ifeq ($(ARCH),aarch64)
diff --git a/drivers/arm/gic/v2/gicdv2_helpers.c b/drivers/arm/gic/v2/gicdv2_helpers.c
index 2f3f7f8..464bb34 100644
--- a/drivers/arm/gic/v2/gicdv2_helpers.c
+++ b/drivers/arm/gic/v2/gicdv2_helpers.c
@@ -320,7 +320,7 @@
void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
{
- uint8_t val = pri & GIC_PRI_MASK;
+ uint8_t val = (uint8_t)(pri & GIC_PRI_MASK);
mmio_write_8(base + GICD_IPRIORITYR + id, val);
}
diff --git a/drivers/arm/gicv5/gicv5_cpuif.c b/drivers/arm/gicv5/gicv5_cpuif.c
new file mode 100644
index 0000000..eb17206
--- /dev/null
+++ b/drivers/arm/gicv5/gicv5_cpuif.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/gic.h>
+#include <drivers/arm/gicv5.h>
+
+void gic_cpuif_enable(unsigned int cpu_idx)
+{
+}
+
+void gic_cpuif_disable(unsigned int cpu_idx)
+{
+}
+
+void gic_pcpu_init(unsigned int cpu_idx)
+{
+ gicv5_enable_ppis();
+}
+
+void gic_pcpu_off(unsigned int cpu_idx)
+{
+}
+
diff --git a/drivers/arm/gicv5/gicv5_iri.c b/drivers/arm/gicv5/gicv5_iri.c
new file mode 100644
index 0000000..049f3f0
--- /dev/null
+++ b/drivers/arm/gicv5/gicv5_iri.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <cdefs.h>
+#include <drivers/arm/gic.h>
+#include <drivers/arm/gicv5.h>
+
+#if USE_GIC_DRIVER != 5
+#error "This file should only be used with USE_GIC_DRIVER=5"
+#endif
+
+void __init gic_init(unsigned int cpu_idx)
+{
+ gicv5_driver_init();
+}
+
+void gic_save(void)
+{
+}
+
+void gic_resume(void)
+{
+}
diff --git a/drivers/arm/gicv5/gicv5_main.c b/drivers/arm/gicv5/gicv5_main.c
new file mode 100644
index 0000000..803a96d
--- /dev/null
+++ b/drivers/arm/gicv5/gicv5_main.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <cdefs.h>
+
+#include <arch.h>
+#include <arch_features.h>
+#include <arch_helpers.h>
+
+#include <bl31/interrupt_mgmt.h>
+#include <common/debug.h>
+#include <drivers/arm/gicv5.h>
+
+/*
+ * Check for a bad platform configuration.
+ * Not expected to be called on release builds.
+ */
+static inline bool probe_component(uintptr_t base_addr, uint8_t component)
+{
+ uint32_t aidr = read_iri_aidr(base_addr);
+
+ if (EXTRACT(IRI_AIDR_COMPONENT, aidr) != component) {
+ ERROR("GICv5 frame belongs to wrong component\n");
+ return false;
+ }
+
+ if (EXTRACT(IRI_AIDR_ARCH_MAJOR, aidr) != IRI_AIDR_ARCH_MAJOR_V5) {
+ ERROR("Bad GICv5 major version\n");
+ return false;
+ }
+
+ /* there was a bump in architecture and we've not updated the driver */
+ assert(EXTRACT(IRI_AIDR_ARCH_MINOR, aidr) == IRI_AIDR_ARCH_MINOR_P0);
+
+ return true;
+}
+
+static inline bool iwb_domain_supported(uint32_t idr0, uint8_t domain)
+{
+ return (EXTRACT(IWB_IDR0_DOMAINS, idr0) & (1U << domain)) != 0U;
+}
+
+static void iwb_configure_domainr(uintptr_t base_addr, struct gicv5_wire_props wire)
+{
+ uint32_t reg_offset = (wire.id % 16U) * 2U;
+ uint32_t reg_index = wire.id / 16U;
+ uint32_t val = read_iwb_wdomainr(base_addr, reg_index) &
+ ~(IWB_WDOMAINR_DOMAINX_MASK << reg_offset);
+
+ write_iwb_wdomainr(base_addr, reg_index, val | wire.domain << reg_offset);
+}
+
+static void iwb_configure_wtmr(uintptr_t base_addr, struct gicv5_wire_props wire)
+{
+ uint32_t reg_offset = wire.id % 32U;
+ uint32_t reg_index = wire.id / 32U;
+ uint32_t val = read_iwb_wtmr(base_addr, reg_index) & ~(1U << reg_offset);
+
+ write_iwb_wtmr(base_addr, reg_index, val | wire.tm << reg_offset);
+}
+
+static void iwb_enable(const struct gicv5_iwb *config)
+{
+ uintptr_t base_addr = config->config_frame;
+ uint32_t idr0;
+ uint16_t num_regs;
+
+ assert(probe_component(base_addr, IRI_AIDR_COMPONENT_IWB));
+
+ idr0 = read_iwb_idr0(base_addr);
+ num_regs = EXTRACT(IWB_IDR0_IWRANGE, idr0) + 1U;
+
+ /* initialise all wires as disabled */
+ for (int i = 0U; i < num_regs; i++) {
+ write_iwb_wenabler(base_addr, i, 0U);
+ }
+
+ /* default all wires to the NS domain */
+ for (int i = 0U; i < num_regs * 2; i++) {
+ write_iwb_wdomainr(base_addr, i, 0x55555555);
+ }
+
+ for (uint32_t i = 0U; i < config->num_wires; i++) {
+ assert(iwb_domain_supported(idr0, config->wires[i].domain));
+ assert(config->wires[i].id <= num_regs * 32);
+
+ iwb_configure_domainr(base_addr, config->wires[i]);
+ iwb_configure_wtmr(base_addr, config->wires[i]);
+ }
+
+ write_iwb_cr0(base_addr, IWB_CR0_IWBEN_BIT);
+ WAIT_FOR_IDLE_IWB_WENABLE_STATUSR(base_addr);
+ WAIT_FOR_IDLE_IWB_WDOMAIN_STATUSR(base_addr);
+ WAIT_FOR_IDLE_IWB_CR0(base_addr);
+}
+
+static void irs_configure_wire(uintptr_t base_addr, uint32_t wire, uint8_t domain)
+{
+ write_irs_spi_selr(base_addr, wire);
+ WAIT_FOR_VIDLE_IRS_SPI_STATUSR(base_addr);
+
+ write_irs_spi_domainr(base_addr, domain);
+ WAIT_FOR_VIDLE_IRS_SPI_STATUSR(base_addr);
+}
+
+static void irs_enable(const struct gicv5_irs *config)
+{
+ uint32_t spi_base, spi_range;
+ uintptr_t base_addr = config->el3_config_frame;
+
+ spi_base = EXTRACT(IRS_IDR7_SPI_BASE, read_irs_idr7(base_addr));
+ spi_range = EXTRACT(IRS_IDR6_SPI_IRS_RANGE, read_irs_idr6(base_addr));
+
+ assert(probe_component(base_addr, IRI_AIDR_COMPONENT_IRS));
+
+ if (spi_range == 0U) {
+ assert(config->num_spis == 0U);
+ }
+
+ /* default all wires to the NS domain */
+ for (uint32_t i = spi_base; i < spi_base + spi_range; i++) {
+ irs_configure_wire(base_addr, i, INTDMN_NS);
+ }
+
+ for (uint32_t i = 0U; i < config->num_spis; i++) {
+ assert((config->spis[i].id >= spi_base) &&
+ (config->spis[i].id < spi_base + spi_range));
+
+ irs_configure_wire(base_addr, config->spis[i].id, config->spis[i].domain);
+
+ /* don't (can't) configure TM of wires for other domains */
+ if (config->spis[i].domain == INTDMN_EL3) {
+ write_irs_spi_cfgr(base_addr, config->spis[i].tm);
+ WAIT_FOR_VIDLE_IRS_SPI_STATUSR(base_addr);
+ }
+ }
+}
+
+void __init gicv5_driver_init(void)
+{
+ for (size_t i = 0U; i < plat_gicv5_driver_data.num_iwbs; i++) {
+ iwb_enable(&plat_gicv5_driver_data.iwbs[i]);
+ }
+
+ for (size_t i = 0U; i < plat_gicv5_driver_data.num_irss; i++) {
+ irs_enable(&plat_gicv5_driver_data.irss[i]);
+ }
+}
+
+/*
+ * There exists a theoretical configuration where FEAT_RME is enabled
+ * without using TrustZone (i.e., no Secure world present). Currently,
+ * there is no reliable mechanism to detect this scenario at runtime.
+ *
+ * TODO: Add support for this configuration in the future if required.
+ */
+bool gicv5_has_interrupt_type(unsigned int type)
+{
+ switch (type) {
+ case INTR_TYPE_EL3:
+ case INTR_TYPE_S_EL1:
+ case INTR_TYPE_NS:
+ return true;
+ case INTR_TYPE_RL:
+ return is_feat_rme_supported();
+ default:
+ return false;
+ }
+}
+
+uint8_t gicv5_get_pending_interrupt_type(void)
+{
+ /* there is no pending interrupt expected */
+ return INTR_TYPE_INVAL;
+}
+
+/* TODO: these will probably end up contexted. Make Linux work for now */
+void gicv5_enable_ppis(void)
+{
+ uint64_t domainr = 0U;
+
+ /* the only ones described in the device tree at the moment */
+ write_icc_ppi_domainr(domainr, PPI_PMUIRQ, INTDMN_NS);
+ write_icc_ppi_domainr(domainr, PPI_GICMNT, INTDMN_NS);
+ write_icc_ppi_domainr(domainr, PPI_CNTHP, INTDMN_NS);
+ write_icc_ppi_domainr(domainr, PPI_CNTV, INTDMN_NS);
+ write_icc_ppi_domainr(domainr, PPI_CNTPS, INTDMN_NS);
+ write_icc_ppi_domainr(domainr, PPI_CNTP, INTDMN_NS);
+
+ write_icc_ppi_domainr0_el3(domainr);
+}
diff --git a/drivers/arm/mhu/mhu_v3_x.c b/drivers/arm/mhu/mhu_v3_x.c
index 118c608..ddeb1e6 100644
--- a/drivers/arm/mhu/mhu_v3_x.c
+++ b/drivers/arm/mhu/mhu_v3_x.c
@@ -72,7 +72,7 @@
/* Read the MHU Architecture Minor Revision */
dev->subversion =
- ((aidr & MHU_ARCH_MINOR_REV_MASK) >> MHU_ARCH_MINOR_REV_MASK);
+ ((aidr & MHU_ARCH_MINOR_REV_MASK) >> MHU_ARCH_MINOR_REV_OFF);
/* Return error if the MHU minor revision is not 0 */
if (dev->subversion != MHU_MINOR_REV_3_0) {
diff --git a/drivers/console/multi_console.c b/drivers/console/multi_console.c
index 59a4a86..89a1b87 100644
--- a/drivers/console/multi_console.c
+++ b/drivers/console/multi_console.c
@@ -11,7 +11,7 @@
#include <drivers/console.h>
console_t *console_list;
-static uint8_t console_state = CONSOLE_FLAG_BOOT;
+static uint32_t console_state = CONSOLE_FLAG_BOOT;
IMPORT_SYM(console_t *, __STACKS_START__, stacks_start)
IMPORT_SYM(console_t *, __STACKS_END__, stacks_end)
@@ -39,11 +39,12 @@
assert(to_be_deleted != NULL);
- for (ptr = &console_list; *ptr != NULL; ptr = &(*ptr)->next)
+ for (ptr = &console_list; *ptr != NULL; ptr = &(*ptr)->next) {
if (*ptr == to_be_deleted) {
*ptr = (*ptr)->next;
return to_be_deleted;
}
+ }
return NULL;
}
@@ -95,7 +96,7 @@
console_t *console;
for (console = console_list; console != NULL; console = console->next) {
- if ((console->flags & console_state) && (console->putc != NULL)) {
+ if (((console->flags & console_state) != 0U) && (console->putc != NULL)) {
int ret = do_putc(c, console);
if ((err == ERROR_NO_VALID_CONSOLE) || (ret < err)) {
err = ret;
@@ -123,7 +124,7 @@
do { /* Keep polling while at least one console works correctly. */
for (console = console_list; console != NULL;
console = console->next)
- if ((console->flags & console_state) && (console->getc != NULL)) {
+ if (((console->flags & console_state) != 0U) && (console->getc != NULL)) {
int ret = console->getc(console);
if (ret >= 0) {
return ret;
@@ -143,7 +144,7 @@
console_t *console;
for (console = console_list; console != NULL; console = console->next)
- if ((console->flags & console_state) && (console->flush != NULL)) {
+ if (((console->flags & console_state) != 0U) && (console->flush != NULL)) {
console->flush(console);
}
}
diff --git a/drivers/imx/usdhc/imx_usdhc.c b/drivers/imx/usdhc/imx_usdhc.c
index 49dfc07..7168679 100644
--- a/drivers/imx/usdhc/imx_usdhc.c
+++ b/drivers/imx/usdhc/imx_usdhc.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright 2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,10 +14,26 @@
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <drivers/mmc.h>
-#include <lib/mmio.h>
+#include <lib/mmio_poll.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
#include <imx_usdhc.h>
+/* These masks represent the commands which involve a data transfer. */
+#define ADTC_MASK_SD (BIT_32(6U) | BIT_32(17U) | BIT_32(18U) |\
+ BIT_32(24U) | BIT_32(25U))
+#define ADTC_MASK_ACMD (BIT_64(51U))
+
+#define USDHC_TIMEOUT_US (1U * 1000U) /* 1 msec */
+#define USDHC_TRANSFER_TIMEOUT (1U * 1000U * 1000U) /* 1 sec */
+
+struct imx_usdhc_device_data {
+ uint32_t addr;
+ uint32_t blk_size;
+ uint32_t blks;
+ bool valid;
+};
+
static void imx_usdhc_initialize(void);
static int imx_usdhc_send_cmd(struct mmc_cmd *cmd);
static int imx_usdhc_set_ios(unsigned int clk, unsigned int width);
@@ -34,38 +51,106 @@
};
static imx_usdhc_params_t imx_usdhc_params;
+static struct imx_usdhc_device_data imx_usdhc_data;
+
+static bool imx_usdhc_is_buf_valid(void)
+{
+ return imx_usdhc_data.valid;
+}
+
+static bool imx_usdhc_is_buf_multiblk(void)
+{
+ return imx_usdhc_data.blks > 1U;
+}
+
+static void imx_usdhc_inval_buf_data(void)
+{
+ imx_usdhc_data.valid = false;
+}
+
+static int imx_usdhc_save_buf_data(uintptr_t buf, size_t size)
+{
+ uint32_t block_size;
+ uint64_t blks;
+
+ if (size <= MMC_BLOCK_SIZE) {
+ block_size = (uint32_t)size;
+ } else {
+ block_size = MMC_BLOCK_SIZE;
+ }
+
+ if (buf > UINT32_MAX) {
+ return -EOVERFLOW;
+ }
+
+ imx_usdhc_data.addr = (uint32_t)buf;
+ imx_usdhc_data.blk_size = block_size;
+ blks = size / block_size;
+ imx_usdhc_data.blks = (uint32_t)blks;
+
+ imx_usdhc_data.valid = true;
+
+ return 0;
+}
+
+static void imx_usdhc_write_buf_data(void)
+{
+ uintptr_t reg_base = imx_usdhc_params.reg_base;
+ uint32_t addr, blks, blk_size;
+
+ addr = imx_usdhc_data.addr;
+ blks = imx_usdhc_data.blks;
+ blk_size = imx_usdhc_data.blk_size;
+
+ mmio_write_32(reg_base + DSADDR, addr);
+ mmio_write_32(reg_base + BLKATT, BLKATT_BLKCNT(blks) |
+ BLKATT_BLKSIZE(blk_size));
+}
#define IMX7_MMC_SRC_CLK_RATE (200 * 1000 * 1000)
-static void imx_usdhc_set_clk(int clk)
+static int imx_usdhc_set_clk(unsigned int clk)
{
- int div = 1;
- int pre_div = 1;
unsigned int sdhc_clk = IMX7_MMC_SRC_CLK_RATE;
uintptr_t reg_base = imx_usdhc_params.reg_base;
+ unsigned int pre_div = 1U, div = 1U;
+ uint32_t pstate;
+ int ret;
assert(clk > 0);
while (sdhc_clk / (16 * pre_div) > clk && pre_div < 256)
pre_div *= 2;
- while (sdhc_clk / div > clk && div < 16)
+ while (((sdhc_clk / (div * pre_div)) > clk) && (div < 16U)) {
div++;
+ }
pre_div >>= 1;
div -= 1;
clk = (pre_div << 8) | (div << 4);
+ ret = mmio_read_32_poll_timeout(reg_base + PSTATE, pstate,
+ (pstate & PSTATE_SDSTB) != 0U,
+ USDHC_TIMEOUT_US);
+ if (ret == -ETIMEDOUT) {
+ ERROR("Unstable SD clock\n");
+ return ret;
+ }
+
mmio_clrbits32(reg_base + VENDSPEC, VENDSPEC_CARD_CLKEN);
mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk);
udelay(10000);
mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_PER_CLKEN | VENDSPEC_CARD_CLKEN);
+
+ return 0;
}
static void imx_usdhc_initialize(void)
{
- unsigned int timeout = 10000;
uintptr_t reg_base = imx_usdhc_params.reg_base;
+ uint32_t sysctrl;
+ int ret;
assert((imx_usdhc_params.reg_base & MMC_BLOCK_MASK) == 0);
@@ -73,10 +158,12 @@
mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTA);
/* wait for reset done */
- while ((mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTA)) {
- if (!timeout)
- ERROR("IMX MMC reset timeout.\n");
- timeout--;
+ ret = mmio_read_32_poll_timeout(reg_base + SYSCTRL, sysctrl,
+ (sysctrl & SYSCTRL_RSTA) == 0U,
+ USDHC_TIMEOUT_US);
+ if (ret == -ETIMEDOUT) {
+ ERROR("Failed to reset the USDHC controller\n");
+ panic();
}
mmio_write_32(reg_base + MMCBOOT, 0);
@@ -88,7 +175,11 @@
mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_IPG_CLKEN | VENDSPEC_PER_CLKEN);
/* Set the initial boot clock rate */
- imx_usdhc_set_clk(MMC_BOOT_CLK_RATE);
+ ret = imx_usdhc_set_clk(MMC_BOOT_CLK_RATE);
+ if (ret != 0) {
+ panic();
+ }
+
udelay(100);
/* Clear read/write ready status */
@@ -105,79 +196,124 @@
mmio_clrsetbits32(reg_base + WATERMARKLEV, WMKLV_MASK, 16 | (16 << 16));
}
-#define FSL_CMD_RETRIES 1000
+static bool is_data_transfer_to_card(const struct mmc_cmd *cmd)
+{
+ unsigned int cmd_idx = cmd->cmd_idx;
+
+ return (cmd_idx == MMC_CMD(24)) || (cmd_idx == MMC_CMD(25));
+}
+
+static bool is_data_transfer_cmd(const struct mmc_cmd *cmd)
+{
+ uintptr_t reg_base = imx_usdhc_params.reg_base;
+ unsigned int cmd_idx = cmd->cmd_idx;
+ uint32_t xfer_type;
+
+ xfer_type = mmio_read_32(reg_base + XFERTYPE);
+
+ if (XFERTYPE_GET_CMD(xfer_type) == MMC_CMD(55)) {
+ return (ADTC_MASK_ACMD & BIT_64(cmd_idx)) != 0ULL;
+ }
+
+ if ((ADTC_MASK_SD & BIT_32(cmd->cmd_idx)) != 0U) {
+ return true;
+ }
+
+ return false;
+}
+
+static int get_xfr_type(const struct mmc_cmd *cmd, bool data, uint32_t *xfertype)
+{
+ *xfertype = XFERTYPE_CMD(cmd->cmd_idx);
+
+ switch (cmd->resp_type) {
+ case MMC_RESPONSE_R2:
+ *xfertype |= XFERTYPE_RSPTYP_136;
+ *xfertype |= XFERTYPE_CCCEN;
+ break;
+ case MMC_RESPONSE_R4:
+ *xfertype |= XFERTYPE_RSPTYP_48;
+ break;
+ case MMC_RESPONSE_R6:
+ *xfertype |= XFERTYPE_RSPTYP_48;
+ *xfertype |= XFERTYPE_CICEN;
+ *xfertype |= XFERTYPE_CCCEN;
+ break;
+ case MMC_RESPONSE_R1B:
+ *xfertype |= XFERTYPE_RSPTYP_48_BUSY;
+ *xfertype |= XFERTYPE_CICEN;
+ *xfertype |= XFERTYPE_CCCEN;
+ break;
+ case MMC_RESPONSE_NONE:
+ break;
+ default:
+ ERROR("Invalid CMD response: %u\n", cmd->resp_type);
+ return -EINVAL;
+ }
+
+ if (data) {
+ *xfertype |= XFERTYPE_DPSEL;
+ }
+
+ return 0;
+}
static int imx_usdhc_send_cmd(struct mmc_cmd *cmd)
{
uintptr_t reg_base = imx_usdhc_params.reg_base;
- unsigned int xfertype = 0, mixctl = 0, multiple = 0, data = 0, err = 0;
- unsigned int state, flags = INTSTATEN_CC | INTSTATEN_CTOE;
- unsigned int cmd_retries = 0;
+ unsigned int flags = INTSTATEN_CC | INTSTATEN_CTOE;
+ uint32_t xfertype, pstate, intstat, sysctrl;
+ unsigned int mixctl = 0;
+ int err = 0, ret;
+ bool data;
assert(cmd);
+ data = is_data_transfer_cmd(cmd);
+
+ err = get_xfr_type(cmd, data, &xfertype);
+ if (err != 0) {
+ return err;
+ }
+
/* clear all irq status */
mmio_write_32(reg_base + INTSTAT, 0xffffffff);
/* Wait for the bus to be idle */
- do {
- state = mmio_read_32(reg_base + PSTATE);
- } while (state & (PSTATE_CDIHB | PSTATE_CIHB));
+ err = mmio_read_32_poll_timeout(reg_base + PSTATE, pstate,
+ (pstate & (PSTATE_CDIHB | PSTATE_CIHB)) == 0U,
+ USDHC_TIMEOUT_US);
+ if (err == -ETIMEDOUT) {
+ ERROR("Failed to wait an idle bus\n");
+ return err;
+ }
- while (mmio_read_32(reg_base + PSTATE) & PSTATE_DLA)
- ;
+ err = mmio_read_32_poll_timeout(reg_base + PSTATE, pstate,
+ (pstate & PSTATE_DLA) == 0U,
+ USDHC_TIMEOUT_US);
+ if (err == -ETIMEDOUT) {
+ ERROR("Active data line during the uSDHC init\n");
+ return err;
+ }
mmio_write_32(reg_base + INTSIGEN, 0);
- udelay(1000);
-
- switch (cmd->cmd_idx) {
- case MMC_CMD(12):
- xfertype |= XFERTYPE_CMDTYP_ABORT;
- break;
- case MMC_CMD(18):
- multiple = 1;
- /* for read op */
- /* fallthrough */
- case MMC_CMD(17):
- case MMC_CMD(8):
- mixctl |= MIXCTRL_DTDSEL;
- data = 1;
- break;
- case MMC_CMD(25):
- multiple = 1;
- /* for data op flag */
- /* fallthrough */
- case MMC_CMD(24):
- data = 1;
- break;
- default:
- break;
- }
-
- if (multiple) {
- mixctl |= MIXCTRL_MSBSEL;
- mixctl |= MIXCTRL_BCEN;
- }
if (data) {
- xfertype |= XFERTYPE_DPSEL;
mixctl |= MIXCTRL_DMAEN;
}
- if (cmd->resp_type & MMC_RSP_48 && cmd->resp_type != MMC_RESPONSE_R2)
- xfertype |= XFERTYPE_RSPTYP_48;
- else if (cmd->resp_type & MMC_RSP_136)
- xfertype |= XFERTYPE_RSPTYP_136;
- else if (cmd->resp_type & MMC_RSP_BUSY)
- xfertype |= XFERTYPE_RSPTYP_48_BUSY;
+ if (!is_data_transfer_to_card(cmd)) {
+ mixctl |= MIXCTRL_DTDSEL;
+ }
- if (cmd->resp_type & MMC_RSP_CMD_IDX)
- xfertype |= XFERTYPE_CICEN;
+ if ((cmd->cmd_idx != MMC_CMD(55)) && imx_usdhc_is_buf_valid()) {
+ if (imx_usdhc_is_buf_multiblk()) {
+ mixctl |= MIXCTRL_MSBSEL | MIXCTRL_BCEN;
+ }
- if (cmd->resp_type & MMC_RSP_CRC)
- xfertype |= XFERTYPE_CCCEN;
-
- xfertype |= XFERTYPE_CMD(cmd->cmd_idx);
+ imx_usdhc_write_buf_data();
+ imx_usdhc_inval_buf_data();
+ }
/* Send the command */
mmio_write_32(reg_base + CMDARG, cmd->cmd_arg);
@@ -185,19 +321,15 @@
mmio_write_32(reg_base + XFERTYPE, xfertype);
/* Wait for the command done */
- do {
- state = mmio_read_32(reg_base + INTSTAT);
- if (cmd_retries)
- udelay(1);
- } while ((!(state & flags)) && ++cmd_retries < FSL_CMD_RETRIES);
-
- if ((state & (INTSTATEN_CTOE | CMD_ERR)) || cmd_retries == FSL_CMD_RETRIES) {
- if (cmd_retries == FSL_CMD_RETRIES)
- err = -ETIMEDOUT;
- else
+ err = mmio_read_32_poll_timeout(reg_base + INTSTAT, intstat,
+ (intstat & flags) != 0U,
+ USDHC_TIMEOUT_US);
+ if ((err == -ETIMEDOUT) || ((intstat & (INTSTATEN_CTOE | CMD_ERR)) != 0U)) {
+ if ((intstat & (INTSTATEN_CTOE | CMD_ERR)) != 0U) {
err = -EIO;
+ }
ERROR("imx_usdhc mmc cmd %d state 0x%x errno=%d\n",
- cmd->cmd_idx, state, err);
+ cmd->cmd_idx, intstat, err);
goto out;
}
@@ -220,28 +352,41 @@
/* Wait until all of the blocks are transferred */
if (data) {
flags = DATA_COMPLETE;
- do {
- state = mmio_read_32(reg_base + INTSTAT);
+ err = mmio_read_32_poll_timeout(reg_base + INTSTAT, intstat,
+ (((intstat & (INTSTATEN_DTOE | DATA_ERR)) != 0U) ||
+ ((intstat & flags) == flags)),
+ USDHC_TRANSFER_TIMEOUT);
+ if ((intstat & (INTSTATEN_DTOE | DATA_ERR)) != 0U) {
+ err = -EIO;
+ ERROR("imx_usdhc mmc data state 0x%x\n", intstat);
+ goto out;
+ }
- if (state & (INTSTATEN_DTOE | DATA_ERR)) {
- err = -EIO;
- ERROR("imx_usdhc mmc data state 0x%x\n", state);
- goto out;
- }
- } while ((state & flags) != flags);
+ if (err == -ETIMEDOUT) {
+ ERROR("Timeout in block transfer\n");
+ goto out;
+ }
}
out:
/* Reset CMD and DATA on error */
if (err) {
mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTC);
- while (mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTC)
- ;
+ ret = mmio_read_32_poll_timeout(reg_base + SYSCTRL, sysctrl,
+ (sysctrl & SYSCTRL_RSTC) == 0U,
+ USDHC_TIMEOUT_US);
+ if (ret == -ETIMEDOUT) {
+ ERROR("Failed to reset the CMD line\n");
+ }
if (data) {
mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTD);
- while (mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTD)
- ;
+ ret = mmio_read_32_poll_timeout(reg_base + SYSCTRL, sysctrl,
+ (sysctrl & SYSCTRL_RSTD) == 0U,
+ USDHC_TIMEOUT_US);
+ if (ret == -ETIMEDOUT) {
+ ERROR("Failed to reset the data line\n");
+ }
}
}
@@ -254,8 +399,12 @@
static int imx_usdhc_set_ios(unsigned int clk, unsigned int width)
{
uintptr_t reg_base = imx_usdhc_params.reg_base;
+ int ret;
- imx_usdhc_set_clk(clk);
+ ret = imx_usdhc_set_clk(clk);
+ if (ret != 0) {
+ return ret;
+ }
if (width == MMC_BUS_WIDTH_4)
mmio_clrsetbits32(reg_base + PROTCTRL, PROTCTRL_WIDTH_MASK,
@@ -269,17 +418,13 @@
static int imx_usdhc_prepare(int lba, uintptr_t buf, size_t size)
{
- uintptr_t reg_base = imx_usdhc_params.reg_base;
-
- mmio_write_32(reg_base + DSADDR, buf);
- mmio_write_32(reg_base + BLKATT,
- (size / MMC_BLOCK_SIZE) << 16 | MMC_BLOCK_SIZE);
-
- return 0;
+ flush_dcache_range(buf, size);
+ return imx_usdhc_save_buf_data(buf, size);
}
static int imx_usdhc_read(int lba, uintptr_t buf, size_t size)
{
+ inv_dcache_range(buf, size);
return 0;
}
@@ -291,13 +436,24 @@
void imx_usdhc_init(imx_usdhc_params_t *params,
struct mmc_device_info *mmc_dev_info)
{
+ int ret __maybe_unused;
+
assert((params != 0) &&
((params->reg_base & MMC_BLOCK_MASK) == 0) &&
- (params->clk_rate > 0) &&
((params->bus_width == MMC_BUS_WIDTH_1) ||
(params->bus_width == MMC_BUS_WIDTH_4) ||
(params->bus_width == MMC_BUS_WIDTH_8)));
+#if PLAT_XLAT_TABLES_DYNAMIC
+ ret = mmap_add_dynamic_region(params->reg_base, params->reg_base,
+ PAGE_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE);
+ if (ret != 0) {
+ ERROR("Failed to map the uSDHC registers\n");
+ panic();
+ }
+#endif
+
memcpy(&imx_usdhc_params, params, sizeof(imx_usdhc_params_t));
mmc_init(&imx_usdhc_ops, params->clk_rate, params->bus_width,
params->flags, mmc_dev_info);
diff --git a/drivers/imx/usdhc/imx_usdhc.h b/drivers/imx/usdhc/imx_usdhc.h
index e063316..bb0ef01 100644
--- a/drivers/imx/usdhc/imx_usdhc.h
+++ b/drivers/imx/usdhc/imx_usdhc.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright 2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,8 +12,8 @@
typedef struct imx_usdhc_params {
uintptr_t reg_base;
- int clk_rate;
- int bus_width;
+ unsigned int clk_rate;
+ unsigned int bus_width;
unsigned int flags;
} imx_usdhc_params_t;
@@ -20,115 +21,119 @@
struct mmc_device_info *mmc_dev_info);
/* iMX MMC registers definition */
-#define DSADDR 0x000
-#define BLKATT 0x004
-#define CMDARG 0x008
-#define CMDRSP0 0x010
-#define CMDRSP1 0x014
-#define CMDRSP2 0x018
-#define CMDRSP3 0x01c
+#define DSADDR 0x000U
+#define BLKATT 0x004U
+#define BLKATT_BLKCNT(x) (((x) << 16U) & GENMASK_32(31U, 16U))
+#define BLKATT_BLKSIZE(x) ((x) & GENMASK_32(12U, 0U))
+#define CMDARG 0x008U
+#define CMDRSP0 0x010U
+#define CMDRSP1 0x014U
+#define CMDRSP2 0x018U
+#define CMDRSP3 0x01cU
-#define XFERTYPE 0x00c
-#define XFERTYPE_CMD(x) (((x) & 0x3f) << 24)
-#define XFERTYPE_CMDTYP_ABORT (3 << 22)
-#define XFERTYPE_DPSEL BIT(21)
-#define XFERTYPE_CICEN BIT(20)
-#define XFERTYPE_CCCEN BIT(19)
-#define XFERTYPE_RSPTYP_136 BIT(16)
-#define XFERTYPE_RSPTYP_48 BIT(17)
-#define XFERTYPE_RSPTYP_48_BUSY (BIT(16) | BIT(17))
+#define XFERTYPE 0x00cU
+#define XFERTYPE_CMD(x) (((x) & 0x3fU) << 24U)
+#define XFERTYPE_GET_CMD(x) (((x) & GENMASK_32(29U, 24U)) >> 24U)
+#define XFERTYPE_CMDTYP_ABORT (3U << 22U)
+#define XFERTYPE_DPSEL BIT_32(21U)
+#define XFERTYPE_CICEN BIT_32(20U)
+#define XFERTYPE_CCCEN BIT_32(19U)
+#define XFERTYPE_RSPTYP_136 BIT_32(16U)
+#define XFERTYPE_RSPTYP_48 BIT_32(17U)
+#define XFERTYPE_RSPTYP_48_BUSY (BIT_32(16U) | BIT_32(17U))
-#define PSTATE 0x024
-#define PSTATE_DAT0 BIT(24)
-#define PSTATE_DLA BIT(2)
-#define PSTATE_CDIHB BIT(1)
-#define PSTATE_CIHB BIT(0)
+#define PSTATE 0x024U
+#define PSTATE_DAT0 BIT_32(24U)
+#define PSTATE_SDSTB BIT_32(3U)
+#define PSTATE_DLA BIT_32(2U)
+#define PSTATE_CDIHB BIT_32(1U)
+#define PSTATE_CIHB BIT_32(0U)
-#define PROTCTRL 0x028
-#define PROTCTRL_LE BIT(5)
-#define PROTCTRL_WIDTH_4 BIT(1)
-#define PROTCTRL_WIDTH_8 BIT(2)
-#define PROTCTRL_WIDTH_MASK 0x6
+#define PROTCTRL 0x028U
+#define PROTCTRL_LE BIT_32(5U)
+#define PROTCTRL_WIDTH_4 BIT_32(1U)
+#define PROTCTRL_WIDTH_8 BIT_32(2U)
+#define PROTCTRL_WIDTH_MASK 0x6U
-#define SYSCTRL 0x02c
-#define SYSCTRL_RSTD BIT(26)
-#define SYSCTRL_RSTC BIT(25)
-#define SYSCTRL_RSTA BIT(24)
-#define SYSCTRL_CLOCK_MASK 0x0000fff0
-#define SYSCTRL_TIMEOUT_MASK 0x000f0000
-#define SYSCTRL_TIMEOUT(x) ((0xf & (x)) << 16)
+#define SYSCTRL 0x02cU
+#define SYSCTRL_RSTD BIT_32(26U)
+#define SYSCTRL_RSTC BIT_32(25U)
+#define SYSCTRL_RSTA BIT_32(24U)
+#define SYSCTRL_CLOCK_MASK GENMASK_32(15U, 4U)
+#define SYSCTRL_TIMEOUT_MASK GENMASK_32(19U, 16U)
+#define SYSCTRL_TIMEOUT(x) ((0xfU & (x)) << 16U)
-#define INTSTAT 0x030
-#define INTSTAT_DMAE BIT(28)
-#define INTSTAT_DEBE BIT(22)
-#define INTSTAT_DCE BIT(21)
-#define INTSTAT_DTOE BIT(20)
-#define INTSTAT_CIE BIT(19)
-#define INTSTAT_CEBE BIT(18)
-#define INTSTAT_CCE BIT(17)
-#define INTSTAT_DINT BIT(3)
-#define INTSTAT_BGE BIT(2)
-#define INTSTAT_TC BIT(1)
-#define INTSTAT_CC BIT(0)
+#define INTSTAT 0x030U
+#define INTSTAT_DMAE BIT_32(28U)
+#define INTSTAT_DEBE BIT_32(22U)
+#define INTSTAT_DCE BIT_32(21U)
+#define INTSTAT_DTOE BIT_32(20U)
+#define INTSTAT_CIE BIT_32(19U)
+#define INTSTAT_CEBE BIT_32(18U)
+#define INTSTAT_CCE BIT_32(17U)
+#define INTSTAT_DINT BIT_32(3U)
+#define INTSTAT_BGE BIT_32(2U)
+#define INTSTAT_TC BIT_32(1U)
+#define INTSTAT_CC BIT_32(0U)
#define CMD_ERR (INTSTAT_CIE | INTSTAT_CEBE | INTSTAT_CCE)
#define DATA_ERR (INTSTAT_DMAE | INTSTAT_DEBE | INTSTAT_DCE | \
INTSTAT_DTOE)
#define DATA_COMPLETE (INTSTAT_DINT | INTSTAT_TC)
-#define INTSTATEN 0x034
-#define INTSTATEN_DEBE BIT(22)
-#define INTSTATEN_DCE BIT(21)
-#define INTSTATEN_DTOE BIT(20)
-#define INTSTATEN_CIE BIT(19)
-#define INTSTATEN_CEBE BIT(18)
-#define INTSTATEN_CCE BIT(17)
-#define INTSTATEN_CTOE BIT(16)
-#define INTSTATEN_CINT BIT(8)
-#define INTSTATEN_BRR BIT(5)
-#define INTSTATEN_BWR BIT(4)
-#define INTSTATEN_DINT BIT(3)
-#define INTSTATEN_TC BIT(1)
-#define INTSTATEN_CC BIT(0)
+#define INTSTATEN 0x034U
+#define INTSTATEN_DEBE BIT_32(22U)
+#define INTSTATEN_DCE BIT_32(21U)
+#define INTSTATEN_DTOE BIT_32(20U)
+#define INTSTATEN_CIE BIT_32(19U)
+#define INTSTATEN_CEBE BIT_32(18U)
+#define INTSTATEN_CCE BIT_32(17U)
+#define INTSTATEN_CTOE BIT_32(16U)
+#define INTSTATEN_CINT BIT_32(8U)
+#define INTSTATEN_BRR BIT_32(5U)
+#define INTSTATEN_BWR BIT_32(4U)
+#define INTSTATEN_DINT BIT_32(3U)
+#define INTSTATEN_TC BIT_32(1U)
+#define INTSTATEN_CC BIT_32(0U)
#define EMMC_INTSTATEN_BITS (INTSTATEN_CC | INTSTATEN_TC | INTSTATEN_DINT | \
INTSTATEN_BWR | INTSTATEN_BRR | INTSTATEN_CINT | \
INTSTATEN_CTOE | INTSTATEN_CCE | INTSTATEN_CEBE | \
INTSTATEN_CIE | INTSTATEN_DTOE | INTSTATEN_DCE | \
INTSTATEN_DEBE)
-#define INTSIGEN 0x038
+#define INTSIGEN 0x038U
-#define WATERMARKLEV 0x044
-#define WMKLV_RD_MASK 0xff
-#define WMKLV_WR_MASK 0x00ff0000
+#define WATERMARKLEV 0x044U
+#define WMKLV_RD_MASK GENMASK_32(7U, 0U)
+#define WMKLV_WR_MASK GENMASK_32(23U, 16U)
#define WMKLV_MASK (WMKLV_RD_MASK | WMKLV_WR_MASK)
-#define MIXCTRL 0x048
-#define MIXCTRL_MSBSEL BIT(5)
-#define MIXCTRL_DTDSEL BIT(4)
-#define MIXCTRL_DDREN BIT(3)
-#define MIXCTRL_AC12EN BIT(2)
-#define MIXCTRL_BCEN BIT(1)
-#define MIXCTRL_DMAEN BIT(0)
-#define MIXCTRL_DATMASK 0x7f
+#define MIXCTRL 0x048U
+#define MIXCTRL_MSBSEL BIT_32(5U)
+#define MIXCTRL_DTDSEL BIT_32(4U)
+#define MIXCTRL_DDREN BIT_32(3U)
+#define MIXCTRL_AC12EN BIT_32(2U)
+#define MIXCTRL_BCEN BIT_32(1U)
+#define MIXCTRL_DMAEN BIT_32(0U)
+#define MIXCTRL_DATMASK 0x7fU
-#define DLLCTRL 0x060
+#define DLLCTRL 0x060U
-#define CLKTUNECTRLSTS 0x068
+#define CLKTUNECTRLSTS 0x068U
-#define VENDSPEC 0x0c0
-#define VENDSPEC_RSRV1 BIT(29)
-#define VENDSPEC_CARD_CLKEN BIT(14)
-#define VENDSPEC_PER_CLKEN BIT(13)
-#define VENDSPEC_AHB_CLKEN BIT(12)
-#define VENDSPEC_IPG_CLKEN BIT(11)
-#define VENDSPEC_AC12_CHKBUSY BIT(3)
-#define VENDSPEC_EXTDMA BIT(0)
+#define VENDSPEC 0x0c0U
+#define VENDSPEC_RSRV1 BIT_32(29U)
+#define VENDSPEC_CARD_CLKEN BIT_32(14U)
+#define VENDSPEC_PER_CLKEN BIT_32(13U)
+#define VENDSPEC_AHB_CLKEN BIT_32(12U)
+#define VENDSPEC_IPG_CLKEN BIT_32(11U)
+#define VENDSPEC_AC12_CHKBUSY BIT_32(3U)
+#define VENDSPEC_EXTDMA BIT_32(0U)
#define VENDSPEC_INIT (VENDSPEC_RSRV1 | VENDSPEC_CARD_CLKEN | \
VENDSPEC_PER_CLKEN | VENDSPEC_AHB_CLKEN | \
VENDSPEC_IPG_CLKEN | VENDSPEC_AC12_CHKBUSY | \
VENDSPEC_EXTDMA)
-#define MMCBOOT 0x0c4
+#define MMCBOOT 0x0c4U
#define mmio_clrsetbits32(addr, clear, set) mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set))
#define mmio_clrbits32(addr, clear) mmio_write_32(addr, mmio_read_32(addr) & ~(clear))
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index b51e744..93a958c 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -437,7 +437,7 @@
int ret;
/* CMD0: reset to IDLE */
- ret = mmc_send_cmd(MMC_CMD(0), 0, 0, NULL);
+ ret = mmc_send_cmd(MMC_CMD(0), 0, MMC_RESPONSE_NONE, NULL);
if (ret != 0) {
return ret;
}
diff --git a/drivers/nxp/crypto/caam/src/hw_key_blob.c b/drivers/nxp/crypto/caam/src/hw_key_blob.c
index 6bcb6ba..0ac750d 100644
--- a/drivers/nxp/crypto/caam/src/hw_key_blob.c
+++ b/drivers/nxp/crypto/caam/src/hw_key_blob.c
@@ -43,6 +43,10 @@
struct job_descriptor *jobdesc = &desc;
uint32_t in_sz = 16U;
+ if (size <= 0 || size > 16) {
+ ERROR("Error: Requested invalid length of HUK.\n");
+ return -1;
+ }
/* Output blob will have 32 bytes key blob in beginning and
* 16 byte HMAC identifier at end of data blob
*/
diff --git a/drivers/nxp/crypto/caam/src/rng.c b/drivers/nxp/crypto/caam/src/rng.c
index 58430db..0331040 100644
--- a/drivers/nxp/crypto/caam/src/rng.c
+++ b/drivers/nxp/crypto/caam/src/rng.c
@@ -41,7 +41,7 @@
if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED) {
*state_handle = 0;
ret_code = 1;
- } else if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED) {
+ } else if (rdsta & RNG_STATE1_HANDLE_INSTANTIATED) {
*state_handle = 1;
ret_code = 1;
}
diff --git a/drivers/st/bsec/bsec3.c b/drivers/st/bsec/bsec3.c
index 3fdaf16..03d8928 100644
--- a/drivers/st/bsec/bsec3.c
+++ b/drivers/st/bsec/bsec3.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -30,18 +30,6 @@
#define BSEC_OTP_BANK_SHIFT U(5)
#define BSEC_TIMEOUT_VALUE U(0x800000) /* ~7sec @1.2GHz */
-/* Magic use to indicated valid SHADOW = 'B' 'S' 'E' 'C' */
-#define BSEC_MAGIC U(0x42534543)
-
-#define OTP_MAX_SIZE (STM32MP2_OTP_MAX_ID + U(1))
-
-struct bsec_shadow {
- uint32_t magic;
- uint32_t state;
- uint32_t value[OTP_MAX_SIZE];
- uint32_t status[OTP_MAX_SIZE];
-};
-
static uint32_t otp_bank(uint32_t otp)
{
if (otp > STM32MP2_OTP_MAX_ID) {
@@ -167,7 +155,7 @@
ERROR("BSEC reset critical error 0x%x\n", status);
panic();
}
- if ((status & BSEC_OTPSR_FUSEOK) != BSEC_OTPSR_FUSEOK) {
+ if ((status & BSEC_OTPSR_INIT_DONE) != BSEC_OTPSR_INIT_DONE) {
ERROR("BSEC reset critical error 0x%x\n", status);
panic();
}
@@ -467,8 +455,8 @@
uint32_t status = bsec_get_status();
uint32_t bsec_sr = mmio_read_32(BSEC_BASE + BSEC_SR);
- if ((status & BSEC_OTPSR_FUSEOK) == BSEC_OTPSR_FUSEOK) {
- /* NVSTATE is only valid if FUSEOK */
+ if ((status & BSEC_OTPSR_INIT_DONE) == BSEC_OTPSR_INIT_DONE) {
+ /* NVSTATE is only valid if INIT_DONE */
uint32_t nvstates = (bsec_sr & BSEC_SR_NVSTATE_MASK) >> BSEC_SR_NVSTATE_SHIFT;
if (nvstates == BSEC_SR_NVSTATE_OPEN) {
diff --git a/drivers/st/clk/clk-stm32mp2.c b/drivers/st/clk/clk-stm32mp2.c
index 12839f1..1266e00 100644
--- a/drivers/st/clk/clk-stm32mp2.c
+++ b/drivers/st/clk/clk-stm32mp2.c
@@ -105,7 +105,9 @@
_SPDIFSYMB,
_CK_PLL1,
_CK_PLL2,
+#if !STM32MP21
_CK_PLL3,
+#endif /* !STM32MP21 */
_CK_PLL4,
_CK_PLL5,
_CK_PLL6,
@@ -180,6 +182,9 @@
_CK_ICN_APB2,
_CK_ICN_APB3,
_CK_ICN_APB4,
+#if STM32MP21
+ _CK_ICN_APB5,
+#endif /* STM32MP21 */
_CK_ICN_APBDBG,
_CK_BKPSRAM,
_CK_BSEC,
@@ -200,51 +205,82 @@
_CK_GPIOG,
_CK_GPIOH,
_CK_GPIOI,
+#if !STM32MP21
_CK_GPIOJ,
_CK_GPIOK,
+#endif /* !STM32MP21 */
_CK_GPIOZ,
+#if STM32MP21
+ _CK_HASH1,
+ _CK_HASH2,
+#else /* STM32MP21 */
_CK_HASH,
+#endif /* STM32MP21 */
_CK_I2C1,
_CK_I2C2,
+#if !STM32MP23
_CK_I2C3,
+#endif /* !STM32MP23 */
+#if STM32MP25
_CK_I2C4,
_CK_I2C5,
_CK_I2C6,
+#endif /* STM32MP25 */
+#if !STM32MP21
_CK_I2C7,
_CK_I2C8,
+#endif /* !STM32MP21 */
_CK_IWDG1,
_CK_IWDG2,
_CK_OSPI1,
+#if !STM32MP21
_CK_OSPI2,
_CK_OSPIIOM,
+#endif /* !STM32MP21 */
_CK_PKA,
_CK_RETRAM,
+#if STM32MP21
+ _CK_RNG1,
+ _CK_RNG2,
+#else /* STM32MP21 */
_CK_RNG,
+#endif /* STM32MP21 */
_CK_RTC,
_CK_SAES,
_CK_SDMMC1,
_CK_SDMMC2,
_CK_SRAM1,
+#if !STM32MP21
_CK_SRAM2,
+#endif /* !STM32MP21 */
_CK_STGEN,
_CK_SYSCPU1,
_CK_SYSRAM,
_CK_UART4,
_CK_UART5,
_CK_UART7,
+#if STM32MP25
_CK_UART8,
_CK_UART9,
+#endif /* STM32MP25 */
_CK_USART1,
_CK_USART2,
_CK_USART3,
_CK_USART6,
+#if STM32MP21
+ _CK_USBHEHCI,
+ _CK_USBHOHCI,
+#else /* STM32MP21 */
_CK_USB2EHCI,
_CK_USB2OHCI,
+#endif /* STM32MP21 */
_CK_USB2PHY1,
_CK_USB2PHY2,
+#if !STM32MP21
_CK_USB3DR,
_CK_USB3PCIEPHY,
_CK_USBTC,
+#endif /* !STM32MP21 */
CK_LAST
};
@@ -271,6 +307,7 @@
_CK_FLEXGEN_58, _CK_HSE
};
+#if !STM32MP21
static const uint16_t usb3pciphy_src[] = {
_CK_FLEXGEN_34, _CK_HSE
};
@@ -278,6 +315,7 @@
static const uint16_t d3per_src[] = {
_CK_MSI, _CK_LSI, _CK_LSE
};
+#endif /* !STM32MP21 */
#define MUX_CONF(id, src, _offset, _shift, _witdh)[id] = {\
.id_parents = src,\
@@ -290,7 +328,7 @@
},\
}
-static const struct parent_cfg parent_mp25[] = {
+static const struct parent_cfg parent_mp2[] = {
MUX_CONF(MUX_MUXSEL0, muxsel_src, RCC_MUXSELCFGR, 0, 2),
MUX_CONF(MUX_MUXSEL1, muxsel_src, RCC_MUXSELCFGR, 4, 2),
MUX_CONF(MUX_MUXSEL2, muxsel_src, RCC_MUXSELCFGR, 8, 2),
@@ -303,8 +341,10 @@
MUX_CONF(MUX_RTC, rtc_src, RCC_BDCR, 16, 2),
MUX_CONF(MUX_USB2PHY1, usb2phy1_src, RCC_USB2PHY1CFGR, 15, 1),
MUX_CONF(MUX_USB2PHY2, usb2phy2_src, RCC_USB2PHY2CFGR, 15, 1),
+#if !STM32MP21
MUX_CONF(MUX_USB3PCIEPHY, usb3pciphy_src, RCC_USB3PCIEPHYCFGR, 15, 1),
MUX_CONF(MUX_D3PER, d3per_src, RCC_D3DCR, 16, 2),
+#endif /* !STM32MP21 */
};
/* GATES */
@@ -324,15 +364,26 @@
GATE_SYSRAM,
GATE_RETRAM,
GATE_SRAM1,
+#if !STM32MP21
GATE_SRAM2,
+#endif /* !STM32MP21 */
GATE_DDRPHYC,
GATE_SYSCPU1,
GATE_CRC,
+#if !STM32MP21
GATE_OSPIIOM,
+#endif /* !STM32MP21 */
GATE_BKPSRAM,
+#if STM32MP21
+ GATE_HASH1,
+ GATE_HASH2,
+ GATE_RNG1,
+ GATE_RNG2,
+#else /* STM32MP21 */
GATE_HASH,
GATE_RNG,
+#endif /* STM32MP21 */
GATE_CRYP1,
GATE_CRYP2,
GATE_SAES,
@@ -347,18 +398,27 @@
GATE_GPIOG,
GATE_GPIOH,
GATE_GPIOI,
+#if !STM32MP21
GATE_GPIOJ,
GATE_GPIOK,
+#endif /* !STM32MP21 */
GATE_GPIOZ,
GATE_RTC,
GATE_DDRCP,
/* WARNING 2 CLOCKS FOR ONE GATE */
+#if STM32MP21
+ GATE_USBHOHCI,
+ GATE_USBHEHCI,
+#else /* STM32MP21 */
GATE_USB2OHCI,
GATE_USB2EHCI,
+#endif /* STM32MP21 */
+#if !STM32MP21
GATE_USB3DR,
+#endif /* !STM32MP21 */
GATE_BSEC,
GATE_IWDG1,
@@ -373,22 +433,34 @@
GATE_UART5,
GATE_I2C1,
GATE_I2C2,
+#if !STM32MP23
GATE_I2C3,
+#endif /* !STM32MP23 */
+#if STM32MP25
GATE_I2C5,
GATE_I2C4,
GATE_I2C6,
+#endif /* STM32MP25 */
+#if !STM32MP21
GATE_I2C7,
+#endif /* !STM32MP21 */
GATE_USART1,
GATE_USART6,
GATE_UART7,
+#if STM32MP25
GATE_UART8,
GATE_UART9,
+#endif /* STM32MP25 */
GATE_STGEN,
+#if !STM32MP21
GATE_USB3PCIEPHY,
GATE_USBTC,
GATE_I2C8,
+#endif /* !STM32MP21 */
GATE_OSPI1,
+#if !STM32MP21
GATE_OSPI2,
+#endif /* !STM32MP21 */
GATE_FMC,
GATE_SDMMC1,
GATE_SDMMC2,
@@ -403,30 +475,57 @@
.set_clr = (_offset_clr),\
}
-static const struct gate_cfg gates_mp25[LAST_GATE] = {
+static const struct gate_cfg gates_mp2[LAST_GATE] = {
GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0),
+#if STM32MP21
+ GATE_CFG(GATE_LSI, RCC_LSICR, 0, 0),
+#else /* STM32MP21 */
GATE_CFG(GATE_LSI, RCC_BDCR, 9, 0),
+#endif /* STM32MP21 */
GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0),
GATE_CFG(GATE_HSI, RCC_OCENSETR, 0, 1),
GATE_CFG(GATE_HSE, RCC_OCENSETR, 8, 1),
+#if STM32MP21
+ GATE_CFG(GATE_MSI, RCC_OCENSETR, 2, 0),
+#else /* STM32MP21 */
GATE_CFG(GATE_MSI, RCC_D3DCR, 0, 0),
+#endif /* STM32MP21 */
+#if STM32MP21
+ GATE_CFG(GATE_LSI_RDY, RCC_LSICR, 1, 0),
+#else /* STM32MP21 */
GATE_CFG(GATE_LSI_RDY, RCC_BDCR, 10, 0),
+#endif /* STM32MP21 */
GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0),
+#if STM32MP21
+ GATE_CFG(GATE_MSI_RDY, RCC_OCRDYR, 2, 0),
+#else /* STM32MP21 */
GATE_CFG(GATE_MSI_RDY, RCC_D3DCR, 2, 0),
+#endif /* STM32MP21 */
GATE_CFG(GATE_HSE_RDY, RCC_OCRDYR, 8, 0),
GATE_CFG(GATE_HSI_RDY, RCC_OCRDYR, 0, 0),
GATE_CFG(GATE_SYSRAM, RCC_SYSRAMCFGR, 1, 0),
GATE_CFG(GATE_RETRAM, RCC_RETRAMCFGR, 1, 0),
GATE_CFG(GATE_SRAM1, RCC_SRAM1CFGR, 1, 0),
+#if !STM32MP21
GATE_CFG(GATE_SRAM2, RCC_SRAM2CFGR, 1, 0),
+#endif /* !STM32MP21 */
GATE_CFG(GATE_DDRPHYC, RCC_DDRPHYCAPBCFGR, 1, 0),
GATE_CFG(GATE_SYSCPU1, RCC_SYSCPU1CFGR, 1, 0),
GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0),
+#if !STM32MP21
GATE_CFG(GATE_OSPIIOM, RCC_OSPIIOMCFGR, 1, 0),
+#endif /* !STM32MP21 */
GATE_CFG(GATE_BKPSRAM, RCC_BKPSRAMCFGR, 1, 0),
+#if STM32MP21
+ GATE_CFG(GATE_HASH1, RCC_HASH1CFGR, 1, 0),
+ GATE_CFG(GATE_HASH2, RCC_HASH2CFGR, 1, 0),
+ GATE_CFG(GATE_RNG1, RCC_RNG1CFGR, 1, 0),
+ GATE_CFG(GATE_RNG2, RCC_RNG2CFGR, 1, 0),
+#else /* STM32MP21 */
GATE_CFG(GATE_HASH, RCC_HASHCFGR, 1, 0),
GATE_CFG(GATE_RNG, RCC_RNGCFGR, 1, 0),
+#endif /* STM32MP21 */
GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0),
GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0),
GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0),
@@ -440,16 +539,23 @@
GATE_CFG(GATE_GPIOG, RCC_GPIOGCFGR, 1, 0),
GATE_CFG(GATE_GPIOH, RCC_GPIOHCFGR, 1, 0),
GATE_CFG(GATE_GPIOI, RCC_GPIOICFGR, 1, 0),
+#if !STM32MP21
GATE_CFG(GATE_GPIOJ, RCC_GPIOJCFGR, 1, 0),
GATE_CFG(GATE_GPIOK, RCC_GPIOKCFGR, 1, 0),
+#endif /* !STM32MP21 */
GATE_CFG(GATE_GPIOZ, RCC_GPIOZCFGR, 1, 0),
GATE_CFG(GATE_RTC, RCC_RTCCFGR, 1, 0),
GATE_CFG(GATE_DDRCP, RCC_DDRCPCFGR, 1, 0),
/* WARNING 2 CLOCKS FOR ONE GATE */
+#if STM32MP21
+ GATE_CFG(GATE_USBHOHCI, RCC_USBHCFGR, 1, 0),
+ GATE_CFG(GATE_USBHEHCI, RCC_USBHCFGR, 1, 0),
+#else /* STM32MP21 */
GATE_CFG(GATE_USB2OHCI, RCC_USB2CFGR, 1, 0),
GATE_CFG(GATE_USB2EHCI, RCC_USB2CFGR, 1, 0),
GATE_CFG(GATE_USB3DR, RCC_USB3DRCFGR, 1, 0),
+#endif /* STM32MP21 */
GATE_CFG(GATE_BSEC, RCC_BSECCFGR, 1, 0),
GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0),
GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0),
@@ -461,22 +567,34 @@
GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0),
GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0),
GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0),
+#if !STM32MP23
GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0),
+#endif /* !STM32MP23 */
+#if STM32MP25
GATE_CFG(GATE_I2C5, RCC_I2C5CFGR, 1, 0),
GATE_CFG(GATE_I2C4, RCC_I2C4CFGR, 1, 0),
GATE_CFG(GATE_I2C6, RCC_I2C6CFGR, 1, 0),
+#endif /* STM32MP25 */
+#if !STM32MP21
GATE_CFG(GATE_I2C7, RCC_I2C7CFGR, 1, 0),
+#endif /* !STM32MP21 */
GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0),
GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0),
GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0),
+#if STM32MP25
GATE_CFG(GATE_UART8, RCC_UART8CFGR, 1, 0),
GATE_CFG(GATE_UART9, RCC_UART9CFGR, 1, 0),
+#endif /* STM32MP25 */
GATE_CFG(GATE_STGEN, RCC_STGENCFGR, 1, 0),
+#if !STM32MP21
GATE_CFG(GATE_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 1, 0),
GATE_CFG(GATE_USBTC, RCC_USBTCCFGR, 1, 0),
GATE_CFG(GATE_I2C8, RCC_I2C8CFGR, 1, 0),
+#endif /* !STM32MP21 */
GATE_CFG(GATE_OSPI1, RCC_OSPI1CFGR, 1, 0),
+#if !STM32MP21
GATE_CFG(GATE_OSPI2, RCC_OSPI2CFGR, 1, 0),
+#endif /* !STM32MP21 */
GATE_CFG(GATE_FMC, RCC_FMCCFGR, 1, 0),
GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0),
GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0),
@@ -499,11 +617,14 @@
.bitrdy = _bitrdy,\
}
-static const struct div_cfg dividers_mp25[] = {
+static const struct div_cfg dividers_mp2[] = {
DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 31),
DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 31),
DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 31),
DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 31),
+#if STM32MP21
+ DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 0, apb_div_table, 31),
+#endif /* STM32MP21 */
DIV_CFG(DIV_APBDBG, RCC_APBDBGDIVR, 0, 3, 0, apb_div_table, 31),
DIV_CFG(DIV_LSMCU, RCC_LSMCUDIVR, 0, 1, 0, NULL, 31),
DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, 0),
@@ -520,7 +641,7 @@
NB_OSCILLATOR
};
-static struct clk_oscillator_data stm32mp25_osc_data[] = {
+static struct clk_oscillator_data stm32mp2_osc_data[] = {
OSCILLATOR(OSC_HSI, _CK_HSI, "clk-hsi", GATE_HSI, GATE_HSI_RDY,
NULL, NULL, NULL),
@@ -551,7 +672,7 @@
static const char *clk_stm32_get_oscillator_name(enum stm32_osc id)
{
if (id < NB_OSCILLATOR) {
- return stm32mp25_osc_data[id].name;
+ return stm32mp2_osc_data[id].name;
}
return NULL;
@@ -590,10 +711,12 @@
.reg_pllxcfgr1 = (_reg),\
}
-static const struct stm32_clk_pll stm32mp25_clk_pll[_PLL_NB] = {
+static const struct stm32_clk_pll stm32mp2_clk_pll[_PLL_NB] = {
CLK_PLL_CFG(_PLL1, _CK_PLL1, A35_SS_CHGCLKREQ),
CLK_PLL_CFG(_PLL2, _CK_PLL2, RCC_PLL2CFGR1),
+#if !STM32MP21
CLK_PLL_CFG(_PLL3, _CK_PLL3, RCC_PLL3CFGR1),
+#endif /* !STM32MP21 */
CLK_PLL_CFG(_PLL4, _CK_PLL4, RCC_PLL4CFGR1),
CLK_PLL_CFG(_PLL5, _CK_PLL5, RCC_PLL5CFGR1),
CLK_PLL_CFG(_PLL6, _CK_PLL6, RCC_PLL6CFGR1),
@@ -603,7 +726,7 @@
static const struct stm32_clk_pll *clk_stm32_pll_data(unsigned int idx)
{
- return &stm32mp25_clk_pll[idx];
+ return &stm32mp2_clk_pll[idx];
}
static unsigned long clk_get_pll_fvco(struct stm32_clk_priv *priv,
@@ -958,6 +1081,7 @@
#define RCC_16_MHZ UL(16000000)
#ifdef IMAGE_BL2
+#if !STM32MP21
static int clk_stm32_osc_msi_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate,
unsigned long prate)
{
@@ -982,12 +1106,16 @@
return ret;
}
+#endif /* !STM32MP21 */
#endif /* IMAGE_BL2 */
static unsigned long clk_stm32_osc_msi_recalc_rate(struct stm32_clk_priv *priv,
int id __unused,
unsigned long prate __unused)
{
+#if STM32MP21
+ return RCC_16_MHZ;
+#else /* STM32MP21 */
uintptr_t address = priv->base + RCC_BDCR;
if ((mmio_read_32(address) & RCC_BDCR_MSIFREQSEL) == 0U) {
@@ -995,6 +1123,7 @@
} else {
return RCC_16_MHZ;
}
+#endif /* STM32MP21 */
}
static const struct stm32_clk_ops clk_stm32_osc_msi_ops = {
@@ -1039,10 +1168,10 @@
STM32_OSC_MSI_OPS,
STM32_RTC_OPS,
- MP25_LAST_OPS
+ MP2_LAST_OPS
};
-static const struct stm32_clk_ops *ops_array_mp25[MP25_LAST_OPS] = {
+static const struct stm32_clk_ops *ops_array_mp2[MP2_LAST_OPS] = {
[NO_OPS] = NULL,
[FIXED_FACTOR_OPS] = &clk_fixed_factor_ops,
[GATE_OPS] = &clk_gate_ops,
@@ -1061,7 +1190,7 @@
[STM32_RTC_OPS] = &clk_stm32_rtc_ops
};
-static const struct clk_stm32 stm32mp25_clk[CK_LAST] = {
+static const struct clk_stm32 stm32mp2_clk[CK_LAST] = {
CLK_FIXED_RATE(_CK_0_MHZ, _NO_ID, RCC_0_MHZ),
/* ROOT CLOCKS */
@@ -1081,7 +1210,9 @@
CLK_PLL1(_CK_PLL1, PLL1_CK, MUX(MUX_MUXSEL5), _PLL1, 0),
CLK_PLL(_CK_PLL2, PLL2_CK, MUX(MUX_MUXSEL6), _PLL2, 0),
+#if !STM32MP21
CLK_PLL(_CK_PLL3, PLL3_CK, MUX(MUX_MUXSEL7), _PLL3, 0),
+#endif /* !STM32MP21 */
CLK_PLL(_CK_PLL4, PLL4_CK, MUX(MUX_MUXSEL0), _PLL4, 0),
CLK_PLL(_CK_PLL5, PLL5_CK, MUX(MUX_MUXSEL1), _PLL5, 0),
CLK_PLL(_CK_PLL6, PLL6_CK, MUX(MUX_MUXSEL2), _PLL6, 0),
@@ -1158,21 +1289,35 @@
STM32_DIV(_CK_ICN_APB2, CK_ICN_APB2, _CK_ICN_LS_MCU, 0, DIV_APB2),
STM32_DIV(_CK_ICN_APB3, CK_ICN_APB3, _CK_ICN_LS_MCU, 0, DIV_APB3),
STM32_DIV(_CK_ICN_APB4, CK_ICN_APB4, _CK_ICN_LS_MCU, 0, DIV_APB4),
+#if STM32MP21
+ STM32_DIV(_CK_ICN_APB5, CK_ICN_APB5, _CK_ICN_LS_MCU, 0, DIV_APB5),
+#endif /* STM32MP21 */
STM32_DIV(_CK_ICN_APBDBG, CK_ICN_APBDBG, _CK_ICN_LS_MCU, 0, DIV_APBDBG),
/* KERNEL CLOCK */
STM32_GATE(_CK_SYSRAM, CK_BUS_SYSRAM, _CK_ICN_HS_MCU, 0, GATE_SYSRAM),
STM32_GATE(_CK_RETRAM, CK_BUS_RETRAM, _CK_ICN_HS_MCU, 0, GATE_RETRAM),
STM32_GATE(_CK_SRAM1, CK_BUS_SRAM1, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM1),
+#if !STM32MP21
STM32_GATE(_CK_SRAM2, CK_BUS_SRAM2, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM2),
+#endif /* !STM32MP21 */
STM32_GATE(_CK_DDRPHYC, CK_BUS_DDRPHYC, _CK_ICN_LS_MCU, 0, GATE_DDRPHYC),
STM32_GATE(_CK_SYSCPU1, CK_BUS_SYSCPU1, _CK_ICN_LS_MCU, 0, GATE_SYSCPU1),
STM32_GATE(_CK_CRC, CK_BUS_CRC, _CK_ICN_LS_MCU, 0, GATE_CRC),
+#if !STM32MP21
STM32_GATE(_CK_OSPIIOM, CK_BUS_OSPIIOM, _CK_ICN_LS_MCU, 0, GATE_OSPIIOM),
+#endif /* !STM32MP21 */
STM32_GATE(_CK_BKPSRAM, CK_BUS_BKPSRAM, _CK_ICN_LS_MCU, 0, GATE_BKPSRAM),
+#if STM32MP21
+ STM32_GATE(_CK_HASH1, CK_BUS_HASH1, _CK_ICN_LS_MCU, 0, GATE_HASH1),
+ STM32_GATE(_CK_HASH2, CK_BUS_HASH2, _CK_ICN_LS_MCU, 0, GATE_HASH2),
+ STM32_GATE(_CK_RNG1, CK_BUS_RNG1, _CK_ICN_LS_MCU, 0, GATE_RNG1),
+ STM32_GATE(_CK_RNG2, CK_BUS_RNG2, _CK_ICN_LS_MCU, 0, GATE_RNG2),
+#else /* STM32MP21 */
STM32_GATE(_CK_HASH, CK_BUS_HASH, _CK_ICN_LS_MCU, 0, GATE_HASH),
STM32_GATE(_CK_RNG, CK_BUS_RNG, _CK_ICN_LS_MCU, 0, GATE_RNG),
+#endif /* STM32MP21 */
STM32_GATE(_CK_CRYP1, CK_BUS_CRYP1, _CK_ICN_LS_MCU, 0, GATE_CRYP1),
STM32_GATE(_CK_CRYP2, CK_BUS_CRYP2, _CK_ICN_LS_MCU, 0, GATE_CRYP2),
STM32_GATE(_CK_SAES, CK_BUS_SAES, _CK_ICN_LS_MCU, 0, GATE_SAES),
@@ -1187,18 +1332,27 @@
STM32_GATE(_CK_GPIOG, CK_BUS_GPIOG, _CK_ICN_LS_MCU, 0, GATE_GPIOG),
STM32_GATE(_CK_GPIOH, CK_BUS_GPIOH, _CK_ICN_LS_MCU, 0, GATE_GPIOH),
STM32_GATE(_CK_GPIOI, CK_BUS_GPIOI, _CK_ICN_LS_MCU, 0, GATE_GPIOI),
+#if !STM32MP21
STM32_GATE(_CK_GPIOJ, CK_BUS_GPIOJ, _CK_ICN_LS_MCU, 0, GATE_GPIOJ),
STM32_GATE(_CK_GPIOK, CK_BUS_GPIOK, _CK_ICN_LS_MCU, 0, GATE_GPIOK),
+#endif /* !STM32MP21 */
STM32_GATE(_CK_GPIOZ, CK_BUS_GPIOZ, _CK_ICN_LS_MCU, 0, GATE_GPIOZ),
STM32_GATE(_CK_RTC, CK_BUS_RTC, _CK_ICN_LS_MCU, 0, GATE_RTC),
STM32_GATE(_CK_DDRCP, CK_BUS_DDR, _CK_ICN_DDR, 0, GATE_DDRCP),
/* WARNING 2 CLOCKS FOR ONE GATE */
+#if STM32MP21
+ STM32_GATE(_CK_USBHOHCI, CK_BUS_USBHOHCI, _CK_ICN_HSL, 0, GATE_USBHOHCI),
+ STM32_GATE(_CK_USBHEHCI, CK_BUS_USBHEHCI, _CK_ICN_HSL, 0, GATE_USBHEHCI),
+#else /* STM32MP21 */
STM32_GATE(_CK_USB2OHCI, CK_BUS_USB2OHCI, _CK_ICN_HSL, 0, GATE_USB2OHCI),
STM32_GATE(_CK_USB2EHCI, CK_BUS_USB2EHCI, _CK_ICN_HSL, 0, GATE_USB2EHCI),
+#endif /* STM32MP21 */
+#if !STM32MP21
STM32_GATE(_CK_USB3DR, CK_BUS_USB3DR, _CK_ICN_HSL, 0, GATE_USB3DR),
+#endif /* !STM32MP21 */
STM32_GATE(_CK_BSEC, CK_BUS_BSEC, _CK_ICN_APB3, 0, GATE_BSEC),
STM32_GATE(_CK_IWDG1, CK_BUS_IWDG1, _CK_ICN_APB3, 0, GATE_IWDG1),
@@ -1211,24 +1365,41 @@
STM32_GATE(_CK_UART4, CK_KER_UART4, _CK_FLEXGEN_08, 0, GATE_UART4),
STM32_GATE(_CK_USART3, CK_KER_USART3, _CK_FLEXGEN_09, 0, GATE_USART3),
STM32_GATE(_CK_UART5, CK_KER_UART5, _CK_FLEXGEN_09, 0, GATE_UART5),
+#if STM32MP21
+ STM32_GATE(_CK_I2C1, CK_KER_I2C1, _CK_FLEXGEN_13, 0, GATE_I2C1),
+ STM32_GATE(_CK_I2C2, CK_KER_I2C2, _CK_FLEXGEN_13, 0, GATE_I2C2),
+ STM32_GATE(_CK_USART1, CK_KER_USART1, _CK_FLEXGEN_18, 0, GATE_USART1),
+ STM32_GATE(_CK_USART6, CK_KER_USART6, _CK_FLEXGEN_19, 0, GATE_USART6),
+ STM32_GATE(_CK_UART7, CK_KER_UART7, _CK_FLEXGEN_20, 0, GATE_UART7),
+ STM32_GATE(_CK_I2C3, CK_KER_I2C3, _CK_FLEXGEN_38, 0, GATE_I2C3),
+#else /* STM32MP21 */
STM32_GATE(_CK_I2C1, CK_KER_I2C1, _CK_FLEXGEN_12, 0, GATE_I2C1),
STM32_GATE(_CK_I2C2, CK_KER_I2C2, _CK_FLEXGEN_12, 0, GATE_I2C2),
+#if STM32MP25
STM32_GATE(_CK_I2C3, CK_KER_I2C3, _CK_FLEXGEN_13, 0, GATE_I2C3),
STM32_GATE(_CK_I2C5, CK_KER_I2C5, _CK_FLEXGEN_13, 0, GATE_I2C5),
STM32_GATE(_CK_I2C4, CK_KER_I2C4, _CK_FLEXGEN_14, 0, GATE_I2C4),
STM32_GATE(_CK_I2C6, CK_KER_I2C6, _CK_FLEXGEN_14, 0, GATE_I2C6),
+#endif /* STM32MP25 */
STM32_GATE(_CK_I2C7, CK_KER_I2C7, _CK_FLEXGEN_15, 0, GATE_I2C7),
STM32_GATE(_CK_USART1, CK_KER_USART1, _CK_FLEXGEN_19, 0, GATE_USART1),
STM32_GATE(_CK_USART6, CK_KER_USART6, _CK_FLEXGEN_20, 0, GATE_USART6),
STM32_GATE(_CK_UART7, CK_KER_UART7, _CK_FLEXGEN_21, 0, GATE_UART7),
+#if STM32MP25
STM32_GATE(_CK_UART8, CK_KER_UART8, _CK_FLEXGEN_21, 0, GATE_UART8),
STM32_GATE(_CK_UART9, CK_KER_UART9, _CK_FLEXGEN_22, 0, GATE_UART9),
+#endif /* STM32MP25 */
+#endif /* STM32MP21 */
STM32_GATE(_CK_STGEN, CK_KER_STGEN, _CK_FLEXGEN_33, 0, GATE_STGEN),
+#if !STM32MP21
STM32_GATE(_CK_USB3PCIEPHY, CK_KER_USB3PCIEPHY, _CK_FLEXGEN_34, 0, GATE_USB3PCIEPHY),
STM32_GATE(_CK_USBTC, CK_KER_USBTC, _CK_FLEXGEN_35, 0, GATE_USBTC),
STM32_GATE(_CK_I2C8, CK_KER_I2C8, _CK_FLEXGEN_38, 0, GATE_I2C8),
+#endif /* !STM32MP21 */
STM32_GATE(_CK_OSPI1, CK_KER_OSPI1, _CK_FLEXGEN_48, 0, GATE_OSPI1),
+#if !STM32MP21
STM32_GATE(_CK_OSPI2, CK_KER_OSPI2, _CK_FLEXGEN_49, 0, GATE_OSPI2),
+#endif /* !STM32MP21 */
STM32_GATE(_CK_FMC, CK_KER_FMC, _CK_FLEXGEN_50, 0, GATE_FMC),
STM32_GATE(_CK_SDMMC1, CK_KER_SDMMC1, _CK_FLEXGEN_51, 0, GATE_SDMMC1),
STM32_GATE(_CK_SDMMC2, CK_KER_SDMMC2, _CK_FLEXGEN_52, 0, GATE_SDMMC2),
@@ -1240,7 +1411,9 @@
CLKSRC_CA35SS,
CLKSRC_PLL1,
CLKSRC_PLL2,
+#if !STM32MP21
CLKSRC_PLL3,
+#endif /* !STM32MP21 */
CLKSRC_PLL4,
CLKSRC_PLL5,
CLKSRC_PLL6,
@@ -1656,6 +1829,11 @@
int err;
for (i = _PLL1; i < _PLL_NB; i++) {
+#if STM32MP21
+ if (i == _PLL3) {
+ continue;
+ }
+#endif
err = clk_stm32_pll_init(priv, i);
if (err) {
return err;
@@ -1886,6 +2064,7 @@
static void stm32_enable_oscillator_msi(struct stm32_clk_priv *priv)
{
+#if !STM32MP21
struct stm32_clk_platdata *pdata = priv->pdata;
struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_MSI];
int err;
@@ -1896,6 +2075,7 @@
osci->freq / 1000000U);
panic();
}
+#endif /* !STM32MP21 */
_clk_stm32_enable(priv, _CK_MSI);
}
@@ -2204,6 +2384,11 @@
int subnode = 0;
int err = 0;
+#if STM32MP21
+ if (i == _PLL3) {
+ continue;
+ }
+#endif
snprintf(name, sizeof(name), "st,pll-%u", i + 1);
subnode = fdt_subnode_offset(fdt, node, name);
@@ -2266,49 +2451,53 @@
}
#endif /* IMAGE_BL2 */
-static struct stm32_osci_dt_cfg mp25_osci[NB_OSCILLATOR];
+static struct stm32_osci_dt_cfg mp2_osci[NB_OSCILLATOR];
-static struct stm32_pll_dt_cfg mp25_pll[_PLL_NB];
+static struct stm32_pll_dt_cfg mp2_pll[_PLL_NB];
#define DT_FLEXGEN_CLK_MAX 64
-static uint32_t mp25_flexgen[DT_FLEXGEN_CLK_MAX];
+static uint32_t mp2_flexgen[DT_FLEXGEN_CLK_MAX];
+#if STM32MP21
+#define DT_BUS_CLK_MAX 7
+#else /* STM32MP21 */
#define DT_BUS_CLK_MAX 6
-static uint32_t mp25_busclk[DT_BUS_CLK_MAX];
+#endif /* STM32MP21 */
+static uint32_t mp2_busclk[DT_BUS_CLK_MAX];
#define DT_KERNEL_CLK_MAX 20
-static uint32_t mp25_kernelclk[DT_KERNEL_CLK_MAX];
+static uint32_t mp2_kernelclk[DT_KERNEL_CLK_MAX];
-static struct stm32_clk_platdata stm32mp25_pdata = {
- .osci = mp25_osci,
+static struct stm32_clk_platdata stm32mp2_pdata = {
+ .osci = mp2_osci,
.nosci = NB_OSCILLATOR,
- .pll = mp25_pll,
+ .pll = mp2_pll,
.npll = _PLL_NB,
- .flexgen = mp25_flexgen,
+ .flexgen = mp2_flexgen,
.nflexgen = DT_FLEXGEN_CLK_MAX,
- .busclk = mp25_busclk,
+ .busclk = mp2_busclk,
.nbusclk = DT_BUS_CLK_MAX,
- .kernelclk = mp25_kernelclk,
+ .kernelclk = mp2_kernelclk,
.nkernelclk = DT_KERNEL_CLK_MAX,
};
-static uint8_t refcounts_mp25[CK_LAST];
+static uint8_t refcounts_mp2[CK_LAST];
-static struct stm32_clk_priv stm32mp25_clock_data = {
+static struct stm32_clk_priv stm32mp2_clock_data = {
.base = RCC_BASE,
- .num = ARRAY_SIZE(stm32mp25_clk),
- .clks = stm32mp25_clk,
- .parents = parent_mp25,
- .nb_parents = ARRAY_SIZE(parent_mp25),
- .gates = gates_mp25,
- .nb_gates = ARRAY_SIZE(gates_mp25),
- .div = dividers_mp25,
- .nb_div = ARRAY_SIZE(dividers_mp25),
- .osci_data = stm32mp25_osc_data,
- .nb_osci_data = ARRAY_SIZE(stm32mp25_osc_data),
- .gate_refcounts = refcounts_mp25,
- .pdata = &stm32mp25_pdata,
- .ops_array = ops_array_mp25,
+ .num = ARRAY_SIZE(stm32mp2_clk),
+ .clks = stm32mp2_clk,
+ .parents = parent_mp2,
+ .nb_parents = ARRAY_SIZE(parent_mp2),
+ .gates = gates_mp2,
+ .nb_gates = ARRAY_SIZE(gates_mp2),
+ .div = dividers_mp2,
+ .nb_div = ARRAY_SIZE(dividers_mp2),
+ .osci_data = stm32mp2_osc_data,
+ .nb_osci_data = ARRAY_SIZE(stm32mp2_osc_data),
+ .gate_refcounts = refcounts_mp2,
+ .pdata = &stm32mp2_pdata,
+ .ops_array = ops_array_mp2,
};
int stm32mp2_clk_init(void)
@@ -2317,13 +2506,13 @@
int ret;
#ifdef IMAGE_BL2
- ret = stm32_clk_parse_fdt(&stm32mp25_pdata);
+ ret = stm32_clk_parse_fdt(&stm32mp2_pdata);
if (ret != 0) {
return ret;
}
#endif
- ret = clk_stm32_init(&stm32mp25_clock_data, base);
+ ret = clk_stm32_init(&stm32mp2_clock_data, base);
if (ret != 0) {
return ret;
}
diff --git a/drivers/st/crypto/stm32_hash.c b/drivers/st/crypto/stm32_hash.c
index bd49324..e1a519e 100644
--- a/drivers/st/crypto/stm32_hash.c
+++ b/drivers/st/crypto/stm32_hash.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -46,13 +46,13 @@
#endif
#if STM32_HASH_VER == 4
#define HASH_CR_ALGO_SHIFT U(17)
-#define HASH_CR_ALGO_SHA1 (0x0U << HASH_CR_ALGO_SHIFT)
-#define HASH_CR_ALGO_SHA224 (0x2U << HASH_CR_ALGO_SHIFT)
-#define HASH_CR_ALGO_SHA256 (0x3U << HASH_CR_ALGO_SHIFT)
-#define HASH_CR_ALGO_SHA384 (0xCU << HASH_CR_ALGO_SHIFT)
-#define HASH_CR_ALGO_SHA512_224 (0xDU << HASH_CR_ALGO_SHIFT)
-#define HASH_CR_ALGO_SHA512_256 (0xEU << HASH_CR_ALGO_SHIFT)
-#define HASH_CR_ALGO_SHA512 (0xFU << HASH_CR_ALGO_SHIFT)
+#define HASH_CR_ALGO_SHA1 ((uint32_t)(0x0U) << HASH_CR_ALGO_SHIFT)
+#define HASH_CR_ALGO_SHA224 ((uint32_t)(0x2U) << HASH_CR_ALGO_SHIFT)
+#define HASH_CR_ALGO_SHA256 ((uint32_t)(0x3U) << HASH_CR_ALGO_SHIFT)
+#define HASH_CR_ALGO_SHA384 ((uint32_t)(0xCU) << HASH_CR_ALGO_SHIFT)
+#define HASH_CR_ALGO_SHA512_224 ((uint32_t)(0xDU) << HASH_CR_ALGO_SHIFT)
+#define HASH_CR_ALGO_SHA512_256 ((uint32_t)(0xEU) << HASH_CR_ALGO_SHIFT)
+#define HASH_CR_ALGO_SHA512 ((uint32_t)(0xFU) << HASH_CR_ALGO_SHIFT)
#endif
/* Status Flags */
@@ -139,7 +139,7 @@
{
uint32_t reg;
- reg = HASH_CR_INIT | (HASH_DATA_8_BITS << HASH_CR_DATATYPE_SHIFT);
+ reg = HASH_CR_INIT | ((uint32_t)HASH_DATA_8_BITS << HASH_CR_DATATYPE_SHIFT);
switch (mode) {
#if STM32_HASH_VER == 2
@@ -191,7 +191,7 @@
for (i = 0U; i < (stm32_hash.digest_size / sizeof(uint32_t)); i++) {
dsg = __builtin_bswap32(mmio_read_32(hash_base() +
HASH_HREG(i)));
- memcpy(digest + (i * sizeof(uint32_t)), &dsg, sizeof(uint32_t));
+ (void)(memcpy(&digest[i * sizeof(uint32_t)], (uint8_t *)&dsg, sizeof(uint32_t)));
}
/*
@@ -206,23 +206,27 @@
int stm32_hash_update(const uint8_t *buffer, size_t length)
{
size_t remain_length = length;
+ uint8_t *remain_buf = (uint8_t *)&stm32_remain.buffer;
+ const uint8_t *buf = buffer;
int ret = 0;
if ((length == 0U) || (buffer == NULL)) {
return 0;
}
- clk_enable(stm32_hash.clock);
+ ret = clk_enable(stm32_hash.clock);
+ if (ret != 0) {
+ return ret;
+ }
if (stm32_remain.length != 0U) {
uint32_t copysize;
copysize = MIN((sizeof(uint32_t) - stm32_remain.length),
length);
- memcpy(((uint8_t *)&stm32_remain.buffer) + stm32_remain.length,
- buffer, copysize);
+ (void)(memcpy(&remain_buf[stm32_remain.length], buf, copysize));
remain_length -= copysize;
- buffer += copysize;
+ buf = &buf[copysize];
if (stm32_remain.length == sizeof(uint32_t)) {
ret = hash_write_data(stm32_remain.buffer);
if (ret != 0) {
@@ -236,20 +240,20 @@
while (remain_length / sizeof(uint32_t) != 0U) {
uint32_t tmp_buf;
- memcpy(&tmp_buf, buffer, sizeof(uint32_t));
+ (void)(memcpy((void *)&tmp_buf, buf, sizeof(uint32_t)));
ret = hash_write_data(tmp_buf);
if (ret != 0) {
goto exit;
}
- buffer += sizeof(uint32_t);
+ buf = &buf[sizeof(uint32_t)];
remain_length -= sizeof(uint32_t);
}
if (remain_length != 0U) {
assert(stm32_remain.length == 0U);
- memcpy((uint8_t *)&stm32_remain.buffer, buffer, remain_length);
+ (void)(memcpy((uint8_t *)&stm32_remain.buffer, buf, remain_length));
stm32_remain.length = remain_length;
}
@@ -263,7 +267,10 @@
{
int ret;
- clk_enable(stm32_hash.clock);
+ ret = clk_enable(stm32_hash.clock);
+ if (ret != 0) {
+ return ret;
+ }
if (stm32_remain.length != 0U) {
ret = hash_write_data(stm32_remain.buffer);
@@ -303,7 +310,10 @@
void stm32_hash_init(enum stm32_hash_algo_mode mode)
{
- clk_enable(stm32_hash.clock);
+ if (clk_enable(stm32_hash.clock) != 0) {
+ ERROR("%s: fail to enable clock\n", __func__);
+ panic();
+ }
hash_hw_init(mode);
@@ -316,6 +326,7 @@
{
struct dt_node_info hash_info;
int node;
+ int ret;
for (node = dt_get_node(&hash_info, -1, DT_HASH_COMPAT);
node != -FDT_ERR_NOTFOUND;
@@ -336,7 +347,10 @@
stm32_hash.base = hash_info.base;
stm32_hash.clock = hash_info.clock;
- clk_enable(stm32_hash.clock);
+ ret = clk_enable(stm32_hash.clock);
+ if (ret != 0) {
+ return ret;
+ }
if (hash_info.reset >= 0) {
uint32_t id = (uint32_t)hash_info.reset;
diff --git a/drivers/st/crypto/stm32_saes.c b/drivers/st/crypto/stm32_saes.c
index f4da571..547ff89 100644
--- a/drivers/st/crypto/stm32_saes.c
+++ b/drivers/st/crypto/stm32_saes.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2022-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -211,9 +211,11 @@
uint64_t timeout;
/* Reset IP */
- mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
- udelay(SAES_RESET_DELAY);
- mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
+ if ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_BUSY) != _SAES_SR_BUSY) {
+ mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
+ udelay(SAES_RESET_DELAY);
+ mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
+ }
timeout = timeout_init_us(SAES_TIMEOUT_US);
while ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_BUSY) == _SAES_SR_BUSY) {
diff --git a/drivers/st/ddr/stm32mp2_ddr_helpers.c b/drivers/st/ddr/stm32mp2_ddr_helpers.c
index a2a4082..8efb7cf 100644
--- a/drivers/st/ddr/stm32mp2_ddr_helpers.c
+++ b/drivers/st/ddr/stm32mp2_ddr_helpers.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -363,8 +363,6 @@
mmio_write_32(stm32mp_rcc_base() + RCC_DDRCPCFGR,
RCC_DDRCPCFGR_DDRCPLPEN | RCC_DDRCPCFGR_DDRCPEN);
- /* TODO: check if ddr_sr_exit_loop() is needed here */
-
return 0;
}
@@ -390,13 +388,6 @@
return ddr_sr_exit_loop();
}
-uint32_t ddr_get_io_calibration_val(void)
-{
- /* TODO create related service */
-
- return 0U;
-}
-
int ddr_sr_entry(bool standby)
{
int ret = -EINVAL;
diff --git a/drivers/st/ddr/stm32mp2_ram.c b/drivers/st/ddr/stm32mp2_ram.c
index 95f05e7..2b0e317 100644
--- a/drivers/st/ddr/stm32mp2_ram.c
+++ b/drivers/st/ddr/stm32mp2_ram.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2021-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -142,9 +142,6 @@
ERROR("DDR rw test: can't access memory @ 0x%lx\n", uret);
panic();
}
-
- /* TODO Restore area overwritten by training */
- //stm32_restore_ddr_training_area();
} else {
size_t retsize;
diff --git a/drivers/st/ddr/stm32mp_ddr.c b/drivers/st/ddr/stm32mp_ddr.c
index 98968d5..4aa5c73 100644
--- a/drivers/st/ddr/stm32mp_ddr.c
+++ b/drivers/st/ddr/stm32mp_ddr.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2022-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -44,7 +44,7 @@
ddr_registers[type].name, i);
panic();
} else {
-#if !STM32MP13 && !STM32MP15
+#ifdef STM32MP2X
if (desc[i].qd) {
stm32mp_ddr_start_sw_done(priv->ctl);
}
@@ -52,7 +52,7 @@
value = *((uint32_t *)((uintptr_t)param +
desc[i].par_offset));
mmio_write_32(ptr, value);
-#if !STM32MP13 && !STM32MP15
+#ifdef STM32MP2X
if (desc[i].qd) {
stm32mp_ddr_wait_sw_done_ack(priv->ctl);
}
@@ -277,9 +277,9 @@
/* Toggle rfshctl3.refresh_update_level */
rfshctl3 = mmio_read_32((uintptr_t)&ctl->rfshctl3);
if ((rfshctl3 & refresh_update_level) == refresh_update_level) {
- mmio_setbits_32((uintptr_t)&ctl->rfshctl3, refresh_update_level);
- } else {
mmio_clrbits_32((uintptr_t)&ctl->rfshctl3, refresh_update_level);
+ } else {
+ mmio_setbits_32((uintptr_t)&ctl->rfshctl3, refresh_update_level);
refresh_update_level = 0U;
}
@@ -293,7 +293,7 @@
if (timeout_elapsed(timeout)) {
panic();
}
- } while ((rfshctl3 & DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL) != refresh_update_level);
+ } while ((rfshctl3 & DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL) == refresh_update_level);
VERBOSE("[0x%lx] rfshctl3 = 0x%x\n", (uintptr_t)&ctl->rfshctl3, rfshctl3);
}
diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c
index 44d7c09..2d64de3 100644
--- a/drivers/st/gpio/stm32_gpio.c
+++ b/drivers/st/gpio/stm32_gpio.c
@@ -282,7 +282,7 @@
clk_disable(clock);
-#if STM32MP13 || STM32MP15
+#ifdef STM32MP1X
if (status == DT_SECURE) {
stm32mp_register_secure_gpio(bank, pin);
#if !IMAGE_BL2
diff --git a/drivers/st/iwdg/stm32_iwdg.c b/drivers/st/iwdg/stm32_iwdg.c
index 74451d7..3d78c20 100644
--- a/drivers/st/iwdg/stm32_iwdg.c
+++ b/drivers/st/iwdg/stm32_iwdg.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,7 +33,6 @@
uintptr_t base;
unsigned long clock;
uint8_t flags;
- int num_irq;
};
static struct stm32_iwdg_instance stm32_iwdg[IWDG_MAX_INSTANCE];
diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c
index 66988d7..e07d9e7 100644
--- a/drivers/st/mmc/stm32_sdmmc2.c
+++ b/drivers/st/mmc/stm32_sdmmc2.c
@@ -129,7 +129,7 @@
#define DT_SDMMC2_COMPAT "st,stm32-sdmmc2"
#endif
-#if STM32MP13 || STM32MP15
+#ifdef STM32MP1X
#define SDMMC_FIFO_SIZE 64U
#else
#define SDMMC_FIFO_SIZE 1024U
diff --git a/drivers/st/regulator/regulator_fixed.c b/drivers/st/regulator/regulator_fixed.c
index 6c9d3b1..6b14b5d 100644
--- a/drivers/st/regulator/regulator_fixed.c
+++ b/drivers/st/regulator/regulator_fixed.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,7 +21,6 @@
struct fixed_data {
char name[FIXED_NAME_LEN];
- uint16_t volt;
struct regul_description desc;
};
diff --git a/drivers/tpm/tpm2_fifo.c b/drivers/tpm/tpm2_fifo.c
index 7c4b9d8..07a0bc0 100644
--- a/drivers/tpm/tpm2_fifo.c
+++ b/drivers/tpm/tpm2_fifo.c
@@ -246,7 +246,7 @@
err = tpm2_wait_reg_bits(tpm_base_addr + TPM_FIFO_REG_STATUS,
TPM_STAT_AVAIL,
- chip_data->timeout_msec_c,
+ chip_data->timeout_msec_a,
status);
if (err < 0) {
return err;
diff --git a/fdts/cca_cot_descriptors.dtsi b/fdts/cca_cot_descriptors.dts
similarity index 100%
rename from fdts/cca_cot_descriptors.dtsi
rename to fdts/cca_cot_descriptors.dts
diff --git a/fdts/dualroot_cot_descriptors.dtsi b/fdts/dualroot_cot_descriptors.dts
similarity index 100%
rename from fdts/dualroot_cot_descriptors.dtsi
rename to fdts/dualroot_cot_descriptors.dts
diff --git a/fdts/fvp-base-psci-common.dtsi b/fdts/fvp-base-psci-common.dtsi
index bdb0229..92d832f 100644
--- a/fdts/fvp-base-psci-common.dtsi
+++ b/fdts/fvp-base-psci-common.dtsi
@@ -29,10 +29,7 @@
chosen {
stdout-path = "serial0:115200n8";
-/* SPM_MM doesn't like this */
-#if SPM_MM == 0
bootargs = "console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on";
-#endif
};
aliases {
@@ -262,10 +259,10 @@
ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>,
/* First 3GB of 256GB PCIe memory region 2 */
<0x2000000 0x40 0x00000000 0x40 0x00000000 0x0 0xc0000000>;
- interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
msi-map = <0x0 &its 0x0 0x10000>;
iommu-map = <0x0 &smmu 0x0 0x10000>;
diff --git a/fdts/tbbr_cot_descriptors.dtsi b/fdts/tbbr_cot_descriptors.dts
similarity index 100%
rename from fdts/tbbr_cot_descriptors.dtsi
rename to fdts/tbbr_cot_descriptors.dts
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index e8c4054..a1cf5be 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -91,6 +91,17 @@
#define SERROR_EXCEPTION 0x180
/*******************************************************************************
+ * Encodings for GICv5 EL3 system registers
+ ******************************************************************************/
+#define ICC_PPI_DOMAINR0_EL3 S3_6_C12_C8_4
+#define ICC_PPI_DOMAINR1_EL3 S3_6_C12_C8_5
+#define ICC_PPI_DOMAINR2_EL3 S3_6_C12_C8_6
+#define ICC_PPI_DOMAINR3_EL3 S3_6_C12_C8_7
+
+#define ICC_PPI_DOMAINR_FIELD_MASK ULL(0x3)
+#define ICC_PPI_DOMAINR_COUNT (32)
+
+/*******************************************************************************
* Definitions for CPU system register interface to GICv3
******************************************************************************/
#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
@@ -432,6 +443,13 @@
#define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0)
#define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf)
+/* ID_AA64MMFR4_EL1 definitions */
+#define ID_AA64MMFR4_EL1 S3_0_C0_C7_4
+
+#define ID_AA64MMFR4_EL1_FGWTE3_SHIFT U(16)
+#define ID_AA64MMFR4_EL1_FGWTE3_MASK ULL(0xf)
+#define FGWTE3_IMPLEMENTED ULL(0x1)
+
/* ID_AA64PFR1_EL1 definitions */
#define ID_AA64PFR1_EL1_BT_SHIFT U(0)
@@ -504,6 +522,11 @@
#define SME2_IMPLEMENTED ULL(0x2)
#define SME_NOT_IMPLEMENTED ULL(0x0)
+/* ID_AA64PFR2_EL1 definitions */
+#define ID_AA64PFR2_EL1 S3_0_C0_C4_2
+#define ID_AA64PFR2_EL1_GCIE_SHIFT 12
+#define ID_AA64PFR2_EL1_GCIE_MASK ULL(0xf)
+
/* ID_PFR1_EL1 definitions */
#define ID_PFR1_VIRTEXT_SHIFT U(12)
#define ID_PFR1_VIRTEXT_MASK U(0xf)
@@ -620,7 +643,11 @@
#define CPACR_EL1_SMEN_MASK ULL(0x3)
/* SCR definitions */
+#if ENABLE_FEAT_GCIE
+#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5) | SCR_FIQ_BIT)
+#else
#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
+#endif
#define SCR_NSE_SHIFT U(62)
#define SCR_FGTEN2_BIT (UL(1) << 59)
#define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT)
@@ -679,9 +706,8 @@
#define MDCR_SBRBE(x) ((x) << MDCR_SBRBE_SHIFT)
#define MDCR_SBRBE_ALL ULL(0x3)
#define MDCR_SBRBE_NS ULL(0x1)
-#define MDCR_NSTB(x) ((x) << 24)
-#define MDCR_NSTB_EL1 ULL(0x3)
-#define MDCR_NSTB_EL3 ULL(0x2)
+#define MDCR_NSTB_EN_BIT (ULL(1) << 24)
+#define MDCR_NSTB_SS_BIT (ULL(1) << 25)
#define MDCR_NSTBE_BIT (ULL(1) << 26)
#define MDCR_MTPME_BIT (ULL(1) << 28)
#define MDCR_TDCC_BIT (ULL(1) << 27)
@@ -696,9 +722,8 @@
#define MDCR_SPD32_LEGACY ULL(0x0)
#define MDCR_SPD32_DISABLE ULL(0x2)
#define MDCR_SPD32_ENABLE ULL(0x3)
-#define MDCR_NSPB(x) ((x) << 12)
-#define MDCR_NSPB_EL1 ULL(0x3)
-#define MDCR_NSPB_EL3 ULL(0x2)
+#define MDCR_NSPB_SS_BIT (ULL(1) << 13)
+#define MDCR_NSPB_EN_BIT (ULL(1) << 12)
#define MDCR_NSPBE_BIT (ULL(1) << 11)
#define MDCR_TDOSA_BIT (ULL(1) << 10)
#define MDCR_TDA_BIT (ULL(1) << 9)
@@ -864,6 +889,24 @@
#define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT)
#define SPSR_PACM_BIT_AARCH64 BIT_64(35)
+/*
+ * SPSR_EL2
+ * M=0x9 (0b1001 EL2h)
+ * M[4]=0
+ * DAIF=0xF Exceptions masked on entry.
+ * BTYPE=0 BTI not yet supported.
+ * SSBS=0 Not yet supported.
+ * IL=0 Not an illegal exception return.
+ * SS=0 Not single stepping.
+ * PAN=1 RMM shouldn't access Unprivileged memory when running in VHE mode.
+ * UAO=0
+ * DIT=0
+ * TCO=0
+ * NZCV=0
+ */
+#define SPSR_EL2_REALM (SPSR_M_EL2H | (0xF << SPSR_DAIF_SHIFT) | \
+ SPSR_PAN_BIT)
+
#define DISABLE_ALL_EXCEPTIONS \
(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
@@ -1556,7 +1599,7 @@
/*******************************************************************************
* Definitions for DynamicIQ Shared Unit registers
******************************************************************************/
-#define CLUSTERPWRDN_EL1 S3_0_c15_c3_6
+#define CLUSTERPWRDN_EL1 S3_0_C15_C3_6
/*******************************************************************************
* FEAT_FPMR - Floating point Mode Register
@@ -1602,4 +1645,68 @@
#define MECIDR_EL2_MECIDWidthm1_MASK U(0xf)
#define MECIDR_EL2_MECIDWidthm1_SHIFT U(0)
+/******************************************************************************
+ * FEAT_FGWTE3 - Fine Grained Write Trap
+ ******************************************************************************/
+#define FGWTE3_EL3 S3_6_C1_C1_5
+
+/* FGWTE3_EL3 Defintions */
+#define FGWTE3_EL3_VBAR_EL3_BIT (U(1) << 21)
+#define FGWTE3_EL3_TTBR0_EL3_BIT (U(1) << 20)
+#define FGWTE3_EL3_TPIDR_EL3_BIT (U(1) << 19)
+#define FGWTE3_EL3_TCR_EL3_BIT (U(1) << 18)
+#define FGWTE3_EL3_SPMROOTCR_EL3_BIT (U(1) << 17)
+#define FGWTE3_EL3_SCTLR2_EL3_BIT (U(1) << 16)
+#define FGWTE3_EL3_SCTLR_EL3_BIT (U(1) << 15)
+#define FGWTE3_EL3_PIR_EL3_BIT (U(1) << 14)
+#define FGWTE3_EL3_MECID_RL_A_EL3_BIT (U(1) << 12)
+#define FGWTE3_EL3_MAIR2_EL3_BIT (U(1) << 10)
+#define FGWTE3_EL3_MAIR_EL3_BIT (U(1) << 9)
+#define FGWTE3_EL3_GPTBR_EL3_BIT (U(1) << 8)
+#define FGWTE3_EL3_GPCCR_EL3_BIT (U(1) << 7)
+#define FGWTE3_EL3_GCSPR_EL3_BIT (U(1) << 6)
+#define FGWTE3_EL3_GCSCR_EL3_BIT (U(1) << 5)
+#define FGWTE3_EL3_AMAIR2_EL3_BIT (U(1) << 4)
+#define FGWTE3_EL3_AMAIR_EL3_BIT (U(1) << 3)
+#define FGWTE3_EL3_AFSR1_EL3_BIT (U(1) << 2)
+#define FGWTE3_EL3_AFSR0_EL3_BIT (U(1) << 1)
+#define FGWTE3_EL3_ACTLR_EL3_BIT (U(1) << 0)
+
+#define FGWTE3_EL3_EARLY_INIT_VAL ( \
+ FGWTE3_EL3_VBAR_EL3_BIT | \
+ FGWTE3_EL3_TTBR0_EL3_BIT | \
+ FGWTE3_EL3_SPMROOTCR_EL3_BIT | \
+ FGWTE3_EL3_SCTLR2_EL3_BIT | \
+ FGWTE3_EL3_PIR_EL3_BIT | \
+ FGWTE3_EL3_MECID_RL_A_EL3_BIT | \
+ FGWTE3_EL3_MAIR2_EL3_BIT | \
+ FGWTE3_EL3_MAIR_EL3_BIT | \
+ FGWTE3_EL3_GPTBR_EL3_BIT | \
+ FGWTE3_EL3_GPCCR_EL3_BIT | \
+ FGWTE3_EL3_GCSPR_EL3_BIT | \
+ FGWTE3_EL3_GCSCR_EL3_BIT | \
+ FGWTE3_EL3_AMAIR2_EL3_BIT | \
+ FGWTE3_EL3_AMAIR_EL3_BIT | \
+ FGWTE3_EL3_AFSR1_EL3_BIT | \
+ FGWTE3_EL3_AFSR0_EL3_BIT)
+
+#if HW_ASSISTED_COHERENCY
+#define FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT FGWTE3_EL3_SCTLR_EL3_BIT |
+#else
+#define FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT
+#endif
+
+#if !(CRASH_REPORTING)
+#define FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT FGWTE3_EL3_TPIDR_EL3_BIT |
+#else
+#define FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT
+#endif
+
+#define FGWTE3_EL3_LATE_INIT_VAL ( \
+ FGWTE3_EL3_EARLY_INIT_VAL | \
+ FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT \
+ FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT \
+ FGWTE3_EL3_TCR_EL3_BIT | \
+ FGWTE3_EL3_ACTLR_EL3_BIT)
+
#endif /* ARCH_H */
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 757ce06..ddb5e23 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -148,6 +148,8 @@
* +----------------------------+
* | FEAT_PAUTH_LR |
* +----------------------------+
+ * | FEAT_FGWTE3 |
+ * +----------------------------+
*/
__attribute__((always_inline))
@@ -271,6 +273,11 @@
CREATE_FEATURE_FUNCS(feat_fgt2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
ID_AA64MMFR0_EL1_FGT_MASK, FGT2_IMPLEMENTED, ENABLE_FEAT_FGT2)
+/* FEAT_FGWTE3: Fine-grained write traps EL3 */
+CREATE_FEATURE_FUNCS(feat_fgwte3, id_aa64mmfr4_el1, ID_AA64MMFR4_EL1_FGWTE3_SHIFT,
+ ID_AA64MMFR4_EL1_FGWTE3_MASK, FGWTE3_IMPLEMENTED,
+ ENABLE_FEAT_FGWTE3)
+
/* FEAT_ECV: Enhanced Counter Virtualization */
CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
ID_AA64MMFR0_EL1_ECV_MASK, 1U, ENABLE_FEAT_ECV)
@@ -520,4 +527,11 @@
CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU)
+/*************************************************************************
+ * Function to identify the presence of FEAT_GCIE (GICv5 CPU interface
+ * extension).
+ ************************************************************************/
+CREATE_FEATURE_FUNCS(feat_gcie, id_aa64pfr2_el1, ID_AA64PFR2_EL1_GCIE_SHIFT,
+ ID_AA64PFR2_EL1_GCIE_MASK, 1U, ENABLE_FEAT_GCIE)
+
#endif /* ARCH_FEATURES_H */
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index c885424..b0ad93b 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -559,6 +559,12 @@
DEFINE_SYSREG_RW_FUNCS(dacr32_el2)
DEFINE_SYSREG_RW_FUNCS(ifsr32_el2)
+/* GICv5 System Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr0_el3, ICC_PPI_DOMAINR0_EL3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr1_el3, ICC_PPI_DOMAINR1_EL3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr2_el3, ICC_PPI_DOMAINR2_EL3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr3_el3, ICC_PPI_DOMAINR3_EL3)
+
/* GICv3 System Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
@@ -764,6 +770,11 @@
/* FEAT_MEC Registers */
DEFINE_RENAME_SYSREG_READ_FUNC(mecidr_el2, MECIDR_EL2)
+DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr4_el1, ID_AA64MMFR4_EL1)
+
+/* FEAT_FGWTE3 Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(fgwte3_el3, FGWTE3_EL3)
+
#define IS_IN_EL(x) \
(GET_EL(read_CurrentEl()) == MODE_EL##x)
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index fce0f2c..ee5d8d9 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -65,7 +65,11 @@
* ---------------------------------------------------------------------
*/
bl plat_my_core_pos
- bl _cpu_data_by_index
+ /* index into the cpu_data */
+ mov_imm x1, CPU_DATA_SIZE
+ mul x0, x0, x1
+ adr_l x1, percpu_data
+ add x0, x0, x1
msr tpidr_el3, x0
#endif /* IMAGE_BL31 */
diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h
index 8b9dfb6..0ca760e 100644
--- a/include/bl31/interrupt_mgmt.h
+++ b/include/bl31/interrupt_mgmt.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,7 +16,8 @@
#define INTR_TYPE_S_EL1 U(0)
#define INTR_TYPE_EL3 U(1)
#define INTR_TYPE_NS U(2)
-#define MAX_INTR_TYPES U(3)
+#define INTR_TYPE_RL U(3)
+#define MAX_INTR_TYPES U(4)
#define INTR_TYPE_INVAL MAX_INTR_TYPES
/* Interrupt routing modes */
@@ -82,6 +83,7 @@
#ifndef __ASSEMBLER__
#include <errno.h>
+#include <stddef.h>
#include <stdint.h>
/*******************************************************************************
@@ -142,7 +144,7 @@
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
-u_register_t get_scr_el3_from_routing_model(uint32_t security_state);
+u_register_t get_scr_el3_from_routing_model(size_t security_state);
int32_t set_routing_model(uint32_t type, uint32_t flags);
int32_t register_interrupt_type_handler(uint32_t type,
interrupt_type_handler_t handler,
diff --git a/include/common/debug.h b/include/common/debug.h
index 0ddb400..6d7f2c6 100644
--- a/include/common/debug.h
+++ b/include/common/debug.h
@@ -32,6 +32,7 @@
#include <cdefs.h>
#include <stdarg.h>
#include <stdbool.h>
+#include <stdint.h>
#include <stdio.h>
#include <drivers/console.h>
@@ -135,7 +136,7 @@
void tf_log(const char *fmt, ...) __printflike(1, 2);
void tf_log_newline(const char log_fmt[2]);
-void tf_log_set_max_level(unsigned int log_level);
+void tf_log_set_max_level(uint32_t log_level);
#endif /* __ASSEMBLER__ */
#endif /* DEBUG_H */
diff --git a/include/common/feat_detect.h b/include/common/feat_detect.h
index 18e6c42..04e4c02 100644
--- a/include/common/feat_detect.h
+++ b/include/common/feat_detect.h
@@ -8,7 +8,7 @@
#define FEAT_DETECT_H
/* Function Prototypes */
-void detect_arch_features(void);
+void detect_arch_features(unsigned int core_pos);
/* Macro Definitions */
#define FEAT_STATE_DISABLED 0
diff --git a/include/drivers/arm/cci.h b/include/drivers/arm/cci.h
index 5aea95a..d48b3d6 100644
--- a/include/drivers/arm/cci.h
+++ b/include/drivers/arm/cci.h
@@ -102,6 +102,7 @@
#ifndef __ASSEMBLER__
+#include <stddef.h>
#include <stdint.h>
/* Function declarations */
@@ -116,10 +117,10 @@
* SLAVE_IF_UNUSED should be used in the map to represent no AMBA 4 master exists
* for that interface.
*/
-void cci_init(uintptr_t base, const int *map, unsigned int num_cci_masters);
+void cci_init(uintptr_t base, const int *map, size_t num_cci_masters);
-void cci_enable_snoop_dvm_reqs(unsigned int master_id);
-void cci_disable_snoop_dvm_reqs(unsigned int master_id);
+void cci_enable_snoop_dvm_reqs(size_t master_id);
+void cci_disable_snoop_dvm_reqs(size_t master_id);
#endif /* __ASSEMBLER__ */
#endif /* CCI_H */
diff --git a/include/drivers/arm/css/dsu.h b/include/drivers/arm/css/dsu.h
deleted file mode 100644
index 4d7822b..0000000
--- a/include/drivers/arm/css/dsu.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef DSU_H
-#define DSU_H
-
-#define PMCR_N_MAX 0x1f
-
-#define save_pmu_reg(state, reg) state->reg = read_##reg()
-
-#define restore_pmu_reg(context, reg) write_##reg(context->reg)
-
-typedef struct cluster_pmu_state{
- uint64_t clusterpmcr;
- uint64_t clusterpmcntenset;
- uint64_t clusterpmccntr;
- uint64_t clusterpmovsset;
- uint64_t clusterpmselr;
- uint64_t clusterpmsevtyper;
- uint64_t counter_val[PMCR_N_MAX];
- uint64_t counter_type[PMCR_N_MAX];
-} cluster_pmu_state_t;
-
-static inline unsigned int read_cluster_eventctr_num(void)
-{
- return ((read_clusterpmcr() >> CLUSTERPMCR_N_SHIFT) &
- CLUSTERPMCR_N_MASK);
-}
-
-
-void save_dsu_pmu_state(cluster_pmu_state_t *cluster_pmu_context);
-
-void restore_dsu_pmu_state(cluster_pmu_state_t *cluster_pmu_context);
-
-void cluster_on_dsu_pmu_context_restore(void);
-
-void cluster_off_dsu_pmu_context_save(void);
-
-#endif /* DSU_H */
diff --git a/include/drivers/arm/dsu.h b/include/drivers/arm/dsu.h
new file mode 100644
index 0000000..492babd
--- /dev/null
+++ b/include/drivers/arm/dsu.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DSU_H
+#define DSU_H
+
+#if defined(__aarch64__)
+#include <dsu_def.h>
+
+/*
+ * Power Control Registers enable bit of Auxilary Control register.
+ * ACTLR_EL3_PWREN_BIT definition is same among cores like Cortex-X925,
+ * Cortex-X4, Cortex-A520, Cortex-A725 that are used in a cluster
+ * with DSU.
+ */
+#define ACTLR_EL3_PWREN_BIT BIT(7)
+
+#define PMCR_N_MAX 0x1f
+
+#define save_pmu_reg(state, reg) state->reg = read_##reg()
+
+#define restore_pmu_reg(context, reg) write_##reg(context->reg)
+
+typedef struct cluster_pmu_state {
+ uint64_t clusterpmcr;
+ uint64_t clusterpmcntenset;
+ uint64_t clusterpmccntr;
+ uint64_t clusterpmovsset;
+ uint64_t clusterpmselr;
+ uint64_t clusterpmsevtyper;
+ uint64_t counter_val[PMCR_N_MAX];
+ uint64_t counter_type[PMCR_N_MAX];
+} cluster_pmu_state_t;
+
+typedef struct dsu_driver_data {
+ uint8_t clusterpwrdwn_pwrdn;
+ uint8_t clusterpwrdwn_memret;
+ uint8_t clusterpwrctlr_cachepwr;
+ uint8_t clusterpwrctlr_funcret;
+} dsu_driver_data_t;
+
+extern const dsu_driver_data_t plat_dsu_data;
+
+static inline unsigned int read_cluster_eventctr_num(void)
+{
+ return ((read_clusterpmcr() >> CLUSTERPMCR_N_SHIFT) &
+ CLUSTERPMCR_N_MASK);
+}
+
+void save_dsu_pmu_state(cluster_pmu_state_t *cluster_pmu_context);
+
+void restore_dsu_pmu_state(cluster_pmu_state_t *cluster_pmu_context);
+
+void cluster_on_dsu_pmu_context_restore(void);
+
+void cluster_off_dsu_pmu_context_save(void);
+
+void dsu_driver_init(const dsu_driver_data_t *data);
+#endif
+#endif /* DSU_H */
diff --git a/include/drivers/arm/gicv5.h b/include/drivers/arm/gicv5.h
new file mode 100644
index 0000000..d01d24b
--- /dev/null
+++ b/include/drivers/arm/gicv5.h
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GICV5_H
+#define GICV5_H
+
+#ifndef __ASSEMBLER__
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <lib/mmio.h>
+#endif
+
+#include <lib/utils_def.h>
+
+/* Interrupt Domain definitions */
+#define INTDMN_S 0
+#define INTDMN_NS 1
+#define INTDMN_EL3 2
+#define INTDMN_RL 3
+
+/* Trigger modes */
+#define TM_EDGE 0
+#define TM_LEVEL 1
+
+/* Architected PPI numbers */
+#define PPI_TRBIRQ 31
+#define PPI_CNTP 30
+#define PPI_CNTPS 29
+#define PPI_CNTHV 28
+#define PPI_CNTV 27
+#define PPI_CNTHP 26
+#define PPI_GICMNT 25
+#define PPI_CTIIRQ 24
+#define PPI_PMUIRQ 23
+#define PPI_COMMIRQ 22
+#define PPI_PMBIRQ 21
+#define PPI_CNTHPS 20
+#define PPI_CNTHVS 19
+#define PPI_DB_NS 2
+#define PPI_DB_RL 1
+#define PPI_DB_S 0
+
+/* Register fields common to all IRI components.
+ * They have the same name and offset in every config frame */
+#define IRI_AIDR_COMPONENT_SHIFT 8
+#define IRI_AIDR_COMPONENT_WIDTH 4
+#define IRI_AIDR_COMPONENT_IRS 0
+#define IRI_AIDR_COMPONENT_ITS 1
+#define IRI_AIDR_COMPONENT_IWB 2
+#define IRI_AIDR_ARCH_MAJOR_SHIFT 4
+#define IRI_AIDR_ARCH_MAJOR_WIDTH 4
+#define IRI_AIDR_ARCH_MAJOR_V5 0
+#define IRI_AIDR_ARCH_MINOR_SHIFT 0
+#define IRI_AIDR_ARCH_MINOR_WIDTH 4
+#define IRI_AIDR_ARCH_MINOR_P0 0
+
+/* IRS register fields */
+#define IRS_IDR6_SPI_IRS_RANGE_SHIFT 0
+#define IRS_IDR6_SPI_IRS_RANGE_WIDTH 24
+#define IRS_IDR7_SPI_BASE_SHIFT 0
+#define IRS_IDR7_SPI_BASE_WIDTH 24
+
+#define IRS_SPI_STATUSR_IDLE_BIT BIT(0)
+#define IRS_SPI_STATUSR_V_BIT BIT(1)
+
+/* IWB register fields */
+#define IWB_IDR0_DOMAINS_SHIFT 11
+#define IWB_IDR0_DOMAINS_WIDTH 4
+#define IWB_IDR0_IWRANGE_SHIFT 0
+#define IWB_IDR0_IWRANGE_WIDTH 10
+
+#define IWB_CR0_IWBEN_BIT BIT(0)
+#define IWB_CR0_IDLE_BIT BIT(1)
+
+#define IWB_WENABLE_STATUSR_IDLE_BIT BIT(0)
+#define IWB_WDOMAIN_STATUSR_IDLE_BIT BIT(0)
+
+#define IWB_WDOMAINR_DOMAINX_MASK 0x3
+
+#ifndef __ASSEMBLER__
+
+#define _PPI_FIELD_SHIFT(_REG, _ppi_id) \
+ ((_ppi_id % (ICC_PPI_##_REG##_COUNT)) * (64 / ICC_PPI_##_REG##_COUNT))
+
+#define write_icc_ppi_domainr(_var, _ppi_id, _value) \
+ do { \
+ _var |= (uint64_t)_value << _PPI_FIELD_SHIFT(DOMAINR, _ppi_id);\
+ } while (false)
+
+
+#define DEFINE_GICV5_MMIO_WRITE_FUNC(_name, _offset) \
+static inline void write_##_name(uintptr_t base, uint32_t val) \
+{ \
+ mmio_write_32(base + _offset, val); \
+}
+
+#define DEFINE_GICV5_MMIO_READ_FUNC(_name, _offset) \
+static inline uint32_t read_##_name(uintptr_t base) \
+{ \
+ return mmio_read_32(base + _offset); \
+}
+
+#define DEFINE_GICV5_MMIO_WRITE_INDEXED_FUNC(_name, _offset) \
+static inline void write_##_name(uintptr_t base, uint16_t index, uint32_t val) \
+{ \
+ mmio_write_32(base + _offset + (index * sizeof(uint32_t)), val); \
+}
+
+#define DEFINE_GICV5_MMIO_READ_INDEXED_FUNC(_name, _offset) \
+static inline uint32_t read_##_name(uintptr_t base, uint16_t index) \
+{ \
+ return mmio_read_32(base + _offset + (index * sizeof(uint32_t))); \
+}
+
+#define DEFINE_GICV5_MMIO_RW_FUNCS(_name, _offset) \
+ DEFINE_GICV5_MMIO_READ_FUNC(_name, _offset) \
+ DEFINE_GICV5_MMIO_WRITE_FUNC(_name, _offset)
+
+#define DEFINE_GICV5_MMIO_RW_INDEXED_FUNCS(_name, _offset) \
+ DEFINE_GICV5_MMIO_READ_INDEXED_FUNC(_name, _offset) \
+ DEFINE_GICV5_MMIO_WRITE_INDEXED_FUNC(_name, _offset)
+
+DEFINE_GICV5_MMIO_READ_FUNC(iri_aidr, 0x44)
+
+DEFINE_GICV5_MMIO_READ_FUNC(iwb_idr0, 0x00)
+DEFINE_GICV5_MMIO_RW_FUNCS( iwb_cr0, 0x80)
+DEFINE_GICV5_MMIO_READ_FUNC(iwb_wenable_statusr, 0xc0)
+DEFINE_GICV5_MMIO_READ_FUNC(iwb_wdomain_statusr, 0xc4)
+DEFINE_GICV5_MMIO_RW_INDEXED_FUNCS(iwb_wenabler, 0x2000)
+DEFINE_GICV5_MMIO_RW_INDEXED_FUNCS(iwb_wtmr, 0x4000)
+DEFINE_GICV5_MMIO_RW_INDEXED_FUNCS(iwb_wdomainr, 0x6000)
+
+DEFINE_GICV5_MMIO_READ_FUNC(irs_idr6, 0x0018)
+DEFINE_GICV5_MMIO_READ_FUNC(irs_idr7, 0x001c)
+DEFINE_GICV5_MMIO_RW_FUNCS( irs_spi_selr, 0x0108)
+DEFINE_GICV5_MMIO_RW_FUNCS( irs_spi_domainr, 0x010c)
+DEFINE_GICV5_MMIO_RW_FUNCS( irs_spi_cfgr, 0x0114)
+DEFINE_GICV5_MMIO_READ_FUNC(irs_spi_statusr, 0x0118)
+
+#define WAIT_FOR_IDLE(base, reg, reg_up) \
+ do { \
+ while ((read_##reg(base) & reg_up##_IDLE_BIT) == 0U) {} \
+ } while (0)
+
+/* wait for IDLE but also check the V bit was set */
+#define WAIT_FOR_VIDLE(base, reg, reg_up) \
+ do { \
+ uint32_t val; \
+ while (((val = read_##reg(base)) & reg_up##_IDLE_BIT) == 0U) {} \
+ assert((val & reg##_V_BIT) != 0U); \
+ } while (0)
+
+#define WAIT_FOR_VIDLE_IRS_SPI_STATUSR(base) \
+ WAIT_FOR_IDLE(base, irs_spi_statusr, IRS_SPI_STATUSR)
+
+#define WAIT_FOR_IDLE_IWB_WENABLE_STATUSR(base) \
+ WAIT_FOR_IDLE(base, iwb_wenable_statusr, IWB_WENABLE_STATUSR)
+#define WAIT_FOR_IDLE_IWB_WDOMAIN_STATUSR(base) \
+ WAIT_FOR_IDLE(base, iwb_wdomain_statusr, IWB_WDOMAIN_STATUSR)
+#define WAIT_FOR_IDLE_IWB_CR0(base) \
+ WAIT_FOR_IDLE(base, iwb_cr0, IWB_CR0)
+
+#define WIRE_PROP_DESC(_id, _domain, _tm) \
+ { \
+ .id = (_id), \
+ .domain = (_domain), \
+ .tm = (_tm), \
+ }
+
+struct gicv5_wire_props {
+ /* continuous wire ID as seen by the attached component */
+ uint32_t id;
+ /* use the INTDMN_XYZ macros */
+ uint8_t domain:2;
+ /* use the TM_XYZ (eg. TM_EDGE) macros */
+ uint8_t tm:1;
+};
+
+/* to describe every IRS in the system */
+struct gicv5_irs {
+ /* mapped device nGnRnE by the platform*/
+ uintptr_t el3_config_frame;
+ struct gicv5_wire_props *spis;
+ uint32_t num_spis;
+};
+
+/*
+ * to describe every IWB in the system where EL3 is the MPPAS. IWBs that have
+ * another world as an MPPAS need not be included
+ */
+struct gicv5_iwb {
+ /* mapped device nGnRnE by the platform*/
+ uintptr_t config_frame;
+ struct gicv5_wire_props *wires;
+ uint32_t num_wires;
+};
+
+struct gicv5_driver_data {
+ struct gicv5_irs *irss;
+ struct gicv5_iwb *iwbs;
+ uint32_t num_irss;
+ uint32_t num_iwbs;
+};
+
+extern const struct gicv5_driver_data plat_gicv5_driver_data;
+
+void gicv5_driver_init();
+uint8_t gicv5_get_pending_interrupt_type(void);
+bool gicv5_has_interrupt_type(unsigned int type);
+void gicv5_enable_ppis();
+#endif /* __ASSEMBLER__ */
+#endif /* GICV5_H */
diff --git a/include/drivers/cadence/cdns_sdmmc.h b/include/drivers/cadence/cdns_sdmmc.h
index f8d616f..895a705 100644
--- a/include/drivers/cadence/cdns_sdmmc.h
+++ b/include/drivers/cadence/cdns_sdmmc.h
@@ -342,7 +342,6 @@
/* MMC Peripheral Definition */
#define SOCFPGA_MMC_BLOCK_MASK (SOCFPGA_MMC_BLOCK_SIZE - U(1))
#define SOCFPGA_MMC_BOOT_CLK_RATE (400 * 1000)
-#define MMC_RESPONSE_NONE 0
#define SDHC_CDNS_SRS03_VALUE 0x01020013
/* Value randomly chosen for eMMC RCA, it should be > 1 */
diff --git a/include/drivers/console.h b/include/drivers/console.h
index 0de2c99..300bceb 100644
--- a/include/drivers/console.h
+++ b/include/drivers/console.h
@@ -23,13 +23,13 @@
#define CONSOLE_T_DRVDATA (U(5) * REGSZ)
#endif
-#define CONSOLE_FLAG_BOOT (U(1) << 0)
-#define CONSOLE_FLAG_RUNTIME (U(1) << 1)
-#define CONSOLE_FLAG_CRASH (U(1) << 2)
+#define CONSOLE_FLAG_BOOT BIT_32(0)
+#define CONSOLE_FLAG_RUNTIME BIT_32(1)
+#define CONSOLE_FLAG_CRASH BIT_32(2)
/* Bits 3 to 7 reserved for additional scopes in future expansion. */
#define CONSOLE_FLAG_SCOPE_MASK GENMASK(7, 0)
/* Bits 8 to 31 for non-scope use. */
-#define CONSOLE_FLAG_TRANSLATE_CRLF (U(1) << 8)
+#define CONSOLE_FLAG_TRANSLATE_CRLF BIT_32(8)
/* Returned by getc callbacks when receive FIFO is empty. */
#define ERROR_NO_PENDING_CHAR (-1)
diff --git a/include/drivers/measured_boot/event_log/event_handoff.h b/include/drivers/measured_boot/event_log/event_handoff.h
index e969d1f..f8c8716 100644
--- a/include/drivers/measured_boot/event_log/event_handoff.h
+++ b/include/drivers/measured_boot/event_log/event_handoff.h
@@ -10,7 +10,7 @@
#include <stdint.h>
-#include <lib/transfer_list.h>
+#include <transfer_list.h>
/**
* Initializes or extends the TPM event log in the transfer list.
diff --git a/include/drivers/measured_boot/event_log/event_log.h b/include/drivers/measured_boot/event_log/event_log.h
index b5adfdc..1313111 100644
--- a/include/drivers/measured_boot/event_log/event_log.h
+++ b/include/drivers/measured_boot/event_log/event_log.h
@@ -11,7 +11,9 @@
#include <stdint.h>
#include <drivers/auth/crypto_mod.h>
+#if TRANSFER_LIST
#include "event_handoff.h"
+#endif
#include "tcg.h"
/*
diff --git a/include/drivers/mmc.h b/include/drivers/mmc.h
index 454a85a..55ed35c 100644
--- a/include/drivers/mmc.h
+++ b/include/drivers/mmc.h
@@ -52,6 +52,7 @@
#define MMC_RESPONSE_R5 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
#define MMC_RESPONSE_R6 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
#define MMC_RESPONSE_R7 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
+#define MMC_RESPONSE_NONE 0U
/* Value randomly chosen for eMMC RCA, it should be > 1 */
#define MMC_FIX_RCA 6
diff --git a/include/drivers/nxp/crypto/caam/sec_hw_specific.h b/include/drivers/nxp/crypto/caam/sec_hw_specific.h
index bc11aca..02bd4d0 100644
--- a/include/drivers/nxp/crypto/caam/sec_hw_specific.h
+++ b/include/drivers/nxp/crypto/caam/sec_hw_specific.h
@@ -123,6 +123,7 @@
/* RNG RDSTA bitmask */
#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
+#define RNG_STATE1_HANDLE_INSTANTIATED 0x00000002
#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
/* use von Neumann data in both entropy shifter and statistical checker */
#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0
diff --git a/include/drivers/st/bsec3_reg.h b/include/drivers/st/bsec3_reg.h
index 177e30b..4263f76 100644
--- a/include/drivers/st/bsec3_reg.h
+++ b/include/drivers/st/bsec3_reg.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -84,7 +84,7 @@
/* BSEC_OTPSR register fields */
#define BSEC_OTPSR_BUSY BIT_32(0)
-#define BSEC_OTPSR_FUSEOK BIT_32(1)
+#define BSEC_OTPSR_INIT_DONE BIT_32(1)
#define BSEC_OTPSR_HIDEUP BIT_32(2)
#define BSEC_OTPSR_OTPNVIR BIT_32(4)
#define BSEC_OTPSR_OTPERR BIT_32(5)
diff --git a/include/drivers/st/stm32mp21_pwr.h b/include/drivers/st/stm32mp21_pwr.h
new file mode 100644
index 0000000..570f079
--- /dev/null
+++ b/include/drivers/st/stm32mp21_pwr.h
@@ -0,0 +1,416 @@
+/*
+ * Copyright (c) 2025, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP21_PWR_H
+#define STM32MP21_PWR_H
+
+#include <lib/utils_def.h>
+
+#define PWR_CR1 U(0x00)
+#define PWR_CR2 U(0x04)
+#define PWR_CR3 U(0x08)
+#define PWR_CR7 U(0x18)
+#define PWR_CR8 U(0x1C)
+#define PWR_CR9 U(0x20)
+#define PWR_CR10 U(0x24)
+#define PWR_CR11 U(0x28)
+#define PWR_BDCR U(0x38)
+#define PWR_CPU1CR U(0x40)
+#define PWR_CPU2CR U(0x44)
+#define PWR_D1CR U(0x4C)
+#define PWR_D2CR U(0x50)
+#define PWR_WKUPCR1 U(0x60)
+#define PWR_WKUPCR2 U(0x64)
+#define PWR_WKUPCR3 U(0x68)
+#define PWR_WKUPCR4 U(0x6C)
+#define PWR_WKUPCR5 U(0x70)
+#define PWR_WKUPCR6 U(0x74)
+#define PWR_RSECCFGR U(0x100)
+#define PWR_RPRIVCFGR U(0x104)
+#define PWR_R0CIDCFGR U(0x108)
+#define PWR_R1CIDCFGR U(0x10C)
+#define PWR_R2CIDCFGR U(0x110)
+#define PWR_R3CIDCFGR U(0x114)
+#define PWR_R4CIDCFGR U(0x118)
+#define PWR_R5CIDCFGR U(0x11C)
+#define PWR_R6CIDCFGR U(0x120)
+#define PWR_WIOSECCFGR U(0x180)
+#define PWR_WIOPRIVCFGR U(0x184)
+#define PWR_WIO1CIDCFGR U(0x188)
+#define PWR_WIO1SEMCR U(0x18C)
+#define PWR_WIO2CIDCFGR U(0x190)
+#define PWR_WIO2SEMCR U(0x194)
+#define PWR_WIO3CIDCFGR U(0x198)
+#define PWR_WIO3SEMCR U(0x19C)
+#define PWR_WIO4CIDCFGR U(0x1A0)
+#define PWR_WIO4SEMCR U(0x1A4)
+#define PWR_WIO5CIDCFGR U(0x1A8)
+#define PWR_WIO5SEMCR U(0x1AC)
+#define PWR_WIO6CIDCFGR U(0x1B0)
+#define PWR_WIO6SEMCR U(0x1B4)
+#define PWR_CPU1D1SR U(0x200)
+#define PWR_CPU2D2SR U(0x204)
+#define PWR_DBGR U(0x308)
+#define PWR_VERR U(0x3F4)
+#define PWR_IPIDR U(0x3F8)
+#define PWR_SIDR U(0x3FC)
+
+/* PWR_CR1 register fields */
+#define PWR_CR1_VDDIO3VMEN BIT(0)
+#define PWR_CR1_USB33VMEN BIT(2)
+#define PWR_CR1_AVMEN BIT(4)
+#define PWR_CR1_VDDIO3SV BIT(8)
+#define PWR_CR1_USB33SV BIT(10)
+#define PWR_CR1_ASV BIT(12)
+#define PWR_CR1_VDDIO3RDY BIT(16)
+#define PWR_CR1_USB33RDY BIT(18)
+#define PWR_CR1_ARDY BIT(20)
+#define PWR_CR1_VDDIOVRSEL BIT(24)
+#define PWR_CR1_VDDIO3VRSEL BIT(25)
+#define PWR_CR1_GPVMO BIT(31)
+
+/* PWR_CR2 register fields */
+#define PWR_CR2_MONEN BIT(0)
+#define PWR_CR2_VBATL BIT(8)
+#define PWR_CR2_VBATH BIT(9)
+#define PWR_CR2_TEMPL BIT(10)
+#define PWR_CR2_TEMPH BIT(11)
+
+/* PWR_CR3 register fields */
+#define PWR_CR3_PVDEN BIT(0)
+#define PWR_CR3_PVDO BIT(8)
+
+/* PWR_CR7 register fields */
+#define PWR_CR7_VDDIO2VMEN BIT(0)
+#define PWR_CR7_VDDIO2SV BIT(8)
+#define PWR_CR7_VDDIO2RDY BIT(16)
+#define PWR_CR7_VDDIO2VRSEL BIT(24)
+#define PWR_CR7_VDDIO2VRSTBY BIT(25)
+
+/* PWR_CR8 register fields */
+#define PWR_CR8_VDDIO1VMEN BIT(0)
+#define PWR_CR8_VDDIO1SV BIT(8)
+#define PWR_CR8_VDDIO1RDY BIT(16)
+#define PWR_CR8_VDDIO1VRSEL BIT(24)
+#define PWR_CR8_VDDIO1VRSTBY BIT(25)
+
+/* PWR_CR9 register fields */
+#define PWR_CR9_BKPRBSEN BIT(0)
+
+/* PWR_CR10 register fields */
+#define PWR_CR10_RETRBSEN_MASK GENMASK_32(1, 0)
+#define PWR_CR10_RETRBSEN_SHIFT 0
+#define PWR_CR10_RETRBSEN_DISABLE 0U
+#define PWR_CR10_RETRBSEN_STANDBY_VBAT 1U
+#define PWR_CR10_RETRBSEN_STANDBY 2U
+
+/* PWR_CR11 register fields */
+#define PWR_CR11_DDRRETDIS BIT(0)
+
+/* PWR_BDCR register fields */
+#define PWR_BDCR_DBP BIT(0)
+
+/* PWR_CPU1CR register fields */
+#define PWR_CPU1CR_PDDS_D2 BIT(0)
+#define PWR_CPU1CR_PDDS_D1 BIT(1)
+#define PWR_CPU1CR_VBF BIT(4)
+#define PWR_CPU1CR_STOPF BIT(5)
+#define PWR_CPU1CR_SBF BIT(6)
+#define PWR_CPU1CR_SBF_D1 BIT(7)
+#define PWR_CPU1CR_CSSF BIT(9)
+#define PWR_CPU1CR_STANDBYWFIL2 BIT(15)
+#define PWR_CPU1CR_LPDS_D1 BIT(16)
+#define PWR_CPU1CR_LVDS_D1 BIT(17)
+
+/* PWR_CPU2CR register fields */
+#define PWR_CPU2CR_PDDS_D2 BIT(0)
+#define PWR_CPU2CR_VBF BIT(4)
+#define PWR_CPU2CR_STOPF BIT(5)
+#define PWR_CPU2CR_SBF BIT(6)
+#define PWR_CPU2CR_SBF_D2 BIT(7)
+#define PWR_CPU2CR_CSSF BIT(9)
+#define PWR_CPU2CR_DEEPSLEEP BIT(15)
+#define PWR_CPU2CR_LPDS_D2 BIT(16)
+#define PWR_CPU2CR_LVDS_D2 BIT(17)
+
+/* PWR_D1CR register fields */
+#define PWR_D1CR_LPCFG_D1 BIT(0)
+#define PWR_D1CR_POPL_D1_MASK GENMASK_32(12, 8)
+#define PWR_D1CR_POPL_D1_SHIFT 8
+
+/* PWR_D2CR register fields */
+#define PWR_D2CR_LPCFG_D2 BIT(0)
+#define PWR_D2CR_POPL_D2_MASK GENMASK_32(12, 8)
+#define PWR_D2CR_POPL_D2_SHIFT 8
+#define PWR_D2CR_LPLVDLY_D2_MASK GENMASK_32(18, 16)
+#define PWR_D2CR_LPLVDLY_D2_SHIFT 16
+#define PWR_D2CR_PODH_D2_MASK GENMASK_32(27, 24)
+#define PWR_D2CR_PODH_D2_SHIFT 24
+
+/* PWR_WKUPCR1 register fields */
+#define PWR_WKUPCR1_WKUPC BIT(0)
+#define PWR_WKUPCR1_WKUPP BIT(8)
+#define PWR_WKUPCR1_WKUPPUPD_MASK GENMASK_32(13, 12)
+#define PWR_WKUPCR1_WKUPPUPD_SHIFT 12
+#define PWR_WKUPCR1_WKUPENCPU1 BIT(16)
+#define PWR_WKUPCR1_WKUPENCPU2 BIT(17)
+#define PWR_WKUPCR1_WKUPF BIT(31)
+
+/* PWR_WKUPCR2 register fields */
+#define PWR_WKUPCR2_WKUPC BIT(0)
+#define PWR_WKUPCR2_WKUPP BIT(8)
+#define PWR_WKUPCR2_WKUPPUPD_MASK GENMASK_32(13, 12)
+#define PWR_WKUPCR2_WKUPPUPD_SHIFT 12
+#define PWR_WKUPCR2_WKUPENCPU1 BIT(16)
+#define PWR_WKUPCR2_WKUPENCPU2 BIT(17)
+#define PWR_WKUPCR2_WKUPF BIT(31)
+
+/* PWR_WKUPCR3 register fields */
+#define PWR_WKUPCR3_WKUPC BIT(0)
+#define PWR_WKUPCR3_WKUPP BIT(8)
+#define PWR_WKUPCR3_WKUPPUPD_MASK GENMASK_32(13, 12)
+#define PWR_WKUPCR3_WKUPPUPD_SHIFT 12
+#define PWR_WKUPCR3_WKUPENCPU1 BIT(16)
+#define PWR_WKUPCR3_WKUPENCPU2 BIT(17)
+#define PWR_WKUPCR3_WKUPF BIT(31)
+
+/* PWR_WKUPCR4 register fields */
+#define PWR_WKUPCR4_WKUPC BIT(0)
+#define PWR_WKUPCR4_WKUPP BIT(8)
+#define PWR_WKUPCR4_WKUPPUPD_MASK GENMASK_32(13, 12)
+#define PWR_WKUPCR4_WKUPPUPD_SHIFT 12
+#define PWR_WKUPCR4_WKUPENCPU1 BIT(16)
+#define PWR_WKUPCR4_WKUPENCPU2 BIT(17)
+#define PWR_WKUPCR4_WKUPF BIT(31)
+
+/* PWR_WKUPCR5 register fields */
+#define PWR_WKUPCR5_WKUPC BIT(0)
+#define PWR_WKUPCR5_WKUPP BIT(8)
+#define PWR_WKUPCR5_WKUPPUPD_MASK GENMASK_32(13, 12)
+#define PWR_WKUPCR5_WKUPPUPD_SHIFT 12
+#define PWR_WKUPCR5_WKUPENCPU1 BIT(16)
+#define PWR_WKUPCR5_WKUPENCPU2 BIT(17)
+#define PWR_WKUPCR5_WKUPF BIT(31)
+
+/* PWR_WKUPCR6 register fields */
+#define PWR_WKUPCR6_WKUPC BIT(0)
+#define PWR_WKUPCR6_WKUPP BIT(8)
+#define PWR_WKUPCR6_WKUPPUPD_MASK GENMASK_32(13, 12)
+#define PWR_WKUPCR6_WKUPPUPD_SHIFT 12
+#define PWR_WKUPCR6_WKUPENCPU1 BIT(16)
+#define PWR_WKUPCR6_WKUPENCPU2 BIT(17)
+#define PWR_WKUPCR6_WKUPF BIT(31)
+
+/* PWR_RSECCFGR register fields */
+#define PWR_RSECCFGR_RSEC0 BIT(0)
+#define PWR_RSECCFGR_RSEC1 BIT(1)
+#define PWR_RSECCFGR_RSEC2 BIT(2)
+#define PWR_RSECCFGR_RSEC3 BIT(3)
+#define PWR_RSECCFGR_RSEC4 BIT(4)
+#define PWR_RSECCFGR_RSEC5 BIT(5)
+#define PWR_RSECCFGR_RSEC6 BIT(6)
+
+/* PWR_RPRIVCFGR register fields */
+#define PWR_RPRIVCFGR_RPRIV0 BIT(0)
+#define PWR_RPRIVCFGR_RPRIV1 BIT(1)
+#define PWR_RPRIVCFGR_RPRIV2 BIT(2)
+#define PWR_RPRIVCFGR_RPRIV3 BIT(3)
+#define PWR_RPRIVCFGR_RPRIV4 BIT(4)
+#define PWR_RPRIVCFGR_RPRIV5 BIT(5)
+#define PWR_RPRIVCFGR_RPRIV6 BIT(6)
+
+/* PWR_R0CIDCFGR register fields */
+#define PWR_R0CIDCFGR_CFEN BIT(0)
+#define PWR_R0CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R0CIDCFGR_SCID_SHIFT 4
+
+/* PWR_R1CIDCFGR register fields */
+#define PWR_R1CIDCFGR_CFEN BIT(0)
+#define PWR_R1CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R1CIDCFGR_SCID_SHIFT 4
+
+/* PWR_R2CIDCFGR register fields */
+#define PWR_R2CIDCFGR_CFEN BIT(0)
+#define PWR_R2CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R2CIDCFGR_SCID_SHIFT 4
+
+/* PWR_R3CIDCFGR register fields */
+#define PWR_R3CIDCFGR_CFEN BIT(0)
+#define PWR_R3CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R3CIDCFGR_SCID_SHIFT 4
+
+/* PWR_R4CIDCFGR register fields */
+#define PWR_R4CIDCFGR_CFEN BIT(0)
+#define PWR_R4CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R4CIDCFGR_SCID_SHIFT 4
+
+/* PWR_R5CIDCFGR register fields */
+#define PWR_R5CIDCFGR_CFEN BIT(0)
+#define PWR_R5CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R5CIDCFGR_SCID_SHIFT 4
+
+/* PWR_R6CIDCFGR register fields */
+#define PWR_R6CIDCFGR_CFEN BIT(0)
+#define PWR_R6CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R6CIDCFGR_SCID_SHIFT 4
+
+/* PWR_WIOSECCFGR register fields */
+#define PWR_WIOSECCFGR_WIOSEC1 BIT(0)
+#define PWR_WIOSECCFGR_WIOSEC2 BIT(1)
+#define PWR_WIOSECCFGR_WIOSEC3 BIT(2)
+#define PWR_WIOSECCFGR_WIOSEC4 BIT(3)
+#define PWR_WIOSECCFGR_WIOSEC5 BIT(4)
+#define PWR_WIOSECCFGR_WIOSEC6 BIT(5)
+
+/* PWR_WIOPRIVCFGR register fields */
+#define PWR_WIOPRIVCFGR_WIOPRIV1 BIT(0)
+#define PWR_WIOPRIVCFGR_WIOPRIV2 BIT(1)
+#define PWR_WIOPRIVCFGR_WIOPRIV3 BIT(2)
+#define PWR_WIOPRIVCFGR_WIOPRIV4 BIT(3)
+#define PWR_WIOPRIVCFGR_WIOPRIV5 BIT(4)
+#define PWR_WIOPRIVCFGR_WIOPRIV6 BIT(5)
+
+/* PWR_WIO1CIDCFGR register fields */
+#define PWR_WIO1CIDCFGR_CFEN BIT(0)
+#define PWR_WIO1CIDCFGR_SEM_EN BIT(1)
+#define PWR_WIO1CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO1CIDCFGR_SCID_SHIFT 4
+#define PWR_WIO1CIDCFGR_SEMWLC0 BIT(16)
+#define PWR_WIO1CIDCFGR_SEMWLC1 BIT(17)
+#define PWR_WIO1CIDCFGR_SEMWLC2 BIT(18)
+#define PWR_WIO1CIDCFGR_SEMWLC3 BIT(19)
+#define PWR_WIO1CIDCFGR_SEMWLC4 BIT(20)
+#define PWR_WIO1CIDCFGR_SEMWLC5 BIT(21)
+#define PWR_WIO1CIDCFGR_SEMWLC6 BIT(22)
+#define PWR_WIO1CIDCFGR_SEMWLC7 BIT(23)
+
+/* PWR_WIO1SEMCR register fields */
+#define PWR_WIO1SEMCR_SEM_MUTEX BIT(0)
+#define PWR_WIO1SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO1SEMCR_SEMCID_SHIFT 4
+
+/* PWR_WIO2CIDCFGR register fields */
+#define PWR_WIO2CIDCFGR_CFEN BIT(0)
+#define PWR_WIO2CIDCFGR_SEM_EN BIT(1)
+#define PWR_WIO2CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO2CIDCFGR_SCID_SHIFT 4
+#define PWR_WIO2CIDCFGR_SEMWLC0 BIT(16)
+#define PWR_WIO2CIDCFGR_SEMWLC1 BIT(17)
+#define PWR_WIO2CIDCFGR_SEMWLC2 BIT(18)
+#define PWR_WIO2CIDCFGR_SEMWLC3 BIT(19)
+#define PWR_WIO2CIDCFGR_SEMWLC4 BIT(20)
+#define PWR_WIO2CIDCFGR_SEMWLC5 BIT(21)
+#define PWR_WIO2CIDCFGR_SEMWLC6 BIT(22)
+#define PWR_WIO2CIDCFGR_SEMWLC7 BIT(23)
+
+/* PWR_WIO2SEMCR register fields */
+#define PWR_WIO2SEMCR_SEM_MUTEX BIT(0)
+#define PWR_WIO2SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO2SEMCR_SEMCID_SHIFT 4
+
+/* PWR_WIO3CIDCFGR register fields */
+#define PWR_WIO3CIDCFGR_CFEN BIT(0)
+#define PWR_WIO3CIDCFGR_SEM_EN BIT(1)
+#define PWR_WIO3CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO3CIDCFGR_SCID_SHIFT 4
+#define PWR_WIO3CIDCFGR_SEMWLC0 BIT(16)
+#define PWR_WIO3CIDCFGR_SEMWLC1 BIT(17)
+#define PWR_WIO3CIDCFGR_SEMWLC2 BIT(18)
+#define PWR_WIO3CIDCFGR_SEMWLC3 BIT(19)
+#define PWR_WIO3CIDCFGR_SEMWLC4 BIT(20)
+#define PWR_WIO3CIDCFGR_SEMWLC5 BIT(21)
+#define PWR_WIO3CIDCFGR_SEMWLC6 BIT(22)
+#define PWR_WIO3CIDCFGR_SEMWLC7 BIT(23)
+
+/* PWR_WIO3SEMCR register fields */
+#define PWR_WIO3SEMCR_SEM_MUTEX BIT(0)
+#define PWR_WIO3SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO3SEMCR_SEMCID_SHIFT 4
+
+/* PWR_WIO4CIDCFGR register fields */
+#define PWR_WIO4CIDCFGR_CFEN BIT(0)
+#define PWR_WIO4CIDCFGR_SEM_EN BIT(1)
+#define PWR_WIO4CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO4CIDCFGR_SCID_SHIFT 4
+#define PWR_WIO4CIDCFGR_SEMWLC0 BIT(16)
+#define PWR_WIO4CIDCFGR_SEMWLC1 BIT(17)
+#define PWR_WIO4CIDCFGR_SEMWLC2 BIT(18)
+#define PWR_WIO4CIDCFGR_SEMWLC3 BIT(19)
+#define PWR_WIO4CIDCFGR_SEMWLC4 BIT(20)
+#define PWR_WIO4CIDCFGR_SEMWLC5 BIT(21)
+#define PWR_WIO4CIDCFGR_SEMWLC6 BIT(22)
+#define PWR_WIO4CIDCFGR_SEMWLC7 BIT(23)
+
+/* PWR_WIO4SEMCR register fields */
+#define PWR_WIO4SEMCR_SEM_MUTEX BIT(0)
+#define PWR_WIO4SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO4SEMCR_SEMCID_SHIFT 4
+
+/* PWR_WIO5CIDCFGR register fields */
+#define PWR_WIO5CIDCFGR_CFEN BIT(0)
+#define PWR_WIO5CIDCFGR_SEM_EN BIT(1)
+#define PWR_WIO5CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO5CIDCFGR_SCID_SHIFT 4
+#define PWR_WIO5CIDCFGR_SEMWLC0 BIT(16)
+#define PWR_WIO5CIDCFGR_SEMWLC1 BIT(17)
+#define PWR_WIO5CIDCFGR_SEMWLC2 BIT(18)
+#define PWR_WIO5CIDCFGR_SEMWLC3 BIT(19)
+#define PWR_WIO5CIDCFGR_SEMWLC4 BIT(20)
+#define PWR_WIO5CIDCFGR_SEMWLC5 BIT(21)
+#define PWR_WIO5CIDCFGR_SEMWLC6 BIT(22)
+#define PWR_WIO5CIDCFGR_SEMWLC7 BIT(23)
+
+/* PWR_WIO5SEMCR register fields */
+#define PWR_WIO5SEMCR_SEM_MUTEX BIT(0)
+#define PWR_WIO5SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO5SEMCR_SEMCID_SHIFT 4
+
+/* PWR_WIO6CIDCFGR register fields */
+#define PWR_WIO6CIDCFGR_CFEN BIT(0)
+#define PWR_WIO6CIDCFGR_SEM_EN BIT(1)
+#define PWR_WIO6CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO6CIDCFGR_SCID_SHIFT 4
+#define PWR_WIO6CIDCFGR_SEMWLC0 BIT(16)
+#define PWR_WIO6CIDCFGR_SEMWLC1 BIT(17)
+#define PWR_WIO6CIDCFGR_SEMWLC2 BIT(18)
+#define PWR_WIO6CIDCFGR_SEMWLC3 BIT(19)
+#define PWR_WIO6CIDCFGR_SEMWLC4 BIT(20)
+#define PWR_WIO6CIDCFGR_SEMWLC5 BIT(21)
+#define PWR_WIO6CIDCFGR_SEMWLC6 BIT(22)
+#define PWR_WIO6CIDCFGR_SEMWLC7 BIT(23)
+
+/* PWR_WIO6SEMCR register fields */
+#define PWR_WIO6SEMCR_SEM_MUTEX BIT(0)
+#define PWR_WIO6SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO6SEMCR_SEMCID_SHIFT 4
+
+/* PWR_CPU1D1SR register fields */
+#define PWR_CPU1D1SR_HOLD_BOOT BIT(0)
+#define PWR_CPU1D1SR_CSTATE_MASK GENMASK_32(3, 2)
+#define PWR_CPU1D1SR_CSTATE_SHIFT 2
+#define PWR_CPU1D1SR_DSTATE_MASK GENMASK_32(10, 8)
+#define PWR_CPU1D1SR_DSTATE_SHIFT 8
+
+/* PWR_CPU2D2SR register fields */
+#define PWR_CPU2D2SR_HOLD_BOOT BIT(0)
+#define PWR_CPU2D2SR_WFBEN BIT(1)
+#define PWR_CPU2D2SR_CSTATE_MASK GENMASK_32(3, 2)
+#define PWR_CPU2D2SR_CSTATE_SHIFT 2
+#define PWR_CPU2D2SR_DSTATE_MASK GENMASK_32(10, 8)
+#define PWR_CPU2D2SR_DSTATE_SHIFT 8
+
+/* PWR_DBGR register fields */
+#define PWR_DBGR_VDDIOKRETRAM BIT(16)
+#define PWR_DBGR_VDDIOKBKPRAM BIT(17)
+
+/* PWR_VERR register fields */
+#define PWR_VERR_MINREV_MASK GENMASK_32(3, 0)
+#define PWR_VERR_MINREV_SHIFT 0
+#define PWR_VERR_MAJREV_MASK GENMASK_32(7, 4)
+#define PWR_VERR_MAJREV_SHIFT 4
+
+#endif /* STM32MP21_PWR_H */
+
diff --git a/include/drivers/st/stm32mp21_rcc.h b/include/drivers/st/stm32mp21_rcc.h
new file mode 100644
index 0000000..a3787d0
--- /dev/null
+++ b/include/drivers/st/stm32mp21_rcc.h
@@ -0,0 +1,4668 @@
+/*
+ * Copyright (c) 2025, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP21_RCC_H
+#define STM32MP21_RCC_H
+
+#include <lib/utils_def.h>
+
+#define RCC_SECCFGR0 U(0x0)
+#define RCC_SECCFGR1 U(0x4)
+#define RCC_SECCFGR2 U(0x8)
+#define RCC_SECCFGR3 U(0xC)
+#define RCC_PRIVCFGR0 U(0x10)
+#define RCC_PRIVCFGR1 U(0x14)
+#define RCC_PRIVCFGR2 U(0x18)
+#define RCC_PRIVCFGR3 U(0x1C)
+#define RCC_RCFGLOCKR0 U(0x20)
+#define RCC_RCFGLOCKR1 U(0x24)
+#define RCC_RCFGLOCKR2 U(0x28)
+#define RCC_RCFGLOCKR3 U(0x2C)
+#define RCC_R0CIDCFGR U(0x30)
+#define RCC_R0SEMCR U(0x34)
+#define RCC_R1CIDCFGR U(0x38)
+#define RCC_R1SEMCR U(0x3C)
+#define RCC_R2CIDCFGR U(0x40)
+#define RCC_R2SEMCR U(0x44)
+#define RCC_R3CIDCFGR U(0x48)
+#define RCC_R3SEMCR U(0x4C)
+#define RCC_R4CIDCFGR U(0x50)
+#define RCC_R4SEMCR U(0x54)
+#define RCC_R5CIDCFGR U(0x58)
+#define RCC_R5SEMCR U(0x5C)
+#define RCC_R6CIDCFGR U(0x60)
+#define RCC_R6SEMCR U(0x64)
+#define RCC_R7CIDCFGR U(0x68)
+#define RCC_R7SEMCR U(0x6C)
+#define RCC_R8CIDCFGR U(0x70)
+#define RCC_R8SEMCR U(0x74)
+#define RCC_R9CIDCFGR U(0x78)
+#define RCC_R9SEMCR U(0x7C)
+#define RCC_R10CIDCFGR U(0x80)
+#define RCC_R10SEMCR U(0x84)
+#define RCC_R11CIDCFGR U(0x88)
+#define RCC_R11SEMCR U(0x8C)
+#define RCC_R12CIDCFGR U(0x90)
+#define RCC_R12SEMCR U(0x94)
+#define RCC_R13CIDCFGR U(0x98)
+#define RCC_R13SEMCR U(0x9C)
+#define RCC_R14CIDCFGR U(0xA0)
+#define RCC_R14SEMCR U(0xA4)
+#define RCC_R15CIDCFGR U(0xA8)
+#define RCC_R15SEMCR U(0xAC)
+#define RCC_R16CIDCFGR U(0xB0)
+#define RCC_R16SEMCR U(0xB4)
+#define RCC_R17CIDCFGR U(0xB8)
+#define RCC_R17SEMCR U(0xBC)
+#define RCC_R18CIDCFGR U(0xC0)
+#define RCC_R18SEMCR U(0xC4)
+#define RCC_R19CIDCFGR U(0xC8)
+#define RCC_R19SEMCR U(0xCC)
+#define RCC_R20CIDCFGR U(0xD0)
+#define RCC_R20SEMCR U(0xD4)
+#define RCC_R21CIDCFGR U(0xD8)
+#define RCC_R21SEMCR U(0xDC)
+#define RCC_R22CIDCFGR U(0xE0)
+#define RCC_R22SEMCR U(0xE4)
+#define RCC_R23CIDCFGR U(0xE8)
+#define RCC_R23SEMCR U(0xEC)
+#define RCC_R24CIDCFGR U(0xF0)
+#define RCC_R24SEMCR U(0xF4)
+#define RCC_R25CIDCFGR U(0xF8)
+#define RCC_R25SEMCR U(0xFC)
+#define RCC_R26CIDCFGR U(0x100)
+#define RCC_R26SEMCR U(0x104)
+#define RCC_R27CIDCFGR U(0x108)
+#define RCC_R27SEMCR U(0x10C)
+#define RCC_R28CIDCFGR U(0x110)
+#define RCC_R28SEMCR U(0x114)
+#define RCC_R29CIDCFGR U(0x118)
+#define RCC_R29SEMCR U(0x11C)
+#define RCC_R30CIDCFGR U(0x120)
+#define RCC_R30SEMCR U(0x124)
+#define RCC_R31CIDCFGR U(0x128)
+#define RCC_R31SEMCR U(0x12C)
+#define RCC_R32CIDCFGR U(0x130)
+#define RCC_R32SEMCR U(0x134)
+#define RCC_R33CIDCFGR U(0x138)
+#define RCC_R33SEMCR U(0x13C)
+#define RCC_R34CIDCFGR U(0x140)
+#define RCC_R34SEMCR U(0x144)
+#define RCC_R35CIDCFGR U(0x148)
+#define RCC_R35SEMCR U(0x14C)
+#define RCC_R36CIDCFGR U(0x150)
+#define RCC_R36SEMCR U(0x154)
+#define RCC_R37CIDCFGR U(0x158)
+#define RCC_R37SEMCR U(0x15C)
+#define RCC_R38CIDCFGR U(0x160)
+#define RCC_R38SEMCR U(0x164)
+#define RCC_R39CIDCFGR U(0x168)
+#define RCC_R39SEMCR U(0x16C)
+#define RCC_R40CIDCFGR U(0x170)
+#define RCC_R40SEMCR U(0x174)
+#define RCC_R41CIDCFGR U(0x178)
+#define RCC_R41SEMCR U(0x17C)
+#define RCC_R42CIDCFGR U(0x180)
+#define RCC_R42SEMCR U(0x184)
+#define RCC_R43CIDCFGR U(0x188)
+#define RCC_R43SEMCR U(0x18C)
+#define RCC_R44CIDCFGR U(0x190)
+#define RCC_R44SEMCR U(0x194)
+#define RCC_R45CIDCFGR U(0x198)
+#define RCC_R45SEMCR U(0x19C)
+#define RCC_R46CIDCFGR U(0x1A0)
+#define RCC_R46SEMCR U(0x1A4)
+#define RCC_R47CIDCFGR U(0x1A8)
+#define RCC_R47SEMCR U(0x1AC)
+#define RCC_R48CIDCFGR U(0x1B0)
+#define RCC_R48SEMCR U(0x1B4)
+#define RCC_R49CIDCFGR U(0x1B8)
+#define RCC_R49SEMCR U(0x1BC)
+#define RCC_R50CIDCFGR U(0x1C0)
+#define RCC_R50SEMCR U(0x1C4)
+#define RCC_R51CIDCFGR U(0x1C8)
+#define RCC_R51SEMCR U(0x1CC)
+#define RCC_R52CIDCFGR U(0x1D0)
+#define RCC_R52SEMCR U(0x1D4)
+#define RCC_R53CIDCFGR U(0x1D8)
+#define RCC_R53SEMCR U(0x1DC)
+#define RCC_R54CIDCFGR U(0x1E0)
+#define RCC_R54SEMCR U(0x1E4)
+#define RCC_R55CIDCFGR U(0x1E8)
+#define RCC_R55SEMCR U(0x1EC)
+#define RCC_R56CIDCFGR U(0x1F0)
+#define RCC_R56SEMCR U(0x1F4)
+#define RCC_R57CIDCFGR U(0x1F8)
+#define RCC_R57SEMCR U(0x1FC)
+#define RCC_R58CIDCFGR U(0x200)
+#define RCC_R58SEMCR U(0x204)
+#define RCC_R59CIDCFGR U(0x208)
+#define RCC_R59SEMCR U(0x20C)
+#define RCC_R60CIDCFGR U(0x210)
+#define RCC_R60SEMCR U(0x214)
+#define RCC_R61CIDCFGR U(0x218)
+#define RCC_R61SEMCR U(0x21C)
+#define RCC_R62CIDCFGR U(0x220)
+#define RCC_R62SEMCR U(0x224)
+#define RCC_R63CIDCFGR U(0x228)
+#define RCC_R63SEMCR U(0x22C)
+#define RCC_R64CIDCFGR U(0x230)
+#define RCC_R64SEMCR U(0x234)
+#define RCC_R65CIDCFGR U(0x238)
+#define RCC_R65SEMCR U(0x23C)
+#define RCC_R66CIDCFGR U(0x240)
+#define RCC_R66SEMCR U(0x244)
+#define RCC_R67CIDCFGR U(0x248)
+#define RCC_R67SEMCR U(0x24C)
+#define RCC_R68CIDCFGR U(0x250)
+#define RCC_R68SEMCR U(0x254)
+#define RCC_R69CIDCFGR U(0x258)
+#define RCC_R69SEMCR U(0x25C)
+#define RCC_R70CIDCFGR U(0x260)
+#define RCC_R70SEMCR U(0x264)
+#define RCC_R71CIDCFGR U(0x268)
+#define RCC_R71SEMCR U(0x26C)
+#define RCC_R72CIDCFGR U(0x270)
+#define RCC_R72SEMCR U(0x274)
+#define RCC_R73CIDCFGR U(0x278)
+#define RCC_R73SEMCR U(0x27C)
+#define RCC_R74CIDCFGR U(0x280)
+#define RCC_R74SEMCR U(0x284)
+#define RCC_R75CIDCFGR U(0x288)
+#define RCC_R75SEMCR U(0x28C)
+#define RCC_R76CIDCFGR U(0x290)
+#define RCC_R76SEMCR U(0x294)
+#define RCC_R77CIDCFGR U(0x298)
+#define RCC_R77SEMCR U(0x29C)
+#define RCC_R78CIDCFGR U(0x2A0)
+#define RCC_R78SEMCR U(0x2A4)
+#define RCC_R79CIDCFGR U(0x2A8)
+#define RCC_R79SEMCR U(0x2AC)
+#define RCC_R80CIDCFGR U(0x2B0)
+#define RCC_R80SEMCR U(0x2B4)
+#define RCC_R81CIDCFGR U(0x2B8)
+#define RCC_R81SEMCR U(0x2BC)
+#define RCC_R82CIDCFGR U(0x2C0)
+#define RCC_R82SEMCR U(0x2C4)
+#define RCC_R83CIDCFGR U(0x2C8)
+#define RCC_R83SEMCR U(0x2CC)
+#define RCC_R84CIDCFGR U(0x2D0)
+#define RCC_R84SEMCR U(0x2D4)
+#define RCC_R85CIDCFGR U(0x2D8)
+#define RCC_R85SEMCR U(0x2DC)
+#define RCC_R86CIDCFGR U(0x2E0)
+#define RCC_R86SEMCR U(0x2E4)
+#define RCC_R87CIDCFGR U(0x2E8)
+#define RCC_R87SEMCR U(0x2EC)
+#define RCC_R88CIDCFGR U(0x2F0)
+#define RCC_R88SEMCR U(0x2F4)
+#define RCC_R89CIDCFGR U(0x2F8)
+#define RCC_R89SEMCR U(0x2FC)
+#define RCC_R90CIDCFGR U(0x300)
+#define RCC_R90SEMCR U(0x304)
+#define RCC_R91CIDCFGR U(0x308)
+#define RCC_R91SEMCR U(0x30C)
+#define RCC_R92CIDCFGR U(0x310)
+#define RCC_R92SEMCR U(0x314)
+#define RCC_R93CIDCFGR U(0x318)
+#define RCC_R93SEMCR U(0x31C)
+#define RCC_R94CIDCFGR U(0x320)
+#define RCC_R94SEMCR U(0x324)
+#define RCC_R95CIDCFGR U(0x328)
+#define RCC_R95SEMCR U(0x32C)
+#define RCC_R96CIDCFGR U(0x330)
+#define RCC_R96SEMCR U(0x334)
+#define RCC_R97CIDCFGR U(0x338)
+#define RCC_R97SEMCR U(0x33C)
+#define RCC_R98CIDCFGR U(0x340)
+#define RCC_R98SEMCR U(0x344)
+#define RCC_R99CIDCFGR U(0x348)
+#define RCC_R99SEMCR U(0x34C)
+#define RCC_R100CIDCFGR U(0x350)
+#define RCC_R100SEMCR U(0x354)
+#define RCC_R101CIDCFGR U(0x358)
+#define RCC_R101SEMCR U(0x35C)
+#define RCC_R102CIDCFGR U(0x360)
+#define RCC_R102SEMCR U(0x364)
+#define RCC_R103CIDCFGR U(0x368)
+#define RCC_R103SEMCR U(0x36C)
+#define RCC_R104CIDCFGR U(0x370)
+#define RCC_R104SEMCR U(0x374)
+#define RCC_R105CIDCFGR U(0x378)
+#define RCC_R105SEMCR U(0x37C)
+#define RCC_R106CIDCFGR U(0x380)
+#define RCC_R106SEMCR U(0x384)
+#define RCC_R107CIDCFGR U(0x388)
+#define RCC_R107SEMCR U(0x38C)
+#define RCC_R108CIDCFGR U(0x390)
+#define RCC_R108SEMCR U(0x394)
+#define RCC_R109CIDCFGR U(0x398)
+#define RCC_R109SEMCR U(0x39C)
+#define RCC_R110CIDCFGR U(0x3A0)
+#define RCC_R110SEMCR U(0x3A4)
+#define RCC_R111CIDCFGR U(0x3A8)
+#define RCC_R111SEMCR U(0x3AC)
+#define RCC_R112CIDCFGR U(0x3B0)
+#define RCC_R112SEMCR U(0x3B4)
+#define RCC_R113CIDCFGR U(0x3B8)
+#define RCC_R113SEMCR U(0x3BC)
+#define RCC_GRSTCSETR U(0x400)
+#define RCC_C1RSTCSETR U(0x404)
+#define RCC_C2RSTCSETR U(0x40C)
+#define RCC_HWRSTSCLRR U(0x410)
+#define RCC_C1HWRSTSCLRR U(0x414)
+#define RCC_C2HWRSTSCLRR U(0x418)
+#define RCC_C1BOOTRSTSSETR U(0x41C)
+#define RCC_C1BOOTRSTSCLRR U(0x420)
+#define RCC_C2BOOTRSTSSETR U(0x424)
+#define RCC_C2BOOTRSTSCLRR U(0x428)
+#define RCC_C1SREQSETR U(0x42C)
+#define RCC_C1SREQCLRR U(0x430)
+#define RCC_CPUBOOTCR U(0x434)
+#define RCC_STBYBOOTCR U(0x438)
+#define RCC_LEGBOOTCR U(0x43C)
+#define RCC_BDCR U(0x440)
+#define RCC_RDCR U(0x44C)
+#define RCC_C1MSRDCR U(0x450)
+#define RCC_PWRLPDLYCR U(0x454)
+#define RCC_C1CIESETR U(0x458)
+#define RCC_C1CIFCLRR U(0x45C)
+#define RCC_C2CIESETR U(0x460)
+#define RCC_C2CIFCLRR U(0x464)
+#define RCC_IWDGC1FZSETR U(0x468)
+#define RCC_IWDGC1FZCLRR U(0x46C)
+#define RCC_IWDGC1CFGSETR U(0x470)
+#define RCC_IWDGC1CFGCLRR U(0x474)
+#define RCC_IWDGC2FZSETR U(0x478)
+#define RCC_IWDGC2FZCLRR U(0x47C)
+#define RCC_IWDGC2CFGSETR U(0x480)
+#define RCC_IWDGC2CFGCLRR U(0x484)
+#define RCC_MCO1CFGR U(0x488)
+#define RCC_MCO2CFGR U(0x48C)
+#define RCC_OCENSETR U(0x490)
+#define RCC_OCENCLRR U(0x494)
+#define RCC_OCRDYR U(0x498)
+#define RCC_HSICFGR U(0x49C)
+#define RCC_MSICFGR U(0x4A0)
+#define RCC_LSICR U(0x4A4)
+#define RCC_RTCDIVR U(0x4A8)
+#define RCC_APB1DIVR U(0x4AC)
+#define RCC_APB2DIVR U(0x4B0)
+#define RCC_APB3DIVR U(0x4B4)
+#define RCC_APB4DIVR U(0x4B8)
+#define RCC_APB5DIVR U(0x4BC)
+#define RCC_APBDBGDIVR U(0x4C0)
+#define RCC_TIMG1PRER U(0x4C8)
+#define RCC_TIMG2PRER U(0x4CC)
+#define RCC_LSMCUDIVR U(0x4D0)
+#define RCC_DDRCPCFGR U(0x4D4)
+#define RCC_DDRCAPBCFGR U(0x4D8)
+#define RCC_DDRPHYCAPBCFGR U(0x4DC)
+#define RCC_DDRPHYCCFGR U(0x4E0)
+#define RCC_DDRCFGR U(0x4E4)
+#define RCC_DDRITFCFGR U(0x4E8)
+#define RCC_SYSRAMCFGR U(0x4F0)
+#define RCC_SRAM1CFGR U(0x4F8)
+#define RCC_RETRAMCFGR U(0x500)
+#define RCC_BKPSRAMCFGR U(0x504)
+#define RCC_OSPI1CFGR U(0x514)
+#define RCC_FMCCFGR U(0x51C)
+#define RCC_DBGCFGR U(0x520)
+#define RCC_STMCFGR U(0x524)
+#define RCC_ETRCFGR U(0x528)
+#define RCC_GPIOACFGR U(0x52C)
+#define RCC_GPIOBCFGR U(0x530)
+#define RCC_GPIOCCFGR U(0x534)
+#define RCC_GPIODCFGR U(0x538)
+#define RCC_GPIOECFGR U(0x53C)
+#define RCC_GPIOFCFGR U(0x540)
+#define RCC_GPIOGCFGR U(0x544)
+#define RCC_GPIOHCFGR U(0x548)
+#define RCC_GPIOICFGR U(0x54C)
+#define RCC_GPIOZCFGR U(0x558)
+#define RCC_HPDMA1CFGR U(0x55C)
+#define RCC_HPDMA2CFGR U(0x560)
+#define RCC_HPDMA3CFGR U(0x564)
+#define RCC_IPCC1CFGR U(0x570)
+#define RCC_RTCCFGR U(0x578)
+#define RCC_SYSCPU1CFGR U(0x580)
+#define RCC_BSECCFGR U(0x584)
+#define RCC_PLL2CFGR1 U(0x590)
+#define RCC_PLL2CFGR2 U(0x594)
+#define RCC_PLL2CFGR3 U(0x598)
+#define RCC_PLL2CFGR4 U(0x59C)
+#define RCC_PLL2CFGR5 U(0x5A0)
+#define RCC_PLL2CFGR6 U(0x5A8)
+#define RCC_PLL2CFGR7 U(0x5AC)
+#define RCC_HSIFMONCR U(0x5E0)
+#define RCC_HSIFVALR U(0x5E4)
+#define RCC_MSIFMONCR U(0x5E8)
+#define RCC_MSIFVALR U(0x5EC)
+#define RCC_TIM1CFGR U(0x700)
+#define RCC_TIM2CFGR U(0x704)
+#define RCC_TIM3CFGR U(0x708)
+#define RCC_TIM4CFGR U(0x70C)
+#define RCC_TIM5CFGR U(0x710)
+#define RCC_TIM6CFGR U(0x714)
+#define RCC_TIM7CFGR U(0x718)
+#define RCC_TIM8CFGR U(0x71C)
+#define RCC_TIM10CFGR U(0x720)
+#define RCC_TIM11CFGR U(0x724)
+#define RCC_TIM12CFGR U(0x728)
+#define RCC_TIM13CFGR U(0x72C)
+#define RCC_TIM14CFGR U(0x730)
+#define RCC_TIM15CFGR U(0x734)
+#define RCC_TIM16CFGR U(0x738)
+#define RCC_TIM17CFGR U(0x73C)
+#define RCC_LPTIM1CFGR U(0x744)
+#define RCC_LPTIM2CFGR U(0x748)
+#define RCC_LPTIM3CFGR U(0x74C)
+#define RCC_LPTIM4CFGR U(0x750)
+#define RCC_LPTIM5CFGR U(0x754)
+#define RCC_SPI1CFGR U(0x758)
+#define RCC_SPI2CFGR U(0x75C)
+#define RCC_SPI3CFGR U(0x760)
+#define RCC_SPI4CFGR U(0x764)
+#define RCC_SPI5CFGR U(0x768)
+#define RCC_SPI6CFGR U(0x76C)
+#define RCC_SPDIFRXCFGR U(0x778)
+#define RCC_USART1CFGR U(0x77C)
+#define RCC_USART2CFGR U(0x780)
+#define RCC_USART3CFGR U(0x784)
+#define RCC_UART4CFGR U(0x788)
+#define RCC_UART5CFGR U(0x78C)
+#define RCC_USART6CFGR U(0x790)
+#define RCC_UART7CFGR U(0x794)
+#define RCC_LPUART1CFGR U(0x7A0)
+#define RCC_I2C1CFGR U(0x7A4)
+#define RCC_I2C2CFGR U(0x7A8)
+#define RCC_I2C3CFGR U(0x7AC)
+#define RCC_SAI1CFGR U(0x7C4)
+#define RCC_SAI2CFGR U(0x7C8)
+#define RCC_SAI3CFGR U(0x7CC)
+#define RCC_SAI4CFGR U(0x7D0)
+#define RCC_MDF1CFGR U(0x7D8)
+#define RCC_FDCANCFGR U(0x7E0)
+#define RCC_HDPCFGR U(0x7E4)
+#define RCC_ADC1CFGR U(0x7E8)
+#define RCC_ADC2CFGR U(0x7EC)
+#define RCC_ETH1CFGR U(0x7F0)
+#define RCC_ETH2CFGR U(0x7F4)
+#define RCC_USBHCFGR U(0x7FC)
+#define RCC_USB2PHY1CFGR U(0x800)
+#define RCC_OTGCFGR U(0x808)
+#define RCC_USB2PHY2CFGR U(0x80C)
+#define RCC_STGENCFGR U(0x824)
+#define RCC_SDMMC1CFGR U(0x830)
+#define RCC_SDMMC2CFGR U(0x834)
+#define RCC_SDMMC3CFGR U(0x838)
+#define RCC_LTDCCFGR U(0x840)
+#define RCC_CSICFGR U(0x858)
+#define RCC_DCMIPPCFGR U(0x85C)
+#define RCC_DCMIPSSICFGR U(0x860)
+#define RCC_RNG1CFGR U(0x870)
+#define RCC_RNG2CFGR U(0x874)
+#define RCC_PKACFGR U(0x878)
+#define RCC_SAESCFGR U(0x87C)
+#define RCC_HASH1CFGR U(0x880)
+#define RCC_HASH2CFGR U(0x884)
+#define RCC_CRYP1CFGR U(0x888)
+#define RCC_CRYP2CFGR U(0x88C)
+#define RCC_IWDG1CFGR U(0x894)
+#define RCC_IWDG2CFGR U(0x898)
+#define RCC_IWDG3CFGR U(0x89C)
+#define RCC_IWDG4CFGR U(0x8A0)
+#define RCC_WWDG1CFGR U(0x8A4)
+#define RCC_VREFCFGR U(0x8AC)
+#define RCC_DTSCFGR U(0x8B0)
+#define RCC_CRCCFGR U(0x8B4)
+#define RCC_SERCCFGR U(0x8B8)
+#define RCC_DDRPERFMCFGR U(0x8C0)
+#define RCC_I3C1CFGR U(0x8C8)
+#define RCC_I3C2CFGR U(0x8CC)
+#define RCC_I3C3CFGR U(0x8D0)
+#define RCC_MUXSELCFGR U(0x1000)
+#define RCC_XBAR0CFGR U(0x1018)
+#define RCC_XBAR1CFGR U(0x101C)
+#define RCC_XBAR2CFGR U(0x1020)
+#define RCC_XBAR3CFGR U(0x1024)
+#define RCC_XBAR4CFGR U(0x1028)
+#define RCC_XBAR5CFGR U(0x102C)
+#define RCC_XBAR6CFGR U(0x1030)
+#define RCC_XBAR7CFGR U(0x1034)
+#define RCC_XBAR8CFGR U(0x1038)
+#define RCC_XBAR9CFGR U(0x103C)
+#define RCC_XBAR10CFGR U(0x1040)
+#define RCC_XBAR11CFGR U(0x1044)
+#define RCC_XBAR12CFGR U(0x1048)
+#define RCC_XBAR13CFGR U(0x104C)
+#define RCC_XBAR14CFGR U(0x1050)
+#define RCC_XBAR15CFGR U(0x1054)
+#define RCC_XBAR16CFGR U(0x1058)
+#define RCC_XBAR17CFGR U(0x105C)
+#define RCC_XBAR18CFGR U(0x1060)
+#define RCC_XBAR19CFGR U(0x1064)
+#define RCC_XBAR20CFGR U(0x1068)
+#define RCC_XBAR21CFGR U(0x106C)
+#define RCC_XBAR22CFGR U(0x1070)
+#define RCC_XBAR23CFGR U(0x1074)
+#define RCC_XBAR24CFGR U(0x1078)
+#define RCC_XBAR25CFGR U(0x107C)
+#define RCC_XBAR26CFGR U(0x1080)
+#define RCC_XBAR27CFGR U(0x1084)
+#define RCC_XBAR28CFGR U(0x1088)
+#define RCC_XBAR29CFGR U(0x108C)
+#define RCC_XBAR30CFGR U(0x1090)
+#define RCC_XBAR31CFGR U(0x1094)
+#define RCC_XBAR32CFGR U(0x1098)
+#define RCC_XBAR33CFGR U(0x109C)
+#define RCC_XBAR34CFGR U(0x10A0)
+#define RCC_XBAR35CFGR U(0x10A4)
+#define RCC_XBAR36CFGR U(0x10A8)
+#define RCC_XBAR37CFGR U(0x10AC)
+#define RCC_XBAR38CFGR U(0x10B0)
+#define RCC_XBAR39CFGR U(0x10B4)
+#define RCC_XBAR40CFGR U(0x10B8)
+#define RCC_XBAR41CFGR U(0x10BC)
+#define RCC_XBAR42CFGR U(0x10C0)
+#define RCC_XBAR43CFGR U(0x10C4)
+#define RCC_XBAR44CFGR U(0x10C8)
+#define RCC_XBAR45CFGR U(0x10CC)
+#define RCC_XBAR46CFGR U(0x10D0)
+#define RCC_XBAR47CFGR U(0x10D4)
+#define RCC_XBAR48CFGR U(0x10D8)
+#define RCC_XBAR49CFGR U(0x10DC)
+#define RCC_XBAR50CFGR U(0x10E0)
+#define RCC_XBAR51CFGR U(0x10E4)
+#define RCC_XBAR52CFGR U(0x10E8)
+#define RCC_XBAR53CFGR U(0x10EC)
+#define RCC_XBAR54CFGR U(0x10F0)
+#define RCC_XBAR55CFGR U(0x10F4)
+#define RCC_XBAR56CFGR U(0x10F8)
+#define RCC_XBAR57CFGR U(0x10FC)
+#define RCC_XBAR58CFGR U(0x1100)
+#define RCC_XBAR59CFGR U(0x1104)
+#define RCC_XBAR60CFGR U(0x1108)
+#define RCC_XBAR61CFGR U(0x110C)
+#define RCC_XBAR62CFGR U(0x1110)
+#define RCC_XBAR63CFGR U(0x1114)
+#define RCC_PREDIV0CFGR U(0x1118)
+#define RCC_PREDIV1CFGR U(0x111C)
+#define RCC_PREDIV2CFGR U(0x1120)
+#define RCC_PREDIV3CFGR U(0x1124)
+#define RCC_PREDIV4CFGR U(0x1128)
+#define RCC_PREDIV5CFGR U(0x112C)
+#define RCC_PREDIV6CFGR U(0x1130)
+#define RCC_PREDIV7CFGR U(0x1134)
+#define RCC_PREDIV8CFGR U(0x1138)
+#define RCC_PREDIV9CFGR U(0x113C)
+#define RCC_PREDIV10CFGR U(0x1140)
+#define RCC_PREDIV11CFGR U(0x1144)
+#define RCC_PREDIV12CFGR U(0x1148)
+#define RCC_PREDIV13CFGR U(0x114C)
+#define RCC_PREDIV14CFGR U(0x1150)
+#define RCC_PREDIV15CFGR U(0x1154)
+#define RCC_PREDIV16CFGR U(0x1158)
+#define RCC_PREDIV17CFGR U(0x115C)
+#define RCC_PREDIV18CFGR U(0x1160)
+#define RCC_PREDIV19CFGR U(0x1164)
+#define RCC_PREDIV20CFGR U(0x1168)
+#define RCC_PREDIV21CFGR U(0x116C)
+#define RCC_PREDIV22CFGR U(0x1170)
+#define RCC_PREDIV23CFGR U(0x1174)
+#define RCC_PREDIV24CFGR U(0x1178)
+#define RCC_PREDIV25CFGR U(0x117C)
+#define RCC_PREDIV26CFGR U(0x1180)
+#define RCC_PREDIV27CFGR U(0x1184)
+#define RCC_PREDIV28CFGR U(0x1188)
+#define RCC_PREDIV29CFGR U(0x118C)
+#define RCC_PREDIV30CFGR U(0x1190)
+#define RCC_PREDIV31CFGR U(0x1194)
+#define RCC_PREDIV32CFGR U(0x1198)
+#define RCC_PREDIV33CFGR U(0x119C)
+#define RCC_PREDIV34CFGR U(0x11A0)
+#define RCC_PREDIV35CFGR U(0x11A4)
+#define RCC_PREDIV36CFGR U(0x11A8)
+#define RCC_PREDIV37CFGR U(0x11AC)
+#define RCC_PREDIV38CFGR U(0x11B0)
+#define RCC_PREDIV39CFGR U(0x11B4)
+#define RCC_PREDIV40CFGR U(0x11B8)
+#define RCC_PREDIV41CFGR U(0x11BC)
+#define RCC_PREDIV42CFGR U(0x11C0)
+#define RCC_PREDIV43CFGR U(0x11C4)
+#define RCC_PREDIV44CFGR U(0x11C8)
+#define RCC_PREDIV45CFGR U(0x11CC)
+#define RCC_PREDIV46CFGR U(0x11D0)
+#define RCC_PREDIV47CFGR U(0x11D4)
+#define RCC_PREDIV48CFGR U(0x11D8)
+#define RCC_PREDIV49CFGR U(0x11DC)
+#define RCC_PREDIV50CFGR U(0x11E0)
+#define RCC_PREDIV51CFGR U(0x11E4)
+#define RCC_PREDIV52CFGR U(0x11E8)
+#define RCC_PREDIV53CFGR U(0x11EC)
+#define RCC_PREDIV54CFGR U(0x11F0)
+#define RCC_PREDIV55CFGR U(0x11F4)
+#define RCC_PREDIV56CFGR U(0x11F8)
+#define RCC_PREDIV57CFGR U(0x11FC)
+#define RCC_PREDIV58CFGR U(0x1200)
+#define RCC_PREDIV59CFGR U(0x1204)
+#define RCC_PREDIV60CFGR U(0x1208)
+#define RCC_PREDIV61CFGR U(0x120C)
+#define RCC_PREDIV62CFGR U(0x1210)
+#define RCC_PREDIV63CFGR U(0x1214)
+#define RCC_PREDIVSR1 U(0x1218)
+#define RCC_PREDIVSR2 U(0x121C)
+#define RCC_FINDIV0CFGR U(0x1224)
+#define RCC_FINDIV1CFGR U(0x1228)
+#define RCC_FINDIV2CFGR U(0x122C)
+#define RCC_FINDIV3CFGR U(0x1230)
+#define RCC_FINDIV4CFGR U(0x1234)
+#define RCC_FINDIV5CFGR U(0x1238)
+#define RCC_FINDIV6CFGR U(0x123C)
+#define RCC_FINDIV7CFGR U(0x1240)
+#define RCC_FINDIV8CFGR U(0x1244)
+#define RCC_FINDIV9CFGR U(0x1248)
+#define RCC_FINDIV10CFGR U(0x124C)
+#define RCC_FINDIV11CFGR U(0x1250)
+#define RCC_FINDIV12CFGR U(0x1254)
+#define RCC_FINDIV13CFGR U(0x1258)
+#define RCC_FINDIV14CFGR U(0x125C)
+#define RCC_FINDIV15CFGR U(0x1260)
+#define RCC_FINDIV16CFGR U(0x1264)
+#define RCC_FINDIV17CFGR U(0x1268)
+#define RCC_FINDIV18CFGR U(0x126C)
+#define RCC_FINDIV19CFGR U(0x1270)
+#define RCC_FINDIV20CFGR U(0x1274)
+#define RCC_FINDIV21CFGR U(0x1278)
+#define RCC_FINDIV22CFGR U(0x127C)
+#define RCC_FINDIV23CFGR U(0x1280)
+#define RCC_FINDIV24CFGR U(0x1284)
+#define RCC_FINDIV25CFGR U(0x1288)
+#define RCC_FINDIV26CFGR U(0x128C)
+#define RCC_FINDIV27CFGR U(0x1290)
+#define RCC_FINDIV28CFGR U(0x1294)
+#define RCC_FINDIV29CFGR U(0x1298)
+#define RCC_FINDIV30CFGR U(0x129C)
+#define RCC_FINDIV31CFGR U(0x12A0)
+#define RCC_FINDIV32CFGR U(0x12A4)
+#define RCC_FINDIV33CFGR U(0x12A8)
+#define RCC_FINDIV34CFGR U(0x12AC)
+#define RCC_FINDIV35CFGR U(0x12B0)
+#define RCC_FINDIV36CFGR U(0x12B4)
+#define RCC_FINDIV37CFGR U(0x12B8)
+#define RCC_FINDIV38CFGR U(0x12BC)
+#define RCC_FINDIV39CFGR U(0x12C0)
+#define RCC_FINDIV40CFGR U(0x12C4)
+#define RCC_FINDIV41CFGR U(0x12C8)
+#define RCC_FINDIV42CFGR U(0x12CC)
+#define RCC_FINDIV43CFGR U(0x12D0)
+#define RCC_FINDIV44CFGR U(0x12D4)
+#define RCC_FINDIV45CFGR U(0x12D8)
+#define RCC_FINDIV46CFGR U(0x12DC)
+#define RCC_FINDIV47CFGR U(0x12E0)
+#define RCC_FINDIV48CFGR U(0x12E4)
+#define RCC_FINDIV49CFGR U(0x12E8)
+#define RCC_FINDIV50CFGR U(0x12EC)
+#define RCC_FINDIV51CFGR U(0x12F0)
+#define RCC_FINDIV52CFGR U(0x12F4)
+#define RCC_FINDIV53CFGR U(0x12F8)
+#define RCC_FINDIV54CFGR U(0x12FC)
+#define RCC_FINDIV55CFGR U(0x1300)
+#define RCC_FINDIV56CFGR U(0x1304)
+#define RCC_FINDIV57CFGR U(0x1308)
+#define RCC_FINDIV58CFGR U(0x130C)
+#define RCC_FINDIV59CFGR U(0x1310)
+#define RCC_FINDIV60CFGR U(0x1314)
+#define RCC_FINDIV61CFGR U(0x1318)
+#define RCC_FINDIV62CFGR U(0x131C)
+#define RCC_FINDIV63CFGR U(0x1320)
+#define RCC_FINDIVSR1 U(0x1324)
+#define RCC_FINDIVSR2 U(0x1328)
+#define RCC_FCALCOBS0CFGR U(0x1340)
+#define RCC_FCALCOBS1CFGR U(0x1344)
+#define RCC_FCALCREFCFGR U(0x1348)
+#define RCC_FCALCCR1 U(0x134C)
+#define RCC_FCALCCR2 U(0x1354)
+#define RCC_FCALCSR U(0x1358)
+#define RCC_PLL4CFGR1 U(0x1360)
+#define RCC_PLL4CFGR2 U(0x1364)
+#define RCC_PLL4CFGR3 U(0x1368)
+#define RCC_PLL4CFGR4 U(0x136C)
+#define RCC_PLL4CFGR5 U(0x1370)
+#define RCC_PLL4CFGR6 U(0x1378)
+#define RCC_PLL4CFGR7 U(0x137C)
+#define RCC_PLL5CFGR1 U(0x1388)
+#define RCC_PLL5CFGR2 U(0x138C)
+#define RCC_PLL5CFGR3 U(0x1390)
+#define RCC_PLL5CFGR4 U(0x1394)
+#define RCC_PLL5CFGR5 U(0x1398)
+#define RCC_PLL5CFGR6 U(0x13A0)
+#define RCC_PLL5CFGR7 U(0x13A4)
+#define RCC_PLL6CFGR1 U(0x13B0)
+#define RCC_PLL6CFGR2 U(0x13B4)
+#define RCC_PLL6CFGR3 U(0x13B8)
+#define RCC_PLL6CFGR4 U(0x13BC)
+#define RCC_PLL6CFGR5 U(0x13C0)
+#define RCC_PLL6CFGR6 U(0x13C8)
+#define RCC_PLL6CFGR7 U(0x13CC)
+#define RCC_PLL7CFGR1 U(0x13D8)
+#define RCC_PLL7CFGR2 U(0x13DC)
+#define RCC_PLL7CFGR3 U(0x13E0)
+#define RCC_PLL7CFGR4 U(0x13E4)
+#define RCC_PLL7CFGR5 U(0x13E8)
+#define RCC_PLL7CFGR6 U(0x13F0)
+#define RCC_PLL7CFGR7 U(0x13F4)
+#define RCC_PLL8CFGR1 U(0x1400)
+#define RCC_PLL8CFGR2 U(0x1404)
+#define RCC_PLL8CFGR3 U(0x1408)
+#define RCC_PLL8CFGR4 U(0x140C)
+#define RCC_PLL8CFGR5 U(0x1410)
+#define RCC_PLL8CFGR6 U(0x1418)
+#define RCC_PLL8CFGR7 U(0x141C)
+#define RCC_VERR U(0xFFF4)
+#define RCC_IDR U(0xFFF8)
+#define RCC_SIDR U(0xFFFC)
+
+/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
+#define RCC_MP_ENCLRR_OFFSET U(4)
+
+/* RCC_SECCFGR3 register fields */
+#define RCC_SECCFGR3_SEC_MASK GENMASK_32(17, 0)
+#define RCC_SECCFGR3_SEC_SHIFT 0
+
+/* RCC_PRIVCFGR3 register fields */
+#define RCC_PRIVCFGR3_PRIV_MASK GENMASK_32(17, 0)
+#define RCC_PRIVCFGR3_PRIV_SHIFT 0
+
+/* RCC_RCFGLOCKR3 register fields */
+#define RCC_RCFGLOCKR3_RLOCK_MASK GENMASK_32(17, 0)
+#define RCC_RCFGLOCKR3_RLOCK_SHIFT 0
+
+/* RCC_R0CIDCFGR register fields */
+#define RCC_R0CIDCFGR_CFEN BIT(0)
+#define RCC_R0CIDCFGR_SEM_EN BIT(1)
+#define RCC_R0CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R0CIDCFGR_SCID_SHIFT 4
+#define RCC_R0CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R0CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R0SEMCR register fields */
+#define RCC_R0SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R0SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R0SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R1CIDCFGR register fields */
+#define RCC_R1CIDCFGR_CFEN BIT(0)
+#define RCC_R1CIDCFGR_SEM_EN BIT(1)
+#define RCC_R1CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R1CIDCFGR_SCID_SHIFT 4
+#define RCC_R1CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R1CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R1SEMCR register fields */
+#define RCC_R1SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R1SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R1SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R2CIDCFGR register fields */
+#define RCC_R2CIDCFGR_CFEN BIT(0)
+#define RCC_R2CIDCFGR_SEM_EN BIT(1)
+#define RCC_R2CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R2CIDCFGR_SCID_SHIFT 4
+#define RCC_R2CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R2CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R2SEMCR register fields */
+#define RCC_R2SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R2SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R2SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R3CIDCFGR register fields */
+#define RCC_R3CIDCFGR_CFEN BIT(0)
+#define RCC_R3CIDCFGR_SEM_EN BIT(1)
+#define RCC_R3CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R3CIDCFGR_SCID_SHIFT 4
+#define RCC_R3CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R3CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R3SEMCR register fields */
+#define RCC_R3SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R3SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R3SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R4CIDCFGR register fields */
+#define RCC_R4CIDCFGR_CFEN BIT(0)
+#define RCC_R4CIDCFGR_SEM_EN BIT(1)
+#define RCC_R4CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R4CIDCFGR_SCID_SHIFT 4
+#define RCC_R4CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R4CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R4SEMCR register fields */
+#define RCC_R4SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R4SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R4SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R5CIDCFGR register fields */
+#define RCC_R5CIDCFGR_CFEN BIT(0)
+#define RCC_R5CIDCFGR_SEM_EN BIT(1)
+#define RCC_R5CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R5CIDCFGR_SCID_SHIFT 4
+#define RCC_R5CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R5CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R5SEMCR register fields */
+#define RCC_R5SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R5SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R5SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R6CIDCFGR register fields */
+#define RCC_R6CIDCFGR_CFEN BIT(0)
+#define RCC_R6CIDCFGR_SEM_EN BIT(1)
+#define RCC_R6CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R6CIDCFGR_SCID_SHIFT 4
+#define RCC_R6CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R6CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R6SEMCR register fields */
+#define RCC_R6SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R6SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R6SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R7CIDCFGR register fields */
+#define RCC_R7CIDCFGR_CFEN BIT(0)
+#define RCC_R7CIDCFGR_SEM_EN BIT(1)
+#define RCC_R7CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R7CIDCFGR_SCID_SHIFT 4
+#define RCC_R7CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R7CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R7SEMCR register fields */
+#define RCC_R7SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R7SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R7SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R8CIDCFGR register fields */
+#define RCC_R8CIDCFGR_CFEN BIT(0)
+#define RCC_R8CIDCFGR_SEM_EN BIT(1)
+#define RCC_R8CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R8CIDCFGR_SCID_SHIFT 4
+#define RCC_R8CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R8CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R8SEMCR register fields */
+#define RCC_R8SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R8SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R8SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R9CIDCFGR register fields */
+#define RCC_R9CIDCFGR_CFEN BIT(0)
+#define RCC_R9CIDCFGR_SEM_EN BIT(1)
+#define RCC_R9CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R9CIDCFGR_SCID_SHIFT 4
+#define RCC_R9CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R9CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R9SEMCR register fields */
+#define RCC_R9SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R9SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R9SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R10CIDCFGR register fields */
+#define RCC_R10CIDCFGR_CFEN BIT(0)
+#define RCC_R10CIDCFGR_SEM_EN BIT(1)
+#define RCC_R10CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R10CIDCFGR_SCID_SHIFT 4
+#define RCC_R10CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R10CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R10SEMCR register fields */
+#define RCC_R10SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R10SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R10SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R11CIDCFGR register fields */
+#define RCC_R11CIDCFGR_CFEN BIT(0)
+#define RCC_R11CIDCFGR_SEM_EN BIT(1)
+#define RCC_R11CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R11CIDCFGR_SCID_SHIFT 4
+#define RCC_R11CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R11CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R11SEMCR register fields */
+#define RCC_R11SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R11SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R11SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R12CIDCFGR register fields */
+#define RCC_R12CIDCFGR_CFEN BIT(0)
+#define RCC_R12CIDCFGR_SEM_EN BIT(1)
+#define RCC_R12CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R12CIDCFGR_SCID_SHIFT 4
+#define RCC_R12CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R12CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R12SEMCR register fields */
+#define RCC_R12SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R12SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R12SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R13CIDCFGR register fields */
+#define RCC_R13CIDCFGR_CFEN BIT(0)
+#define RCC_R13CIDCFGR_SEM_EN BIT(1)
+#define RCC_R13CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R13CIDCFGR_SCID_SHIFT 4
+#define RCC_R13CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R13CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R13SEMCR register fields */
+#define RCC_R13SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R13SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R13SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R14CIDCFGR register fields */
+#define RCC_R14CIDCFGR_CFEN BIT(0)
+#define RCC_R14CIDCFGR_SEM_EN BIT(1)
+#define RCC_R14CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R14CIDCFGR_SCID_SHIFT 4
+#define RCC_R14CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R14CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R14SEMCR register fields */
+#define RCC_R14SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R14SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R14SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R15CIDCFGR register fields */
+#define RCC_R15CIDCFGR_CFEN BIT(0)
+#define RCC_R15CIDCFGR_SEM_EN BIT(1)
+#define RCC_R15CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R15CIDCFGR_SCID_SHIFT 4
+#define RCC_R15CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R15CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R15SEMCR register fields */
+#define RCC_R15SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R15SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R15SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R16CIDCFGR register fields */
+#define RCC_R16CIDCFGR_CFEN BIT(0)
+#define RCC_R16CIDCFGR_SEM_EN BIT(1)
+#define RCC_R16CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R16CIDCFGR_SCID_SHIFT 4
+#define RCC_R16CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R16CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R16SEMCR register fields */
+#define RCC_R16SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R16SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R16SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R17CIDCFGR register fields */
+#define RCC_R17CIDCFGR_CFEN BIT(0)
+#define RCC_R17CIDCFGR_SEM_EN BIT(1)
+#define RCC_R17CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R17CIDCFGR_SCID_SHIFT 4
+#define RCC_R17CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R17CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R17SEMCR register fields */
+#define RCC_R17SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R17SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R17SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R18CIDCFGR register fields */
+#define RCC_R18CIDCFGR_CFEN BIT(0)
+#define RCC_R18CIDCFGR_SEM_EN BIT(1)
+#define RCC_R18CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R18CIDCFGR_SCID_SHIFT 4
+#define RCC_R18CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R18CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R18SEMCR register fields */
+#define RCC_R18SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R18SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R18SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R19CIDCFGR register fields */
+#define RCC_R19CIDCFGR_CFEN BIT(0)
+#define RCC_R19CIDCFGR_SEM_EN BIT(1)
+#define RCC_R19CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R19CIDCFGR_SCID_SHIFT 4
+#define RCC_R19CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R19CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R19SEMCR register fields */
+#define RCC_R19SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R19SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R19SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R20CIDCFGR register fields */
+#define RCC_R20CIDCFGR_CFEN BIT(0)
+#define RCC_R20CIDCFGR_SEM_EN BIT(1)
+#define RCC_R20CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R20CIDCFGR_SCID_SHIFT 4
+#define RCC_R20CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R20CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R20SEMCR register fields */
+#define RCC_R20SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R20SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R20SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R21CIDCFGR register fields */
+#define RCC_R21CIDCFGR_CFEN BIT(0)
+#define RCC_R21CIDCFGR_SEM_EN BIT(1)
+#define RCC_R21CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R21CIDCFGR_SCID_SHIFT 4
+#define RCC_R21CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R21CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R21SEMCR register fields */
+#define RCC_R21SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R21SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R21SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R22CIDCFGR register fields */
+#define RCC_R22CIDCFGR_CFEN BIT(0)
+#define RCC_R22CIDCFGR_SEM_EN BIT(1)
+#define RCC_R22CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R22CIDCFGR_SCID_SHIFT 4
+#define RCC_R22CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R22CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R22SEMCR register fields */
+#define RCC_R22SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R22SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R22SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R23CIDCFGR register fields */
+#define RCC_R23CIDCFGR_CFEN BIT(0)
+#define RCC_R23CIDCFGR_SEM_EN BIT(1)
+#define RCC_R23CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R23CIDCFGR_SCID_SHIFT 4
+#define RCC_R23CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R23CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R23SEMCR register fields */
+#define RCC_R23SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R23SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R23SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R24CIDCFGR register fields */
+#define RCC_R24CIDCFGR_CFEN BIT(0)
+#define RCC_R24CIDCFGR_SEM_EN BIT(1)
+#define RCC_R24CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R24CIDCFGR_SCID_SHIFT 4
+#define RCC_R24CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R24CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R24SEMCR register fields */
+#define RCC_R24SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R24SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R24SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R25CIDCFGR register fields */
+#define RCC_R25CIDCFGR_CFEN BIT(0)
+#define RCC_R25CIDCFGR_SEM_EN BIT(1)
+#define RCC_R25CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R25CIDCFGR_SCID_SHIFT 4
+#define RCC_R25CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R25CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R25SEMCR register fields */
+#define RCC_R25SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R25SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R25SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R26CIDCFGR register fields */
+#define RCC_R26CIDCFGR_CFEN BIT(0)
+#define RCC_R26CIDCFGR_SEM_EN BIT(1)
+#define RCC_R26CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R26CIDCFGR_SCID_SHIFT 4
+#define RCC_R26CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R26CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R26SEMCR register fields */
+#define RCC_R26SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R26SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R26SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R27CIDCFGR register fields */
+#define RCC_R27CIDCFGR_CFEN BIT(0)
+#define RCC_R27CIDCFGR_SEM_EN BIT(1)
+#define RCC_R27CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R27CIDCFGR_SCID_SHIFT 4
+#define RCC_R27CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R27CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R27SEMCR register fields */
+#define RCC_R27SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R27SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R27SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R28CIDCFGR register fields */
+#define RCC_R28CIDCFGR_CFEN BIT(0)
+#define RCC_R28CIDCFGR_SEM_EN BIT(1)
+#define RCC_R28CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R28CIDCFGR_SCID_SHIFT 4
+#define RCC_R28CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R28CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R28SEMCR register fields */
+#define RCC_R28SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R28SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R28SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R29CIDCFGR register fields */
+#define RCC_R29CIDCFGR_CFEN BIT(0)
+#define RCC_R29CIDCFGR_SEM_EN BIT(1)
+#define RCC_R29CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R29CIDCFGR_SCID_SHIFT 4
+#define RCC_R29CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R29CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R29SEMCR register fields */
+#define RCC_R29SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R29SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R29SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R30CIDCFGR register fields */
+#define RCC_R30CIDCFGR_CFEN BIT(0)
+#define RCC_R30CIDCFGR_SEM_EN BIT(1)
+#define RCC_R30CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R30CIDCFGR_SCID_SHIFT 4
+#define RCC_R30CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R30CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R30SEMCR register fields */
+#define RCC_R30SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R30SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R30SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R31CIDCFGR register fields */
+#define RCC_R31CIDCFGR_CFEN BIT(0)
+#define RCC_R31CIDCFGR_SEM_EN BIT(1)
+#define RCC_R31CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R31CIDCFGR_SCID_SHIFT 4
+#define RCC_R31CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R31CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R31SEMCR register fields */
+#define RCC_R31SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R31SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R31SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R32CIDCFGR register fields */
+#define RCC_R32CIDCFGR_CFEN BIT(0)
+#define RCC_R32CIDCFGR_SEM_EN BIT(1)
+#define RCC_R32CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R32CIDCFGR_SCID_SHIFT 4
+#define RCC_R32CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R32CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R32SEMCR register fields */
+#define RCC_R32SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R32SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R32SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R33CIDCFGR register fields */
+#define RCC_R33CIDCFGR_CFEN BIT(0)
+#define RCC_R33CIDCFGR_SEM_EN BIT(1)
+#define RCC_R33CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R33CIDCFGR_SCID_SHIFT 4
+#define RCC_R33CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R33CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R33SEMCR register fields */
+#define RCC_R33SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R33SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R33SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R34CIDCFGR register fields */
+#define RCC_R34CIDCFGR_CFEN BIT(0)
+#define RCC_R34CIDCFGR_SEM_EN BIT(1)
+#define RCC_R34CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R34CIDCFGR_SCID_SHIFT 4
+#define RCC_R34CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R34CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R34SEMCR register fields */
+#define RCC_R34SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R34SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R34SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R35CIDCFGR register fields */
+#define RCC_R35CIDCFGR_CFEN BIT(0)
+#define RCC_R35CIDCFGR_SEM_EN BIT(1)
+#define RCC_R35CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R35CIDCFGR_SCID_SHIFT 4
+#define RCC_R35CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R35CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R35SEMCR register fields */
+#define RCC_R35SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R35SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R35SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R36CIDCFGR register fields */
+#define RCC_R36CIDCFGR_CFEN BIT(0)
+#define RCC_R36CIDCFGR_SEM_EN BIT(1)
+#define RCC_R36CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R36CIDCFGR_SCID_SHIFT 4
+#define RCC_R36CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R36CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R36SEMCR register fields */
+#define RCC_R36SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R36SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R36SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R37CIDCFGR register fields */
+#define RCC_R37CIDCFGR_CFEN BIT(0)
+#define RCC_R37CIDCFGR_SEM_EN BIT(1)
+#define RCC_R37CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R37CIDCFGR_SCID_SHIFT 4
+#define RCC_R37CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R37CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R37SEMCR register fields */
+#define RCC_R37SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R37SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R37SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R38CIDCFGR register fields */
+#define RCC_R38CIDCFGR_CFEN BIT(0)
+#define RCC_R38CIDCFGR_SEM_EN BIT(1)
+#define RCC_R38CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R38CIDCFGR_SCID_SHIFT 4
+#define RCC_R38CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R38CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R38SEMCR register fields */
+#define RCC_R38SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R38SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R38SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R39CIDCFGR register fields */
+#define RCC_R39CIDCFGR_CFEN BIT(0)
+#define RCC_R39CIDCFGR_SEM_EN BIT(1)
+#define RCC_R39CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R39CIDCFGR_SCID_SHIFT 4
+#define RCC_R39CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R39CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R39SEMCR register fields */
+#define RCC_R39SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R39SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R39SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R40CIDCFGR register fields */
+#define RCC_R40CIDCFGR_CFEN BIT(0)
+#define RCC_R40CIDCFGR_SEM_EN BIT(1)
+#define RCC_R40CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R40CIDCFGR_SCID_SHIFT 4
+#define RCC_R40CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R40CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R40SEMCR register fields */
+#define RCC_R40SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R40SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R40SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R41CIDCFGR register fields */
+#define RCC_R41CIDCFGR_CFEN BIT(0)
+#define RCC_R41CIDCFGR_SEM_EN BIT(1)
+#define RCC_R41CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R41CIDCFGR_SCID_SHIFT 4
+#define RCC_R41CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R41CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R41SEMCR register fields */
+#define RCC_R41SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R41SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R41SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R42CIDCFGR register fields */
+#define RCC_R42CIDCFGR_CFEN BIT(0)
+#define RCC_R42CIDCFGR_SEM_EN BIT(1)
+#define RCC_R42CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R42CIDCFGR_SCID_SHIFT 4
+#define RCC_R42CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R42CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R42SEMCR register fields */
+#define RCC_R42SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R42SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R42SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R43CIDCFGR register fields */
+#define RCC_R43CIDCFGR_CFEN BIT(0)
+#define RCC_R43CIDCFGR_SEM_EN BIT(1)
+#define RCC_R43CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R43CIDCFGR_SCID_SHIFT 4
+#define RCC_R43CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R43CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R43SEMCR register fields */
+#define RCC_R43SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R43SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R43SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R44CIDCFGR register fields */
+#define RCC_R44CIDCFGR_CFEN BIT(0)
+#define RCC_R44CIDCFGR_SEM_EN BIT(1)
+#define RCC_R44CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R44CIDCFGR_SCID_SHIFT 4
+#define RCC_R44CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R44CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R44SEMCR register fields */
+#define RCC_R44SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R44SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R44SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R45CIDCFGR register fields */
+#define RCC_R45CIDCFGR_CFEN BIT(0)
+#define RCC_R45CIDCFGR_SEM_EN BIT(1)
+#define RCC_R45CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R45CIDCFGR_SCID_SHIFT 4
+#define RCC_R45CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R45CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R45SEMCR register fields */
+#define RCC_R45SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R45SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R45SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R46CIDCFGR register fields */
+#define RCC_R46CIDCFGR_CFEN BIT(0)
+#define RCC_R46CIDCFGR_SEM_EN BIT(1)
+#define RCC_R46CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R46CIDCFGR_SCID_SHIFT 4
+#define RCC_R46CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R46CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R46SEMCR register fields */
+#define RCC_R46SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R46SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R46SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R47CIDCFGR register fields */
+#define RCC_R47CIDCFGR_CFEN BIT(0)
+#define RCC_R47CIDCFGR_SEM_EN BIT(1)
+#define RCC_R47CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R47CIDCFGR_SCID_SHIFT 4
+#define RCC_R47CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R47CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R47SEMCR register fields */
+#define RCC_R47SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R47SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R47SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R48CIDCFGR register fields */
+#define RCC_R48CIDCFGR_CFEN BIT(0)
+#define RCC_R48CIDCFGR_SEM_EN BIT(1)
+#define RCC_R48CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R48CIDCFGR_SCID_SHIFT 4
+#define RCC_R48CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R48CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R48SEMCR register fields */
+#define RCC_R48SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R48SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R48SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R49CIDCFGR register fields */
+#define RCC_R49CIDCFGR_CFEN BIT(0)
+#define RCC_R49CIDCFGR_SEM_EN BIT(1)
+#define RCC_R49CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R49CIDCFGR_SCID_SHIFT 4
+#define RCC_R49CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R49CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R49SEMCR register fields */
+#define RCC_R49SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R49SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R49SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R50CIDCFGR register fields */
+#define RCC_R50CIDCFGR_CFEN BIT(0)
+#define RCC_R50CIDCFGR_SEM_EN BIT(1)
+#define RCC_R50CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R50CIDCFGR_SCID_SHIFT 4
+#define RCC_R50CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R50CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R50SEMCR register fields */
+#define RCC_R50SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R50SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R50SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R51CIDCFGR register fields */
+#define RCC_R51CIDCFGR_CFEN BIT(0)
+#define RCC_R51CIDCFGR_SEM_EN BIT(1)
+#define RCC_R51CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R51CIDCFGR_SCID_SHIFT 4
+#define RCC_R51CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R51CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R51SEMCR register fields */
+#define RCC_R51SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R51SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R51SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R52CIDCFGR register fields */
+#define RCC_R52CIDCFGR_CFEN BIT(0)
+#define RCC_R52CIDCFGR_SEM_EN BIT(1)
+#define RCC_R52CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R52CIDCFGR_SCID_SHIFT 4
+#define RCC_R52CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R52CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R52SEMCR register fields */
+#define RCC_R52SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R52SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R52SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R53CIDCFGR register fields */
+#define RCC_R53CIDCFGR_CFEN BIT(0)
+#define RCC_R53CIDCFGR_SEM_EN BIT(1)
+#define RCC_R53CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R53CIDCFGR_SCID_SHIFT 4
+#define RCC_R53CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R53CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R53SEMCR register fields */
+#define RCC_R53SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R53SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R53SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R54CIDCFGR register fields */
+#define RCC_R54CIDCFGR_CFEN BIT(0)
+#define RCC_R54CIDCFGR_SEM_EN BIT(1)
+#define RCC_R54CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R54CIDCFGR_SCID_SHIFT 4
+#define RCC_R54CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R54CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R54SEMCR register fields */
+#define RCC_R54SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R54SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R54SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R55CIDCFGR register fields */
+#define RCC_R55CIDCFGR_CFEN BIT(0)
+#define RCC_R55CIDCFGR_SEM_EN BIT(1)
+#define RCC_R55CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R55CIDCFGR_SCID_SHIFT 4
+#define RCC_R55CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R55CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R55SEMCR register fields */
+#define RCC_R55SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R55SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R55SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R56CIDCFGR register fields */
+#define RCC_R56CIDCFGR_CFEN BIT(0)
+#define RCC_R56CIDCFGR_SEM_EN BIT(1)
+#define RCC_R56CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R56CIDCFGR_SCID_SHIFT 4
+#define RCC_R56CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R56CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R56SEMCR register fields */
+#define RCC_R56SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R56SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R56SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R57CIDCFGR register fields */
+#define RCC_R57CIDCFGR_CFEN BIT(0)
+#define RCC_R57CIDCFGR_SEM_EN BIT(1)
+#define RCC_R57CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R57CIDCFGR_SCID_SHIFT 4
+#define RCC_R57CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R57CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R57SEMCR register fields */
+#define RCC_R57SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R57SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R57SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R58CIDCFGR register fields */
+#define RCC_R58CIDCFGR_CFEN BIT(0)
+#define RCC_R58CIDCFGR_SEM_EN BIT(1)
+#define RCC_R58CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R58CIDCFGR_SCID_SHIFT 4
+#define RCC_R58CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R58CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R58SEMCR register fields */
+#define RCC_R58SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R58SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R58SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R59CIDCFGR register fields */
+#define RCC_R59CIDCFGR_CFEN BIT(0)
+#define RCC_R59CIDCFGR_SEM_EN BIT(1)
+#define RCC_R59CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R59CIDCFGR_SCID_SHIFT 4
+#define RCC_R59CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R59CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R59SEMCR register fields */
+#define RCC_R59SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R59SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R59SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R60CIDCFGR register fields */
+#define RCC_R60CIDCFGR_CFEN BIT(0)
+#define RCC_R60CIDCFGR_SEM_EN BIT(1)
+#define RCC_R60CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R60CIDCFGR_SCID_SHIFT 4
+#define RCC_R60CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R60CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R60SEMCR register fields */
+#define RCC_R60SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R60SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R60SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R61CIDCFGR register fields */
+#define RCC_R61CIDCFGR_CFEN BIT(0)
+#define RCC_R61CIDCFGR_SEM_EN BIT(1)
+#define RCC_R61CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R61CIDCFGR_SCID_SHIFT 4
+#define RCC_R61CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R61CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R61SEMCR register fields */
+#define RCC_R61SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R61SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R61SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R62CIDCFGR register fields */
+#define RCC_R62CIDCFGR_CFEN BIT(0)
+#define RCC_R62CIDCFGR_SEM_EN BIT(1)
+#define RCC_R62CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R62CIDCFGR_SCID_SHIFT 4
+#define RCC_R62CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R62CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R62SEMCR register fields */
+#define RCC_R62SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R62SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R62SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R63CIDCFGR register fields */
+#define RCC_R63CIDCFGR_CFEN BIT(0)
+#define RCC_R63CIDCFGR_SEM_EN BIT(1)
+#define RCC_R63CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R63CIDCFGR_SCID_SHIFT 4
+#define RCC_R63CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R63CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R63SEMCR register fields */
+#define RCC_R63SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R63SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R63SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R64CIDCFGR register fields */
+#define RCC_R64CIDCFGR_CFEN BIT(0)
+#define RCC_R64CIDCFGR_SEM_EN BIT(1)
+#define RCC_R64CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R64CIDCFGR_SCID_SHIFT 4
+#define RCC_R64CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R64CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R64SEMCR register fields */
+#define RCC_R64SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R64SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R64SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R65CIDCFGR register fields */
+#define RCC_R65CIDCFGR_CFEN BIT(0)
+#define RCC_R65CIDCFGR_SEM_EN BIT(1)
+#define RCC_R65CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R65CIDCFGR_SCID_SHIFT 4
+#define RCC_R65CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R65CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R65SEMCR register fields */
+#define RCC_R65SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R65SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R65SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R66CIDCFGR register fields */
+#define RCC_R66CIDCFGR_CFEN BIT(0)
+#define RCC_R66CIDCFGR_SEM_EN BIT(1)
+#define RCC_R66CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R66CIDCFGR_SCID_SHIFT 4
+#define RCC_R66CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R66CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R66SEMCR register fields */
+#define RCC_R66SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R66SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R66SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R67CIDCFGR register fields */
+#define RCC_R67CIDCFGR_CFEN BIT(0)
+#define RCC_R67CIDCFGR_SEM_EN BIT(1)
+#define RCC_R67CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R67CIDCFGR_SCID_SHIFT 4
+#define RCC_R67CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R67CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R67SEMCR register fields */
+#define RCC_R67SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R67SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R67SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R68CIDCFGR register fields */
+#define RCC_R68CIDCFGR_CFEN BIT(0)
+#define RCC_R68CIDCFGR_SEM_EN BIT(1)
+#define RCC_R68CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R68CIDCFGR_SCID_SHIFT 4
+#define RCC_R68CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R68CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R68SEMCR register fields */
+#define RCC_R68SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R68SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R68SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R69CIDCFGR register fields */
+#define RCC_R69CIDCFGR_CFEN BIT(0)
+#define RCC_R69CIDCFGR_SEM_EN BIT(1)
+#define RCC_R69CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R69CIDCFGR_SCID_SHIFT 4
+#define RCC_R69CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R69CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R69SEMCR register fields */
+#define RCC_R69SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R69SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R69SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R70CIDCFGR register fields */
+#define RCC_R70CIDCFGR_CFEN BIT(0)
+#define RCC_R70CIDCFGR_SEM_EN BIT(1)
+#define RCC_R70CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R70CIDCFGR_SCID_SHIFT 4
+#define RCC_R70CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R70CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R70SEMCR register fields */
+#define RCC_R70SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R70SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R70SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R71CIDCFGR register fields */
+#define RCC_R71CIDCFGR_CFEN BIT(0)
+#define RCC_R71CIDCFGR_SEM_EN BIT(1)
+#define RCC_R71CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R71CIDCFGR_SCID_SHIFT 4
+#define RCC_R71CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R71CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R71SEMCR register fields */
+#define RCC_R71SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R71SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R71SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R72CIDCFGR register fields */
+#define RCC_R72CIDCFGR_CFEN BIT(0)
+#define RCC_R72CIDCFGR_SEM_EN BIT(1)
+#define RCC_R72CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R72CIDCFGR_SCID_SHIFT 4
+#define RCC_R72CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R72CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R72SEMCR register fields */
+#define RCC_R72SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R72SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R72SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R73CIDCFGR register fields */
+#define RCC_R73CIDCFGR_CFEN BIT(0)
+#define RCC_R73CIDCFGR_SEM_EN BIT(1)
+#define RCC_R73CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R73CIDCFGR_SCID_SHIFT 4
+#define RCC_R73CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R73CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R73SEMCR register fields */
+#define RCC_R73SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R73SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R73SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R74CIDCFGR register fields */
+#define RCC_R74CIDCFGR_CFEN BIT(0)
+#define RCC_R74CIDCFGR_SEM_EN BIT(1)
+#define RCC_R74CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R74CIDCFGR_SCID_SHIFT 4
+#define RCC_R74CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R74CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R74SEMCR register fields */
+#define RCC_R74SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R74SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R74SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R75CIDCFGR register fields */
+#define RCC_R75CIDCFGR_CFEN BIT(0)
+#define RCC_R75CIDCFGR_SEM_EN BIT(1)
+#define RCC_R75CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R75CIDCFGR_SCID_SHIFT 4
+#define RCC_R75CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R75CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R75SEMCR register fields */
+#define RCC_R75SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R75SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R75SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R76CIDCFGR register fields */
+#define RCC_R76CIDCFGR_CFEN BIT(0)
+#define RCC_R76CIDCFGR_SEM_EN BIT(1)
+#define RCC_R76CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R76CIDCFGR_SCID_SHIFT 4
+#define RCC_R76CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R76CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R76SEMCR register fields */
+#define RCC_R76SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R76SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R76SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R77CIDCFGR register fields */
+#define RCC_R77CIDCFGR_CFEN BIT(0)
+#define RCC_R77CIDCFGR_SEM_EN BIT(1)
+#define RCC_R77CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R77CIDCFGR_SCID_SHIFT 4
+#define RCC_R77CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R77CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R77SEMCR register fields */
+#define RCC_R77SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R77SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R77SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R78CIDCFGR register fields */
+#define RCC_R78CIDCFGR_CFEN BIT(0)
+#define RCC_R78CIDCFGR_SEM_EN BIT(1)
+#define RCC_R78CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R78CIDCFGR_SCID_SHIFT 4
+#define RCC_R78CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R78CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R78SEMCR register fields */
+#define RCC_R78SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R78SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R78SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R79CIDCFGR register fields */
+#define RCC_R79CIDCFGR_CFEN BIT(0)
+#define RCC_R79CIDCFGR_SEM_EN BIT(1)
+#define RCC_R79CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R79CIDCFGR_SCID_SHIFT 4
+#define RCC_R79CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R79CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R79SEMCR register fields */
+#define RCC_R79SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R79SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R79SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R80CIDCFGR register fields */
+#define RCC_R80CIDCFGR_CFEN BIT(0)
+#define RCC_R80CIDCFGR_SEM_EN BIT(1)
+#define RCC_R80CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R80CIDCFGR_SCID_SHIFT 4
+#define RCC_R80CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R80CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R80SEMCR register fields */
+#define RCC_R80SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R80SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R80SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R81CIDCFGR register fields */
+#define RCC_R81CIDCFGR_CFEN BIT(0)
+#define RCC_R81CIDCFGR_SEM_EN BIT(1)
+#define RCC_R81CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R81CIDCFGR_SCID_SHIFT 4
+#define RCC_R81CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R81CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R81SEMCR register fields */
+#define RCC_R81SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R81SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R81SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R82CIDCFGR register fields */
+#define RCC_R82CIDCFGR_CFEN BIT(0)
+#define RCC_R82CIDCFGR_SEM_EN BIT(1)
+#define RCC_R82CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R82CIDCFGR_SCID_SHIFT 4
+#define RCC_R82CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R82CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R82SEMCR register fields */
+#define RCC_R82SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R82SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R82SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R83CIDCFGR register fields */
+#define RCC_R83CIDCFGR_CFEN BIT(0)
+#define RCC_R83CIDCFGR_SEM_EN BIT(1)
+#define RCC_R83CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R83CIDCFGR_SCID_SHIFT 4
+#define RCC_R83CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R83CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R83SEMCR register fields */
+#define RCC_R83SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R83SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R83SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R84CIDCFGR register fields */
+#define RCC_R84CIDCFGR_CFEN BIT(0)
+#define RCC_R84CIDCFGR_SEM_EN BIT(1)
+#define RCC_R84CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R84CIDCFGR_SCID_SHIFT 4
+#define RCC_R84CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R84CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R84SEMCR register fields */
+#define RCC_R84SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R84SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R84SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R85CIDCFGR register fields */
+#define RCC_R85CIDCFGR_CFEN BIT(0)
+#define RCC_R85CIDCFGR_SEM_EN BIT(1)
+#define RCC_R85CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R85CIDCFGR_SCID_SHIFT 4
+#define RCC_R85CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R85CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R85SEMCR register fields */
+#define RCC_R85SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R85SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R85SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R86CIDCFGR register fields */
+#define RCC_R86CIDCFGR_CFEN BIT(0)
+#define RCC_R86CIDCFGR_SEM_EN BIT(1)
+#define RCC_R86CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R86CIDCFGR_SCID_SHIFT 4
+#define RCC_R86CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R86CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R86SEMCR register fields */
+#define RCC_R86SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R86SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R86SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R87CIDCFGR register fields */
+#define RCC_R87CIDCFGR_CFEN BIT(0)
+#define RCC_R87CIDCFGR_SEM_EN BIT(1)
+#define RCC_R87CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R87CIDCFGR_SCID_SHIFT 4
+#define RCC_R87CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R87CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R87SEMCR register fields */
+#define RCC_R87SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R87SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R87SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R88CIDCFGR register fields */
+#define RCC_R88CIDCFGR_CFEN BIT(0)
+#define RCC_R88CIDCFGR_SEM_EN BIT(1)
+#define RCC_R88CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R88CIDCFGR_SCID_SHIFT 4
+#define RCC_R88CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R88CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R88SEMCR register fields */
+#define RCC_R88SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R88SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R88SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R89CIDCFGR register fields */
+#define RCC_R89CIDCFGR_CFEN BIT(0)
+#define RCC_R89CIDCFGR_SEM_EN BIT(1)
+#define RCC_R89CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R89CIDCFGR_SCID_SHIFT 4
+#define RCC_R89CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R89CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R89SEMCR register fields */
+#define RCC_R89SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R89SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R89SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R90CIDCFGR register fields */
+#define RCC_R90CIDCFGR_CFEN BIT(0)
+#define RCC_R90CIDCFGR_SEM_EN BIT(1)
+#define RCC_R90CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R90CIDCFGR_SCID_SHIFT 4
+#define RCC_R90CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R90CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R90SEMCR register fields */
+#define RCC_R90SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R90SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R90SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R91CIDCFGR register fields */
+#define RCC_R91CIDCFGR_CFEN BIT(0)
+#define RCC_R91CIDCFGR_SEM_EN BIT(1)
+#define RCC_R91CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R91CIDCFGR_SCID_SHIFT 4
+#define RCC_R91CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R91CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R91SEMCR register fields */
+#define RCC_R91SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R91SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R91SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R92CIDCFGR register fields */
+#define RCC_R92CIDCFGR_CFEN BIT(0)
+#define RCC_R92CIDCFGR_SEM_EN BIT(1)
+#define RCC_R92CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R92CIDCFGR_SCID_SHIFT 4
+#define RCC_R92CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R92CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R92SEMCR register fields */
+#define RCC_R92SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R92SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R92SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R93CIDCFGR register fields */
+#define RCC_R93CIDCFGR_CFEN BIT(0)
+#define RCC_R93CIDCFGR_SEM_EN BIT(1)
+#define RCC_R93CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R93CIDCFGR_SCID_SHIFT 4
+#define RCC_R93CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R93CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R93SEMCR register fields */
+#define RCC_R93SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R93SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R93SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R94CIDCFGR register fields */
+#define RCC_R94CIDCFGR_CFEN BIT(0)
+#define RCC_R94CIDCFGR_SEM_EN BIT(1)
+#define RCC_R94CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R94CIDCFGR_SCID_SHIFT 4
+#define RCC_R94CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R94CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R94SEMCR register fields */
+#define RCC_R94SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R94SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R94SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R95CIDCFGR register fields */
+#define RCC_R95CIDCFGR_CFEN BIT(0)
+#define RCC_R95CIDCFGR_SEM_EN BIT(1)
+#define RCC_R95CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R95CIDCFGR_SCID_SHIFT 4
+#define RCC_R95CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R95CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R95SEMCR register fields */
+#define RCC_R95SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R95SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R95SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R96CIDCFGR register fields */
+#define RCC_R96CIDCFGR_CFEN BIT(0)
+#define RCC_R96CIDCFGR_SEM_EN BIT(1)
+#define RCC_R96CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R96CIDCFGR_SCID_SHIFT 4
+#define RCC_R96CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R96CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R96SEMCR register fields */
+#define RCC_R96SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R96SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R96SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R97CIDCFGR register fields */
+#define RCC_R97CIDCFGR_CFEN BIT(0)
+#define RCC_R97CIDCFGR_SEM_EN BIT(1)
+#define RCC_R97CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R97CIDCFGR_SCID_SHIFT 4
+#define RCC_R97CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R97CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R97SEMCR register fields */
+#define RCC_R97SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R97SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R97SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R98CIDCFGR register fields */
+#define RCC_R98CIDCFGR_CFEN BIT(0)
+#define RCC_R98CIDCFGR_SEM_EN BIT(1)
+#define RCC_R98CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R98CIDCFGR_SCID_SHIFT 4
+#define RCC_R98CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R98CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R98SEMCR register fields */
+#define RCC_R98SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R98SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R98SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R99CIDCFGR register fields */
+#define RCC_R99CIDCFGR_CFEN BIT(0)
+#define RCC_R99CIDCFGR_SEM_EN BIT(1)
+#define RCC_R99CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R99CIDCFGR_SCID_SHIFT 4
+#define RCC_R99CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R99CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R99SEMCR register fields */
+#define RCC_R99SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R99SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R99SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R100CIDCFGR register fields */
+#define RCC_R100CIDCFGR_CFEN BIT(0)
+#define RCC_R100CIDCFGR_SEM_EN BIT(1)
+#define RCC_R100CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R100CIDCFGR_SCID_SHIFT 4
+#define RCC_R100CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R100CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R100SEMCR register fields */
+#define RCC_R100SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R100SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R100SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R101CIDCFGR register fields */
+#define RCC_R101CIDCFGR_CFEN BIT(0)
+#define RCC_R101CIDCFGR_SEM_EN BIT(1)
+#define RCC_R101CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R101CIDCFGR_SCID_SHIFT 4
+#define RCC_R101CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R101CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R101SEMCR register fields */
+#define RCC_R101SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R101SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R101SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R102CIDCFGR register fields */
+#define RCC_R102CIDCFGR_CFEN BIT(0)
+#define RCC_R102CIDCFGR_SEM_EN BIT(1)
+#define RCC_R102CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R102CIDCFGR_SCID_SHIFT 4
+#define RCC_R102CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R102CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R102SEMCR register fields */
+#define RCC_R102SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R102SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R102SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R103CIDCFGR register fields */
+#define RCC_R103CIDCFGR_CFEN BIT(0)
+#define RCC_R103CIDCFGR_SEM_EN BIT(1)
+#define RCC_R103CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R103CIDCFGR_SCID_SHIFT 4
+#define RCC_R103CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R103CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R103SEMCR register fields */
+#define RCC_R103SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R103SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R103SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R104CIDCFGR register fields */
+#define RCC_R104CIDCFGR_CFEN BIT(0)
+#define RCC_R104CIDCFGR_SEM_EN BIT(1)
+#define RCC_R104CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R104CIDCFGR_SCID_SHIFT 4
+#define RCC_R104CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R104CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R104SEMCR register fields */
+#define RCC_R104SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R104SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R104SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R105CIDCFGR register fields */
+#define RCC_R105CIDCFGR_CFEN BIT(0)
+#define RCC_R105CIDCFGR_SEM_EN BIT(1)
+#define RCC_R105CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R105CIDCFGR_SCID_SHIFT 4
+#define RCC_R105CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R105CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R105SEMCR register fields */
+#define RCC_R105SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R105SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R105SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R106CIDCFGR register fields */
+#define RCC_R106CIDCFGR_CFEN BIT(0)
+#define RCC_R106CIDCFGR_SEM_EN BIT(1)
+#define RCC_R106CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R106CIDCFGR_SCID_SHIFT 4
+#define RCC_R106CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R106CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R106SEMCR register fields */
+#define RCC_R106SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R106SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R106SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R107CIDCFGR register fields */
+#define RCC_R107CIDCFGR_CFEN BIT(0)
+#define RCC_R107CIDCFGR_SEM_EN BIT(1)
+#define RCC_R107CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R107CIDCFGR_SCID_SHIFT 4
+#define RCC_R107CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R107CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R107SEMCR register fields */
+#define RCC_R107SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R107SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R107SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R108CIDCFGR register fields */
+#define RCC_R108CIDCFGR_CFEN BIT(0)
+#define RCC_R108CIDCFGR_SEM_EN BIT(1)
+#define RCC_R108CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R108CIDCFGR_SCID_SHIFT 4
+#define RCC_R108CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R108CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R108SEMCR register fields */
+#define RCC_R108SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R108SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R108SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R109CIDCFGR register fields */
+#define RCC_R109CIDCFGR_CFEN BIT(0)
+#define RCC_R109CIDCFGR_SEM_EN BIT(1)
+#define RCC_R109CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R109CIDCFGR_SCID_SHIFT 4
+#define RCC_R109CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R109CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R109SEMCR register fields */
+#define RCC_R109SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R109SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R109SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R110CIDCFGR register fields */
+#define RCC_R110CIDCFGR_CFEN BIT(0)
+#define RCC_R110CIDCFGR_SEM_EN BIT(1)
+#define RCC_R110CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R110CIDCFGR_SCID_SHIFT 4
+#define RCC_R110CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R110CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R110SEMCR register fields */
+#define RCC_R110SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R110SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R110SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R111CIDCFGR register fields */
+#define RCC_R111CIDCFGR_CFEN BIT(0)
+#define RCC_R111CIDCFGR_SEM_EN BIT(1)
+#define RCC_R111CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R111CIDCFGR_SCID_SHIFT 4
+#define RCC_R111CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R111CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R111SEMCR register fields */
+#define RCC_R111SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R111SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R111SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R112CIDCFGR register fields */
+#define RCC_R112CIDCFGR_CFEN BIT(0)
+#define RCC_R112CIDCFGR_SEM_EN BIT(1)
+#define RCC_R112CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R112CIDCFGR_SCID_SHIFT 4
+#define RCC_R112CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R112CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R112SEMCR register fields */
+#define RCC_R112SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R112SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R112SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R113CIDCFGR register fields */
+#define RCC_R113CIDCFGR_CFEN BIT(0)
+#define RCC_R113CIDCFGR_SEM_EN BIT(1)
+#define RCC_R113CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R113CIDCFGR_SCID_SHIFT 4
+#define RCC_R113CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R113CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R113SEMCR register fields */
+#define RCC_R113SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R113SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R113SEMCR_SEMCID_SHIFT 4
+
+/* RCC_RxCIDCFGR register fields */
+#define RCC_RxCIDCFGR_CFEN BIT(0)
+#define RCC_RxCIDCFGR_SEM_EN BIT(1)
+#define RCC_RxCIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_RxCIDCFGR_SCID_SHIFT 4
+#define RCC_RxCIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_RxCIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_RxSEMCR register fields */
+#define RCC_RxSEMCR_SEM_MUTEX BIT(0)
+#define RCC_RxSEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_RxSEMCR_SEMCID_SHIFT 4
+
+/* RCC_GRSTCSETR register fields */
+#define RCC_GRSTCSETR_SYSRST BIT(0)
+
+/* RCC_C1RSTCSETR register fields */
+#define RCC_C1RSTCSETR_C1RST BIT(0)
+
+/* RCC_C2RSTCSETR register fields */
+#define RCC_C2RSTCSETR_C2RST BIT(0)
+
+/* RCC_CxRSTCSETR register fields */
+#define RCC_CxRSTCSETR_CxRST BIT(0)
+
+/* RCC_HWRSTSCLRR register fields */
+#define RCC_HWRSTSCLRR_PORRSTF BIT(0)
+#define RCC_HWRSTSCLRR_BORRSTF BIT(1)
+#define RCC_HWRSTSCLRR_PADRSTF BIT(2)
+#define RCC_HWRSTSCLRR_HCSSRSTF BIT(3)
+#define RCC_HWRSTSCLRR_VCORERSTF BIT(4)
+#define RCC_HWRSTSCLRR_SYSC1RSTF BIT(5)
+#define RCC_HWRSTSCLRR_SYSC2RSTF BIT(6)
+#define RCC_HWRSTSCLRR_IWDG1SYSRSTF BIT(7)
+#define RCC_HWRSTSCLRR_IWDG2SYSRSTF BIT(8)
+#define RCC_HWRSTSCLRR_IWDG3SYSRSTF BIT(9)
+#define RCC_HWRSTSCLRR_IWDG4SYSRSTF BIT(10)
+#define RCC_HWRSTSCLRR_RETCRCERRRSTF BIT(12)
+#define RCC_HWRSTSCLRR_RETECCFAILCRCRSTF BIT(13)
+#define RCC_HWRSTSCLRR_RETECCFAILRESTRSTF BIT(14)
+
+/* RCC_C1HWRSTSCLRR register fields */
+#define RCC_C1HWRSTSCLRR_VCPURSTF BIT(0)
+#define RCC_C1HWRSTSCLRR_C1RSTF BIT(1)
+
+/* RCC_C2HWRSTSCLRR register fields */
+#define RCC_C2HWRSTSCLRR_C2RSTF BIT(0)
+
+/* RCC_C1BOOTRSTSSETR register fields */
+#define RCC_C1BOOTRSTSSETR_PORRSTF BIT(0)
+#define RCC_C1BOOTRSTSSETR_BORRSTF BIT(1)
+#define RCC_C1BOOTRSTSSETR_PADRSTF BIT(2)
+#define RCC_C1BOOTRSTSSETR_HCSSRSTF BIT(3)
+#define RCC_C1BOOTRSTSSETR_VCORERSTF BIT(4)
+#define RCC_C1BOOTRSTSSETR_VCPURSTF BIT(5)
+#define RCC_C1BOOTRSTSSETR_SYSC1RSTF BIT(6)
+#define RCC_C1BOOTRSTSSETR_SYSC2RSTF BIT(7)
+#define RCC_C1BOOTRSTSSETR_IWDG1SYSRSTF BIT(8)
+#define RCC_C1BOOTRSTSSETR_IWDG2SYSRSTF BIT(9)
+#define RCC_C1BOOTRSTSSETR_IWDG3SYSRSTF BIT(10)
+#define RCC_C1BOOTRSTSSETR_IWDG4SYSRSTF BIT(11)
+#define RCC_C1BOOTRSTSSETR_C1RSTF BIT(13)
+#define RCC_C1BOOTRSTSSETR_RETCRCERRRSTF BIT(17)
+#define RCC_C1BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18)
+#define RCC_C1BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19)
+#define RCC_C1BOOTRSTSSETR_STBYC1RSTF BIT(20)
+#define RCC_C1BOOTRSTSSETR_D1STBYRSTF BIT(22)
+#define RCC_C1BOOTRSTSSETR_D2STBYRSTF BIT(23)
+
+/* RCC_C1BOOTRSTSCLRR register fields */
+#define RCC_C1BOOTRSTSCLRR_PORRSTF BIT(0)
+#define RCC_C1BOOTRSTSCLRR_BORRSTF BIT(1)
+#define RCC_C1BOOTRSTSCLRR_PADRSTF BIT(2)
+#define RCC_C1BOOTRSTSCLRR_HCSSRSTF BIT(3)
+#define RCC_C1BOOTRSTSCLRR_VCORERSTF BIT(4)
+#define RCC_C1BOOTRSTSCLRR_VCPURSTF BIT(5)
+#define RCC_C1BOOTRSTSCLRR_SYSC1RSTF BIT(6)
+#define RCC_C1BOOTRSTSCLRR_SYSC2RSTF BIT(7)
+#define RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8)
+#define RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9)
+#define RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10)
+#define RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11)
+#define RCC_C1BOOTRSTSCLRR_C1RSTF BIT(13)
+#define RCC_C1BOOTRSTSCLRR_RETCRCERRRSTF BIT(17)
+#define RCC_C1BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18)
+#define RCC_C1BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19)
+#define RCC_C1BOOTRSTSCLRR_STBYC1RSTF BIT(20)
+#define RCC_C1BOOTRSTSCLRR_D1STBYRSTF BIT(22)
+#define RCC_C1BOOTRSTSCLRR_D2STBYRSTF BIT(23)
+
+#define RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF (RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF)
+
+/* RCC_C2BOOTRSTSSETR register fields */
+#define RCC_C2BOOTRSTSSETR_PORRSTF BIT(0)
+#define RCC_C2BOOTRSTSSETR_BORRSTF BIT(1)
+#define RCC_C2BOOTRSTSSETR_PADRSTF BIT(2)
+#define RCC_C2BOOTRSTSSETR_HCSSRSTF BIT(3)
+#define RCC_C2BOOTRSTSSETR_VCORERSTF BIT(4)
+#define RCC_C2BOOTRSTSSETR_SYSC1RSTF BIT(6)
+#define RCC_C2BOOTRSTSSETR_SYSC2RSTF BIT(7)
+#define RCC_C2BOOTRSTSSETR_IWDG1SYSRSTF BIT(8)
+#define RCC_C2BOOTRSTSSETR_IWDG2SYSRSTF BIT(9)
+#define RCC_C2BOOTRSTSSETR_IWDG3SYSRSTF BIT(10)
+#define RCC_C2BOOTRSTSSETR_IWDG4SYSRSTF BIT(11)
+#define RCC_C2BOOTRSTSSETR_C2RSTF BIT(14)
+#define RCC_C2BOOTRSTSSETR_RETCRCERRRSTF BIT(17)
+#define RCC_C2BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18)
+#define RCC_C2BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19)
+#define RCC_C2BOOTRSTSSETR_STBYC2RSTF BIT(21)
+#define RCC_C2BOOTRSTSSETR_D2STBYRSTF BIT(23)
+
+/* RCC_C2BOOTRSTSCLRR register fields */
+#define RCC_C2BOOTRSTSCLRR_PORRSTF BIT(0)
+#define RCC_C2BOOTRSTSCLRR_BORRSTF BIT(1)
+#define RCC_C2BOOTRSTSCLRR_PADRSTF BIT(2)
+#define RCC_C2BOOTRSTSCLRR_HCSSRSTF BIT(3)
+#define RCC_C2BOOTRSTSCLRR_VCORERSTF BIT(4)
+#define RCC_C2BOOTRSTSCLRR_SYSC1RSTF BIT(6)
+#define RCC_C2BOOTRSTSCLRR_SYSC2RSTF BIT(7)
+#define RCC_C2BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8)
+#define RCC_C2BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9)
+#define RCC_C2BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10)
+#define RCC_C2BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11)
+#define RCC_C2BOOTRSTSCLRR_C2RSTF BIT(14)
+#define RCC_C2BOOTRSTSCLRR_RETCRCERRRSTF BIT(17)
+#define RCC_C2BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18)
+#define RCC_C2BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19)
+#define RCC_C2BOOTRSTSCLRR_STBYC2RSTF BIT(21)
+#define RCC_C2BOOTRSTSCLRR_D2STBYRSTF BIT(23)
+
+/* RCC_C1SREQSETR register fields */
+#define RCC_C1SREQSETR_STPREQ_P0 BIT(0)
+#define RCC_C1SREQSETR_STPREQ_P1 BIT(1)
+#define RCC_C1SREQSETR_STPREQ_MASK GENMASK_32(1, 0)
+#define RCC_C1SREQSETR_ESLPREQ BIT(16)
+
+/* RCC_C1SREQCLRR register fields */
+#define RCC_C1SREQCLRR_STPREQ_P0 BIT(0)
+#define RCC_C1SREQCLRR_STPREQ_P1 BIT(1)
+#define RCC_C1SREQCLRR_STPREQ_MASK GENMASK_32(1, 0)
+#define RCC_C1SREQCLRR_ESLPREQ BIT(16)
+
+/* RCC_CPUBOOTCR register fields */
+#define RCC_CPUBOOTCR_BOOT_CPU2 BIT(0)
+#define RCC_CPUBOOTCR_BOOT_CPU1 BIT(1)
+
+/* RCC_STBYBOOTCR register fields */
+#define RCC_STBYBOOTCR_CPU_BEN_SEL BIT(1)
+#define RCC_STBYBOOTCR_COLD_CPU2 BIT(2)
+#define RCC_STBYBOOTCR_CPU2_HW_BEN BIT(4)
+#define RCC_STBYBOOTCR_CPU1_HW_BEN BIT(5)
+#define RCC_STBYBOOTCR_RET_CRCERR_RSTEN BIT(8)
+
+/* RCC_LEGBOOTCR register fields */
+#define RCC_LEGBOOTCR_LEGACY_BEN BIT(0)
+
+/* RCC_BDCR register fields */
+#define RCC_BDCR_LSEON BIT(0)
+#define RCC_BDCR_LSEBYP BIT(1)
+#define RCC_BDCR_LSERDY BIT(2)
+#define RCC_BDCR_LSEDIGBYP BIT(3)
+#define RCC_BDCR_LSEDRV_MASK GENMASK_32(5, 4)
+#define RCC_BDCR_LSEDRV_SHIFT 4
+#define RCC_BDCR_LSECSSON BIT(6)
+#define RCC_BDCR_LSEGFON BIT(7)
+#define RCC_BDCR_LSECSSD BIT(8)
+#define RCC_BDCR_RTCSRC_MASK GENMASK_32(17, 16)
+#define RCC_BDCR_RTCSRC_SHIFT 16
+#define RCC_BDCR_RTCCKEN BIT(20)
+#define RCC_BDCR_VSWRST BIT(31)
+
+/* RCC_RDCR register fields */
+#define RCC_RDCR_MRD_MASK GENMASK_32(20, 16)
+#define RCC_RDCR_MRD_SHIFT 16
+#define RCC_RDCR_EADLY_MASK GENMASK_32(27, 24)
+#define RCC_RDCR_EADLY_SHIFT 24
+
+/* RCC_C1MSRDCR register fields */
+#define RCC_C1MSRDCR_C1MSRD_MASK GENMASK_32(4, 0)
+#define RCC_C1MSRDCR_C1MSRD_SHIFT 0
+#define RCC_C1MSRDCR_C1MSRST BIT(8)
+
+/* RCC_PWRLPDLYCR register fields */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK_32(21, 0)
+#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0
+#define RCC_PWRLPDLYCR_CPU2TMPSKP BIT(24)
+
+/* RCC_C1CIESETR register fields */
+#define RCC_C1CIESETR_LSIRDYIE BIT(0)
+#define RCC_C1CIESETR_LSERDYIE BIT(1)
+#define RCC_C1CIESETR_HSIRDYIE BIT(2)
+#define RCC_C1CIESETR_HSERDYIE BIT(3)
+#define RCC_C1CIESETR_MSIRDYIE BIT(4)
+#define RCC_C1CIESETR_PLL1RDYIE BIT(5)
+#define RCC_C1CIESETR_PLL2RDYIE BIT(6)
+#define RCC_C1CIESETR_PLL3RDYIE BIT(7)
+#define RCC_C1CIESETR_PLL4RDYIE BIT(8)
+#define RCC_C1CIESETR_PLL5RDYIE BIT(9)
+#define RCC_C1CIESETR_PLL6RDYIE BIT(10)
+#define RCC_C1CIESETR_PLL7RDYIE BIT(11)
+#define RCC_C1CIESETR_PLL8RDYIE BIT(12)
+#define RCC_C1CIESETR_LSECSSIE BIT(16)
+#define RCC_C1CIESETR_WKUPIE BIT(20)
+
+/* RCC_C1CIFCLRR register fields */
+#define RCC_C1CIFCLRR_LSIRDYF BIT(0)
+#define RCC_C1CIFCLRR_LSERDYF BIT(1)
+#define RCC_C1CIFCLRR_HSIRDYF BIT(2)
+#define RCC_C1CIFCLRR_HSERDYF BIT(3)
+#define RCC_C1CIFCLRR_MSIRDYF BIT(4)
+#define RCC_C1CIFCLRR_PLL1RDYF BIT(5)
+#define RCC_C1CIFCLRR_PLL2RDYF BIT(6)
+#define RCC_C1CIFCLRR_PLL3RDYF BIT(7)
+#define RCC_C1CIFCLRR_PLL4RDYF BIT(8)
+#define RCC_C1CIFCLRR_PLL5RDYF BIT(9)
+#define RCC_C1CIFCLRR_PLL6RDYF BIT(10)
+#define RCC_C1CIFCLRR_PLL7RDYF BIT(11)
+#define RCC_C1CIFCLRR_PLL8RDYF BIT(12)
+#define RCC_C1CIFCLRR_LSECSSF BIT(16)
+#define RCC_C1CIFCLRR_WKUPF BIT(20)
+
+/* RCC_C2CIESETR register fields */
+#define RCC_C2CIESETR_LSIRDYIE BIT(0)
+#define RCC_C2CIESETR_LSERDYIE BIT(1)
+#define RCC_C2CIESETR_HSIRDYIE BIT(2)
+#define RCC_C2CIESETR_HSERDYIE BIT(3)
+#define RCC_C2CIESETR_MSIRDYIE BIT(4)
+#define RCC_C2CIESETR_PLL1RDYIE BIT(5)
+#define RCC_C2CIESETR_PLL2RDYIE BIT(6)
+#define RCC_C2CIESETR_PLL3RDYIE BIT(7)
+#define RCC_C2CIESETR_PLL4RDYIE BIT(8)
+#define RCC_C2CIESETR_PLL5RDYIE BIT(9)
+#define RCC_C2CIESETR_PLL6RDYIE BIT(10)
+#define RCC_C2CIESETR_PLL7RDYIE BIT(11)
+#define RCC_C2CIESETR_PLL8RDYIE BIT(12)
+#define RCC_C2CIESETR_LSECSSIE BIT(16)
+#define RCC_C2CIESETR_WKUPIE BIT(20)
+
+/* RCC_C2CIFCLRR register fields */
+#define RCC_C2CIFCLRR_LSIRDYF BIT(0)
+#define RCC_C2CIFCLRR_LSERDYF BIT(1)
+#define RCC_C2CIFCLRR_HSIRDYF BIT(2)
+#define RCC_C2CIFCLRR_HSERDYF BIT(3)
+#define RCC_C2CIFCLRR_MSIRDYF BIT(4)
+#define RCC_C2CIFCLRR_PLL1RDYF BIT(5)
+#define RCC_C2CIFCLRR_PLL2RDYF BIT(6)
+#define RCC_C2CIFCLRR_PLL3RDYF BIT(7)
+#define RCC_C2CIFCLRR_PLL4RDYF BIT(8)
+#define RCC_C2CIFCLRR_PLL5RDYF BIT(9)
+#define RCC_C2CIFCLRR_PLL6RDYF BIT(10)
+#define RCC_C2CIFCLRR_PLL7RDYF BIT(11)
+#define RCC_C2CIFCLRR_PLL8RDYF BIT(12)
+#define RCC_C2CIFCLRR_LSECSSF BIT(16)
+#define RCC_C2CIFCLRR_WKUPF BIT(20)
+
+/* RCC_CxCIESETR register fields */
+#define RCC_CxCIESETR_LSIRDYIE BIT(0)
+#define RCC_CxCIESETR_LSERDYIE BIT(1)
+#define RCC_CxCIESETR_HSIRDYIE BIT(2)
+#define RCC_CxCIESETR_HSERDYIE BIT(3)
+#define RCC_CxCIESETR_CSIRDYIE BIT(4)
+#define RCC_CxCIESETR_SHSIRDYIE BIT(5)
+#define RCC_CxCIESETR_PLL1RDYIE BIT(6)
+#define RCC_CxCIESETR_PLL2RDYIE BIT(7)
+#define RCC_CxCIESETR_PLL3RDYIE BIT(8)
+#define RCC_CxCIESETR_PLL4RDYIE BIT(9)
+#define RCC_CxCIESETR_PLL5RDYIE BIT(10)
+#define RCC_CxCIESETR_PLL6RDYIE BIT(11)
+#define RCC_CxCIESETR_PLL7RDYIE BIT(12)
+#define RCC_CxCIESETR_PLL8RDYIE BIT(13)
+#define RCC_CxCIESETR_LSECSSIE BIT(16)
+#define RCC_CxCIESETR_WKUPIE BIT(20)
+
+/* RCC_CxCIFCLRR register fields */
+#define RCC_CxCIFCLRR_LSIRDYF BIT(0)
+#define RCC_CxCIFCLRR_LSERDYF BIT(1)
+#define RCC_CxCIFCLRR_HSIRDYF BIT(2)
+#define RCC_CxCIFCLRR_HSERDYF BIT(3)
+#define RCC_CxCIFCLRR_CSIRDYF BIT(4)
+#define RCC_CxCIFCLRR_SHSIRDYF BIT(5)
+#define RCC_CxCIFCLRR_PLL1RDYF BIT(6)
+#define RCC_CxCIFCLRR_PLL2RDYF BIT(7)
+#define RCC_CxCIFCLRR_PLL3RDYF BIT(8)
+#define RCC_CxCIFCLRR_PLL4RDYF BIT(9)
+#define RCC_CxCIFCLRR_PLL5RDYF BIT(10)
+#define RCC_CxCIFCLRR_PLL6RDYF BIT(11)
+#define RCC_CxCIFCLRR_PLL7RDYF BIT(12)
+#define RCC_CxCIFCLRR_PLL8RDYF BIT(13)
+#define RCC_CxCIFCLRR_LSECSSF BIT(16)
+#define RCC_CxCIFCLRR_WKUPF BIT(20)
+
+/* RCC_IWDGC1FZSETR register fields */
+#define RCC_IWDGC1FZSETR_FZ_IWDG1 BIT(0)
+#define RCC_IWDGC1FZSETR_FZ_IWDG2 BIT(1)
+
+/* RCC_IWDGC1FZCLRR register fields */
+#define RCC_IWDGC1FZCLRR_FZ_IWDG1 BIT(0)
+#define RCC_IWDGC1FZCLRR_FZ_IWDG2 BIT(1)
+
+/* RCC_IWDGC1CFGSETR register fields */
+#define RCC_IWDGC1CFGSETR_IWDG1_SYSRSTEN BIT(0)
+#define RCC_IWDGC1CFGSETR_IWDG2_SYSRSTEN BIT(2)
+#define RCC_IWDGC1CFGSETR_IWDG2_KERRST BIT(18)
+
+/* RCC_IWDGC1CFGCLRR register fields */
+#define RCC_IWDGC1CFGCLRR_IWDG1_SYSRSTEN BIT(0)
+#define RCC_IWDGC1CFGCLRR_IWDG2_SYSRSTEN BIT(2)
+#define RCC_IWDGC1CFGCLRR_IWDG2_KERRST BIT(18)
+
+/* RCC_IWDGC2FZSETR register fields */
+#define RCC_IWDGC2FZSETR_FZ_IWDG3 BIT(0)
+#define RCC_IWDGC2FZSETR_FZ_IWDG4 BIT(1)
+
+/* RCC_IWDGC2FZCLRR register fields */
+#define RCC_IWDGC2FZCLRR_FZ_IWDG3 BIT(0)
+#define RCC_IWDGC2FZCLRR_FZ_IWDG4 BIT(1)
+
+/* RCC_IWDGC2CFGSETR register fields */
+#define RCC_IWDGC2CFGSETR_IWDG3_SYSRSTEN BIT(0)
+#define RCC_IWDGC2CFGSETR_IWDG4_SYSRSTEN BIT(2)
+#define RCC_IWDGC2CFGSETR_IWDG4_KERRST BIT(18)
+
+/* RCC_IWDGC2CFGCLRR register fields */
+#define RCC_IWDGC2CFGCLRR_IWDG3_SYSRSTEN BIT(0)
+#define RCC_IWDGC2CFGCLRR_IWDG4_SYSRSTEN BIT(2)
+#define RCC_IWDGC2CFGCLRR_IWDG4_KERRST BIT(18)
+
+/* RCC_MCO1CFGR register fields */
+#define RCC_MCO1CFGR_MCO1SEL BIT(0)
+#define RCC_MCO1CFGR_MCO1ON BIT(8)
+
+/* RCC_MCO2CFGR register fields */
+#define RCC_MCO2CFGR_MCO2SEL BIT(0)
+#define RCC_MCO2CFGR_MCO2ON BIT(8)
+
+/* RCC_MCOxCFGR register fields */
+#define RCC_MCOxCFGR_MCOxSEL BIT(0)
+#define RCC_MCOxCFGR_MCOxON BIT(8)
+
+/* RCC_OCENSETR register fields */
+#define RCC_OCENSETR_HSION BIT(0)
+#define RCC_OCENSETR_HSIKERON BIT(1)
+#define RCC_OCENSETR_MSION BIT(2)
+#define RCC_OCENSETR_MSIKERON BIT(3)
+#define RCC_OCENSETR_HSEDIV2ON BIT(5)
+#define RCC_OCENSETR_HSEDIV2BYP BIT(6)
+#define RCC_OCENSETR_HSEDIGBYP BIT(7)
+#define RCC_OCENSETR_HSEON BIT(8)
+#define RCC_OCENSETR_HSEKERON BIT(9)
+#define RCC_OCENSETR_HSEBYP BIT(10)
+#define RCC_OCENSETR_HSECSSON BIT(11)
+
+/* RCC_OCENCLRR register fields */
+#define RCC_OCENCLRR_HSION BIT(0)
+#define RCC_OCENCLRR_HSIKERON BIT(1)
+#define RCC_OCENCLRR_MSION BIT(2)
+#define RCC_OCENCLRR_MSIKERON BIT(3)
+#define RCC_OCENCLRR_HSEDIV2ON BIT(5)
+#define RCC_OCENCLRR_HSEDIV2BYP BIT(6)
+#define RCC_OCENCLRR_HSEDIGBYP BIT(7)
+#define RCC_OCENCLRR_HSEON BIT(8)
+#define RCC_OCENCLRR_HSEKERON BIT(9)
+#define RCC_OCENCLRR_HSEBYP BIT(10)
+
+/* RCC_OCRDYR register fields */
+#define RCC_OCRDYR_HSIRDY BIT(0)
+#define RCC_OCRDYR_MSIRDY BIT(2)
+#define RCC_OCRDYR_HSERDY BIT(8)
+#define RCC_OCRDYR_CKREST BIT(25)
+
+/* RCC_HSICFGR register fields */
+#define RCC_HSICFGR_HSITRIM_MASK GENMASK_32(14, 8)
+#define RCC_HSICFGR_HSITRIM_SHIFT 8
+#define RCC_HSICFGR_HSICAL_MASK GENMASK_32(24, 16)
+#define RCC_HSICFGR_HSICAL_SHIFT 16
+
+/* RCC_MSICFGR register fields */
+#define RCC_MSICFGR_MSITRIM_MASK GENMASK_32(12, 8)
+#define RCC_MSICFGR_MSITRIM_SHIFT 8
+#define RCC_MSICFGR_MSICAL_MASK GENMASK_32(23, 16)
+#define RCC_MSICFGR_MSICAL_SHIFT 16
+
+/* RCC_LSICR register fields */
+#define RCC_LSICR_LSION BIT(0)
+#define RCC_LSICR_LSIRDY BIT(1)
+
+/* RCC_RTCDIVR register fields */
+#define RCC_RTCDIVR_RTCDIV_MASK GENMASK_32(5, 0)
+#define RCC_RTCDIVR_RTCDIV_SHIFT 0
+
+/* RCC_APB1DIVR register fields */
+#define RCC_APB1DIVR_APB1DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB1DIVR_APB1DIV_SHIFT 0
+#define RCC_APB1DIVR_APB1DIVRDY BIT(31)
+
+/* RCC_APB2DIVR register fields */
+#define RCC_APB2DIVR_APB2DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB2DIVR_APB2DIV_SHIFT 0
+#define RCC_APB2DIVR_APB2DIVRDY BIT(31)
+
+/* RCC_APB3DIVR register fields */
+#define RCC_APB3DIVR_APB3DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB3DIVR_APB3DIV_SHIFT 0
+#define RCC_APB3DIVR_APB3DIVRDY BIT(31)
+
+/* RCC_APB4DIVR register fields */
+#define RCC_APB4DIVR_APB4DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB4DIVR_APB4DIV_SHIFT 0
+#define RCC_APB4DIVR_APB4DIVRDY BIT(31)
+
+/* RCC_APB5DIVR register fields */
+#define RCC_APB5DIVR_APB5DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB5DIVR_APB5DIV_SHIFT 0
+#define RCC_APB5DIVR_APB5DIVRDY BIT(31)
+
+/* RCC_APBDBGDIVR register fields */
+#define RCC_APBDBGDIVR_APBDBGDIV_MASK GENMASK_32(2, 0)
+#define RCC_APBDBGDIVR_APBDBGDIV_SHIFT 0
+#define RCC_APBDBGDIVR_APBDBGDIVRDY BIT(31)
+
+/* RCC_APBxDIVR register fields */
+#define RCC_APBxDIVR_APBxDIV_MASK GENMASK_32(2, 0)
+#define RCC_APBxDIVR_APBxDIV_SHIFT 0
+#define RCC_APBxDIVR_APBxDIVRDY BIT(31)
+
+/* RCC_TIMG1PRER register fields */
+#define RCC_TIMG1PRER_TIMG1PRE BIT(0)
+#define RCC_TIMG1PRER_TIMG1PRERDY BIT(31)
+
+/* RCC_TIMG2PRER register fields */
+#define RCC_TIMG2PRER_TIMG2PRE BIT(0)
+#define RCC_TIMG2PRER_TIMG2PRERDY BIT(31)
+
+/* RCC_TIMGxPRER register fields */
+#define RCC_TIMGxPRER_TIMGxPRE BIT(0)
+#define RCC_TIMGxPRER_TIMGxPRERDY BIT(31)
+
+/* RCC_LSMCUDIVR register fields */
+#define RCC_LSMCUDIVR_LSMCUDIV BIT(0)
+#define RCC_LSMCUDIVR_LSMCUDIVRDY BIT(31)
+
+/* RCC_DDRCPCFGR register fields */
+#define RCC_DDRCPCFGR_DDRCPRST BIT(0)
+#define RCC_DDRCPCFGR_DDRCPEN BIT(1)
+#define RCC_DDRCPCFGR_DDRCPLPEN BIT(2)
+
+/* RCC_DDRCAPBCFGR register fields */
+#define RCC_DDRCAPBCFGR_DDRCAPBRST BIT(0)
+#define RCC_DDRCAPBCFGR_DDRCAPBEN BIT(1)
+#define RCC_DDRCAPBCFGR_DDRCAPBLPEN BIT(2)
+
+/* RCC_DDRPHYCAPBCFGR register fields */
+#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST BIT(0)
+#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN BIT(1)
+#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN BIT(2)
+
+/* RCC_DDRPHYCCFGR register fields */
+#define RCC_DDRPHYCCFGR_DDRPHYCEN BIT(1)
+
+/* RCC_DDRCFGR register fields */
+#define RCC_DDRCFGR_DDRCFGRST BIT(0)
+#define RCC_DDRCFGR_DDRCFGEN BIT(1)
+#define RCC_DDRCFGR_DDRCFGLPEN BIT(2)
+
+/* RCC_DDRITFCFGR register fields */
+#define RCC_DDRITFCFGR_DDRRST BIT(0)
+#define RCC_DDRITFCFGR_DDRCKMOD_MASK GENMASK_32(5, 4)
+#define RCC_DDRITFCFGR_DDRCKMOD_SHIFT 4
+#define RCC_DDRITFCFGR_DDRCKMOD_HSR BIT(5)
+#define RCC_DDRITFCFGR_DDRSHR BIT(8)
+#define RCC_DDRITFCFGR_DDRPHYDLP BIT(16)
+
+/* RCC_SYSRAMCFGR register fields */
+#define RCC_SYSRAMCFGR_SYSRAMEN BIT(1)
+#define RCC_SYSRAMCFGR_SYSRAMLPEN BIT(2)
+
+/* RCC_SRAM1CFGR register fields */
+#define RCC_SRAM1CFGR_SRAM1EN BIT(1)
+#define RCC_SRAM1CFGR_SRAM1LPEN BIT(2)
+
+/* RCC_RETRAMCFGR register fields */
+#define RCC_RETRAMCFGR_RETRAMEN BIT(1)
+#define RCC_RETRAMCFGR_RETRAMLPEN BIT(2)
+
+/* RCC_BKPSRAMCFGR register fields */
+#define RCC_BKPSRAMCFGR_BKPSRAMEN BIT(1)
+#define RCC_BKPSRAMCFGR_BKPSRAMLPEN BIT(2)
+
+/* RCC_OSPI1CFGR register fields */
+#define RCC_OSPI1CFGR_OSPI1RST BIT(0)
+#define RCC_OSPI1CFGR_OSPI1EN BIT(1)
+#define RCC_OSPI1CFGR_OSPI1LPEN BIT(2)
+#define RCC_OSPI1CFGR_OTFDEC1RST BIT(8)
+#define RCC_OSPI1CFGR_OSPI1DLLRST BIT(16)
+
+/* RCC_OSPIxCFGR register fields */
+#define RCC_OSPIxCFGR_OSPIxRST BIT(0)
+#define RCC_OSPIxCFGR_OSPIxEN BIT(1)
+#define RCC_OSPIxCFGR_OSPIxLPEN BIT(2)
+#define RCC_OSPIxCFGR_OTFDECxRST BIT(8)
+#define RCC_OSPIxCFGR_OSPIxDLLRST BIT(16)
+
+/* RCC_FMCCFGR register fields */
+#define RCC_FMCCFGR_FMCRST BIT(0)
+#define RCC_FMCCFGR_FMCEN BIT(1)
+#define RCC_FMCCFGR_FMCLPEN BIT(2)
+
+/* RCC_DBGCFGR register fields */
+#define RCC_DBGCFGR_DBGEN BIT(8)
+#define RCC_DBGCFGR_TRACEEN BIT(9)
+#define RCC_DBGCFGR_DBGMCUEN BIT(10)
+#define RCC_DBGCFGR_DBGRST BIT(12)
+
+/* RCC_STMCFGR register fields */
+#define RCC_STMCFGR_STMEN BIT(1)
+#define RCC_STMCFGR_STMLPEN BIT(2)
+
+/* RCC_ETRCFGR register fields */
+#define RCC_ETRCFGR_ETREN BIT(1)
+#define RCC_ETRCFGR_ETRLPEN BIT(2)
+
+/* RCC_GPIOACFGR register fields */
+#define RCC_GPIOACFGR_GPIOARST BIT(0)
+#define RCC_GPIOACFGR_GPIOAEN BIT(1)
+#define RCC_GPIOACFGR_GPIOALPEN BIT(2)
+
+/* RCC_GPIOBCFGR register fields */
+#define RCC_GPIOBCFGR_GPIOBRST BIT(0)
+#define RCC_GPIOBCFGR_GPIOBEN BIT(1)
+#define RCC_GPIOBCFGR_GPIOBLPEN BIT(2)
+
+/* RCC_GPIOCCFGR register fields */
+#define RCC_GPIOCCFGR_GPIOCRST BIT(0)
+#define RCC_GPIOCCFGR_GPIOCEN BIT(1)
+#define RCC_GPIOCCFGR_GPIOCLPEN BIT(2)
+
+/* RCC_GPIODCFGR register fields */
+#define RCC_GPIODCFGR_GPIODRST BIT(0)
+#define RCC_GPIODCFGR_GPIODEN BIT(1)
+#define RCC_GPIODCFGR_GPIODLPEN BIT(2)
+
+/* RCC_GPIOECFGR register fields */
+#define RCC_GPIOECFGR_GPIOERST BIT(0)
+#define RCC_GPIOECFGR_GPIOEEN BIT(1)
+#define RCC_GPIOECFGR_GPIOELPEN BIT(2)
+
+/* RCC_GPIOFCFGR register fields */
+#define RCC_GPIOFCFGR_GPIOFRST BIT(0)
+#define RCC_GPIOFCFGR_GPIOFEN BIT(1)
+#define RCC_GPIOFCFGR_GPIOFLPEN BIT(2)
+
+/* RCC_GPIOGCFGR register fields */
+#define RCC_GPIOGCFGR_GPIOGRST BIT(0)
+#define RCC_GPIOGCFGR_GPIOGEN BIT(1)
+#define RCC_GPIOGCFGR_GPIOGLPEN BIT(2)
+
+/* RCC_GPIOHCFGR register fields */
+#define RCC_GPIOHCFGR_GPIOHRST BIT(0)
+#define RCC_GPIOHCFGR_GPIOHEN BIT(1)
+#define RCC_GPIOHCFGR_GPIOHLPEN BIT(2)
+
+/* RCC_GPIOICFGR register fields */
+#define RCC_GPIOICFGR_GPIOIRST BIT(0)
+#define RCC_GPIOICFGR_GPIOIEN BIT(1)
+#define RCC_GPIOICFGR_GPIOILPEN BIT(2)
+
+/* RCC_GPIOZCFGR register fields */
+#define RCC_GPIOZCFGR_GPIOZRST BIT(0)
+#define RCC_GPIOZCFGR_GPIOZEN BIT(1)
+#define RCC_GPIOZCFGR_GPIOZLPEN BIT(2)
+
+/* RCC_GPIOxCFGR register fields */
+#define RCC_GPIOxCFGR_GPIOxRST BIT(0)
+#define RCC_GPIOxCFGR_GPIOxEN BIT(1)
+#define RCC_GPIOxCFGR_GPIOxLPEN BIT(2)
+#define RCC_GPIOxCFGR_GPIOxAMEN BIT(3)
+
+/* RCC_HPDMA1CFGR register fields */
+#define RCC_HPDMA1CFGR_HPDMA1RST BIT(0)
+#define RCC_HPDMA1CFGR_HPDMA1EN BIT(1)
+#define RCC_HPDMA1CFGR_HPDMA1LPEN BIT(2)
+
+/* RCC_HPDMA2CFGR register fields */
+#define RCC_HPDMA2CFGR_HPDMA2RST BIT(0)
+#define RCC_HPDMA2CFGR_HPDMA2EN BIT(1)
+#define RCC_HPDMA2CFGR_HPDMA2LPEN BIT(2)
+
+/* RCC_HPDMA3CFGR register fields */
+#define RCC_HPDMA3CFGR_HPDMA3RST BIT(0)
+#define RCC_HPDMA3CFGR_HPDMA3EN BIT(1)
+#define RCC_HPDMA3CFGR_HPDMA3LPEN BIT(2)
+
+/* RCC_HPDMAxCFGR register fields */
+#define RCC_HPDMAxCFGR_HPDMAxRST BIT(0)
+#define RCC_HPDMAxCFGR_HPDMAxEN BIT(1)
+#define RCC_HPDMAxCFGR_HPDMAxLPEN BIT(2)
+
+/* RCC_IPCC1CFGR register fields */
+#define RCC_IPCC1CFGR_IPCC1RST BIT(0)
+#define RCC_IPCC1CFGR_IPCC1EN BIT(1)
+#define RCC_IPCC1CFGR_IPCC1LPEN BIT(2)
+
+/* RCC_RTCCFGR register fields */
+#define RCC_RTCCFGR_RTCEN BIT(1)
+#define RCC_RTCCFGR_RTCLPEN BIT(2)
+
+/* RCC_SYSCPU1CFGR register fields */
+#define RCC_SYSCPU1CFGR_SYSCPU1EN BIT(1)
+#define RCC_SYSCPU1CFGR_SYSCPU1LPEN BIT(2)
+
+/* RCC_BSECCFGR register fields */
+#define RCC_BSECCFGR_BSECEN BIT(1)
+#define RCC_BSECCFGR_BSECLPEN BIT(2)
+
+/* RCC_PLL2CFGR1 register fields */
+#define RCC_PLL2CFGR1_SSMODRST BIT(0)
+#define RCC_PLL2CFGR1_PLLEN BIT(8)
+#define RCC_PLL2CFGR1_PLLRDY BIT(24)
+#define RCC_PLL2CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL2CFGR2 register fields */
+#define RCC_PLL2CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL2CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL2CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL2CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL2CFGR3 register fields */
+#define RCC_PLL2CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL2CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL2CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL2CFGR3_DACEN BIT(25)
+#define RCC_PLL2CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL2CFGR4 register fields */
+#define RCC_PLL2CFGR4_DSMEN BIT(8)
+#define RCC_PLL2CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL2CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL2CFGR5 register fields */
+#define RCC_PLL2CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL2CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL2CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL2CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL2CFGR6 register fields */
+#define RCC_PLL2CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL2CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL2CFGR7 register fields */
+#define RCC_PLL2CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL2CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLLxCFGR1 register fields */
+#define RCC_PLLxCFGR1_SSMODRST BIT(0)
+#define RCC_PLLxCFGR1_PLLEN BIT(8)
+#define RCC_PLLxCFGR1_PLLRDY BIT(24)
+#define RCC_PLLxCFGR1_CKREFST BIT(28)
+
+/* RCC_PLLxCFGR2 register fields */
+#define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLLxCFGR2_FREFDIV_SHIFT 0
+#define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLLxCFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLLxCFGR3 register fields */
+#define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLLxCFGR3_FRACIN_SHIFT 0
+#define RCC_PLLxCFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLLxCFGR3_DACEN BIT(25)
+#define RCC_PLLxCFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLLxCFGR4 register fields */
+#define RCC_PLLxCFGR4_DSMEN BIT(8)
+#define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLLxCFGR4_BYPASS BIT(10)
+
+/* RCC_PLLxCFGR5 register fields */
+#define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLLxCFGR5_DIVVAL_SHIFT 0
+#define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLLxCFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLLxCFGR6 register fields */
+#define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLLxCFGR7 register fields */
+#define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_HSIFMONCR register fields */
+#define RCC_HSIFMONCR_HSIREF_MASK GENMASK_32(10, 0)
+#define RCC_HSIFMONCR_HSIREF_SHIFT 0
+#define RCC_HSIFMONCR_HSIMONEN BIT(15)
+#define RCC_HSIFMONCR_HSIDEV_MASK GENMASK_32(21, 16)
+#define RCC_HSIFMONCR_HSIDEV_SHIFT 16
+#define RCC_HSIFMONCR_HSIMONIE BIT(30)
+#define RCC_HSIFMONCR_HSIMONF BIT(31)
+
+/* RCC_HSIFVALR register fields */
+#define RCC_HSIFVALR_HSIVAL_MASK GENMASK_32(10, 0)
+#define RCC_HSIFVALR_HSIVAL_SHIFT 0
+
+/* RCC_MSIFMONCR register fields */
+#define RCC_MSIFMONCR_MSIREF_MASK GENMASK_32(8, 0)
+#define RCC_MSIFMONCR_MSIREF_SHIFT 0
+#define RCC_MSIFMONCR_MSIMONEN BIT(15)
+#define RCC_MSIFMONCR_MSIDEV_MASK GENMASK_32(20, 16)
+#define RCC_MSIFMONCR_MSIDEV_SHIFT 16
+#define RCC_MSIFMONCR_MSIMONIE BIT(30)
+#define RCC_MSIFMONCR_MSIMONF BIT(31)
+
+/* RCC_MSIFVALR register fields */
+#define RCC_MSIFVALR_MSIVAL_MASK GENMASK_32(8, 0)
+#define RCC_MSIFVALR_MSIVAL_SHIFT 0
+
+/* RCC_TIM1CFGR register fields */
+#define RCC_TIM1CFGR_TIM1RST BIT(0)
+#define RCC_TIM1CFGR_TIM1EN BIT(1)
+#define RCC_TIM1CFGR_TIM1LPEN BIT(2)
+
+/* RCC_TIM2CFGR register fields */
+#define RCC_TIM2CFGR_TIM2RST BIT(0)
+#define RCC_TIM2CFGR_TIM2EN BIT(1)
+#define RCC_TIM2CFGR_TIM2LPEN BIT(2)
+
+/* RCC_TIM3CFGR register fields */
+#define RCC_TIM3CFGR_TIM3RST BIT(0)
+#define RCC_TIM3CFGR_TIM3EN BIT(1)
+#define RCC_TIM3CFGR_TIM3LPEN BIT(2)
+
+/* RCC_TIM4CFGR register fields */
+#define RCC_TIM4CFGR_TIM4RST BIT(0)
+#define RCC_TIM4CFGR_TIM4EN BIT(1)
+#define RCC_TIM4CFGR_TIM4LPEN BIT(2)
+
+/* RCC_TIM5CFGR register fields */
+#define RCC_TIM5CFGR_TIM5RST BIT(0)
+#define RCC_TIM5CFGR_TIM5EN BIT(1)
+#define RCC_TIM5CFGR_TIM5LPEN BIT(2)
+
+/* RCC_TIM6CFGR register fields */
+#define RCC_TIM6CFGR_TIM6RST BIT(0)
+#define RCC_TIM6CFGR_TIM6EN BIT(1)
+#define RCC_TIM6CFGR_TIM6LPEN BIT(2)
+
+/* RCC_TIM7CFGR register fields */
+#define RCC_TIM7CFGR_TIM7RST BIT(0)
+#define RCC_TIM7CFGR_TIM7EN BIT(1)
+#define RCC_TIM7CFGR_TIM7LPEN BIT(2)
+
+/* RCC_TIM8CFGR register fields */
+#define RCC_TIM8CFGR_TIM8RST BIT(0)
+#define RCC_TIM8CFGR_TIM8EN BIT(1)
+#define RCC_TIM8CFGR_TIM8LPEN BIT(2)
+
+/* RCC_TIM10CFGR register fields */
+#define RCC_TIM10CFGR_TIM10RST BIT(0)
+#define RCC_TIM10CFGR_TIM10EN BIT(1)
+#define RCC_TIM10CFGR_TIM10LPEN BIT(2)
+
+/* RCC_TIM11CFGR register fields */
+#define RCC_TIM11CFGR_TIM11RST BIT(0)
+#define RCC_TIM11CFGR_TIM11EN BIT(1)
+#define RCC_TIM11CFGR_TIM11LPEN BIT(2)
+
+/* RCC_TIM12CFGR register fields */
+#define RCC_TIM12CFGR_TIM12RST BIT(0)
+#define RCC_TIM12CFGR_TIM12EN BIT(1)
+#define RCC_TIM12CFGR_TIM12LPEN BIT(2)
+
+/* RCC_TIM13CFGR register fields */
+#define RCC_TIM13CFGR_TIM13RST BIT(0)
+#define RCC_TIM13CFGR_TIM13EN BIT(1)
+#define RCC_TIM13CFGR_TIM13LPEN BIT(2)
+
+/* RCC_TIM14CFGR register fields */
+#define RCC_TIM14CFGR_TIM14RST BIT(0)
+#define RCC_TIM14CFGR_TIM14EN BIT(1)
+#define RCC_TIM14CFGR_TIM14LPEN BIT(2)
+
+/* RCC_TIM15CFGR register fields */
+#define RCC_TIM15CFGR_TIM15RST BIT(0)
+#define RCC_TIM15CFGR_TIM15EN BIT(1)
+#define RCC_TIM15CFGR_TIM15LPEN BIT(2)
+
+/* RCC_TIM16CFGR register fields */
+#define RCC_TIM16CFGR_TIM16RST BIT(0)
+#define RCC_TIM16CFGR_TIM16EN BIT(1)
+#define RCC_TIM16CFGR_TIM16LPEN BIT(2)
+
+/* RCC_TIM17CFGR register fields */
+#define RCC_TIM17CFGR_TIM17RST BIT(0)
+#define RCC_TIM17CFGR_TIM17EN BIT(1)
+#define RCC_TIM17CFGR_TIM17LPEN BIT(2)
+
+/* RCC_LPTIM1CFGR register fields */
+#define RCC_LPTIM1CFGR_LPTIM1RST BIT(0)
+#define RCC_LPTIM1CFGR_LPTIM1EN BIT(1)
+#define RCC_LPTIM1CFGR_LPTIM1LPEN BIT(2)
+
+/* RCC_LPTIM2CFGR register fields */
+#define RCC_LPTIM2CFGR_LPTIM2RST BIT(0)
+#define RCC_LPTIM2CFGR_LPTIM2EN BIT(1)
+#define RCC_LPTIM2CFGR_LPTIM2LPEN BIT(2)
+
+/* RCC_LPTIM3CFGR register fields */
+#define RCC_LPTIM3CFGR_LPTIM3RST BIT(0)
+#define RCC_LPTIM3CFGR_LPTIM3EN BIT(1)
+#define RCC_LPTIM3CFGR_LPTIM3LPEN BIT(2)
+
+/* RCC_LPTIM4CFGR register fields */
+#define RCC_LPTIM4CFGR_LPTIM4RST BIT(0)
+#define RCC_LPTIM4CFGR_LPTIM4EN BIT(1)
+#define RCC_LPTIM4CFGR_LPTIM4LPEN BIT(2)
+
+/* RCC_LPTIM5CFGR register fields */
+#define RCC_LPTIM5CFGR_LPTIM5RST BIT(0)
+#define RCC_LPTIM5CFGR_LPTIM5EN BIT(1)
+#define RCC_LPTIM5CFGR_LPTIM5LPEN BIT(2)
+
+/* RCC_LPTIMxCFGR register fields */
+#define RCC_LPTIMxCFGR_LPTIMxRST BIT(0)
+#define RCC_LPTIMxCFGR_LPTIMxEN BIT(1)
+#define RCC_LPTIMxCFGR_LPTIMxLPEN BIT(2)
+#define RCC_LPTIMxCFGR_LPTIMxAMEN BIT(3)
+
+/* RCC_SPI1CFGR register fields */
+#define RCC_SPI1CFGR_SPI1RST BIT(0)
+#define RCC_SPI1CFGR_SPI1EN BIT(1)
+#define RCC_SPI1CFGR_SPI1LPEN BIT(2)
+
+/* RCC_SPI2CFGR register fields */
+#define RCC_SPI2CFGR_SPI2RST BIT(0)
+#define RCC_SPI2CFGR_SPI2EN BIT(1)
+#define RCC_SPI2CFGR_SPI2LPEN BIT(2)
+
+/* RCC_SPI3CFGR register fields */
+#define RCC_SPI3CFGR_SPI3RST BIT(0)
+#define RCC_SPI3CFGR_SPI3EN BIT(1)
+#define RCC_SPI3CFGR_SPI3LPEN BIT(2)
+
+/* RCC_SPI4CFGR register fields */
+#define RCC_SPI4CFGR_SPI4RST BIT(0)
+#define RCC_SPI4CFGR_SPI4EN BIT(1)
+#define RCC_SPI4CFGR_SPI4LPEN BIT(2)
+
+/* RCC_SPI5CFGR register fields */
+#define RCC_SPI5CFGR_SPI5RST BIT(0)
+#define RCC_SPI5CFGR_SPI5EN BIT(1)
+#define RCC_SPI5CFGR_SPI5LPEN BIT(2)
+
+/* RCC_SPI6CFGR register fields */
+#define RCC_SPI6CFGR_SPI6RST BIT(0)
+#define RCC_SPI6CFGR_SPI6EN BIT(1)
+#define RCC_SPI6CFGR_SPI6LPEN BIT(2)
+
+/* RCC_SPIxCFGR register fields */
+#define RCC_SPIxCFGR_SPIxRST BIT(0)
+#define RCC_SPIxCFGR_SPIxEN BIT(1)
+#define RCC_SPIxCFGR_SPIxLPEN BIT(2)
+#define RCC_SPIxCFGR_SPIxAMEN BIT(3)
+
+/* RCC_SPDIFRXCFGR register fields */
+#define RCC_SPDIFRXCFGR_SPDIFRXRST BIT(0)
+#define RCC_SPDIFRXCFGR_SPDIFRXEN BIT(1)
+#define RCC_SPDIFRXCFGR_SPDIFRXLPEN BIT(2)
+
+/* RCC_USART1CFGR register fields */
+#define RCC_USART1CFGR_USART1RST BIT(0)
+#define RCC_USART1CFGR_USART1EN BIT(1)
+#define RCC_USART1CFGR_USART1LPEN BIT(2)
+
+/* RCC_USART2CFGR register fields */
+#define RCC_USART2CFGR_USART2RST BIT(0)
+#define RCC_USART2CFGR_USART2EN BIT(1)
+#define RCC_USART2CFGR_USART2LPEN BIT(2)
+
+/* RCC_USART3CFGR register fields */
+#define RCC_USART3CFGR_USART3RST BIT(0)
+#define RCC_USART3CFGR_USART3EN BIT(1)
+#define RCC_USART3CFGR_USART3LPEN BIT(2)
+
+/* RCC_UART4CFGR register fields */
+#define RCC_UART4CFGR_UART4RST BIT(0)
+#define RCC_UART4CFGR_UART4EN BIT(1)
+#define RCC_UART4CFGR_UART4LPEN BIT(2)
+
+/* RCC_UART5CFGR register fields */
+#define RCC_UART5CFGR_UART5RST BIT(0)
+#define RCC_UART5CFGR_UART5EN BIT(1)
+#define RCC_UART5CFGR_UART5LPEN BIT(2)
+
+/* RCC_USART6CFGR register fields */
+#define RCC_USART6CFGR_USART6RST BIT(0)
+#define RCC_USART6CFGR_USART6EN BIT(1)
+#define RCC_USART6CFGR_USART6LPEN BIT(2)
+
+/* RCC_UART7CFGR register fields */
+#define RCC_UART7CFGR_UART7RST BIT(0)
+#define RCC_UART7CFGR_UART7EN BIT(1)
+#define RCC_UART7CFGR_UART7LPEN BIT(2)
+
+/* RCC_USARTxCFGR register fields */
+#define RCC_USARTxCFGR_USARTxRST BIT(0)
+#define RCC_USARTxCFGR_USARTxEN BIT(1)
+#define RCC_USARTxCFGR_USARTxLPEN BIT(2)
+
+/* RCC_UARTxCFGR register fields */
+#define RCC_UARTxCFGR_UARTxRST BIT(0)
+#define RCC_UARTxCFGR_UARTxEN BIT(1)
+#define RCC_UARTxCFGR_UARTxLPEN BIT(2)
+
+/* RCC_LPUART1CFGR register fields */
+#define RCC_LPUART1CFGR_LPUART1RST BIT(0)
+#define RCC_LPUART1CFGR_LPUART1EN BIT(1)
+#define RCC_LPUART1CFGR_LPUART1LPEN BIT(2)
+
+/* RCC_I2C1CFGR register fields */
+#define RCC_I2C1CFGR_I2C1RST BIT(0)
+#define RCC_I2C1CFGR_I2C1EN BIT(1)
+#define RCC_I2C1CFGR_I2C1LPEN BIT(2)
+
+/* RCC_I2C2CFGR register fields */
+#define RCC_I2C2CFGR_I2C2RST BIT(0)
+#define RCC_I2C2CFGR_I2C2EN BIT(1)
+#define RCC_I2C2CFGR_I2C2LPEN BIT(2)
+
+/* RCC_I2C3CFGR register fields */
+#define RCC_I2C3CFGR_I2C3RST BIT(0)
+#define RCC_I2C3CFGR_I2C3EN BIT(1)
+#define RCC_I2C3CFGR_I2C3LPEN BIT(2)
+
+/* RCC_I2CxCFGR register fields */
+#define RCC_I2CxCFGR_I2CxRST BIT(0)
+#define RCC_I2CxCFGR_I2CxEN BIT(1)
+#define RCC_I2CxCFGR_I2CxLPEN BIT(2)
+#define RCC_I2CxCFGR_I2CxAMEN BIT(3)
+
+/* RCC_SAI1CFGR register fields */
+#define RCC_SAI1CFGR_SAI1RST BIT(0)
+#define RCC_SAI1CFGR_SAI1EN BIT(1)
+#define RCC_SAI1CFGR_SAI1LPEN BIT(2)
+
+/* RCC_SAI2CFGR register fields */
+#define RCC_SAI2CFGR_SAI2RST BIT(0)
+#define RCC_SAI2CFGR_SAI2EN BIT(1)
+#define RCC_SAI2CFGR_SAI2LPEN BIT(2)
+
+/* RCC_SAI3CFGR register fields */
+#define RCC_SAI3CFGR_SAI3RST BIT(0)
+#define RCC_SAI3CFGR_SAI3EN BIT(1)
+#define RCC_SAI3CFGR_SAI3LPEN BIT(2)
+
+/* RCC_SAI4CFGR register fields */
+#define RCC_SAI4CFGR_SAI4RST BIT(0)
+#define RCC_SAI4CFGR_SAI4EN BIT(1)
+#define RCC_SAI4CFGR_SAI4LPEN BIT(2)
+
+/* RCC_SAIxCFGR register fields */
+#define RCC_SAIxCFGR_SAIxRST BIT(0)
+#define RCC_SAIxCFGR_SAIxEN BIT(1)
+#define RCC_SAIxCFGR_SAIxLPEN BIT(2)
+
+/* RCC_MDF1CFGR register fields */
+#define RCC_MDF1CFGR_MDF1RST BIT(0)
+#define RCC_MDF1CFGR_MDF1EN BIT(1)
+#define RCC_MDF1CFGR_MDF1LPEN BIT(2)
+
+/* RCC_FDCANCFGR register fields */
+#define RCC_FDCANCFGR_FDCANRST BIT(0)
+#define RCC_FDCANCFGR_FDCANEN BIT(1)
+#define RCC_FDCANCFGR_FDCANLPEN BIT(2)
+
+/* RCC_HDPCFGR register fields */
+#define RCC_HDPCFGR_HDPRST BIT(0)
+#define RCC_HDPCFGR_HDPEN BIT(1)
+
+/* RCC_ADC1CFGR register fields */
+#define RCC_ADC1CFGR_ADC1RST BIT(0)
+#define RCC_ADC1CFGR_ADC1EN BIT(1)
+#define RCC_ADC1CFGR_ADC1LPEN BIT(2)
+#define RCC_ADC1CFGR_ADC1KERSEL BIT(12)
+
+/* RCC_ADC2CFGR register fields */
+#define RCC_ADC2CFGR_ADC2RST BIT(0)
+#define RCC_ADC2CFGR_ADC2EN BIT(1)
+#define RCC_ADC2CFGR_ADC2LPEN BIT(2)
+#define RCC_ADC2CFGR_ADC2KERSEL_MASK GENMASK_32(13, 12)
+#define RCC_ADC2CFGR_ADC2KERSEL_SHIFT 12
+
+/* RCC_ETH1CFGR register fields */
+#define RCC_ETH1CFGR_ETH1RST BIT(0)
+#define RCC_ETH1CFGR_ETH1MACEN BIT(1)
+#define RCC_ETH1CFGR_ETH1MACLPEN BIT(2)
+#define RCC_ETH1CFGR_ETH1STPEN BIT(4)
+#define RCC_ETH1CFGR_ETH1EN BIT(5)
+#define RCC_ETH1CFGR_ETH1LPEN BIT(6)
+#define RCC_ETH1CFGR_ETH1TXEN BIT(8)
+#define RCC_ETH1CFGR_ETH1TXLPEN BIT(9)
+#define RCC_ETH1CFGR_ETH1RXEN BIT(10)
+#define RCC_ETH1CFGR_ETH1RXLPEN BIT(11)
+
+/* RCC_ETH2CFGR register fields */
+#define RCC_ETH2CFGR_ETH2RST BIT(0)
+#define RCC_ETH2CFGR_ETH2MACEN BIT(1)
+#define RCC_ETH2CFGR_ETH2MACLPEN BIT(2)
+#define RCC_ETH2CFGR_ETH2STPEN BIT(4)
+#define RCC_ETH2CFGR_ETH2EN BIT(5)
+#define RCC_ETH2CFGR_ETH2LPEN BIT(6)
+#define RCC_ETH2CFGR_ETH2TXEN BIT(8)
+#define RCC_ETH2CFGR_ETH2TXLPEN BIT(9)
+#define RCC_ETH2CFGR_ETH2RXEN BIT(10)
+#define RCC_ETH2CFGR_ETH2RXLPEN BIT(11)
+
+/* RCC_ETHxCFGR register fields */
+#define RCC_ETHxCFGR_ETHxRST BIT(0)
+#define RCC_ETHxCFGR_ETHxMACEN BIT(1)
+#define RCC_ETHxCFGR_ETHxMACLPEN BIT(2)
+#define RCC_ETHxCFGR_ETHxSTPEN BIT(4)
+#define RCC_ETHxCFGR_ETHxEN BIT(5)
+#define RCC_ETHxCFGR_ETHxLPEN BIT(6)
+#define RCC_ETHxCFGR_ETHxTXEN BIT(8)
+#define RCC_ETHxCFGR_ETHxTXLPEN BIT(9)
+#define RCC_ETHxCFGR_ETHxRXEN BIT(10)
+#define RCC_ETHxCFGR_ETHxRXLPEN BIT(11)
+
+/* RCC_USBHCFGR register fields */
+#define RCC_USBHCFGR_USBHRST BIT(0)
+#define RCC_USBHCFGR_USBHEN BIT(1)
+#define RCC_USBHCFGR_USBHLPEN BIT(2)
+#define RCC_USBHCFGR_USBHSTPEN BIT(4)
+
+/* RCC_USB2PHY1CFGR register fields */
+#define RCC_USB2PHY1CFGR_USB2PHY1RST BIT(0)
+#define RCC_USB2PHY1CFGR_USB2PHY1EN BIT(1)
+#define RCC_USB2PHY1CFGR_USB2PHY1LPEN BIT(2)
+#define RCC_USB2PHY1CFGR_USB2PHY1STPEN BIT(4)
+#define RCC_USB2PHY1CFGR_USB2PHY1CKREFSEL BIT(15)
+
+/* RCC_OTGCFGR register fields */
+#define RCC_OTGCFGR_OTGRST BIT(0)
+#define RCC_OTGCFGR_OTGEN BIT(1)
+#define RCC_OTGCFGR_OTGLPEN BIT(2)
+
+/* RCC_USB2PHY2CFGR register fields */
+#define RCC_USB2PHY2CFGR_USB2PHY2RST BIT(0)
+#define RCC_USB2PHY2CFGR_USB2PHY2EN BIT(1)
+#define RCC_USB2PHY2CFGR_USB2PHY2LPEN BIT(2)
+#define RCC_USB2PHY2CFGR_USB2PHY2STPEN BIT(4)
+#define RCC_USB2PHY2CFGR_USB2PHY2CKREFSEL BIT(15)
+
+/* RCC_USB2PHYxCFGR register fields */
+#define RCC_USB2PHYxCFGR_USB2PHY1RST BIT(0)
+#define RCC_USB2PHYxCFGR_USB2PHY1EN BIT(1)
+#define RCC_USB2PHYxCFGR_USB2PHY1LPEN BIT(2)
+#define RCC_USB2PHYxCFGR_USB2PHY1STPEN BIT(4)
+#define RCC_USB2PHYxCFGR_USB2PHY1CKREFSEL BIT(15)
+
+/* RCC_STGENCFGR register fields */
+#define RCC_STGENCFGR_STGENEN BIT(1)
+#define RCC_STGENCFGR_STGENLPEN BIT(2)
+#define RCC_STGENCFGR_STGENSTPEN BIT(4)
+
+/* RCC_SDMMC1CFGR register fields */
+#define RCC_SDMMC1CFGR_SDMMC1RST BIT(0)
+#define RCC_SDMMC1CFGR_SDMMC1EN BIT(1)
+#define RCC_SDMMC1CFGR_SDMMC1LPEN BIT(2)
+#define RCC_SDMMC1CFGR_SDMMC1DLLRST BIT(16)
+
+/* RCC_SDMMC2CFGR register fields */
+#define RCC_SDMMC2CFGR_SDMMC2RST BIT(0)
+#define RCC_SDMMC2CFGR_SDMMC2EN BIT(1)
+#define RCC_SDMMC2CFGR_SDMMC2LPEN BIT(2)
+#define RCC_SDMMC2CFGR_SDMMC2DLLRST BIT(16)
+
+/* RCC_SDMMC3CFGR register fields */
+#define RCC_SDMMC3CFGR_SDMMC3RST BIT(0)
+#define RCC_SDMMC3CFGR_SDMMC3EN BIT(1)
+#define RCC_SDMMC3CFGR_SDMMC3LPEN BIT(2)
+#define RCC_SDMMC3CFGR_SDMMC3DLLRST BIT(16)
+
+/* RCC_SDMMCxCFGR register fields */
+#define RCC_SDMMCxCFGR_SDMMC1RST BIT(0)
+#define RCC_SDMMCxCFGR_SDMMC1EN BIT(1)
+#define RCC_SDMMCxCFGR_SDMMC1LPEN BIT(2)
+#define RCC_SDMMCxCFGR_SDMMC1DLLRST BIT(16)
+
+/* RCC_LTDCCFGR register fields */
+#define RCC_LTDCCFGR_LTDCRST BIT(0)
+#define RCC_LTDCCFGR_LTDCEN BIT(1)
+#define RCC_LTDCCFGR_LTDCLPEN BIT(2)
+
+/* RCC_CSICFGR register fields */
+#define RCC_CSICFGR_CSIRST BIT(0)
+#define RCC_CSICFGR_CSIEN BIT(1)
+#define RCC_CSICFGR_CSILPEN BIT(2)
+
+/* RCC_DCMIPPCFGR register fields */
+#define RCC_DCMIPPCFGR_DCMIPPRST BIT(0)
+#define RCC_DCMIPPCFGR_DCMIPPEN BIT(1)
+#define RCC_DCMIPPCFGR_DCMIPPLPEN BIT(2)
+
+/* RCC_DCMIPSSICFGR register fields */
+#define RCC_DCMIPSSICFGR_DCMIPSSIRST BIT(0)
+#define RCC_DCMIPSSICFGR_DCMIPSSIEN BIT(1)
+#define RCC_DCMIPSSICFGR_DCMIPSSILPEN BIT(2)
+
+/* RCC_RNG1CFGR register fields */
+#define RCC_RNG1CFGR_RNG1RST BIT(0)
+#define RCC_RNG1CFGR_RNG1EN BIT(1)
+#define RCC_RNG1CFGR_RNG1LPEN BIT(2)
+
+/* RCC_RNG2CFGR register fields */
+#define RCC_RNG2CFGR_RNG2RST BIT(0)
+#define RCC_RNG2CFGR_RNG2EN BIT(1)
+#define RCC_RNG2CFGR_RNG2LPEN BIT(2)
+
+/* RCC_PKACFGR register fields */
+#define RCC_PKACFGR_PKARST BIT(0)
+#define RCC_PKACFGR_PKAEN BIT(1)
+#define RCC_PKACFGR_PKALPEN BIT(2)
+
+/* RCC_SAESCFGR register fields */
+#define RCC_SAESCFGR_SAESRST BIT(0)
+#define RCC_SAESCFGR_SAESEN BIT(1)
+#define RCC_SAESCFGR_SAESLPEN BIT(2)
+
+/* RCC_HASH1CFGR register fields */
+#define RCC_HASH1CFGR_HASH1RST BIT(0)
+#define RCC_HASH1CFGR_HASH1EN BIT(1)
+#define RCC_HASH1CFGR_HASH1LPEN BIT(2)
+
+/* RCC_HASH2CFGR register fields */
+#define RCC_HASH2CFGR_HASH2RST BIT(0)
+#define RCC_HASH2CFGR_HASH2EN BIT(1)
+#define RCC_HASH2CFGR_HASH2LPEN BIT(2)
+
+/* RCC_CRYP1CFGR register fields */
+#define RCC_CRYP1CFGR_CRYP1RST BIT(0)
+#define RCC_CRYP1CFGR_CRYP1EN BIT(1)
+#define RCC_CRYP1CFGR_CRYP1LPEN BIT(2)
+
+/* RCC_CRYP2CFGR register fields */
+#define RCC_CRYP2CFGR_CRYP2RST BIT(0)
+#define RCC_CRYP2CFGR_CRYP2EN BIT(1)
+#define RCC_CRYP2CFGR_CRYP2LPEN BIT(2)
+
+/* RCC_CRYPxCFGR register fields */
+#define RCC_CRYPxCFGR_CRYPxRST BIT(0)
+#define RCC_CRYPxCFGR_CRYPxEN BIT(1)
+#define RCC_CRYPxCFGR_CRYPxLPEN BIT(2)
+
+/* RCC_IWDG1CFGR register fields */
+#define RCC_IWDG1CFGR_IWDG1EN BIT(1)
+#define RCC_IWDG1CFGR_IWDG1LPEN BIT(2)
+
+/* RCC_IWDG2CFGR register fields */
+#define RCC_IWDG2CFGR_IWDG2EN BIT(1)
+#define RCC_IWDG2CFGR_IWDG2LPEN BIT(2)
+
+/* RCC_IWDG3CFGR register fields */
+#define RCC_IWDG3CFGR_IWDG3EN BIT(1)
+#define RCC_IWDG3CFGR_IWDG3LPEN BIT(2)
+
+/* RCC_IWDG4CFGR register fields */
+#define RCC_IWDG4CFGR_IWDG4EN BIT(1)
+#define RCC_IWDG4CFGR_IWDG4LPEN BIT(2)
+
+/* RCC_IWDGxCFGR register fields */
+#define RCC_IWDGxCFGR_IWDGxEN BIT(1)
+#define RCC_IWDGxCFGR_IWDGxLPEN BIT(2)
+
+/* RCC_WWDG1CFGR register fields */
+#define RCC_WWDG1CFGR_WWDG1RST BIT(0)
+#define RCC_WWDG1CFGR_WWDG1EN BIT(1)
+#define RCC_WWDG1CFGR_WWDG1LPEN BIT(2)
+
+/* RCC_VREFCFGR register fields */
+#define RCC_VREFCFGR_VREFRST BIT(0)
+#define RCC_VREFCFGR_VREFEN BIT(1)
+#define RCC_VREFCFGR_VREFLPEN BIT(2)
+
+/* RCC_DTSCFGR register fields */
+#define RCC_DTSCFGR_DTSRST BIT(0)
+#define RCC_DTSCFGR_DTSEN BIT(1)
+#define RCC_DTSCFGR_DTSLPEN BIT(2)
+#define RCC_DTSCFGR_DTSKERSEL_MASK GENMASK_32(13, 12)
+#define RCC_DTSCFGR_DTSKERSEL_SHIFT 12
+
+/* RCC_CRCCFGR register fields */
+#define RCC_CRCCFGR_CRCRST BIT(0)
+#define RCC_CRCCFGR_CRCEN BIT(1)
+#define RCC_CRCCFGR_CRCLPEN BIT(2)
+
+/* RCC_SERCCFGR register fields */
+#define RCC_SERCCFGR_SERCRST BIT(0)
+#define RCC_SERCCFGR_SERCEN BIT(1)
+#define RCC_SERCCFGR_SERCLPEN BIT(2)
+
+/* RCC_DDRPERFMCFGR register fields */
+#define RCC_DDRPERFMCFGR_DDRPERFMRST BIT(0)
+#define RCC_DDRPERFMCFGR_DDRPERFMEN BIT(1)
+#define RCC_DDRPERFMCFGR_DDRPERFMLPEN BIT(2)
+
+/* RCC_I3C1CFGR register fields */
+#define RCC_I3C1CFGR_I3C1RST BIT(0)
+#define RCC_I3C1CFGR_I3C1EN BIT(1)
+#define RCC_I3C1CFGR_I3C1LPEN BIT(2)
+
+/* RCC_I3C2CFGR register fields */
+#define RCC_I3C2CFGR_I3C2RST BIT(0)
+#define RCC_I3C2CFGR_I3C2EN BIT(1)
+#define RCC_I3C2CFGR_I3C2LPEN BIT(2)
+
+/* RCC_I3C3CFGR register fields */
+#define RCC_I3C3CFGR_I3C3RST BIT(0)
+#define RCC_I3C3CFGR_I3C3EN BIT(1)
+#define RCC_I3C3CFGR_I3C3LPEN BIT(2)
+
+/* RCC_I3CxCFGR register fields */
+#define RCC_I3CxCFGR_I3CxRST BIT(0)
+#define RCC_I3CxCFGR_I3CxEN BIT(1)
+#define RCC_I3CxCFGR_I3CxLPEN BIT(2)
+#define RCC_I3CxCFGR_I3CxAMEN BIT(3)
+
+/* RCC_MUXSELCFGR register fields */
+#define RCC_MUXSELCFGR_MUXSEL0_MASK GENMASK_32(2, 0)
+#define RCC_MUXSELCFGR_MUXSEL0_SHIFT 0
+#define RCC_MUXSELCFGR_MUXSEL1_MASK GENMASK_32(6, 4)
+#define RCC_MUXSELCFGR_MUXSEL1_SHIFT 4
+#define RCC_MUXSELCFGR_MUXSEL2_MASK GENMASK_32(10, 8)
+#define RCC_MUXSELCFGR_MUXSEL2_SHIFT 8
+#define RCC_MUXSELCFGR_MUXSEL3_MASK GENMASK_32(14, 12)
+#define RCC_MUXSELCFGR_MUXSEL3_SHIFT 12
+#define RCC_MUXSELCFGR_MUXSEL4_MASK GENMASK_32(18, 16)
+#define RCC_MUXSELCFGR_MUXSEL4_SHIFT 16
+#define RCC_MUXSELCFGR_MUXSEL5_MASK GENMASK_32(21, 20)
+#define RCC_MUXSELCFGR_MUXSEL5_SHIFT 20
+#define RCC_MUXSELCFGR_MUXSEL6_MASK GENMASK_32(25, 24)
+#define RCC_MUXSELCFGR_MUXSEL6_SHIFT 24
+#define RCC_MUXSELCFGR_MUXSEL7_MASK GENMASK_32(29, 28)
+#define RCC_MUXSELCFGR_MUXSEL7_SHIFT 28
+
+/* RCC_XBAR0CFGR register fields */
+#define RCC_XBAR0CFGR_XBAR0SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR0CFGR_XBAR0SEL_SHIFT 0
+#define RCC_XBAR0CFGR_XBAR0EN BIT(6)
+#define RCC_XBAR0CFGR_XBAR0STS BIT(7)
+
+/* RCC_XBAR1CFGR register fields */
+#define RCC_XBAR1CFGR_XBAR1SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR1CFGR_XBAR1SEL_SHIFT 0
+#define RCC_XBAR1CFGR_XBAR1EN BIT(6)
+#define RCC_XBAR1CFGR_XBAR1STS BIT(7)
+
+/* RCC_XBAR2CFGR register fields */
+#define RCC_XBAR2CFGR_XBAR2SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR2CFGR_XBAR2SEL_SHIFT 0
+#define RCC_XBAR2CFGR_XBAR2EN BIT(6)
+#define RCC_XBAR2CFGR_XBAR2STS BIT(7)
+
+/* RCC_XBAR3CFGR register fields */
+#define RCC_XBAR3CFGR_XBAR3SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR3CFGR_XBAR3SEL_SHIFT 0
+#define RCC_XBAR3CFGR_XBAR3EN BIT(6)
+#define RCC_XBAR3CFGR_XBAR3STS BIT(7)
+
+/* RCC_XBAR4CFGR register fields */
+#define RCC_XBAR4CFGR_XBAR4SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR4CFGR_XBAR4SEL_SHIFT 0
+#define RCC_XBAR4CFGR_XBAR4EN BIT(6)
+#define RCC_XBAR4CFGR_XBAR4STS BIT(7)
+
+/* RCC_XBAR5CFGR register fields */
+#define RCC_XBAR5CFGR_XBAR5SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR5CFGR_XBAR5SEL_SHIFT 0
+#define RCC_XBAR5CFGR_XBAR5EN BIT(6)
+#define RCC_XBAR5CFGR_XBAR5STS BIT(7)
+
+/* RCC_XBAR6CFGR register fields */
+#define RCC_XBAR6CFGR_XBAR6SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR6CFGR_XBAR6SEL_SHIFT 0
+#define RCC_XBAR6CFGR_XBAR6EN BIT(6)
+#define RCC_XBAR6CFGR_XBAR6STS BIT(7)
+
+/* RCC_XBAR7CFGR register fields */
+#define RCC_XBAR7CFGR_XBAR7SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR7CFGR_XBAR7SEL_SHIFT 0
+#define RCC_XBAR7CFGR_XBAR7EN BIT(6)
+#define RCC_XBAR7CFGR_XBAR7STS BIT(7)
+
+/* RCC_XBAR8CFGR register fields */
+#define RCC_XBAR8CFGR_XBAR8SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR8CFGR_XBAR8SEL_SHIFT 0
+#define RCC_XBAR8CFGR_XBAR8EN BIT(6)
+#define RCC_XBAR8CFGR_XBAR8STS BIT(7)
+
+/* RCC_XBAR9CFGR register fields */
+#define RCC_XBAR9CFGR_XBAR9SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR9CFGR_XBAR9SEL_SHIFT 0
+#define RCC_XBAR9CFGR_XBAR9EN BIT(6)
+#define RCC_XBAR9CFGR_XBAR9STS BIT(7)
+
+/* RCC_XBAR10CFGR register fields */
+#define RCC_XBAR10CFGR_XBAR10SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR10CFGR_XBAR10SEL_SHIFT 0
+#define RCC_XBAR10CFGR_XBAR10EN BIT(6)
+#define RCC_XBAR10CFGR_XBAR10STS BIT(7)
+
+/* RCC_XBAR11CFGR register fields */
+#define RCC_XBAR11CFGR_XBAR11SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR11CFGR_XBAR11SEL_SHIFT 0
+#define RCC_XBAR11CFGR_XBAR11EN BIT(6)
+#define RCC_XBAR11CFGR_XBAR11STS BIT(7)
+
+/* RCC_XBAR12CFGR register fields */
+#define RCC_XBAR12CFGR_XBAR12SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR12CFGR_XBAR12SEL_SHIFT 0
+#define RCC_XBAR12CFGR_XBAR12EN BIT(6)
+#define RCC_XBAR12CFGR_XBAR12STS BIT(7)
+
+/* RCC_XBAR13CFGR register fields */
+#define RCC_XBAR13CFGR_XBAR13SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR13CFGR_XBAR13SEL_SHIFT 0
+#define RCC_XBAR13CFGR_XBAR13EN BIT(6)
+#define RCC_XBAR13CFGR_XBAR13STS BIT(7)
+
+/* RCC_XBAR14CFGR register fields */
+#define RCC_XBAR14CFGR_XBAR14SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR14CFGR_XBAR14SEL_SHIFT 0
+#define RCC_XBAR14CFGR_XBAR14EN BIT(6)
+#define RCC_XBAR14CFGR_XBAR14STS BIT(7)
+
+/* RCC_XBAR15CFGR register fields */
+#define RCC_XBAR15CFGR_XBAR15SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR15CFGR_XBAR15SEL_SHIFT 0
+#define RCC_XBAR15CFGR_XBAR15EN BIT(6)
+#define RCC_XBAR15CFGR_XBAR15STS BIT(7)
+
+/* RCC_XBAR16CFGR register fields */
+#define RCC_XBAR16CFGR_XBAR16SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR16CFGR_XBAR16SEL_SHIFT 0
+#define RCC_XBAR16CFGR_XBAR16EN BIT(6)
+#define RCC_XBAR16CFGR_XBAR16STS BIT(7)
+
+/* RCC_XBAR17CFGR register fields */
+#define RCC_XBAR17CFGR_XBAR17SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR17CFGR_XBAR17SEL_SHIFT 0
+#define RCC_XBAR17CFGR_XBAR17EN BIT(6)
+#define RCC_XBAR17CFGR_XBAR17STS BIT(7)
+
+/* RCC_XBAR18CFGR register fields */
+#define RCC_XBAR18CFGR_XBAR18SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR18CFGR_XBAR18SEL_SHIFT 0
+#define RCC_XBAR18CFGR_XBAR18EN BIT(6)
+#define RCC_XBAR18CFGR_XBAR18STS BIT(7)
+
+/* RCC_XBAR19CFGR register fields */
+#define RCC_XBAR19CFGR_XBAR19SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR19CFGR_XBAR19SEL_SHIFT 0
+#define RCC_XBAR19CFGR_XBAR19EN BIT(6)
+#define RCC_XBAR19CFGR_XBAR19STS BIT(7)
+
+/* RCC_XBAR20CFGR register fields */
+#define RCC_XBAR20CFGR_XBAR20SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR20CFGR_XBAR20SEL_SHIFT 0
+#define RCC_XBAR20CFGR_XBAR20EN BIT(6)
+#define RCC_XBAR20CFGR_XBAR20STS BIT(7)
+
+/* RCC_XBAR21CFGR register fields */
+#define RCC_XBAR21CFGR_XBAR21SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR21CFGR_XBAR21SEL_SHIFT 0
+#define RCC_XBAR21CFGR_XBAR21EN BIT(6)
+#define RCC_XBAR21CFGR_XBAR21STS BIT(7)
+
+/* RCC_XBAR22CFGR register fields */
+#define RCC_XBAR22CFGR_XBAR22SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR22CFGR_XBAR22SEL_SHIFT 0
+#define RCC_XBAR22CFGR_XBAR22EN BIT(6)
+#define RCC_XBAR22CFGR_XBAR22STS BIT(7)
+
+/* RCC_XBAR23CFGR register fields */
+#define RCC_XBAR23CFGR_XBAR23SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR23CFGR_XBAR23SEL_SHIFT 0
+#define RCC_XBAR23CFGR_XBAR23EN BIT(6)
+#define RCC_XBAR23CFGR_XBAR23STS BIT(7)
+
+/* RCC_XBAR24CFGR register fields */
+#define RCC_XBAR24CFGR_XBAR24SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR24CFGR_XBAR24SEL_SHIFT 0
+#define RCC_XBAR24CFGR_XBAR24EN BIT(6)
+#define RCC_XBAR24CFGR_XBAR24STS BIT(7)
+
+/* RCC_XBAR25CFGR register fields */
+#define RCC_XBAR25CFGR_XBAR25SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR25CFGR_XBAR25SEL_SHIFT 0
+#define RCC_XBAR25CFGR_XBAR25EN BIT(6)
+#define RCC_XBAR25CFGR_XBAR25STS BIT(7)
+
+/* RCC_XBAR26CFGR register fields */
+#define RCC_XBAR26CFGR_XBAR26SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR26CFGR_XBAR26SEL_SHIFT 0
+#define RCC_XBAR26CFGR_XBAR26EN BIT(6)
+#define RCC_XBAR26CFGR_XBAR26STS BIT(7)
+
+/* RCC_XBAR27CFGR register fields */
+#define RCC_XBAR27CFGR_XBAR27SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR27CFGR_XBAR27SEL_SHIFT 0
+#define RCC_XBAR27CFGR_XBAR27EN BIT(6)
+#define RCC_XBAR27CFGR_XBAR27STS BIT(7)
+
+/* RCC_XBAR28CFGR register fields */
+#define RCC_XBAR28CFGR_XBAR28SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR28CFGR_XBAR28SEL_SHIFT 0
+#define RCC_XBAR28CFGR_XBAR28EN BIT(6)
+#define RCC_XBAR28CFGR_XBAR28STS BIT(7)
+
+/* RCC_XBAR29CFGR register fields */
+#define RCC_XBAR29CFGR_XBAR29SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR29CFGR_XBAR29SEL_SHIFT 0
+#define RCC_XBAR29CFGR_XBAR29EN BIT(6)
+#define RCC_XBAR29CFGR_XBAR29STS BIT(7)
+
+/* RCC_XBAR30CFGR register fields */
+#define RCC_XBAR30CFGR_XBAR30SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR30CFGR_XBAR30SEL_SHIFT 0
+#define RCC_XBAR30CFGR_XBAR30EN BIT(6)
+#define RCC_XBAR30CFGR_XBAR30STS BIT(7)
+
+/* RCC_XBAR31CFGR register fields */
+#define RCC_XBAR31CFGR_XBAR31SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR31CFGR_XBAR31SEL_SHIFT 0
+#define RCC_XBAR31CFGR_XBAR31EN BIT(6)
+#define RCC_XBAR31CFGR_XBAR31STS BIT(7)
+
+/* RCC_XBAR32CFGR register fields */
+#define RCC_XBAR32CFGR_XBAR32SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR32CFGR_XBAR32SEL_SHIFT 0
+#define RCC_XBAR32CFGR_XBAR32EN BIT(6)
+#define RCC_XBAR32CFGR_XBAR32STS BIT(7)
+
+/* RCC_XBAR33CFGR register fields */
+#define RCC_XBAR33CFGR_XBAR33SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR33CFGR_XBAR33SEL_SHIFT 0
+#define RCC_XBAR33CFGR_XBAR33EN BIT(6)
+#define RCC_XBAR33CFGR_XBAR33STS BIT(7)
+
+/* RCC_XBAR34CFGR register fields */
+#define RCC_XBAR34CFGR_XBAR34SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR34CFGR_XBAR34SEL_SHIFT 0
+#define RCC_XBAR34CFGR_XBAR34EN BIT(6)
+#define RCC_XBAR34CFGR_XBAR34STS BIT(7)
+
+/* RCC_XBAR35CFGR register fields */
+#define RCC_XBAR35CFGR_XBAR35SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR35CFGR_XBAR35SEL_SHIFT 0
+#define RCC_XBAR35CFGR_XBAR35EN BIT(6)
+#define RCC_XBAR35CFGR_XBAR35STS BIT(7)
+
+/* RCC_XBAR36CFGR register fields */
+#define RCC_XBAR36CFGR_XBAR36SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR36CFGR_XBAR36SEL_SHIFT 0
+#define RCC_XBAR36CFGR_XBAR36EN BIT(6)
+#define RCC_XBAR36CFGR_XBAR36STS BIT(7)
+
+/* RCC_XBAR37CFGR register fields */
+#define RCC_XBAR37CFGR_XBAR37SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR37CFGR_XBAR37SEL_SHIFT 0
+#define RCC_XBAR37CFGR_XBAR37EN BIT(6)
+#define RCC_XBAR37CFGR_XBAR37STS BIT(7)
+
+/* RCC_XBAR38CFGR register fields */
+#define RCC_XBAR38CFGR_XBAR38SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR38CFGR_XBAR38SEL_SHIFT 0
+#define RCC_XBAR38CFGR_XBAR38EN BIT(6)
+#define RCC_XBAR38CFGR_XBAR38STS BIT(7)
+
+/* RCC_XBAR39CFGR register fields */
+#define RCC_XBAR39CFGR_XBAR39SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR39CFGR_XBAR39SEL_SHIFT 0
+#define RCC_XBAR39CFGR_XBAR39EN BIT(6)
+#define RCC_XBAR39CFGR_XBAR39STS BIT(7)
+
+/* RCC_XBAR40CFGR register fields */
+#define RCC_XBAR40CFGR_XBAR40SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR40CFGR_XBAR40SEL_SHIFT 0
+#define RCC_XBAR40CFGR_XBAR40EN BIT(6)
+#define RCC_XBAR40CFGR_XBAR40STS BIT(7)
+
+/* RCC_XBAR41CFGR register fields */
+#define RCC_XBAR41CFGR_XBAR41SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR41CFGR_XBAR41SEL_SHIFT 0
+#define RCC_XBAR41CFGR_XBAR41EN BIT(6)
+#define RCC_XBAR41CFGR_XBAR41STS BIT(7)
+
+/* RCC_XBAR42CFGR register fields */
+#define RCC_XBAR42CFGR_XBAR42SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR42CFGR_XBAR42SEL_SHIFT 0
+#define RCC_XBAR42CFGR_XBAR42EN BIT(6)
+#define RCC_XBAR42CFGR_XBAR42STS BIT(7)
+
+/* RCC_XBAR43CFGR register fields */
+#define RCC_XBAR43CFGR_XBAR43SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR43CFGR_XBAR43SEL_SHIFT 0
+#define RCC_XBAR43CFGR_XBAR43EN BIT(6)
+#define RCC_XBAR43CFGR_XBAR43STS BIT(7)
+
+/* RCC_XBAR44CFGR register fields */
+#define RCC_XBAR44CFGR_XBAR44SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR44CFGR_XBAR44SEL_SHIFT 0
+#define RCC_XBAR44CFGR_XBAR44EN BIT(6)
+#define RCC_XBAR44CFGR_XBAR44STS BIT(7)
+
+/* RCC_XBAR45CFGR register fields */
+#define RCC_XBAR45CFGR_XBAR45SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR45CFGR_XBAR45SEL_SHIFT 0
+#define RCC_XBAR45CFGR_XBAR45EN BIT(6)
+#define RCC_XBAR45CFGR_XBAR45STS BIT(7)
+
+/* RCC_XBAR46CFGR register fields */
+#define RCC_XBAR46CFGR_XBAR46SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR46CFGR_XBAR46SEL_SHIFT 0
+#define RCC_XBAR46CFGR_XBAR46EN BIT(6)
+#define RCC_XBAR46CFGR_XBAR46STS BIT(7)
+
+/* RCC_XBAR47CFGR register fields */
+#define RCC_XBAR47CFGR_XBAR47SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR47CFGR_XBAR47SEL_SHIFT 0
+#define RCC_XBAR47CFGR_XBAR47EN BIT(6)
+#define RCC_XBAR47CFGR_XBAR47STS BIT(7)
+
+/* RCC_XBAR48CFGR register fields */
+#define RCC_XBAR48CFGR_XBAR48SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR48CFGR_XBAR48SEL_SHIFT 0
+#define RCC_XBAR48CFGR_XBAR48EN BIT(6)
+#define RCC_XBAR48CFGR_XBAR48STS BIT(7)
+
+/* RCC_XBAR49CFGR register fields */
+#define RCC_XBAR49CFGR_XBAR49SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR49CFGR_XBAR49SEL_SHIFT 0
+#define RCC_XBAR49CFGR_XBAR49EN BIT(6)
+#define RCC_XBAR49CFGR_XBAR49STS BIT(7)
+
+/* RCC_XBAR50CFGR register fields */
+#define RCC_XBAR50CFGR_XBAR50SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR50CFGR_XBAR50SEL_SHIFT 0
+#define RCC_XBAR50CFGR_XBAR50EN BIT(6)
+#define RCC_XBAR50CFGR_XBAR50STS BIT(7)
+
+/* RCC_XBAR51CFGR register fields */
+#define RCC_XBAR51CFGR_XBAR51SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR51CFGR_XBAR51SEL_SHIFT 0
+#define RCC_XBAR51CFGR_XBAR51EN BIT(6)
+#define RCC_XBAR51CFGR_XBAR51STS BIT(7)
+
+/* RCC_XBAR52CFGR register fields */
+#define RCC_XBAR52CFGR_XBAR52SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR52CFGR_XBAR52SEL_SHIFT 0
+#define RCC_XBAR52CFGR_XBAR52EN BIT(6)
+#define RCC_XBAR52CFGR_XBAR52STS BIT(7)
+
+/* RCC_XBAR53CFGR register fields */
+#define RCC_XBAR53CFGR_XBAR53SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR53CFGR_XBAR53SEL_SHIFT 0
+#define RCC_XBAR53CFGR_XBAR53EN BIT(6)
+#define RCC_XBAR53CFGR_XBAR53STS BIT(7)
+
+/* RCC_XBAR54CFGR register fields */
+#define RCC_XBAR54CFGR_XBAR54SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR54CFGR_XBAR54SEL_SHIFT 0
+#define RCC_XBAR54CFGR_XBAR54EN BIT(6)
+#define RCC_XBAR54CFGR_XBAR54STS BIT(7)
+
+/* RCC_XBAR55CFGR register fields */
+#define RCC_XBAR55CFGR_XBAR55SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR55CFGR_XBAR55SEL_SHIFT 0
+#define RCC_XBAR55CFGR_XBAR55EN BIT(6)
+#define RCC_XBAR55CFGR_XBAR55STS BIT(7)
+
+/* RCC_XBAR56CFGR register fields */
+#define RCC_XBAR56CFGR_XBAR56SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR56CFGR_XBAR56SEL_SHIFT 0
+#define RCC_XBAR56CFGR_XBAR56EN BIT(6)
+#define RCC_XBAR56CFGR_XBAR56STS BIT(7)
+
+/* RCC_XBAR57CFGR register fields */
+#define RCC_XBAR57CFGR_XBAR57SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR57CFGR_XBAR57SEL_SHIFT 0
+#define RCC_XBAR57CFGR_XBAR57EN BIT(6)
+#define RCC_XBAR57CFGR_XBAR57STS BIT(7)
+
+/* RCC_XBAR58CFGR register fields */
+#define RCC_XBAR58CFGR_XBAR58SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR58CFGR_XBAR58SEL_SHIFT 0
+#define RCC_XBAR58CFGR_XBAR58EN BIT(6)
+#define RCC_XBAR58CFGR_XBAR58STS BIT(7)
+
+/* RCC_XBAR59CFGR register fields */
+#define RCC_XBAR59CFGR_XBAR59SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR59CFGR_XBAR59SEL_SHIFT 0
+#define RCC_XBAR59CFGR_XBAR59EN BIT(6)
+#define RCC_XBAR59CFGR_XBAR59STS BIT(7)
+
+/* RCC_XBAR60CFGR register fields */
+#define RCC_XBAR60CFGR_XBAR60SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR60CFGR_XBAR60SEL_SHIFT 0
+#define RCC_XBAR60CFGR_XBAR60EN BIT(6)
+#define RCC_XBAR60CFGR_XBAR60STS BIT(7)
+
+/* RCC_XBAR61CFGR register fields */
+#define RCC_XBAR61CFGR_XBAR61SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR61CFGR_XBAR61SEL_SHIFT 0
+#define RCC_XBAR61CFGR_XBAR61EN BIT(6)
+#define RCC_XBAR61CFGR_XBAR61STS BIT(7)
+
+/* RCC_XBAR62CFGR register fields */
+#define RCC_XBAR62CFGR_XBAR62SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR62CFGR_XBAR62SEL_SHIFT 0
+#define RCC_XBAR62CFGR_XBAR62EN BIT(6)
+#define RCC_XBAR62CFGR_XBAR62STS BIT(7)
+
+/* RCC_XBAR63CFGR register fields */
+#define RCC_XBAR63CFGR_XBAR63SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR63CFGR_XBAR63SEL_SHIFT 0
+#define RCC_XBAR63CFGR_XBAR63EN BIT(6)
+#define RCC_XBAR63CFGR_XBAR63STS BIT(7)
+
+/* RCC_XBARxCFGR register fields */
+#define RCC_XBARxCFGR_XBARxSEL_MASK GENMASK_32(3, 0)
+#define RCC_XBARxCFGR_XBARxSEL_SHIFT 0
+#define RCC_XBARxCFGR_XBARxEN BIT(6)
+#define RCC_XBARxCFGR_XBARxSTS BIT(7)
+
+/* RCC_PREDIV0CFGR register fields */
+#define RCC_PREDIV0CFGR_PREDIV0_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV0CFGR_PREDIV0_SHIFT 0
+
+/* RCC_PREDIV1CFGR register fields */
+#define RCC_PREDIV1CFGR_PREDIV1_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV1CFGR_PREDIV1_SHIFT 0
+
+/* RCC_PREDIV2CFGR register fields */
+#define RCC_PREDIV2CFGR_PREDIV2_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV2CFGR_PREDIV2_SHIFT 0
+
+/* RCC_PREDIV3CFGR register fields */
+#define RCC_PREDIV3CFGR_PREDIV3_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV3CFGR_PREDIV3_SHIFT 0
+
+/* RCC_PREDIV4CFGR register fields */
+#define RCC_PREDIV4CFGR_PREDIV4_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV4CFGR_PREDIV4_SHIFT 0
+
+/* RCC_PREDIV5CFGR register fields */
+#define RCC_PREDIV5CFGR_PREDIV5_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV5CFGR_PREDIV5_SHIFT 0
+
+/* RCC_PREDIV6CFGR register fields */
+#define RCC_PREDIV6CFGR_PREDIV6_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV6CFGR_PREDIV6_SHIFT 0
+
+/* RCC_PREDIV7CFGR register fields */
+#define RCC_PREDIV7CFGR_PREDIV7_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV7CFGR_PREDIV7_SHIFT 0
+
+/* RCC_PREDIV8CFGR register fields */
+#define RCC_PREDIV8CFGR_PREDIV8_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV8CFGR_PREDIV8_SHIFT 0
+
+/* RCC_PREDIV9CFGR register fields */
+#define RCC_PREDIV9CFGR_PREDIV9_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV9CFGR_PREDIV9_SHIFT 0
+
+/* RCC_PREDIV10CFGR register fields */
+#define RCC_PREDIV10CFGR_PREDIV10_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV10CFGR_PREDIV10_SHIFT 0
+
+/* RCC_PREDIV11CFGR register fields */
+#define RCC_PREDIV11CFGR_PREDIV11_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV11CFGR_PREDIV11_SHIFT 0
+
+/* RCC_PREDIV12CFGR register fields */
+#define RCC_PREDIV12CFGR_PREDIV12_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV12CFGR_PREDIV12_SHIFT 0
+
+/* RCC_PREDIV13CFGR register fields */
+#define RCC_PREDIV13CFGR_PREDIV13_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV13CFGR_PREDIV13_SHIFT 0
+
+/* RCC_PREDIV14CFGR register fields */
+#define RCC_PREDIV14CFGR_PREDIV14_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV14CFGR_PREDIV14_SHIFT 0
+
+/* RCC_PREDIV15CFGR register fields */
+#define RCC_PREDIV15CFGR_PREDIV15_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV15CFGR_PREDIV15_SHIFT 0
+
+/* RCC_PREDIV16CFGR register fields */
+#define RCC_PREDIV16CFGR_PREDIV16_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV16CFGR_PREDIV16_SHIFT 0
+
+/* RCC_PREDIV17CFGR register fields */
+#define RCC_PREDIV17CFGR_PREDIV17_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV17CFGR_PREDIV17_SHIFT 0
+
+/* RCC_PREDIV18CFGR register fields */
+#define RCC_PREDIV18CFGR_PREDIV18_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV18CFGR_PREDIV18_SHIFT 0
+
+/* RCC_PREDIV19CFGR register fields */
+#define RCC_PREDIV19CFGR_PREDIV19_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV19CFGR_PREDIV19_SHIFT 0
+
+/* RCC_PREDIV20CFGR register fields */
+#define RCC_PREDIV20CFGR_PREDIV20_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV20CFGR_PREDIV20_SHIFT 0
+
+/* RCC_PREDIV21CFGR register fields */
+#define RCC_PREDIV21CFGR_PREDIV21_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV21CFGR_PREDIV21_SHIFT 0
+
+/* RCC_PREDIV22CFGR register fields */
+#define RCC_PREDIV22CFGR_PREDIV22_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV22CFGR_PREDIV22_SHIFT 0
+
+/* RCC_PREDIV23CFGR register fields */
+#define RCC_PREDIV23CFGR_PREDIV23_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV23CFGR_PREDIV23_SHIFT 0
+
+/* RCC_PREDIV24CFGR register fields */
+#define RCC_PREDIV24CFGR_PREDIV24_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV24CFGR_PREDIV24_SHIFT 0
+
+/* RCC_PREDIV25CFGR register fields */
+#define RCC_PREDIV25CFGR_PREDIV25_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV25CFGR_PREDIV25_SHIFT 0
+
+/* RCC_PREDIV26CFGR register fields */
+#define RCC_PREDIV26CFGR_PREDIV26_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV26CFGR_PREDIV26_SHIFT 0
+
+/* RCC_PREDIV27CFGR register fields */
+#define RCC_PREDIV27CFGR_PREDIV27_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV27CFGR_PREDIV27_SHIFT 0
+
+/* RCC_PREDIV28CFGR register fields */
+#define RCC_PREDIV28CFGR_PREDIV28_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV28CFGR_PREDIV28_SHIFT 0
+
+/* RCC_PREDIV29CFGR register fields */
+#define RCC_PREDIV29CFGR_PREDIV29_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV29CFGR_PREDIV29_SHIFT 0
+
+/* RCC_PREDIV30CFGR register fields */
+#define RCC_PREDIV30CFGR_PREDIV30_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV30CFGR_PREDIV30_SHIFT 0
+
+/* RCC_PREDIV31CFGR register fields */
+#define RCC_PREDIV31CFGR_PREDIV31_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV31CFGR_PREDIV31_SHIFT 0
+
+/* RCC_PREDIV32CFGR register fields */
+#define RCC_PREDIV32CFGR_PREDIV32_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV32CFGR_PREDIV32_SHIFT 0
+
+/* RCC_PREDIV33CFGR register fields */
+#define RCC_PREDIV33CFGR_PREDIV33_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV33CFGR_PREDIV33_SHIFT 0
+
+/* RCC_PREDIV34CFGR register fields */
+#define RCC_PREDIV34CFGR_PREDIV34_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV34CFGR_PREDIV34_SHIFT 0
+
+/* RCC_PREDIV35CFGR register fields */
+#define RCC_PREDIV35CFGR_PREDIV35_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV35CFGR_PREDIV35_SHIFT 0
+
+/* RCC_PREDIV36CFGR register fields */
+#define RCC_PREDIV36CFGR_PREDIV36_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV36CFGR_PREDIV36_SHIFT 0
+
+/* RCC_PREDIV37CFGR register fields */
+#define RCC_PREDIV37CFGR_PREDIV37_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV37CFGR_PREDIV37_SHIFT 0
+
+/* RCC_PREDIV38CFGR register fields */
+#define RCC_PREDIV38CFGR_PREDIV38_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV38CFGR_PREDIV38_SHIFT 0
+
+/* RCC_PREDIV39CFGR register fields */
+#define RCC_PREDIV39CFGR_PREDIV39_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV39CFGR_PREDIV39_SHIFT 0
+
+/* RCC_PREDIV40CFGR register fields */
+#define RCC_PREDIV40CFGR_PREDIV40_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV40CFGR_PREDIV40_SHIFT 0
+
+/* RCC_PREDIV41CFGR register fields */
+#define RCC_PREDIV41CFGR_PREDIV41_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV41CFGR_PREDIV41_SHIFT 0
+
+/* RCC_PREDIV42CFGR register fields */
+#define RCC_PREDIV42CFGR_PREDIV42_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV42CFGR_PREDIV42_SHIFT 0
+
+/* RCC_PREDIV43CFGR register fields */
+#define RCC_PREDIV43CFGR_PREDIV43_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV43CFGR_PREDIV43_SHIFT 0
+
+/* RCC_PREDIV44CFGR register fields */
+#define RCC_PREDIV44CFGR_PREDIV44_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV44CFGR_PREDIV44_SHIFT 0
+
+/* RCC_PREDIV45CFGR register fields */
+#define RCC_PREDIV45CFGR_PREDIV45_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV45CFGR_PREDIV45_SHIFT 0
+
+/* RCC_PREDIV46CFGR register fields */
+#define RCC_PREDIV46CFGR_PREDIV46_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV46CFGR_PREDIV46_SHIFT 0
+
+/* RCC_PREDIV47CFGR register fields */
+#define RCC_PREDIV47CFGR_PREDIV47_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV47CFGR_PREDIV47_SHIFT 0
+
+/* RCC_PREDIV48CFGR register fields */
+#define RCC_PREDIV48CFGR_PREDIV48_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV48CFGR_PREDIV48_SHIFT 0
+
+/* RCC_PREDIV49CFGR register fields */
+#define RCC_PREDIV49CFGR_PREDIV49_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV49CFGR_PREDIV49_SHIFT 0
+
+/* RCC_PREDIV50CFGR register fields */
+#define RCC_PREDIV50CFGR_PREDIV50_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV50CFGR_PREDIV50_SHIFT 0
+
+/* RCC_PREDIV51CFGR register fields */
+#define RCC_PREDIV51CFGR_PREDIV51_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV51CFGR_PREDIV51_SHIFT 0
+
+/* RCC_PREDIV52CFGR register fields */
+#define RCC_PREDIV52CFGR_PREDIV52_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV52CFGR_PREDIV52_SHIFT 0
+
+/* RCC_PREDIV53CFGR register fields */
+#define RCC_PREDIV53CFGR_PREDIV53_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV53CFGR_PREDIV53_SHIFT 0
+
+/* RCC_PREDIV54CFGR register fields */
+#define RCC_PREDIV54CFGR_PREDIV54_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV54CFGR_PREDIV54_SHIFT 0
+
+/* RCC_PREDIV55CFGR register fields */
+#define RCC_PREDIV55CFGR_PREDIV55_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV55CFGR_PREDIV55_SHIFT 0
+
+/* RCC_PREDIV56CFGR register fields */
+#define RCC_PREDIV56CFGR_PREDIV56_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV56CFGR_PREDIV56_SHIFT 0
+
+/* RCC_PREDIV57CFGR register fields */
+#define RCC_PREDIV57CFGR_PREDIV57_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV57CFGR_PREDIV57_SHIFT 0
+
+/* RCC_PREDIV58CFGR register fields */
+#define RCC_PREDIV58CFGR_PREDIV58_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV58CFGR_PREDIV58_SHIFT 0
+
+/* RCC_PREDIV59CFGR register fields */
+#define RCC_PREDIV59CFGR_PREDIV59_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV59CFGR_PREDIV59_SHIFT 0
+
+/* RCC_PREDIV60CFGR register fields */
+#define RCC_PREDIV60CFGR_PREDIV60_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV60CFGR_PREDIV60_SHIFT 0
+
+/* RCC_PREDIV61CFGR register fields */
+#define RCC_PREDIV61CFGR_PREDIV61_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV61CFGR_PREDIV61_SHIFT 0
+
+/* RCC_PREDIV62CFGR register fields */
+#define RCC_PREDIV62CFGR_PREDIV62_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV62CFGR_PREDIV62_SHIFT 0
+
+/* RCC_PREDIV63CFGR register fields */
+#define RCC_PREDIV63CFGR_PREDIV63_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV63CFGR_PREDIV63_SHIFT 0
+
+/* RCC_PREDIVxCFGR register fields */
+#define RCC_PREDIVxCFGR_PREDIVx_MASK GENMASK_32(9, 0)
+#define RCC_PREDIVxCFGR_PREDIVx_SHIFT 0
+
+/* RCC_FINDIV0CFGR register fields */
+#define RCC_FINDIV0CFGR_FINDIV0_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV0CFGR_FINDIV0_SHIFT 0
+#define RCC_FINDIV0CFGR_FINDIV0EN BIT(6)
+
+/* RCC_FINDIV1CFGR register fields */
+#define RCC_FINDIV1CFGR_FINDIV1_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV1CFGR_FINDIV1_SHIFT 0
+#define RCC_FINDIV1CFGR_FINDIV1EN BIT(6)
+
+/* RCC_FINDIV2CFGR register fields */
+#define RCC_FINDIV2CFGR_FINDIV2_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV2CFGR_FINDIV2_SHIFT 0
+#define RCC_FINDIV2CFGR_FINDIV2EN BIT(6)
+
+/* RCC_FINDIV3CFGR register fields */
+#define RCC_FINDIV3CFGR_FINDIV3_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV3CFGR_FINDIV3_SHIFT 0
+#define RCC_FINDIV3CFGR_FINDIV3EN BIT(6)
+
+/* RCC_FINDIV4CFGR register fields */
+#define RCC_FINDIV4CFGR_FINDIV4_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV4CFGR_FINDIV4_SHIFT 0
+#define RCC_FINDIV4CFGR_FINDIV4EN BIT(6)
+
+/* RCC_FINDIV5CFGR register fields */
+#define RCC_FINDIV5CFGR_FINDIV5_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV5CFGR_FINDIV5_SHIFT 0
+#define RCC_FINDIV5CFGR_FINDIV5EN BIT(6)
+
+/* RCC_FINDIV6CFGR register fields */
+#define RCC_FINDIV6CFGR_FINDIV6_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV6CFGR_FINDIV6_SHIFT 0
+#define RCC_FINDIV6CFGR_FINDIV6EN BIT(6)
+
+/* RCC_FINDIV7CFGR register fields */
+#define RCC_FINDIV7CFGR_FINDIV7_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV7CFGR_FINDIV7_SHIFT 0
+#define RCC_FINDIV7CFGR_FINDIV7EN BIT(6)
+
+/* RCC_FINDIV8CFGR register fields */
+#define RCC_FINDIV8CFGR_FINDIV8_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV8CFGR_FINDIV8_SHIFT 0
+#define RCC_FINDIV8CFGR_FINDIV8EN BIT(6)
+
+/* RCC_FINDIV9CFGR register fields */
+#define RCC_FINDIV9CFGR_FINDIV9_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV9CFGR_FINDIV9_SHIFT 0
+#define RCC_FINDIV9CFGR_FINDIV9EN BIT(6)
+
+/* RCC_FINDIV10CFGR register fields */
+#define RCC_FINDIV10CFGR_FINDIV10_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV10CFGR_FINDIV10_SHIFT 0
+#define RCC_FINDIV10CFGR_FINDIV10EN BIT(6)
+
+/* RCC_FINDIV11CFGR register fields */
+#define RCC_FINDIV11CFGR_FINDIV11_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV11CFGR_FINDIV11_SHIFT 0
+#define RCC_FINDIV11CFGR_FINDIV11EN BIT(6)
+
+/* RCC_FINDIV12CFGR register fields */
+#define RCC_FINDIV12CFGR_FINDIV12_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV12CFGR_FINDIV12_SHIFT 0
+#define RCC_FINDIV12CFGR_FINDIV12EN BIT(6)
+
+/* RCC_FINDIV13CFGR register fields */
+#define RCC_FINDIV13CFGR_FINDIV13_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV13CFGR_FINDIV13_SHIFT 0
+#define RCC_FINDIV13CFGR_FINDIV13EN BIT(6)
+
+/* RCC_FINDIV14CFGR register fields */
+#define RCC_FINDIV14CFGR_FINDIV14_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV14CFGR_FINDIV14_SHIFT 0
+#define RCC_FINDIV14CFGR_FINDIV14EN BIT(6)
+
+/* RCC_FINDIV15CFGR register fields */
+#define RCC_FINDIV15CFGR_FINDIV15_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV15CFGR_FINDIV15_SHIFT 0
+#define RCC_FINDIV15CFGR_FINDIV15EN BIT(6)
+
+/* RCC_FINDIV16CFGR register fields */
+#define RCC_FINDIV16CFGR_FINDIV16_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV16CFGR_FINDIV16_SHIFT 0
+#define RCC_FINDIV16CFGR_FINDIV16EN BIT(6)
+
+/* RCC_FINDIV17CFGR register fields */
+#define RCC_FINDIV17CFGR_FINDIV17_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV17CFGR_FINDIV17_SHIFT 0
+#define RCC_FINDIV17CFGR_FINDIV17EN BIT(6)
+
+/* RCC_FINDIV18CFGR register fields */
+#define RCC_FINDIV18CFGR_FINDIV18_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV18CFGR_FINDIV18_SHIFT 0
+#define RCC_FINDIV18CFGR_FINDIV18EN BIT(6)
+
+/* RCC_FINDIV19CFGR register fields */
+#define RCC_FINDIV19CFGR_FINDIV19_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV19CFGR_FINDIV19_SHIFT 0
+#define RCC_FINDIV19CFGR_FINDIV19EN BIT(6)
+
+/* RCC_FINDIV20CFGR register fields */
+#define RCC_FINDIV20CFGR_FINDIV20_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV20CFGR_FINDIV20_SHIFT 0
+#define RCC_FINDIV20CFGR_FINDIV20EN BIT(6)
+
+/* RCC_FINDIV21CFGR register fields */
+#define RCC_FINDIV21CFGR_FINDIV21_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV21CFGR_FINDIV21_SHIFT 0
+#define RCC_FINDIV21CFGR_FINDIV21EN BIT(6)
+
+/* RCC_FINDIV22CFGR register fields */
+#define RCC_FINDIV22CFGR_FINDIV22_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV22CFGR_FINDIV22_SHIFT 0
+#define RCC_FINDIV22CFGR_FINDIV22EN BIT(6)
+
+/* RCC_FINDIV23CFGR register fields */
+#define RCC_FINDIV23CFGR_FINDIV23_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV23CFGR_FINDIV23_SHIFT 0
+#define RCC_FINDIV23CFGR_FINDIV23EN BIT(6)
+
+/* RCC_FINDIV24CFGR register fields */
+#define RCC_FINDIV24CFGR_FINDIV24_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV24CFGR_FINDIV24_SHIFT 0
+#define RCC_FINDIV24CFGR_FINDIV24EN BIT(6)
+
+/* RCC_FINDIV25CFGR register fields */
+#define RCC_FINDIV25CFGR_FINDIV25_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV25CFGR_FINDIV25_SHIFT 0
+#define RCC_FINDIV25CFGR_FINDIV25EN BIT(6)
+
+/* RCC_FINDIV26CFGR register fields */
+#define RCC_FINDIV26CFGR_FINDIV26_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV26CFGR_FINDIV26_SHIFT 0
+#define RCC_FINDIV26CFGR_FINDIV26EN BIT(6)
+
+/* RCC_FINDIV27CFGR register fields */
+#define RCC_FINDIV27CFGR_FINDIV27_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV27CFGR_FINDIV27_SHIFT 0
+#define RCC_FINDIV27CFGR_FINDIV27EN BIT(6)
+
+/* RCC_FINDIV28CFGR register fields */
+#define RCC_FINDIV28CFGR_FINDIV28_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV28CFGR_FINDIV28_SHIFT 0
+#define RCC_FINDIV28CFGR_FINDIV28EN BIT(6)
+
+/* RCC_FINDIV29CFGR register fields */
+#define RCC_FINDIV29CFGR_FINDIV29_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV29CFGR_FINDIV29_SHIFT 0
+#define RCC_FINDIV29CFGR_FINDIV29EN BIT(6)
+
+/* RCC_FINDIV30CFGR register fields */
+#define RCC_FINDIV30CFGR_FINDIV30_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV30CFGR_FINDIV30_SHIFT 0
+#define RCC_FINDIV30CFGR_FINDIV30EN BIT(6)
+
+/* RCC_FINDIV31CFGR register fields */
+#define RCC_FINDIV31CFGR_FINDIV31_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV31CFGR_FINDIV31_SHIFT 0
+#define RCC_FINDIV31CFGR_FINDIV31EN BIT(6)
+
+/* RCC_FINDIV32CFGR register fields */
+#define RCC_FINDIV32CFGR_FINDIV32_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV32CFGR_FINDIV32_SHIFT 0
+#define RCC_FINDIV32CFGR_FINDIV32EN BIT(6)
+
+/* RCC_FINDIV33CFGR register fields */
+#define RCC_FINDIV33CFGR_FINDIV33_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV33CFGR_FINDIV33_SHIFT 0
+#define RCC_FINDIV33CFGR_FINDIV33EN BIT(6)
+
+/* RCC_FINDIV34CFGR register fields */
+#define RCC_FINDIV34CFGR_FINDIV34_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV34CFGR_FINDIV34_SHIFT 0
+#define RCC_FINDIV34CFGR_FINDIV34EN BIT(6)
+
+/* RCC_FINDIV35CFGR register fields */
+#define RCC_FINDIV35CFGR_FINDIV35_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV35CFGR_FINDIV35_SHIFT 0
+#define RCC_FINDIV35CFGR_FINDIV35EN BIT(6)
+
+/* RCC_FINDIV36CFGR register fields */
+#define RCC_FINDIV36CFGR_FINDIV36_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV36CFGR_FINDIV36_SHIFT 0
+#define RCC_FINDIV36CFGR_FINDIV36EN BIT(6)
+
+/* RCC_FINDIV37CFGR register fields */
+#define RCC_FINDIV37CFGR_FINDIV37_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV37CFGR_FINDIV37_SHIFT 0
+#define RCC_FINDIV37CFGR_FINDIV37EN BIT(6)
+
+/* RCC_FINDIV38CFGR register fields */
+#define RCC_FINDIV38CFGR_FINDIV38_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV38CFGR_FINDIV38_SHIFT 0
+#define RCC_FINDIV38CFGR_FINDIV38EN BIT(6)
+
+/* RCC_FINDIV39CFGR register fields */
+#define RCC_FINDIV39CFGR_FINDIV39_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV39CFGR_FINDIV39_SHIFT 0
+#define RCC_FINDIV39CFGR_FINDIV39EN BIT(6)
+
+/* RCC_FINDIV40CFGR register fields */
+#define RCC_FINDIV40CFGR_FINDIV40_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV40CFGR_FINDIV40_SHIFT 0
+#define RCC_FINDIV40CFGR_FINDIV40EN BIT(6)
+
+/* RCC_FINDIV41CFGR register fields */
+#define RCC_FINDIV41CFGR_FINDIV41_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV41CFGR_FINDIV41_SHIFT 0
+#define RCC_FINDIV41CFGR_FINDIV41EN BIT(6)
+
+/* RCC_FINDIV42CFGR register fields */
+#define RCC_FINDIV42CFGR_FINDIV42_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV42CFGR_FINDIV42_SHIFT 0
+#define RCC_FINDIV42CFGR_FINDIV42EN BIT(6)
+
+/* RCC_FINDIV43CFGR register fields */
+#define RCC_FINDIV43CFGR_FINDIV43_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV43CFGR_FINDIV43_SHIFT 0
+#define RCC_FINDIV43CFGR_FINDIV43EN BIT(6)
+
+/* RCC_FINDIV44CFGR register fields */
+#define RCC_FINDIV44CFGR_FINDIV44_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV44CFGR_FINDIV44_SHIFT 0
+#define RCC_FINDIV44CFGR_FINDIV44EN BIT(6)
+
+/* RCC_FINDIV45CFGR register fields */
+#define RCC_FINDIV45CFGR_FINDIV45_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV45CFGR_FINDIV45_SHIFT 0
+#define RCC_FINDIV45CFGR_FINDIV45EN BIT(6)
+
+/* RCC_FINDIV46CFGR register fields */
+#define RCC_FINDIV46CFGR_FINDIV46_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV46CFGR_FINDIV46_SHIFT 0
+#define RCC_FINDIV46CFGR_FINDIV46EN BIT(6)
+
+/* RCC_FINDIV47CFGR register fields */
+#define RCC_FINDIV47CFGR_FINDIV47_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV47CFGR_FINDIV47_SHIFT 0
+#define RCC_FINDIV47CFGR_FINDIV47EN BIT(6)
+
+/* RCC_FINDIV48CFGR register fields */
+#define RCC_FINDIV48CFGR_FINDIV48_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV48CFGR_FINDIV48_SHIFT 0
+#define RCC_FINDIV48CFGR_FINDIV48EN BIT(6)
+
+/* RCC_FINDIV49CFGR register fields */
+#define RCC_FINDIV49CFGR_FINDIV49_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV49CFGR_FINDIV49_SHIFT 0
+#define RCC_FINDIV49CFGR_FINDIV49EN BIT(6)
+
+/* RCC_FINDIV50CFGR register fields */
+#define RCC_FINDIV50CFGR_FINDIV50_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV50CFGR_FINDIV50_SHIFT 0
+#define RCC_FINDIV50CFGR_FINDIV50EN BIT(6)
+
+/* RCC_FINDIV51CFGR register fields */
+#define RCC_FINDIV51CFGR_FINDIV51_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV51CFGR_FINDIV51_SHIFT 0
+#define RCC_FINDIV51CFGR_FINDIV51EN BIT(6)
+
+/* RCC_FINDIV52CFGR register fields */
+#define RCC_FINDIV52CFGR_FINDIV52_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV52CFGR_FINDIV52_SHIFT 0
+#define RCC_FINDIV52CFGR_FINDIV52EN BIT(6)
+
+/* RCC_FINDIV53CFGR register fields */
+#define RCC_FINDIV53CFGR_FINDIV53_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV53CFGR_FINDIV53_SHIFT 0
+#define RCC_FINDIV53CFGR_FINDIV53EN BIT(6)
+
+/* RCC_FINDIV54CFGR register fields */
+#define RCC_FINDIV54CFGR_FINDIV54_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV54CFGR_FINDIV54_SHIFT 0
+#define RCC_FINDIV54CFGR_FINDIV54EN BIT(6)
+
+/* RCC_FINDIV55CFGR register fields */
+#define RCC_FINDIV55CFGR_FINDIV55_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV55CFGR_FINDIV55_SHIFT 0
+#define RCC_FINDIV55CFGR_FINDIV55EN BIT(6)
+
+/* RCC_FINDIV56CFGR register fields */
+#define RCC_FINDIV56CFGR_FINDIV56_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV56CFGR_FINDIV56_SHIFT 0
+#define RCC_FINDIV56CFGR_FINDIV56EN BIT(6)
+
+/* RCC_FINDIV57CFGR register fields */
+#define RCC_FINDIV57CFGR_FINDIV57_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV57CFGR_FINDIV57_SHIFT 0
+#define RCC_FINDIV57CFGR_FINDIV57EN BIT(6)
+
+/* RCC_FINDIV58CFGR register fields */
+#define RCC_FINDIV58CFGR_FINDIV58_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV58CFGR_FINDIV58_SHIFT 0
+#define RCC_FINDIV58CFGR_FINDIV58EN BIT(6)
+
+/* RCC_FINDIV59CFGR register fields */
+#define RCC_FINDIV59CFGR_FINDIV59_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV59CFGR_FINDIV59_SHIFT 0
+#define RCC_FINDIV59CFGR_FINDIV59EN BIT(6)
+
+/* RCC_FINDIV60CFGR register fields */
+#define RCC_FINDIV60CFGR_FINDIV60_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV60CFGR_FINDIV60_SHIFT 0
+#define RCC_FINDIV60CFGR_FINDIV60EN BIT(6)
+
+/* RCC_FINDIV61CFGR register fields */
+#define RCC_FINDIV61CFGR_FINDIV61_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV61CFGR_FINDIV61_SHIFT 0
+#define RCC_FINDIV61CFGR_FINDIV61EN BIT(6)
+
+/* RCC_FINDIV62CFGR register fields */
+#define RCC_FINDIV62CFGR_FINDIV62_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV62CFGR_FINDIV62_SHIFT 0
+#define RCC_FINDIV62CFGR_FINDIV62EN BIT(6)
+
+/* RCC_FINDIV63CFGR register fields */
+#define RCC_FINDIV63CFGR_FINDIV63_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV63CFGR_FINDIV63_SHIFT 0
+#define RCC_FINDIV63CFGR_FINDIV63EN BIT(6)
+
+/* RCC_FINDIVxCFGR register fields */
+#define RCC_FINDIVxCFGR_FINDIVx_MASK GENMASK_32(5, 0)
+#define RCC_FINDIVxCFGR_FINDIVx_SHIFT 0
+#define RCC_FINDIVxCFGR_FINDIVxEN BIT(6)
+
+/* RCC_FCALCOBS0CFGR register fields */
+#define RCC_FCALCOBS0CFGR_CKINTSEL_MASK GENMASK_32(7, 0)
+#define RCC_FCALCOBS0CFGR_CKINTSEL_SHIFT 0
+#define RCC_FCALCOBS0CFGR_CKEXTSEL_MASK GENMASK_32(10, 8)
+#define RCC_FCALCOBS0CFGR_CKEXTSEL_SHIFT 8
+#define RCC_FCALCOBS0CFGR_FCALCCKEXTSEL BIT(15)
+#define RCC_FCALCOBS0CFGR_CKOBSEXTSEL BIT(16)
+#define RCC_FCALCOBS0CFGR_FCALCCKINV BIT(17)
+#define RCC_FCALCOBS0CFGR_CKOBSINV BIT(18)
+#define RCC_FCALCOBS0CFGR_CKOBSDIV_MASK GENMASK_32(24, 22)
+#define RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT 22
+#define RCC_FCALCOBS0CFGR_FCALCCKEN BIT(25)
+#define RCC_FCALCOBS0CFGR_CKOBSEN BIT(26)
+
+/* RCC_FCALCOBS1CFGR register fields */
+#define RCC_FCALCOBS1CFGR_CKINTSEL_MASK GENMASK_32(7, 0)
+#define RCC_FCALCOBS1CFGR_CKINTSEL_SHIFT 0
+#define RCC_FCALCOBS1CFGR_CKEXTSEL_MASK GENMASK_32(10, 8)
+#define RCC_FCALCOBS1CFGR_CKEXTSEL_SHIFT 8
+#define RCC_FCALCOBS1CFGR_CKOBSEXTSEL BIT(16)
+#define RCC_FCALCOBS1CFGR_CKOBSINV BIT(18)
+#define RCC_FCALCOBS1CFGR_CKOBSDIV_MASK GENMASK_32(24, 22)
+#define RCC_FCALCOBS1CFGR_CKOBSDIV_SHIFT 22
+#define RCC_FCALCOBS1CFGR_CKOBSEN BIT(26)
+#define RCC_FCALCOBS1CFGR_FCALCRSTN BIT(27)
+
+/* RCC_FCALCREFCFGR register fields */
+#define RCC_FCALCREFCFGR_FCALCREFCKSEL_MASK GENMASK_32(2, 0)
+#define RCC_FCALCREFCFGR_FCALCREFCKSEL_SHIFT 0
+
+/* RCC_FCALCCR1 register fields */
+#define RCC_FCALCCR1_FCALCRUN BIT(0)
+
+/* RCC_FCALCCR2 register fields */
+#define RCC_FCALCCR2_FCALCMD_MASK GENMASK_32(4, 3)
+#define RCC_FCALCCR2_FCALCMD_SHIFT 3
+#define RCC_FCALCCR2_FCALCTWC_MASK GENMASK_32(14, 11)
+#define RCC_FCALCCR2_FCALCTWC_SHIFT 11
+#define RCC_FCALCCR2_FCALCTYP_MASK GENMASK_32(21, 17)
+#define RCC_FCALCCR2_FCALCTYP_SHIFT 17
+
+/* RCC_FCALCSR register fields */
+#define RCC_FCALCSR_FVAL_MASK GENMASK_32(16, 0)
+#define RCC_FCALCSR_FVAL_SHIFT 0
+#define RCC_FCALCSR_FCALCSTS BIT(19)
+
+/* RCC_PLL4CFGR1 register fields */
+#define RCC_PLL4CFGR1_SSMODRST BIT(0)
+#define RCC_PLL4CFGR1_PLLEN BIT(8)
+#define RCC_PLL4CFGR1_PLLRDY BIT(24)
+#define RCC_PLL4CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL4CFGR2 register fields */
+#define RCC_PLL4CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL4CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL4CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL4CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL4CFGR3 register fields */
+#define RCC_PLL4CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL4CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL4CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL4CFGR3_DACEN BIT(25)
+#define RCC_PLL4CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL4CFGR4 register fields */
+#define RCC_PLL4CFGR4_DSMEN BIT(8)
+#define RCC_PLL4CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL4CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL4CFGR5 register fields */
+#define RCC_PLL4CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL4CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL4CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL4CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL4CFGR6 register fields */
+#define RCC_PLL4CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL4CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL4CFGR7 register fields */
+#define RCC_PLL4CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL4CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLL5CFGR1 register fields */
+#define RCC_PLL5CFGR1_SSMODRST BIT(0)
+#define RCC_PLL5CFGR1_PLLEN BIT(8)
+#define RCC_PLL5CFGR1_PLLRDY BIT(24)
+#define RCC_PLL5CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL5CFGR2 register fields */
+#define RCC_PLL5CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL5CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL5CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL5CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL5CFGR3 register fields */
+#define RCC_PLL5CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL5CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL5CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL5CFGR3_DACEN BIT(25)
+#define RCC_PLL5CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL5CFGR4 register fields */
+#define RCC_PLL5CFGR4_DSMEN BIT(8)
+#define RCC_PLL5CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL5CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL5CFGR5 register fields */
+#define RCC_PLL5CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL5CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL5CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL5CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL5CFGR6 register fields */
+#define RCC_PLL5CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL5CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL5CFGR7 register fields */
+#define RCC_PLL5CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL5CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLL6CFGR1 register fields */
+#define RCC_PLL6CFGR1_SSMODRST BIT(0)
+#define RCC_PLL6CFGR1_PLLEN BIT(8)
+#define RCC_PLL6CFGR1_PLLRDY BIT(24)
+#define RCC_PLL6CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL6CFGR2 register fields */
+#define RCC_PLL6CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL6CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL6CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL6CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL6CFGR3 register fields */
+#define RCC_PLL6CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL6CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL6CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL6CFGR3_DACEN BIT(25)
+#define RCC_PLL6CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL6CFGR4 register fields */
+#define RCC_PLL6CFGR4_DSMEN BIT(8)
+#define RCC_PLL6CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL6CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL6CFGR5 register fields */
+#define RCC_PLL6CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL6CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL6CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL6CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL6CFGR6 register fields */
+#define RCC_PLL6CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL6CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL6CFGR7 register fields */
+#define RCC_PLL6CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL6CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLL7CFGR1 register fields */
+#define RCC_PLL7CFGR1_SSMODRST BIT(0)
+#define RCC_PLL7CFGR1_PLLEN BIT(8)
+#define RCC_PLL7CFGR1_PLLRDY BIT(24)
+#define RCC_PLL7CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL7CFGR2 register fields */
+#define RCC_PLL7CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL7CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL7CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL7CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL7CFGR3 register fields */
+#define RCC_PLL7CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL7CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL7CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL7CFGR3_DACEN BIT(25)
+#define RCC_PLL7CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL7CFGR4 register fields */
+#define RCC_PLL7CFGR4_DSMEN BIT(8)
+#define RCC_PLL7CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL7CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL7CFGR5 register fields */
+#define RCC_PLL7CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL7CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL7CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL7CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL7CFGR6 register fields */
+#define RCC_PLL7CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL7CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL7CFGR7 register fields */
+#define RCC_PLL7CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL7CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLL8CFGR1 register fields */
+#define RCC_PLL8CFGR1_SSMODRST BIT(0)
+#define RCC_PLL8CFGR1_PLLEN BIT(8)
+#define RCC_PLL8CFGR1_PLLRDY BIT(24)
+#define RCC_PLL8CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL8CFGR2 register fields */
+#define RCC_PLL8CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL8CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL8CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL8CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL8CFGR3 register fields */
+#define RCC_PLL8CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL8CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL8CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL8CFGR3_DACEN BIT(25)
+#define RCC_PLL8CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL8CFGR4 register fields */
+#define RCC_PLL8CFGR4_DSMEN BIT(8)
+#define RCC_PLL8CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL8CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL8CFGR5 register fields */
+#define RCC_PLL8CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL8CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL8CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL8CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL8CFGR6 register fields */
+#define RCC_PLL8CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL8CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL8CFGR7 register fields */
+#define RCC_PLL8CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL8CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLLxCFGR1 register fields */
+#define RCC_PLLxCFGR1_SSMODRST BIT(0)
+#define RCC_PLLxCFGR1_PLLEN BIT(8)
+#define RCC_PLLxCFGR1_PLLRDY BIT(24)
+#define RCC_PLLxCFGR1_CKREFST BIT(28)
+
+/* RCC_PLLxCFGR2 register fields */
+#define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLLxCFGR2_FREFDIV_SHIFT 0
+#define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLLxCFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLLxCFGR3 register fields */
+#define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLLxCFGR3_FRACIN_SHIFT 0
+#define RCC_PLLxCFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLLxCFGR3_DACEN BIT(25)
+#define RCC_PLLxCFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLLxCFGR4 register fields */
+#define RCC_PLLxCFGR4_DSMEN BIT(8)
+#define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLLxCFGR4_BYPASS BIT(10)
+
+/* RCC_PLLxCFGR5 register fields */
+#define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLLxCFGR5_DIVVAL_SHIFT 0
+#define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLLxCFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLLxCFGR6 register fields */
+#define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLLxCFGR7 register fields */
+#define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_VERR register fields */
+#define RCC_VERR_MINREV_MASK GENMASK_32(3, 0)
+#define RCC_VERR_MINREV_SHIFT 0
+#define RCC_VERR_MAJREV_MASK GENMASK_32(7, 4)
+#define RCC_VERR_MAJREV_SHIFT 4
+
+#endif /* STM32MP21_RCC_H */
diff --git a/include/drivers/st/stm32mp25_rcc.h b/include/drivers/st/stm32mp25_rcc.h
index d5d228c..752d3c3 100644
--- a/include/drivers/st/stm32mp25_rcc.h
+++ b/include/drivers/st/stm32mp25_rcc.h
@@ -2308,6 +2308,12 @@
#define RCC_C1BOOTRSTSCLRR_D1STBYRSTF BIT(22)
#define RCC_C1BOOTRSTSCLRR_D2STBYRSTF BIT(23)
+#define RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF (RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF)
+
/* RCC_C2BOOTRSTSSETR register fields */
#define RCC_C2BOOTRSTSSETR_PORRSTF BIT(0)
#define RCC_C2BOOTRSTSSETR_BORRSTF BIT(1)
diff --git a/include/drivers/st/stm32mp2_ddr_helpers.h b/include/drivers/st/stm32mp2_ddr_helpers.h
index 9329fff..d9bf7ae 100644
--- a/include/drivers/st/stm32mp2_ddr_helpers.h
+++ b/include/drivers/st/stm32mp2_ddr_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,7 +22,6 @@
void ddr_activate_controller(struct stm32mp_ddrctl *ctl, bool sr_entry);
void ddr_wait_lp3_mode(bool state);
int ddr_sr_exit_loop(void);
-uint32_t ddr_get_io_calibration_val(void);
int ddr_sr_entry(bool standby);
int ddr_sr_exit(void);
enum stm32mp2_ddr_sr_mode ddr_read_sr_mode(void);
diff --git a/include/drivers/st/stm32mp_ddr.h b/include/drivers/st/stm32mp_ddr.h
index 57b0668..970ff19 100644
--- a/include/drivers/st/stm32mp_ddr.h
+++ b/include/drivers/st/stm32mp_ddr.h
@@ -28,7 +28,7 @@
struct stm32mp_ddr_reg_desc {
uint16_t offset; /* Offset for base address */
uint8_t par_offset; /* Offset for parameter array */
-#if !STM32MP13 && !STM32MP15
+#ifdef STM32MP2X
bool qd; /* quasi-dynamic register if true */
#endif
};
diff --git a/include/dt-bindings/clock/st,stm32mp21-rcc.h b/include/dt-bindings/clock/st,stm32mp21-rcc.h
new file mode 100644
index 0000000..f23c536
--- /dev/null
+++ b/include/dt-bindings/clock/st,stm32mp21-rcc.h
@@ -0,0 +1,429 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
+ * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com>
+ */
+
+#ifndef _DT_BINDINGS_STM32MP21_CLKS_H_
+#define _DT_BINDINGS_STM32MP21_CLKS_H_
+
+/* INTERNAL/EXTERNAL OSCILLATORS */
+#define HSI_CK 0
+#define HSE_CK 1
+#define MSI_CK 2
+#define LSI_CK 3
+#define LSE_CK 4
+#define I2S_CK 5
+#define RTC_CK 6
+#define SPDIF_CK_SYMB 7
+
+/* PLL CLOCKS */
+#define PLL1_CK 8
+#define PLL2_CK 9
+#define PLL4_CK 10
+#define PLL5_CK 11
+#define PLL6_CK 12
+#define PLL7_CK 13
+#define PLL8_CK 14
+
+#define CK_CPU1 15
+
+/* APB DIV CLOCKS */
+#define CK_ICN_APB1 16
+#define CK_ICN_APB2 17
+#define CK_ICN_APB3 18
+#define CK_ICN_APB4 19
+#define CK_ICN_APB5 20
+#define CK_ICN_APBDBG 21
+
+/* GLOBAL TIMER */
+#define TIMG1_CK 22
+#define TIMG2_CK 23
+
+/* FLEXGEN CLOCKS */
+#define CK_ICN_HS_MCU 24
+#define CK_ICN_SDMMC 25
+#define CK_ICN_DDR 26
+#define CK_ICN_DISPLAY 27
+#define CK_ICN_HSL 28
+#define CK_ICN_NIC 29
+#define CK_ICN_VID 30
+#define CK_FLEXGEN_07 31
+#define CK_FLEXGEN_08 32
+#define CK_FLEXGEN_09 33
+#define CK_FLEXGEN_10 34
+#define CK_FLEXGEN_11 35
+#define CK_FLEXGEN_12 36
+#define CK_FLEXGEN_13 37
+#define CK_FLEXGEN_14 38
+#define CK_FLEXGEN_15 39
+#define CK_FLEXGEN_16 40
+#define CK_FLEXGEN_17 41
+#define CK_FLEXGEN_18 42
+#define CK_FLEXGEN_19 43
+#define CK_FLEXGEN_20 44
+#define CK_FLEXGEN_21 45
+#define CK_FLEXGEN_22 46
+#define CK_FLEXGEN_23 47
+#define CK_FLEXGEN_24 48
+#define CK_FLEXGEN_25 49
+#define CK_FLEXGEN_26 50
+#define CK_FLEXGEN_27 51
+#define CK_FLEXGEN_28 52
+#define CK_FLEXGEN_29 53
+#define CK_FLEXGEN_30 54
+#define CK_FLEXGEN_31 55
+#define CK_FLEXGEN_32 56
+#define CK_FLEXGEN_33 57
+#define CK_FLEXGEN_34 58
+#define CK_FLEXGEN_35 59
+#define CK_FLEXGEN_36 60
+#define CK_FLEXGEN_37 61
+#define CK_FLEXGEN_38 62
+#define CK_FLEXGEN_39 63
+#define CK_FLEXGEN_40 64
+#define CK_FLEXGEN_41 65
+#define CK_FLEXGEN_42 66
+#define CK_FLEXGEN_43 67
+#define CK_FLEXGEN_44 68
+#define CK_FLEXGEN_45 69
+#define CK_FLEXGEN_46 70
+#define CK_FLEXGEN_47 71
+#define CK_FLEXGEN_48 72
+#define CK_FLEXGEN_49 73
+#define CK_FLEXGEN_50 74
+#define CK_FLEXGEN_51 75
+#define CK_FLEXGEN_52 76
+#define CK_FLEXGEN_53 77
+#define CK_FLEXGEN_54 78
+#define CK_FLEXGEN_55 79
+#define CK_FLEXGEN_56 80
+#define CK_FLEXGEN_57 81
+#define CK_FLEXGEN_58 82
+#define CK_FLEXGEN_59 83
+#define CK_FLEXGEN_60 84
+#define CK_FLEXGEN_61 85
+#define CK_FLEXGEN_62 86
+#define CK_FLEXGEN_63 87
+
+/* LOW SPEED MCU CLOCK */
+#define CK_ICN_LS_MCU 88
+
+#define CK_BUS_STM 89
+#define CK_BUS_FMC 90
+#define CK_BUS_ETH1 91
+#define CK_BUS_ETH2 92
+#define CK_BUS_DDRPHYC 93
+#define CK_BUS_SYSCPU1 94
+#define CK_BUS_HPDMA1 95
+#define CK_BUS_HPDMA2 96
+#define CK_BUS_HPDMA3 97
+#define CK_BUS_ADC1 98
+#define CK_BUS_ADC2 99
+#define CK_BUS_IPCC1 100
+#define CK_BUS_DCMIPSSI 101
+#define CK_BUS_CRC 102
+#define CK_BUS_MDF1 103
+#define CK_BUS_BKPSRAM 104
+#define CK_BUS_HASH1 105
+#define CK_BUS_HASH2 106
+#define CK_BUS_RNG1 107
+#define CK_BUS_RNG2 108
+#define CK_BUS_CRYP1 109
+#define CK_BUS_CRYP2 110
+#define CK_BUS_SAES 111
+#define CK_BUS_PKA 112
+#define CK_BUS_GPIOA 113
+#define CK_BUS_GPIOB 114
+#define CK_BUS_GPIOC 115
+#define CK_BUS_GPIOD 116
+#define CK_BUS_GPIOE 117
+#define CK_BUS_GPIOF 118
+#define CK_BUS_GPIOG 119
+#define CK_BUS_GPIOH 120
+#define CK_BUS_GPIOI 121
+#define CK_BUS_GPIOZ 122
+#define CK_BUS_RTC 124
+#define CK_BUS_LPUART1 125
+#define CK_BUS_LPTIM3 126
+#define CK_BUS_LPTIM4 127
+#define CK_BUS_LPTIM5 128
+#define CK_BUS_TIM2 129
+#define CK_BUS_TIM3 130
+#define CK_BUS_TIM4 131
+#define CK_BUS_TIM5 132
+#define CK_BUS_TIM6 133
+#define CK_BUS_TIM7 134
+#define CK_BUS_TIM10 135
+#define CK_BUS_TIM11 136
+#define CK_BUS_TIM12 137
+#define CK_BUS_TIM13 138
+#define CK_BUS_TIM14 139
+#define CK_BUS_LPTIM1 140
+#define CK_BUS_LPTIM2 141
+#define CK_BUS_SPI2 142
+#define CK_BUS_SPI3 143
+#define CK_BUS_SPDIFRX 144
+#define CK_BUS_USART2 145
+#define CK_BUS_USART3 146
+#define CK_BUS_UART4 147
+#define CK_BUS_UART5 148
+#define CK_BUS_I2C1 149
+#define CK_BUS_I2C2 150
+#define CK_BUS_I2C3 151
+#define CK_BUS_I3C1 152
+#define CK_BUS_I3C2 153
+#define CK_BUS_I3C3 154
+#define CK_BUS_TIM1 155
+#define CK_BUS_TIM8 156
+#define CK_BUS_TIM15 157
+#define CK_BUS_TIM16 158
+#define CK_BUS_TIM17 159
+#define CK_BUS_SAI1 160
+#define CK_BUS_SAI2 161
+#define CK_BUS_SAI3 162
+#define CK_BUS_SAI4 163
+#define CK_BUS_USART1 164
+#define CK_BUS_USART6 165
+#define CK_BUS_UART7 166
+#define CK_BUS_FDCAN 167
+#define CK_BUS_SPI1 168
+#define CK_BUS_SPI4 169
+#define CK_BUS_SPI5 170
+#define CK_BUS_SPI6 171
+#define CK_BUS_BSEC 172
+#define CK_BUS_IWDG1 173
+#define CK_BUS_IWDG2 174
+#define CK_BUS_IWDG3 175
+#define CK_BUS_IWDG4 176
+#define CK_BUS_WWDG1 177
+#define CK_BUS_VREF 178
+#define CK_BUS_DTS 179
+#define CK_BUS_SERC 180
+#define CK_BUS_HDP 181
+#define CK_BUS_DDRPERFM 182
+#define CK_BUS_OTG 183
+#define CK_BUS_LTDC 184
+#define CK_BUS_CSI 185
+#define CK_BUS_DCMIPP 186
+#define CK_BUS_DDRC 187
+#define CK_BUS_DDRCFG 188
+#define CK_BUS_STGEN 189
+#define CK_SYSDBG 190
+#define CK_KER_TIM2 191
+#define CK_KER_TIM3 192
+#define CK_KER_TIM4 193
+#define CK_KER_TIM5 194
+#define CK_KER_TIM6 195
+#define CK_KER_TIM7 196
+#define CK_KER_TIM10 197
+#define CK_KER_TIM11 198
+#define CK_KER_TIM12 199
+#define CK_KER_TIM13 200
+#define CK_KER_TIM14 201
+#define CK_KER_TIM1 202
+#define CK_KER_TIM8 203
+#define CK_KER_TIM15 204
+#define CK_KER_TIM16 205
+#define CK_KER_TIM17 206
+#define CK_BUS_SYSRAM 207
+#define CK_BUS_RETRAM 208
+#define CK_BUS_OSPI1 209
+#define CK_BUS_OTFD1 210
+#define CK_BUS_SRAM1 211
+#define CK_BUS_SDMMC1 212
+#define CK_BUS_SDMMC2 213
+#define CK_BUS_SDMMC3 214
+#define CK_BUS_DDR 215
+#define CK_BUS_RISAF4 216
+#define CK_BUS_USBHOHCI 217
+#define CK_BUS_USBHEHCI 218
+#define CK_KER_LPTIM1 219
+#define CK_KER_LPTIM2 220
+#define CK_KER_USART2 221
+#define CK_KER_UART4 222
+#define CK_KER_USART3 223
+#define CK_KER_UART5 224
+#define CK_KER_SPI2 225
+#define CK_KER_SPI3 226
+#define CK_KER_SPDIFRX 227
+#define CK_KER_I2C1 228
+#define CK_KER_I2C2 229
+#define CK_KER_I3C1 230
+#define CK_KER_I3C2 231
+#define CK_KER_I2C3 232
+#define CK_KER_I3C3 233
+#define CK_KER_SPI1 234
+#define CK_KER_SPI4 235
+#define CK_KER_SPI5 236
+#define CK_KER_SPI6 237
+#define CK_KER_USART1 238
+#define CK_KER_USART6 239
+#define CK_KER_UART7 240
+#define CK_KER_MDF1 241
+#define CK_KER_SAI1 242
+#define CK_KER_SAI2 243
+#define CK_KER_SAI3 244
+#define CK_KER_SAI4 245
+#define CK_KER_FDCAN 246
+#define CK_KER_CSI 247
+#define CK_KER_CSITXESC 248
+#define CK_KER_CSIPHY 249
+#define CK_KER_STGEN 250
+#define CK_KER_USB2PHY2EN 251
+#define CK_KER_LPUART1 252
+#define CK_KER_LPTIM3 253
+#define CK_KER_LPTIM4 254
+#define CK_KER_LPTIM5 255
+#define CK_KER_TSDBG 256
+#define CK_KER_TPIU 257
+#define CK_BUS_ETR 258
+#define CK_BUS_SYSATB 259
+#define CK_KER_ADC1 260
+#define CK_KER_ADC2 261
+#define CK_KER_OSPI1 262
+#define CK_KER_FMC 263
+#define CK_KER_SDMMC1 264
+#define CK_KER_SDMMC2 265
+#define CK_KER_SDMMC3 266
+#define CK_KER_ETH1 267
+#define CK_KER_ETH2 268
+#define CK_KER_ETH1PTP 269
+#define CK_KER_ETH2PTP 270
+#define CK_KER_USB2PHY1 271
+#define CK_KER_USB2PHY2 272
+#define CK_MCO1 273
+#define CK_MCO2 274
+#define CK_KER_DTS 275
+#define CK_ETH1_RX 276
+#define CK_ETH1_TX 277
+#define CK_ETH1_MAC 278
+#define CK_ETH2_RX 279
+#define CK_ETH2_TX 280
+#define CK_ETH2_MAC 281
+#define CK_ETH1_STP 282
+#define CK_ETH2_STP 283
+#define CK_KER_LTDC 284
+#define HSE_DIV2_CK 285
+#define CK_DBGMCU 286
+#define CK_DAP 287
+#define CK_KER_ETR 288
+#define CK_KER_STM 289
+
+#define STM32MP21_LAST_CLK 290
+
+#define CK_SCMI_ICN_HS_MCU 0
+#define CK_SCMI_ICN_SDMMC 1
+#define CK_SCMI_ICN_DDR 2
+#define CK_SCMI_ICN_DISPLAY 3
+#define CK_SCMI_ICN_HSL 4
+#define CK_SCMI_ICN_NIC 5
+#define CK_SCMI_ICN_VID 6
+#define CK_SCMI_FLEXGEN_07 7
+#define CK_SCMI_FLEXGEN_08 8
+#define CK_SCMI_FLEXGEN_09 9
+#define CK_SCMI_FLEXGEN_10 10
+#define CK_SCMI_FLEXGEN_11 11
+#define CK_SCMI_FLEXGEN_12 12
+#define CK_SCMI_FLEXGEN_13 13
+#define CK_SCMI_FLEXGEN_14 14
+#define CK_SCMI_FLEXGEN_15 15
+#define CK_SCMI_FLEXGEN_16 16
+#define CK_SCMI_FLEXGEN_17 17
+#define CK_SCMI_FLEXGEN_18 18
+#define CK_SCMI_FLEXGEN_19 19
+#define CK_SCMI_FLEXGEN_20 20
+#define CK_SCMI_FLEXGEN_21 21
+#define CK_SCMI_FLEXGEN_22 22
+#define CK_SCMI_FLEXGEN_23 23
+#define CK_SCMI_FLEXGEN_24 24
+#define CK_SCMI_FLEXGEN_25 25
+#define CK_SCMI_FLEXGEN_26 26
+#define CK_SCMI_FLEXGEN_27 27
+#define CK_SCMI_FLEXGEN_28 28
+#define CK_SCMI_FLEXGEN_29 29
+#define CK_SCMI_FLEXGEN_30 30
+#define CK_SCMI_FLEXGEN_31 31
+#define CK_SCMI_FLEXGEN_32 32
+#define CK_SCMI_FLEXGEN_33 33
+#define CK_SCMI_FLEXGEN_34 34
+#define CK_SCMI_FLEXGEN_35 35
+#define CK_SCMI_FLEXGEN_36 36
+#define CK_SCMI_FLEXGEN_37 37
+#define CK_SCMI_FLEXGEN_38 38
+#define CK_SCMI_FLEXGEN_39 39
+#define CK_SCMI_FLEXGEN_40 40
+#define CK_SCMI_FLEXGEN_41 41
+#define CK_SCMI_FLEXGEN_42 42
+#define CK_SCMI_FLEXGEN_43 43
+#define CK_SCMI_FLEXGEN_44 44
+#define CK_SCMI_FLEXGEN_45 45
+#define CK_SCMI_FLEXGEN_46 46
+#define CK_SCMI_FLEXGEN_47 47
+#define CK_SCMI_FLEXGEN_48 48
+#define CK_SCMI_FLEXGEN_49 49
+#define CK_SCMI_FLEXGEN_50 50
+#define CK_SCMI_FLEXGEN_51 51
+#define CK_SCMI_FLEXGEN_52 52
+#define CK_SCMI_FLEXGEN_53 53
+#define CK_SCMI_FLEXGEN_54 54
+#define CK_SCMI_FLEXGEN_55 55
+#define CK_SCMI_FLEXGEN_56 56
+#define CK_SCMI_FLEXGEN_57 57
+#define CK_SCMI_FLEXGEN_58 58
+#define CK_SCMI_FLEXGEN_59 59
+#define CK_SCMI_FLEXGEN_60 60
+#define CK_SCMI_FLEXGEN_61 61
+#define CK_SCMI_FLEXGEN_62 62
+#define CK_SCMI_FLEXGEN_63 63
+#define CK_SCMI_ICN_LS_MCU 64
+#define CK_SCMI_HSE 65
+#define CK_SCMI_LSE 66
+#define CK_SCMI_HSI 67
+#define CK_SCMI_LSI 68
+#define CK_SCMI_MSI 69
+#define CK_SCMI_HSE_DIV2 70
+#define CK_SCMI_CPU1 71
+#define CK_SCMI_SYSCPU1 72
+#define CK_SCMI_PLL2 73
+#define CK_SCMI_RTC 74
+#define CK_SCMI_RTCCK 75
+#define CK_SCMI_ICN_APB1 76
+#define CK_SCMI_ICN_APB2 77
+#define CK_SCMI_ICN_APB3 78
+#define CK_SCMI_ICN_APB4 79
+#define CK_SCMI_ICN_APB5 80
+#define CK_SCMI_ICN_APBDBG 81
+#define CK_SCMI_TIMG1 82
+#define CK_SCMI_TIMG2 83
+#define CK_SCMI_BKPSRAM 84
+#define CK_SCMI_BSEC 85
+#define CK_SCMI_BUS_ETR 86
+#define CK_SCMI_FMC 87
+#define CK_SCMI_GPIOA 88
+#define CK_SCMI_GPIOB 89
+#define CK_SCMI_GPIOC 90
+#define CK_SCMI_GPIOD 91
+#define CK_SCMI_GPIOE 92
+#define CK_SCMI_GPIOF 93
+#define CK_SCMI_GPIOG 94
+#define CK_SCMI_GPIOH 95
+#define CK_SCMI_GPIOI 96
+#define CK_SCMI_GPIOZ 97
+#define CK_SCMI_HPDMA1 98
+#define CK_SCMI_HPDMA2 99
+#define CK_SCMI_HPDMA3 100
+#define CK_SCMI_IPCC1 101
+#define CK_SCMI_RETRAM 102
+#define CK_SCMI_SRAM1 103
+#define CK_SCMI_SYSRAM 104
+#define CK_SCMI_OSPI1 105
+#define CK_SCMI_TPIU 106
+#define CK_SCMI_SYSDBG 107
+#define CK_SCMI_SYSATB 108
+#define CK_SCMI_TSDBG 109
+#define CK_SCMI_BUS_STM 110
+#define CK_SCMI_KER_STM 111
+#define CK_SCMI_KER_ETR 112
+
+#endif /* _DT_BINDINGS_STM32MP21_CLKS_H_ */
diff --git a/include/dt-bindings/clock/stm32mp21-clksrc.h b/include/dt-bindings/clock/stm32mp21-clksrc.h
new file mode 100644
index 0000000..560ca0a
--- /dev/null
+++ b/include/dt-bindings/clock/stm32mp21-clksrc.h
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (C) 2025, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_STM32MP21_CLKSRC_H_
+#define _DT_BINDINGS_CLOCK_STM32MP21_CLKSRC_H_
+
+#define CMD_DIV 0
+#define CMD_MUX 1
+#define CMD_CLK 2
+#define CMD_FLEXGEN 3
+
+#define CMD_ADDR_BIT 0x80000000
+
+#define CMD_SHIFT 26
+#define CMD_MASK 0xFC000000
+#define CMD_DATA_MASK 0x03FFFFFF
+
+#define DIV_ID_SHIFT 8
+#define DIV_ID_MASK 0x0000FF00
+
+#define DIV_DIVN_SHIFT 0
+#define DIV_DIVN_MASK 0x000000FF
+
+#define MUX_ID_SHIFT 4
+#define MUX_ID_MASK 0x00000FF0
+
+#define MUX_SEL_SHIFT 0
+#define MUX_SEL_MASK 0x0000000F
+
+/* CLK define */
+#define CLK_ON_MASK BIT(21)
+#define CLK_ON_SHIFT 21
+
+#define CLK_ID_MASK GENMASK_32(20, 12)
+#define CLK_ID_SHIFT 12
+
+#define CLK_NO_DIV_MASK 0x0000080
+#define CLK_DIV_MASK GENMASK_32(10, 5)
+#define CLK_DIV_SHIFT 5
+
+#define CLK_NO_SEL_MASK 0x00000010
+#define CLK_SEL_MASK GENMASK_32(3, 0)
+#define CLK_SEL_SHIFT 0
+
+#define CLK_CFG(clk_id, sel, div, state) ((CMD_CLK << CMD_SHIFT) |\
+ ((state) << CLK_ON_SHIFT) |\
+ ((clk_id) << CLK_ID_SHIFT) |\
+ ((div) << CLK_DIV_SHIFT) |\
+ ((sel) << CLK_SEL_SHIFT))
+
+#define CLK_OFF 0
+#define CLK_ON 1
+#define CLK_NODIV 0x00000040
+#define CLK_NOMUX 0x00000010
+
+/* Flexgen define */
+#define FLEX_ID_SHIFT 20
+#define FLEX_SEL_SHIFT 16
+#define FLEX_PDIV_SHIFT 6
+#define FLEX_FDIV_SHIFT 0
+
+#define FLEX_ID_MASK GENMASK_32(25, 20)
+#define FLEX_SEL_MASK GENMASK_32(19, 16)
+#define FLEX_PDIV_MASK GENMASK_32(15, 6)
+#define FLEX_FDIV_MASK GENMASK_32(5, 0)
+
+#define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\
+ ((div_id) << DIV_ID_SHIFT |\
+ (div)))
+
+#define MUX_CFG(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\
+ ((mux_id) << MUX_ID_SHIFT |\
+ (sel)))
+
+#define CLK_ADDR_SHIFT 16
+#define CLK_ADDR_MASK 0x7FFF0000
+#define CLK_ADDR_VAL_MASK 0xFFFF
+
+#define DIV_LSMCU 0
+#define DIV_APB1 1
+#define DIV_APB2 2
+#define DIV_APB3 3
+#define DIV_APB4 4
+#define DIV_APB5 5
+#define DIV_APBDBG 6
+#define DIV_RTC 7
+#define DIV_NB 8
+
+#define MUX_MUXSEL0 0
+#define MUX_MUXSEL1 1
+#define MUX_MUXSEL2 2
+#define MUX_MUXSEL3 3
+#define MUX_MUXSEL4 4
+#define MUX_MUXSEL5 5
+#define MUX_MUXSEL6 6
+#define MUX_MUXSEL7 7
+#define MUX_XBARSEL 8
+#define MUX_RTC 9
+#define MUX_MCO1 10
+#define MUX_MCO2 11
+#define MUX_ADC1 12
+#define MUX_ADC2 13
+#define MUX_USB2PHY1 14
+#define MUX_USB2PHY2 15
+#define MUX_DTS 16
+#define MUX_CPU1 17
+#define MUX_NB 18
+
+#define MUXSEL_HSI 0
+#define MUXSEL_HSE 1
+#define MUXSEL_MSI 2
+
+/* KERNEL source clocks */
+#define MUX_RTC_DISABLED 0x0
+#define MUX_RTC_LSE 0x1
+#define MUX_RTC_LSI 0x2
+#define MUX_RTC_HSE 0x3
+
+#define MUX_MCO1_FLEX61 0x0
+#define MUX_MCO1_OBSER0 0x1
+
+#define MUX_MCO2_FLEX62 0x0
+#define MUX_MCO2_OBSER1 0x1
+
+#define MUX_ADC1_FLEX46 0x0
+#define MUX_ADC1_LSMCU 0x1
+
+#define MUX_ADC2_FLEX47 0x0
+#define MUX_ADC2_LSMCU 0x1
+#define MUX_ADC2_FLEX46 0x2
+
+#define MUX_USB2PHY1_FLEX57 0x0
+#define MUX_USB2PHY1_HSE 0x1
+
+#define MUX_USB2PHY2_FLEX58 0x0
+#define MUX_USB2PHY2_HSE 0x1
+
+#define MUX_DTS_HSI 0x0
+#define MUX_DTS_HSE 0x1
+#define MUX_DTS_MSI 0x2
+
+/* PLLs source clocks */
+#define PLL_SRC_HSI 0x0
+#define PLL_SRC_HSE 0x1
+#define PLL_SRC_MSI 0x2
+#define PLL_SRC_DISABLED 0x3
+
+/* XBAR source clocks */
+#define XBAR_SRC_PLL4 0x0
+#define XBAR_SRC_PLL5 0x1
+#define XBAR_SRC_PLL6 0x2
+#define XBAR_SRC_PLL7 0x3
+#define XBAR_SRC_PLL8 0x4
+#define XBAR_SRC_HSI 0x5
+#define XBAR_SRC_HSE 0x6
+#define XBAR_SRC_MSI 0x7
+#define XBAR_SRC_HSI_KER 0x8
+#define XBAR_SRC_HSE_KER 0x9
+#define XBAR_SRC_MSI_KER 0xA
+#define XBAR_SRC_SPDIF_SYMB 0xB
+#define XBAR_SRC_I2S 0xC
+#define XBAR_SRC_LSI 0xD
+#define XBAR_SRC_LSE 0xE
+
+/*
+ * Configure a XBAR channel with its clock source
+ * channel_nb: XBAR channel number from 0 to 63
+ * channel_src: one of the 15 previous XBAR source clocks defines
+ * channel_prediv: value of the PREDIV in channel RCC_PREDIVxCFGR register
+ * can be either 1, 2, 4 or 1024
+ * channel_findiv: value of the FINDIV in channel RCC_FINDIVxCFGR register
+ * from 1 to 64
+ */
+
+#define FLEXGEN_CFG(ch, sel, pdiv, fdiv) ((CMD_FLEXGEN << CMD_SHIFT) |\
+ ((ch) << FLEX_ID_SHIFT) |\
+ ((sel) << FLEX_SEL_SHIFT) |\
+ ((pdiv) << FLEX_PDIV_SHIFT) |\
+ ((fdiv) << FLEX_FDIV_SHIFT))
+
+/* Register addresses of MCO1 & MCO2 */
+#define MCO1 0x488
+#define MCO2 0x48C
+
+#define MCO_OFF 0
+#define MCO_ON 1
+#define MCO_STATUS_SHIFT 8
+
+#define MCO_CFG(addr, sel, status) (CMD_ADDR_BIT |\
+ ((addr) << CLK_ADDR_SHIFT) |\
+ ((status) << MCO_STATUS_SHIFT) |\
+ (sel))
+
+/* define for st,pll /csg */
+#define SSCG_MODE_CENTER_SPREAD 0
+#define SSCG_MODE_DOWN_SPREAD 1
+
+/* define for st,drive */
+#define LSEDRV_LOWEST 0
+#define LSEDRV_MEDIUM_LOW 2
+#define LSEDRV_MEDIUM_HIGH 1
+#define LSEDRV_HIGHEST 3
+
+#endif /* _DT_BINDINGS_CLOCK_STM32MP21_CLKSRC_H_ */
diff --git a/include/dt-bindings/reset/st,stm32mp21-rcc.h b/include/dt-bindings/reset/st,stm32mp21-rcc.h
new file mode 100644
index 0000000..377a170
--- /dev/null
+++ b/include/dt-bindings/reset/st,stm32mp21-rcc.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
+ * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com>
+ */
+
+#ifndef _DT_BINDINGS_STM32MP21_RESET_H_
+#define _DT_BINDINGS_STM32MP21_RESET_H_
+
+/* TF-A use a binding required by driver, not aligned with Linux*/
+
+#define SYS_R 8192
+#define C1_R 8224
+#define C2_R 8288
+#define C2_HOLDBOOT_R 8608
+#define C1_HOLDBOOT_R 8609
+#define VSW_R 8672
+#define C1MS_R 8840
+#define IWDG2_KER_R 9106
+#define IWDG4_KER_R 9234
+#define DDRCP_R 9888
+#define DDRCAPB_R 9920
+#define DDRPHYCAPB_R 9952
+#define DDRCFG_R 10016
+#define DDR_R 10048
+#define OSPI1_R 10400
+#define OSPI1DLL_R 10416
+#define FMC_R 10464
+#define DBG_R 10508
+#define GPIOA_R 10592
+#define GPIOB_R 10624
+#define GPIOC_R 10656
+#define GPIOD_R 10688
+#define GPIOE_R 10720
+#define GPIOF_R 10752
+#define GPIOG_R 10784
+#define GPIOH_R 10816
+#define GPIOI_R 10848
+#define GPIOZ_R 10944
+#define HPDMA1_R 10976
+#define HPDMA2_R 11008
+#define HPDMA3_R 11040
+#define IPCC1_R 11136
+#define SSMOD_R 11392
+#define TIM1_R 14336
+#define TIM2_R 14368
+#define TIM3_R 14400
+#define TIM4_R 14432
+#define TIM5_R 14464
+#define TIM6_R 14496
+#define TIM7_R 14528
+#define TIM8_R 14560
+#define TIM10_R 14592
+#define TIM11_R 14624
+#define TIM12_R 14656
+#define TIM13_R 14688
+#define TIM14_R 14720
+#define TIM15_R 14752
+#define TIM16_R 14784
+#define TIM17_R 14816
+#define LPTIM1_R 14880
+#define LPTIM2_R 14912
+#define LPTIM3_R 14944
+#define LPTIM4_R 14976
+#define LPTIM5_R 15008
+#define SPI1_R 15040
+#define SPI2_R 15072
+#define SPI3_R 15104
+#define SPI4_R 15136
+#define SPI5_R 15168
+#define SPI6_R 15200
+#define SPDIFRX_R 15296
+#define USART1_R 15328
+#define USART2_R 15360
+#define USART3_R 15392
+#define UART4_R 15424
+#define UART5_R 15456
+#define USART6_R 15488
+#define UART7_R 15520
+#define LPUART1_R 15616
+#define I2C1_R 15648
+#define I2C2_R 15680
+#define I2C3_R 15712
+#define SAI1_R 15904
+#define SAI2_R 15936
+#define SAI3_R 15968
+#define SAI4_R 16000
+#define MDF1_R 16064
+#define ADF1_R 16096
+#define FDCAN_R 16128
+#define HDP_R 16160
+#define ADC1_R 16192
+#define ADC2_R 16224
+#define ETH1_R 16256
+#define ETH2_R 16288
+#define USBH_R 16352
+#define USB2PHY1_R 16384
+#define OTG_R 16448
+#define USB2PHY2_R 16480
+#define SDMMC1_R 16768
+#define SDMMC1DLL_R 16784
+#define SDMMC2_R 16800
+#define SDMMC2DLL_R 16816
+#define SDMMC3_R 16832
+#define SDMMC3DLL_R 16848
+#define LTDC_R 16896
+#define CSI_R 17088
+#define DCMIPP_R 17120
+#define DCMIPSSI_R 17152
+#define RNG1_R 17280
+#define RNG2_R 17312
+#define PKA_R 17344
+#define SAES_R 17376
+#define HASH1_R 17408
+#define HASH2_R 17440
+#define CRYP1_R 17472
+#define CRYP2_R 17504
+#define WWDG1_R 17696
+#define VREF_R 17760
+#define DTS_R 17792
+#define CRC_R 17824
+#define SERC_R 17856
+#define I3C1_R 17984
+#define I3C2_R 18016
+#define I3C3_R 18048
+
+#define RST_SCMI_C1_R 0
+#define RST_SCMI_C2_R 1
+#define RST_SCMI_C1_HOLDBOOT_R 2
+#define RST_SCMI_C2_HOLDBOOT_R 3
+#define RST_SCMI_FMC 4
+#define RST_SCMI_OSPI1 5
+#define RST_SCMI_OSPI1DLL 6
+
+#endif /* _DT_BINDINGS_STM32MP21_RESET_H_ */
diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h
index a47a47e..ccd35f9 100644
--- a/include/lib/cpus/aarch64/cortex_a710.h
+++ b/include/lib/cpus/aarch64/cortex_a710.h
@@ -44,6 +44,11 @@
#define CORTEX_A710_CPUACTLR3_EL1 S3_0_C15_C1_2
/*******************************************************************************
+ * CPU Auxiliary Control register 4 specific definitions.
+ ******************************************************************************/
+#define CORTEX_A710_CPUACTLR4_EL1 S3_0_C15_C1_3
+
+/*******************************************************************************
* CPU Auxiliary Control register 5 specific definitions.
******************************************************************************/
#define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index 402e07f..331bfdb 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -152,14 +152,14 @@
* If the field equals 1, branch targets trained in one context cannot
* affect speculative execution in a different context.
*
- * If the field equals 2, it means that the system is also aware of
+ * If the field equals 2 or 3, it means that the system is also aware of
* SCXTNUM_ELx register contexts. We aren't using them in the TF, so we
* expect users of the registers to do the right thing.
*
* Only apply mitigations if the value of this field is 0.
*/
#if ENABLE_ASSERTIONS
- cmp \_reg, #3 /* Only values 0 to 2 are expected */
+ cmp \_reg, #4 /* Only values 0 to 3 are expected */
ASM_ASSERT(lo)
#endif
@@ -653,4 +653,15 @@
#endif
.endm
+/*
+ * Call this just before a return to indicate support for pabandon. Only
+ * necessary on an abandon call, but harmless on a powerdown call.
+ *
+ * PSCI wants us to tell it we handled a pabandon by returning 0. This is the
+ * only way support for it is indicated.
+ */
+.macro signal_pabandon_handled
+ mov_imm x0, PABANDON_ACK
+.endm
+
#endif /* CPU_MACROS_S */
diff --git a/include/lib/cpus/aarch64/dsu_def.h b/include/lib/cpus/aarch64/dsu_def.h
index 78b3e7f..089ea52 100644
--- a/include/lib/cpus/aarch64/dsu_def.h
+++ b/include/lib/cpus/aarch64/dsu_def.h
@@ -26,14 +26,32 @@
#define CLUSTERIDR_VAR_SHIFT U(4)
#define CLUSTERIDR_VAR_BITS U(4)
+#define CLUSTERREVIDR_EL1 S3_0_C15_C3_2
+
/********************************************************************
* DSU Cluster Auxiliary Control registers definitions
********************************************************************/
#define CLUSTERACTLR_EL1 S3_0_C15_C3_3
-#define CLUSTERPWRCTLR_EL1 S3_0_C15_C3_5
-#define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15)
-#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15)
+/* CLUSTERPWRCTLR_EL1 register definitions */
+#define CLUSTERPWRCTLR_EL1 S3_0_C15_C3_5
+#define CLUSTERPWRCTLR_FUNCRET_WIDTH U(3)
+#define CLUSTERPWRCTLR_FUNCRET_SHIFT U(0)
+#define CLUSTERPWRCTLR_FUNCRET_RESET U(0)
+#define CLUSTERPWRCTLR_CACHEPWR_WIDTH U(4)
+#define CLUSTERPWRCTLR_CACHEPWR_SHIFT U(4)
+#define CLUSTERPWRCTLR_CACHEPWR_RESET U(7)
+
+#define CLUSTERACTLR_EL1_ASSERT_CBUSY (ULL(1) << 8)
+#define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15)
+#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15)
+#define CLUSTERACTLR_EL1_IGNORE_INTERCONNECT_CBUSY (ULL(3) << 20)
+
+/* CLUSTERPWRDN_EL1 register definitions */
+#define CLUSTERPWRDN_PWRDN_WIDTH U(1)
+#define CLUSTERPWRDN_PWRDN_SHIFT U(0)
+#define CLUSTERPWRDN_MEMRET_WIDTH U(1)
+#define CLUSTERPWRDN_MEMRET_SHIFT U(1)
/********************************************************************
* Masks applied for DSU errata workarounds
diff --git a/include/lib/cpus/aarch64/dsu_macros.S b/include/lib/cpus/aarch64/dsu_macros.S
index 6c8cb69..fd23f66 100644
--- a/include/lib/cpus/aarch64/dsu_macros.S
+++ b/include/lib/cpus/aarch64/dsu_macros.S
@@ -94,4 +94,44 @@
orr x0, x0, #CLUSTERACTLR_EL1_DISABLE_SCLK_GATING
msr CLUSTERACTLR_EL1, x0
.endm
+
+/*
+ * Check if erratum is fixed via CLUSTERREVIDR_EL1 bit (\bitpos).
+ * If not fixed (bit is clear), set x0 = ERRATA_APPLIES (from x3).
+ * If fixed (bit is set), keep x0 = ERRATA_NOT_APPLIES.
+ */
+.macro check_revidr_bit bitpos:req
+ mrs x4, CLUSTERREVIDR_EL1
+ mov x1, #1
+ lsl x1, x1, #\bitpos
+ tst x1, x4
+ csel x0, x0, x3, NE
+.endm
+
+.macro check_errata_dsu_2900952_applies
+ mov x0, #ERRATA_NOT_APPLIES
+ mov x3, #ERRATA_APPLIES
+
+ /* Check if DSU revision is equal to r2p0 */
+ mrs x1, CLUSTERIDR_EL1
+
+ /* DSU variant and revision bitfields in CLUSTERIDR are adjacent */
+ ubfx x2, x1, #CLUSTERIDR_REV_SHIFT,\
+ #(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS)
+ cmp x2, #(0x2 << CLUSTERIDR_VAR_SHIFT)
+ b.ne 1f
+ check_revidr_bit 1
+1:
+.endm
+
+.macro errata_dsu_2900952_wa_apply
+
+ ldr x1, =((CLUSTERACTLR_EL1_IGNORE_INTERCONNECT_CBUSY | \
+ CLUSTERACTLR_EL1_ASSERT_CBUSY))
+
+ mrs x0, CLUSTERACTLR_EL1
+ orr x0, x0, x1
+ msr CLUSTERACTLR_EL1, x0
+.endm
+
#endif /* DSU_MACROS_S */
diff --git a/include/lib/cpus/cpu_ops.h b/include/lib/cpus/cpu_ops.h
index 5ba78cf..765cd59 100644
--- a/include/lib/cpus/cpu_ops.h
+++ b/include/lib/cpus/cpu_ops.h
@@ -21,6 +21,12 @@
/* The number of CPU operations allowed */
#define CPU_MAX_PWR_DWN_OPS 2
+/*
+ * value needs to be distinct from CPUPWRCTLR_EL1 likely values: its top bits
+ * are RES0 and its bottom bits will be written to power down. Pick the opposite
+ * with something that looks like "abandon" in the middle.
+ */
+#define PABANDON_ACK 0xffaba4d4aba4d400
/*
* Define the sizes of the fields in the cpu_ops structure. Word size is set per
@@ -104,7 +110,7 @@
void (*e_handler_func)(long es);
#endif /* __aarch64__ */
#if (defined(IMAGE_BL31) || defined(IMAGE_BL32)) && CPU_MAX_PWR_DWN_OPS
- void (*pwr_dwn_ops[CPU_MAX_PWR_DWN_OPS])(void);
+ u_register_t (*pwr_dwn_ops[CPU_MAX_PWR_DWN_OPS])();
#endif /* (defined(IMAGE_BL31) || defined(IMAGE_BL32)) && CPU_MAX_PWR_DWN_OPS */
void *errata_list_start;
void *errata_list_end;
diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h
index 235e2b9..bb755e0 100644
--- a/include/lib/cpus/errata.h
+++ b/include/lib/cpus/errata.h
@@ -93,8 +93,9 @@
* NOTE an erratum and CVE id could clash. However, both numbers are very large
* and the probablity is minuscule. Working around this makes code very
* complicated and extremely difficult to read so it is not considered. In the
- * unlikely event that this does happen, prepending the CVE id with a 0 should
- * resolve the conflict
+ * unlikely event that this does happen, the build will fail, and unless the
+ * framework is updated to account for this one of the IDs will need to be
+ * altered to prevent the conflict.
*/
#define NO_ISB 1
#define NO_ASSERT 0
diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h
index 72a8ea2..80f68f7f 100644
--- a/include/lib/el3_runtime/context_mgmt.h
+++ b/include/lib/el3_runtime/context_mgmt.h
@@ -23,22 +23,21 @@
******************************************************************************/
void cm_init(void);
void *cm_get_context_by_index(unsigned int cpu_idx,
- unsigned int security_state);
+ size_t security_state);
void cm_set_context_by_index(unsigned int cpu_idx,
void *context,
unsigned int security_state);
-void *cm_get_context(uint32_t security_state);
+void *cm_get_context(size_t security_state);
void cm_set_context(void *context, uint32_t security_state);
void cm_init_my_context(const struct entry_point_info *ep);
void cm_setup_context(cpu_context_t *ctx, const struct entry_point_info *ep);
-void cm_prepare_el3_exit(uint32_t security_state);
+void cm_prepare_el3_exit(size_t security_state);
void cm_prepare_el3_exit_ns(void);
#ifdef __aarch64__
#if IMAGE_BL31
void cm_manage_extensions_el3(unsigned int my_idx);
-void manage_extensions_nonsecure_per_world(void);
-void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx);
+void cm_manage_extensions_per_world(void);
#endif
#if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
@@ -90,7 +89,6 @@
void *cm_get_next_context(void);
void cm_set_next_context(void *context);
static inline void cm_manage_extensions_el3(unsigned int cpu_idx) {}
-static inline void manage_extensions_nonsecure_per_world(void) {}
#endif /* __aarch64__ */
#endif /* CONTEXT_MGMT_H */
diff --git a/include/lib/el3_runtime/cpu_data.h b/include/lib/el3_runtime/cpu_data.h
index 3dc156a..ba2f8d5 100644
--- a/include/lib/el3_runtime/cpu_data.h
+++ b/include/lib/el3_runtime/cpu_data.h
@@ -138,7 +138,7 @@
void *cpu_context[CPU_DATA_CONTEXT_NUM];
#endif /* __aarch64__ */
entry_point_info_t *warmboot_ep_info;
- uintptr_t cpu_ops_ptr;
+ struct cpu_ops *cpu_ops_ptr;
struct psci_cpu_data psci_svc_cpu_data;
#if ENABLE_PAUTH
uint64_t apiakey[2];
@@ -196,16 +196,19 @@
assert_cpu_data_pmf_ts0_offset_mismatch);
#endif
-struct cpu_data *_cpu_data_by_index(uint32_t cpu_index);
+static inline cpu_data_t *_cpu_data_by_index(unsigned int cpu_index)
+{
+ return &percpu_data[cpu_index];
+}
#ifdef __aarch64__
/* Return the cpu_data structure for the current CPU. */
-static inline struct cpu_data *_cpu_data(void)
+static inline cpu_data_t *_cpu_data(void)
{
return (cpu_data_t *)read_tpidr_el3();
}
#else
-struct cpu_data *_cpu_data(void);
+cpu_data_t *_cpu_data(void);
#endif
/*
@@ -214,7 +217,7 @@
* an access is not out-of-bounds. The function assumes security_state is
* valid.
*/
-static inline context_pas_t get_cpu_context_index(uint32_t security_state)
+static inline context_pas_t get_cpu_context_index(size_t security_state)
{
if (security_state == SECURE) {
return CPU_CONTEXT_SECURE;
diff --git a/include/lib/extensions/spe.h b/include/lib/extensions/spe.h
index 0a41e1e..b58e18c 100644
--- a/include/lib/extensions/spe.h
+++ b/include/lib/extensions/spe.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,14 +11,18 @@
#include <context.h>
#if ENABLE_SPE_FOR_NS
-void spe_enable(cpu_context_t *ctx);
-void spe_disable(cpu_context_t *ctx);
+void spe_enable_ns(cpu_context_t *ctx);
+void spe_disable_secure(cpu_context_t *ctx);
+void spe_disable_realm(cpu_context_t *ctx);
void spe_init_el2_unused(void);
#else
-static inline void spe_enable(cpu_context_t *ctx)
+static inline void spe_enable_ns(cpu_context_t *ctx)
{
}
-static inline void spe_disable(cpu_context_t *ctx)
+static inline void spe_disable_secure(cpu_context_t *ctx)
+{
+}
+static inline void spe_disable_realm(cpu_context_t *ctx)
{
}
static inline void spe_init_el2_unused(void)
diff --git a/include/lib/extensions/trbe.h b/include/lib/extensions/trbe.h
index 2c488e0..bd36f54 100644
--- a/include/lib/extensions/trbe.h
+++ b/include/lib/extensions/trbe.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,14 +10,22 @@
#include <context.h>
#if ENABLE_TRBE_FOR_NS
-void trbe_disable(cpu_context_t *ctx);
-void trbe_enable(cpu_context_t *ctx);
+void trbe_enable_ns(cpu_context_t *ctx);
+void trbe_disable_ns(cpu_context_t *ctx);
+void trbe_disable_secure(cpu_context_t *ctx);
+void trbe_disable_realm(cpu_context_t *ctx);
void trbe_init_el2_unused(void);
#else
-static inline void trbe_disable(cpu_context_t *ctx)
+static inline void trbe_enable_ns(cpu_context_t *ctx)
{
}
-static inline void trbe_enable(cpu_context_t *ctx)
+static inline void trbe_disable_ns(cpu_context_t *ctx)
+{
+}
+static inline void trbe_disable_secure(cpu_context_t *ctx)
+{
+}
+static inline void trbe_disable_realm(cpu_context_t *ctx)
{
}
static inline void trbe_init_el2_unused(void)
diff --git a/include/lib/libc/stdbool.h b/include/lib/libc/stdbool.h
index c2c9b22..30ced2a 100644
--- a/include/lib/libc/stdbool.h
+++ b/include/lib/libc/stdbool.h
@@ -9,8 +9,8 @@
#define bool _Bool
-#define true (0 < 1)
-#define false (0 > 1)
+#define true (0 == 0)
+#define false (0 == 1)
#define __bool_true_false_are_defined 1
diff --git a/include/lib/libc/string_private.h b/include/lib/libc/string_private.h
index da85fae..ab7647a 100644
--- a/include/lib/libc/string_private.h
+++ b/include/lib/libc/string_private.h
@@ -11,6 +11,7 @@
#include <stddef.h>
+void *memcpy(void *dst, const void *src, size_t len);
int memcmp(const void *s1, const void *s2, size_t len);
int strcmp(const char *s1, const char *s2);
int strncmp(const char *s1, const char *s2, size_t n);
diff --git a/include/lib/mmio_poll.h b/include/lib/mmio_poll.h
new file mode 100644
index 0000000..1b2aa0a
--- /dev/null
+++ b/include/lib/mmio_poll.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MMIO_POLL_H
+#define MMIO_POLL_H
+
+#include <errno.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+/**
+ * mmio_read_poll_timeout - Continuously check an address until a specific
+ * condition is satisfied or a timeout is reached.
+ * @op: The mmio_read_* operator to read the register
+ * @val: The variable where the read value is stored.
+ * @cond: The condition used to stop polling, which can be a macro using @val.
+ * @timeout_us: Timeout in microseconds.
+ * @args: Arguments to be passed to @op.
+ *
+ * Return: 0 if the condition @cond is evaluated to true within @timeout_us
+ * microseconds, or -ETIMEOUT in case of a timeout. In either case,
+ * the last read value will be stored in @val.
+ */
+#define mmio_read_poll_timeout(op, val, cond, timeout_us, args...)\
+({\
+ int _rv = -ETIMEDOUT; \
+ uint32_t _tout_us = (timeout_us); \
+ uint64_t _tout = timeout_init_us(_tout_us);\
+ do {\
+ (val) = (op)(args);\
+ if (cond) { \
+ _rv = 0;\
+ break;\
+ } \
+ } while (!timeout_elapsed(_tout));\
+ _rv;\
+})
+
+#define mmio_read_32_poll_timeout(addr, val, cond, timeout_us) \
+ mmio_read_poll_timeout(&mmio_read_32, val, cond, timeout_us, addr)
+
+#endif /* MMIO_POLL_H */
diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h
index 68e721a..b146d39 100644
--- a/include/lib/psci/psci.h
+++ b/include/lib/psci/psci.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -376,7 +376,6 @@
#if PSCI_OS_INIT_MODE
int psci_set_suspend_mode(unsigned int mode);
#endif
-void psci_power_down_wfi(void);
void psci_arch_setup(void);
#endif /*__ASSEMBLER__*/
diff --git a/include/lib/psci/psci_lib.h b/include/lib/psci/psci_lib.h
index 8c9296b..12efe17 100644
--- a/include/lib/psci/psci_lib.h
+++ b/include/lib/psci/psci_lib.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,7 +25,7 @@
int32_t (*svc_off)(u_register_t __unused unused);
void (*svc_suspend)(u_register_t max_off_pwrlvl);
void (*svc_on_finish)(u_register_t __unused unused);
- void (*svc_suspend_finish)(u_register_t max_off_pwrlvl);
+ void (*svc_suspend_finish)(u_register_t max_off_pwrlvl, bool abandon);
int32_t (*svc_migrate)(u_register_t from_cpu, u_register_t to_cpu);
int32_t (*svc_migrate_info)(u_register_t *resident_cpu);
void (*svc_system_off)(void);
@@ -98,6 +98,7 @@
void __dead2 psci_pwrdown_cpu_end_terminal(void);
void psci_pwrdown_cpu_end_wakeup(unsigned int power_level);
void psci_do_manage_extensions(void);
+unsigned int psci_num_cpus_running_on_safe(unsigned int this_core);
#endif /* __ASSEMBLER__ */
diff --git a/include/lib/spinlock.h b/include/lib/spinlock.h
index 055a911..56d9b51 100644
--- a/include/lib/spinlock.h
+++ b/include/lib/spinlock.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +9,7 @@
#ifndef __ASSEMBLER__
+#include <stdbool.h>
#include <stdint.h>
typedef struct spinlock {
@@ -25,6 +26,8 @@
void bit_lock(bitlock_t *lock, uint8_t mask);
void bit_unlock(bitlock_t *lock, uint8_t mask);
+bool spin_trylock(spinlock_t *lock);
+
#else
/* Spin lock definitions for use in assembly */
diff --git a/include/lib/transfer_list.h b/include/lib/transfer_list.h
deleted file mode 100644
index bdc6349..0000000
--- a/include/lib/transfer_list.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * Copyright (c) 2023-2024, Linaro Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __TRANSFER_LIST_H
-#define __TRANSFER_LIST_H
-
-#include <stdbool.h>
-#include <stdint.h>
-
-#include <common/ep_info.h>
-#include <lib/utils_def.h>
-
-#define TRANSFER_LIST_SIGNATURE U(0x4a0fb10b)
-#define TRANSFER_LIST_VERSION U(0x0001)
-
-/*
- * Init value of maximum alignment required by any TE data in the TL
- * specified as a power of two
- */
-#define TRANSFER_LIST_INIT_MAX_ALIGN U(3)
-
-/* Alignment required by TE header start address, in bytes */
-#define TRANSFER_LIST_GRANULE U(8)
-
-/*
- * Version of the register convention used.
- * Set to 1 for both AArch64 and AArch32 according to fw handoff spec v0.9
- */
-#define REGISTER_CONVENTION_VERSION_SHIFT_64 UL(32)
-#define REGISTER_CONVENTION_VERSION_SHIFT_32 UL(24)
-#define REGISTER_CONVENTION_VERSION_MASK UL(0xff)
-#define REGISTER_CONVENTION_VERSION UL(1)
-
-#define TRANSFER_LIST_HANDOFF_X1_VALUE(__version) \
- ((TRANSFER_LIST_SIGNATURE & \
- ((1UL << REGISTER_CONVENTION_VERSION_SHIFT_64) - 1)) | \
- (((__version) & REGISTER_CONVENTION_VERSION_MASK) << \
- REGISTER_CONVENTION_VERSION_SHIFT_64))
-
-#define TRANSFER_LIST_HANDOFF_R1_VALUE(__version) \
- ((TRANSFER_LIST_SIGNATURE & \
- ((1UL << REGISTER_CONVENTION_VERSION_SHIFT_32) - 1)) | \
- (((__version) & REGISTER_CONVENTION_VERSION_MASK) << \
- REGISTER_CONVENTION_VERSION_SHIFT_32))
-
-#ifndef __ASSEMBLER__
-
-#define TL_FLAGS_HAS_CHECKSUM BIT(0)
-
-enum transfer_list_tag_id {
- TL_TAG_EMPTY = 0,
- TL_TAG_FDT = 1,
- TL_TAG_HOB_BLOCK = 2,
- TL_TAG_HOB_LIST = 3,
- TL_TAG_ACPI_TABLE_AGGREGATE = 4,
- TL_TAG_TPM_EVLOG = 5,
- TL_TAG_OPTEE_PAGABLE_PART = 0x100,
- TL_TAG_DT_SPMC_MANIFEST = 0x101,
- TL_TAG_EXEC_EP_INFO64 = 0x102,
- TL_TAG_SRAM_LAYOUT64 = 0x104,
- TL_TAG_MBEDTLS_HEAP_INFO = 0x105,
- TL_TAG_EXEC_EP_INFO32 = 0x106,
- TL_TAG_SRAM_LAYOUT32 = 0x107,
-};
-
-enum transfer_list_ops {
- TL_OPS_NON, /* invalid for any operation */
- TL_OPS_ALL, /* valid for all operations */
- TL_OPS_RO, /* valid for read only */
- TL_OPS_CUS, /* abort or switch to special code to interpret */
-};
-
-struct transfer_list_header {
- uint32_t signature;
- uint8_t checksum;
- uint8_t version;
- uint8_t hdr_size;
- uint8_t alignment; /* max alignment of TE data */
- uint32_t size; /* TL header + all TEs */
- uint32_t max_size;
- uint32_t flags;
- uint32_t reserved; /* spare bytes */
- /*
- * Commented out element used to visualize dynamic part of the
- * data structure.
- *
- * Note that struct transfer_list_entry also is dynamic in size
- * so the elements can't be indexed directly but instead must be
- * traversed in order
- *
- * struct transfer_list_entry entries[];
- */
-};
-
-struct __attribute__((packed)) transfer_list_entry {
- uint32_t tag_id : 24;
- uint8_t hdr_size;
- uint32_t data_size;
- /*
- * Commented out element used to visualize dynamic part of the
- * data structure.
- *
- * Note that padding is added at the end of @data to make to reach
- * a 8-byte boundary.
- *
- * uint8_t data[ROUNDUP(data_size, 8)];
- */
-};
-
-CASSERT(sizeof(struct transfer_list_entry) == U(0x8), assert_transfer_list_entry_size);
-
-void transfer_entry_dump(struct transfer_list_entry *te);
-void transfer_list_dump(struct transfer_list_header *tl);
-struct transfer_list_header *transfer_list_ensure(void *addr, size_t size);
-entry_point_info_t *
-transfer_list_set_handoff_args(struct transfer_list_header *tl,
- entry_point_info_t *ep_info);
-struct transfer_list_header *transfer_list_init(void *addr, size_t max_size);
-
-struct transfer_list_header *
-transfer_list_relocate(struct transfer_list_header *tl, void *addr,
- size_t max_size);
-enum transfer_list_ops
-transfer_list_check_header(const struct transfer_list_header *tl);
-
-void transfer_list_update_checksum(struct transfer_list_header *tl);
-bool transfer_list_verify_checksum(const struct transfer_list_header *tl);
-
-bool transfer_list_set_data_size(struct transfer_list_header *tl,
- struct transfer_list_entry *entry,
- uint32_t new_data_size);
-
-void *transfer_list_entry_data(struct transfer_list_entry *entry);
-bool transfer_list_rem(struct transfer_list_header *tl,
- struct transfer_list_entry *entry);
-
-struct transfer_list_entry *transfer_list_add(struct transfer_list_header *tl,
- uint32_t tag_id,
- uint32_t data_size,
- const void *data);
-
-struct transfer_list_entry *
-transfer_list_add_with_align(struct transfer_list_header *tl, uint32_t tag_id,
- uint32_t data_size, const void *data,
- uint8_t alignment);
-
-struct transfer_list_entry *
-transfer_list_next(struct transfer_list_header *tl,
- struct transfer_list_entry *last);
-
-struct transfer_list_entry *transfer_list_find(struct transfer_list_header *tl,
- uint32_t tag_id);
-
-#endif /*__ASSEMBLER__*/
-#endif /*__TRANSFER_LIST_H*/
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 68e464a..7dcc5ce 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -86,6 +86,12 @@
#define EXTRACT(regfield, reg) \
(((reg) & MASK(regfield)) >> (regfield##_SHIFT))
+#define UPDATE_REG_FIELD(regfield, reg, val) \
+ do { \
+ (reg) &= ~(MASK(regfield)); \
+ (reg) |= ((uint64_t)(val) << (regfield##_SHIFT)); \
+ } while (0)
+
/*
* This variant of div_round_up can be used in macro definition but should not
* be used in C code as the `div` parameter is evaluated twice.
diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h
index f540fa5..a0bc1f3 100644
--- a/include/lib/xlat_tables/xlat_tables_defs.h
+++ b/include/lib/xlat_tables/xlat_tables_defs.h
@@ -148,8 +148,8 @@
/* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */
#define ATTR_NON_CACHEABLE MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_NC, MAIR_NORM_NC)
-/* Device-nGnRE */
-#define ATTR_DEVICE MAIR_DEV_nGnRE
+/* Device-nGnRnE */
+#define ATTR_DEVICE MAIR_DEV_nGnRnE
/* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */
#define ATTR_IWBWA_OWBWA_NTR MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_WB_NTR_RWA, MAIR_NORM_WB_NTR_RWA)
#define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3))
diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h
index 64fe5ef..6a0d890 100644
--- a/include/lib/xlat_tables/xlat_tables_v2.h
+++ b/include/lib/xlat_tables/xlat_tables_v2.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -407,9 +407,11 @@
* memory page it lies within are returned.
* attr
* Output parameter where to store the attributes of the targeted memory page.
+ * table_level
+ * Output parameter where to store base_va's table level
*/
int xlat_get_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va,
- uint32_t *attr);
+ uint32_t *attr, unsigned int *table_level);
int xlat_get_mem_attributes(uintptr_t base_va, uint32_t *attr);
#endif /*__ASSEMBLER__*/
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index aed85f5..4a9c2d8 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -17,9 +17,11 @@
#include <lib/el3_runtime/cpu_data.h>
#include <lib/gpt_rme/gpt_rme.h>
#include <lib/spinlock.h>
-#include <lib/transfer_list.h>
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_compat.h>
+#if TRANSFER_LIST
+#include <transfer_list.h>
+#endif
/*******************************************************************************
* Forward declarations
@@ -290,6 +292,7 @@
void arm_bl31_plat_arch_setup(void);
/* Firmware Handoff utility functions */
+#if TRANSFER_LIST
void arm_transfer_list_dyn_cfg_init(struct transfer_list_header *secure_tl);
void arm_transfer_list_populate_ep_info(bl_mem_params_node_t *next_param_node,
struct transfer_list_header *secure_tl);
@@ -298,6 +301,7 @@
struct transfer_list_entry *
arm_transfer_list_set_heap_info(struct transfer_list_header *tl);
void arm_transfer_list_get_heap_info(void **heap_addr, size_t *heap_size);
+#endif
/* TSP utility functions */
void arm_tsp_early_platform_setup(u_register_t arg0, u_register_t arg1,
diff --git a/include/plat/common/plat_lfa.h b/include/plat/common/plat_lfa.h
new file mode 100644
index 0000000..fa7c2f9
--- /dev/null
+++ b/include/plat/common/plat_lfa.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_LFA_H
+#define PLAT_LFA_H
+
+#include <services/lfa_component_desc.h>
+#include <tools_share/uuid.h>
+
+typedef struct plat_lfa_component_info {
+ const uint32_t lfa_component_id;
+ const uuid_t uuid;
+ struct lfa_component_ops *activator;
+ bool activation_pending;
+} plat_lfa_component_info_t;
+
+uint32_t plat_lfa_get_components(plat_lfa_component_info_t **components);
+bool is_plat_lfa_activation_pending(uint32_t lfa_component_id);
+int plat_lfa_cancel(uint32_t lfa_component_id);
+int plat_lfa_load_auth_image(uint32_t lfa_component_id);
+
+#endif /* PLAT_LFA_H */
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index b9985a3..d7c5ed9 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -24,6 +24,9 @@
#if DRTM_SUPPORT
#include "plat_drtm.h"
#endif /* DRTM_SUPPORT */
+#if LFA_SUPPORT
+#include "plat_lfa.h"
+#endif /* LFA_SUPPORT */
/*******************************************************************************
* Forward declarations
@@ -493,6 +496,11 @@
int32_t plat_get_soc_revision(void);
/*
+ * Optional function to get SoC name
+ */
+int32_t plat_get_soc_name(char *soc_name);
+
+/*
* Optional function to check for SMCCC function availability for platform
*/
int32_t plat_is_smccc_feature_available(u_register_t fid);
diff --git a/include/services/arm_arch_svc.h b/include/services/arm_arch_svc.h
index ea7de0e..4f5c24b 100644
--- a/include/services/arm_arch_svc.h
+++ b/include/services/arm_arch_svc.h
@@ -18,6 +18,9 @@
#define SMCCC_GET_SOC_VERSION U(0)
#define SMCCC_GET_SOC_REVISION U(1)
+#define SMCCC_GET_SOC_NAME U(2)
+
+#define SMCCC_SOC_NAME_LEN U(136)
#ifndef __ASSEMBLER__
#if ARCH_FEATURE_AVAILABILITY
@@ -207,6 +210,7 @@
SCR_FIQ_BIT | \
SCR_IRQ_BIT | \
SCR_NS_BIT | \
+ SCR_NSE_BIT | \
SCR_RES1_BITS | \
SCR_FEAT_MEC | \
SCR_PLAT_IGNORED)
@@ -271,7 +275,7 @@
#endif
#if ENABLE_TRBE_FOR_NS
-#define MDCR_FEAT_TRBE MDCR_NSTB(1UL)
+#define MDCR_FEAT_TRBE MDCR_NSTB_EN_BIT
#else
#define MDCR_FEAT_TRBE (0)
#endif
@@ -283,7 +287,7 @@
#endif
#if ENABLE_SPE_FOR_NS
-#define MDCR_FEAT_SPE MDCR_NSPB(1UL)
+#define MDCR_FEAT_SPE MDCR_NSPB_EN_BIT
#else
#define MDCR_FEAT_SPE (0)
#endif
@@ -313,12 +317,12 @@
MDCR_SBRBE(2UL) | \
MDCR_MTPME_BIT | \
MDCR_NSTBE_BIT | \
- MDCR_NSTB(2UL) | \
+ MDCR_NSTB_SS_BIT | \
MDCR_MCCD_BIT | \
MDCR_SCCD_BIT | \
MDCR_SDD_BIT | \
MDCR_SPD32(3UL) | \
- MDCR_NSPB(2UL) | \
+ MDCR_NSPB_SS_BIT | \
MDCR_NSPBE_BIT | \
MDCR_PLAT_IGNORED)
CASSERT((MDCR_EL3_FEATS & MDCR_EL3_IGNORED) == 0, mdcr_feat_is_ignored);
diff --git a/include/services/bl31_lfa.h b/include/services/bl31_lfa.h
new file mode 100644
index 0000000..cfe436c
--- /dev/null
+++ b/include/services/bl31_lfa.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BL31_LFA_H
+#define BL31_LFA_H
+
+#include <services/lfa_component_desc.h>
+
+struct lfa_component_ops *get_bl31_activator(void);
+
+#endif /* BL31_LFA_H */
diff --git a/include/services/drtm_svc.h b/include/services/drtm_svc.h
index 56ae129..8e27b18 100644
--- a/include/services/drtm_svc.h
+++ b/include/services/drtm_svc.h
@@ -102,7 +102,7 @@
#define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK ULL(0xFFFFFFFF)
#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT U(8)
-#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK ULL(0xF)
+#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK ULL(0xFFFF)
#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT U(0)
#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK ULL(0xFF)
diff --git a/include/services/lfa_component_desc.h b/include/services/lfa_component_desc.h
new file mode 100644
index 0000000..5f198bd
--- /dev/null
+++ b/include/services/lfa_component_desc.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef LFA_COMPONENT_DESC_H
+#define LFA_COMPONENT_DESC_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+typedef enum {
+ PRIME_NONE = 0,
+ PRIME_STARTED,
+ PRIME_COMPLETE,
+} lfa_prime_status_t;
+
+struct lfa_component_status {
+ uint32_t component_id;
+ lfa_prime_status_t prime_status;
+ bool cpu_rendezvous_required;
+};
+
+typedef int32_t (*component_prime_fn)(struct lfa_component_status *activation);
+typedef int32_t (*component_activate_fn)(struct lfa_component_status *activation,
+ uint64_t ep_address,
+ uint64_t context_id);
+
+struct lfa_component_ops {
+ component_prime_fn prime;
+ component_activate_fn activate;
+ bool may_reset_cpu;
+ bool cpu_rendezvous_required;
+};
+
+#endif /* LFA_COMPONENT_DESC_H */
diff --git a/include/services/lfa_holding_pen.h b/include/services/lfa_holding_pen.h
new file mode 100644
index 0000000..9420747
--- /dev/null
+++ b/include/services/lfa_holding_pen.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef LFA_HOLDING_PEN_H
+#define LFA_HOLDING_PEN_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <services/lfa_svc.h>
+
+bool lfa_holding_start(void);
+enum lfa_retc lfa_holding_wait(void);
+void lfa_holding_release(enum lfa_retc status);
+
+#endif
diff --git a/include/services/lfa_svc.h b/include/services/lfa_svc.h
new file mode 100644
index 0000000..69d549c
--- /dev/null
+++ b/include/services/lfa_svc.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef LFA_SVC_H
+#define LFA_SVC_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <lib/smccc.h>
+#include <services/lfa_component_desc.h>
+#include <tools_share/uuid.h>
+
+/*
+ * SMC function IDs for LFA Service
+ * Upper word bits set: Fast call, SMC64, Standard Secure Svc. Call (OEN = 4)
+ */
+#define LFA_FID(func_num) \
+ ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \
+ (SMC_64 << FUNCID_CC_SHIFT) | \
+ (OEN_STD_START << FUNCID_OEN_SHIFT) | \
+ ((func_num) << FUNCID_NUM_SHIFT))
+
+#define LFA_VERSION LFA_FID(0x2E0)
+#define LFA_FEATURES LFA_FID(0x2E1)
+#define LFA_GET_INFO LFA_FID(0x2E2)
+#define LFA_GET_INVENTORY LFA_FID(0x2E3)
+#define LFA_PRIME LFA_FID(0x2E4)
+#define LFA_ACTIVATE LFA_FID(0x2E5)
+#define LFA_CANCEL LFA_FID(0x2E6)
+
+/* Check whether FID is in the range */
+#define is_lfa_fid(_fid) \
+ ((_fid >= LFA_VERSION) && (_fid <= LFA_CANCEL))
+
+/* LFA Service Calls version numbers */
+#define LFA_VERSION_MAJOR U(1)
+#define LFA_VERSION_MAJOR_SHIFT 16
+#define LFA_VERSION_MAJOR_MASK U(0x7FFF)
+#define LFA_VERSION_MINOR U(0)
+#define LFA_VERSION_MINOR_SHIFT 0
+#define LFA_VERSION_MINOR_MASK U(0xFFFF)
+
+#define LFA_VERSION_VAL \
+ ((((LFA_VERSION_MAJOR) & LFA_VERSION_MAJOR_MASK) << \
+ LFA_VERSION_MAJOR_SHIFT) \
+ | (((LFA_VERSION_MINOR) & LFA_VERSION_MINOR_MASK) << \
+ LFA_VERSION_MINOR_SHIFT))
+
+#define LFA_INVALID_COMPONENT U(0xFFFFFFFF)
+
+#define LFA_ACTIVATION_CAPABLE_SHIFT 0
+#define LFA_ACTIVATION_PENDING_SHIFT 1
+#define LFA_MAY_RESET_CPU_SHIFT 2
+#define LFA_CPU_RENDEZVOUS_OPTIONAL_SHIFT 3
+
+#define LFA_SKIP_CPU_RENDEZVOUS_BIT BIT(0)
+
+/* List of errors as per the specification */
+enum lfa_retc {
+ LFA_SUCCESS = 0,
+ LFA_NOT_SUPPORTED = -1,
+ LFA_BUSY = -2,
+ LFA_AUTH_ERROR = -3,
+ LFA_NO_MEMORY = -4,
+ LFA_CRITICAL_ERROR = -5,
+ LFA_DEVICE_ERROR = -6,
+ LFA_WRONG_STATE = -7,
+ LFA_INVALID_PARAMETERS = -8,
+ LFA_COMPONENT_WRONG_STATE = -9,
+ LFA_INVALID_ADDRESS = -10,
+ LFA_ACTIVATION_FAILED = -11,
+};
+
+/* Initialization routine for the LFA service */
+int lfa_setup(void);
+
+uint64_t lfa_smc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
+ u_register_t x3, u_register_t x4, void *cookie,
+ void *handle, u_register_t flags);
+void lfa_reset_activation(void);
+
+#endif /* LFA_SVC_H */
diff --git a/include/services/rmmd_rmm_lfa.h b/include/services/rmmd_rmm_lfa.h
new file mode 100644
index 0000000..6720cb5
--- /dev/null
+++ b/include/services/rmmd_rmm_lfa.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RMMD_RMM_LFA_H
+#define RMMD_RMM_LFA_H
+
+#include <services/lfa_component_desc.h>
+
+struct lfa_component_ops *get_rmm_activator(void);
+
+#endif /* RMMD_RMM_LFA_H */
diff --git a/include/services/spm_mm_svc.h b/include/services/spm_mm_svc.h
index b4ed1ab..6086c0f 100644
--- a/include/services/spm_mm_svc.h
+++ b/include/services/spm_mm_svc.h
@@ -67,6 +67,13 @@
#define MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64 U(0xC4000065)
/*
+ * Vendor-specific EL3 range SMC IDs defined for TPM start method for pre-FFA
+ * configuration. These SMCs are converted to MM_COMMUNICATE calls.
+ */
+#define TPM_START_SMC_32 U(0x87000040)
+#define TPM_START_SMC_64 U(0xC7000040)
+
+/*
* Macros used by MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64.
*/
@@ -120,6 +127,16 @@
uint64_t x2,
uint64_t x3);
+/* Helper to handle TPM Start SVC call */
+uint64_t spm_mm_tpm_start_handler(uint32_t smc_fid,
+ uint64_t x1,
+ uint64_t x2,
+ uint64_t x3,
+ uint64_t x4,
+ void *cookie,
+ void *handle,
+ uint64_t flags);
+
#endif /* __ASSEMBLER__ */
#endif /* SPM_MM_SVC_H */
diff --git a/include/services/spmd_svc.h b/include/services/spmd_svc.h
index 95f0707..f8443bd 100644
--- a/include/services/spmd_svc.h
+++ b/include/services/spmd_svc.h
@@ -27,7 +27,8 @@
uint64_t x4,
void *cookie,
void *handle,
- uint64_t flags);
+ uint64_t flags,
+ uint32_t secure_ffa_version);
uint64_t spmd_smc_switch_state(uint32_t smc_fid,
bool secure_origin,
uint64_t x1,
@@ -35,7 +36,8 @@
uint64_t x3,
uint64_t x4,
void *handle,
- uint64_t flags);
+ uint64_t flags,
+ uint32_t secure_ffa_version);
#endif /* __ASSEMBLER__ */
#endif /* SPMD_SVC_H */
diff --git a/include/services/ven_el3_svc.h b/include/services/ven_el3_svc.h
index 0336059..ffa7d0e 100644
--- a/include/services/ven_el3_svc.h
+++ b/include/services/ven_el3_svc.h
@@ -21,7 +21,7 @@
#define VEN_EL3_SVC_VERSION 0x8700ff03
#define VEN_EL3_SVC_VERSION_MAJOR 1
-#define VEN_EL3_SVC_VERSION_MINOR 1
+#define VEN_EL3_SVC_VERSION_MINOR 2
/* DEBUGFS_SMC_32 0x87000010U */
/* DEBUGFS_SMC_64 0xC7000010U */
@@ -32,4 +32,7 @@
/* ACS_SMC_HANDLER_32 0x87000030U */
/* ACS_SMC_HANDLER_64 0xC7000030U */
+/* TPM_START_SMC_32 0x87000040U */
+/* TPM_START_SMC_64 0xC7000040U */
+
#endif /* VEN_EL3_SVC_H */
diff --git a/lib/aarch64/armclang_printf.S b/lib/aarch64/armclang_printf.S
index f9326fd..12622ae 100644
--- a/lib/aarch64/armclang_printf.S
+++ b/lib/aarch64/armclang_printf.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,6 +11,7 @@
.globl __0printf
.globl __1printf
.globl __2printf
+ .globl __2snprintf
func __0printf
b printf
@@ -23,3 +24,7 @@
func __2printf
b printf
endfunc __2printf
+
+func __2snprintf
+ b snprintf
+endfunc __2snprintf
diff --git a/lib/cpus/aarch32/cpu_helpers.S b/lib/cpus/aarch32/cpu_helpers.S
index 83e3e49..863448c 100644
--- a/lib/cpus/aarch32/cpu_helpers.S
+++ b/lib/cpus/aarch32/cpu_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -47,46 +47,7 @@
#endif
-#ifdef IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */
- /*
- * void prepare_cpu_pwr_dwn(unsigned int power_level)
- *
- * Prepare CPU power down function for all platforms. The function takes
- * a domain level to be powered down as its parameter. After the cpu_ops
- * pointer is retrieved from cpu_data, the handler for requested power
- * level is called.
- */
- .globl prepare_cpu_pwr_dwn
-func prepare_cpu_pwr_dwn
- /*
- * If the given power level exceeds CPU_MAX_PWR_DWN_OPS, we call the
- * power down handler for the last power level
- */
- mov r2, #(CPU_MAX_PWR_DWN_OPS - 1)
- cmp r0, r2
- movhi r0, r2
-
- push {r0, lr}
- bl _cpu_data
- pop {r2, lr}
-
- ldr r0, [r0, #CPU_DATA_CPU_OPS_PTR]
-#if ENABLE_ASSERTIONS
- cmp r0, #0
- ASM_ASSERT(ne)
-#endif
-
- /* Get the appropriate power down handler */
- mov r1, #CPU_PWR_DWN_OPS
- add r1, r1, r2, lsl #2
- ldr r1, [r0, r1]
-#if ENABLE_ASSERTIONS
- cmp r1, #0
- ASM_ASSERT(ne)
-#endif
- bx r1
-endfunc prepare_cpu_pwr_dwn
-
+#ifdef IMAGE_BL32
/*
* Initializes the cpu_ops_ptr if not already initialized
* in cpu_data. This must only be called after the data cache
diff --git a/lib/cpus/aarch64/aem_generic.S b/lib/cpus/aarch64/aem_generic.S
index 9843943..243f657 100644
--- a/lib/cpus/aarch64/aem_generic.S
+++ b/lib/cpus/aarch64/aem_generic.S
@@ -12,15 +12,6 @@
func aem_generic_core_pwr_dwn
/* ---------------------------------------------
- * Disable the Data Cache.
- * ---------------------------------------------
- */
- mrs x1, sctlr_el3
- bic x1, x1, #SCTLR_C_BIT
- msr sctlr_el3, x1
- isb
-
- /* ---------------------------------------------
* AEM model supports L3 caches in which case L2
* will be private per core caches and flush
* from L1 to L2 is not sufficient.
@@ -60,15 +51,6 @@
func aem_generic_cluster_pwr_dwn
/* ---------------------------------------------
- * Disable the Data Cache.
- * ---------------------------------------------
- */
- mrs x1, sctlr_el3
- bic x1, x1, #SCTLR_C_BIT
- msr sctlr_el3, x1
- isb
-
- /* ---------------------------------------------
* Flush all caches to PoC.
* ---------------------------------------------
*/
diff --git a/lib/cpus/aarch64/cortex_a35.S b/lib/cpus/aarch64/cortex_a35.S
index 40e6200..bb354df 100644
--- a/lib/cpus/aarch64/cortex_a35.S
+++ b/lib/cpus/aarch64/cortex_a35.S
@@ -13,16 +13,6 @@
cpu_reset_prologue cortex_a35
/* ---------------------------------------------
- * Disable L1 data cache and unified L2 cache
- * ---------------------------------------------
- */
-func cortex_a35_disable_dcache
- sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
- isb
- ret
-endfunc cortex_a35_disable_dcache
-
- /* ---------------------------------------------
* Disable intra-cluster coherency
* ---------------------------------------------
*/
@@ -55,12 +45,6 @@
mov x18, x30
/* ---------------------------------------------
- * Turn off caches.
- * ---------------------------------------------
- */
- bl cortex_a35_disable_dcache
-
- /* ---------------------------------------------
* Flush L1 caches.
* ---------------------------------------------
*/
@@ -79,12 +63,6 @@
mov x18, x30
/* ---------------------------------------------
- * Turn off caches.
- * ---------------------------------------------
- */
- bl cortex_a35_disable_dcache
-
- /* ---------------------------------------------
* Flush L1 caches.
* ---------------------------------------------
*/
diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
index 258817f..1285034 100644
--- a/lib/cpus/aarch64/cortex_a510.S
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -187,6 +187,7 @@
* ----------------------------------------------------
*/
func cortex_a510_core_pwr_dwn
+ apply_erratum cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
diff --git a/lib/cpus/aarch64/cortex_a520.S b/lib/cpus/aarch64/cortex_a520.S
index ac8019e0..5e0b711 100644
--- a/lib/cpus/aarch64/cortex_a520.S
+++ b/lib/cpus/aarch64/cortex_a520.S
@@ -9,6 +9,7 @@
#include <common/bl_common.h>
#include <cortex_a520.h>
#include <cpu_macros.S>
+#include <dsu_macros.S>
#include <plat_macros.S>
.global check_erratum_cortex_a520_2938996
@@ -37,6 +38,15 @@
check_erratum_ls cortex_a520, ERRATUM(2858100), CPU_REV(0, 1)
+workaround_reset_start cortex_a520, ERRATUM(2900952), ERRATA_DSU_2900952
+ errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_a520, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_a520, ERRATUM(2900952)
+ check_errata_dsu_2900952_applies
+ ret
+check_erratum_custom_end cortex_a520, ERRATUM(2900952)
+
add_erratum_entry cortex_a520, ERRATUM(2938996), ERRATA_A520_2938996
check_erratum_ls cortex_a520, ERRATUM(2938996), CPU_REV(0, 1)
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S
index dbfff87..e3b69ab 100644
--- a/lib/cpus/aarch64/cortex_a53.S
+++ b/lib/cpus/aarch64/cortex_a53.S
@@ -15,16 +15,6 @@
cpu_reset_prologue cortex_a53
/* ---------------------------------------------
- * Disable L1 data cache and unified L2 cache
- * ---------------------------------------------
- */
-func cortex_a53_disable_dcache
- sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
- isb
- ret
-endfunc cortex_a53_disable_dcache
-
- /* ---------------------------------------------
* Disable intra-cluster coherency
* ---------------------------------------------
*/
@@ -144,12 +134,6 @@
mov x18, x30
/* ---------------------------------------------
- * Turn off caches.
- * ---------------------------------------------
- */
- bl cortex_a53_disable_dcache
-
- /* ---------------------------------------------
* Flush L1 caches.
* ---------------------------------------------
*/
@@ -168,12 +152,6 @@
mov x18, x30
/* ---------------------------------------------
- * Turn off caches.
- * ---------------------------------------------
- */
- bl cortex_a53_disable_dcache
-
- /* ---------------------------------------------
* Flush L1 caches.
* ---------------------------------------------
*/
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index 553f6f9..18521a2 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -16,16 +16,6 @@
cpu_reset_prologue cortex_a57
/* ---------------------------------------------
- * Disable L1 data cache and unified L2 cache
- * ---------------------------------------------
- */
-func cortex_a57_disable_dcache
- sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
- isb
- ret
-endfunc cortex_a57_disable_dcache
-
- /* ---------------------------------------------
* Disable all types of L2 prefetches.
* ---------------------------------------------
*/
@@ -59,7 +49,7 @@
msr osdlr_el1, x0
isb
- apply_erratum cortex_a57, ERRATUM(817169), ERRATA_A57_817169, NO_GET_CPU_REV
+ apply_erratum cortex_a57, ERRATUM(817169), ERRATA_A57_817169
dsb sy
ret
@@ -200,12 +190,6 @@
mov x18, x30
/* ---------------------------------------------
- * Turn off caches.
- * ---------------------------------------------
- */
- bl cortex_a57_disable_dcache
-
- /* ---------------------------------------------
* Disable the L2 prefetches.
* ---------------------------------------------
*/
@@ -240,12 +224,6 @@
mov x18, x30
/* ---------------------------------------------
- * Turn off caches.
- * ---------------------------------------------
- */
- bl cortex_a57_disable_dcache
-
- /* ---------------------------------------------
* Disable the L2 prefetches.
* ---------------------------------------------
*/
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
index 54bb453..65fa98f 100644
--- a/lib/cpus/aarch64/cortex_a710.S
+++ b/lib/cpus/aarch64/cortex_a710.S
@@ -31,6 +31,55 @@
cpu_reset_prologue cortex_a710
+workaround_reset_start cortex_a710, ERRATUM(1901946), ERRATA_A710_1901946
+ sysreg_bit_set CORTEX_A710_CPUACTLR4_EL1, BIT(15)
+workaround_reset_end cortex_a710, ERRATUM(1901946)
+
+check_erratum_range cortex_a710, ERRATUM(1901946), CPU_REV(1, 0), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(1916945), ERRATA_A710_1916945
+ sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(8)
+workaround_reset_end cortex_a710, ERRATUM(1916945)
+
+check_erratum_ls cortex_a710, ERRATUM(1916945), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(1917258), ERRATA_A710_1917258
+ sysreg_bit_set CORTEX_A710_CPUACTLR4_EL1, BIT(43)
+workaround_reset_end cortex_a710, ERRATUM(1917258)
+
+check_erratum_ls cortex_a710, ERRATUM(1917258), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(1927200), ERRATA_A710_1927200
+ mov x0, #0
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0x10E3900002
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0x10FFF00083
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0
+
+ mov x0, #1
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0x10E3800082
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0x10FFF00083
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0
+
+ mov x0, #2
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0x10E3800200
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0x10FFF003E0
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0
+workaround_reset_end cortex_a710, ERRATUM(1927200)
+
+check_erratum_ls cortex_a710, ERRATUM(1927200), CPU_REV(1, 0)
+
workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031
ldr x0,=0x6
msr S3_6_c15_c8_0,x0
@@ -227,7 +276,7 @@
* ----------------------------------------------------
*/
func cortex_a710_core_pwr_dwn
- apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768, NO_GET_CPU_REV
+ apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768
apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV
/* ---------------------------------------------------
diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S
index 23b27ab..f35f867 100644
--- a/lib/cpus/aarch64/cortex_a72.S
+++ b/lib/cpus/aarch64/cortex_a72.S
@@ -18,18 +18,6 @@
cpu_reset_prologue cortex_a72
/* ---------------------------------------------
- * Disable L1 data cache and unified L2 cache
- * ---------------------------------------------
- */
-func cortex_a72_disable_dcache
- mrs x1, sctlr_el3
- bic x1, x1, #SCTLR_C_BIT
- msr sctlr_el3, x1
- isb
- ret
-endfunc cortex_a72_disable_dcache
-
- /* ---------------------------------------------
* Disable all types of L2 prefetches.
* ---------------------------------------------
*/
@@ -177,12 +165,6 @@
mov x18, x30
/* ---------------------------------------------
- * Turn off caches.
- * ---------------------------------------------
- */
- bl cortex_a72_disable_dcache
-
- /* ---------------------------------------------
* Disable the L2 prefetches.
* ---------------------------------------------
*/
@@ -223,12 +205,6 @@
mov x18, x30
/* ---------------------------------------------
- * Turn off caches.
- * ---------------------------------------------
- */
- bl cortex_a72_disable_dcache
-
- /* ---------------------------------------------
* Disable the L2 prefetches.
* ---------------------------------------------
*/
diff --git a/lib/cpus/aarch64/cortex_a720.S b/lib/cpus/aarch64/cortex_a720.S
index e639996..0c713c3 100644
--- a/lib/cpus/aarch64/cortex_a720.S
+++ b/lib/cpus/aarch64/cortex_a720.S
@@ -9,6 +9,7 @@
#include <common/bl_common.h>
#include <cortex_a720.h>
#include <cpu_macros.S>
+#include <dsu_macros.S>
#include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S"
@@ -42,6 +43,15 @@
check_erratum_ls cortex_a720, ERRATUM(2844092), CPU_REV(0, 1)
+workaround_reset_start cortex_a720, ERRATUM(2900952), ERRATA_DSU_2900952
+ errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_a720, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_a720, ERRATUM(2900952)
+ check_errata_dsu_2900952_applies
+ ret
+check_erratum_custom_end cortex_a720, ERRATUM(2900952)
+
workaround_reset_start cortex_a720, ERRATUM(2926083), ERRATA_A720_2926083
/* Erratum 2926083 workaround is required only if SPE is enabled */
#if ENABLE_SPE_FOR_NS != 0
diff --git a/lib/cpus/aarch64/cortex_a725.S b/lib/cpus/aarch64/cortex_a725.S
index 682ca45..e940bde 100644
--- a/lib/cpus/aarch64/cortex_a725.S
+++ b/lib/cpus/aarch64/cortex_a725.S
@@ -9,6 +9,7 @@
#include <common/bl_common.h>
#include <cortex_a725.h>
#include <cpu_macros.S>
+#include <dsu_macros.S>
#include <plat_macros.S>
/* Hardware handled coherency */
@@ -25,6 +26,15 @@
.global check_erratum_cortex_a725_3699564
+workaround_reset_start cortex_a725, ERRATUM(2900952), ERRATA_DSU_2900952
+ errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_a725, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_a725, ERRATUM(2900952)
+ check_errata_dsu_2900952_applies
+ ret
+check_erratum_custom_end cortex_a725, ERRATUM(2900952)
+
add_erratum_entry cortex_a725, ERRATUM(3699564), ERRATA_A725_3699564
check_erratum_ls cortex_a725, ERRATUM(3699564), CPU_REV(0, 1)
diff --git a/lib/cpus/aarch64/cortex_a73.S b/lib/cpus/aarch64/cortex_a73.S
index 9cc6fdb..14f1ef8 100644
--- a/lib/cpus/aarch64/cortex_a73.S
+++ b/lib/cpus/aarch64/cortex_a73.S
@@ -13,16 +13,6 @@
cpu_reset_prologue cortex_a73
/* ---------------------------------------------
- * Disable L1 data cache
- * ---------------------------------------------
- */
-func cortex_a73_disable_dcache
- sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
- isb
- ret
-endfunc cortex_a73_disable_dcache
-
- /* ---------------------------------------------
* Disable intra-cluster coherency
* ---------------------------------------------
*/
@@ -123,12 +113,6 @@
mov x18, x30
/* ---------------------------------------------
- * Turn off caches.
- * ---------------------------------------------
- */
- bl cortex_a73_disable_dcache
-
- /* ---------------------------------------------
* Flush L1 caches.
* ---------------------------------------------
*/
@@ -147,12 +131,6 @@
mov x18, x30
/* ---------------------------------------------
- * Turn off caches.
- * ---------------------------------------------
- */
- bl cortex_a73_disable_dcache
-
- /* ---------------------------------------------
* Flush L1 caches.
* ---------------------------------------------
*/
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index ca5ccf7..fc6d737 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -515,7 +515,7 @@
*/
sysreg_bit_set CORTEX_A76_CPUPWRCTLR_EL1, CORTEX_A76_CORE_PWRDN_EN_MASK
- apply_erratum cortex_a76, ERRATUM(2743102), ERRATA_A76_2743102, NO_GET_CPU_REV
+ apply_erratum cortex_a76, ERRATUM(2743102), ERRATA_A76_2743102
isb
ret
diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S
index 82a20ec..09b25e2 100644
--- a/lib/cpus/aarch64/cortex_a77.S
+++ b/lib/cpus/aarch64/cortex_a77.S
@@ -169,7 +169,7 @@
sysreg_bit_set CORTEX_A77_CPUPWRCTLR_EL1, \
CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100, NO_GET_CPU_REV
+ apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100
isb
ret
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index b166823..7623446 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -191,7 +191,7 @@
func cortex_a78_core_pwr_dwn
sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019, NO_GET_CPU_REV
+ apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019
isb
ret
diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S
index 19d988e..0349cc5 100644
--- a/lib/cpus/aarch64/cortex_a78c.S
+++ b/lib/cpus/aarch64/cortex_a78c.S
@@ -129,7 +129,7 @@
*/
sysreg_bit_set CORTEX_A78C_CPUPWRCTLR_EL1, CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121, NO_GET_CPU_REV
+ apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121
isb
ret
diff --git a/lib/cpus/aarch64/cortex_alto.S b/lib/cpus/aarch64/cortex_alto.S
index 69a630d..6d0e08b 100644
--- a/lib/cpus/aarch64/cortex_alto.S
+++ b/lib/cpus/aarch64/cortex_alto.S
@@ -41,6 +41,7 @@
sysreg_bit_set CORTEX_ALTO_IMP_CPUPWRCTLR_EL1, \
CORTEX_ALTO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
isb
+ signal_pabandon_handled
ret
endfunc cortex_alto_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_gelas.S b/lib/cpus/aarch64/cortex_gelas.S
index 4cdec32..d322006 100644
--- a/lib/cpus/aarch64/cortex_gelas.S
+++ b/lib/cpus/aarch64/cortex_gelas.S
@@ -21,10 +21,6 @@
#error "Gelas supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
-#if FEAT_PABANDON == 0
-#error "Gelas must be compiled with FEAT_PABANDON enabled"
-#endif
-
#if ERRATA_SME_POWER_DOWN == 0
#error "Gelas needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly"
#endif
@@ -56,6 +52,7 @@
sysreg_bit_toggle CORTEX_GELAS_CPUPWRCTLR_EL1, \
CORTEX_GELAS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
+ signal_pabandon_handled
ret
endfunc cortex_gelas_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S
index 910a6a9..a67553d 100644
--- a/lib/cpus/aarch64/cortex_x2.S
+++ b/lib/cpus/aarch64/cortex_x2.S
@@ -180,7 +180,7 @@
*/
sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- apply_erratum cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515, NO_GET_CPU_REV
+ apply_erratum cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515
isb
ret
endfunc cortex_x2_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index 158ee0e..8879b54 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -96,10 +96,28 @@
check_erratum_ls cortex_x3, ERRATUM(2779509), CPU_REV(1, 1)
+workaround_reset_start cortex_x3, ERRATUM(3213672), ERRATA_X3_3213672
+ sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(36)
+workaround_reset_end cortex_x3, ERRATUM(3213672)
+
+check_erratum_ls cortex_x3, ERRATUM(3213672), CPU_REV(1, 2)
+
+workaround_reset_start cortex_x3, ERRATUM(3692984), ERRATA_X3_3692984
+ sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41)
+workaround_reset_end cortex_x3, ERRATUM(3692984)
+
+check_erratum_ls cortex_x3, ERRATUM(3692984), CPU_REV(1, 2)
+
add_erratum_entry cortex_x3, ERRATUM(3701769), ERRATA_X3_3701769
check_erratum_ls cortex_x3, ERRATUM(3701769), CPU_REV(1, 2)
+workaround_reset_start cortex_x3, ERRATUM(3827463), ERRATA_X3_3827463
+ sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(1)
+workaround_reset_end cortex_x3, ERRATUM(3827463)
+
+check_erratum_ls cortex_x3, ERRATUM(3827463), CPU_REV(1, 1)
+
workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
override_vector_table wa_cve_vbar_cortex_x3
@@ -137,7 +155,7 @@
* ----------------------------------------------------
*/
func cortex_x3_core_pwr_dwn
- apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909, NO_GET_CPU_REV
+ apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index 1d0c377..72a2595 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -9,6 +9,7 @@
#include <common/bl_common.h>
#include <cortex_x4.h>
#include <cpu_macros.S>
+#include <dsu_macros.S>
#include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S"
@@ -64,6 +65,15 @@
check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1)
+workaround_reset_start cortex_x4, ERRATUM(2900952), ERRATA_DSU_2900952
+ errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_x4, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_x4, ERRATUM(2900952)
+ check_errata_dsu_2900952_applies
+ ret
+check_erratum_custom_end cortex_x4, ERRATUM(2900952)
+
workaround_reset_start cortex_x4, ERRATUM(2923985), ERRATA_X4_2923985
sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, (BIT(11) | BIT(10))
workaround_reset_end cortex_x4, ERRATUM(2923985)
@@ -144,7 +154,7 @@
*/
sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089, NO_GET_CPU_REV
+ apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
isb
ret
diff --git a/lib/cpus/aarch64/cortex_x925.S b/lib/cpus/aarch64/cortex_x925.S
index 0663b21..003dc97 100644
--- a/lib/cpus/aarch64/cortex_x925.S
+++ b/lib/cpus/aarch64/cortex_x925.S
@@ -9,6 +9,7 @@
#include <common/bl_common.h>
#include <cortex_x925.h>
#include <cpu_macros.S>
+#include <dsu_macros.S>
#include <plat_macros.S>
/* Hardware handled coherency */
@@ -23,6 +24,15 @@
cpu_reset_prologue cortex_x925
+workaround_reset_start cortex_x925, ERRATUM(2900952), ERRATA_DSU_2900952
+ errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_x925, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_x925, ERRATUM(2900952)
+ check_errata_dsu_2900952_applies
+ ret
+check_erratum_custom_end cortex_x925, ERRATUM(2900952)
+
add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747
check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1)
diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S
index 105da5c..1b20d5c 100644
--- a/lib/cpus/aarch64/cpu_helpers.S
+++ b/lib/cpus/aarch64/cpu_helpers.S
@@ -14,44 +14,6 @@
#include <lib/cpus/errata.h>
#include <lib/el3_runtime/cpu_data.h>
-#ifdef IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
- /*
- * void prepare_cpu_pwr_dwn(unsigned int power_level)
- *
- * Prepare CPU power down function for all platforms. The function takes
- * a domain level to be powered down as its parameter. After the cpu_ops
- * pointer is retrieved from cpu_data, the handler for requested power
- * level is called.
- */
- .globl prepare_cpu_pwr_dwn
-func prepare_cpu_pwr_dwn
- /*
- * If the given power level exceeds CPU_MAX_PWR_DWN_OPS, we call the
- * power down handler for the last power level
- */
- mov_imm x2, (CPU_MAX_PWR_DWN_OPS - 1)
- cmp x0, x2
- csel x2, x2, x0, hi
-
- mrs x1, tpidr_el3
- ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR]
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif
-
- /* Get the appropriate power down handler */
- mov x1, #CPU_PWR_DWN_OPS
- add x1, x1, x2, lsl #3
- ldr x1, [x0, x1]
-#if ENABLE_ASSERTIONS
- cmp x1, #0
- ASM_ASSERT(ne)
-#endif
- br x1
-endfunc prepare_cpu_pwr_dwn
-
-
/*
* Initializes the cpu_ops_ptr if not already initialized
* in cpu_data. This can be called without a runtime stack, but may
@@ -70,7 +32,6 @@
1:
ret
endfunc init_cpu_ops
-#endif /* IMAGE_BL31 */
#if defined(IMAGE_BL31) && CRASH_REPORTING
/*
diff --git a/lib/cpus/aarch64/generic.S b/lib/cpus/aarch64/generic.S
index 0a10eed..c59575c 100644
--- a/lib/cpus/aarch64/generic.S
+++ b/lib/cpus/aarch64/generic.S
@@ -13,28 +13,10 @@
cpu_reset_prologue generic
- /* ---------------------------------------------
- * Disable L1 data cache and unified L2 cache
- * ---------------------------------------------
- */
-func generic_disable_dcache
- mrs x1, sctlr_el3
- bic x1, x1, #SCTLR_C_BIT
- msr sctlr_el3, x1
- isb
- ret
-endfunc generic_disable_dcache
-
func generic_core_pwr_dwn
mov x18, x30
/* ---------------------------------------------
- * Turn off caches.
- * ---------------------------------------------
- */
- bl generic_disable_dcache
-
- /* ---------------------------------------------
* Flush L1 caches.
* ---------------------------------------------
*/
@@ -48,12 +30,6 @@
mov x18, x30
/* ---------------------------------------------
- * Turn off caches.
- * ---------------------------------------------
- */
- bl generic_disable_dcache
-
- /* ---------------------------------------------
* Flush L1 caches.
* ---------------------------------------------
*/
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index e821ecb..baeb83c 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -240,7 +240,7 @@
*/
sysreg_bit_set NEOVERSE_N1_CPUPWRCTLR_EL1, NEOVERSE_N1_CORE_PWRDN_EN_MASK
- apply_erratum neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102, NO_GET_CPU_REV
+ apply_erratum neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102
isb
ret
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
index 7d9d7f1..2f053ac 100644
--- a/lib/cpus/aarch64/neoverse_n2.S
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -274,7 +274,7 @@
cpu_reset_func_end neoverse_n2
func neoverse_n2_core_pwr_dwn
- apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478, NO_GET_CPU_REV
+ apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478
apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV
/* ---------------------------------------------------
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
index f975be0..96b52aa 100644
--- a/lib/cpus/aarch64/neoverse_v1.S
+++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -253,7 +253,7 @@
* ---------------------------------------------
*/
sysreg_bit_set NEOVERSE_V1_CPUPWRCTLR_EL1, NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093, NO_GET_CPU_REV
+ apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093
isb
ret
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S
index 9526b80..8224f93 100644
--- a/lib/cpus/aarch64/neoverse_v2.S
+++ b/lib/cpus/aarch64/neoverse_v2.S
@@ -113,7 +113,7 @@
* ---------------------------------------------------
*/
sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372, NO_GET_CPU_REV
+ apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
isb
ret
diff --git a/lib/cpus/aarch64/qemu_max.S b/lib/cpus/aarch64/qemu_max.S
index a727379..7980066 100644
--- a/lib/cpus/aarch64/qemu_max.S
+++ b/lib/cpus/aarch64/qemu_max.S
@@ -12,15 +12,6 @@
func qemu_max_core_pwr_dwn
/* ---------------------------------------------
- * Disable the Data Cache.
- * ---------------------------------------------
- */
- mrs x1, sctlr_el3
- bic x1, x1, #SCTLR_C_BIT
- msr sctlr_el3, x1
- isb
-
- /* ---------------------------------------------
* Flush L1 cache to L2.
* ---------------------------------------------
*/
@@ -33,15 +24,6 @@
func qemu_max_cluster_pwr_dwn
/* ---------------------------------------------
- * Disable the Data Cache.
- * ---------------------------------------------
- */
- mrs x1, sctlr_el3
- bic x1, x1, #SCTLR_C_BIT
- msr sctlr_el3, x1
- isb
-
- /* ---------------------------------------------
* Flush all caches to PoC.
* ---------------------------------------------
*/
diff --git a/lib/cpus/aarch64/travis.S b/lib/cpus/aarch64/travis.S
index d53e46f..a959acb 100644
--- a/lib/cpus/aarch64/travis.S
+++ b/lib/cpus/aarch64/travis.S
@@ -21,10 +21,6 @@
#error "Travis supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
-#if FEAT_PABANDON == 0
-#error "Travis must be compiled with FEAT_PABANDON enabled"
-#endif
-
#if ERRATA_SME_POWER_DOWN == 0
#error "Travis needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly"
#endif
@@ -52,6 +48,7 @@
sysreg_bit_toggle TRAVIS_IMP_CPUPWRCTLR_EL1, \
TRAVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
isb
+ signal_pabandon_handled
ret
endfunc travis_core_pwr_dwn
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 4b8de00..4bf76f9 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -561,6 +561,22 @@
# the Neoverse V3 cpu and is still open.
CPU_FLAG_LIST += ERRATA_V3_3701767
+# Flag to apply erratum 1901946 workaround during reset. This erratum applies
+# to revision r1p0 and is fixed in r2p0.
+CPU_FLAG_LIST += ERRATA_A710_1901946
+
+# Flag to apply erratum 1916945 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the Cortex-A710 CPU and is fixed in r2p0.
+CPU_FLAG_LIST += ERRATA_A710_1916945
+
+# Flag to apply erratum 1917258 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the Cortex-A710 CPU and is fixed in r2p0.
+CPU_FLAG_LIST += ERRATA_A710_1917258
+
+# Flag to apply erratum 1927200 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the Cortex-A710 CPU and is fixed in r2p0.
+CPU_FLAG_LIST += ERRATA_A710_1927200
+
# Flag to apply erratum 1987031 workaround during reset. This erratum applies
# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
CPU_FLAG_LIST += ERRATA_A710_1987031
@@ -830,6 +846,19 @@
# to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_X3_2779509
+# Flag to apply erratum 3213672 workaround on reset. This erratum applies
+# to revisions r0p0, r1p0, r1p1 and r1p2 of the Cortex-X3 cpu.
+# It is still open.
+CPU_FLAG_LIST += ERRATA_X3_3213672
+
+# Flag to apply erratum 3692984 workaround on reset. This erratum applies
+# to revisions r0p0, r1p0, r1p1, r1p2 of the Cortex-X3 cpu and is still open.
+CPU_FLAG_LIST += ERRATA_X3_3692984
+
+# Flag to apply erratum 3827463 workaround on reset. This erratum applies
+# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu. It is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_X3_3827463
+
# Flag to apply erratum 2701112 workaround for platforms that do not use an
# Arm interconnect IP. This erratum applies to revisions r0p0 of the Cortex-X4
# cpu and is fixed in r0p1.
@@ -1063,6 +1092,13 @@
# results in higher DSU power consumption on idle.
CPU_FLAG_LIST += ERRATA_DSU_2313941
+# Flag to apply DSU erratum 2900952 during reset. This erratum applies
+# to some implementations of DSU-120 revision r2p0. Erratum might be fixed
+# in some implementations of r2p0. This can be determined by reading
+# the IMP_CLUSTERREVIDR_EL1 register where a set bit indicates that
+# the erratum is fixed in this part. It is fixed in r2p1.
+CPU_FLAG_LIST += ERRATA_DSU_2900952
+
ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0)
ifeq (${WORKAROUND_CVE_2018_3639},0)
$(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1")
diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c
index ab68467..47e8699 100644
--- a/lib/cpus/errata_report.c
+++ b/lib/cpus/errata_report.c
@@ -31,7 +31,7 @@
/* Errata format: BL stage, CPU, errata ID, message */
#define ERRATA_FORMAT "%s: %s: CPU workaround for %s was %s\n"
-#define CVE_FORMAT "%s: %s: CPU workaround for CVE %u_%u was %s\n"
+#define CVE_FORMAT "%s: %s: CPU workaround for CVE %u_%04u was %s\n"
#define ERRATUM_FORMAT "%s: %s: CPU workaround for erratum %u was %s\n"
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index 00d9c01..b150cb9 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -175,7 +175,7 @@
* HYP mode then HYP mode is disabled by configuring all necessary HYP mode
* registers.
******************************************************************************/
-void cm_prepare_el3_exit(uint32_t security_state)
+void cm_prepare_el3_exit(size_t security_state)
{
uint32_t hsctlr, scr;
cpu_context_t *ctx = cm_get_context(security_state);
diff --git a/lib/el3_runtime/aarch32/cpu_data.S b/lib/el3_runtime/aarch32/cpu_data.S
deleted file mode 100644
index e59b7fd..0000000
--- a/lib/el3_runtime/aarch32/cpu_data.S
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2016, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <asm_macros.S>
-#include <lib/el3_runtime/cpu_data.h>
-
- .globl _cpu_data
- .globl _cpu_data_by_index
-
-/* -----------------------------------------------------------------
- * cpu_data_t *_cpu_data(void)
- *
- * Return the cpu_data structure for the current CPU.
- * -----------------------------------------------------------------
- */
-func _cpu_data
- /* r12 is pushed to meet the 8 byte stack alignment requirement */
- push {r12, lr}
- bl plat_my_core_pos
- pop {r12, lr}
- b _cpu_data_by_index
-endfunc _cpu_data
-
-/* -----------------------------------------------------------------
- * cpu_data_t *_cpu_data_by_index(uint32_t cpu_index)
- *
- * Return the cpu_data structure for the CPU with given linear index
- *
- * This can be called without a valid stack.
- * clobbers: r0, r1
- * -----------------------------------------------------------------
- */
-func _cpu_data_by_index
- mov_imm r1, CPU_DATA_SIZE
- mul r0, r0, r1
- ldr r1, =percpu_data
- add r0, r0, r1
- bx lr
-endfunc _cpu_data_by_index
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index d04e02f..2a6158a 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -48,11 +48,9 @@
#endif /* ENABLE_FEAT_TWED */
per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM];
-static bool has_secure_perworld_init;
static void manage_extensions_nonsecure(cpu_context_t *ctx);
static void manage_extensions_secure(cpu_context_t *ctx);
-static void manage_extensions_secure_per_world(void);
#if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)))
static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep)
@@ -150,34 +148,29 @@
#endif
manage_extensions_secure(ctx);
-
- /**
- * manage_extensions_secure_per_world api has to be executed once,
- * as the registers getting initialised, maintain constant value across
- * all the cpus for the secure world.
- * Henceforth, this check ensures that the registers are initialised once
- * and avoids re-initialization from multiple cores.
- */
- if (!has_secure_perworld_init) {
- manage_extensions_secure_per_world();
- }
}
-#if ENABLE_RME
+#if ENABLE_RME && IMAGE_BL31
/******************************************************************************
* This function performs initializations that are specific to REALM state
* and updates the cpu context specified by 'ctx'.
+ *
+ * NOTE: any changes to this function must be verified by an RMMD maintainer.
*****************************************************************************/
static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep)
{
u_register_t scr_el3;
el3_state_t *state;
+ el2_sysregs_t *el2_ctx;
state = get_el3state_ctx(ctx);
scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
+ el2_ctx = get_el2_sysregs_ctx(ctx);
scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT;
+ write_el2_ctx_common(el2_ctx, spsr_el2, SPSR_EL2_REALM);
+
/* CSV2 version 2 and above */
if (is_feat_csv2_2_supported()) {
/* Enable access to the SCXTNUM_ELx registers. */
@@ -191,6 +184,15 @@
scr_el3 |= SCR_SCTLR2En_BIT;
}
+ if (is_feat_d128_supported()) {
+ /*
+ * Set the D128En bit in SCR_EL3 to enable access to 128-bit
+ * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1,
+ * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers.
+ */
+ scr_el3 |= SCR_D128En_BIT;
+ }
+
write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
if (is_feat_fgt2_supported()) {
@@ -205,8 +207,22 @@
brbe_enable(ctx);
}
+ /*
+ * Enable access to TPIDR2_EL0 if SME/SME2 is enabled for Non Secure world.
+ */
+ if (is_feat_sme_supported()) {
+ sme_enable(ctx);
+ }
+
+ if (is_feat_spe_supported()) {
+ spe_disable_realm(ctx);
+ }
+
+ if (is_feat_trbe_supported()) {
+ trbe_disable_realm(ctx);
+ }
}
-#endif /* ENABLE_RME */
+#endif /* ENABLE_RME && IMAGE_BL31 */
/******************************************************************************
* This function performs initializations that are specific to NON-SECURE state
@@ -313,12 +329,6 @@
/* Initialize EL2 context registers */
#if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
-
- /*
- * Initialize SCTLR_EL2 context register with reset value.
- */
- write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1);
-
if (is_feat_hcx_supported()) {
/*
* Initialize register HCRX_EL2 with its init value.
@@ -585,6 +595,13 @@
}
pmuv3_enable(ctx);
+
+#if CTX_INCLUDE_EL2_REGS
+ /*
+ * Initialize SCTLR_EL2 context register with reset value.
+ */
+ write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1);
+#endif /* CTX_INCLUDE_EL2_REGS */
#endif /* IMAGE_BL31 */
/*
@@ -623,7 +640,7 @@
******************************************************************************/
void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
{
- unsigned int security_state;
+ size_t security_state;
assert(ctx != NULL);
@@ -640,7 +657,7 @@
case SECURE:
setup_secure_context(ctx, ep);
break;
-#if ENABLE_RME
+#if ENABLE_RME && IMAGE_BL31
case REALM:
setup_realm_context(ctx, ep);
break;
@@ -675,16 +692,17 @@
sme_init_el3();
}
+ if (is_feat_fgwte3_supported()) {
+ write_fgwte3_el3(FGWTE3_EL3_EARLY_INIT_VAL);
+ }
pmuv3_init_el3();
}
-#endif /* IMAGE_BL31 */
/******************************************************************************
* Function to initialise the registers with the RESET values in the context
* memory, which are maintained per world.
******************************************************************************/
-#if IMAGE_BL31
-void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx)
+static void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx)
{
/*
* Initialise CPTR_EL3, setting all fields rather than relying on hw.
@@ -709,15 +727,13 @@
per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL;
}
-#endif /* IMAGE_BL31 */
/*******************************************************************************
* Initialise per_world_context for Non-Secure world.
* This function enables the architecture extensions, which have same value
* across the cores for the non-secure world.
******************************************************************************/
-#if IMAGE_BL31
-void manage_extensions_nonsecure_per_world(void)
+static void manage_extensions_nonsecure_per_world(void)
{
cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]);
@@ -745,7 +761,6 @@
fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
}
}
-#endif /* IMAGE_BL31 */
/*******************************************************************************
* Initialise per_world_context for Secure world.
@@ -754,7 +769,6 @@
******************************************************************************/
static void manage_extensions_secure_per_world(void)
{
-#if IMAGE_BL31
cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
if (is_feat_sme_supported()) {
@@ -793,11 +807,56 @@
if (is_feat_sys_reg_trace_supported()) {
sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
}
-
- has_secure_perworld_init = true;
-#endif /* IMAGE_BL31 */
}
+static void manage_extensions_realm_per_world(void)
+{
+#if ENABLE_RME
+ cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_REALM]);
+
+ if (is_feat_sve_supported()) {
+ /*
+ * Enable SVE and FPU in realm context when it is enabled for NS.
+ * Realm manager must ensure that the SVE and FPU register
+ * contexts are properly managed.
+ */
+ sve_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
+ }
+
+ /* NS can access this but Realm shouldn't */
+ if (is_feat_sys_reg_trace_supported()) {
+ sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
+ }
+
+ /*
+ * If SME/SME2 is supported and enabled for NS world, then disable trapping
+ * of SME instructions for Realm world. RMM will save/restore required
+ * registers that are shared with SVE/FPU so that Realm can use FPU or SVE.
+ */
+ if (is_feat_sme_supported()) {
+ sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
+ }
+
+ /*
+ * If FEAT_MPAM is supported and enabled, then disable trapping access
+ * to the MPAM registers for Realm world. Instead, RMM will configure
+ * the access to be trapped by itself so it can inject undefined aborts
+ * back to the Realm.
+ */
+ if (is_feat_mpam_supported()) {
+ mpam_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
+ }
+#endif /* ENABLE_RME */
+}
+
+void cm_manage_extensions_per_world(void)
+{
+ manage_extensions_nonsecure_per_world();
+ manage_extensions_secure_per_world();
+ manage_extensions_realm_per_world();
+}
+#endif /* IMAGE_BL31 */
+
/*******************************************************************************
* Enable architecture extensions on first entry to Non-secure world.
******************************************************************************/
@@ -821,20 +880,15 @@
debugv8p9_extended_bp_wp_enable(ctx);
}
- /*
- * SPE, TRBE, and BRBE have multi-field enables that affect which world
- * they apply to. Despite this, it is useful to ignore these for
- * simplicity in determining the feature's per world enablement status.
- * This is only possible when context is written per-world. Relied on
- * by SMCCC_ARCH_FEATURE_AVAILABILITY
- */
if (is_feat_spe_supported()) {
- spe_enable(ctx);
+ spe_enable_ns(ctx);
}
- if (!check_if_trbe_disable_affected_core()) {
- if (is_feat_trbe_supported()) {
- trbe_enable(ctx);
+ if (is_feat_trbe_supported()) {
+ if (check_if_trbe_disable_affected_core()) {
+ trbe_disable_ns(ctx);
+ } else {
+ trbe_enable_ns(ctx);
}
}
@@ -920,18 +974,12 @@
}
}
- /*
- * SPE and TRBE cannot be fully disabled from EL3 registers alone, only
- * sysreg access can. In case the EL1 controls leave them active on
- * context switch, we want the owning security state to be NS so Secure
- * can't be DOSed.
- */
if (is_feat_spe_supported()) {
- spe_disable(ctx);
+ spe_disable_secure(ctx);
}
if (is_feat_trbe_supported()) {
- trbe_disable(ctx);
+ trbe_disable_secure(ctx);
}
#endif /* IMAGE_BL31 */
}
@@ -1062,7 +1110,7 @@
* EL2 then EL2 is disabled by configuring all necessary EL2 registers.
* For all entries, the EL1 registers are initialized from the cpu_context
******************************************************************************/
-void cm_prepare_el3_exit(uint32_t security_state)
+void cm_prepare_el3_exit(size_t security_state)
{
u_register_t sctlr_el2, scr_el3;
cpu_context_t *ctx = cm_get_context(security_state);
@@ -1126,6 +1174,14 @@
init_nonsecure_el2_unused(ctx);
}
}
+
+ if (is_feat_fgwte3_supported()) {
+ /*
+ * TCR_EL3 and ACTLR_EL3 could be overwritten
+ * by platforms and hence is locked a bit late.
+ */
+ write_fgwte3_el3(FGWTE3_EL3_LATE_INIT_VAL);
+ }
}
#if (!CTX_INCLUDE_EL2_REGS)
/* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */
diff --git a/lib/el3_runtime/aarch64/cpu_data.S b/lib/el3_runtime/aarch64/cpu_data.S
deleted file mode 100644
index 02d9415..0000000
--- a/lib/el3_runtime/aarch64/cpu_data.S
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <asm_macros.S>
-#include <lib/el3_runtime/cpu_data.h>
-
-.globl _cpu_data_by_index
-
-/* -----------------------------------------------------------------
- * cpu_data_t *_cpu_data_by_index(uint32_t cpu_index)
- *
- * Return the cpu_data structure for the CPU with given linear index
- *
- * This can be called without a valid stack.
- * clobbers: x0, x1
- * -----------------------------------------------------------------
- */
-func _cpu_data_by_index
- mov_imm x1, CPU_DATA_SIZE
- mul x0, x0, x1
- adrp x1, percpu_data
- add x1, x1, :lo12:percpu_data
- add x0, x0, x1
- ret
-endfunc _cpu_data_by_index
diff --git a/lib/el3_runtime/cpu_data_array.c b/lib/el3_runtime/cpu_data_array.c
index 2056182..f2e97f0 100644
--- a/lib/el3_runtime/cpu_data_array.c
+++ b/lib/el3_runtime/cpu_data_array.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2016, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,6 +8,14 @@
#include <lib/cassert.h>
#include <lib/el3_runtime/cpu_data.h>
+#include <plat/common/platform.h>
/* The per_cpu_ptr_cache_t space allocation */
cpu_data_t percpu_data[PLATFORM_CORE_COUNT];
+
+#ifndef __aarch64__
+cpu_data_t *_cpu_data(void)
+{
+ return _cpu_data_by_index(plat_my_core_pos());
+}
+#endif
diff --git a/lib/extensions/brbe/brbe.c b/lib/extensions/brbe/brbe.c
index f951654..b34fc5d 100644
--- a/lib/extensions/brbe/brbe.c
+++ b/lib/extensions/brbe/brbe.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,7 +17,7 @@
/*
* MDCR_EL3.SBRBE = 0b01
* Allows BRBE usage in non-secure world and prohibited in
- * secure world.
+ * secure world. This is relied on by SMCCC_ARCH_FEATURE_AVAILABILITY.
*
* MDCR_EL3.{E3BREW, E3BREC} = 0b00
* Branch recording at EL3 is disabled
diff --git a/lib/extensions/spe/spe.c b/lib/extensions/spe/spe.c
index e499486..ddd8516 100644
--- a/lib/extensions/spe/spe.c
+++ b/lib/extensions/spe/spe.c
@@ -13,47 +13,78 @@
#include <plat/common/platform.h>
-void spe_enable(cpu_context_t *ctx)
+/*
+ * SPE is an unusual feature. Its enable is split into two:
+ * - (NSPBE, NSPB[0]) - the security state bits - determines which security
+ * state owns the profiling buffer.
+ * - NSPB[1] - the enable bit - determines if the security state that owns the
+ * buffer may access SPE registers.
+ *
+ * There is a secondary id register PMBIDR_EL1 that is more granular than
+ * ID_AA64DFR0_EL1. When a security state owns the buffer, PMBIDR_EL1.P will
+ * report that SPE programming is allowed. This means that the usual assumption
+ * that leaving all bits to a default of zero will disable the feature may not
+ * work correctly. To correctly disable SPE, the current security state must NOT
+ * own the buffer, irrespective of the enable bit. Then, to play nicely with
+ * SMCCC_ARCH_FEATURE_AVAILABILITY, the enable bit should correspond to the
+ * enable status. The feature is architected this way to allow for lazy context
+ * switching of the buffer - a world can be made owner of the buffer (with
+ * PMBIDR_EL1.P reporting full access) without giving it access to the registers
+ * (by trapping to EL3). Then context switching can be deferred until a world
+ * tries to use SPE at which point access can be given and the trapping
+ * instruction repeated.
+ *
+ * This can be simplified to the following rules:
+ * 1. To enable SPE for world X:
+ * * world X owns the buffer ((NSPBE, NSPB[0]) == SCR_EL3.{NSE, NS})
+ * * trapping disabled (NSPB[0] == 1)
+ * 2. To disable SPE for world X:
+ * * world X does not own the buffer ((NSPBE, NSPB[0]) != SCR_EL3.{NSE, NS})
+ * * trapping enabled (NSPB[0] == 0)
+ */
+
+/*
+ * MDCR_EL3.EnPMSN (ARM v8.7) and MDCR_EL3.EnPMS3: Do not trap access to
+ * PMSNEVFR_EL1 or PMSDSFR_EL1 register at NS-EL1 or NS-EL2 to EL3 if
+ * FEAT_SPEv1p2 or FEAT_SPE_FDS are implemented. Setting these bits to 1 doesn't
+ * have any effect on it when the features aren't implemented.
+ */
+void spe_enable_ns(cpu_context_t *ctx)
{
el3_state_t *state = get_el3state_ctx(ctx);
u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
- /*
- * MDCR_EL3.NSPB (ARM v8.2): SPE enabled in Non-secure state
- * and disabled in secure state. Accesses to SPE registers at
- * S-EL1 generate trap exceptions to EL3.
- *
- * MDCR_EL3.NSPBE: Profiling Buffer uses Non-secure Virtual Addresses.
- * When FEAT_RME is not implemented, this field is RES0.
- *
- * MDCR_EL3.EnPMSN (ARM v8.7) and MDCR_EL3.EnPMS3: Do not trap access to
- * PMSNEVFR_EL1 or PMSDSFR_EL1 register at NS-EL1 or NS-EL2 to EL3 if FEAT_SPEv1p2
- * or FEAT_SPE_FDS are implemented. Setting these bits to 1 doesn't have any
- * effect on it when the features aren't implemented.
- */
- mdcr_el3_val |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT | MDCR_EnPMS3_BIT;
+ mdcr_el3_val |= MDCR_NSPB_EN_BIT | MDCR_NSPB_SS_BIT | MDCR_EnPMSN_BIT | MDCR_EnPMS3_BIT;
mdcr_el3_val &= ~(MDCR_NSPBE_BIT);
+
write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
-void spe_disable(cpu_context_t *ctx)
+/*
+ * MDCR_EL3.EnPMSN (ARM v8.7) and MDCR_EL3.EnPMS3: Clear the bits to trap access
+ * of PMSNEVFR_EL1 and PMSDSFR_EL1 from EL2/EL1 to EL3.
+ */
+static void spe_disable_others(cpu_context_t *ctx)
{
el3_state_t *state = get_el3state_ctx(ctx);
u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
- /*
- * MDCR_EL3.{NSPB,NSPBE} = 0b00, 0b0
- * Disable access of profiling buffer control registers from lower ELs
- * in any security state. Secure state owns the buffer.
- *
- * MDCR_EL3.EnPMSN (ARM v8.7) and MDCR_EL3.EnPMS3: Clear the bits to trap access
- * of PMSNEVFR_EL1 and PMSDSFR_EL1 from EL2/EL1 to EL3.
- */
- mdcr_el3_val &= ~(MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_NSPBE_BIT | MDCR_EnPMSN_BIT |
+ mdcr_el3_val |= MDCR_NSPB_SS_BIT;
+ mdcr_el3_val &= ~(MDCR_NSPB_EN_BIT | MDCR_NSPBE_BIT | MDCR_EnPMSN_BIT |
MDCR_EnPMS3_BIT);
write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
+void spe_disable_secure(cpu_context_t *ctx)
+{
+ spe_disable_others(ctx);
+}
+
+void spe_disable_realm(cpu_context_t *ctx)
+{
+ spe_disable_others(ctx);
+}
+
void spe_init_el2_unused(void)
{
uint64_t v;
diff --git a/lib/extensions/trbe/trbe.c b/lib/extensions/trbe/trbe.c
index 24d88ae..eeae0a7 100644
--- a/lib/extensions/trbe/trbe.c
+++ b/lib/extensions/trbe/trbe.c
@@ -9,41 +9,82 @@
#include <arch_helpers.h>
#include <lib/extensions/trbe.h>
-void trbe_enable(cpu_context_t *ctx)
+
+/*
+ * TRBE is an unusual feature. Its enable is split into two:
+ * - (NSTBE, NSTB[0]) - the security state bits - determines which security
+ * state owns the trace buffer.
+ * - NSTB[1] - the enable bit - determines if the security state that owns the
+ * buffer may access TRBE registers.
+ *
+ * There is a secondary id register TRBIDR_EL1 that is more granular than
+ * ID_AA64DFR0_EL1. When a security state owns the buffer, TRBIDR_EL1.P will
+ * report that TRBE programming is allowed. This means that the usual assumption
+ * that leaving all bits to a default of zero will disable the feature may not
+ * work correctly. To correctly disable TRBE, the current security state must NOT
+ * own the buffer, irrespective of the enable bit. Then, to play nicely with
+ * SMCCC_ARCH_FEATURE_AVAILABILITY, the enable bit should correspond to the
+ * enable status. The feature is architected this way to allow for lazy context
+ * switching of the buffer - a world can be made owner of the buffer (with
+ * TRBIDR_EL1.P reporting full access) without giving it access to the registers
+ * (by trapping to EL3). Then context switching can be deferred until a world
+ * tries to use TRBE at which point access can be given and the trapping
+ * instruction repeated.
+ *
+ * This can be simplified to the following rules:
+ * 1. To enable TRBE for world X:
+ * * world X owns the buffer ((NSTBE, NSTB[0]) == SCR_EL3.{NSE, NS})
+ * * trapping disabled (NSTB[0] == 1)
+ * 2. To disable TRBE for world X:
+ * * world X does not own the buffer ((NSTBE, NSTB[0]) != SCR_EL3.{NSE, NS})
+ * * trapping enabled (NSTB[0] == 0)
+ */
+void trbe_enable_ns(cpu_context_t *ctx)
{
el3_state_t *state = get_el3state_ctx(ctx);
u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
- /*
- * MDCR_EL3.NSTBE = 0b0
- * Trace Buffer owning Security state is Non-secure state. If FEAT_RME
- * is not implemented, this field is RES0.
- *
- * MDCR_EL3.NSTB = 0b11
- * Allow access of trace buffer control registers from NS-EL1 and
- * NS-EL2, tracing is prohibited in Secure and Realm state (if
- * implemented).
- */
- mdcr_el3_val |= MDCR_NSTB(MDCR_NSTB_EL1);
+ mdcr_el3_val |= MDCR_NSTB_EN_BIT | MDCR_NSTB_SS_BIT;
mdcr_el3_val &= ~(MDCR_NSTBE_BIT);
+
write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
-void trbe_disable(cpu_context_t *ctx)
+static void trbe_disable_all(cpu_context_t *ctx, bool ns)
{
el3_state_t *state = get_el3state_ctx(ctx);
u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
- /*
- * MDCR_EL3.{NSTBE,NSTB} = 0b0, 0b00
- * Disable access of trace buffer control registers from lower ELs in
- * any security state. Secure state owns the buffer.
- */
- mdcr_el3_val &= ~(MDCR_NSTB(MDCR_NSTB_EL1));
- mdcr_el3_val &= ~(MDCR_NSTBE_BIT);
+ mdcr_el3_val &= ~MDCR_NSTB_EN_BIT;
+ mdcr_el3_val &= ~MDCR_NSTBE_BIT;
+
+ /* make NS owner, except when NS is running */
+ if (ns) {
+ mdcr_el3_val &= ~MDCR_NSTB_SS_BIT;
+ } else {
+ mdcr_el3_val |= MDCR_NSTB_SS_BIT;
+ }
+
write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
+
+void trbe_disable_ns(cpu_context_t *ctx)
+{
+ trbe_disable_all(ctx, true);
+}
+
+void trbe_disable_secure(cpu_context_t *ctx)
+{
+ trbe_disable_all(ctx, false);
+}
+
+void trbe_disable_realm(cpu_context_t *ctx)
+{
+ trbe_disable_all(ctx, false);
+}
+
+
void trbe_init_el2_unused(void)
{
/*
diff --git a/lib/libc/memcpy.c b/lib/libc/memcpy.c
index ca31de5..e8be154 100644
--- a/lib/libc/memcpy.c
+++ b/lib/libc/memcpy.c
@@ -12,8 +12,9 @@
const char *s = src;
char *d = dst;
- while (len--)
+ while (len--) {
*d++ = *s++;
+ }
return dst;
}
diff --git a/lib/libc/memmove.c b/lib/libc/memmove.c
index 6451e4e..7aee83f 100644
--- a/lib/libc/memmove.c
+++ b/lib/libc/memmove.c
@@ -24,8 +24,9 @@
const char *end = dst;
const char *s = (const char *)src + len;
char *d = (char *)dst + len;
- while (d != end)
+ while (d != end) {
*--d = *--s;
+ }
}
return dst;
}
diff --git a/lib/libc/printf.c b/lib/libc/printf.c
index c9e8a04..65c5238 100644
--- a/lib/libc/printf.c
+++ b/lib/libc/printf.c
@@ -131,8 +131,9 @@
(void)putchar((int32_t)'-');
unum = (unsigned long long int)-num;
padn--;
- } else
+ } else {
unum = (unsigned long long int)num;
+ }
count += unsigned_num_print(unum, 10,
padc, padn, uppercase);
@@ -164,8 +165,9 @@
padc, padn, uppercase);
break;
case 'z':
- if (sizeof(size_t) == 8U)
+ if (sizeof(size_t) == 8U) {
l_count = 2;
+ }
fmt++;
goto loop;
diff --git a/lib/locks/exclusive/aarch32/spinlock.S b/lib/locks/exclusive/aarch32/spinlock.S
index 853d096..6962933 100644
--- a/lib/locks/exclusive/aarch32/spinlock.S
+++ b/lib/locks/exclusive/aarch32/spinlock.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,6 +21,21 @@
#define COND_SEV() sev
#endif
+/*
+ * Function: spin_lock
+ * -------------------
+ * Acquires a spinlock by continuously attempting to set it.
+ * Will block (spin) until the lock is successfully acquired.
+ *
+ * Arguments:
+ * r0 - Pointer to the spinlock variable (uint32_t *lock)
+ *
+ * Return:
+ * None
+ *
+ * Description:
+ * Blocks until the lock is acquired using LDREX/STREX with WFE for wait.
+ */
func spin_lock
mov r2, #1
1:
@@ -34,7 +49,47 @@
bx lr
endfunc spin_lock
+/*
+ * Function: spin_trylock
+ * ----------------------
+ * Attempts to acquire the spinlock once without blocking.
+ *
+ * Arguments:
+ * r0 - Pointer to the spinlock variable (uint32_t *lock)
+ *
+ * Return:
+ * r0 - 1 if lock was successfully acquired
+ * 0 if lock was already held
+ *
+ * Description:
+ * Tries once to acquire the lock using LDREX/STREX.
+ */
+func spin_trylock
+ mov r2, #1
+ ldrex r1, [r0]
+ cmp r1, #0
+ strexeq r1, r2, [r0]
+ cmpeq r1, #0
+ dmb
+ moveq r0, #1
+ movne r0, #0
+ bx lr
+endfunc spin_trylock
+/*
+ * Function: spin_unlock
+ * ---------------------
+ * Releases the spinlock by clearing its value.
+ *
+ * Arguments:
+ * r0 - Pointer to the spinlock variable (uint32_t *lock)
+ *
+ * Return:
+ * None
+ *
+ * Description:
+ * Releases the lock using store-release and sends SEV.
+ */
func spin_unlock
mov r1, #0
stl r1, [r0]
diff --git a/lib/locks/exclusive/aarch64/spinlock.S b/lib/locks/exclusive/aarch64/spinlock.S
index 77bb7fe..bbe28b2 100644
--- a/lib/locks/exclusive/aarch64/spinlock.S
+++ b/lib/locks/exclusive/aarch64/spinlock.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,13 +22,23 @@
*/
/*
- * Acquire lock using Compare and Swap instruction.
+ * Function: spin_lock
+ * -------------------
+ * Acquires a spinlock using the Compare-And-Swap (CASA) instruction.
+ * Spins until the lock is successfully acquired.
*
- * Compare for 0 with acquire semantics, and swap 1. If failed to acquire, use
- * load exclusive semantics to monitor the address and enter WFE.
+ * Arguments:
+ * x0 - Pointer to the spinlock variable (spinlock_t *lock)
*
- * void spin_lock(spinlock_t *lock);
+ * Return:
+ * None
+ *
+ * Description:
+ * - Attempts to acquire the lock by performing a compare-and-swap of 0 -> 1.
+ * - If the lock is already held, uses LDAXR/WFE to efficiently wait.
+ * - Loops until the lock is acquired.
*/
+
func spin_lock
mov w2, #1
1: mov w1, wzr
@@ -42,12 +52,48 @@
ret
endfunc spin_lock
+/*
+ * Function: spin_trylock
+ * ----------------------
+ * Attempts to acquire the spinlock using the CASA instruction without spinning.
+ *
+ * Arguments:
+ * x0 - Pointer to the spinlock variable (spinlock_t *lock)
+ *
+ * Return:
+ * w0 - 1 if lock was successfully acquired
+ * 0 if lock was already held
+ *
+ * Description:
+ * - Performs a single compare-and-swap operation.
+ * - If the lock is already held, returns failure immediately.
+ */
+func spin_trylock
+ mov w1, wzr
+ mov w2, #1
+ casa w1, w2, [x0]
+ eor w0, w1, #1
+ ret
+endfunc spin_trylock
+
#else /* !USE_SPINLOCK_CAS */
/*
- * Acquire lock using load-/store-exclusive instruction pair.
+ * Function: spin_lock
+ * -------------------
+ * Acquires a spinlock using the load-acquire (LDAXR) and store-exclusive
+ * (STXR) instruction pair.Spins until the lock is acquired.
*
- * void spin_lock(spinlock_t *lock);
+ * Arguments:
+ * x0 - Pointer to the spinlock variable (spinlock_t *lock)
+ *
+ * Return:
+ * None
+ *
+ * Description:
+ * - Waits for the lock to be released using WFE.
+ * - Attempts to acquire it by setting the value to 1 using LDAXR/STXR.
+ * - Uses SEVL/WFE to reduce power while waiting.
*/
func spin_lock
mov w2, #1
@@ -60,16 +106,53 @@
ret
endfunc spin_lock
+/*
+ * Function: spin_trylock
+ * ----------------------
+ * Attempts to acquire the spinlock once using LDAXR/STXR without spinning.
+ *
+ * Arguments:
+ * x0 - Pointer to the spinlock variable (spinlock_t *lock)
+ *
+ * Return:
+ * w0 - 1 if lock was successfully acquired
+ * 0 if lock was already held
+ *
+ * Description:
+ * - Loads the lock value.
+ * - If unlocked (0), attempts to store 1 to acquire it.
+ * - Returns success or failure based on the outcome.
+ */
+func spin_trylock
+ mov w2, #1
+ ldaxr w1, [x0]
+ cbnz w1, fail
+ stxr w1, w2, [x0]
+ cbnz w1, fail
+ mov w0, #1
+ ret
+fail:
+ mov w0, #0
+ ret
+endfunc spin_trylock
+
#endif /* USE_SPINLOCK_CAS */
/*
- * Release lock previously acquired by spin_lock.
+ * Function: spin_unlock
+ * ---------------------
+ * Releases the spinlock previously acquired by spin_lock or spin_trylock.
*
- * Use store-release to unconditionally clear the spinlock variable.
- * Store operation generates an event to all cores waiting in WFE
- * when address is monitored by the global monitor.
+ * Arguments:
+ * x0 - Pointer to the spinlock variable (spinlock_t *lock)
*
- * void spin_unlock(spinlock_t *lock);
+ * Return:
+ * None
+ *
+ * Description:
+ * Use store-release to unconditionally clear the spinlock variable.
+ * Store operation generates an event to all cores waiting in WFE
+ * when address is monitored by the global monitor
*/
func spin_unlock
stlr wzr, [x0]
diff --git a/lib/psci/aarch32/psci_helpers.S b/lib/psci/aarch32/psci_helpers.S
index 4e1013c..493715a 100644
--- a/lib/psci/aarch32/psci_helpers.S
+++ b/lib/psci/aarch32/psci_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,44 +10,47 @@
.globl psci_do_pwrdown_cache_maintenance
.globl psci_do_pwrup_cache_maintenance
- .globl psci_power_down_wfi
/* -----------------------------------------------------------------------
- * void psci_do_pwrdown_cache_maintenance(unsigned int power level);
+ * void psci_do_pwrdown_cache_maintenance(void);
*
- * This function performs cache maintenance for the specified power
- * level. The levels of cache affected are determined by the power
- * level which is passed as the argument i.e. level 0 results
- * in a flush of the L1 cache. Both the L1 and L2 caches are flushed
- * for a higher power level.
- *
- * Additionally, this function also ensures that stack memory is correctly
- * flushed out to avoid coherency issues due to a change in its memory
- * attributes after the data cache is disabled.
+ * This function turns off data caches and also ensures that stack memory
+ * is correctly flushed out to avoid coherency issues due to a change in
+ * its memory attributes.
* -----------------------------------------------------------------------
*/
func psci_do_pwrdown_cache_maintenance
push {r4, lr}
+ bl plat_get_my_stack
- /* ----------------------------------------------
- * Turn OFF cache and do stack maintenance
- * prior to cpu operations . This sequence is
- * different from AArch64 because in AArch32 the
- * assembler routines for cpu operations utilize
- * the stack whereas in AArch64 it doesn't.
- * ----------------------------------------------
- */
- mov r4, r0
- bl do_stack_maintenance
+ /* Turn off the D-cache */
+ ldcopr r1, SCTLR
+ bic r1, #SCTLR_C_BIT
+ stcopr r1, SCTLR
+ isb
/* ---------------------------------------------
- * Invoke CPU-specifc power down operations for
- * the appropriate level
+ * Calculate and store the size of the used
+ * stack memory in r1.
* ---------------------------------------------
*/
- mov r0, r4
- pop {r4, lr}
- b prepare_cpu_pwr_dwn
+ mov r4, r0
+ mov r1, sp
+ sub r1, r0, r1
+ mov r0, sp
+ bl flush_dcache_range
+
+ /* ---------------------------------------------
+ * Calculate and store the size of the unused
+ * stack memory in r1. Calculate and store the
+ * stack base address in r0.
+ * ---------------------------------------------
+ */
+ sub r0, r4, #PLATFORM_STACK_SIZE
+ sub r1, sp, r0
+ bl inv_dcache_range
+
+ pop {r4, pc}
endfunc psci_do_pwrdown_cache_maintenance
@@ -93,57 +96,3 @@
pop {r12, pc}
endfunc psci_do_pwrup_cache_maintenance
-
- /* ---------------------------------------------
- * void do_stack_maintenance(void)
- * Do stack maintenance by flushing the used
- * stack to the main memory and invalidating the
- * remainder.
- * ---------------------------------------------
- */
-func do_stack_maintenance
- push {r4, lr}
- bl plat_get_my_stack
-
- /* Turn off the D-cache */
- ldcopr r1, SCTLR
- bic r1, #SCTLR_C_BIT
- stcopr r1, SCTLR
- isb
-
- /* ---------------------------------------------
- * Calculate and store the size of the used
- * stack memory in r1.
- * ---------------------------------------------
- */
- mov r4, r0
- mov r1, sp
- sub r1, r0, r1
- mov r0, sp
- bl flush_dcache_range
-
- /* ---------------------------------------------
- * Calculate and store the size of the unused
- * stack memory in r1. Calculate and store the
- * stack base address in r0.
- * ---------------------------------------------
- */
- sub r0, r4, #PLATFORM_STACK_SIZE
- sub r1, sp, r0
- bl inv_dcache_range
-
- pop {r4, pc}
-endfunc do_stack_maintenance
-
-/* -----------------------------------------------------------------------
- * This function is called to indicate to the power controller that it
- * is safe to power down this cpu. It should not exit the wfi and will
- * be released from reset upon power up.
- * -----------------------------------------------------------------------
- */
-func psci_power_down_wfi
- dsb sy // ensure write buffer empty
-1:
- wfi
- b 1b
-endfunc psci_power_down_wfi
diff --git a/lib/psci/aarch64/psci_helpers.S b/lib/psci/aarch64/psci_helpers.S
index b297f9b..ce8adc2 100644
--- a/lib/psci/aarch64/psci_helpers.S
+++ b/lib/psci/aarch64/psci_helpers.S
@@ -12,32 +12,24 @@
.globl psci_do_pwrdown_cache_maintenance
.globl psci_do_pwrup_cache_maintenance
- .globl psci_power_down_wfi
/* -----------------------------------------------------------------------
- * void psci_do_pwrdown_cache_maintenance(unsigned int power level);
+ * void psci_do_pwrdown_cache_maintenance(void);
*
- * This function performs cache maintenance for the specified power
- * level. The levels of cache affected are determined by the power
- * level which is passed as the argument i.e. level 0 results
- * in a flush of the L1 cache. Both the L1 and L2 caches are flushed
- * for a higher power level.
- *
- * Additionally, this function also ensures that stack memory is correctly
- * flushed out to avoid coherency issues due to a change in its memory
- * attributes after the data cache is disabled.
+ * This function turns off data caches and also ensures that stack memory
+ * is correctly flushed out to avoid coherency issues due to a change in
+ * its memory attributes.
* -----------------------------------------------------------------------
*/
func psci_do_pwrdown_cache_maintenance
stp x29, x30, [sp,#-16]!
stp x19, x20, [sp,#-16]!
- /* ---------------------------------------------
- * Invoke CPU-specific power down operations for
- * the appropriate level
- * ---------------------------------------------
- */
- bl prepare_cpu_pwr_dwn
+ /* Disable L1 data cache and unified L2 cache */
+ mrs x1, sctlr_el3
+ bic x1, x1, #SCTLR_C_BIT
+ msr sctlr_el3, x1
+ isb
/* ---------------------------------------------
* Do stack maintenance by flushing the used
@@ -116,26 +108,3 @@
ldp x29, x30, [sp], #16
ret
endfunc psci_do_pwrup_cache_maintenance
-
-/* -----------------------------------------------------------------------
- * void psci_power_down_wfi(void); This function is called to indicate to the
- * power controller that it is safe to power down this cpu. It may exit if the
- * request was denied and reset did not occur
- * -----------------------------------------------------------------------
- */
-func psci_power_down_wfi
- apply_erratum cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597
-
- dsb sy // ensure write buffer empty
- wfi
-
- /*
- * in case the WFI wasn't terminal, we have to undo errata mitigations.
- * These will be smart enough to handle being called the same way
- */
- apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219
- apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909, NO_GET_CPU_REV
- apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV
-
- ret
-endfunc psci_power_down_wfi
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 1c634e3..bc1bad0 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -14,6 +14,7 @@
#include <common/debug.h>
#include <context.h>
#include <drivers/delay_timer.h>
+#include <lib/cpus/cpu_ops.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/extensions/spe.h>
#include <lib/pmf/pmf.h>
@@ -215,7 +216,7 @@
******************************************************************************/
bool psci_is_last_on_cpu(unsigned int my_idx)
{
- for (unsigned int cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) {
+ for (unsigned int cpu_idx = 0U; cpu_idx < psci_plat_core_count; cpu_idx++) {
if (cpu_idx == my_idx) {
assert(psci_get_aff_info_state() == AFF_STATE_ON);
continue;
@@ -239,7 +240,7 @@
{
unsigned int cpu_idx;
- for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) {
+ for (cpu_idx = 0U; cpu_idx < psci_plat_core_count; cpu_idx++) {
if (psci_get_aff_info_state_by_idx(cpu_idx) == AFF_STATE_OFF) {
return false;
}
@@ -249,6 +250,33 @@
}
/*******************************************************************************
+ * Counts the number of CPUs in the system that are currently in the ON or
+ * ON_PENDING state.
+ *
+ * @note This function does not acquire any power domain locks. It must only be
+ * called in contexts where it is guaranteed that PSCI state transitions
+ * are not concurrently happening, or where locks are already held.
+ *
+ * @return The number of CPUs currently in AFF_STATE_ON or AFF_STATE_ON_PENDING.
+ ******************************************************************************/
+static unsigned int psci_num_cpus_running(void)
+{
+ unsigned int cpu_idx;
+ unsigned int no_of_cpus = 0U;
+ aff_info_state_t aff_state;
+
+ for (cpu_idx = 0U; cpu_idx < psci_plat_core_count; cpu_idx++) {
+ aff_state = psci_get_aff_info_state_by_idx(cpu_idx);
+ if (aff_state == AFF_STATE_ON ||
+ aff_state == AFF_STATE_ON_PENDING) {
+ no_of_cpus++;
+ }
+ }
+
+ return no_of_cpus;
+}
+
+/*******************************************************************************
* Routine to return the maximum power level to traverse to after a cpu has
* been physically powered up. It is expected to be called immediately after
* reset from assembler code.
@@ -976,6 +1004,11 @@
unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
+#if FEATURE_DETECTION
+ /* Detect if features enabled during compilation are supported by PE. */
+ detect_arch_features(cpu_idx);
+#endif /* FEATURE_DETECTION */
+
/* Init registers that never change for the lifetime of TF-A */
cm_manage_extensions_el3(cpu_idx);
@@ -1028,7 +1061,7 @@
unsigned int max_off_lvl = psci_find_max_off_lvl(&state_info);
assert(max_off_lvl != PSCI_INVALID_PWR_LVL);
- psci_cpu_suspend_to_powerdown_finish(cpu_idx, max_off_lvl, &state_info);
+ psci_cpu_suspend_to_powerdown_finish(cpu_idx, max_off_lvl, &state_info, false);
}
/*
@@ -1168,6 +1201,44 @@
return (n_valid > 1U) ? 1 : 0;
}
+static u_register_t call_cpu_pwr_dwn(unsigned int power_level)
+{
+ struct cpu_ops *ops = get_cpu_data(cpu_ops_ptr);
+
+ /* Call the last available power down handler */
+ if (power_level > CPU_MAX_PWR_DWN_OPS - 1) {
+ power_level = CPU_MAX_PWR_DWN_OPS - 1;
+ }
+
+ assert(ops != NULL);
+ assert(ops->pwr_dwn_ops[power_level] != NULL);
+
+ return ops->pwr_dwn_ops[power_level]();
+}
+
+static void prepare_cpu_pwr_dwn(unsigned int power_level)
+{
+ /* ignore the return, all cpus should behave the same */
+ (void)call_cpu_pwr_dwn(power_level);
+}
+
+static void prepare_cpu_pwr_up(unsigned int power_level)
+{
+ /*
+ * Call the pwr_dwn cpu hook again, indicating that an abandon happened.
+ * The cpu driver is expected to clean up. We ask it to return
+ * PABANDON_ACK to indicate that it has handled this. This is a
+ * heuristic: the value has been chosen such that an unported CPU is
+ * extremely unlikely to return this value.
+ */
+ u_register_t ret = call_cpu_pwr_dwn(power_level);
+
+ /* unreachable on AArch32 so cast down to calm the compiler */
+ if (ret != (u_register_t) PABANDON_ACK) {
+ panic();
+ }
+}
+
/*******************************************************************************
* Initiate power down sequence, by calling power down operations registered for
* this CPU.
@@ -1185,26 +1256,24 @@
PMF_CACHE_MAINT);
#endif
-#if HW_ASSISTED_COHERENCY
+#if !HW_ASSISTED_COHERENCY
/*
- * With hardware-assisted coherency, the CPU drivers only initiate the
- * power down sequence, without performing cache-maintenance operations
- * in software. Data caches enabled both before and after this call.
- */
- prepare_cpu_pwr_dwn(power_level);
-#else
- /*
- * Without hardware-assisted coherency, the CPU drivers disable data
- * caches, then perform cache-maintenance operations in software.
+ * Disable data caching and handle the stack's cache maintenance.
*
- * This also calls prepare_cpu_pwr_dwn() to initiate power down
- * sequence, but that function will return with data caches disabled.
- * We must ensure that the stack memory is flushed out to memory before
- * we start popping from it again.
+ * If the core can't automatically exit coherency, the cpu driver needs
+ * to flush caches and exit coherency. We can't do this with data caches
+ * enabled. The cpu driver will decide which caches to flush based on
+ * the power level.
+ *
+ * If automatic coherency management is possible, we can keep data
+ * caches on until the very end and let hardware do cache maintenance.
*/
- psci_do_pwrdown_cache_maintenance(power_level);
+ psci_do_pwrdown_cache_maintenance();
#endif
+ /* Initiate the power down sequence by calling into the cpu driver. */
+ prepare_cpu_pwr_dwn(power_level);
+
#if ENABLE_RUNTIME_INSTRUMENTATION
PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
RT_INSTR_EXIT_CFLUSH,
@@ -1230,6 +1299,9 @@
}
#endif /* ERRATA_SME_POWER_DOWN */
+ /* ensure write buffer empty */
+ dsbsy();
+
/*
* Execute a wfi which, in most cases, will allow the power controller
* to physically power down this cpu. Under some circumstances that may
@@ -1237,7 +1309,7 @@
* power down.
*/
for (int i = 0; i < 32; i++)
- psci_power_down_wfi();
+ wfi();
/* Wake up wasn't transient. System is probably in a bad state. */
ERROR("Could not power off CPU.\n");
@@ -1251,31 +1323,30 @@
void psci_pwrdown_cpu_end_wakeup(unsigned int power_level)
{
+ /* ensure write buffer empty */
+ dsbsy();
+
/*
- * Usually, will be terminal. In some circumstances the powerdown will
- * be denied and we'll need to unwind
+ * Turn the core off. Usually, will be terminal. In some circumstances
+ * the powerdown will be denied and we'll need to unwind.
*/
- psci_power_down_wfi();
+ wfi();
/*
* Waking up does not require hardware-assisted coherency, but that is
- * the case for every core that can wake up. Untangling the cache
- * coherency code from powerdown is a non-trivial effort which isn't
- * needed for our purposes.
+ * the case for every core that can wake up. Can either happen because
+ * of errata or pabandon.
*/
-#if !FEAT_PABANDON
- ERROR("Systems without FEAT_PABANDON shouldn't wake up.\n");
+#if !defined(__aarch64__) || !HW_ASSISTED_COHERENCY
+ ERROR("AArch32 systems shouldn't wake up.\n");
panic();
-#else /* FEAT_PABANDON */
-
+#endif
/*
* Begin unwinding. Everything can be shared with CPU_ON and co later,
* except the CPU specific bit. Cores that have hardware-assisted
- * coherency don't have much to do so just calling the hook again is
- * the simplest way to achieve this
+ * coherency should be able to handle this.
*/
- prepare_cpu_pwr_dwn(power_level);
-#endif /* FEAT_PABANDON */
+ prepare_cpu_pwr_up(power_level);
}
/*******************************************************************************
@@ -1371,3 +1442,30 @@
return true;
}
+
+/*******************************************************************************
+ * Safely counts the number of CPUs in the system that are currently in the ON
+ * or ON_PENDING state.
+ *
+ * This function acquires and releases the necessary power domain locks to
+ * ensure consistency of the CPU state information.
+ *
+ * @param this_core The index of the current core making the query.
+ *
+ * @return The number of CPUs currently in AFF_STATE_ON or AFF_STATE_ON_PENDING.
+ ******************************************************************************/
+unsigned int psci_num_cpus_running_on_safe(unsigned int this_core)
+{
+ unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
+ unsigned int no_of_cpus;
+
+ psci_get_parent_pwr_domain_nodes(this_core, PLAT_MAX_PWR_LVL, parent_nodes);
+
+ psci_acquire_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes);
+
+ no_of_cpus = psci_num_cpus_running();
+
+ psci_release_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes);
+
+ return no_of_cpus;
+}
diff --git a/lib/psci/psci_lib.mk b/lib/psci/psci_lib.mk
index 527ad3a..e1dbec2 100644
--- a/lib/psci/psci_lib.mk
+++ b/lib/psci/psci_lib.mk
@@ -1,11 +1,10 @@
#
-# Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
PSCI_LIB_SOURCES := lib/el3_runtime/cpu_data_array.c \
- lib/el3_runtime/${ARCH}/cpu_data.S \
lib/el3_runtime/${ARCH}/context_mgmt.c \
lib/cpus/${ARCH}/cpu_helpers.S \
lib/cpus/errata_report.c \
diff --git a/lib/psci/psci_main.c b/lib/psci/psci_main.c
index f126f49..308c6f9 100644
--- a/lib/psci/psci_main.c
+++ b/lib/psci/psci_main.c
@@ -64,9 +64,6 @@
psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
plat_local_state_t cpu_pd_state;
unsigned int cpu_idx = plat_my_core_pos();
-#if PSCI_OS_INIT_MODE
- plat_local_state_t prev[PLAT_MAX_PWR_LVL];
-#endif
#if ERRATA_SME_POWER_DOWN
/*
@@ -103,7 +100,7 @@
panic();
}
- /* Fast path for CPU standby.*/
+ /* Fast path for local CPU standby, won't interact with higher power levels. */
if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) {
if (psci_plat_pm_ops->cpu_standby == NULL) {
return PSCI_E_INVALID_PARAMS;
@@ -116,18 +113,6 @@
cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL];
psci_set_cpu_local_state(cpu_pd_state);
-#if PSCI_OS_INIT_MODE
- /*
- * If in OS-initiated mode, save a copy of the previous
- * requested local power states and update the new requested
- * local power states for this CPU.
- */
- if (psci_suspend_mode == OS_INIT) {
- psci_update_req_local_pwr_states(target_pwrlvl, cpu_idx,
- &state_info, prev);
- }
-#endif
-
#if ENABLE_PSCI_STAT
plat_psci_stat_accounting_start(&state_info);
#endif
@@ -143,16 +128,6 @@
/* Upon exit from standby, set the state back to RUN. */
psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
-#if PSCI_OS_INIT_MODE
- /*
- * If in OS-initiated mode, restore the previous requested
- * local power states for this CPU.
- */
- if (psci_suspend_mode == OS_INIT) {
- psci_restore_req_local_pwr_states(cpu_idx, prev);
- }
-#endif
-
#if ENABLE_RUNTIME_INSTRUMENTATION
PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
RT_INSTR_EXIT_HW_LOW_PWR,
@@ -300,7 +275,7 @@
flush_cpu_data_by_index(target_idx,
psci_svc_cpu_data.aff_info_state);
- return psci_get_aff_info_state_by_idx(target_idx);
+ return (int)psci_get_aff_info_state_by_idx(target_idx);
}
int psci_migrate(u_register_t target_cpu)
@@ -356,8 +331,9 @@
* psci_spd_migrate_info() returns.
*/
rc = psci_spd_migrate_info(&resident_cpu_mpidr);
- if ((rc != PSCI_TOS_NOT_UP_MIG_CAP) && (rc != PSCI_TOS_UP_MIG_CAP))
+ if ((rc != PSCI_TOS_NOT_UP_MIG_CAP) && (rc != PSCI_TOS_UP_MIG_CAP)) {
return (u_register_t)(register_t) PSCI_E_INVALID_PARAMS;
+ }
return resident_cpu_mpidr;
}
@@ -368,12 +344,14 @@
int rc;
/* Validate target_cpu */
- if (!is_valid_mpidr(target_cpu))
+ if (!is_valid_mpidr(target_cpu)) {
return PSCI_E_INVALID_PARAMS;
+ }
/* Validate power_level against PLAT_MAX_PWR_LVL */
- if (power_level > PLAT_MAX_PWR_LVL)
+ if (power_level > PLAT_MAX_PWR_LVL) {
return PSCI_E_INVALID_PARAMS;
+ }
/*
* Dispatch this call to platform to query power controller, and pass on
diff --git a/lib/psci/psci_mem_protect.c b/lib/psci/psci_mem_protect.c
index 385dcd2..68ad705 100644
--- a/lib/psci/psci_mem_protect.c
+++ b/lib/psci/psci_mem_protect.c
@@ -18,10 +18,12 @@
assert(psci_plat_pm_ops->read_mem_protect != NULL);
assert(psci_plat_pm_ops->write_mem_protect != NULL);
- if (psci_plat_pm_ops->read_mem_protect(&val) < 0)
+ if (psci_plat_pm_ops->read_mem_protect(&val) < 0) {
return (u_register_t) PSCI_E_NOT_SUPPORTED;
- if (psci_plat_pm_ops->write_mem_protect(enable) < 0)
+ }
+ if (psci_plat_pm_ops->write_mem_protect(enable) < 0) {
return (u_register_t) PSCI_E_NOT_SUPPORTED;
+ }
return (val != 0) ? 1U : 0U;
}
@@ -32,8 +34,9 @@
assert(psci_plat_pm_ops->mem_protect_chk != NULL);
- if ((length == 0U) || check_uptr_overflow(base, length - 1U))
+ if ((length == 0U) || check_uptr_overflow(base, length - 1U)) {
return (u_register_t) PSCI_E_DENIED;
+ }
ret = psci_plat_pm_ops->mem_protect_chk(base, length);
return (ret < 0) ?
diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h
index f3f5a5c..446f23d 100644
--- a/lib/psci/psci_private.h
+++ b/lib/psci/psci_private.h
@@ -323,13 +323,6 @@
bool psci_is_last_on_cpu(unsigned int my_idx);
int psci_spd_migrate_info(u_register_t *mpidr);
-/*
- * CPU power down is directly called only when HW_ASSISTED_COHERENCY is
- * available. Otherwise, this needs post-call stack maintenance, which is
- * handled in assembly.
- */
-void prepare_cpu_pwr_dwn(unsigned int power_level);
-
/* This function applies various CPU errata during power down. */
void apply_cpu_pwr_dwn_errata(void);
@@ -348,10 +341,13 @@
psci_power_state_t *state_info,
unsigned int is_power_down_state);
-void psci_cpu_suspend_to_powerdown_finish(unsigned int cpu_idx, unsigned int max_off_lvl, const psci_power_state_t *state_info);
+void psci_cpu_suspend_to_powerdown_finish(unsigned int cpu_idx,
+ unsigned int max_off_lvl,
+ const psci_power_state_t *state_info,
+ bool abandon);
/* Private exported functions from psci_helpers.S */
-void psci_do_pwrdown_cache_maintenance(unsigned int pwr_level);
+void psci_do_pwrdown_cache_maintenance(void);
void psci_do_pwrup_cache_maintenance(void);
/* Private exported functions from psci_system_off.c */
diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c
index 0863a82..44c9bdb 100644
--- a/lib/psci/psci_setup.c
+++ b/lib/psci/psci_setup.c
@@ -63,8 +63,7 @@
/* Initialize with an invalid mpidr */
psci_cpu_pd_nodes[node_idx].mpidr = PSCI_INVALID_MPIDR;
- svc_cpu_data =
- &(_cpu_data_by_index(node_idx)->psci_svc_cpu_data);
+ svc_cpu_data = &get_cpu_data_by_index(node_idx, psci_svc_cpu_data);
/* Set the Affinity Info for the cores as OFF */
svc_cpu_data->aff_info_state = AFF_STATE_OFF;
diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c
index 73b9a67..c04c547 100644
--- a/lib/psci/psci_suspend.c
+++ b/lib/psci/psci_suspend.c
@@ -184,17 +184,6 @@
#endif
if (is_power_down_state != 0U) {
- /*
- * WHen CTX_INCLUDE_EL2_REGS is usnet, we're probably runnig
- * with some SPD that assumes the core is going off so it
- * doesn't bother saving NS's context. Do that here until we
- * figure out a way to make this coherent.
- */
-#if FEAT_PABANDON
-#if !CTX_INCLUDE_EL2_REGS
- cm_el1_sysregs_context_save(NON_SECURE);
-#endif
-#endif
max_off_lvl = psci_find_max_off_lvl(state_info);
psci_suspend_to_pwrdown_start(idx, end_pwrlvl, end_pwrlvl, state_info);
}
@@ -274,13 +263,7 @@
* the system back to a usable state.
*/
if (is_power_down_state != 0U) {
-#if FEAT_PABANDON
- psci_cpu_suspend_to_powerdown_finish(idx, max_off_lvl, state_info);
-
-#if !CTX_INCLUDE_EL2_REGS
- cm_el1_sysregs_context_restore(NON_SECURE);
-#endif
-#endif
+ psci_cpu_suspend_to_powerdown_finish(idx, max_off_lvl, state_info, true);
} else {
psci_cpu_suspend_to_standby_finish(end_pwrlvl, state_info);
}
@@ -307,7 +290,7 @@
* are called by the common finisher routine in psci_common.c. The `state_info`
* is the psci_power_state from which this CPU has woken up from.
******************************************************************************/
-void psci_cpu_suspend_to_powerdown_finish(unsigned int cpu_idx, unsigned int max_off_lvl, const psci_power_state_t *state_info)
+void psci_cpu_suspend_to_powerdown_finish(unsigned int cpu_idx, unsigned int max_off_lvl, const psci_power_state_t *state_info, bool abandon)
{
unsigned int counter_freq;
@@ -335,9 +318,11 @@
gic_cpuif_enable(cpu_idx);
#endif /* USE_GIC_DRIVER */
- /* Re-init the cntfrq_el0 register */
- counter_freq = plat_get_syscnt_freq2();
- write_cntfrq_el0(counter_freq);
+ if (!abandon) {
+ /* Re-init the cntfrq_el0 register */
+ counter_freq = plat_get_syscnt_freq2();
+ write_cntfrq_el0(counter_freq);
+ }
/*
* Call the cpu suspend finish handler registered by the Secure Payload
@@ -345,7 +330,7 @@
* error, it's expected to assert within
*/
if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_suspend_finish != NULL)) {
- psci_spd_pm->svc_suspend_finish(max_off_lvl);
+ psci_spd_pm->svc_suspend_finish(max_off_lvl, abandon);
}
/* This loses its meaning when not suspending, reset so it's correct for OFF */
diff --git a/lib/transfer_list/transfer_list.c b/lib/transfer_list/transfer_list.c
deleted file mode 100644
index 4d4a167..0000000
--- a/lib/transfer_list/transfer_list.c
+++ /dev/null
@@ -1,546 +0,0 @@
-/*
- * Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <assert.h>
-#include <inttypes.h>
-#include <string.h>
-
-#include <common/debug.h>
-#include <lib/transfer_list.h>
-#include <lib/utils_def.h>
-
-void transfer_list_dump(struct transfer_list_header *tl)
-{
- struct transfer_list_entry *te = NULL;
- int i = 0;
-
- if (!tl) {
- return;
- }
- INFO("Dump transfer list:\n");
- INFO("signature 0x%x\n", tl->signature);
- INFO("checksum 0x%x\n", tl->checksum);
- INFO("version 0x%x\n", tl->version);
- INFO("hdr_size 0x%x\n", tl->hdr_size);
- INFO("alignment 0x%x\n", tl->alignment);
- INFO("size 0x%x\n", tl->size);
- INFO("max_size 0x%x\n", tl->max_size);
- INFO("flags 0x%x\n", tl->flags);
- while (true) {
- te = transfer_list_next(tl, te);
- if (!te) {
- break;
- }
-
- INFO("Entry %d:\n", i++);
- transfer_entry_dump(te);
- }
-}
-
-void transfer_entry_dump(struct transfer_list_entry *te)
-{
- if (te) {
- INFO("tag_id 0x%x\n", te->tag_id);
- INFO("hdr_size 0x%x\n", te->hdr_size);
- INFO("data_size 0x%x\n", te->data_size);
- INFO("data_addr 0x%lx\n",
- (unsigned long)transfer_list_entry_data(te));
- }
-}
-
-/*******************************************************************************
- * Set the handoff arguments according to the transfer list payload
- * Return pointer to the entry point info if arguments are set properly
- * or NULL if not
- ******************************************************************************/
-entry_point_info_t *
-transfer_list_set_handoff_args(struct transfer_list_header *tl,
- entry_point_info_t *ep_info)
-{
- struct transfer_list_entry *te = NULL;
- void *dt = NULL;
-
- if (!ep_info || !tl || transfer_list_check_header(tl) == TL_OPS_NON) {
- return NULL;
- }
-
- te = transfer_list_find(tl, TL_TAG_FDT);
- dt = transfer_list_entry_data(te);
-
-#ifdef __aarch64__
- if (GET_RW(ep_info->spsr) == MODE_RW_64) {
- ep_info->args.arg0 = (uintptr_t)dt;
- ep_info->args.arg1 = TRANSFER_LIST_HANDOFF_X1_VALUE(REGISTER_CONVENTION_VERSION);
- ep_info->args.arg2 = 0;
- } else
-#endif
- {
- ep_info->args.arg0 = 0;
- ep_info->args.arg1 = TRANSFER_LIST_HANDOFF_R1_VALUE(REGISTER_CONVENTION_VERSION);
- ep_info->args.arg2 = (uintptr_t)dt;
- }
-
- ep_info->args.arg3 = (uintptr_t)tl;
-
- return ep_info;
-}
-
-/*******************************************************************************
- * Creating a transfer list in a reserved memory region specified
- * Compliant to 2.4.5 of Firmware handoff specification (v0.9)
- * Return pointer to the created transfer list or NULL on error
- ******************************************************************************/
-struct transfer_list_header *transfer_list_init(void *addr, size_t max_size)
-{
- struct transfer_list_header *tl = addr;
-
- if (!addr || max_size == 0) {
- return NULL;
- }
-
- if (!is_aligned((uintptr_t)addr, 1 << TRANSFER_LIST_INIT_MAX_ALIGN) ||
- !is_aligned(max_size, 1 << TRANSFER_LIST_INIT_MAX_ALIGN) ||
- max_size < sizeof(*tl)) {
- return NULL;
- }
-
- memset(tl, 0, max_size);
- tl->signature = TRANSFER_LIST_SIGNATURE;
- tl->version = TRANSFER_LIST_VERSION;
- tl->hdr_size = sizeof(*tl);
- tl->alignment = TRANSFER_LIST_INIT_MAX_ALIGN; /* initial max align */
- tl->size = sizeof(*tl); /* initial size is the size of header */
- tl->max_size = max_size;
- tl->flags = TL_FLAGS_HAS_CHECKSUM;
-
- transfer_list_update_checksum(tl);
-
- return tl;
-}
-
-/*******************************************************************************
- * Relocating a transfer list to a reserved memory region specified
- * Compliant to 2.4.6 of Firmware handoff specification (v0.9)
- * Return pointer to the relocated transfer list or NULL on error
- ******************************************************************************/
-struct transfer_list_header *
-transfer_list_relocate(struct transfer_list_header *tl, void *addr,
- size_t max_size)
-{
- uintptr_t new_addr, align_mask, align_off;
- struct transfer_list_header *new_tl;
- uint32_t new_max_size;
-
- if (!tl || !addr || max_size == 0) {
- return NULL;
- }
-
- align_mask = (1 << tl->alignment) - 1;
- align_off = (uintptr_t)tl & align_mask;
- new_addr = ((uintptr_t)addr & ~align_mask) + align_off;
-
- if (new_addr < (uintptr_t)addr) {
- new_addr += (1 << tl->alignment);
- }
-
- new_max_size = max_size - (new_addr - (uintptr_t)addr);
-
- /* the new space is not sufficient for the tl */
- if (tl->size > new_max_size) {
- return NULL;
- }
-
- new_tl = (struct transfer_list_header *)new_addr;
- memmove(new_tl, tl, tl->size);
- new_tl->max_size = new_max_size;
-
- transfer_list_update_checksum(new_tl);
-
- return new_tl;
-}
-
-/*******************************************************************************
- * Verifying the header of a transfer list
- * Compliant to 2.4.1 of Firmware handoff specification (v0.9)
- * Return transfer list operation status code
- ******************************************************************************/
-enum transfer_list_ops
-transfer_list_check_header(const struct transfer_list_header *tl)
-{
- if (!tl) {
- return TL_OPS_NON;
- }
-
- if (tl->signature != TRANSFER_LIST_SIGNATURE) {
- VERBOSE("Bad transfer list signature 0x%x\n", tl->signature);
- return TL_OPS_NON;
- }
-
- if (!tl->max_size) {
- VERBOSE("Bad transfer list max size 0x%x\n", tl->max_size);
- return TL_OPS_NON;
- }
-
- if (tl->size > tl->max_size) {
- VERBOSE("Bad transfer list size 0x%x\n", tl->size);
- return TL_OPS_NON;
- }
-
- if (tl->hdr_size != sizeof(struct transfer_list_header)) {
- VERBOSE("Bad transfer list header size 0x%x\n", tl->hdr_size);
- return TL_OPS_NON;
- }
-
- if (!transfer_list_verify_checksum(tl)) {
- VERBOSE("Bad transfer list checksum 0x%x\n", tl->checksum);
- return TL_OPS_NON;
- }
-
- if (tl->version == 0) {
- VERBOSE("Transfer list version is invalid\n");
- return TL_OPS_NON;
- } else if (tl->version == TRANSFER_LIST_VERSION) {
- INFO("Transfer list version is valid for all operations\n");
- return TL_OPS_ALL;
- } else if (tl->version > TRANSFER_LIST_VERSION) {
- INFO("Transfer list version is valid for read-only\n");
- return TL_OPS_RO;
- }
-
- INFO("Old transfer list version is detected\n");
- return TL_OPS_CUS;
-}
-
-/*******************************************************************************
- * Enumerate the next transfer entry
- * Return pointer to the next transfer entry or NULL on error
- ******************************************************************************/
-struct transfer_list_entry *transfer_list_next(struct transfer_list_header *tl,
- struct transfer_list_entry *last)
-{
- struct transfer_list_entry *te = NULL;
- uintptr_t tl_ev = 0;
- uintptr_t va = 0;
- uintptr_t ev = 0;
- size_t sz = 0;
-
- if (!tl) {
- return NULL;
- }
-
- tl_ev = (uintptr_t)tl + tl->size;
-
- if (last) {
- va = (uintptr_t)last;
- /* check if the total size overflow */
- if (add_overflow(last->hdr_size, last->data_size, &sz)) {
- return NULL;
- }
- /* roundup to the next entry */
- if (add_with_round_up_overflow(va, sz, TRANSFER_LIST_GRANULE,
- &va)) {
- return NULL;
- }
- } else {
- va = (uintptr_t)tl + tl->hdr_size;
- }
-
- te = (struct transfer_list_entry *)va;
-
- if (va + sizeof(*te) > tl_ev || te->hdr_size < sizeof(*te) ||
- add_overflow(te->hdr_size, te->data_size, &sz) ||
- add_overflow(va, sz, &ev) || ev > tl_ev) {
- return NULL;
- }
-
- return te;
-}
-
-/*******************************************************************************
- * Calculate the byte sum of a transfer list
- * Return byte sum of the transfer list
- ******************************************************************************/
-static uint8_t calc_byte_sum(const struct transfer_list_header *tl)
-{
- uint8_t *b = (uint8_t *)tl;
- uint8_t cs = 0;
- size_t n = 0;
-
- for (n = 0; n < tl->size; n++) {
- cs += b[n];
- }
-
- return cs;
-}
-
-/*******************************************************************************
- * Update the checksum of a transfer list
- * Return updated checksum of the transfer list
- ******************************************************************************/
-void transfer_list_update_checksum(struct transfer_list_header *tl)
-{
- uint8_t cs;
-
- if (!tl || !(tl->flags & TL_FLAGS_HAS_CHECKSUM)) {
- return;
- }
-
- cs = calc_byte_sum(tl);
- cs -= tl->checksum;
- cs = 256 - cs;
- tl->checksum = cs;
- assert(transfer_list_verify_checksum(tl));
-}
-
-/*******************************************************************************
- * Verify the checksum of a transfer list
- * Return true if verified or false if not
- ******************************************************************************/
-bool transfer_list_verify_checksum(const struct transfer_list_header *tl)
-{
- if (!tl) {
- return false;
- }
-
- if (!(tl->flags & TL_FLAGS_HAS_CHECKSUM)) {
- return true;
- }
-
- return !calc_byte_sum(tl);
-}
-
-/*******************************************************************************
- * Update the data size of a transfer entry
- * Return true on success or false on error
- ******************************************************************************/
-bool transfer_list_set_data_size(struct transfer_list_header *tl,
- struct transfer_list_entry *te,
- uint32_t new_data_size)
-{
- uintptr_t tl_old_ev, new_ev = 0, old_ev = 0, ru_new_ev;
- struct transfer_list_entry *dummy_te = NULL;
- size_t gap = 0;
- size_t mov_dis = 0;
- size_t sz = 0;
-
- if (!tl || !te) {
- return false;
- }
- tl_old_ev = (uintptr_t)tl + tl->size;
-
- /*
- * calculate the old and new end of TE
- * both must be roundup to align with TRANSFER_LIST_GRANULE
- */
- if (add_overflow(te->hdr_size, te->data_size, &sz) ||
- add_with_round_up_overflow((uintptr_t)te, sz, TRANSFER_LIST_GRANULE,
- &old_ev)) {
- return false;
- }
- if (add_overflow(te->hdr_size, new_data_size, &sz) ||
- add_with_round_up_overflow((uintptr_t)te, sz, TRANSFER_LIST_GRANULE,
- &new_ev)) {
- return false;
- }
-
- if (new_ev > old_ev) {
- /*
- * move distance should be roundup
- * to meet the requirement of TE data max alignment
- * ensure that the increased size doesn't exceed
- * the max size of TL
- */
- mov_dis = new_ev - old_ev;
- if (round_up_overflow(mov_dis, 1 << tl->alignment, &mov_dis) ||
- tl->size + mov_dis > tl->max_size) {
- return false;
- }
- ru_new_ev = old_ev + mov_dis;
- memmove((void *)ru_new_ev, (void *)old_ev, tl_old_ev - old_ev);
- tl->size += mov_dis;
- gap = ru_new_ev - new_ev;
- } else {
- gap = old_ev - new_ev;
- }
-
- if (gap >= sizeof(*dummy_te)) {
- /* create a dummy TE to fill up the gap */
- dummy_te = (struct transfer_list_entry *)new_ev;
- dummy_te->tag_id = TL_TAG_EMPTY;
- dummy_te->hdr_size = sizeof(*dummy_te);
- dummy_te->data_size = gap - sizeof(*dummy_te);
- }
-
- te->data_size = new_data_size;
-
- transfer_list_update_checksum(tl);
- return true;
-}
-
-/*******************************************************************************
- * Remove a specified transfer entry from a transfer list
- * Return true on success or false on error
- ******************************************************************************/
-bool transfer_list_rem(struct transfer_list_header *tl,
- struct transfer_list_entry *te)
-{
- if (!tl || !te || (uintptr_t)te > (uintptr_t)tl + tl->size) {
- return false;
- }
- te->tag_id = TL_TAG_EMPTY;
- transfer_list_update_checksum(tl);
- return true;
-}
-
-/*******************************************************************************
- * Add a new transfer entry into a transfer list
- * Compliant to 2.4.3 of Firmware handoff specification (v0.9)
- * Return pointer to the added transfer entry or NULL on error
- ******************************************************************************/
-struct transfer_list_entry *transfer_list_add(struct transfer_list_header *tl,
- uint32_t tag_id,
- uint32_t data_size,
- const void *data)
-{
- uintptr_t max_tl_ev, tl_ev, ev;
- struct transfer_list_entry *te = NULL;
- uint8_t *te_data = NULL;
- size_t sz = 0;
-
- if (!tl) {
- return NULL;
- }
-
- max_tl_ev = (uintptr_t)tl + tl->max_size;
- tl_ev = (uintptr_t)tl + tl->size;
- ev = tl_ev;
-
- /*
- * skip the step 1 (optional step)
- * new TE will be added into the tail
- */
- if (add_overflow(sizeof(*te), data_size, &sz) ||
- add_with_round_up_overflow(ev, sz, TRANSFER_LIST_GRANULE, &ev) ||
- ev > max_tl_ev) {
- return NULL;
- }
-
- te = (struct transfer_list_entry *)tl_ev;
- te->tag_id = tag_id;
- te->hdr_size = sizeof(*te);
- te->data_size = data_size;
- tl->size += ev - tl_ev;
-
- if (data) {
- /* get TE data pointer */
- te_data = transfer_list_entry_data(te);
- if (!te_data) {
- return NULL;
- }
- memmove(te_data, data, data_size);
- }
-
- transfer_list_update_checksum(tl);
-
- return te;
-}
-
-/*******************************************************************************
- * Add a new transfer entry into a transfer list with specified new data
- * alignment requirement
- * Compliant to 2.4.4 of Firmware handoff specification (v0.9)
- * Return pointer to the added transfer entry or NULL on error
- ******************************************************************************/
-struct transfer_list_entry *
-transfer_list_add_with_align(struct transfer_list_header *tl, uint32_t tag_id,
- uint32_t data_size, const void *data,
- uint8_t alignment)
-{
- struct transfer_list_entry *te = NULL;
- uintptr_t tl_ev, ev, new_tl_ev;
- size_t dummy_te_data_sz = 0;
-
- if (!tl) {
- return NULL;
- }
-
- tl_ev = (uintptr_t)tl + tl->size;
- ev = tl_ev + sizeof(struct transfer_list_entry);
-
- if (!is_aligned(ev, 1 << alignment)) {
- /*
- * TE data address is not aligned to the new alignment
- * fill the gap with an empty TE as a placeholder before
- * adding the desire TE
- */
- new_tl_ev = round_up(ev, 1 << alignment) -
- sizeof(struct transfer_list_entry);
- dummy_te_data_sz =
- new_tl_ev - tl_ev - sizeof(struct transfer_list_entry);
- if (!transfer_list_add(tl, TL_TAG_EMPTY, dummy_te_data_sz,
- NULL)) {
- return NULL;
- }
- }
-
- te = transfer_list_add(tl, tag_id, data_size, data);
-
- if (alignment > tl->alignment) {
- tl->alignment = alignment;
- transfer_list_update_checksum(tl);
- }
-
- return te;
-}
-
-/*******************************************************************************
- * Search for an existing transfer entry with the specified tag id from a
- * transfer list
- * Return pointer to the found transfer entry or NULL on error
- ******************************************************************************/
-struct transfer_list_entry *transfer_list_find(struct transfer_list_header *tl,
- uint32_t tag_id)
-{
- struct transfer_list_entry *te = NULL;
-
- do {
- te = transfer_list_next(tl, te);
- } while (te && (te->tag_id != tag_id));
-
- return te;
-}
-
-/*******************************************************************************
- * Retrieve the data pointer of a specified transfer entry
- * Return pointer to the transfer entry data or NULL on error
- ******************************************************************************/
-void *transfer_list_entry_data(struct transfer_list_entry *entry)
-{
- if (!entry) {
- return NULL;
- }
- return (uint8_t *)entry + entry->hdr_size;
-}
-
-/*******************************************************************************
- * Verifies that the transfer list has not already been initialized, then
- * initializes it at the specified memory location.
- *
- * Return pointer to the transfer list or NULL on error
- * *****************************************************************************/
-struct transfer_list_header *transfer_list_ensure(void *addr, size_t size)
-{
- struct transfer_list_header *tl = NULL;
-
- if (transfer_list_check_header(addr) == TL_OPS_ALL) {
- return (struct transfer_list_header *)addr;
- }
-
- tl = transfer_list_init((void *)addr, size);
-
- return tl;
-}
diff --git a/lib/transfer_list/transfer_list.mk b/lib/transfer_list/transfer_list.mk
index 3ec4df2..91b6b57 100644
--- a/lib/transfer_list/transfer_list.mk
+++ b/lib/transfer_list/transfer_list.mk
@@ -1,21 +1,25 @@
#
-# Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2023-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
ifeq (${TRANSFER_LIST},1)
-ifeq (${ARCH},aarch32)
-$(eval $(call add_define,TRANSFER_LIST_AARCH32))
-endif
+# Default path if not set externally
+LIBTL_PATH ?= contrib/libtl
-TRANSFER_LIST_SOURCES += $(addprefix lib/transfer_list/, \
- transfer_list.c)
+# Common include paths (always needed)
+INCLUDES += -I$(LIBTL_PATH)/include \
+ -I$(LIBTL_PATH)/include/arm
-BL31_SOURCES += $(TRANSFER_LIST_SOURCES)
-BL2_SOURCES += $(TRANSFER_LIST_SOURCES)
-BL1_SOURCES += $(TRANSFER_LIST_SOURCES)
+LIBTL_SRC_PATH := $(LIBTL_PATH)/src
+
+LIBTL_SRCS := $(addprefix $(LIBTL_SRC_PATH)/, \
+ arm/ep_info.c \
+ generic/logging.c \
+ generic/transfer_list.c)
+
+$(eval $(call MAKE_LIB,tl))
endif # TRANSFER_LIST
-
diff --git a/lib/xlat_tables_v2/xlat_tables_context.c b/lib/xlat_tables_v2/xlat_tables_context.c
index ae9244a..81e53ee 100644
--- a/lib/xlat_tables_v2/xlat_tables_context.c
+++ b/lib/xlat_tables_v2/xlat_tables_context.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -112,7 +112,7 @@
int xlat_get_mem_attributes(uintptr_t base_va, uint32_t *attr)
{
- return xlat_get_mem_attributes_ctx(&tf_xlat_ctx, base_va, attr);
+ return xlat_get_mem_attributes_ctx(&tf_xlat_ctx, base_va, attr, NULL);
}
int xlat_change_mem_attributes(uintptr_t base_va, size_t size, uint32_t attr)
diff --git a/lib/xlat_tables_v2/xlat_tables_utils.c b/lib/xlat_tables_v2/xlat_tables_utils.c
index a3b913c..94b3347 100644
--- a/lib/xlat_tables_v2/xlat_tables_utils.c
+++ b/lib/xlat_tables_v2/xlat_tables_utils.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -487,10 +487,10 @@
int xlat_get_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va,
- uint32_t *attr)
+ uint32_t *attr, unsigned int *table_level)
{
return xlat_get_mem_attributes_internal(ctx, base_va, attr,
- NULL, NULL, NULL);
+ NULL, NULL, table_level);
}
diff --git a/make_helpers/arch_features.mk b/make_helpers/arch_features.mk
index 1561a59..8bcf866 100644
--- a/make_helpers/arch_features.mk
+++ b/make_helpers/arch_features.mk
@@ -58,11 +58,6 @@
armv8-5-a-feats += ${armv8-4-a-feats}
FEAT_LIST := ${armv8-5-a-feats}
-# Enable Memory tagging, Branch Target Identification for aarch64 only.
-ifeq ($(ARCH), aarch64)
- mem_tag_arch_support ?= yes
-endif #(ARCH=aarch64)
-
endif
# Enable the features which are mandatory from ARCH version 8.6 and upwards.
@@ -433,9 +428,15 @@
# Flag to enable access to Arm v9.3 FEAT_D128 extension
ENABLE_FEAT_D128 ?= 0
+# Flag to enable access to GICv5 CPU interface extension (FEAT_GCIE)
+ENABLE_FEAT_GCIE ?= 0
+
#----
#9.4
#----
# Flag to enable access to Guarded Control Stack (FEAT_GCS).
ENABLE_FEAT_GCS ?= 0
+
+# Flag to enable Fine Grained Write Traps (FEAT_FGWTE3) for EL3.
+ENABLE_FEAT_FGWTE3 ?= 0
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk
index aa16751..19c3faa 100644
--- a/make_helpers/build_macros.mk
+++ b/make_helpers/build_macros.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -284,6 +284,49 @@
MAKE_DEP = -Wp,-MD,$1 -MT $2 -MP
+# MAKE_TOOL_C builds a C source file and generates the dependency file
+# $(1) = output directory
+# $(2) = source file (%.c)
+# $(3) = lowercase name of the tool
+# $(4) = uppercase name of the tool
+define MAKE_TOOL_C
+
+$(eval SRC := $(2))
+$(eval OBJ := $(patsubst %.c,$(1)/$(3)/%.o,$(SRC)))
+$(eval DEP := $(patsubst %.o,%.d,$(OBJ)))
+
+$(eval TOOL_DEFINES := $($(4)_DEFINES))
+$(eval TOOL_INCLUDE_DIRS := $($(4)_INCLUDE_DIRS))
+$(eval TOOL_CPPFLAGS := $($(4)_CPPFLAGS) $(addprefix -D,$(TOOL_DEFINES)) $(addprefix -I,$(TOOL_INCLUDE_DIRS)))
+$(eval TOOL_CFLAGS := $($(4)_CFLAGS))
+
+$(OBJ): $(SRC) $(filter-out %.d,$(MAKEFILE_LIST)) | $$$$(@D)/
+ $$(s)echo " HOSTCC $$<"
+ $$(q)$(host-cc) $$(HOSTCCFLAGS) $(TOOL_CPPFLAGS) $(TOOL_CFLAGS) $(call MAKE_DEP,$(DEP),$(OBJ)) -c $$< -o $$@
+
+-include $(DEP)
+
+endef
+
+# MAKE_TOOL
+# $(1) = output directory
+# $(2) = lowercase name of the tool
+# $(3) = uppercase name of the tool
+define MAKE_TOOL
+$(eval SRCS := $($(3)_SOURCES))
+$(eval OBJS := $(patsubst %.c,$(1)/$(2)/%.o,$(SRCS)))
+$(eval DST := $(1)/$(2)/$(2)$(.exe))
+$(eval $(foreach src,$(SRCS),$(call MAKE_TOOL_C,$(1),$(src),$(2),$(3))))
+
+$(DST): $(OBJS) $(filter-out %.d,$(MAKEFILE_LIST))
+ $$(s)echo " HOSTLD $$@"
+ $$(q)$(host-cc) $${OBJS} -o $$@ $($(3)_LDFLAGS)
+ $$(s)echo
+ $$(s)echo "Built $$@ successfully"
+ $$(s)echo
+
+all: $(DST)
+endef
# MAKE_C_LIB builds a C source file and generates the dependency file
# $(1) = output directory
@@ -297,7 +340,7 @@
$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $$$$(@D)/
$$(s)echo " CC $$<"
- $$(q)$($(ARCH)-cc) $$($(LIB)_CFLAGS) $$(TF_CFLAGS) $$(CFLAGS) $(call MAKE_DEP,$(DEP),$(OBJ)) -c $$< -o $$@
+ $$(q)$($(ARCH)-cc) $$($(LIB)_CFLAGS) $$(TF_CFLAGS) $(call MAKE_DEP,$(DEP),$(OBJ)) -c $$< -o $$@
-include $(DEP)
@@ -314,7 +357,7 @@
$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $$$$(@D)/
$$(s)echo " AS $$<"
- $$(q)$($(ARCH)-as) -x assembler-with-cpp $$(TF_CFLAGS_$(ARCH)) $$(ASFLAGS) $(call MAKE_DEP,$(DEP),$(OBJ)) -c $$< -o $$@
+ $$(q)$($(ARCH)-as) -x assembler-with-cpp $$(TF_CFLAGS) $$(ASFLAGS) $(call MAKE_DEP,$(DEP),$(OBJ)) -c $$< -o $$@
-include $(DEP)
@@ -331,14 +374,14 @@
$(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2))))
$(eval DEP := $(patsubst %.o,%.d,$(OBJ)))
-$(eval BL_DEFINES := IMAGE_$(4) $($(4)_DEFINES) $(PLAT_BL_COMMON_DEFINES))
-$(eval BL_INCLUDE_DIRS := $($(4)_INCLUDE_DIRS) $(PLAT_BL_COMMON_INCLUDE_DIRS))
-$(eval BL_CPPFLAGS := $($(4)_CPPFLAGS) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)) $(PLAT_BL_COMMON_CPPFLAGS))
-$(eval BL_CFLAGS := $($(4)_CFLAGS) $(PLAT_BL_COMMON_CFLAGS))
+$(eval BL_DEFINES := IMAGE_$(4) $($(4)_DEFINES))
+$(eval BL_INCLUDE_DIRS := $($(4)_INCLUDE_DIRS))
+$(eval BL_CPPFLAGS := $($(4)_CPPFLAGS) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)))
+$(eval BL_CFLAGS := $($(4)_CFLAGS))
$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $$$$(@D)/
$$(s)echo " CC $$<"
- $$(q)$($(ARCH)-cc) $$(LTO_CFLAGS) $$(TF_CFLAGS) $$(CFLAGS) $(BL_CPPFLAGS) $(BL_CFLAGS) $(call MAKE_DEP,$(DEP),$(OBJ)) -c $$< -o $$@
+ $$(q)$($(ARCH)-cc) $$(LTO_CFLAGS) $$(TF_CFLAGS) $(BL_CPPFLAGS) $(BL_CFLAGS) $(call MAKE_DEP,$(DEP),$(OBJ)) -c $$< -o $$@
-include $(DEP)
@@ -355,19 +398,33 @@
$(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2))))
$(eval DEP := $(patsubst %.o,%.d,$(OBJ)))
-$(eval BL_DEFINES := IMAGE_$(4) $($(4)_DEFINES) $(PLAT_BL_COMMON_DEFINES))
-$(eval BL_INCLUDE_DIRS := $($(4)_INCLUDE_DIRS) $(PLAT_BL_COMMON_INCLUDE_DIRS))
-$(eval BL_CPPFLAGS := $($(4)_CPPFLAGS) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)) $(PLAT_BL_COMMON_CPPFLAGS))
-$(eval BL_ASFLAGS := $($(4)_ASFLAGS) $(PLAT_BL_COMMON_ASFLAGS))
+$(eval BL_DEFINES := IMAGE_$(4) $($(4)_DEFINES))
+$(eval BL_INCLUDE_DIRS := $($(4)_INCLUDE_DIRS))
+$(eval BL_CPPFLAGS := $($(4)_CPPFLAGS) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)))
+$(eval BL_ASFLAGS := $($(4)_ASFLAGS))
$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $$$$(@D)/
$$(s)echo " AS $$<"
- $$(q)$($(ARCH)-as) -x assembler-with-cpp $$(TF_CFLAGS_$(ARCH)) $$(ASFLAGS) $(BL_CPPFLAGS) $(BL_ASFLAGS) $(call MAKE_DEP,$(DEP),$(OBJ)) -c $$< -o $$@
+ $$(q)$($(ARCH)-as) -x assembler-with-cpp $$(TF_CFLAGS) $$(ASFLAGS) $(BL_CPPFLAGS) $(BL_ASFLAGS) $(call MAKE_DEP,$(DEP),$(OBJ)) -c $$< -o $$@
-include $(DEP)
endef
+# MAKE_PRE run the C preprocessor on a file
+# $(1) = output file
+# $(2) = list of input files
+# $(3) = dep file
+# $(4) = list of rule-specific flags to pass
+define MAKE_PRE
+$(eval OUT := $(1))
+$(eval SRC := $(2))
+$(eval DEP := $(3))
+$(eval CUSTOM_FLAGS := $(4))
+$(OUT): $(SRC) $(filter-out %.d,$(MAKEFILE_LIST)) | $$$$(@D)/
+ $$(s)echo " CPP $$<"
+ $$(q)$($(ARCH)-cpp) -E -P -x assembler-with-cpp $$(TF_CFLAGS) $(CUSTOM_FLAGS) $(call MAKE_DEP,$(DEP),$(OUT)) -o $$@ $$<
+endef
# MAKE_LD generate the linker script using the C preprocessor
# $(1) = output linker script
@@ -378,14 +435,12 @@
$(eval DEP := $(1).d)
-$(eval BL_DEFINES := IMAGE_$(4) $($(4)_DEFINES) $(PLAT_BL_COMMON_DEFINES))
-$(eval BL_INCLUDE_DIRS := $($(4)_INCLUDE_DIRS) $(PLAT_BL_COMMON_INCLUDE_DIRS))
-$(eval BL_CPPFLAGS := $($(4)_CPPFLAGS) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)) $(PLAT_BL_COMMON_CPPFLAGS))
+$(eval BL_DEFINES := IMAGE_$(4) $($(4)_DEFINES))
+$(eval BL_INCLUDE_DIRS := $($(4)_INCLUDE_DIRS))
+$(eval BL_CPPFLAGS := $($(4)_CPPFLAGS) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)))
+$(eval FLAGS := -D__LINKER__ $(BL_CPPFLAGS))
-$(1): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $$$$(@D)/
- $$(s)echo " PP $$<"
- $$(q)$($(ARCH)-cpp) -E $$(CPPFLAGS) $(BL_CPPFLAGS) $(TF_CFLAGS_$(ARCH)) -P -x assembler-with-cpp -D__LINKER__ $(call MAKE_DEP,$(DEP),$1) -o $$@ $$<
-
+$(eval $(call MAKE_PRE,$(1),$(2),$(DEP),$(FLAGS)))
-include $(DEP)
endef
@@ -596,10 +651,7 @@
# Dependencies of the DT compilation on its pre-compiled DTS
$(eval DTBDEP := $(patsubst %.dtb,%.d,$(DOBJ)))
-$(DPRE): $(2) | $$$$(@D)/
- $$(s)echo " CPP $$<"
- $(eval DTBS := $(addprefix $(1)/,$(call SOURCES_TO_DTBS,$(2))))
- $$(q)$($(ARCH)-cpp) -E $$(TF_CFLAGS_$(ARCH)) $$(DTC_CPPFLAGS) -MT $(DTBS) -MMD -MF $(DTSDEP) -o $(DPRE) $$<
+$(eval $(call MAKE_PRE,$(DPRE),$(2),$(DTSDEP),$(DTC_CPPFLAGS)))
$(DOBJ): $(DPRE) $(filter-out %.d,$(MAKEFILE_LIST)) | $$$$(@D)/
$$(s)echo " DTC $$<"
diff --git a/make_helpers/cflags.mk b/make_helpers/cflags.mk
new file mode 100644
index 0000000..e237c51
--- /dev/null
+++ b/make_helpers/cflags.mk
@@ -0,0 +1,300 @@
+#
+# Copyright (c) 2025, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+GCC_V_OUTPUT := $(if $($(ARCH)-cc),$(shell $($(ARCH)-cc) -v 2>&1))
+PIE_FOUND := $(findstring --enable-default-pie,${GCC_V_OUTPUT})
+
+################################################################################
+# Compiler Configuration based on ARCH_MAJOR and ARCH_MINOR flags
+################################################################################
+ifeq (${ARM_ARCH_MAJOR},7)
+ target32-directive = -target arm-none-eabi
+# Will set march-directive from platform configuration
+else
+ target32-directive = -target armv8a-none-eabi
+endif #(ARM_ARCH_MAJOR)
+
+ifneq ($(filter %-clang,$($(ARCH)-cc-id)),)
+ ifeq ($($(ARCH)-cc-id),arm-clang)
+ TF_CFLAGS_aarch32 := -target arm-arm-none-eabi
+ TF_CFLAGS_aarch64 := -target aarch64-arm-none-eabi
+ else
+ TF_CFLAGS_aarch32 = $(target32-directive)
+ TF_CFLAGS_aarch64 := -target aarch64-elf
+ endif
+endif #(clang)
+
+# Process Debug flag
+ifneq (${DEBUG}, 0)
+ TF_CFLAGS += -g -gdwarf-4
+endif #(Debug)
+
+ifeq (${AARCH32_INSTRUCTION_SET},A32)
+ TF_CFLAGS_aarch32 += -marm
+else ifeq (${AARCH32_INSTRUCTION_SET},T32)
+ TF_CFLAGS_aarch32 += -mthumb
+endif #(AARCH32_INSTRUCTION_SET)
+
+TF_CFLAGS_aarch32 += -mno-unaligned-access
+TF_CFLAGS_aarch64 += -mgeneral-regs-only -mstrict-align
+
+##############################################################################
+# WARNINGS Configuration
+###############################################################################
+# General warnings
+WARNINGS := -Wall -Wmissing-include-dirs -Wunused \
+ -Wdisabled-optimization -Wvla -Wshadow \
+ -Wredundant-decls
+# stricter warnings
+WARNINGS += -Wextra -Wno-trigraphs
+# too verbose for generic build
+WARNINGS += -Wno-missing-field-initializers \
+ -Wno-type-limits -Wno-sign-compare \
+# on clang this flag gets reset if -Wextra is set after it. No difference on gcc
+WARNINGS += -Wno-unused-parameter
+
+# Additional warnings
+# Level 1 - infrequent warnings we should have none of
+# full -Wextra
+WARNING1 += -Wsign-compare
+WARNING1 += -Wtype-limits
+WARNING1 += -Wmissing-field-initializers
+
+# Level 2 - problematic warnings that we want
+# zlib, compiler-rt, coreboot, and mbdedtls blow up with these
+# TODO: disable just for them and move into default build
+WARNING2 += -Wold-style-definition
+WARNING2 += -Wmissing-prototypes
+WARNING2 += -Wmissing-format-attribute
+# TF-A aims to comply with this eventually. Effort too large at present
+WARNING2 += -Wundef
+# currently very involved and many platforms set this off
+WARNING2 += -Wunused-const-variable=2
+
+# Level 3 - very pedantic, frequently ignored
+WARNING3 := -Wbad-function-cast
+WARNING3 += -Waggregate-return
+WARNING3 += -Wnested-externs
+WARNING3 += -Wcast-align
+WARNING3 += -Wcast-qual
+WARNING3 += -Wconversion
+WARNING3 += -Wpacked
+WARNING3 += -Wpointer-arith
+WARNING3 += -Wswitch-default
+
+ifeq (${W},1)
+ WARNINGS += $(WARNING1)
+else ifeq (${W},2)
+ WARNINGS += $(WARNING1) $(WARNING2)
+else ifeq (${W},3)
+ WARNINGS += $(WARNING1) $(WARNING2) $(WARNING3)
+endif #(W)
+
+ifneq (${E},0)
+ ERRORS := -Werror
+endif #(E)
+
+# Compiler specific warnings
+ifeq ($(filter %-clang,$($(ARCH)-cc-id)),)
+# not using clang
+# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105523
+TF_CFLAGS_MIN_PAGE_SIZE := $(call cc_option, --param=min-pagesize=0)
+TF_CFLAGS += $(TF_CFLAGS_MIN_PAGE_SIZE)
+
+ifeq ($(HARDEN_SLS), 1)
+ TF_CFLAGS_MHARDEN_SLS := $(call cc_option, -mharden-sls=all)
+ TF_CFLAGS_aarch64 += $(TF_CFLAGS_MHARDEN_SLS)
+endif
+
+WARNINGS += -Wunused-but-set-variable -Wmaybe-uninitialized \
+ -Wpacked-bitfield-compat -Wshift-overflow=2 \
+ -Wlogical-op
+
+else
+# using clang
+WARNINGS += -Wshift-overflow -Wshift-sign-overflow \
+ -Wlogical-op-parentheses
+endif #(Clang Warning)
+
+CPPFLAGS = ${DEFINES} ${INCLUDES} ${MBEDTLS_INC} -nostdinc \
+ $(ERRORS) $(WARNINGS)
+
+
+TF_CFLAGS += -ffunction-sections -fdata-sections \
+ -ffreestanding -fno-common \
+ -Os -std=gnu99
+
+ifneq (${BP_OPTION},none)
+ TF_CFLAGS_aarch64 += -mbranch-protection=${BP_OPTION}
+endif #(BP_OPTION)
+
+ifeq (${SANITIZE_UB},on)
+ TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover
+endif #(${SANITIZE_UB},on)
+
+ifeq (${SANITIZE_UB},trap)
+ TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover \
+ -fsanitize-undefined-trap-on-error
+endif #(${SANITIZE_UB},trap)
+
+ifeq ($($(ARCH)-cc-id),gnu-gcc)
+ # Enable LTO only for aarch64
+ LTO_CFLAGS = $(if $(filter-out 0,$(ENABLE_LTO)),-flto)
+endif #(gnu-gcc)
+
+ifeq (${ERROR_DEPRECATED},0)
+# Check if deprecated declarations and cpp warnings should be treated as error or not.
+ifneq ($(filter %-clang,$($(ARCH)-cc-id)),)
+ CPPFLAGS += -Wno-error=deprecated-declarations
+else
+ CPPFLAGS += -Wno-error=deprecated-declarations -Wno-error=cpp
+endif
+endif #(!ERROR_DEPRECATED)
+
+################################################################################
+# Platform specific Makefile might provide us ARCH_MAJOR/MINOR use that to come
+# up with appropriate march values for compiler.
+################################################################################
+include ${MAKE_HELPERS_DIRECTORY}march.mk
+ifeq (${ARM_ARCH_MAJOR},7)
+include make_helpers/armv7-a-cpus.mk
+endif
+
+TF_CFLAGS += $(march-directive)
+
+ifneq ($(PIE_FOUND),)
+ TF_CFLAGS += -fno-PIE
+endif
+
+TF_CFLAGS += $(CPPFLAGS) $(TF_CFLAGS_$(ARCH))
+TF_CFLAGS += $(CFLAGS)
+ASFLAGS += -Wa,--fatal-warnings
+TF_LDFLAGS += -z noexecstack
+
+# LD = armlink
+ifeq ($($(ARCH)-ld-id),arm-link)
+ TF_LDFLAGS += --diag_error=warning --lto_level=O1
+ TF_LDFLAGS += --remove --info=unused,unusedsymbols
+ TF_LDFLAGS += $(TF_LDFLAGS_$(ARCH))
+
+# LD = gcc (used when GCC LTO is enabled)
+else ifeq ($($(ARCH)-ld-id),gnu-gcc)
+ # Pass ld options with Wl or Xlinker switches
+ TF_LDFLAGS += $(call ld_option,-Xlinker --no-warn-rwx-segments)
+ TF_LDFLAGS += -Wl,--fatal-warnings -O1
+ TF_LDFLAGS += -Wl,--gc-sections
+
+ TF_LDFLAGS += -Wl,-z,common-page-size=4096 #Configure page size constants
+ TF_LDFLAGS += -Wl,-z,max-page-size=4096
+ TF_LDFLAGS += -Wl,--build-id=none
+
+ ifeq ($(ENABLE_LTO),1)
+ TF_LDFLAGS += -flto -fuse-linker-plugin
+ TF_LDFLAGS += -flto-partition=one
+ endif #(ENABLE_LTO)
+
+# GCC automatically adds fix-cortex-a53-843419 flag when used to link
+# which breaks some builds, so disable if errata fix is not explicitly enabled
+ ifeq (${ARCH},aarch64)
+ ifneq (${ERRATA_A53_843419},1)
+ TF_LDFLAGS += -mno-fix-cortex-a53-843419
+ endif
+ endif
+ TF_LDFLAGS += -nostdlib
+ TF_LDFLAGS += $(subst --,-Xlinker --,$(TF_LDFLAGS_$(ARCH)))
+
+# LD = gcc-ld (ld) or llvm-ld (ld.lld) or other
+else
+# With ld.bfd version 2.39 and newer new warnings are added. Skip those since we
+# are not loaded by a elf loader.
+ TF_LDFLAGS += $(call ld_option, --no-warn-rwx-segments)
+ TF_LDFLAGS += -O1
+ TF_LDFLAGS += --gc-sections
+
+ TF_LDFLAGS += -z common-page-size=4096 # Configure page size constants
+ TF_LDFLAGS += -z max-page-size=4096
+ TF_LDFLAGS += --build-id=none
+
+# ld.lld doesn't recognize the errata flags,
+# therefore don't add those in that case.
+# ld.lld reports section type mismatch warnings,
+# therefore don't add --fatal-warnings to it.
+ ifneq ($($(ARCH)-ld-id),llvm-lld)
+ TF_LDFLAGS += $(TF_LDFLAGS_$(ARCH)) --fatal-warnings
+ endif
+
+endif #(LD = armlink)
+
+ifneq ($(PIE_FOUND),)
+ifeq ($($(ARCH)-ld-id),gnu-gcc)
+ TF_LDFLAGS += -no-pie
+endif
+endif #(PIE_FOUND)
+
+ifeq ($($(ARCH)-ld-id),gnu-gcc)
+ PIE_LDFLAGS += -Wl,-pie -Wl,--no-dynamic-linker
+else
+ PIE_LDFLAGS += -pie --no-dynamic-linker
+endif
+
+ifeq ($(ENABLE_PIE),1)
+ ifeq ($(RESET_TO_BL2),1)
+ ifneq ($(BL2_IN_XIP_MEM),1)
+ BL2_CPPFLAGS += -fpie
+ BL2_CFLAGS += -fpie
+ BL2_LDFLAGS += $(PIE_LDFLAGS)
+ endif #(BL2_IN_XIP_MEM)
+ endif #(RESET_TO_BL2)
+ BL31_CPPFLAGS += -fpie
+ BL31_CFLAGS += -fpie
+ BL31_LDFLAGS += $(PIE_LDFLAGS)
+
+ BL32_CPPFLAGS += -fpie
+ BL32_CFLAGS += -fpie
+ BL32_LDFLAGS += $(PIE_LDFLAGS)
+endif #(ENABLE_PIE)
+
+BL1_CPPFLAGS += -DREPORT_ERRATA=${DEBUG}
+BL31_CPPFLAGS += -DREPORT_ERRATA=${DEBUG}
+BL32_CPPFLAGS += -DREPORT_ERRATA=${DEBUG}
+
+BL1_CPPFLAGS += -DIMAGE_AT_EL3
+ifeq ($(RESET_TO_BL2),1)
+ BL2_CPPFLAGS += -DIMAGE_AT_EL3
+else
+ BL2_CPPFLAGS += -DIMAGE_AT_EL1
+endif #(RESET_TO_BL2)
+
+ifeq (${ARCH},aarch64)
+ BL2U_CPPFLAGS += -DIMAGE_AT_EL1
+ BL31_CPPFLAGS += -DIMAGE_AT_EL3
+ BL32_CPPFLAGS += -DIMAGE_AT_EL1
+else
+ BL32_CPPFLAGS += -DIMAGE_AT_EL3
+endif
+
+ifeq (${SPD},spmd)
+ ifeq ($(findstring optee_sp,$(ARM_SPMC_MANIFEST_DTS)),optee_sp)
+ DTC_CPPFLAGS += -DOPTEE_SP_FW_CONFIG
+ endif
+
+ ifeq ($(findstring trusty_sp,$(ARM_SPMC_MANIFEST_DTS)),trusty_sp)
+ DTC_CPPFLAGS += -DTRUSTY_SP_FW_CONFIG
+ endif
+
+ ifeq ($(TS_SP_FW_CONFIG),1)
+ DTC_CPPFLAGS += -DTS_SP_FW_CONFIG
+ endif
+
+ ifneq ($(ARM_BL2_SP_LIST_DTS),)
+ DTC_CPPFLAGS += -DARM_BL2_SP_LIST_DTS=$(ARM_BL2_SP_LIST_DTS)
+ endif
+endif
+
+
+DTC_FLAGS += -I dts -O dtb
+DTC_CPPFLAGS += -Ifdts -undef
+
diff --git a/make_helpers/constraints.mk b/make_helpers/constraints.mk
new file mode 100644
index 0000000..594d77b
--- /dev/null
+++ b/make_helpers/constraints.mk
@@ -0,0 +1,388 @@
+#
+# Copyright (c) 2025, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifneq ($(AARCH32_INSTRUCTION_SET),$(filter $(AARCH32_INSTRUCTION_SET),A32 T32))
+ $(error Error: Unknown AArch32 instruction set ${AARCH32_INSTRUCTION_SET})
+endif
+
+ifneq (${ENABLE_RME},0)
+ ifneq (${ARCH},aarch64)
+ $(error ENABLE_RME requires AArch64)
+ endif
+ ifeq ($(SPMC_AT_EL3),1)
+ $(error SPMC_AT_EL3 and ENABLE_RME cannot both be enabled.)
+ endif
+
+ ifneq (${SPD}, none)
+ ifneq (${SPD}, spmd)
+ $(error ENABLE_RME is incompatible with SPD=${SPD}. Use SPD=spmd)
+ endif
+ endif
+endif
+
+ifeq (${CTX_INCLUDE_EL2_REGS}, 1)
+ ifeq (${SPD},none)
+ ifeq (${ENABLE_RME},0)
+ $(error CTX_INCLUDE_EL2_REGS is available only when SPD \
+ or RME is enabled)
+ endif
+ endif
+endif
+
+################################################################################
+# Verify FEAT_RME, FEAT_SCTLR2 and FEAT_TCR2 are enabled if FEAT_MEC is enabled.
+################################################################################
+
+ifneq (${ENABLE_FEAT_MEC},0)
+ ifeq (${ENABLE_RME},0)
+ $(error FEAT_RME must be enabled when FEAT_MEC is enabled.)
+ endif
+ ifeq (${ENABLE_FEAT_TCR2},0)
+ $(error FEAT_TCR2 must be enabled when FEAT_MEC is enabled.)
+ endif
+ ifeq (${ENABLE_FEAT_SCTLR2},0)
+ $(error FEAT_SCTLR2 must be enabled when FEAT_MEC is enabled.)
+ endif
+endif
+
+# Handle all invalid build configurations with SPMD usage.
+ifeq (${ENABLE_SPMD_LP}, 1)
+ifneq (${SPD},spmd)
+ $(error Error: ENABLE_SPMD_LP requires SPD=spmd.)
+endif
+ifeq ($(SPMC_AT_EL3),1)
+ $(error SPMC at EL3 not supported when enabling SPMD Logical partitions.)
+endif
+endif
+
+ifneq (${SPD},none)
+ifeq (${ARCH},aarch32)
+ $(error "Error: SPD is incompatible with AArch32.")
+endif
+ifdef EL3_PAYLOAD_BASE
+ $(warning "SPD and EL3_PAYLOAD_BASE are incompatible build options.")
+ $(warning "The SPD and its BL32 companion will be present but ignored.")
+endif
+ifeq (${SPD},spmd)
+ifeq ($(SPMD_SPM_AT_SEL2),1)
+ ifeq ($(SPMC_AT_EL3),1)
+ $(error SPM cannot be enabled in both S-EL2 and EL3.)
+ endif
+ ifeq ($(CTX_INCLUDE_SVE_REGS),1)
+ $(error SVE context management not needed with Hafnium SPMC.)
+ endif
+endif
+
+ifeq ($(SPMC_AT_EL3_SEL0_SP),1)
+ ifneq ($(SPMC_AT_EL3),1)
+ $(error SEL0 SP cannot be enabled without SPMC at EL3)
+ endif
+endif
+endif #(SPD=spmd)
+endif #(SPD!=none)
+
+# USE_DEBUGFS experimental feature recommended only in debug builds
+ifeq (${USE_DEBUGFS},1)
+ ifeq (${DEBUG},1)
+ $(warning DEBUGFS experimental feature is enabled.)
+ else
+ $(warning DEBUGFS experimental, recommended in DEBUG builds ONLY)
+ endif
+endif #(USE_DEBUGFS)
+
+# USE_SPINLOCK_CAS requires AArch64 build
+ifeq (${USE_SPINLOCK_CAS},1)
+ ifneq (${ARCH},aarch64)
+ $(error USE_SPINLOCK_CAS requires AArch64)
+ endif
+endif #(USE_SPINLOCK_CAS)
+
+ifdef EL3_PAYLOAD_BASE
+ ifdef PRELOADED_BL33_BASE
+ $(warning "PRELOADED_BL33_BASE and EL3_PAYLOAD_BASE are \
+ incompatible build options. EL3_PAYLOAD_BASE has priority.")
+ endif
+ ifneq (${GENERATE_COT},0)
+ $(error "GENERATE_COT and EL3_PAYLOAD_BASE are incompatible \
+ build options.")
+ endif
+ ifneq (${TRUSTED_BOARD_BOOT},0)
+ $(error "TRUSTED_BOARD_BOOT and EL3_PAYLOAD_BASE are \
+ incompatible \ build options.")
+ endif
+endif #(EL3_PAYLOAD_BASE)
+
+ifeq (${NEED_BL33},yes)
+ ifdef EL3_PAYLOAD_BASE
+ $(warning "BL33 image is not needed when option \
+ BL33_PAYLOAD_BASE is used and won't be added to the FIP file.")
+ endif
+ ifdef PRELOADED_BL33_BASE
+ $(warning "BL33 image is not needed when option \
+ PRELOADED_BL33_BASE is used and won't be added to the FIP file.")
+ endif
+endif #(NEED_BL33)
+
+# When building for systems with hardware-assisted coherency, there's no need to
+# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
+ifeq ($(HW_ASSISTED_COHERENCY)-$(USE_COHERENT_MEM),1-1)
+ $(error USE_COHERENT_MEM cannot be enabled with HW_ASSISTED_COHERENCY)
+endif
+
+#For now, BL2_IN_XIP_MEM is only supported when RESET_TO_BL2 is 1.
+ifeq ($(RESET_TO_BL2)-$(BL2_IN_XIP_MEM),0-1)
+ $(error "BL2_IN_XIP_MEM is only supported when RESET_TO_BL2 is enabled")
+endif
+
+# RAS_EXTENSION is deprecated, provide alternate build options
+ifeq ($(RAS_EXTENSION),1)
+ $(error "RAS_EXTENSION is now deprecated, please use ENABLE_FEAT_RAS \
+ and HANDLE_EA_EL3_FIRST_NS instead")
+endif
+
+
+# When FAULT_INJECTION_SUPPORT is used, require that FEAT_RAS is enabled
+ifeq ($(FAULT_INJECTION_SUPPORT),1)
+ ifeq ($(ENABLE_FEAT_RAS),0)
+ $(error For FAULT_INJECTION_SUPPORT, ENABLE_FEAT_RAS must not be 0)
+ endif
+endif #(FAULT_INJECTION_SUPPORT)
+
+# DYN_DISABLE_AUTH can be set only when TRUSTED_BOARD_BOOT=1
+ifeq ($(DYN_DISABLE_AUTH), 1)
+ ifeq (${TRUSTED_BOARD_BOOT}, 0)
+ $(error "TRUSTED_BOARD_BOOT must be enabled for DYN_DISABLE_AUTH \
+ to be set.")
+ endif
+endif #(DYN_DISABLE_AUTH)
+
+# SDEI_IN_FCONF is only supported when SDEI_SUPPORT is enabled.
+ifeq ($(SDEI_SUPPORT)-$(SDEI_IN_FCONF),0-1)
+ $(error "SDEI_IN_FCONF is only supported when SDEI_SUPPORT is enabled")
+endif
+
+# If pointer authentication is used in the firmware, make sure that all the
+# registers associated to it are also saved and restored.
+# Not doing it would leak the value of the keys used by EL3 to EL1 and S-EL1.
+ifneq ($(ENABLE_PAUTH),0)
+ ifeq ($(CTX_INCLUDE_PAUTH_REGS),0)
+ $(error Pointer Authentication requires CTX_INCLUDE_PAUTH_REGS to be enabled)
+ endif
+endif #(ENABLE_PAUTH)
+
+ifneq ($(CTX_INCLUDE_PAUTH_REGS),0)
+ ifneq (${ARCH},aarch64)
+ $(error CTX_INCLUDE_PAUTH_REGS requires AArch64)
+ endif
+endif #(CTX_INCLUDE_PAUTH_REGS)
+
+# Check ENABLE_FEAT_PAUTH_LR
+ifneq (${ENABLE_FEAT_PAUTH_LR},0)
+
+# Make sure PAUTH is enabled
+ifeq (${ENABLE_PAUTH},0)
+ $(error Error: PAUTH_LR cannot be used without PAUTH (see BRANCH_PROTECTION))
+endif
+
+# Make sure SCTLR2 is enabled
+ifeq (${ENABLE_FEAT_SCTLR2},0)
+ $(error Error: PAUTH_LR cannot be used without ENABLE_FEAT_SCTLR2)
+endif
+
+# FEAT_PAUTH_LR is only supported in aarch64 state
+ifneq (${ARCH},aarch64)
+ $(error ENABLE_FEAT_PAUTH_LR requires AArch64)
+endif
+
+# Currently, FEAT_PAUTH_LR is only supported by arm/clang compilers
+# TODO implement for GCC when support is added
+ifeq ($($(ARCH)-cc-id),arm-clang)
+ arch-features := $(arch-features)+pauth-lr
+else
+ $(error Error: ENABLE_FEAT_PAUTH_LR not supported for GCC compiler)
+endif
+
+endif # ${ENABLE_FEAT_PAUTH_LR}
+
+ifeq ($(FEATURE_DETECTION),1)
+ $(info FEATURE_DETECTION is an experimental feature)
+endif #(FEATURE_DETECTION)
+
+ifneq ($(ENABLE_SME2_FOR_NS), 0)
+ ifeq (${ENABLE_SME_FOR_NS}, 0)
+ $(warning "ENABLE_SME2_FOR_NS requires ENABLE_SME_FOR_NS also \
+ to be set")
+ $(warning "Forced ENABLE_SME_FOR_NS=1")
+ override ENABLE_SME_FOR_NS := 1
+ endif
+endif #(ENABLE_SME2_FOR_NS)
+
+ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1)
+ ifeq (${ALLOW_RO_XLAT_TABLES}, 1)
+ $(error "ALLOW_RO_XLAT_TABLES requires translation tables \
+ library v2")
+ endif
+endif #(ARM_XLAT_TABLES_LIB_V1)
+
+ifneq (${DECRYPTION_SUPPORT},none)
+ ifeq (${TRUSTED_BOARD_BOOT}, 0)
+ $(error TRUSTED_BOARD_BOOT must be enabled for DECRYPTION_SUPPORT \
+ to be set)
+ endif
+endif #(DECRYPTION_SUPPORT)
+
+# Ensure that no Aarch64-only features are enabled in Aarch32 build
+ifeq (${ARCH},aarch32)
+ ifneq (${ENABLE_LTO},0)
+ $(error "ENABLE_LTO is not supported with ARCH=aarch32")
+ endif
+
+ # SME/SVE only supported on AArch64
+ ifneq (${ENABLE_SME_FOR_NS},0)
+ $(error "ENABLE_SME_FOR_NS cannot be used with ARCH=aarch32")
+ endif
+
+ ifeq (${ENABLE_SVE_FOR_NS},1)
+ # Warning instead of error due to CI dependency on this
+ $(error "ENABLE_SVE_FOR_NS cannot be used with ARCH=aarch32")
+ endif
+
+ # BRBE is not supported in AArch32
+ ifeq (${ENABLE_BRBE_FOR_NS},1)
+ $(error "ENABLE_BRBE_FOR_NS cannot be used with ARCH=aarch32")
+ endif
+
+ # FEAT_RNG_TRAP is not supported in AArch32
+ ifneq (${ENABLE_FEAT_RNG_TRAP},0)
+ $(error "ENABLE_FEAT_RNG_TRAP cannot be used with ARCH=aarch32")
+ endif
+
+ ifneq (${ENABLE_FEAT_FPMR},0)
+ $(error "ENABLE_FEAT_FPMR cannot be used with ARCH=aarch32")
+ endif
+
+ ifeq (${ARCH_FEATURE_AVAILABILITY},1)
+ $(error "ARCH_FEATURE_AVAILABILITY cannot be used with ARCH=aarch32")
+ endif
+ # FEAT_MOPS is only supported on AArch64
+ ifneq (${ENABLE_FEAT_MOPS},0)
+ $(error "ENABLE_FEAT_MOPS cannot be used with ARCH=aarch32")
+ endif
+ ifneq (${ENABLE_FEAT_GCIE},0)
+ $(error "ENABLE_FEAT_GCIE cannot be used with ARCH=aarch32")
+ endif
+endif #(ARCH=aarch32)
+
+ifneq (${ENABLE_FEAT_FPMR},0)
+ ifeq (${ENABLE_FEAT_FGT},0)
+ $(error "ENABLE_FEAT_FPMR requires ENABLE_FEAT_FGT")
+ endif
+ ifeq (${ENABLE_FEAT_HCX},0)
+ $(error "ENABLE_FEAT_FPMR requires ENABLE_FEAT_HCX")
+ endif
+endif #(ENABLE_FEAT_FPMR)
+
+ifneq (${ENABLE_SME_FOR_NS},0)
+ ifeq (${ENABLE_SVE_FOR_NS},0)
+ $(error "ENABLE_SME_FOR_NS requires ENABLE_SVE_FOR_NS")
+ endif
+endif #(ENABLE_SME_FOR_NS)
+
+# Secure SME/SVE requires the non-secure component as well
+ifeq (${ENABLE_SME_FOR_SWD},1)
+ ifeq (${ENABLE_SME_FOR_NS},0)
+ $(error "ENABLE_SME_FOR_SWD requires ENABLE_SME_FOR_NS")
+ endif
+ ifeq (${ENABLE_SVE_FOR_SWD},0)
+ $(error "ENABLE_SME_FOR_SWD requires ENABLE_SVE_FOR_SWD")
+ endif
+endif #(ENABLE_SME_FOR_SWD)
+
+# Enabling SVE for SWD requires enabling SVE for NWD due to ENABLE_FEAT
+# mechanism.
+ifeq (${ENABLE_SVE_FOR_SWD},1)
+ ifeq (${ENABLE_SVE_FOR_NS},0)
+ $(error "ENABLE_SVE_FOR_SWD requires ENABLE_SVE_FOR_NS")
+ endif
+endif
+
+# Enabling FEAT_MOPS requires access to hcrx_el2 registers which is
+# available only when FEAT_HCX is enabled.
+ifneq (${ENABLE_FEAT_MOPS},0)
+ ifeq (${ENABLE_FEAT_HCX},0)
+ $(error "ENABLE_FEAT_MOPS requires ENABLE_FEAT_HCX")
+ endif
+endif
+
+# Enabling SVE for both the worlds typically requires the context
+# management of SVE registers. The only exception being SPMC at S-EL2.
+ifeq (${ENABLE_SVE_FOR_SWD}, 1)
+ ifneq (${ENABLE_SVE_FOR_NS}, 0)
+ ifeq (${CTX_INCLUDE_SVE_REGS}-$(SPMD_SPM_AT_SEL2),0-0)
+ $(warning "ENABLE_SVE_FOR_SWD and ENABLE_SVE_FOR_NS together require CTX_INCLUDE_SVE_REGS")
+ endif
+ endif
+endif
+
+# Enabling SVE in either world while enabling CTX_INCLUDE_FPREGS requires
+# CTX_INCLUDE_SVE_REGS to be enabled due to architectural dependency between FP
+# and SVE registers.
+ifeq (${CTX_INCLUDE_FPREGS}, 1)
+ ifneq (${ENABLE_SVE_FOR_NS},0)
+ ifeq (${CTX_INCLUDE_SVE_REGS},0)
+ # Warning instead of error due to CI dependency on this
+ $(warning "CTX_INCLUDE_FPREGS and ENABLE_SVE_FOR_NS together require CTX_INCLUDE_SVE_REGS")
+ $(warning "Forced ENABLE_SVE_FOR_NS=0")
+ override ENABLE_SVE_FOR_NS := 0
+ endif
+ endif
+endif #(CTX_INCLUDE_FPREGS)
+
+# SVE context management is only required if secure world has access to SVE/FP
+# functionality.
+ifeq (${CTX_INCLUDE_SVE_REGS},1)
+ ifeq (${ENABLE_SVE_FOR_SWD},0)
+ $(error "CTX_INCLUDE_SVE_REGS requires ENABLE_SVE_FOR_SWD to also be enabled")
+ endif
+endif
+
+# SME cannot be used with CTX_INCLUDE_FPREGS since SPM does its own context
+# management including FPU registers.
+ifeq (${CTX_INCLUDE_FPREGS},1)
+ ifneq (${ENABLE_SME_FOR_NS},0)
+ $(error "ENABLE_SME_FOR_NS cannot be used with CTX_INCLUDE_FPREGS")
+ endif
+endif #(CTX_INCLUDE_FPREGS)
+
+ifeq ($(DRTM_SUPPORT),1)
+ $(info DRTM_SUPPORT is an experimental feature)
+endif
+
+ifeq (${HOB_LIST},1)
+ $(warning HOB_LIST is an experimental feature)
+endif
+
+ifeq (${TRANSFER_LIST},1)
+ $(info TRANSFER_LIST is an experimental feature)
+endif
+
+ifeq (${ENABLE_RME},1)
+ ifneq (${SEPARATE_CODE_AND_RODATA},1)
+ $(error `ENABLE_RME=1` requires `SEPARATE_CODE_AND_RODATA=1`)
+ endif
+endif
+
+ifeq ($(PSA_CRYPTO),1)
+ $(info PSA_CRYPTO is an experimental feature)
+endif
+
+ifeq ($(DICE_PROTECTION_ENVIRONMENT),1)
+ $(info DICE_PROTECTION_ENVIRONMENT is an experimental feature)
+endif
+
+ifeq (${LFA_SUPPORT},1)
+ $(warning LFA_SUPPORT is an experimental feature)
+endif #(LFA_SUPPORT)
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index f438a9d..1ddcd6f 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -10,6 +10,9 @@
# poised to handle dependencies, as all build variables would have a default
# value by then.
+# Warning level to give to the compiler
+W := 0
+
# Use T32 by default
AARCH32_INSTRUCTION_SET := T32
@@ -85,9 +88,6 @@
# Enable the Maximum Power Mitigation Mechanism on supporting cores.
ENABLE_MPMM := 0
-# Enable support for powerdown abandons
-FEAT_PABANDON := 0
-
# Flag to Enable Position Independant support (PIE)
ENABLE_PIE := 0
@@ -346,11 +346,6 @@
# CTX_INCLUDE_EL2_REGS.
CTX_INCLUDE_EL2_REGS := 0
-# Enable Memory tag extension which is supported for architecture greater
-# than Armv8.5-A
-# By default it is set to "no"
-SUPPORT_STACK_MEMTAG := no
-
# Select workaround for AT speculative behaviour.
ERRATA_SPECULATIVE_AT := 0
@@ -440,3 +435,9 @@
# This flag is temporary and it is expected once the interface is
# finalized, this flag will be removed.
RMMD_ENABLE_IDE_KEY_PROG := 0
+
+# Live firmware activation support
+LFA_SUPPORT := 0
+
+# Enable support for arm DSU driver.
+USE_DSU_DRIVER := 0
diff --git a/make_helpers/march.mk b/make_helpers/march.mk
index 8e73116..1a6e852 100644
--- a/make_helpers/march.mk
+++ b/make_helpers/march.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+# Copyright (c) 2023-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -82,6 +82,11 @@
march-directive := -march=${provided-march}
+################################################################################
+# Get Architecture Feature Modifiers
+################################################################################
+arch-features = ${ARM_ARCH_FEATURE}
+
# Set the compiler's architecture feature modifiers
ifneq ($(arch-features), none)
# Strip "none+" from arch-features
diff --git a/plat/allwinner/common/sunxi_native_pm.c b/plat/allwinner/common/sunxi_native_pm.c
index 558b0bb..28abd3c 100644
--- a/plat/allwinner/common/sunxi_native_pm.c
+++ b/plat/allwinner/common/sunxi_native_pm.c
@@ -38,7 +38,7 @@
gicv2_cpuif_enable();
}
-static void __dead2 sunxi_system_off(void)
+static void sunxi_system_off(void)
{
gicv2_cpuif_disable();
@@ -48,9 +48,6 @@
/* Turn off all CPUs */
sunxi_cpu_power_off_others();
sunxi_cpu_power_off_self();
- psci_power_down_wfi();
- /* should never reach here */
- panic();
}
static void __dead2 sunxi_system_reset(void)
diff --git a/plat/allwinner/common/sunxi_scpi_pm.c b/plat/allwinner/common/sunxi_scpi_pm.c
index 8870a71..2341c09 100644
--- a/plat/allwinner/common/sunxi_scpi_pm.c
+++ b/plat/allwinner/common/sunxi_scpi_pm.c
@@ -95,7 +95,7 @@
}
}
-static void __dead2 sunxi_system_off(void)
+static void sunxi_system_off(void)
{
uint32_t ret;
@@ -106,13 +106,9 @@
if (ret != SCP_OK) {
ERROR("PSCI: SCPI %s failed: %d\n", "shutdown", ret);
}
-
- psci_power_down_wfi();
- /* should never reach here */
- panic();
}
-static void __dead2 sunxi_system_reset(void)
+static void sunxi_system_reset(void)
{
uint32_t ret;
@@ -123,10 +119,6 @@
if (ret != SCP_OK) {
ERROR("PSCI: SCPI %s failed: %d\n", "reboot", ret);
}
-
- psci_power_down_wfi();
- /* should never reach here */
- panic();
}
static int sunxi_system_reset2(int is_vendor, int reset_type, u_register_t cookie)
@@ -145,14 +137,8 @@
return PSCI_E_INVALID_PARAMS;
}
- psci_power_down_wfi();
- /* should never reach here */
- panic();
-
/*
- * Should not reach here.
- * However sunxi_system_reset2 has to return some value
- * according to PSCI v1.1 spec.
+ * Continue to core powerdown
*/
return PSCI_E_SUCCESS;
}
diff --git a/plat/allwinner/sun50i_h616/sunxi_power.c b/plat/allwinner/sun50i_h616/sunxi_power.c
index cab7e46..b47149f 100644
--- a/plat/allwinner/sun50i_h616/sunxi_power.c
+++ b/plat/allwinner/sun50i_h616/sunxi_power.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited. All rights reserved.
* Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -49,7 +49,7 @@
int axp_read(uint8_t reg)
{
- uint8_t val;
+ uint8_t val = 0;
int ret;
if (is_using_rsb()) {
diff --git a/plat/amd/common/include/plat_xfer_list.h b/plat/amd/common/include/plat_xfer_list.h
index 24a9c0c..1563200 100644
--- a/plat/amd/common/include/plat_xfer_list.h
+++ b/plat/amd/common/include/plat_xfer_list.h
@@ -7,7 +7,7 @@
#ifndef PLAT_XFER_LIST_H
#define PLAT_XFER_LIST_H
-#include <lib/transfer_list.h>
+#include <transfer_list.h>
int32_t transfer_list_populate_ep_info(entry_point_info_t *bl32,
entry_point_info_t *bl33);
diff --git a/plat/amd/common/plat_fdt.c b/plat/amd/common/plat_fdt.c
index e72c0dd..095527d 100644
--- a/plat/amd/common/plat_fdt.c
+++ b/plat/amd/common/plat_fdt.c
@@ -10,10 +10,15 @@
#include <platform_def.h>
#include <plat_fdt.h>
+#ifdef TRANSFER_LIST
#include <plat_xfer_list.h>
+#endif
#define FIT_CONFS_PATH "/configurations"
+static struct reserve_mem_range rsvnodes[MAX_RESERVE_ADDR_INDICES] = {};
+static uint32_t rsv_count;
+
static bool is_fit_image(void *dtb)
{
int64_t confs_noffset = 0;
@@ -70,3 +75,64 @@
return (uintptr_t)dtb;
}
+
+struct reserve_mem_range *get_reserved_entries_fdt(uint32_t *reserve_nodes)
+{
+ struct reserve_mem_range *rsvmr = NULL;
+
+ if ((rsv_count > 0) && (reserve_nodes != NULL)) {
+ rsvmr = &rsvnodes[0];
+ *reserve_nodes = rsv_count;
+ }
+
+ return rsvmr;
+}
+
+/* TODO: Parse TL overlays for updated tf-a and op-tee reserved nodes */
+uint32_t retrieve_reserved_entries(void)
+{
+ uint32_t ret = 1;
+ void *dtb = NULL;
+ int offset, node;
+ uint32_t i = 0;
+ const fdt32_t *reg_prop;
+
+
+ /* Get DT blob address */
+ dtb = (void *)plat_retrieve_dt_addr();
+
+ /* Check if DT is valid */
+ if (is_valid_dtb(dtb) >= 0) {
+ /* Find reserved memory node */
+ offset = fdt_path_offset(dtb, "/reserved-memory");
+ if (offset >= 0) {
+
+ /* Parse subnodes of reserved-memory */
+ fdt_for_each_subnode(node, dtb, offset) {
+ if (fdt_getprop(dtb, node, "no-map", NULL) == NULL) {
+ continue;
+ }
+
+ if (rsv_count == MAX_RESERVE_ADDR_INDICES) {
+ break;
+ }
+
+ reg_prop = fdt_getprop(dtb, node, "reg", NULL);
+ if (reg_prop == NULL) {
+ INFO("No valid reg prop found for subnode\n");
+ continue;
+ }
+
+ rsvnodes[i].base = (((uint64_t)fdt32_to_cpu(reg_prop[0]) << 32) |
+ fdt32_to_cpu(reg_prop[1]));
+ rsvnodes[i].size = (((uint64_t)fdt32_to_cpu(reg_prop[2]) << 32) |
+ fdt32_to_cpu(reg_prop[3]));
+ i++;
+ }
+ ret = 0;
+ rsv_count = i;
+ }
+ }
+
+ return ret;
+}
diff --git a/plat/amd/common/plat_xfer_list.c b/plat/amd/common/plat_xfer_list.c
index 19c882b..d8dc09d 100644
--- a/plat/amd/common/plat_xfer_list.c
+++ b/plat/amd/common/plat_xfer_list.c
@@ -4,11 +4,12 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stddef.h>
-#include <arch_helpers.h>
-#include <common/debug.h>
-#include <lib/transfer_list.h>
+
#include <platform_def.h>
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <transfer_list.h>
static struct transfer_list_header *tl_hdr;
static int32_t tl_ops_holder;
diff --git a/plat/amd/versal2/aarch64/common.c b/plat/amd/versal2/aarch64/common.c
index 8d9e05c..9e52f9d 100644
--- a/plat/amd/versal2/aarch64/common.c
+++ b/plat/amd/versal2/aarch64/common.c
@@ -8,12 +8,12 @@
#include <common/debug.h>
#include <common/runtime_svc.h>
+#include <def.h>
#include <drivers/generic_delay_timer.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
-
-#include <def.h>
+#include <plat_clkfunc.h>
#include <plat_common.h>
#include <plat_ipi.h>
#include <plat_private.h>
@@ -123,7 +123,7 @@
uintptr_t crl_base, iou_scntrs_base, psx_base;
crl_base = CRL;
- iou_scntrs_base = IOU_SCNTRS;
+ iou_scntrs_base = IOU_SCNTRS_BASE;
psx_base = PSX_CRF;
/* Reset for system timestamp generator in FPX */
@@ -143,13 +143,11 @@
mmio_write_32(iou_scntrs_base + IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET,
IOU_SCNTRS_CONTROL_EN);
+ /* set cntfrq_el0 value so that software can discover the frequency of the system counter */
+ set_cnt_freq();
+
generic_delay_timer_init();
/* Configure IPI data */
soc_ipi_config_table_init();
}
-
-uint32_t plat_get_syscnt_freq2(void)
-{
- return cpu_clock;
-}
diff --git a/plat/amd/versal2/bl31_setup.c b/plat/amd/versal2/bl31_setup.c
index 94ace7d..0726c26 100644
--- a/plat/amd/versal2/bl31_setup.c
+++ b/plat/amd/versal2/bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
* Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
@@ -27,7 +27,9 @@
#include <plat_fdt.h>
#include <plat_private.h>
#include <plat_startup.h>
+#if TRANSFER_LIST
#include <plat_xfer_list.h>
+#endif
#include <pm_api_sys.h>
#include <pm_client.h>
@@ -259,6 +261,7 @@
{
uint32_t flags = 0;
int32_t rc;
+ uint32_t rre_ret = 0;
set_interrupt_rm_flag(flags, NON_SECURE);
rc = register_interrupt_type_handler(INTR_TYPE_EL3,
@@ -267,6 +270,13 @@
panic();
}
+ /* Instead of calling for each time fill in structure early. */
+ rre_ret = retrieve_reserved_entries();
+
+ if (rre_ret != 0) {
+ INFO("Runtime FDT reserve node retreival failed");
+ }
+
console_switch_state(CONSOLE_FLAG_RUNTIME);
}
diff --git a/plat/amd/versal2/include/def.h b/plat/amd/versal2/include/def.h
index 9bef9d0..3b42b15 100644
--- a/plat/amd/versal2/include/def.h
+++ b/plat/amd/versal2/include/def.h
@@ -126,8 +126,14 @@
#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U)
-/* IOU SCNTRS */
-#define IOU_SCNTRS U(0xEC920000)
+#define FPD_SYSTMR_CTRL_BASE U(0xEC920000)
+
+/*
+ * Note: There is no IOU_SCNTRS in Versal Gen 2, the equivalent
+ * functionality is provided through FPD_SYSTMR_CTRL. For compatibility
+ * with existing code, maintain the same macro names.
+ */
+#define IOU_SCNTRS_BASE FPD_SYSTMR_CTRL_BASE
#define IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0)
#define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20)
diff --git a/plat/amd/versal2/plat_psci_pm.c b/plat/amd/versal2/plat_psci_pm.c
index 3cc6b95..97a5997 100644
--- a/plat/amd/versal2/plat_psci_pm.c
+++ b/plat/amd/versal2/plat_psci_pm.c
@@ -14,6 +14,7 @@
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <plat_arm.h>
+#include <plat_fdt.h>
#include "def.h"
#include <ipi.h>
@@ -110,7 +111,7 @@
* Send the system reset request to the firmware if power down request
* is not received from firmware.
*/
- if (pwrdwn_req_received == false) {
+ if (pm_pwrdwn_req_status() == false) {
/*
* TODO: shutdown scope for this reset needs be revised once
* we have a clearer understanding of the overall reset scoping
@@ -186,6 +187,34 @@
return;
}
+static int32_t versal2_validate_ns_entrypoint(uint64_t ns_entrypoint)
+{
+ int32_t ret = PSCI_E_SUCCESS;
+ struct reserve_mem_range *rmr;
+ uint32_t index = 0, counter = 0;
+
+ rmr = get_reserved_entries_fdt(&counter);
+
+ VERBOSE("Validate ns_entry point %lx\n", ns_entrypoint);
+
+ if (counter != 0) {
+ while (index < counter) {
+ if ((ns_entrypoint >= rmr[index].base) &&
+ (ns_entrypoint <= rmr[index].size)) {
+ ret = PSCI_E_INVALID_ADDRESS;
+ break;
+ }
+ index++;
+ }
+ } else {
+ if ((ns_entrypoint >= BL31_BASE) && (ns_entrypoint <= BL31_LIMIT)) {
+ ret = PSCI_E_INVALID_ADDRESS;
+ }
+ }
+
+ return ret;
+}
+
static void versal2_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
(void)target_state;
@@ -312,6 +341,7 @@
.pwr_domain_suspend_finish = versal2_pwr_domain_suspend_finish,
.system_off = versal2_system_off,
.system_reset = versal2_system_reset,
+ .validate_ns_entrypoint = versal2_validate_ns_entrypoint,
.validate_power_state = versal2_validate_power_state,
.get_sys_suspend_power_state = versal2_get_sys_suspend_power_state,
};
diff --git a/plat/amd/versal2/platform.mk b/plat/amd/versal2/platform.mk
index 283ad42..475e8ff 100644
--- a/plat/amd/versal2/platform.mk
+++ b/plat/amd/versal2/platform.mk
@@ -116,6 +116,7 @@
drivers/delay_timer/generic_delay_timer.c \
${GICV3_SOURCES} \
drivers/arm/pl011/aarch64/pl011_console.S \
+ plat/xilinx/common/plat_clkfunc.c \
plat/common/aarch64/crash_console_helpers.S \
plat/arm/common/arm_common.c \
plat/common/plat_gicv3.c \
diff --git a/plat/amd/versal2/pm_service/pm_client.c b/plat/amd/versal2/pm_service/pm_client.c
index 8d6b9b1..67099a6 100644
--- a/plat/amd/versal2/pm_service/pm_client.c
+++ b/plat/amd/versal2/pm_service/pm_client.c
@@ -336,6 +336,23 @@
uintptr_t val;
if (cpuid != (uint32_t) UNDEFINED_CPUID) {
+ /*
+ * Get the core index and use it to calculate offset for
+ * disabling power down and wakeup interrupts.
+ * i.e., Convert cpu-id to core_index with the following mapping:
+ * cpu-id -> core_index
+ * 0 -> 0
+ * 1 -> 1
+ * 2 -> 4
+ * 3 -> 5
+ * 4 -> 8
+ * 5 -> 9
+ * 6 -> 12
+ * 7 -> 13
+ * to match with register database.
+ */
+ uint32_t core_index = cpuid + ((cpuid / 2U) * 2U);
+
pm_client_lock_get();
/* Clear powerdown request */
@@ -346,10 +363,10 @@
isb();
/* Disabled power down interrupt */
- mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(cpuid),
+ mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(core_index),
APU_PCIL_CORE_X_IDS_POWER_MASK);
/* Disable wake interrupt */
- mmio_write_32(APU_PCIL_CORE_X_IDS_WAKE_REG(cpuid),
+ mmio_write_32(APU_PCIL_CORE_X_IDS_WAKE_REG(core_index),
APU_PCIL_CORE_X_IDS_WAKE_MASK);
pm_client_lock_release();
diff --git a/plat/amd/versal2/pm_service/pm_svc_main.c b/plat/amd/versal2/pm_service/pm_svc_main.c
index 10d2ed2..ae26d6b 100644
--- a/plat/amd/versal2/pm_service/pm_svc_main.c
+++ b/plat/amd/versal2/pm_service/pm_svc_main.c
@@ -68,7 +68,12 @@
/* pm_up = true - UP, pm_up = false - DOWN */
static bool pm_up;
static uint32_t sgi = (uint32_t)INVALID_SGI;
-bool pwrdwn_req_received;
+static bool pwrdwn_req_received;
+
+bool pm_pwrdwn_req_status(void)
+{
+ return pwrdwn_req_received;
+}
static void notify_os(void)
{
@@ -163,7 +168,8 @@
break;
case PM_NOTIFY_CB:
if (sgi != INVALID_SGI) {
- if (payload[2] == EVENT_CPU_PWRDWN) {
+ if ((payload[2] == EVENT_CPU_PWRDWN) &&
+ (NODECLASS(payload[1]) == (uint32_t)XPM_NODECLASS_DEVICE)) {
if (pwrdwn_req_received) {
pwrdwn_req_received = false;
request_cpu_pwrdwn();
@@ -182,7 +188,8 @@
*/
}
notify_os();
- } else if (payload[2] == EVENT_CPU_PWRDWN) {
+ } else if ((payload[2] == EVENT_CPU_PWRDWN) &&
+ (NODECLASS(payload[1]) == (uint32_t)XPM_NODECLASS_DEVICE)) {
request_cpu_pwrdwn();
(void)psci_cpu_off();
} else {
@@ -267,6 +274,7 @@
pm_ipi_init(primary_proc);
pm_up = true;
+ pwrdwn_req_received = false;
/* register SGI handler for CPU power down request */
ret = request_intr_type_el3(CPU_PWR_DOWN_REQ_INTR, cpu_pwrdwn_req_handler);
diff --git a/plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c b/plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c
new file mode 100644
index 0000000..7cb88ed
--- /dev/null
+++ b/plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <common/fdt_wrappers.h>
+#include <drivers/arm/gicv3.h>
+
+#include <fconf_hw_config_getter.h>
+
+struct gicv3_config_t gicv3_config;
+
+int fconf_populate_gicv3_config(uintptr_t config)
+{
+ int err;
+ int node;
+ uintptr_t addr;
+
+ /* Necessary to work with libfdt APIs */
+ const void *hw_config_dtb = (const void *)config;
+
+ /*
+ * Find the offset of the node containing "arm,gic-v3" compatible property.
+ * Populating fconf strucutures dynamically is not supported for legacy
+ * systems which use GICv2 IP. Simply skip extracting GIC properties.
+ */
+ node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,gic-v3");
+ if (node < 0) {
+ WARN("FCONF: Unable to locate node with arm,gic-v3 compatible property\n");
+ return 0;
+ }
+ /* The GICv3 DT binding holds at least two address/size pairs,
+ * the first describing the distributor, the second the redistributors.
+ * See: bindings/interrupt-controller/arm,gic-v3.yaml
+ */
+ err = fdt_get_reg_props_by_index(hw_config_dtb, node, 0, &addr, NULL);
+ if (err < 0) {
+ ERROR("FCONF: Failed to read GICD reg property of GIC node\n");
+ return err;
+ }
+ gicv3_config.gicd_base = addr;
+
+ err = fdt_get_reg_props_by_index(hw_config_dtb, node, 1, &addr, NULL);
+ if (err < 0) {
+ ERROR("FCONF: Failed to read GICR reg property of GIC node\n");
+ } else {
+ gicv3_config.gicr_base = addr;
+ }
+
+ return err;
+}
+FCONF_REGISTER_POPULATOR(HW_CONFIG, gicv3_config, fconf_populate_gicv3_config);
diff --git a/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c b/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
index fb7f48e..abc78ce 100644
--- a/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
+++ b/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
@@ -14,7 +14,6 @@
#include <libfdt.h>
#include <plat/common/platform.h>
-struct gicv3_config_t gicv3_config;
struct hw_topology_t soc_topology;
struct uart_serial_config_t uart_serial_config;
struct cpu_timer_t cpu_timer;
@@ -32,45 +31,6 @@
#define ILLEGAL_ADDR ULL(~0)
-int fconf_populate_gicv3_config(uintptr_t config)
-{
- int err;
- int node;
- uintptr_t addr;
-
- /* Necessary to work with libfdt APIs */
- const void *hw_config_dtb = (const void *)config;
-
- /*
- * Find the offset of the node containing "arm,gic-v3" compatible property.
- * Populating fconf strucutures dynamically is not supported for legacy
- * systems which use GICv2 IP. Simply skip extracting GIC properties.
- */
- node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,gic-v3");
- if (node < 0) {
- WARN("FCONF: Unable to locate node with arm,gic-v3 compatible property\n");
- return 0;
- }
- /* The GICv3 DT binding holds at least two address/size pairs,
- * the first describing the distributor, the second the redistributors.
- * See: bindings/interrupt-controller/arm,gic-v3.yaml
- */
- err = fdt_get_reg_props_by_index(hw_config_dtb, node, 0, &addr, NULL);
- if (err < 0) {
- ERROR("FCONF: Failed to read GICD reg property of GIC node\n");
- return err;
- }
- gicv3_config.gicd_base = addr;
-
- err = fdt_get_reg_props_by_index(hw_config_dtb, node, 1, &addr, NULL);
- if (err < 0) {
- ERROR("FCONF: Failed to read GICR reg property of GIC node\n");
- } else {
- gicv3_config.gicr_base = addr;
- }
-
- return err;
-}
int fconf_populate_topology(uintptr_t config)
{
@@ -447,7 +407,6 @@
return 0;
}
-FCONF_REGISTER_POPULATOR(HW_CONFIG, gicv3_config, fconf_populate_gicv3_config);
FCONF_REGISTER_POPULATOR(HW_CONFIG, topology, fconf_populate_topology);
FCONF_REGISTER_POPULATOR(HW_CONFIG, uart_config, fconf_populate_uart_config);
FCONF_REGISTER_POPULATOR(HW_CONFIG, cpu_timer, fconf_populate_cpu_timer);
diff --git a/plat/arm/board/fvp/fdts/fvp_cot_desc.dtsi b/plat/arm/board/fvp/fdts/fvp_cot_desc.dtsi
index 9c8328b..27e32b1 100644
--- a/plat/arm/board/fvp/fdts/fvp_cot_desc.dtsi
+++ b/plat/arm/board/fvp/fdts/fvp_cot_desc.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,10 +7,10 @@
#if COT_DESC_IN_DTB
#if defined(ARM_COT_cca)
- #include "cca_cot_descriptors.dtsi"
+ #include "cca_cot_descriptors.dts"
#elif defined(ARM_COT_dualroot)
- #include "dualroot_cot_descriptors.dtsi"
+ #include "dualroot_cot_descriptors.dts"
#elif defined(ARM_COT_tbbr)
- #include "tbbr_cot_descriptors.dtsi"
+ #include "tbbr_cot_descriptors.dts"
#endif
#endif
diff --git a/plat/arm/board/fvp/fdts/fvp_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
index a11c1de..fd6cf78 100644
--- a/plat/arm/board/fvp/fdts/fvp_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
@@ -27,7 +27,7 @@
load-address = <0x0 0x07f00000>;
max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
id = <HW_CONFIG_ID>;
- secondary-load-address = <0x0 0x82000000>;
+ secondary-load-address = <0x0 FVP_HW_CONFIG_ADDR>;
};
/*
diff --git a/plat/arm/board/fvp/fvp_bl2_setup.c b/plat/arm/board/fvp/fvp_bl2_setup.c
index 989f058..852a1e7 100644
--- a/plat/arm/board/fvp/fvp_bl2_setup.c
+++ b/plat/arm/board/fvp/fvp_bl2_setup.c
@@ -12,7 +12,9 @@
#include <fvp_pas_def.h>
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
-#include <lib/transfer_list.h>
+#if TRANSFER_LIST
+#include <transfer_list.h>
+#endif
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 9d0463d..7f20967 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -68,6 +68,10 @@
#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
DEVICE1_SIZE, \
+ MT_DEVICE | MT_RW | EL3_PAS)
+
+#define MAP_CCN MAP_REGION_FLAT(CCN_BASE, \
+ CCN_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#if FVP_GICR_REGION_PROTECTION
@@ -115,7 +119,7 @@
V2M_MAP_IOFPGA,
MAP_DEVICE0,
#if FVP_INTERCONNECT_DRIVER == FVP_CCN
- MAP_DEVICE1,
+ MAP_CCN,
#endif
#if TRUSTED_BOARD_BOOT
/* To access the Root of Trust Public Key registers. */
@@ -133,7 +137,7 @@
V2M_MAP_IOFPGA,
MAP_DEVICE0,
#if FVP_INTERCONNECT_DRIVER == FVP_CCN
- MAP_DEVICE1,
+ MAP_CCN,
#endif
ARM_MAP_NS_DRAM1,
#ifdef __aarch64__
@@ -208,6 +212,9 @@
MAP_GICD_MEM,
MAP_GICR_MEM,
#else
+#if FVP_INTERCONNECT_DRIVER == FVP_CCN
+ MAP_CCN,
+#endif
MAP_DEVICE1,
#endif /* FVP_GICR_REGION_PROTECTION */
ARM_V2M_MAP_MEM_PROTECT,
@@ -254,6 +261,9 @@
#endif
V2M_MAP_IOFPGA,
MAP_DEVICE0,
+#if FVP_INTERCONNECT_DRIVER == FVP_CCN
+ MAP_CCN,
+#endif
MAP_DEVICE1,
{0}
};
@@ -572,6 +582,13 @@
V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK);
}
+/* Get SoC name */
+int32_t plat_get_soc_name(char *soc_name)
+{
+ snprintf(soc_name, SMCCC_SOC_NAME_LEN, "Arm Platform Revision %d",
+ plat_get_soc_revision());
+ return SMC_ARCH_CALL_SUCCESS;
+}
#if ENABLE_RME
/* BDF mappings for RP0 RC0 */
@@ -773,8 +790,8 @@
/* Set number of consoles */
num_consoles = FVP_RMM_CONSOLE_COUNT;
- /* Set number of device non-coherent address ranges based on DT */
- num_ncoh_regions = FCONF_GET_PROPERTY(hw_config, pci_props, num_ncoh_regions);
+ /* Set number of device non-coherent address ranges for FVP RevC */
+ num_ncoh_regions = 2;
/* Set number of SMMUs */
num_smmus = FVP_RMM_SMMU_COUNT;
@@ -907,6 +924,11 @@
(void)memset((void *)ncoh_region_ptr, 0,
sizeof(struct memory_bank) * num_ncoh_regions);
+ /* Set number of device non-coherent address ranges based on DT */
+ num_ncoh_regions = FCONF_GET_PROPERTY(hw_config, pci_props, num_ncoh_regions);
+ /* At least 1 PCIe region need to be described in DT */
+ assert((num_ncoh_regions > 0) && (num_ncoh_regions <= 2));
+
for (unsigned long i = 0UL; i < num_ncoh_regions; i++) {
ncoh_region_ptr[i].base =
FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].base);
@@ -914,6 +936,17 @@
FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].size);
}
+ /*
+ * Workaround if the DT does not specify the 2nd PCIe region. This code can be
+ * removed when upstream DT is updated to have 2nd PCIe region.
+ */
+ if (num_ncoh_regions == 1) {
+ num_ncoh_regions++;
+ /* Add 3GB of 2nd PCIe region */
+ ncoh_region_ptr[1].base = 0x4000000000;
+ ncoh_region_ptr[1].size = 0xc0000000;
+ }
+
/* Update checksum */
checksum += checksum_calc((uint64_t *)ncoh_region_ptr,
sizeof(struct memory_bank) * num_ncoh_regions);
diff --git a/plat/arm/board/fvp/fvp_cpu_pwr.c b/plat/arm/board/fvp/fvp_cpu_pwr.c
index f2771c2..a294534 100644
--- a/plat/arm/board/fvp/fvp_cpu_pwr.c
+++ b/plat/arm/board/fvp/fvp_cpu_pwr.c
@@ -20,8 +20,8 @@
bool check_cpupwrctrl_el1_is_available(void)
{
- /* Poupulate list of CPU midr that doesn't support CPUPWRCTL_EL1 */
- const unsigned int midr_no_cpupwrctl[] = {
+ /* Populate list of CPU midr that doesn't support CPUPWRCTL_EL1 */
+ static const unsigned int midr_no_cpupwrctl[] = {
BASE_AEM_MIDR,
CORTEX_A35_MIDR,
CORTEX_A53_MIDR,
diff --git a/plat/arm/board/fvp/fvp_def.h b/plat/arm/board/fvp/fvp_def.h
index 831eb35..d87be31 100644
--- a/plat/arm/board/fvp/fvp_def.h
+++ b/plat/arm/board/fvp/fvp_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -53,12 +53,12 @@
* In case of FVP models with CCN, the CCN register space overlaps into
* the NSRAM area.
*/
-#if FVP_INTERCONNECT_DRIVER == FVP_CCN
-#define DEVICE1_BASE UL(0x2e000000)
-#define DEVICE1_SIZE UL(0x1A00000)
-#else
-#define DEVICE1_BASE BASE_GICD_BASE
+#define CCN_BASE UL(0x2e000000)
+#define CCN_SIZE UL(0x1000000)
+/* TODO: this covers gicv5, but macros should be adjusted */
+#if USE_GIC_DRIVER != 5
+#define DEVICE1_BASE BASE_GICD_BASE
#if GIC_ENABLE_V4_EXTN
/* GICv4 mapping: GICD + CORE_COUNT * 256KB */
#define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \
@@ -68,10 +68,11 @@
#define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \
(PLATFORM_CORE_COUNT * 0x20000))
#endif /* GIC_ENABLE_V4_EXTN */
-
-#define NSRAM_BASE UL(0x2e000000)
-#define NSRAM_SIZE UL(0x10000)
+#else
+#define DEVICE1_BASE BASE_IWB_BASE
+#define DEVICE1_SIZE ((BASE_IRS_BASE - BASE_IWB_BASE) + SZ_64K)
#endif
+
/* Devices in the second GB */
#define DEVICE2_BASE UL(0x7fe00000)
#define DEVICE2_SIZE UL(0x00200000)
@@ -124,6 +125,15 @@
#define FVP_SP810_CTRL_TIM2_OV BIT_32(20)
#define FVP_SP810_CTRL_TIM3_OV BIT_32(22)
+
+#define NSRAM_BASE UL(0x2e000000)
+#define NSRAM_SIZE UL(0x10000)
+/*
+ * In case of FVP models with CCN, the CCN register space overlaps into
+ * the NSRAM area.
+ */
+#define CCN_BASE UL(0x2e000000)
+#define CCN_SIZE UL(0x1000000)
/*******************************************************************************
* GIC & interrupt handling related constants
******************************************************************************/
@@ -138,6 +148,9 @@
#define BASE_GICD_SIZE UL(0x10000)
#define BASE_GICR_BASE UL(0x2f100000)
+#define BASE_IWB_BASE UL(0x2f000000)
+#define BASE_IRS_BASE UL(0x2f1c0000)
+
#if GIC_ENABLE_V4_EXTN
/* GICv4 redistributor size: 256KB */
#define BASE_GICR_SIZE UL(0x40000)
diff --git a/plat/arm/board/fvp/fvp_gicv5.c b/plat/arm/board/fvp/fvp_gicv5.c
new file mode 100644
index 0000000..73bd9c5
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_gicv5.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/gicv5.h>
+#include <platform_def.h>
+
+/* wire 26 is the timer interrupt. Will be assigned NS by default */
+struct gicv5_wire_props irs0_spis[] = {
+};
+
+struct gicv5_wire_props iwb0_wires[] = {
+};
+
+struct gicv5_irs irss[] = {{
+ .el3_config_frame = BASE_IRS_BASE,
+ .spis = irs0_spis,
+ .num_spis = ARRAY_SIZE(irs0_spis),
+}};
+
+struct gicv5_iwb iwbs[] = {{
+ .config_frame = BASE_IWB_BASE,
+ .wires = iwb0_wires,
+ .num_wires = ARRAY_SIZE(iwb0_wires)
+}};
+
+const struct gicv5_driver_data plat_gicv5_driver_data = {
+ .irss = irss,
+ .iwbs = iwbs,
+ .num_irss = ARRAY_SIZE(irss),
+ .num_iwbs = ARRAY_SIZE(iwbs)
+};
+
+void fvp_gic_driver_pre_init(void)
+{
+}
+
+void fvp_pcpu_init(void)
+{
+}
diff --git a/plat/arm/board/fvp/fvp_lfa.c b/plat/arm/board/fvp/fvp_lfa.c
new file mode 100644
index 0000000..3c5321d
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_lfa.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <plat/common/platform.h>
+#include <services/bl31_lfa.h>
+#include <services/rmmd_rmm_lfa.h>
+#include <tools_share/firmware_image_package.h>
+
+#include <fvp_lfa_components.h>
+
+/* Keep this array consistent with enum fvp_lfa_component_id_t */
+static plat_lfa_component_info_t fvp_lfa_components[LFA_MAX_DEFINED_COMPONENTS] = {
+ [LFA_BL31_COMPONENT] = {LFA_BL31_COMPONENT, UUID_EL3_RUNTIME_FIRMWARE_BL31,
+ NULL, false},
+#if BL32_BASE
+ [LFA_BL32_COMPONENT] = {LFA_BL32_COMPONENT, UUID_SECURE_PAYLOAD_BL32,
+ NULL, false},
+#endif /* BL32_BASE */
+ [LFA_BL33_COMPONENT] = {LFA_BL33_COMPONENT, UUID_NON_TRUSTED_FIRMWARE_BL33,
+ NULL, false},
+#if ENABLE_RME
+ [LFA_RMM_COMPONENT] = {LFA_RMM_COMPONENT, UUID_REALM_MONITOR_MGMT_FIRMWARE,
+ NULL, false},
+#endif /* ENABLE_RME */
+};
+
+uint32_t plat_lfa_get_components(plat_lfa_component_info_t **components)
+{
+ if (components == NULL) {
+ return -EINVAL;
+ }
+
+ fvp_lfa_components[LFA_BL31_COMPONENT].activator = get_bl31_activator();
+#if ENABLE_RME
+ fvp_lfa_components[LFA_RMM_COMPONENT].activator = get_rmm_activator();
+#endif /* ENABLE_RME */
+
+ *components = fvp_lfa_components;
+ return LFA_MAX_DEFINED_COMPONENTS;
+}
+
+bool is_plat_lfa_activation_pending(uint32_t lfa_component_id)
+{
+#if ENABLE_RME
+ if (lfa_component_id == LFA_RMM_COMPONENT) {
+ return true;
+ }
+#endif /* ENABLE_RME */
+
+ return false;
+}
+
+int plat_lfa_cancel(uint32_t lfa_component_id)
+{
+ /* placeholder function to do cancel LFA of given component */
+ return 0;
+}
+
+int plat_lfa_load_auth_image(uint32_t img_id)
+{
+ /*
+ * In AEM FVP, we don't want to bloat the code by adding
+ * loading and authentication mechanism, so here we assumed
+ * that the components are pre-loaded and authenticated already.
+ */
+ return 0;
+}
diff --git a/plat/arm/board/fvp/include/fvp_lfa_components.h b/plat/arm/board/fvp/include/fvp_lfa_components.h
new file mode 100644
index 0000000..09dcdfd
--- /dev/null
+++ b/plat/arm/board/fvp/include/fvp_lfa_components.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FVP_LFA_COMPONENTS_H
+#define FVP_LFA_COMPONENTS_H
+
+/*
+ * Define platform-specific numeric IDs for LFA FVP components.
+ */
+typedef enum {
+ LFA_BL31_COMPONENT = 0,
+#if BL32_BASE
+ LFA_BL32_COMPONENT,
+#endif /* BL32_BASE */
+ LFA_BL33_COMPONENT,
+#if ENABLE_RME
+ LFA_RMM_COMPONENT,
+#endif /* ENABLE_RME */
+ LFA_MAX_DEFINED_COMPONENTS
+} fvp_lfa_component_id_t;
+
+#endif /* FVP_LFA_COMPONENTS_H */
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 8e8870c..fd7e386 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -22,13 +22,6 @@
# only; enable redistributor frames of all CPU cores by default.
FVP_GICR_REGION_PROTECTION := 0
-ifeq (${HW_ASSISTED_COHERENCY}, 0)
-FVP_DT_PREFIX := fvp-base-gicv3-psci
-else
-FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq
-endif
-# fdts is wrong otherwise
-
# Size (in kilobytes) of the Trusted SRAM region to utilize when building for
# the FVP platform.
ifeq (${ENABLE_RME},1)
@@ -68,6 +61,7 @@
ENABLE_FEAT_D128 := 2
ENABLE_FEAT_FPMR := 2
ENABLE_FEAT_MOPS := 2
+ ENABLE_FEAT_FGWTE3 := 2
endif
ENABLE_SYS_REG_TRACE_FOR_NS := 2
@@ -137,7 +131,26 @@
GICV3_OVERRIDE_DISTIF_PWR_OPS := 1
FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c
+ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),)
+BL31_SOURCES += plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c
+endif
+ifeq (${HW_ASSISTED_COHERENCY}, 0)
+FVP_DT_PREFIX := fvp-base-gicv3-psci
+else
+FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq
+endif
+else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV5)
+USE_GIC_DRIVER := 5
+ENABLE_FEAT_GCIE := 1
+BL31_SOURCES += plat/arm/board/fvp/fvp_gicv5.c
+FVP_DT_PREFIX := "FVP does not provide a GICv5 dts yet"
+ifneq ($(SPD),none)
+ $(error Error: GICv5 is not compatible with SPDs)
+endif
+ifeq ($(ENABLE_RME),1)
+ $(error Error: GICv5 is not compatible with RME)
+endif
else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2)
USE_GIC_DRIVER := 2
@@ -230,7 +243,6 @@
#Build AArch64-only CPUs with no FVP model yet.
ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1)
# travis/gelas need these
- FEAT_PABANDON := 1
ERRATA_SME_POWER_DOWN := 1
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_gelas.S \
lib/cpus/aarch64/nevis.S \
@@ -359,6 +371,10 @@
$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS)))
HW_CONFIG := ${FVP_HW_CONFIG}
+# Allow hw_config's secondary-load-address in the DT to be changed
+FVP_HW_CONFIG_ADDR ?= 0x82000000
+DTC_CPPFLAGS += -DFVP_HW_CONFIG_ADDR=$(FVP_HW_CONFIG_ADDR)
+
# Set default initrd base 128MiB offset of the default kernel address in FVP
INITRD_BASE ?= 0x90000000
@@ -575,3 +591,7 @@
# Build macro necessary for running SPM tests on FVP platform
$(eval $(call add_define,PLAT_TEST_SPM))
+
+ifeq (${LFA_SUPPORT},1)
+BL31_SOURCES += plat/arm/board/fvp/fvp_lfa.c
+endif
diff --git a/plat/arm/board/juno/cert_create_tbbr.mk b/plat/arm/board/juno/cert_create_tbbr.mk
index 4d133b2..639ec97 100644
--- a/plat/arm/board/juno/cert_create_tbbr.mk
+++ b/plat/arm/board/juno/cert_create_tbbr.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2023, Arm Limited. All rights reserved.
+# Copyright (c) 2023-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -8,18 +8,16 @@
ifeq (${PLAT_DEF_OID},1)
ifeq (${ETHOSN_NPU_DRIVER},1)
- $(eval $(call add_define, PLAT_DEF_OID))
- $(eval $(call add_define, PDEF_CERTS))
- $(eval $(call add_define, PDEF_EXTS))
- $(eval $(call add_define, PDEF_KEYS))
+ CRTTOOL_DEFINES += PLAT_DEF_OID
+ CRTTOOL_DEFINES += PDEF_CERTS
+ CRTTOOL_DEFINES += PDEF_EXTS
+ CRTTOOL_DEFINES += PDEF_KEYS
- PLAT_INCLUDE += -I ${PLAT_DIR}/certificate/include \
- -I ../../include/drivers/arm
+ CRTTOOL_INCLUDE_DIRS += ${PLAT_DIR}/certificate/include \
+ ../../include/drivers/arm
- PLAT_OBJECTS += ${PLAT_DIR}certificate/src/juno_tbb_cert.o \
- ${PLAT_DIR}certificate/src/juno_tbb_ext.o \
- ${PLAT_DIR}certificate/src/juno_tbb_key.o
-
- OBJECTS += ${PLAT_OBJECTS}
+ CRTTOOL_SOURCES += ${PLAT_DIR}certificate/src/juno_tbb_cert.c \
+ ${PLAT_DIR}certificate/src/juno_tbb_ext.c \
+ ${PLAT_DIR}certificate/src/juno_tbb_key.c
endif
endif
diff --git a/plat/arm/board/juno/fdts/juno_fw_config.dts b/plat/arm/board/juno/fdts/juno_fw_config.dts
index 11e9574..3cd5ccf 100644
--- a/plat/arm/board/juno/fdts/juno_fw_config.dts
+++ b/plat/arm/board/juno/fdts/juno_fw_config.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,10 +19,19 @@
id = <TB_FW_CONFIG_ID>;
};
+
hw-config {
load-address = <0x0 0x82000000>;
max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
id = <HW_CONFIG_ID>;
};
+
+#if SPMC_AT_EL3
+ tos_fw-config {
+ load-address = <0x0 0x04001D00>;
+ max-size = <0x1000>;
+ id = <TOS_FW_CONFIG_ID>;
+ };
+#endif
};
};
diff --git a/plat/arm/board/juno/fdts/juno_stmm_manifest.dts b/plat/arm/board/juno/fdts/juno_stmm_manifest.dts
new file mode 100644
index 0000000..96d44f9
--- /dev/null
+++ b/plat/arm/board/juno/fdts/juno_stmm_manifest.dts
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+#include <platform_def.h>
+
+/ {
+#define MODE_SEL0 (0x1)
+#define MODE_SEL1 (0x2)
+
+#define SECURE_RO 0x1
+#define SECURE_RW 0x3
+#define SECURE_EXECUTE_RO 0x5
+#define SECURE_EXECUTE_RW 0x7
+#define NON_SECURE_RO 0x9
+#define NON_SECURE_RW 0xB
+#define NON_SECURE_EXECUTE_RO 0xD
+#define NON_SECURE_EXECUTE_RW 0xF
+ /*
+ * FF-A compatible Secure Partition Manager parses the
+ * config file and fetch the following booting arguments to
+ * pass on to the StandAloneMM(StMM) Secure Partition.
+ */
+ compatible = "arm,ffa-manifest-1.0";
+
+ description = "Juno StandaloneMm";
+ ffa-version = <0x00010002>; /* 31:16 - Major, 15:0 - Minor */
+ uuid = <0xdcae8d37 0x46446bf0 0xab401483 0xa3873c93>;
+ id = <0x8001>;
+ execution-ctx-count = <PLATFORM_CORE_COUNT>;
+ exception-level = <MODE_SEL0>; /* SEL0*/
+ execution-state = <0>; /* AArch64*/
+ load-address = <0x0 0xff200000>;
+ image-size = <0x0 0x00300000>;
+ xlat-granule = <0>; /* 4KiB */
+ boot_info_reg = <0>; /* x0 */
+ boot-order = <0>;
+ messaging-method = <0x603>; /* Direct req/resp/req2/resp2 supported. */
+ power-management-messages = <0>;
+ gp-register-num = <0>;
+
+ device-regions {
+ compatible = "arm,ffa-manifest-device-regions";
+
+ /**
+ * System registers, rtc, uart and etc regions for access from S-EL0.
+ */
+ io_fpga {
+ base-address = <0x0 0x1C000000>;
+ pages-count = <0x3000>;
+ attributes = <SECURE_RW>;
+ };
+
+ system_reg_el0 {
+ base-address = <0x0 0x1C010000>;
+ pages-count = <0x10>;
+ attributes = <SECURE_RW>;
+ };
+
+ soc_peripherals {
+ base-address = <0x0 0x7FF50000>;
+ pages-count = <0x90>;
+ attributes = <SECURE_RW>;
+ };
+
+ nor_flash0 {
+ base-address = <0x0 0x08000000>;
+ pages-count = <0x4000>;
+ attributes = <SECURE_RW>;
+ };
+ };
+
+ memory-regions {
+ compatible = "arm,ffa-manifest-memory-regions";
+
+ /*
+ * SPM Payload memory. Mapped as code region for S-EL0
+ * Similar to ARM_SP_IMAGE_MMAP.
+ */
+ stmm_region {
+ description = "image";
+ base-address = <0x0 0xff200000>;
+ pages-count = <0x300>;
+ /* StMM will remap the regions during runtime */
+ attributes = <SECURE_EXECUTE_RO>;
+ };
+
+ /*
+ * Memory shared between EL3 and S-EL0.
+ * Similar to ARM_SPM_BUF_EL0_MMAP.
+ */
+ rx-tx-buffers {
+ description = "shared-buff";
+ base-address = <0x0 0xff500000>;
+ pages-count = <0x100>;
+ attributes = <SECURE_RW>;
+ };
+
+ /*
+ * Memory shared between Normal world and S-EL0.
+ * Similar to ARM_SP_IMAGE_NS_BUF_MMAP.
+ */
+ ns_comm_buffer {
+ /*
+ * Description is needed for StMM to identify
+ * ns-communication buffer.
+ */
+ description = "ns-comm";
+ base-address = <0x0 0xff600000>;
+ pages-count = <0x10>;
+ attributes = <NON_SECURE_RW>;
+ };
+
+ /*
+ * Heap used by SP to allocate memory for DMA.
+ */
+ heap {
+ /*
+ * Description is needed for StMM to identify
+ * heap buffer.
+ */
+ description = "heap";
+ base-address = <0x0 0xFF610000>;
+ pages-count = <0x7F0>;
+ attributes = <SECURE_RW>;
+ };
+ };
+};
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index c8439e9..73ee346 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -14,6 +14,7 @@
#include <plat/arm/board/common/board_css_def.h>
#include <plat/arm/board/common/v2m_def.h>
#include <plat/arm/common/arm_def.h>
+#include <plat/arm/common/arm_spm_def.h>
#include <plat/arm/css/common/css_def.h>
#include <plat/arm/soc/common/soc_css_def.h>
#include <plat/common/common_def.h>
@@ -131,8 +132,15 @@
#endif
#ifdef IMAGE_BL31
-# define PLAT_ARM_MMAP_ENTRIES 8
-# define MAX_XLAT_TABLES 6
+# if SPMC_AT_EL3
+# define PLAT_ARM_MMAP_ENTRIES 10
+# define MAX_XLAT_TABLES 8
+# define PLAT_SP_IMAGE_MMAP_REGIONS 30
+# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 12
+# else
+# define PLAT_ARM_MMAP_ENTRIES 8
+# define MAX_XLAT_TABLES 6
+# endif
#endif
#ifdef IMAGE_BL32
@@ -140,6 +148,30 @@
# define MAX_XLAT_TABLES 4
#endif
+#if SPMC_AT_EL3
+/*
+ * Number of Secure Partitions supported.
+ * SPMC at EL3, uses this count to configure the maximum number of supported
+ * secure partitions.
+ */
+#define SECURE_PARTITION_COUNT 1
+
+/*
+ * Number of Normal World Partitions supported.
+ * SPMC at EL3, uses this count to configure the maximum number of supported
+ * NWd partitions.
+ */
+#define NS_PARTITION_COUNT 1
+
+/*
+ * Number of Logical Partitions supported.
+ * SPMC at EL3, uses this count to configure the maximum number of supported
+ * logical partitions.
+ */
+#define MAX_EL3_LP_DESCS_COUNT 1
+
+#endif /* SPMC_AT_EL3 */
+
/*
* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
* plus a little space for growth.
@@ -211,6 +243,9 @@
# define PLATFORM_STACK_SIZE UL(0x440)
#endif
+#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
+ PLAT_SP_IMAGE_NS_BUF_SIZE)
+
/* CCI related constants */
#define PLAT_ARM_CCI_BASE UL(0x2c090000)
#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4
diff --git a/plat/arm/board/juno/juno_bl31_setup.c b/plat/arm/board/juno/juno_bl31_setup.c
index 2eec105..ae69b43 100644
--- a/plat/arm/board/juno/juno_bl31_setup.c
+++ b/plat/arm/board/juno/juno_bl31_setup.c
@@ -11,6 +11,7 @@
#include <lib/fconf/fconf_dyn_cfg_getter.h>
#include <plat/arm/common/plat_arm.h>
+#include <platform_def.h>
void __init bl31_early_platform_setup2(u_register_t arg0,
u_register_t arg1, u_register_t arg2, u_register_t arg3)
diff --git a/plat/arm/board/juno/juno_common.c b/plat/arm/board/juno/juno_common.c
index 2cd01e4..e3a6b42 100644
--- a/plat/arm/board/juno/juno_common.c
+++ b/plat/arm/board/juno/juno_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -58,6 +58,9 @@
#ifdef JUNO_ETHOSN_TZMP1
JUNO_ETHOSN_PROT_FW_RW,
#endif
+#if SPMC_AT_EL3
+ ARM_SP_IMAGE_MMAP,
+#endif
{0}
};
#endif
diff --git a/plat/arm/board/juno/juno_el3_spmc.c b/plat/arm/board/juno/juno_el3_spmc.c
new file mode 100644
index 0000000..7d1e44f
--- /dev/null
+++ b/plat/arm/board/juno/juno_el3_spmc.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2022-2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <services/el3_spmc_ffa_memory.h>
+
+#include <platform_def.h>
+
+__section(".arm_el3_tzc_dram") __unused static uint8_t plat_spmc_shmem_datastore[PAGE_SIZE];
+
+int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size)
+{
+ *datastore = (uint8_t *)plat_spmc_shmem_datastore;
+ *size = PAGE_SIZE;
+ return 0;
+}
+
+/*
+ * Add dummy implementations of memory management related platform hooks.
+ * These can be used to implement platform specific functionality to support
+ * a memory sharing/lending operation.
+ *
+ * Note: The hooks must be located as part of the initial share request and
+ * final reclaim to prevent order dependencies with operations that may take
+ * place in the normal world without visibility of the SPMC.
+ */
+int plat_spmc_shmem_begin(struct ffa_mtd *desc)
+{
+ return 0;
+}
+int plat_spmc_shmem_reclaim(struct ffa_mtd *desc)
+{
+ return 0;
+}
+
+int plat_spmd_handle_group0_interrupt(uint32_t intid)
+{
+ /*
+ * As of now, there are no sources of Group0 secure interrupt enabled
+ * for Juno.
+ */
+ (void)intid;
+ return -1;
+}
+
diff --git a/plat/arm/board/juno/juno_security.c b/plat/arm/board/juno/juno_security.c
index 72e7e78..23000da 100644
--- a/plat/arm/board/juno/juno_security.c
+++ b/plat/arm/board/juno/juno_security.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -88,6 +88,20 @@
#endif /* JUNO_ETHOSN_TZMP1 */
+#if SPMC_AT_EL3
+
+// Use last 2MB as secure storage only.
+#define V2M_FLASH0_SECURE_START (V2M_FLASH0_BASE + V2M_FLASH0_SIZE - 0x200000)
+#define V2M_FLASH0_SECURE_END (V2M_FLASH0_BASE + V2M_FLASH0_SIZE - 1)
+
+static const arm_tzc_regions_info_t juno_stmm_tzc_regions[] = {
+ ARM_TZC_REGIONS_DEF,
+ { V2M_FLASH0_SECURE_START, V2M_FLASH0_SECURE_END, TZC_REGION_S_RDWR, 0 },
+ {},
+};
+
+#endif /* SPMC_AT_EL3 */
+
/*******************************************************************************
* Set up the MMU-401 SSD tables. The power-on configuration has all stream IDs
* assigned to Non-Secure except some for the DMA-330. Assign those back to the
@@ -161,6 +175,11 @@
INFO("TZC protected FW memory range for NPU TZMP usecase: %p - %p\n",
(void *)JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE,
(void *)JUNO_ETHOSN_FW_TZC_PROT_DRAM2_END);
+#elif SPMC_AT_EL3
+ INFO("TZC protected some of Nor flash memory range for StandaloneMm: %p - %p\n",
+ (void *)V2M_FLASH0_SECURE_START,
+ (void *)V2M_FLASH0_SECURE_END);
+ arm_tzc400_setup(PLAT_ARM_TZC_BASE, juno_stmm_tzc_regions);
#else
arm_tzc400_setup(PLAT_ARM_TZC_BASE, NULL);
#endif
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index 38ba0ed..a5de78f 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -29,6 +29,14 @@
PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S \
plat/arm/board/juno/juno_common.c
+ifeq (${SPMC_AT_EL3}, 1)
+PLAT_BL_COMMON_SOURCES += plat/arm/board/juno/juno_el3_spmc.c
+endif
+
+ifeq (${HOB_LIST}, 1)
+include lib/hob/hob.mk
+endif
+
# Flag to enable support for AArch32 state on JUNO
JUNO_AARCH32_EL3_RUNTIME := 0
$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME))
@@ -205,6 +213,13 @@
# Add the HW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG}))
+
+ifeq (${SPD},spmd)
+ifneq ($(ARM_SPMC_MANIFEST_DTS),)
+FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS}
+endif
+endif
+
include drivers/arm/ethosn/ethosn_npu.mk
include plat/arm/board/common/board_common.mk
include plat/arm/common/arm_common.mk
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index b29f0d6..4a3dfff 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -16,6 +16,7 @@
HW_ASSISTED_COHERENCY := 1
USE_COHERENT_MEM := 0
USE_GIC_DRIVER := 3
+USE_DSU_DRIVER := 1
GIC_ENABLE_V4_EXTN := 1
GICV3_SUPPORT_GIC600 := 1
override NEED_BL2U := no
@@ -122,7 +123,6 @@
# CPU libraries for TARGET_PLATFORM=4
ifeq (${TARGET_PLATFORM}, 4)
-FEAT_PABANDON := 1
# prevent CME related wakups
ERRATA_SME_POWER_DOWN := 1
TC_CPU_SOURCES += lib/cpus/aarch64/cortex_gelas.S \
@@ -162,7 +162,7 @@
${TC_BASE}/tc_topology.c \
lib/fconf/fconf.c \
lib/fconf/fconf_dyn_cfg_getter.c \
- drivers/arm/css/dsu/dsu.c \
+ drivers/arm/dsu/dsu.c \
drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c \
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
index 7f2014b..073e487 100644
--- a/plat/arm/board/tc/tc_bl31_setup.c
+++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -14,6 +14,7 @@
#include <common/debug.h>
#include <drivers/arm/css/css_mhu_doorbell.h>
#include <drivers/arm/css/scmi.h>
+#include <drivers/arm/dsu.h>
#include <drivers/arm/sbsa.h>
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
@@ -74,6 +75,13 @@
#endif
};
+const dsu_driver_data_t plat_dsu_data = {
+ .clusterpwrdwn_pwrdn = false,
+ .clusterpwrdwn_memret = false,
+ .clusterpwrctlr_cachepwr = CLUSTERPWRCTLR_CACHEPWR_RESET,
+ .clusterpwrctlr_funcret = CLUSTERPWRCTLR_FUNCRET_RESET
+};
+
#if (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4)
static void enable_ns_mcn_pmu(void)
{
diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index 06a919c..adfc848 100644
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c
@@ -15,7 +15,7 @@
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
#if TRANSFER_LIST
-#include <lib/transfer_list.h>
+#include <transfer_list.h>
#endif
#include <lib/utils.h>
#include <lib/xlat_tables/xlat_tables_compat.h>
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 522017f..78ab862 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -20,7 +20,7 @@
#include <lib/fconf/fconf_dyn_cfg_getter.h>
#include <lib/gpt_rme/gpt_rme.h>
#if TRANSFER_LIST
-#include <lib/transfer_list.h>
+#include <transfer_list.h>
#endif
#ifdef SPD_opteed
#include <lib/optee_utils.h>
@@ -321,6 +321,7 @@
{
entry_point_info_t *ep __unused;
+#if TRANSFER_LIST
/*
* Information might have been added to the TL before this (i.e. event log)
* make sure the checksum is up to date.
@@ -332,4 +333,5 @@
assert(ep != NULL);
arm_transfer_list_populate_ep_info(next_param_node, secure_tl);
+#endif
}
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index f196269..ce6b21e 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -18,7 +18,7 @@
#include <lib/gpt_rme/gpt_rme.h>
#include <lib/mmio.h>
#if TRANSFER_LIST
-#include <lib/transfer_list.h>
+#include <transfer_list.h>
#endif
#include <lib/xlat_tables/xlat_tables_compat.h>
#include <plat/arm/common/plat_arm.h>
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 53fe806..c668380 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -320,8 +320,11 @@
endif
ifeq (${TRANSFER_LIST}, 1)
- include lib/transfer_list/transfer_list.mk
- TRANSFER_LIST_SOURCES += plat/arm/common/arm_transfer_list.c
+include lib/transfer_list/transfer_list.mk
+
+BL1_SOURCES += plat/arm/common/arm_transfer_list.c
+BL2_SOURCES += plat/arm/common/arm_transfer_list.c
+BL31_SOURCES += plat/arm/common/arm_transfer_list.c
endif
ifneq ($(filter 1,${ENABLE_PMF} ${ETHOSN_NPU_DRIVER}),)
@@ -434,12 +437,12 @@
ifeq (${COT_DESC_IN_DTB},0)
ifeq (${COT},dualroot)
- COTDTPATH := fdts/dualroot_cot_descriptors.dtsi
+ COTDTPATH := fdts/dualroot_cot_descriptors.dts
else ifeq (${COT},cca)
- COTDTPATH := fdts/cca_cot_descriptors.dtsi
+ COTDTPATH := fdts/cca_cot_descriptors.dts
else ifeq (${COT},tbbr)
ifneq (${PLAT},juno)
- COTDTPATH := fdts/tbbr_cot_descriptors.dtsi
+ COTDTPATH := fdts/tbbr_cot_descriptors.dts
endif
endif
endif
@@ -512,22 +515,12 @@
endif
ifneq ($(COTDTPATH),)
- cot-dt-defines = IMAGE_BL2 $(BL2_DEFINES) $(PLAT_BL_COMMON_DEFINES)
- cot-dt-include-dirs = $(BL2_INCLUDE_DIRS) $(PLAT_BL_COMMON_INCLUDE_DIRS)
+ # no custom flags
+ $(eval $(call MAKE_PRE,$(BUILD_PLAT)/$(COTDTPATH),$(COTDTPATH),$(BUILD_PLAT)/$(COTDTPATH:.dts=.o.d)))
- cot-dt-cpp-flags = $(cot-dt-defines:%=-D%)
- cot-dt-cpp-flags += $(cot-dt-include-dirs:%=-I%)
-
- cot-dt-cpp-flags += $(BL2_CPPFLAGS) $(PLAT_BL_COMMON_CPPFLAGS)
- cot-dt-cpp-flags += $(CPPFLAGS) $(BL_CPPFLAGS) $(TF_CFLAGS_$(ARCH))
- cot-dt-cpp-flags += -c -x assembler-with-cpp -E -P -o $@ $<
-
- $(BUILD_PLAT)/$(COTDTPATH:.dtsi=.dts): $(COTDTPATH) | $$(@D)/
- $(q)$($(ARCH)-cpp) $(cot-dt-cpp-flags)
-
- $(BUILD_PLAT)/$(COTDTPATH:.dtsi=.c): $(BUILD_PLAT)/$(COTDTPATH:.dtsi=.dts) | $$(@D)/
+ $(BUILD_PLAT)/$(COTDTPATH:.dts=.c): $(BUILD_PLAT)/$(COTDTPATH) | $$(@D)/
$(if $(host-poetry),$(q)poetry -q install --no-root)
$(q)$(if $(host-poetry),poetry run )cot-dt2c convert-to-c $< $@
- BL2_SOURCES += $(BUILD_PLAT)/$(COTDTPATH:.dtsi=.c)
+ BL2_SOURCES += $(BUILD_PLAT)/$(COTDTPATH:.dts=.c)
endif
diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c
index 18882d3..80da3d9 100644
--- a/plat/arm/css/common/css_pm.c
+++ b/plat/arm/css/common/css_pm.c
@@ -12,7 +12,7 @@
#include <bl31/interrupt_mgmt.h>
#include <common/debug.h>
#include <drivers/arm/css/css_scp.h>
-#include <drivers/arm/css/dsu.h>
+#include <drivers/arm/dsu.h>
#include <lib/cassert.h>
#include <plat/arm/common/plat_arm.h>
diff --git a/plat/common/plat_bl_common.c b/plat/common/plat_bl_common.c
index 4772bad..990a36a 100644
--- a/plat/common/plat_bl_common.c
+++ b/plat/common/plat_bl_common.c
@@ -9,7 +9,9 @@
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
-#include <lib/transfer_list.h>
+#if TRANSFER_LIST
+#include <transfer_list.h>
+#endif
#include <lib/xlat_tables/xlat_tables_compat.h>
#include <plat/common/platform.h>
#include <services/arm_arch_svc.h>
@@ -29,6 +31,7 @@
#pragma weak plat_is_smccc_feature_available
#pragma weak plat_get_soc_version
#pragma weak plat_get_soc_revision
+#pragma weak plat_get_soc_name
int32_t plat_get_soc_version(void)
{
@@ -40,6 +43,11 @@
return SMC_ARCH_CALL_NOT_SUPPORTED;
}
+int32_t plat_get_soc_name(char *soc_name __unused)
+{
+ return SMC_ARCH_CALL_NOT_SUPPORTED;
+}
+
int32_t plat_is_smccc_feature_available(u_register_t fid __unused)
{
return SMC_ARCH_CALL_NOT_SUPPORTED;
diff --git a/plat/common/plat_gicv5.c b/plat/common/plat_gicv5.c
new file mode 100644
index 0000000..e445886
--- /dev/null
+++ b/plat/common/plat_gicv5.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <bl31/interrupt_mgmt.h>
+#include <drivers/arm/gicv5.h>
+
+uint32_t plat_ic_get_pending_interrupt_type(void)
+{
+ return gicv5_get_pending_interrupt_type();
+}
+
+bool plat_ic_has_interrupt_type(unsigned int type)
+{
+ return gicv5_has_interrupt_type(type);
+}
diff --git a/plat/imx/imx8m/imx8mp/gpc.c b/plat/imx/imx8m/imx8mp/gpc.c
index a95eb36..5e2d9e4 100644
--- a/plat/imx/imx8m/imx8mp/gpc.c
+++ b/plat/imx/imx8m/imx8mp/gpc.c
@@ -268,23 +268,6 @@
/* set the PGC bit */
mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);
- /*
- * leave the G1, G2, H1 power domain on until VPUMIX power off,
- * otherwise system will hang due to VPUMIX ACK
- */
- if (domain_id == VPU_H1 || domain_id == VPU_G1 || domain_id == VPU_G2) {
- return;
- }
-
- if (domain_id == VPUMIX) {
- mmio_write_32(IMX_GPC_BASE + PU_PGC_DN_TRG, VPU_G1_PWR_REQ |
- VPU_G2_PWR_REQ | VPU_H1_PWR_REQ);
-
- while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & (VPU_G1_PWR_REQ |
- VPU_G2_PWR_REQ | VPU_H1_PWR_REQ))
- ;
- }
-
/* power down the domain */
mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req);
diff --git a/plat/imx/imx8ulp/imx8ulp_psci.c b/plat/imx/imx8ulp/imx8ulp_psci.c
index 59af8be..e67d0b5 100644
--- a/plat/imx/imx8ulp/imx8ulp_psci.c
+++ b/plat/imx/imx8ulp/imx8ulp_psci.c
@@ -289,7 +289,9 @@
/* LDO1 should be power off in PD mode */
} else if (mode == PD_PWR_MODE) {
/* overwrite the buck3 voltage setting in active mode */
- upower_pmic_i2c_read(0x22, &volt);
+ if (upower_pmic_i2c_read(0x22, &volt) != 0) {
+ panic();
+ }
pd_pmic_reg_cfgs[3].i2c_data = volt;
memcpy(&pwr_sys_cfg->ps_apd_pmic_reg_data_cfg, &pd_pmic_reg_cfgs,
sizeof(ps_apd_pmic_reg_data_cfgs_t));
diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c
index a3c3545..dabe865 100644
--- a/plat/intel/soc/agilex/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex/bl31_plat_setup.c
@@ -67,6 +67,11 @@
mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
PLAT_BAUDRATE, &console);
+
+ /* Enable TF-A BL31 logs when running from non-secure world also. */
+ console_set_scope(&console,
+ (CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH));
+
/*
* Check params passed from BL31 should not be NULL,
*/
diff --git a/plat/intel/soc/agilex5/include/agilex5_system_manager.h b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
index 8c86ab1..f4b53e8 100644
--- a/plat/intel/soc/agilex5/include/agilex5_system_manager.h
+++ b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
@@ -160,6 +160,11 @@
#define SOCFPGA_ECC_QSPI_ECC_STARTACC 0x7C
#define SOCFPGA_ECC_QSPI_ECC_WDCTRL 0x80
+/* IOSSM mailbox address */
+#define IOSSM_CMD_PARAM 0x18400438
+#define IOSSM_CMD_TRIG_OP 0x1840043C
+#define IOSSM_CMD_RESP_STATUS 0x1840045C
+
#define DMA0_STREAM_CTRL_REG 0x10D1217C
#define DMA1_STREAM_CTRL_REG 0x10D12180
#define SDM_STREAM_CTRL_REG 0x10D12184
diff --git a/plat/intel/soc/agilex5/soc/agilex5_ddr.c b/plat/intel/soc/agilex5/soc/agilex5_ddr.c
index 0d60324..acf7528 100644
--- a/plat/intel/soc/agilex5/soc/agilex5_ddr.c
+++ b/plat/intel/soc/agilex5/soc/agilex5_ddr.c
@@ -297,7 +297,7 @@
bool full_mem_init = false;
phys_size_t hw_ddr_size;
phys_size_t config_ddr_size;
- struct io96b_info io96b_ctrl;
+ struct io96b_info io96b_ctrl = {0};
enum reset_type reset_t = get_reset_type(mmio_read_32(SOCFPGA_SYSMGR(
BOOT_SCRATCH_COLD_3)));
bool is_dualport = hoff_ptr->ddr_config & BIT(0);
diff --git a/plat/intel/soc/common/include/socfpga_fcs.h b/plat/intel/soc/common/include/socfpga_fcs.h
index f92678f..21d9b66 100644
--- a/plat/intel/soc/common/include/socfpga_fcs.h
+++ b/plat/intel/soc/common/include/socfpga_fcs.h
@@ -76,6 +76,10 @@
#define FCS_MAX_DATA_SIZE 0x20000000 /* 512 MB */
#define FCS_MIN_DATA_SIZE 0x8 /* 8 Bytes */
+#define FCS_AES_DATA_SIZE_CHECK(x) (((x >= FCS_AES_MIN_DATA_SIZE) && \
+ (x <= FCS_AES_MAX_DATA_SIZE)) ? \
+ true : false)
+
#define FCS_GET_DIGEST_CMD_MAX_WORD_SIZE 7U
#define FCS_GET_DIGEST_RESP_MAX_WORD_SIZE 19U
#define FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE 23U
@@ -362,7 +366,7 @@
uint32_t session_id, uint32_t context_id,
uint64_t src_addr, uint32_t src_size,
uint64_t dst_addr, uint32_t dst_size,
- uint32_t aad_size, uint8_t is_finalised,
+ uint32_t padding_size, uint8_t is_finalised,
uint32_t *send_id, uint64_t smmu_src_addr,
uint64_t smmu_dst_addr);
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index f965b7d..4da318b 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -309,7 +309,7 @@
((client_id << MBOX_CLIENT_ID_SHIFT) | \
(job_id << MBOX_JOB_ID_SHIFT) | \
(args_len << MBOX_CMD_LEN_SHIFT) | \
- (indirect << MBOX_CMD_LEN_SHIFT) | \
+ (indirect << MBOX_INDIRECT_SHIFT) | \
cmd)
#define FLAG_SDM_RESPONSE_IS_VALID BIT(0)
@@ -362,7 +362,7 @@
/* SDM client callback template */
typedef uint8_t (*sdm_command_callback)(void *resp, void *cmd,
- uint32_t *ret_args);
+ uint64_t *ret_args);
/* SDM command data structure */
typedef struct sdm_command {
@@ -394,7 +394,7 @@
sdm_command_callback cb, uint32_t *cb_args,
uint32_t cb_args_len);
-int mailbox_response_poll_v3(uint8_t client_id, uint8_t job_id, uint32_t *ret_args,
+int mailbox_response_poll_v3(uint8_t client_id, uint8_t job_id, uint64_t *ret_args,
uint32_t *ret_args_size);
int mailbox_response_poll_on_intr_v3(uint8_t *client_id, uint8_t *job_id,
diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h
index 7f96adb..9e06397 100644
--- a/plat/intel/soc/common/include/socfpga_sip_svc.h
+++ b/plat/intel/soc/common/include/socfpga_sip_svc.h
@@ -153,6 +153,9 @@
/* ATF build version */
#define INTEL_SIP_SMC_ATF_BUILD_VER 0xC200009B
+/* IO96B ECC Error Injection */
+#define INTEL_SIP_SMC_INJECT_IO96B_ECC_ERR 0xC200009C
+
#define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF
#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF
#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET 4U
@@ -163,6 +166,8 @@
#define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\
SYSMGR_ECC_DDR0_MASK |\
SYSMGR_ECC_DDR1_MASK)
+#define IOSSM_ECC_ERR_INJ_DELAY_USECS (40U)
+#define IOSSM_CMD_STATUS_RESP_READY BIT(0)
/* Non-mailbox SMC Call */
#define INTEL_SIP_SMC_SVC_VERSION 0xC2000200
@@ -255,6 +260,12 @@
#define SMC_RET_ARGS_FOUR (4)
#define SMC_RET_ARGS_FIVE (5)
#define SMC_RET_ARGS_SIX (6)
+#define SMC_RET_ARGS_SEVEN (7)
+#define SMC_RET_ARGS_EIGHT (8)
+#define SMC_RET_ARGS_NINE (9)
+#define SMC_RET_ARGS_TEN (10)
+
+#define MBOX_GEN_CMD_MAX_WORDS (0x1000)
/*
* SiP SVC Version3 SMC Functions IDs
@@ -278,6 +289,14 @@
#define ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP (0x420000E8)
#define ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT (0x420000E9)
+/* RSU related commands */
+#define ALTERA_SIP_SMC_ASYNC_RSU_GET_SPT (0x420000EA)
+#define ALTERA_SIP_SMC_ASYNC_RSU_GET_STATUS (0x420000EB)
+#define ALTERA_SIP_SMC_ASYNC_RSU_NOTIFY (0x420000EC)
+
+/* V3 Generic mailbox command. */
+#define ALTERA_SIP_SMC_ASYNC_GEN_MBOX_CMD (0x420000EE)
+
/* FCS crypto service VAB/SDOS commands */
#define ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER (0x4200012C)
#define ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT (0x4200012D)
@@ -344,6 +363,8 @@
#define GET_CLIENT_ID(x) (((x) & 0xF0) >> 4)
#define GET_JOB_ID(x) ((x) & 0x0F)
+#define GET_ADDR64(high, low) (((uint64_t)(high) \
+ << 32) | (low))
#endif /* SIP_SVC_V3 */
#endif /* SOCFPGA_SIP_SVC_H */
diff --git a/plat/intel/soc/common/sip/socfpga_sip_fcs.c b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
index b9c7b59..507a9e9 100644
--- a/plat/intel/soc/common/sip/socfpga_sip_fcs.c
+++ b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
@@ -25,7 +25,7 @@
static fcs_crypto_service_data fcs_ecdsa_get_pubkey_param;
static fcs_crypto_service_data fcs_ecdh_request_param;
-uint8_t fcs_send_cert_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_send_cert_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -42,7 +42,7 @@
return ret_args_len;
}
-uint8_t fcs_cntr_set_preauth_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cntr_set_preauth_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -57,7 +57,7 @@
return ret_args_len;
}
-uint8_t fcs_get_attest_cert_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_get_attest_cert_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -74,7 +74,7 @@
return ret_args_len;
}
-uint8_t fcs_hkdf_request_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_hkdf_request_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -92,7 +92,7 @@
return ret_args_len;
}
-uint8_t fcs_create_cert_reload_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_create_cert_reload_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -107,7 +107,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_get_digest_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_get_digest_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -124,7 +124,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_mac_verify_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_mac_verify_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -144,7 +144,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_hash_sign_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_hash_sign_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -162,7 +162,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_hash_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_hash_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -180,7 +180,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_aes_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_aes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -198,7 +198,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_data_sign_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_data_sign_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -215,7 +215,7 @@
return ret_args_len;
}
-uint8_t fcs_sdos_crypto_request_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_sdos_crypto_request_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -233,7 +233,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_get_public_key_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_get_public_key_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -251,7 +251,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_data_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_data_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -268,7 +268,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_ecdh_request_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_ecdh_request_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -304,6 +304,17 @@
}
}
+/* As of now used on only Agilex5 platform. */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+static bool is_16_bytes_aligned(uint32_t data)
+{
+ if ((data % (MBOX_WORD_BYTE * 4U)) != 0U)
+ return false;
+ else
+ return true;
+}
+#endif
+
static bool is_32_bytes_aligned(uint32_t data)
{
if ((data % (8U * MBOX_WORD_BYTE)) != 0U) {
@@ -2708,7 +2719,7 @@
uint32_t session_id, uint32_t context_id,
uint64_t src_addr, uint32_t src_size,
uint64_t dst_addr, uint32_t dst_size,
- uint32_t aad_size, uint8_t is_finalised,
+ uint32_t padding_size, uint8_t is_finalised,
uint32_t *send_id, uint64_t smmu_src_addr,
uint64_t smmu_dst_addr)
{
@@ -2719,30 +2730,55 @@
uint32_t fcs_aes_crypt_payload[FCS_AES_CMD_MAX_WORD_SIZE];
uint32_t src_addr_sdm = (uint32_t)src_addr;
uint32_t dst_addr_sdm = (uint32_t)dst_addr;
+ bool is_src_size_aligned;
+ bool is_dst_size_aligned;
+ bool is_src_size_valid;
+ bool is_dst_size_valid;
if (fcs_aes_init_payload.session_id != session_id ||
fcs_aes_init_payload.context_id != context_id) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
+ /* Default source and destination size align check, 32 bytes alignment. */
+ is_src_size_aligned = is_32_bytes_aligned(src_size);
+ is_dst_size_aligned = is_32_bytes_aligned(dst_size);
+ is_src_size_valid = FCS_AES_DATA_SIZE_CHECK(src_size);
+ is_dst_size_valid = FCS_AES_DATA_SIZE_CHECK(dst_size);
+
+ /*
+ * Get the requested block mode.
+ * On the Agilex5 platform with GCM and GCM-GHASH modes, the source and destination size
+ * should be in multiples of 16 bytes. For other platforms and other modes, it should be
+ * in multiples of 32 bytes.
+ */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ uint32_t block_mode = fcs_aes_init_payload.crypto_param[0] & FCS_CRYPTO_BLOCK_MODE_MASK;
+
+ if ((block_mode == FCS_CRYPTO_GCM_MODE) ||
+ (block_mode == FCS_CRYPTO_GCM_GHASH_MODE)) {
+ is_src_size_aligned = is_16_bytes_aligned(src_size);
+ is_dst_size_aligned = is_16_bytes_aligned(dst_size);
+ /* The size validity here is, should be 0 or multiples of 16 bytes. */
+ is_src_size_valid = is_16_bytes_aligned(src_size);
+ is_dst_size_valid = is_16_bytes_aligned(dst_size);
+ }
+#endif
+
if ((!is_8_bytes_aligned(src_addr)) ||
- (!is_32_bytes_aligned(src_size)) ||
+ (!is_src_size_aligned) ||
(!is_address_in_ddr_range(src_addr, src_size))) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
if ((!is_8_bytes_aligned(dst_addr)) ||
- (!is_32_bytes_aligned(dst_size)) ||
+ (!is_dst_size_aligned) ||
(!is_address_in_ddr_range(dst_addr, dst_size))) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
- if ((dst_size > FCS_AES_MAX_DATA_SIZE ||
- dst_size < FCS_AES_MIN_DATA_SIZE) ||
- (src_size > FCS_AES_MAX_DATA_SIZE ||
- src_size < FCS_AES_MIN_DATA_SIZE)) {
+ if (!is_src_size_valid || !is_dst_size_valid)
return INTEL_SIP_SMC_STATUS_REJECTED;
- }
/* Prepare crypto header*/
flag = 0;
@@ -2802,11 +2838,14 @@
fcs_aes_crypt_payload[i] = dst_size;
i++;
- /* Additional Authenticated Data size */
- if (aad_size > 0) {
- fcs_aes_crypt_payload[i] = aad_size;
+ /* Padding data size, only on Agilex5 with GCM and GCM-GHASH modes. */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ if ((block_mode == FCS_CRYPTO_GCM_MODE) ||
+ (block_mode == FCS_CRYPTO_GCM_GHASH_MODE)) {
+ fcs_aes_crypt_payload[i] = padding_size;
i++;
}
+#endif
status = ((smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE) ||
(smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE)) ?
@@ -2828,7 +2867,7 @@
sizeof(fcs_aes_init_payload));
}
- if (status < 0U) {
+ if (status < 0) {
return INTEL_SIP_SMC_STATUS_ERROR;
}
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index 3b3b479..bf1b7fb 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -1442,7 +1442,7 @@
}
int mailbox_response_poll_v3(uint8_t client_id, uint8_t job_id,
- uint32_t *ret_args, uint32_t *ret_args_len)
+ uint64_t *ret_args, uint32_t *ret_args_len)
{
sdm_command_t *cmd_desc = NULL;
sdm_response_t *resp_desc = NULL;
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index f4a3ea0..cbb366e 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
* Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
*
@@ -9,6 +9,7 @@
#include <assert.h>
#include <common/debug.h>
#include <common/runtime_svc.h>
+#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <tools_share/uuid.h>
@@ -799,10 +800,26 @@
}
return INTEL_SIP_SMC_STATUS_OK;
}
+
+static void intel_inject_io96b_ecc_err(const uint32_t *syndrome, const uint32_t command)
+{
+ volatile uint64_t atf_ddr_buffer;
+ volatile uint64_t val;
+
+ mmio_write_32(IOSSM_CMD_PARAM, *syndrome);
+ mmio_write_32(IOSSM_CMD_TRIG_OP, command);
+ udelay(IOSSM_ECC_ERR_INJ_DELAY_USECS);
+ atf_ddr_buffer = 0xCAFEBABEFEEDFACE; /* Write data */
+ memcpy_s((void *)&val, sizeof(val),
+ (void *)&atf_ddr_buffer, sizeof(atf_ddr_buffer));
+
+ /* Clear response_ready BIT0 of status_register before sending next command. */
+ mmio_clrbits_32(IOSSM_CMD_RESP_STATUS, IOSSM_CMD_STATUS_RESP_READY);
+}
#endif
#if SIP_SVC_V3
-uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -816,7 +833,7 @@
return ret_args_len;
}
-uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -831,7 +848,7 @@
return ret_args_len;
}
-uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -848,7 +865,7 @@
return ret_args_len;
}
-uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -866,35 +883,201 @@
return ret_args_len;
}
-static uintptr_t smc_ret(void *handle, uint32_t *ret_args, uint32_t ret_args_len)
+uint8_t sip_smc_cmd_cb_rsu_status(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
+ uint8_t ret_args_len = 0U;
+ uint32_t retry_counter = ~0U;
+ uint32_t failure_source = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ /* Get the failure source and current image retry counter value from the response. */
+ failure_source = resp->resp_data[5] & RSU_VERSION_ACMF_MASK;
+ retry_counter = resp->resp_data[8];
+
+ if ((retry_counter != ~0U) && (failure_source == 0U))
+ resp->resp_data[5] |= RSU_VERSION_ACMF;
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ /* Current CMF */
+ ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[1], resp->resp_data[0]);
+ /* Last Failing CMF Address */
+ ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[3], resp->resp_data[2]);
+ /* Config State */
+ ret_args[ret_args_len++] = resp->resp_data[4];
+ /* Version */
+ ret_args[ret_args_len++] = (GENMASK(16, 0) & resp->resp_data[5]);
+ /* Failure Source */
+ ret_args[ret_args_len++] = ((GENMASK(32, 17) & resp->resp_data[5]) >> 16);
+ /* Error location */
+ ret_args[ret_args_len++] = resp->resp_data[6];
+ /* Error details */
+ ret_args[ret_args_len++] = resp->resp_data[7];
+ /* Current image retry counter */
+ ret_args[ret_args_len++] = resp->resp_data[8];
+
+ return ret_args_len;
+}
+
+uint8_t sip_smc_cmd_cb_rsu_spt(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ /* Sub Partition Table (SPT) 0 address */
+ ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[0], resp->resp_data[1]);
+ /* Sub Partition Table (SPT) 1 address */
+ ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[2], resp->resp_data[3]);
+
+ return ret_args_len;
+}
+
+static uintptr_t smc_ret(void *handle, uint64_t *ret_args, uint32_t ret_args_len)
+{
+
switch (ret_args_len) {
case SMC_RET_ARGS_ONE:
+ VERBOSE("SVC V3: %s: x0 0x%lx\n", __func__, ret_args[0]);
SMC_RET1(handle, ret_args[0]);
break;
case SMC_RET_ARGS_TWO:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx\n", __func__, ret_args[0], ret_args[1]);
SMC_RET2(handle, ret_args[0], ret_args[1]);
break;
case SMC_RET_ARGS_THREE:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2]);
SMC_RET3(handle, ret_args[0], ret_args[1], ret_args[2]);
break;
case SMC_RET_ARGS_FOUR:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3]);
SMC_RET4(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3]);
break;
case SMC_RET_ARGS_FIVE:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]);
SMC_RET5(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]);
break;
+ case SMC_RET_ARGS_SIX:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx x3 0x%lx, x4 0x%lx x5 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5]);
+ SMC_RET6(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5]);
+ break;
+
+ case SMC_RET_ARGS_SEVEN:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t"
+ "x6 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6]);
+ SMC_RET7(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6]);
+ break;
+
+ case SMC_RET_ARGS_EIGHT:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t"
+ "x6 0x%lx, x7 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6], ret_args[7]);
+ SMC_RET8(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6], ret_args[7]);
+ break;
+
+ case SMC_RET_ARGS_NINE:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t"
+ "x6 0x%lx, x7 0x%lx, x8 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6], ret_args[7], ret_args[8]);
+ SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6], ret_args[7], ret_args[8],
+ 0, 0, 0, 0, 0, 0, 0, 0, 0);
+ break;
+
+ case SMC_RET_ARGS_TEN:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t"
+ "x6 0x%lx, x7 0x%lx x8 0x%lx, x9 0x%lx, x10 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3],
+ ret_args[4], ret_args[5], ret_args[6], ret_args[7], ret_args[8],
+ ret_args[9], ret_args[10]);
+ SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6], ret_args[7], ret_args[8], ret_args[9],
+ 0, 0, 0, 0, 0, 0, 0, 0);
+ break;
+
default:
+ VERBOSE("SVC V3: %s ret_args_len is wrong, please check %d\n ",
+ __func__, ret_args_len);
SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
break;
}
}
+static inline bool is_gen_mbox_cmd_allowed(uint32_t cmd)
+{
+ /* Check if the command is allowed to be executed in generic mbox format */
+ bool is_cmd_allowed = false;
+
+ switch (cmd) {
+ case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION:
+ case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION:
+ case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY:
+ case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY:
+ case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY:
+ case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO:
+ case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY:
+ case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST:
+ case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION:
+ /* These commands are not supported in the generic mailbox format. */
+ break;
+
+ default:
+ is_cmd_allowed = true;
+ break;
+ } /* switch */
+
+ return is_cmd_allowed;
+}
+
/*
* This function is responsible for handling all SiP SVC V3 calls from the
* non-secure world.
@@ -929,8 +1112,8 @@
switch (smc_fid) {
case ALTERA_SIP_SMC_ASYNC_RESP_POLL:
{
- uint32_t ret_args[8] = {0};
- uint32_t ret_args_len;
+ uint64_t ret_args[16] = {0};
+ uint32_t ret_args_len = 0;
status = mailbox_response_poll_v3(GET_CLIENT_ID(x1),
GET_JOB_ID(x1),
@@ -1177,6 +1360,111 @@
SMC_RET1(handle, status);
}
+ case ALTERA_SIP_SMC_ASYNC_RSU_GET_SPT:
+ {
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_GET_SUBPARTITION_TABLE,
+ NULL,
+ 0,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_rsu_spt,
+ NULL,
+ 0);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_RSU_GET_STATUS:
+ {
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_RSU_STATUS,
+ NULL,
+ 0,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_rsu_status,
+ NULL,
+ 0);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_RSU_NOTIFY:
+ {
+ uint32_t notify_code = (uint32_t)x2;
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_HPS_STAGE_NOTIFY,
+ ¬ify_code,
+ 1U,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_ret2,
+ NULL,
+ 0);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_GEN_MBOX_CMD:
+ {
+ /* Filter the required commands here. */
+ if (!is_gen_mbox_cmd_allowed(smc_fid)) {
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+
+ /* Collect all the args passed in, and send the mailbox command. */
+ uint32_t mbox_cmd = (uint32_t)x2;
+ uint32_t *cmd_payload_addr = NULL;
+ uint32_t cmd_payload_len = (uint32_t)x4 / MBOX_WORD_BYTE;
+ uint32_t *resp_payload_addr = NULL;
+ uint32_t resp_payload_len = (uint32_t)x6 / MBOX_WORD_BYTE;
+
+ if ((cmd_payload_len > MBOX_GEN_CMD_MAX_WORDS) ||
+ (resp_payload_len > MBOX_GEN_CMD_MAX_WORDS)) {
+ ERROR("MBOX: 0x%x: Command/Response payload length exceeds max limit\n",
+ smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+
+ /* Make sure we have valid command payload length and buffer */
+ if (cmd_payload_len != 0U) {
+ cmd_payload_addr = (uint32_t *)x3;
+ if (cmd_payload_addr == NULL) {
+ ERROR("MBOX: 0x%x: Command payload address is NULL\n",
+ smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+ }
+
+ /* Make sure we have valid response payload length and buffer */
+ if (resp_payload_len != 0U) {
+ resp_payload_addr = (uint32_t *)x5;
+ if (resp_payload_addr == NULL) {
+ ERROR("MBOX: 0x%x: Response payload address is NULL\n",
+ smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+ }
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ mbox_cmd,
+ (uint32_t *)cmd_payload_addr,
+ cmd_payload_len,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_ret_nbytes_cb,
+ (uint32_t *)resp_payload_addr,
+ resp_payload_len);
+
+ SMC_RET1(handle, status);
+ }
+
case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT:
{
uint32_t session_id = (uint32_t)x2;
@@ -1653,7 +1941,7 @@
uint32_t seu_respbuf[3];
int status = INTEL_SIP_SMC_STATUS_OK;
int mbox_status;
- unsigned int len_in_resp;
+ unsigned int len_in_resp = 0;
u_register_t x5, x6, x7;
switch (smc_fid) {
@@ -2194,6 +2482,12 @@
SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR,
VERSION_MINOR, VERSION_PATCH);
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ case INTEL_SIP_SMC_INJECT_IO96B_ECC_ERR:
+ intel_inject_io96b_ecc_err((uint32_t *)&x1, (uint32_t)x2);
+ SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK);
+#endif
+
default:
return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
cookie, handle, flags);
diff --git a/plat/marvell/armada/a8k/common/ble/ble.mk b/plat/marvell/armada/a8k/common/ble/ble.mk
index 5ab6123..5ec559d 100644
--- a/plat/marvell/armada/a8k/common/ble/ble.mk
+++ b/plat/marvell/armada/a8k/common/ble/ble.mk
@@ -24,7 +24,7 @@
BLE_DEFAULT_LINKER_SCRIPT_SOURCE := $(BLE_PATH)/ble.ld.S
BLE_OBJS := $(addprefix $(BUILD_PLAT)/ble/,$(call SOURCES_TO_OBJS,$(BLE_SOURCES)))
-$(BLE_OBJS): PLAT_INCLUDES += -I$(MV_DDR_PATH)
+BLE_INCLUDE_DIRS += $(MV_DDR_PATH)
$(BLE_OBJS): $(MV_DDR_LIB)
$(MV_DDR_LIB): FORCE
diff --git a/plat/marvell/armada/a8k/common/plat_pm.c b/plat/marvell/armada/a8k/common/plat_pm.c
index ae3ee37..b171e92 100644
--- a/plat/marvell/armada/a8k/common/plat_pm.c
+++ b/plat/marvell/armada/a8k/common/plat_pm.c
@@ -733,16 +733,16 @@
}
static void
-__dead2 a8k_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state)
+a8k_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state)
{
struct power_off_method *pm_cfg;
unsigned int srcmd;
unsigned int sdram_reg;
register_t gpio_data = 0, gpio_addr = 0;
+ /* let PSCI lib turn the core off */
if (is_pm_fw_running()) {
- psci_power_down_wfi();
- panic();
+ return;
}
pm_cfg = (struct power_off_method *)plat_marvell_get_pm_cfg();
diff --git a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h
index 4d99df1..d703551 100644
--- a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h
+++ b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h
@@ -37,11 +37,20 @@
#define CPC_PWR_MASK_MCUSYS_MP0 (0xC001)
+#ifdef CPU_PM_SPM_CORE_POWERON
+#define SPM_VLP_MCUSYS_PWR_CON (SPM_BASE + 0x260)
+#define SPM_VLP_MP0_CPUTOP_PWR_CON (SPM_BASE + 0x264)
+#define SPM_VLP_CPU_PWR_CON(core) (SPM_BASE + 0x268 + ((core) * 4))
+#else
+#define SPM_VLP_CPU_PWR_CON(core) 0
+#endif
+
#define PER_CPU_PWR_DATA(ctrl, cluster, core) \
do { \
ctrl.rvbaraddr_l = CORE_RVBRADDR_##cluster##_##core##_L; \
ctrl.arch_addr = MCUCFG_MP0_CLUSTER_CFG5; \
ctrl.pwpr = SPM_MP##cluster##_CPU##core##_PWR_CON; \
+ ctrl.pwpr_intermediate = SPM_VLP_CPU_PWR_CON(core); \
} while (0)
#define PER_CPU_PWR_CTRL(ctrl, cpu) ({ \
@@ -71,6 +80,7 @@
PER_CPU_PWR_DATA(ctrl, 0, 7); \
break; \
default: \
+ PER_CPU_PWR_DATA(ctrl, 0, 0); \
assert(0); \
break; \
} })
@@ -94,6 +104,7 @@
unsigned int rvbaraddr_l;
unsigned int arch_addr;
unsigned int pwpr;
+ unsigned int pwpr_intermediate;
};
#define MCUSYS_STATUS_PDN BIT(0)
diff --git a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_smp.c b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_smp.c
index a1d9c31..cae7a6a 100644
--- a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_smp.c
+++ b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_smp.c
@@ -45,11 +45,19 @@
int mt_smp_power_core_on(unsigned int cpu_id, struct cpu_pwr_ctrl *pwr_ctrl)
{
+ uint32_t pwpr_reg;
unsigned int val = is_core_power_status_on(cpu_id);
CPU_PM_ASSERT(pwr_ctrl);
- mmio_clrbits_32(pwr_ctrl->pwpr, RESETPWRON_CONFIG);
+#ifdef CPU_PM_SPM_CORE_POWERON
+ pwpr_reg = pwr_ctrl->pwpr_intermediate;
+#else
+ pwpr_reg = pwr_ctrl->pwpr;
+#endif
+
+ mmio_clrbits_32(pwpr_reg, RESETPWRON_CONFIG);
+
if (val == 0) {
/*
* Set to 0 after BIG VPROC bulk powered on (configure in MCUPM) and
@@ -59,17 +67,22 @@
mmio_write_32(DREQ20_BIG_VPROC_ISO, 0);
}
+#ifdef CPU_PM_SPM_CORE_POWERON
+ mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG,
+ SSPM_ALL_PWR_CTRL_EN);
+#endif
+
mmio_setbits_32(pwr_ctrl->pwpr, PWR_RST_B);
dsbsy();
- /* set mp0_spmc_pwr_on_cpuX = 1 */
- mmio_setbits_32(pwr_ctrl->pwpr, PWR_ON);
+ /* Set mp0_spmc_pwr_on_cpuX = 1 */
+ mmio_setbits_32(pwpr_reg, PWR_ON);
val = 0;
while (is_core_power_status_on(cpu_id) == 0) {
DO_SMP_CORE_ON_WAIT_TIMEOUT(val);
- mmio_clrbits_32(pwr_ctrl->pwpr, PWR_ON);
- mmio_setbits_32(pwr_ctrl->pwpr, PWR_ON);
+ mmio_clrbits_32(pwpr_reg, PWR_ON);
+ mmio_setbits_32(pwpr_reg, PWR_ON);
}
} else {
INFO("[%s:%d] - core_%u haven been power on\n", __func__, __LINE__, cpu_id);
@@ -80,14 +93,24 @@
int mt_smp_power_core_off(struct cpu_pwr_ctrl *pwr_ctrl)
{
- /* set mp0_spmc_pwr_on_cpuX = 1 */
+ /* Set mp0_spmc_pwr_on_cpuX = 1 */
+#ifdef CPU_PM_SPM_CORE_POWERON
+ mmio_clrbits_32(pwr_ctrl->pwpr_intermediate, PWR_ON);
+#else
mmio_clrbits_32(pwr_ctrl->pwpr, PWR_ON);
+#endif
return MTK_CPUPM_E_OK;
}
void mt_smp_init(void)
{
- /* clear RESETPWRON_CONFIG of mcusys/cluster/core0 */
+ /* INFO=SPMC_INIT: clear resetpwron of mcusys/cluster/core0 */
+#ifdef CPU_PM_SPM_CORE_POWERON
+ mmio_write_32(SPM_POWERON_CONFIG_EN, PROJECT_CODE | BCLK_CG_EN);
+ mmio_clrbits_32(SPM_VLP_MCUSYS_PWR_CON, RESETPWRON_CONFIG);
+ mmio_clrbits_32(SPM_VLP_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG);
+#else
mmio_clrbits_32(SPM_MCUSYS_PWR_CON, RESETPWRON_CONFIG);
mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG);
+#endif
}
diff --git a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_smp.h b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_smp.h
index 4c2f8d2..11b00b8 100644
--- a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_smp.h
+++ b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_smp.h
@@ -10,7 +10,12 @@
#include <lib/mmio.h>
#include <platform_def.h>
+/* === SPM related registers */
+#define SPM_POWERON_CONFIG_EN (SPM_BASE + 0x000)
#define CPU_PWR_STATUS (MCUCFG_BASE + 0xA840)
+/* bit-fields of SPM_POWERON_CONFIG_EN */
+#define PROJECT_CODE (0xB16U << 16)
+#define BCLK_CG_EN BIT(0)
#define SMP_CORE_TIMEOUT_MAX (50000)
#define DO_SMP_CORE_ON_WAIT_TIMEOUT(k_cnt) ({ \
diff --git a/plat/mediatek/drivers/cpu_pm/cpcv3_2/rules.mk b/plat/mediatek/drivers/cpu_pm/cpcv3_2/rules.mk
index 858cf38..b1aa2b4 100644
--- a/plat/mediatek/drivers/cpu_pm/cpcv3_2/rules.mk
+++ b/plat/mediatek/drivers/cpu_pm/cpcv3_2/rules.mk
@@ -14,6 +14,7 @@
LOCAL_SRCS-$(CONFIG_MTK_SMP_EN) += ${LOCAL_DIR}/mt_smp.c
$(eval $(call add_defined_option,CPU_PM_TINYSYS_SUPPORT))
+$(eval $(call add_defined_option,CPU_PM_SPM_CORE_POWERON))
$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/dfd/mt8189/plat_dfd.c b/plat/mediatek/drivers/dfd/mt8189/plat_dfd.c
new file mode 100644
index 0000000..7172e9c
--- /dev/null
+++ b/plat/mediatek/drivers/dfd/mt8189/plat_dfd.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <dfd.h>
+#include <plat_dfd.h>
+
+struct dfd_mcu_ext_pair {
+ uint32_t reg;
+ uint32_t val;
+};
+
+static const struct dfd_mcu_ext_pair ext_init_array[] = {
+ { DFD_INTERNAL_CTL, 0x0018200D },
+ { DFD_INTERNAL_PWR_ON, 0x0000000B },
+ { DFD_INTERNAL_SHIFT_CLK_RATIO, 0x00000000 },
+ { DFD_INTERNAL_TEST_SO_OVER_64, 0x00000001 },
+ { DFD_TEST_SI_0, 0x00000000 },
+ { DFD_TEST_SI_1, 0x00000000 },
+ { DFD_TEST_SI_2, 0x00000000 },
+ { DFD_TEST_SI_3, 0x00000000 },
+ { DFD_INTERNAL_CHAIN_GROUP, 0x00000013 },
+ { DFD_INTERNAL_CHAIN_INV_INFO_LL, 0x00000002 },
+ { DFD_INTERNAL_CHAIN_INV_INFO_LH, 0x40444444 },
+ { DFD_INTERNAL_CHAIN_INV_INFO_HL, 0x00000040 },
+ { DFD_INTERNAL_CHAIN_INV_INFO_HH, 0x00000000 },
+ { DFD_POWER_CTL, 0x000000F9 },
+ { DFD_READ_ADDR, 0x000000F9 },
+ { DFD_V50_GROUP_0_1_DIFF, 1 },
+ { DFD_V50_GROUP_0_2_DIFF, 236 },
+ { DFD_V50_GROUP_0_3_DIFF, 1466 },
+ { DFD_V50_GROUP_0_4_DIFF, 4885 },
+ { DFD_V50_GROUP_0_5_DIFF, 17935 },
+ { DFD_V50_GROUP_0_6_DIFF, 22364 },
+ { DFD_V50_GROUP_0_7_DIFF, 23268 },
+ { DFD_V50_GROUP_0_8_DIFF, 31878 },
+ { DFD_V50_GROUP_0_9_DIFF, 31879 },
+ { DFD_V50_GROUP_0_10_DIFF, 35472 },
+ { DFD_V50_GROUP_0_11_DIFF, 35473 },
+ { DFD_V50_GROUP_0_12_DIFF, 35540 },
+ { DFD_V50_GROUP_0_13_DIFF, 36145 },
+ { DFD_V50_GROUP_0_14_DIFF, 37666 },
+ { DFD_V50_GROUP_0_15_DIFF, 37667 },
+ { DFD_V50_GROUP_0_16_DIFF, 46039 },
+ { DFD_V50_GROUP_0_17_DIFF, 48314 },
+ { DFD_V50_GROUP_0_18_DIFF, 48705 },
+ { DFD_V50_GROUP_0_19_DIFF, 0 },
+ { DFD_V50_GROUP_0_20_DIFF, 0 },
+ { DFD_V50_GROUP_0_21_DIFF, 0 },
+ { DFD_V50_GROUP_0_22_DIFF, 0 },
+ { DFD_V50_GROUP_0_23_DIFF, 0 },
+ { DFD_V50_GROUP_0_24_DIFF, 0 },
+ { DFD_V50_GROUP_0_25_DIFF, 0 },
+ { DFD_V50_GROUP_0_26_DIFF, 0 },
+ { DFD_V50_GROUP_0_27_DIFF, 0 },
+ { DFD_V50_GROUP_0_28_DIFF, 0 },
+ { DFD_V50_GROUP_0_29_DIFF, 0 },
+ { DFD_V50_GROUP_0_30_DIFF, 0 },
+ { DFD_V50_GROUP_0_31_DIFF, 0 },
+ { DFD_V50_GROUP_0_32_DIFF, 0 },
+ { DFD_V50_GROUP_0_33_DIFF, 0 },
+ { DFD_V50_GROUP_0_34_DIFF, 0 },
+ { DFD_V50_GROUP_0_35_DIFF, 0 },
+ { DFD_V50_GROUP_0_36_DIFF, 0 },
+ { DFD_V50_GROUP_0_37_DIFF, 0 },
+ { DFD_V50_GROUP_0_38_DIFF, 0 },
+ { DFD_V50_GROUP_0_39_DIFF, 0 },
+ { DFD_V50_GROUP_0_40_DIFF, 0 },
+ { DFD_V50_GROUP_0_41_DIFF, 0 },
+ { DFD_V50_GROUP_0_42_DIFF, 0 },
+ { DFD_V50_GROUP_0_43_DIFF, 0 },
+ { DFD_V50_GROUP_0_44_DIFF, 0 },
+ { DFD_V50_GROUP_0_45_DIFF, 0 },
+ { DFD_V50_GROUP_0_46_DIFF, 0 },
+ { DFD_V50_GROUP_0_47_DIFF, 0 },
+ { DFD_V50_GROUP_0_48_DIFF, 0 },
+ { DFD_V50_GROUP_0_49_DIFF, 0 },
+ { DFD_V50_GROUP_0_50_DIFF, 0 },
+ { DFD_V50_GROUP_0_51_DIFF, 0 },
+ { DFD_V50_GROUP_0_52_DIFF, 0 },
+ { DFD_V50_GROUP_0_53_DIFF, 0 },
+ { DFD_V50_GROUP_0_54_DIFF, 0 },
+ { DFD_V50_GROUP_0_55_DIFF, 0 },
+ { DFD_V50_GROUP_0_56_DIFF, 0 },
+ { DFD_V50_GROUP_0_57_DIFF, 0 },
+ { DFD_V50_GROUP_0_58_DIFF, 0 },
+ { DFD_V50_GROUP_0_59_DIFF, 0 },
+ { DFD_V50_GROUP_0_60_DIFF, 0 },
+ { DFD_V50_GROUP_0_61_DIFF, 0 },
+ { DFD_V50_GROUP_0_62_DIFF, 0 },
+ { DFD_V50_GROUP_0_63_DIFF, 0x00000001 },
+ { DFD_V50_CHAIN_GROUP_3_0_INFO, 0x00100400 },
+ { DFD_V50_CHAIN_GROUP_7_4_INFO, 0x0b0a0a0a },
+ { DFD_V50_CHAIN_GROUP_11_8_INFO, 0x12120b0b },
+ { DFD_V50_CHAIN_GROUP_15_12_INFO, 0x08080812 },
+ { DFD_V50_CHAIN_GROUP_19_16_INFO, 0x09090909 },
+ { DFD_V50_CHAIN_GROUP_23_20_INFO, 0x0e0e0d05 },
+ { DFD_V50_CHAIN_GROUP_27_24_INFO, 0x0e0e0e0e },
+ { DFD_V50_CHAIN_GROUP_31_28_INFO, 0x0e0e0e0e },
+ { DFD_V50_CHAIN_GROUP_35_32_INFO, 0x06070f0f },
+ { DFD_V50_CHAIN_GROUP_39_36_INFO, 0x06070c06 },
+ { DFD_V50_CHAIN_GROUP_43_40_INFO, 0x06070c06 },
+ { DFD_V50_CHAIN_GROUP_47_44_INFO, 0x06070c06 },
+ { DFD_V50_CHAIN_GROUP_51_48_INFO, 0x06070c06 },
+ { DFD_V50_CHAIN_GROUP_55_52_INFO, 0x06070c06 },
+ { DFD_V50_CHAIN_GROUP_59_56_INFO, 0x00000c06 },
+ { DFD_V50_CHAIN_GROUP_63_60_INFO, 0x11030000 },
+ { DFD_V50_CHAIN_GROUP_67_64_INFO, 0x00000002 },
+ { DFD_V50_CHAIN_GROUP_71_68_INFO, 0x11030101 },
+ { DFD_V50_CHAIN_GROUP_75_72_INFO, 0x00000002 },
+ { DFD_V50_CHAIN_GROUP_79_76_INFO, 0x00000101 },
+ { DFD_V50_CHAIN_GROUP_83_80_INFO, 0x00000000 },
+ { DFD_V50_CHAIN_GROUP_87_84_INFO, 0x00000000 },
+ { DFD_V50_CHAIN_GROUP_91_88_INFO, 0x00000000 },
+ { DFD_V50_CHAIN_GROUP_95_92_INFO, 0x00000000 },
+ { DFD_V50_CHAIN_GROUP_99_96_INFO, 0x00000000 },
+ { DFD_V50_CHAIN_GROUP_103_100_INFO, 0x00000000 },
+ { DFD_V50_CHAIN_GROUP_107_104_INFO, 0x00000000 },
+ { DFD_V50_CHAIN_GROUP_111_108_INFO, 0x00000000 },
+ { DFD_V50_CHAIN_GROUP_115_112_INFO, 0x00000000 },
+ { DFD_V50_CHAIN_GROUP_119_116_INFO, 0x00000000 },
+ { DFD_V50_CHAIN_GROUP_123_120_INFO, 0x00000000 },
+ { DFD_V50_CHAIN_GROUP_127_124_INFO, 0x00000000 },
+};
+
+static uint64_t dfd_cache_dump;
+static bool dfd_enabled;
+static uint64_t dfd_base_addr;
+static uint64_t dfd_chain_length;
+
+void dfd_setup(uint64_t base_addr, uint64_t chain_length, uint64_t cache_dump)
+{
+ unsigned int i;
+
+ mmio_write_32(DFD_INTERNAL_CHAIN_LENGTH_0, chain_length);
+ mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24);
+
+ /* setup global variables for suspend and resume */
+ dfd_enabled = true;
+ dfd_base_addr = base_addr;
+ dfd_chain_length = chain_length;
+ dfd_cache_dump = cache_dump;
+
+ for (i = 0; i < ARRAY_SIZE(ext_init_array); i++)
+ mmio_write_32(ext_init_array[i].reg, ext_init_array[i].val);
+
+ if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) {
+ sync_writel(DFD_V35_ENABLE, 0x1);
+ sync_writel(DFD_V35_TAP_NUMBER, 0xB);
+ sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL);
+ sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL);
+ }
+ dsbsy();
+}
+
+void dfd_resume(void)
+{
+ if (dfd_enabled == true) {
+ dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump);
+ }
+}
diff --git a/plat/mediatek/drivers/dfd/mt8189/plat_dfd.h b/plat/mediatek/drivers/dfd/mt8189/plat_dfd.h
new file mode 100644
index 0000000..415a858
--- /dev/null
+++ b/plat/mediatek/drivers/dfd/mt8189/plat_dfd.h
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_DFD_H
+#define PLAT_DFD_H
+
+#include <lib/mmio.h>
+#include <platform_def.h>
+
+#define sync_writel(addr, val) do { mmio_write_32((addr), (val)); dsbsy(); } while (0)
+
+#define PLAT_MTK_DFD_SETUP_MAGIC (0x99716150)
+#define PLAT_MTK_DFD_READ_MAGIC (0x99716151)
+#define PLAT_MTK_DFD_WRITE_MAGIC (0x99716152)
+
+#define MCU_BIU_BASE (MCUCFG_BASE)
+#define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040)
+#define DFD_CTRL (MCU_BIU_BASE + 0X8040)
+#define DFD_CNT_L (MCU_BIU_BASE + 0X8044)
+#define DFD_CNT_H (MCU_BIU_BASE + 0X8048)
+#define DFD_INTERNAL_CTL (MCU_BIU_BASE + 0XE040)
+#define DFD_INTERNAL_COUNTER (MCU_BIU_BASE + 0XE044)
+#define DFD_INTERNAL_PWR_ON (MCU_BIU_BASE + 0XE048)
+#define DFD_INTERNAL_CHAIN_LENGTH_0 (MCU_BIU_BASE + 0XE04C)
+#define DFD_INTERNAL_SHIFT_CLK_RATIO (MCU_BIU_BASE + 0XE050)
+#define DFD_INTERNAL_COUNTER_RETURN (MCU_BIU_BASE + 0XE054)
+#define DFD_INTERNAL_SRAM_ACCESS (MCU_BIU_BASE + 0XE058)
+#define DFD_FINISH_WAIT_TIME (MCU_BIU_BASE + 0XE05C)
+#define DFD_INTERNAL_CHAIN_GROUP (MCU_BIU_BASE + 0XE060)
+#define DFD_INTERNAL_CHAIN_INV_INFO_LL (MCU_BIU_BASE + 0XE064)
+#define DFD_INTERNAL_CHAIN_INV_INFO_LH (MCU_BIU_BASE + 0XE068)
+#define DFD_INTERNAL_CHAIN_INV_INFO_HL (MCU_BIU_BASE + 0XE06C)
+#define DFD_INTERNAL_CHAIN_INV_INFO_HH (MCU_BIU_BASE + 0XE070)
+#define DFD_INTERNAL_TEST_SO_OVER_64 (MCU_BIU_BASE + 0XE074)
+#define DFD_INTERNAL_MASK_OUT (MCU_BIU_BASE + 0XE078)
+#define DFD_INTERNAL_SW_NS_TRIGGER (MCU_BIU_BASE + 0XE07C)
+#define DFD_INTERNAL_MCSI (MCU_BIU_BASE + 0XE080)
+#define DFD_INTERNAL_MCSI_SEL_STATUS (MCU_BIU_BASE + 0XE084)
+#define DFD_V30_CTL (MCU_BIU_BASE + 0XE088)
+#define DFD_POWER_CTL (MCU_BIU_BASE + 0XE090)
+#define DFD_RESET_ON (MCU_BIU_BASE + 0XE094)
+#define DFD_TEST_SI_0 (MCU_BIU_BASE + 0XE098)
+#define DFD_TEST_SI_1 (MCU_BIU_BASE + 0XE09C)
+#define DFD_STATUS_CLEAN (MCU_BIU_BASE + 0XE0A0)
+#define DFD_STATUS_RETURN (MCU_BIU_BASE + 0XE0A4)
+#define DFD_V35_ENABLE (MCU_BIU_BASE + 0XE0A8)
+#define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0XE0AC)
+#define DFD_V35_TAP_EN (MCU_BIU_BASE + 0XE0B0)
+#define DFD_V35_CTL (MCU_BIU_BASE + 0XE0B4)
+#define DFD_V35_TAP_SEQ0 (MCU_BIU_BASE + 0XE0B8)
+#define DFD_V35_TAP_SEQ1 (MCU_BIU_BASE + 0XE0BC)
+#define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0XE0C0)
+#define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0XE0C4)
+#define DFD_V35_SEQ1_0 (MCU_BIU_BASE + 0XE0C8)
+#define DFD_V35_SEQ1_1 (MCU_BIU_BASE + 0XE0CC)
+#define DFD_V35_SEQ2_0 (MCU_BIU_BASE + 0XE0D0)
+#define DFD_V35_SEQ2_1 (MCU_BIU_BASE + 0XE0D4)
+#define DFD_SOC_CLOCK_STOP_MASK (MCU_BIU_BASE + 0XE0F0)
+#define DFD_HW_TRIGGER_MASK (MCU_BIU_BASE + 0XE0FC)
+#define DFD_V50_ENABLE (MCU_BIU_BASE + 0XE100)
+#define DFD_V50_SELF_TRIGGER_ITERATION (MCU_BIU_BASE + 0XE104)
+#define DFD_V50_START_TRIGGER (MCU_BIU_BASE + 0XE108)
+#define DFD_V50_CPUCK_HALT (MCU_BIU_BASE + 0XE10C)
+#define DFD_V50_26M_RESUME (MCU_BIU_BASE + 0XE110)
+#define DFD_V50_26M_HALT_RELEASE (MCU_BIU_BASE + 0XE114)
+#define DFD_V50_SYSTEM_HALT_TIME (MCU_BIU_BASE + 0XE118)
+#define DFD_V50_GROUP_0_1_DIFF (MCU_BIU_BASE + 0XE11C)
+#define DFD_V50_GROUP_0_2_DIFF (MCU_BIU_BASE + 0XE120)
+#define DFD_V50_GROUP_0_3_DIFF (MCU_BIU_BASE + 0XE124)
+#define DFD_V50_GROUP_0_4_DIFF (MCU_BIU_BASE + 0XE128)
+#define DFD_V50_GROUP_0_5_DIFF (MCU_BIU_BASE + 0XE12C)
+#define DFD_V50_GROUP_0_6_DIFF (MCU_BIU_BASE + 0XE130)
+#define DFD_V50_GROUP_0_7_DIFF (MCU_BIU_BASE + 0XE134)
+#define DFD_V50_GROUP_0_8_DIFF (MCU_BIU_BASE + 0XE138)
+#define DFD_V50_GROUP_0_9_DIFF (MCU_BIU_BASE + 0XE13C)
+#define DFD_V50_GROUP_0_10_DIFF (MCU_BIU_BASE + 0XE140)
+#define DFD_V50_GROUP_0_11_DIFF (MCU_BIU_BASE + 0XE144)
+#define DFD_V50_GROUP_0_12_DIFF (MCU_BIU_BASE + 0XE148)
+#define DFD_V50_GROUP_0_13_DIFF (MCU_BIU_BASE + 0XE14C)
+#define DFD_V50_GROUP_0_14_DIFF (MCU_BIU_BASE + 0XE150)
+#define DFD_V50_GROUP_0_15_DIFF (MCU_BIU_BASE + 0XE154)
+#define DFD_V50_GROUP_0_16_DIFF (MCU_BIU_BASE + 0XE158)
+#define DFD_V50_GROUP_0_17_DIFF (MCU_BIU_BASE + 0XE15C)
+#define DFD_V50_GROUP_0_18_DIFF (MCU_BIU_BASE + 0XE160)
+#define DFD_V50_GROUP_0_19_DIFF (MCU_BIU_BASE + 0XE164)
+#define DFD_V50_GROUP_0_20_DIFF (MCU_BIU_BASE + 0XE168)
+#define DFD_V50_GROUP_0_21_DIFF (MCU_BIU_BASE + 0XE16C)
+#define DFD_V50_GROUP_0_22_DIFF (MCU_BIU_BASE + 0XE170)
+#define DFD_V50_GROUP_0_23_DIFF (MCU_BIU_BASE + 0XE174)
+#define DFD_V50_GROUP_0_24_DIFF (MCU_BIU_BASE + 0XE178)
+#define DFD_V50_GROUP_0_25_DIFF (MCU_BIU_BASE + 0XE17C)
+#define DFD_V50_GROUP_0_26_DIFF (MCU_BIU_BASE + 0XE180)
+#define DFD_V50_GROUP_0_27_DIFF (MCU_BIU_BASE + 0XE184)
+#define DFD_V50_GROUP_0_28_DIFF (MCU_BIU_BASE + 0XE188)
+#define DFD_V50_GROUP_0_29_DIFF (MCU_BIU_BASE + 0XE18C)
+#define DFD_V50_GROUP_0_30_DIFF (MCU_BIU_BASE + 0XE190)
+#define DFD_V50_GROUP_0_31_DIFF (MCU_BIU_BASE + 0XE194)
+#define DFD_V50_CHAIN_GROUP_3_0_INFO (MCU_BIU_BASE + 0XE198)
+#define DFD_V50_CHAIN_GROUP_7_4_INFO (MCU_BIU_BASE + 0XE19C)
+#define DFD_V50_CHAIN_GROUP_11_8_INFO (MCU_BIU_BASE + 0XE1A0)
+#define DFD_V50_CHAIN_GROUP_15_12_INFO (MCU_BIU_BASE + 0XE1A4)
+#define DFD_V50_CHAIN_GROUP_19_16_INFO (MCU_BIU_BASE + 0XE1A8)
+#define DFD_V50_CHAIN_GROUP_23_20_INFO (MCU_BIU_BASE + 0XE1AC)
+#define DFD_V50_CHAIN_GROUP_27_24_INFO (MCU_BIU_BASE + 0XE1B0)
+#define DFD_V50_CHAIN_GROUP_31_28_INFO (MCU_BIU_BASE + 0XE1B4)
+#define DFD_V50_CHAIN_GROUP_35_32_INFO (MCU_BIU_BASE + 0XE1B8)
+#define DFD_V50_CHAIN_GROUP_39_36_INFO (MCU_BIU_BASE + 0XE1BC)
+#define DFD_V50_CHAIN_GROUP_43_40_INFO (MCU_BIU_BASE + 0XE1C0)
+#define DFD_V50_CHAIN_GROUP_47_44_INFO (MCU_BIU_BASE + 0XE1C4)
+#define DFD_V50_CHAIN_GROUP_51_48_INFO (MCU_BIU_BASE + 0XE1C8)
+#define DFD_V50_CHAIN_GROUP_55_52_INFO (MCU_BIU_BASE + 0XE1CC)
+#define DFD_V50_CHAIN_GROUP_59_56_INFO (MCU_BIU_BASE + 0XE1D0)
+#define DFD_V50_CHAIN_GROUP_63_60_INFO (MCU_BIU_BASE + 0XE1D4)
+#define DFD_V50_CHAIN_GROUP_67_64_INFO (MCU_BIU_BASE + 0XE1D8)
+#define DFD_V50_CHAIN_GROUP_71_68_INFO (MCU_BIU_BASE + 0XE1DC)
+#define DFD_V50_CHAIN_GROUP_75_72_INFO (MCU_BIU_BASE + 0XE1E0)
+#define DFD_V50_CHAIN_GROUP_79_76_INFO (MCU_BIU_BASE + 0XE1E4)
+#define DFD_V50_CHAIN_GROUP_83_80_INFO (MCU_BIU_BASE + 0XE1E8)
+#define DFD_V50_CHAIN_GROUP_87_84_INFO (MCU_BIU_BASE + 0XE1EC)
+#define DFD_V50_CHAIN_GROUP_91_88_INFO (MCU_BIU_BASE + 0XE1F0)
+#define DFD_V50_CHAIN_GROUP_95_92_INFO (MCU_BIU_BASE + 0XE1F4)
+#define DFD_V50_CHAIN_GROUP_99_96_INFO (MCU_BIU_BASE + 0XE1F8)
+#define DFD_V50_CHAIN_GROUP_103_100_INFO (MCU_BIU_BASE + 0XE1FC)
+#define DFD_V50_CHAIN_GROUP_107_104_INFO (MCU_BIU_BASE + 0XE200)
+#define DFD_V50_CHAIN_GROUP_111_108_INFO (MCU_BIU_BASE + 0XE204)
+#define DFD_V50_CHAIN_GROUP_115_112_INFO (MCU_BIU_BASE + 0XE208)
+#define DFD_V50_CHAIN_GROUP_119_116_INFO (MCU_BIU_BASE + 0XE20C)
+#define DFD_V50_CHAIN_GROUP_123_120_INFO (MCU_BIU_BASE + 0XE210)
+#define DFD_V50_CHAIN_GROUP_127_124_INFO (MCU_BIU_BASE + 0XE214)
+#define DFD_TEST_SI_2 (MCU_BIU_BASE + 0XE218)
+#define DFD_TEST_SI_3 (MCU_BIU_BASE + 0XE21C)
+#define DFD_TEST_SO (MCU_BIU_BASE + 0XE220)
+#define DFD_BUS_HALT_TIME (MCU_BIU_BASE + 0XE224)
+#define DFD_READ_ADDR (MCU_BIU_BASE + 0XE228)
+#define DFD_V50_CLK_STOP_TIME (MCU_BIU_BASE + 0XE22C)
+#define DFD_V50_GROUP_0_32_DIFF (MCU_BIU_BASE + 0XE230)
+#define DFD_V50_GROUP_0_33_DIFF (MCU_BIU_BASE + 0XE234)
+#define DFD_V50_GROUP_0_34_DIFF (MCU_BIU_BASE + 0XE238)
+#define DFD_V50_GROUP_0_35_DIFF (MCU_BIU_BASE + 0XE23C)
+#define DFD_V50_GROUP_0_36_DIFF (MCU_BIU_BASE + 0XE240)
+#define DFD_V50_GROUP_0_37_DIFF (MCU_BIU_BASE + 0XE244)
+#define DFD_V50_GROUP_0_38_DIFF (MCU_BIU_BASE + 0XE248)
+#define DFD_V50_GROUP_0_39_DIFF (MCU_BIU_BASE + 0XE24C)
+#define DFD_V50_GROUP_0_40_DIFF (MCU_BIU_BASE + 0XE250)
+#define DFD_V50_GROUP_0_41_DIFF (MCU_BIU_BASE + 0XE254)
+#define DFD_V50_GROUP_0_42_DIFF (MCU_BIU_BASE + 0XE258)
+#define DFD_V50_GROUP_0_43_DIFF (MCU_BIU_BASE + 0XE25C)
+#define DFD_V50_GROUP_0_44_DIFF (MCU_BIU_BASE + 0XE260)
+#define DFD_V50_GROUP_0_45_DIFF (MCU_BIU_BASE + 0XE264)
+#define DFD_V50_GROUP_0_46_DIFF (MCU_BIU_BASE + 0XE268)
+#define DFD_V50_GROUP_0_47_DIFF (MCU_BIU_BASE + 0XE26C)
+#define DFD_V50_GROUP_0_48_DIFF (MCU_BIU_BASE + 0XE270)
+#define DFD_V50_GROUP_0_49_DIFF (MCU_BIU_BASE + 0XE274)
+#define DFD_V50_GROUP_0_50_DIFF (MCU_BIU_BASE + 0XE278)
+#define DFD_V50_GROUP_0_51_DIFF (MCU_BIU_BASE + 0XE27C)
+#define DFD_V50_GROUP_0_52_DIFF (MCU_BIU_BASE + 0XE280)
+#define DFD_V50_GROUP_0_53_DIFF (MCU_BIU_BASE + 0XE284)
+#define DFD_V50_GROUP_0_54_DIFF (MCU_BIU_BASE + 0XE288)
+#define DFD_V50_GROUP_0_55_DIFF (MCU_BIU_BASE + 0XE28C)
+#define DFD_V50_GROUP_0_56_DIFF (MCU_BIU_BASE + 0XE290)
+#define DFD_V50_GROUP_0_57_DIFF (MCU_BIU_BASE + 0XE294)
+#define DFD_V50_GROUP_0_58_DIFF (MCU_BIU_BASE + 0XE298)
+#define DFD_V50_GROUP_0_59_DIFF (MCU_BIU_BASE + 0XE29C)
+#define DFD_V50_GROUP_0_60_DIFF (MCU_BIU_BASE + 0XE2A0)
+#define DFD_V50_GROUP_0_61_DIFF (MCU_BIU_BASE + 0XE2A4)
+#define DFD_V50_GROUP_0_62_DIFF (MCU_BIU_BASE + 0XE2A8)
+#define DFD_V50_GROUP_0_63_DIFF (MCU_BIU_BASE + 0XE2AC)
+
+#define DFD_O_PROTECT_EN_REG (0x10001220)
+#define DFD_O_INTRF_MCU_PWR_CTL_MASK (0x10001A3C)
+#define DFD_O_SET_BASEADDR_REG (0x10043010)
+#define DFD_O_REG_0 (0x10001390)
+
+#define DFD_CACHE_DUMP_ENABLE (1U)
+
+#define DFD_V35_TAP_EN_VAL (0x43FF)
+#define DFD_V35_SEQ0_0_VAL (0x63668820)
+#define DFD_READ_ADDR_VAL (0x40000008)
+#define DFD_CHAIN_LENGTH_VAL (0xFFFFFFFF)
+
+#endif /* PLAT_DFD_H */
diff --git a/plat/mediatek/drivers/disp/mt8189/mtk_disp_plat.c b/plat/mediatek/drivers/disp/mt8189/mtk_disp_plat.c
new file mode 100644
index 0000000..cefba82
--- /dev/null
+++ b/plat/mediatek/drivers/disp/mt8189/mtk_disp_plat.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mtk_disp_priv.h>
+#include <mtk_mmap_pool.h>
+#include <platform_def.h>
+
+/* disp config */
+#define MMSYS_SEC_DIS_0 (0xA00)
+#define MMSYS_SEC_DIS_1 (0xA04)
+#define MMSYS_SEC_DIS_2 (0xA08)
+#define MMSYS_SHADOW (0xC00)
+#define MMSYS_CB_CON (0xC0C)
+#define MMSYS_CG_CON (0x110)
+
+const struct mtk_disp_config mt8189_disp_cfg[] = {
+ /*SECURITY0*/
+ DISP_CFG_ENTRY(MMSYS_CONFIG_BASE + MMSYS_SEC_DIS_0, 0xFFFFFFFF),
+ /*SECURITY1*/
+ DISP_CFG_ENTRY(MMSYS_CONFIG_BASE + MMSYS_SEC_DIS_1, 0xFFFFFFFF),
+ /*SECURITY2*/
+ DISP_CFG_ENTRY(MMSYS_CONFIG_BASE + MMSYS_SEC_DIS_2, 0xFFFFFFFF),
+ /*SHADOW*/
+ DISP_CFG_ENTRY(MMSYS_CONFIG_BASE + MMSYS_SHADOW, 0x1),
+ /*CROSSBAR*/
+ DISP_CFG_ENTRY(MMSYS_CONFIG_BASE + MMSYS_CB_CON, 0x00FF0000),
+ /*CG_BIT*/
+ DISP_CFG_ENTRY(MMSYS_CONFIG_BASE + MMSYS_CG_CON, 0x10000),
+};
+
+const struct mtk_disp_config *disp_cfg = &mt8189_disp_cfg[0];
+const size_t disp_cfg_count = ARRAY_SIZE(mt8189_disp_cfg);
diff --git a/plat/mediatek/drivers/disp/mtk_disp_priv.h b/plat/mediatek/drivers/disp/mtk_disp_priv.h
new file mode 100644
index 0000000..9ae1162
--- /dev/null
+++ b/plat/mediatek/drivers/disp/mtk_disp_priv.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DISP_PRIV_H
+#define DISP_PRIV_H
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#define DISP_CFG_ENTRY(base_reg, mask) \
+ { .base = (base_reg), .ns_mask = (mask)}
+
+struct mtk_disp_config {
+ uint32_t base;
+ uint32_t ns_mask;
+};
+
+enum DISP_ATF_CMD {
+ DISP_ATF_CMD_CONFIG_DISP_CONFIG,
+ DISP_ATF_CMD_COUNT,
+};
+
+/* disable secure mode for disp */
+extern const struct mtk_disp_config *disp_cfg;
+extern const size_t disp_cfg_count;
+
+#endif /* DISP_PRIV_H */
diff --git a/plat/mediatek/drivers/disp/mtk_disp_smc.c b/plat/mediatek/drivers/disp/mtk_disp_smc.c
new file mode 100644
index 0000000..746ba46
--- /dev/null
+++ b/plat/mediatek/drivers/disp/mtk_disp_smc.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <mtk_disp_priv.h>
+#include <mtk_sip_svc.h>
+
+/* defination */
+static int mtk_disp_disable_sec(uint32_t larb_id, uint32_t mmu_en_msk)
+{
+ const struct mtk_disp_config *disp_cfg_t;
+ uint32_t cfg_cnt;
+
+ for (cfg_cnt = 0; cfg_cnt < (disp_cfg_count - 1); cfg_cnt++) {
+ disp_cfg_t = &disp_cfg[cfg_cnt];
+ mmio_setbits_32(disp_cfg_t->base, disp_cfg_t->ns_mask);
+ }
+
+ disp_cfg_t = &disp_cfg[disp_cfg_count - 1];
+ mmio_clrbits_32(disp_cfg_t->base, disp_cfg_t->ns_mask);
+
+ return MTK_SIP_E_SUCCESS;
+}
+
+static u_register_t mtk_disp_handler(u_register_t x1, u_register_t x2,
+ u_register_t x3, u_register_t x4,
+ void *handle, struct smccc_res *smccc_ret)
+{
+ uint32_t cmd_id = x1, mdl_id = x2, val = x3;
+ int ret = MTK_SIP_E_NOT_SUPPORTED;
+
+ (void)x4;
+ (void)handle;
+ (void)smccc_ret;
+
+ switch (cmd_id) {
+ case DISP_ATF_CMD_CONFIG_DISP_CONFIG:
+ ret = mtk_disp_disable_sec(mdl_id, val);
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+DECLARE_SMC_HANDLER(MTK_SIP_DISP_CONTROL, mtk_disp_handler);
diff --git a/plat/mediatek/drivers/disp/rules.mk b/plat/mediatek/drivers/disp/rules.mk
new file mode 100644
index 0000000..d05935e
--- /dev/null
+++ b/plat/mediatek/drivers/disp/rules.mk
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := mtk_disp
+
+LOCAL_SRCS-y := ${LOCAL_DIR}/mtk_disp_smc.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/${MTK_SOC}/mtk_disp_plat.c
+
+PLAT_INCLUDES += -I${LOCAL_DIR}
+PLAT_INCLUDES += -I${LOCAL_DIR}/${MTK_SOC}
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/mtcmos/mt8196/mtcmos.c b/plat/mediatek/drivers/mtcmos/mtcmos.c
similarity index 95%
rename from plat/mediatek/drivers/mtcmos/mt8196/mtcmos.c
rename to plat/mediatek/drivers/mtcmos/mtcmos.c
index ee3849f..acd41ee 100644
--- a/plat/mediatek/drivers/mtcmos/mt8196/mtcmos.c
+++ b/plat/mediatek/drivers/mtcmos/mtcmos.c
@@ -50,7 +50,7 @@
#define MTCMOS_TIMEOUT_US 500
-#define ETIMEDOUT 25
+#define MTCMOS_ETIMEDOUT 25
static spinlock_t mtcmos_ctrl_lock;
@@ -69,7 +69,7 @@
ERROR("%s(0x%x, 0x%x, %d) timeout, reg_val=0x%x\n",
__func__, reg, mask, is_set, mmio_read_32(reg));
- return -ETIMEDOUT;
+ return -MTCMOS_ETIMEDOUT;
}
@@ -81,7 +81,7 @@
mmio_write_32(SPM_BUS_PROTECT_EN_SET, mask);
if (mtcmos_wait_for_state(SPM_BUS_PROTECT_RDY_STA, mask,
true))
- return -ETIMEDOUT;
+ return -MTCMOS_ETIMEDOUT;
} else if (state == RELEASE_BUS_PROTECT) {
mmio_write_32(SPM_BUS_PROTECT_EN_CLR, mask);
}
@@ -91,7 +91,7 @@
return 0;
}
-int spm_mtcmos_ctrl(enum mtcmos_state state, uintptr_t reg, uint32_t mask)
+static int spm_mtcmos_ctrl(enum mtcmos_state state, uintptr_t reg, uint32_t mask)
{
int ret = 0;
diff --git a/plat/mediatek/drivers/mtcmos/mt8196/mtcmos.h b/plat/mediatek/drivers/mtcmos/mtcmos.h
similarity index 62%
rename from plat/mediatek/drivers/mtcmos/mt8196/mtcmos.h
rename to plat/mediatek/drivers/mtcmos/mtcmos.h
index 39902bc..925bd09 100644
--- a/plat/mediatek/drivers/mtcmos/mt8196/mtcmos.h
+++ b/plat/mediatek/drivers/mtcmos/mtcmos.h
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8196_MTCMOS_H_
-#define PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8196_MTCMOS_H_
+#ifndef MTCMOS_H
+#define MTCMOS_H
enum mtcmos_state {
STA_POWER_DOWN,
@@ -15,4 +15,4 @@
int spm_mtcmos_ctrl_ufs0(enum mtcmos_state state);
int spm_mtcmos_ctrl_ufs0_phy(enum mtcmos_state state);
-#endif /* PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8196_MTCMOS_H_ */
+#endif /* MTCMOS_H */
diff --git a/plat/mediatek/drivers/mtcmos/rules.mk b/plat/mediatek/drivers/mtcmos/rules.mk
index a8f1df2..c1964a7 100644
--- a/plat/mediatek/drivers/mtcmos/rules.mk
+++ b/plat/mediatek/drivers/mtcmos/rules.mk
@@ -6,8 +6,8 @@
LOCAL_DIR := $(call GET_LOCAL_DIR)
MODULE := mtcmos
-LOCAL_SRCS-y := $(LOCAL_DIR)/${MTK_SOC}/mtcmos.c
+LOCAL_SRCS-y := $(LOCAL_DIR)/mtcmos.c
-PLAT_INCLUDES += -I${LOCAL_DIR}/${MTK_SOC}
+PLAT_INCLUDES += -I${LOCAL_DIR}
$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/pmic/mt6359p/mt6359p_psc.c b/plat/mediatek/drivers/pmic/mt6359p/mt6359p_psc.c
new file mode 100644
index 0000000..6c0eb9c
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt6359p/mt6359p_psc.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+#include <drivers/pmic/pmic_psc.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <pmic_wrap_init_common.h>
+
+#include "registers.h"
+
+static const struct pmic_psc_reg mt6359p_psc_regs[] = {
+ PMIC_PSC_REG(RG_PWRHOLD, MT6359P_PPCCTL0, 0),
+ PMIC_PSC_REG(RG_CRST, MT6359P_PPCCTL1, 0),
+ PMIC_PSC_REG(RG_SMART_RST_SDN_EN, MT6359P_STRUP_CON12, 9),
+ PMIC_PSC_REG(RG_SMART_RST_MODE, MT6359P_STRUP_CON12, 10),
+};
+
+static const struct pmic_psc_config mt6359p_psc_config = {
+ .read_field = pwrap_read_field,
+ .write_field = pwrap_write_field,
+ .regs = mt6359p_psc_regs,
+ .reg_size = ARRAY_SIZE(mt6359p_psc_regs),
+};
+
+static int mt6359p_psc_init(void)
+{
+ return pmic_psc_register(&mt6359p_psc_config);
+}
+
+MTK_PLAT_SETUP_0_INIT(mt6359p_psc_init);
diff --git a/plat/mediatek/drivers/pmic/mt6359p/registers.h b/plat/mediatek/drivers/pmic/mt6359p/registers.h
new file mode 100644
index 0000000..f1b2a6d
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt6359p/registers.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef REGISTER_H
+#define REGISTER_H
+
+/* PMIC Registers for PSC */
+#define MT6359P_PPCCTL0 0xa08
+#define MT6359P_PPCCTL1 0xa0a
+#define MT6359P_STRUP_CON12 0xa12
+
+#endif /* REGISTER_H */
diff --git a/plat/mediatek/drivers/pmic/mt6359p/rules.mk b/plat/mediatek/drivers/pmic/mt6359p/rules.mk
new file mode 100644
index 0000000..39908f8
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt6359p/rules.mk
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := mt6359p
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/${PMIC_CHIP}_psc.c
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/pmic/mt8189/pmic_lowpower_init.c b/plat/mediatek/drivers/pmic/mt8189/pmic_lowpower_init.c
new file mode 100644
index 0000000..aa90b86
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt8189/pmic_lowpower_init.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+
+#include <drivers/pmic/mt6319_lowpower_reg.h>
+#include <drivers/pmic/mt6359p_set_lowpower.h>
+#include <drivers/pmic/pmic_swap_api.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <pmic_wrap_init_common.h>
+
+#define PMIC_SLVID_BUCK_SET_LP(_chip, _slvid, _name, _user, _en, _mode, _cfg) \
+{ \
+ struct spmi_device *sdev = lowpower_sdev[_slvid]; \
+ if (sdev) {\
+ pmic_spmi_update_bits(sdev, \
+ _chip##_RG_BUCK_##_name##_##_user##_OP_CFG_ADDR, \
+ 1 << _user, \
+ _cfg ? 1 << _user : 0); \
+ pmic_spmi_update_bits(sdev, \
+ _chip##_RG_BUCK_##_name##_##_user##_OP_MODE_ADDR, \
+ 1 << _user, \
+ _mode ? 1 << _user : 0); \
+ pmic_spmi_update_bits(sdev, \
+ _chip##_RG_BUCK_##_name##_##_user##_OP_EN_ADDR, \
+ 1 << _user, \
+ _en ? 1 << _user : 0); \
+ } \
+}
+
+struct spmi_device *lowpower_sdev[SPMI_MAX_SLAVE_ID];
+
+static const uint8_t lowpower_slvid_arr[] = {
+ SPMI_SLAVE_7,
+};
+
+static int pmic_spmi_update_bits(struct spmi_device *sdev, uint16_t reg,
+ uint8_t mask, uint8_t val)
+{
+ uint8_t orig = 0;
+ int ret = 0;
+
+ ret = spmi_ext_register_readl(sdev, reg, &orig, 1);
+ if (ret < 0)
+ return ret;
+ orig &= ~mask;
+ orig |= val & mask;
+ ret = spmi_ext_register_writel(sdev, reg, &orig, 1);
+ return ret;
+}
+
+static int pmic_lowpower_init(void)
+{
+ uint8_t i, slvid;
+
+ for (i = 0; i < ARRAY_SIZE(lowpower_slvid_arr); i++) {
+ slvid = lowpower_slvid_arr[i];
+ lowpower_sdev[slvid] = get_spmi_device(SPMI_MASTER_P_1, slvid);
+ if (!lowpower_sdev[slvid])
+ return -ENODEV;
+ }
+
+ PMIC_SLVID_BUCK_SET_LP(MT6319, SPMI_SLAVE_7, VBUCK3, HW0, true, OP_MODE_LP, HW_LP);
+
+ PMIC_BUCK_SET_LP(MT6359P, VPROC2, HW0, true, OP_MODE_LP, HW_OFF);
+ PMIC_BUCK_SET_LP(MT6359P, VPROC2, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_BUCK_SET_LP(MT6359P, VGPU11, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_BUCK_SET_LP(MT6359P, VGPU11, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_BUCK_SET_LP(MT6359P, VS1, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_BUCK_SET_LP(MT6359P, VS1, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_BUCK_SET_LP(MT6359P, VS2, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_BUCK_SET_LP(MT6359P, VS2, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VRF12, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VRF12, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VA12, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VA12, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VA09, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VA09, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VAUX18, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VAUX18, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VXO22, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VXO22, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VUSB, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VUSB, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VUFS, HW0, true, OP_MODE_LP, HW_LP);
+
+ return 0;
+}
+
+MTK_PLAT_SETUP_0_INIT(pmic_lowpower_init);
diff --git a/plat/mediatek/drivers/pmic/mt8189/pmic_shutdown_cfg.c b/plat/mediatek/drivers/pmic/mt8189/pmic_shutdown_cfg.c
new file mode 100644
index 0000000..dbb5852
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt8189/pmic_shutdown_cfg.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "../mt6359p/registers.h"
+#include <drivers/pmic/pmic_shutdown_cfg.h>
+#include <drivers/spmi/spmi_common.h>
+#include <drivers/spmi_api.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <pmic_wrap_init_common.h>
+
+#define MT6319_RG_SEQ_OFF 0x2d
+#define MT6319_TOP_RST_MISC_CLR 0x128
+#define MT6319_TOP_DIG_WPK_H 0x3a9
+#define MT6319_TOP_DIG_WPK_H_MASK 0xFF
+#define MT6319_TOP_DIG_WPK_H_SHIFT 0
+#define MT6319_TOP_DIG_WPK 0x3a8
+#define MT6319_TOP_DIG_WPK_MASK 0xFF
+#define MT6319_TOP_DIG_WPK_SHIFT 0
+
+
+int pmic_shutdown_cfg(void)
+{
+/*
+ * In mt8189, the pmic_shutdown_cfg() api does not need to read and write the
+ * pmic register to determine the return value and in order not to modify the
+ * common code to affect other ICs, the pmic_shutdown_cfg() will directly
+ * return 1.
+ */
+ return 1;
+}
+
+static void shutdown_slave_dev(struct spmi_device *dev)
+{
+ spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK_H, 0x63,
+ MT6319_TOP_DIG_WPK_H_MASK,
+ MT6319_TOP_DIG_WPK_H_SHIFT);
+ spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK, 0x15,
+ MT6319_TOP_DIG_WPK_MASK,
+ MT6319_TOP_DIG_WPK_SHIFT);
+
+ /* Disable WDTRSTB_EN */
+ spmi_ext_register_writel_field(dev, MT6319_TOP_RST_MISC_CLR, 1, 0x1, 0);
+ /* Normal sequence power off when PAD_EN falling */
+ spmi_ext_register_writel_field(dev, MT6319_RG_SEQ_OFF, 1, 0x1, 0);
+
+ spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK_H, 0,
+ MT6319_TOP_DIG_WPK_H_MASK,
+ MT6319_TOP_DIG_WPK_H_SHIFT);
+ spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK, 0,
+ MT6319_TOP_DIG_WPK_MASK,
+ MT6319_TOP_DIG_WPK_SHIFT);
+
+}
+
+int spmi_shutdown(void)
+{
+ struct spmi_device *mt6319_sdev;
+
+ mt6319_sdev = get_spmi_device(SPMI_MASTER_P_1, SPMI_SLAVE_7);
+ if (!mt6319_sdev)
+ return -ENODEV;
+ shutdown_slave_dev(mt6319_sdev);
+
+ if (mmio_read_32((uintptr_t)CHIP_ID_REG) == MTK_CPU_ID_MT8189 &&
+ mmio_read_32((uintptr_t)CPU_SEG_ID_REG) == MTK_CPU_SEG_ID_MT8189H) {
+ mt6319_sdev = get_spmi_device(SPMI_MASTER_P_1, SPMI_SLAVE_8);
+ if (!mt6319_sdev)
+ return -ENODEV;
+ shutdown_slave_dev(mt6319_sdev);
+ }
+
+ /* clear main pmic power hold */
+ pwrap_write_field(MT6359P_PPCCTL0, 0, 0x1, 0);
+
+ return 0;
+}
diff --git a/plat/mediatek/drivers/pmic/mt8189/pmic_swap_api.c b/plat/mediatek/drivers/pmic/mt8189/pmic_swap_api.c
new file mode 100644
index 0000000..0310389
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt8189/pmic_swap_api.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+
+#include <drivers/pmic/pmic_swap_api.h>
+
+/* No need to check second pmic mt6369 */
+bool is_second_pmic_pp_swap(void)
+{
+ return false;
+}
diff --git a/plat/mediatek/drivers/pmic/rules.mk b/plat/mediatek/drivers/pmic/rules.mk
index 0280df8..13ce658 100644
--- a/plat/mediatek/drivers/pmic/rules.mk
+++ b/plat/mediatek/drivers/pmic/rules.mk
@@ -8,15 +8,15 @@
MODULE := pmic
-ifneq (${PMIC_CHIP}, mt6363)
-LOCAL_SRCS-y += ${LOCAL_DIR}/pmic.c
-PLAT_INCLUDES += -I${LOCAL_DIR}/
-else
-LOCAL_SRCS-y := ${LOCAL_DIR}/pmic_psc.c
-LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_common_swap_api.c
+ifeq (${CONFIG_MTK_PMIC_SHUTDOWN_V2}, y)
+LOCAL_SRCS-y := ${LOCAL_DIR}/pmic_common_swap_api.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_psc.c
LOCAL_SRCS-${CONFIG_MTK_PMIC_LOWPOWER} += ${LOCAL_DIR}/${MTK_SOC}/pmic_lowpower_init.c
LOCAL_SRCS-${CONFIG_MTK_PMIC_LOWPOWER} += ${LOCAL_DIR}/${MTK_SOC}/pmic_swap_api.c
LOCAL_SRCS-${CONFIG_MTK_PMIC_SHUTDOWN_CFG} += ${LOCAL_DIR}/${MTK_SOC}/pmic_shutdown_cfg.c
+else
+LOCAL_SRCS-y += ${LOCAL_DIR}/pmic.c
+PLAT_INCLUDES += -I${LOCAL_DIR}/
endif
$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/pmic_wrap/mt8189/pmic_wrap_init.h b/plat/mediatek/drivers/pmic_wrap/mt8189/pmic_wrap_init.h
new file mode 100644
index 0000000..9647326
--- /dev/null
+++ b/plat/mediatek/drivers/pmic_wrap/mt8189/pmic_wrap_init.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_WRAP_INIT_H
+#define PMIC_WRAP_INIT_H
+
+#include <platform_def.h>
+#include <pmic_wrap_init_common.h>
+
+#define PWRAP_DEBUG 0
+
+/* PMIC_WRAP registers */
+struct mt8189_pmic_wrap_regs {
+ uint32_t init_done;
+ uint32_t reserved[511];
+ struct {
+ uint32_t cmd;
+ uint32_t wdata;
+ uint32_t reserved1[3];
+ uint32_t rdata;
+ uint32_t reserved2[3];
+ uint32_t vldclr;
+ uint32_t sta;
+ uint32_t reserved3[5];
+ } wacs[4];
+};
+
+static struct mt8189_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE;
+
+#define PMIF_SPI_SWINF_NO 2
+
+#endif /* PMIC_WRAP_INIT_H */
diff --git a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h
index 4ba1f5c..3a30435 100644
--- a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h
+++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h
@@ -12,10 +12,14 @@
#include "platform_def.h"
/* external API */
+int32_t pmic_wrap_test(void);
int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
+int32_t pwrap_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift);
int32_t pwrap_write(uint32_t adr, uint32_t wdata);
+int32_t pwrap_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift);
-#define GET_WACS_FSM(x) ((x >> 1) & 0x7)
+#define GET_SWINF_INIT_DONE(x) ((x>>15) & 0x00000001)
+#define GET_WACS_FSM(x) ((x >> 1) & 0x7)
/* macro for SWINF_FSM */
#define SWINF_FSM_IDLE (0x00)
@@ -43,6 +47,11 @@
E_PWR_INIT_SIDLY_FAIL = 11,
E_PWR_RESET_TIMEOUT = 12,
E_PWR_TIMEOUT = 13,
+ E_PWR_INVALID_SWINF = 14,
+ E_PWR_INVALID_CMD = 15,
+ E_PWR_INVALID_PMIFID = 16,
+ E_PWR_INVALID_SLVID = 17,
+ E_PWR_INVALID_BYTECNT = 18,
E_PWR_INIT_RESET_SPI = 20,
E_PWR_INIT_SIDLY = 21,
E_PWR_INIT_REG_CLOCK = 22,
diff --git a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v3.c b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v3.c
new file mode 100644
index 0000000..4e9c321
--- /dev/null
+++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v3.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/spinlock.h>
+
+#include <mtk_mmap_pool.h>
+#include "pmic_wrap_init.h"
+#include "pmic_wrap_v3.h"
+
+static spinlock_t wrp_lock;
+
+static uint32_t pwrap_check_idle(uintptr_t wacs_register, uintptr_t wacs_vldclr_register,
+ uint32_t timeout_us)
+{
+ uint32_t reg_rdata = 0U, retry;
+
+ retry = (timeout_us + PWRAP_POLL_STEP_US) / PWRAP_POLL_STEP_US;
+ while (retry != 0) {
+ udelay(PWRAP_POLL_STEP_US);
+ reg_rdata = mmio_read_32(wacs_register);
+ /* if last read command timeout,clear vldclr bit
+ * read command state machine:FSM_REQ-->wfdle-->WFVLDCLR;
+ * write:FSM_REQ-->idle
+ */
+ switch (GET_WACS_FSM(reg_rdata)) {
+ case SWINF_FSM_WFVLDCLR:
+ mmio_write_32(wacs_vldclr_register, 0x1);
+ INFO("WACS_FSM = SWINF_FSM_WFVLDCLR\n");
+ break;
+ case SWINF_FSM_WFDLE:
+ INFO("WACS_FSM = SWINF_FSM_WFDLE\n");
+ break;
+ case SWINF_FSM_REQ:
+ INFO("WACS_FSM = SWINF_FSM_REQ\n");
+ break;
+ case SWINF_FSM_IDLE:
+ goto done;
+ default:
+ break;
+ }
+ retry--;
+ }
+
+done:
+ if (retry == 0) {
+ /* timeout */
+ return E_PWR_WAIT_IDLE_TIMEOUT;
+ }
+
+ return 0U;
+}
+
+static uint32_t pwrap_check_vldclr(uintptr_t wacs_register, uint32_t timeout_us)
+{
+ uint32_t reg_rdata = 0U, retry;
+
+ retry = (timeout_us + PWRAP_POLL_STEP_US) / PWRAP_POLL_STEP_US;
+ while (retry != 0) {
+ udelay(PWRAP_POLL_STEP_US);
+ reg_rdata = mmio_read_32(wacs_register);
+ if (GET_WACS_FSM(reg_rdata) == SWINF_FSM_WFVLDCLR) {
+ break;
+ }
+ retry--;
+ }
+
+ if (retry == 0) {
+ /* timeout */
+ return E_PWR_WAIT_IDLE_TIMEOUT;
+ }
+
+ return 0U;
+}
+
+static int32_t pwrap_swinf_acc(uint32_t swinf_no, uint32_t cmd, uint32_t write,
+ uint32_t pmifid, uint32_t slvid, uint32_t addr,
+ uint32_t bytecnt, uint32_t wdata, uint32_t *rdata)
+{
+ uint32_t reg_rdata = 0x0;
+ int32_t ret = 0x0;
+
+ /* Check argument validation */
+ if ((swinf_no & ~(0x3)) != 0)
+ return -E_PWR_INVALID_SWINF;
+ if ((cmd & ~(0x3)) != 0)
+ return -E_PWR_INVALID_CMD;
+ if ((write & ~(0x1)) != 0)
+ return -E_PWR_INVALID_RW;
+ if ((pmifid & ~(0x1)) != 0)
+ return -E_PWR_INVALID_PMIFID;
+ if ((slvid & ~(0xf)) != 0)
+ return -E_PWR_INVALID_SLVID;
+ if ((addr & ~(0xffff)) != 0)
+ return -E_PWR_INVALID_ADDR;
+ if ((bytecnt & ~(0x1)) != 0)
+ return -E_PWR_INVALID_BYTECNT;
+ if ((wdata & ~(0xffff)) != 0)
+ return -E_PWR_INVALID_WDAT;
+
+ spin_lock(&wrp_lock);
+ /* Check whether INIT_DONE is set */
+ if (pmifid == 0)
+ reg_rdata = mmio_read_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].sta));
+
+ if (GET_SWINF_INIT_DONE(reg_rdata) != 0x1) {
+ ERROR("[PWRAP] init not finish\n");
+ ret = -E_PWR_NOT_INIT_DONE;
+ goto end;
+ }
+
+ /* Wait for Software Interface FSM state to be IDLE */
+ ret = pwrap_check_idle((uintptr_t)(&mtk_pwrap->wacs[swinf_no].sta),
+ (uintptr_t)(&mtk_pwrap->wacs[swinf_no].vldclr), TIMEOUT_WAIT_IDLE);
+ if (ret != 0) {
+ ERROR("[PWRAP] fsm_idle fail\n");
+ goto end;
+ }
+
+ /* Set the write data */
+ if (write == 1) {
+ if (pmifid == 0)
+ mmio_write_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].wdata), wdata);
+ }
+
+ /* Send the command */
+ if (pmifid == 0)
+ mmio_write_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].cmd),
+ (cmd << 30) | (write << 29) | (slvid << 24) | (bytecnt << 16) | addr);
+
+ if (write == 0) {
+ if (rdata == NULL) {
+ ERROR("[PWRAP] rdata null\n");
+ ret = -E_PWR_INVALID_ARG;
+ goto end;
+ }
+
+ /* Wait for Software Interface FSM to be WFVLDCLR */
+ /* read the data and clear the valid flag */
+ ret = pwrap_check_vldclr((uintptr_t)(&mtk_pwrap->wacs[swinf_no].sta), TIMEOUT_READ);
+ if (ret != 0) {
+ ERROR("[PWRAP] fsm_vldclr fail\n");
+ goto end;
+ }
+
+ if (pmifid == 0) {
+ *rdata = mmio_read_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].rdata));
+ mmio_write_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].vldclr), 0x1);
+ }
+ }
+
+end:
+ spin_unlock(&wrp_lock);
+ if (ret < 0)
+ ERROR("%s fail, ret=%d\n", __func__, ret);
+ return ret;
+}
+
+/* external API for pmic_wrap user */
+
+int32_t pwrap_read(uint32_t adr, uint32_t *rdata)
+{
+ return pwrap_swinf_acc(PMIF_SPI_SWINF_NO, DEFAULT_CMD, 0, PMIF_SPI_PMIFID,
+ DEFAULT_SLVID, adr, DEFAULT_BYTECNT, 0x0, rdata);
+}
+
+int32_t pwrap_write(uint32_t adr, uint32_t wdata)
+{
+ return pwrap_swinf_acc(PMIF_SPI_SWINF_NO, DEFAULT_CMD, 1, PMIF_SPI_PMIFID,
+ DEFAULT_SLVID, adr, DEFAULT_BYTECNT, wdata, 0x0);
+}
+
+int32_t pwrap_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift)
+{
+ uint32_t rdata;
+ int32_t ret;
+
+ if (!val)
+ return -E_PWR_INVALID_ARG;
+ ret = pwrap_read(reg, &rdata);
+ if (ret == 0x0)
+ *val = (rdata >> shift) & mask;
+
+ return ret;
+}
+
+int32_t pwrap_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift)
+{
+ uint32_t data;
+ int32_t ret;
+
+ ret = pwrap_read(reg, &data);
+ if (ret != 0)
+ return ret;
+
+ data = data & ~(mask << shift);
+ data |= (val << shift);
+ ret = pwrap_write(reg, data);
+
+ return ret;
+}
+
+#if PWRAP_DEBUG
+static int32_t pwrap_read_test(void)
+{
+ uint32_t rdata = 0;
+ int32_t ret;
+
+ ret = pwrap_read(DEW_READ_TEST, &rdata);
+ if (rdata != DEFAULT_VALUE_READ_TEST) {
+ ERROR("[PWRAP] Read fail,rdata=0x%x,exp=0x5aa5,ret=0x%x\n", rdata, ret);
+ return -E_PWR_READ_TEST_FAIL;
+ }
+ INFO("[PWRAP] Read Test pass,ret=%x\n", ret);
+ return 0;
+}
+
+static int32_t pwrap_write_test(void)
+{
+ uint32_t rdata = 0;
+ int32_t ret;
+ int32_t ret1;
+
+ ret = pwrap_write(DEW_WRITE_TEST, PWRAP_WRITE_TEST_VALUE);
+ ret1 = pwrap_read(DEW_WRITE_TEST, &rdata);
+ if ((rdata != PWRAP_WRITE_TEST_VALUE) || (ret != 0) || (ret1 != 0)) {
+ ERROR("[PWRAP] Write fail,rdata=0x%x,exp=0xa55a,ret=0x%x,ret1=0x%x\n",
+ rdata, ret, ret1);
+ return -E_PWR_WRITE_TEST_FAIL;
+ }
+ INFO("[PWRAP] Write Test pass\n");
+ return 0;
+}
+
+int32_t pmic_wrap_test(void)
+{
+ int32_t ret;
+
+ INFO("[PWRAP] Read/Write Test start\n");
+
+ ret = pwrap_read_test();
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = pwrap_write_test();
+ if (ret != 0) {
+ return ret;
+ }
+ INFO("[PWRAP] Read/Write Test done\n");
+
+ return 0;
+}
+#endif
diff --git a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_v3.h b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_v3.h
new file mode 100644
index 0000000..075c2d5
--- /dev/null
+++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_v3.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_WRAP_V3_H
+#define PMIC_WRAP_V3_H
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <drivers/console.h>
+
+#define PMIF_REG_RANGE (0x774)
+#define PMICSPI_MST_REG_RANGE (0x80)
+#define DEFAULT_CMD 0
+#define DEFAULT_SLVID 0
+#define DEFAULT_BYTECNT 0
+#define PMIF_SPI_PMIFID 0
+/* #define PWRAP_DEBUG 1 */
+
+#if PWRAP_DEBUG
+#define PWRAP_LOG(fmts, args...) do {\
+ console_init(gteearg.atf_log_port, UART_CLOCK, UART_BAUDRATE);\
+ INFO("[%s:%d] -" fmts, __func__, __LINE__, ##args);\
+ console_uninit();\
+ } while (0)
+#endif
+
+/**********************************************************/
+#define DEFAULT_VALUE_READ_TEST (0x5aa5)
+#define PWRAP_WRITE_TEST_VALUE (0xa55a)
+#define PWRAP_POLL_STEP_US (10)
+
+/* timeout setting */
+enum {
+ TIMEOUT_RESET = 50, /* us */
+ TIMEOUT_READ = 50, /* us */
+ TIMEOUT_WAIT_IDLE = 50 /* us */
+};
+
+#endif /* PMIC_WRAP_V3_H */
diff --git a/plat/mediatek/drivers/pmic_wrap/rules.mk b/plat/mediatek/drivers/pmic_wrap/rules.mk
index 9ba44a6..662c7e4 100644
--- a/plat/mediatek/drivers/pmic_wrap/rules.mk
+++ b/plat/mediatek/drivers/pmic_wrap/rules.mk
@@ -10,6 +10,8 @@
ifeq (${USE_PMIC_WRAP_INIT_V2}, 1)
LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init_v2.c
+else ifeq (${USE_PMIC_WRAP_INIT_V3}, 1)
+LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init_v3.c
else
LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init.c
endif
diff --git a/plat/mediatek/drivers/spmi/mt8189/platform_pmif_spmi.c b/plat/mediatek/drivers/spmi/mt8189/platform_pmif_spmi.c
new file mode 100644
index 0000000..417f779
--- /dev/null
+++ b/plat/mediatek/drivers/spmi/mt8189/platform_pmif_spmi.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+#include <drivers/spmi/pmif_common.h>
+#include <drivers/spmi/pmif_v1/pmif.h>
+#include <drivers/spmi/spmi_common.h>
+#include <drivers/spmi/spmi_sw.h>
+#include <drivers/spmi_api.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <mtk_mmap_pool.h>
+
+#define SPMI_GROUP_ID 0xB
+#define SPMI_DEBUG 0
+
+static uint16_t mt6xxx_regs[] = {
+ [PMIF_INIT_DONE] = 0x0000,
+ [PMIF_INF_EN] = 0x0024,
+ [PMIF_ARB_EN] = 0x0150,
+ [PMIF_IRQ_EVENT_EN_0] = 0x0420,
+ [PMIF_IRQ_FLAG_0] = 0x0428,
+ [PMIF_IRQ_CLR_0] = 0x042C,
+ [PMIF_IRQ_EVENT_EN_2] = 0x0440,
+ [PMIF_IRQ_FLAG_2] = 0x0448,
+ [PMIF_IRQ_CLR_2] = 0x044C,
+ [PMIF_WDT_CTRL] = 0x0470,
+ [PMIF_WDT_EVENT_EN_1] = 0x047C,
+ [PMIF_WDT_FLAG_1] = 0x0480,
+ [PMIF_SWINF_2_ACC] = 0x0880,
+ [PMIF_SWINF_2_WDATA_31_0] = 0x0884,
+ [PMIF_SWINF_2_WDATA_63_32] = 0x0888,
+ [PMIF_SWINF_2_RDATA_31_0] = 0x0894,
+ [PMIF_SWINF_2_RDATA_63_32] = 0x0898,
+ [PMIF_SWINF_2_VLD_CLR] = 0x08A4,
+ [PMIF_SWINF_2_STA] = 0x08A8,
+ [PMIF_SWINF_3_ACC] = 0x08C0,
+ [PMIF_SWINF_3_WDATA_31_0] = 0x08C4,
+ [PMIF_SWINF_3_WDATA_63_32] = 0x08C8,
+ [PMIF_SWINF_3_RDATA_31_0] = 0x08D4,
+ [PMIF_SWINF_3_RDATA_63_32] = 0x08D8,
+ [PMIF_SWINF_3_VLD_CLR] = 0x08E4,
+ [PMIF_SWINF_3_STA] = 0x08E8,
+ /* hw mpu */
+ [PMIF_PMIC_ALL_RGN_EN_1] = 0x09B0,
+ [PMIF_PMIC_ALL_RGN_EN_2] = 0x0D30,
+ [PMIF_PMIC_ALL_RGN_0_START] = 0x09B4,
+ [PMIF_PMIC_ALL_RGN_0_END] = 0x09B8,
+ [PMIF_PMIC_ALL_RGN_1_START] = 0x09BC,
+ [PMIF_PMIC_ALL_RGN_1_END] = 0x09C0,
+ [PMIF_PMIC_ALL_RGN_2_START] = 0x09C4,
+ [PMIF_PMIC_ALL_RGN_2_END] = 0x09C8,
+ [PMIF_PMIC_ALL_RGN_3_START] = 0x09CC,
+ [PMIF_PMIC_ALL_RGN_3_END] = 0x09D0,
+ [PMIF_PMIC_ALL_RGN_31_START] = 0x0D34,
+ [PMIF_PMIC_ALL_RGN_31_END] = 0x0D38,
+ [PMIF_PMIC_ALL_INVLD_SLVID] = 0x0AAC,
+ [PMIF_PMIC_ALL_RGN_0_PER0] = 0x0AB0,
+ [PMIF_PMIC_ALL_RGN_0_PER1] = 0x0AB4,
+ [PMIF_PMIC_ALL_RGN_1_PER0] = 0x0AB8,
+ [PMIF_PMIC_ALL_RGN_2_PER0] = 0x0AC0,
+ [PMIF_PMIC_ALL_RGN_3_PER0] = 0x0AC8,
+ [PMIF_PMIC_ALL_RGN_31_PER0] = 0x0E34,
+ [PMIF_PMIC_ALL_RGN_31_PER1] = 0x0E38,
+ [PMIF_PMIC_ALL_RGN_OTHERS_PER0] = 0x0BA8,
+ [PMIF_PMIC_ALL_RGN_OTHERS_PER1] = 0x0BAC,
+};
+
+static uint16_t mt6xxx_spmi_regs[] = {
+ [SPMI_OP_ST_CTRL] = 0x0000,
+ [SPMI_GRP_ID_EN] = 0x0004,
+ [SPMI_OP_ST_STA] = 0x0008,
+ [SPMI_MST_SAMPL] = 0x000c,
+ [SPMI_MST_REQ_EN] = 0x0010,
+ [SPMI_RCS_CTRL] = 0x0014,
+ [SPMI_SLV_3_0_EINT] = 0x0020,
+ [SPMI_SLV_7_4_EINT] = 0x0024,
+ [SPMI_SLV_B_8_EINT] = 0x0028,
+ [SPMI_SLV_F_C_EINT] = 0x002c,
+ [SPMI_REC_CTRL] = 0x0040,
+ [SPMI_REC0] = 0x0044,
+ [SPMI_REC1] = 0x0048,
+ [SPMI_REC2] = 0x004c,
+ [SPMI_REC3] = 0x0050,
+ [SPMI_REC4] = 0x0054,
+ [SPMI_REC_CMD_DEC] = 0x005c,
+ [SPMI_DEC_DBG] = 0x00f8,
+ [SPMI_MST_DBG] = 0x00fc,
+};
+
+struct pmif pmif_spmi_arb[] = {
+ {
+ .regs = mt6xxx_regs,
+ .spmimst_regs = mt6xxx_spmi_regs,
+ .mstid = SPMI_MASTER_0,
+ .read_cmd = pmif_spmi_read_cmd,
+ .write_cmd = pmif_spmi_write_cmd,
+ },
+ {
+ .regs = mt6xxx_regs,
+ .spmimst_regs = mt6xxx_spmi_regs,
+ .mstid = SPMI_MASTER_1,
+ .read_cmd = pmif_spmi_read_cmd,
+ .write_cmd = pmif_spmi_write_cmd,
+ },
+ {
+ .base = (unsigned int *)PMIF_SPMI_P_BASE,
+ .regs = mt6xxx_regs,
+ .spmimst_base = (unsigned int *)SPMI_MST_P_BASE,
+ .spmimst_regs = mt6xxx_spmi_regs,
+ .mstid = SPMI_MASTER_P_1,
+ .read_cmd = pmif_spmi_read_cmd,
+ .write_cmd = pmif_spmi_write_cmd,
+ },
+};
+
+static struct spmi_device spmi_dev[] = {
+ {
+ .slvid = SPMI_SLAVE_7, /* MT6319 */
+ .grpiden = 0x800,
+ .type = BUCK_CPU,
+ .type_id = BUCK_CPU_ID,
+ .mstid = SPMI_MASTER_P_1,/* spmi-p */
+ .hwcid_addr = 0x09,
+ .hwcid_val = 0x15,
+ .swcid_addr = 0x0B,
+ .swcid_val = 0x15,
+ .wpk_key_addr = 0x3A8,
+ .wpk_key_val = 0x6315,
+ .tma_key_addr = 0x39F,
+ .tma_key_val = 0x9CEA,
+ .pmif_arb = &pmif_spmi_arb[SPMI_MASTER_P_1],
+ },
+ {
+ .slvid = SPMI_SLAVE_8, /* MT6319 */
+ .grpiden = 0x800,
+ .type = BUCK_CPU,
+ .type_id = BUCK_CPU_ID,
+ .mstid = SPMI_MASTER_P_1,/* spmi-p */
+ .hwcid_addr = 0x09,
+ .hwcid_val = 0x15,
+ .swcid_addr = 0x0B,
+ .swcid_val = 0x15,
+ .wpk_key_addr = 0x3A8,
+ .wpk_key_val = 0x6315,
+ .tma_key_addr = 0x39F,
+ .tma_key_val = 0x9CEA,
+ .pmif_arb = &pmif_spmi_arb[SPMI_MASTER_P_1],
+ },
+};
+
+int platform_pmif_spmi_init(void)
+{
+/*
+ * The MT8189 chipset comes in two variants: MT8189G and MT8189H. The
+ * MT8189G variant uses a single PMIC IC (MT6319), whereas the MT8189H
+ * variant uses two PMIC ICs. To ensure driver compatibility, we utilize
+ * the CPU ID and segment ID to accurately determine the required number
+ * of SPMIF instances.
+ */
+ if (mmio_read_32((uintptr_t)CHIP_ID_REG) == MTK_CPU_ID_MT8189 &&
+ mmio_read_32((uintptr_t)CPU_SEG_ID_REG) == MTK_CPU_SEG_ID_MT8189G)
+ spmi_device_register(spmi_dev, 1);
+ else
+ spmi_device_register(spmi_dev, ARRAY_SIZE(spmi_dev));
+
+ return 0;
+}
+MTK_ARCH_INIT(platform_pmif_spmi_init);
diff --git a/plat/mediatek/include/drivers/pmic/mt6319_lowpower_reg.h b/plat/mediatek/include/drivers/pmic/mt6319_lowpower_reg.h
new file mode 100644
index 0000000..71a2d2b
--- /dev/null
+++ b/plat/mediatek/include/drivers/pmic/mt6319_lowpower_reg.h
@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT6319_LOWPOWER_REG_H
+#define MT6319_LOWPOWER_REG_H
+
+#define MT6319_RG_LDO_VDIG18_SW_OP_EN_ADDR 0x0196
+#define MT6319_RG_LDO_VDIG18_HW_OP_EN_ADDR 0x0196
+#define MT6319_RG_VDIG18_PWROFF_OP_EN_ADDR 0x0197
+#define MT6319_RG_BUCK_VBUCK1_HW0_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW1_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW2_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW3_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW4_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW5_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW6_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW7_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW8_OP_EN_ADDR 0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW9_OP_EN_ADDR 0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW10_OP_EN_ADDR 0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW11_OP_EN_ADDR 0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW12_OP_EN_ADDR 0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW13_OP_EN_ADDR 0x1708
+#define MT6319_RG_BUCK_VBUCK1_SW_OP_EN_ADDR 0x1490
+#define MT6319_RG_BUCK_VBUCK1_HW0_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW1_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW2_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW3_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW4_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW5_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW6_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW7_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW8_OP_CFG_ADDR 0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW9_OP_CFG_ADDR 0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW10_OP_CFG_ADDR 0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW11_OP_CFG_ADDR 0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW12_OP_CFG_ADDR 0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW13_OP_CFG_ADDR 0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW0_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW1_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW2_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW3_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW4_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW5_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW6_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW7_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW8_OP_MODE_ADDR 0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW9_OP_MODE_ADDR 0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW10_OP_MODE_ADDR 0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW11_OP_MODE_ADDR 0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW12_OP_MODE_ADDR 0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW13_OP_MODE_ADDR 0x170e
+#define MT6319_RG_BUCK_VBUCK2_HW0_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW1_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW2_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW3_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW4_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW5_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW6_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW7_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW8_OP_EN_ADDR 0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW9_OP_EN_ADDR 0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW10_OP_EN_ADDR 0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW11_OP_EN_ADDR 0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW12_OP_EN_ADDR 0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW13_OP_EN_ADDR 0x1711
+#define MT6319_RG_BUCK_VBUCK2_SW_OP_EN_ADDR 0x1510
+#define MT6319_RG_BUCK_VBUCK2_HW0_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW1_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW2_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW3_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW4_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW5_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW6_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW7_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW8_OP_CFG_ADDR 0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW9_OP_CFG_ADDR 0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW10_OP_CFG_ADDR 0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW11_OP_CFG_ADDR 0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW12_OP_CFG_ADDR 0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW13_OP_CFG_ADDR 0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW0_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW1_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW2_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW3_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW4_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW5_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW6_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW7_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW8_OP_MODE_ADD 0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW9_OP_MODE_ADDR 0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW10_OP_MODE_ADDR 0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW11_OP_MODE_ADDR 0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW12_OP_MODE_ADDR 0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW13_OP_MODE_ADDR 0x1717
+#define MT6319_RG_BUCK_VBUCK3_HW0_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW1_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW2_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW3_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW4_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW5_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW6_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW7_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW8_OP_EN_ADDR 0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW9_OP_EN_ADDR 0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW10_OP_EN_ADDR 0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW11_OP_EN_ADDR 0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW12_OP_EN_ADDR 0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW13_OP_EN_ADDR 0x171a
+#define MT6319_RG_BUCK_VBUCK3_SW_OP_EN_ADDR 0x1590
+#define MT6319_RG_BUCK_VBUCK3_HW0_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW1_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW2_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW3_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW4_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW5_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW6_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW7_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW8_OP_CFG_ADDR 0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW9_OP_CFG_ADDR 0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW10_OP_CFG_ADDR 0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW11_OP_CFG_ADDR 0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW12_OP_CFG_ADDR 0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW13_OP_CFG_ADDR 0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW0_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW1_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW2_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW3_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW4_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW5_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW6_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW7_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW8_OP_MODE_ADDR 0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW9_OP_MODE_ADDR 0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW10_OP_MODE_ADDR 0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW11_OP_MODE_ADDR 0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW12_OP_MODE_ADDR 0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW13_OP_MODE_ADDR 0x1720
+#define MT6319_RG_BUCK_VBUCK4_HW0_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW1_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW2_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW3_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW4_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW5_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW6_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW7_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW8_OP_EN_ADDR 0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW9_OP_EN_ADDR 0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW10_OP_EN_ADDR 0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW11_OP_EN_ADDR 0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW12_OP_EN_ADDR 0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW13_OP_EN_ADDR 0x1723
+#define MT6319_RG_BUCK_VBUCK4_SW_OP_EN_ADDR 0x1610
+#define MT6319_RG_BUCK_VBUCK4_HW0_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW1_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW2_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW3_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW4_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW5_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW6_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW7_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW8_OP_CFG_ADDR 0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW9_OP_CFG_ADDR 0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW10_OP_CFG_ADDR 0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW11_OP_CFG_ADDR 0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW12_OP_CFG_ADDR 0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW13_OP_CFG_ADDR 0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW0_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW1_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW2_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW3_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW4_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW5_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW6_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW7_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW8_OP_MODE_ADDR 0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW9_OP_MODE_ADDR 0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW10_OP_MODE_ADDR 0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW11_OP_MODE_ADDR 0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW12_OP_MODE_ADDR 0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW13_OP_MODE_ADDR 0x1729
+
+#endif /* MT6319_LOWPOWER_REG_H */
diff --git a/plat/mediatek/include/drivers/pmic/mt6359p_lowpower_reg.h b/plat/mediatek/include/drivers/pmic/mt6359p_lowpower_reg.h
new file mode 100644
index 0000000..7e14f00
--- /dev/null
+++ b/plat/mediatek/include/drivers/pmic/mt6359p_lowpower_reg.h
@@ -0,0 +1,1593 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT6359P_LOWPOWER_REG_H
+#define MT6359P_LOWPOWER_REG_H
+
+#define MT6359P_RG_BUCK_VPU_VOSEL_SLEEP_ADDR 0x148e
+#define MT6359P_RG_BUCK_VPU_HW0_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW1_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW2_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW3_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW4_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW5_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW6_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW7_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW8_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW9_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW10_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW11_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW12_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW13_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW14_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_SW_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW0_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW1_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW2_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW3_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW4_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW5_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW6_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW7_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW8_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW9_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW10_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW11_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW12_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW13_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW14_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW0_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VPU_HW1_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VPU_HW2_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VPU_HW3_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VPU_HW4_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VPU_HW5_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VPU_HW6_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VPU_HW7_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VPU_HW8_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VPU_HW9_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VPU_HW10_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VPU_HW11_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VPU_HW12_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VPU_HW13_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VPU_HW14_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VCORE_VOSEL_SLEEP_ADDR 0x150e
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_SW_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VGPU11_VOSEL_SLEEP_ADDR 0x158e
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_SW_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VGPU12_VOSEL_SLEEP_ADDR 0x160e
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_SW_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VMODEM_VOSEL_SLEEP_ADDR 0x168e
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_SW_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VPROC1_VOSEL_SLEEP_ADDR 0x170e
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_SW_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VPROC2_VOSEL_SLEEP_ADDR 0x178e
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_SW_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VS1_VOSEL_SLEEP_ADDR 0x180e
+#define MT6359P_RG_BUCK_VS1_HW0_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW1_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW2_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW3_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW4_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW5_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW6_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW7_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW8_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW9_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW10_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW11_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW12_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW13_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW14_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_SW_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW0_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW1_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW2_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW3_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW4_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW5_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW6_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW7_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW8_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW9_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW10_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW11_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW12_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW13_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW14_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW0_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VS1_HW1_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VS1_HW2_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VS1_HW3_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VS1_HW4_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VS1_HW5_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VS1_HW6_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VS1_HW7_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VS1_HW8_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VS1_HW9_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VS1_HW10_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VS1_HW11_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VS1_HW12_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VS1_HW13_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VS1_HW14_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VS2_VOSEL_SLEEP_ADDR 0x188e
+#define MT6359P_RG_BUCK_VS2_HW0_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW1_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW2_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW3_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW4_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW5_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW6_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW7_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW8_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW9_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW10_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW11_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW12_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW13_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW14_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_SW_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW0_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW1_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW2_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW3_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW4_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW5_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW6_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW7_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW8_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW9_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW10_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW11_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW12_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW13_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW14_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW0_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VS2_HW1_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VS2_HW2_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VS2_HW3_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VS2_HW4_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VS2_HW5_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VS2_HW6_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VS2_HW7_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VS2_HW8_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VS2_HW9_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VS2_HW10_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VS2_HW11_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VS2_HW12_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VS2_HW13_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VS2_HW14_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_LDO_VFE28_OP_MODE_ADDR 0x1b8a
+#define MT6359P_RG_LDO_VFE28_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VFE28_HW0_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW1_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW2_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW3_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW4_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW5_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW6_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW7_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW8_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW9_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW10_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW11_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW12_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW13_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW14_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_SW_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW0_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW1_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW2_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW3_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW4_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW5_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW6_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW7_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW8_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW9_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW10_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW11_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW12_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW13_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW14_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_SW_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VXO22_OP_MODE_ADDR 0x1b9c
+#define MT6359P_RG_LDO_VXO22_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VXO22_HW0_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW1_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW2_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW3_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW4_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW5_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW6_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW7_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW8_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW9_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW10_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW11_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW12_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW13_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW14_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_SW_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW0_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW1_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW2_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW3_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW4_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW5_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW6_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW7_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW8_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW9_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW10_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW11_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW12_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW13_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW14_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_SW_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VRF18_OP_MODE_ADDR 0x1bae
+#define MT6359P_RG_LDO_VRF18_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VRF18_HW0_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW1_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW2_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW3_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW4_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW5_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW6_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW7_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW8_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW9_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW10_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW11_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW12_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW13_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW14_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_SW_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW0_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW1_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW2_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW3_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW4_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW5_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW6_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW7_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW8_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW9_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW10_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW11_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW12_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW13_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW14_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_SW_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF12_OP_MODE_ADDR 0x1bc0
+#define MT6359P_RG_LDO_VRF12_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VRF12_HW0_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW1_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW2_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW3_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW4_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW5_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW6_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW7_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW8_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW9_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW10_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW11_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW12_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW13_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW14_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_SW_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW0_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW1_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW2_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW3_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW4_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW5_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW6_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW7_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW8_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW9_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW10_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW11_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW12_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW13_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW14_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_SW_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VEFUSE_OP_MODE_ADDR 0x1bd2
+#define MT6359P_RG_LDO_VEFUSE_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VEFUSE_HW0_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW1_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW2_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW3_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW4_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW5_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW6_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW7_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW8_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW9_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW10_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW11_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW12_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW13_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW14_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_SW_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW0_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW1_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW2_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW3_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW4_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW5_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW6_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW7_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW8_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW9_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW10_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW11_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW12_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW13_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW14_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_SW_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VCN33_1_OP_MODE_ADDR 0x1be4
+#define MT6359P_RG_LDO_VCN33_1_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VCN33_1_HW0_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW1_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW2_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW3_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW4_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW5_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW6_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW7_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW8_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW9_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW10_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW11_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW12_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW13_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW14_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_SW_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW0_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW1_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW2_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW3_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW4_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW5_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW6_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW7_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW8_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW9_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW10_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW11_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW12_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW13_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW14_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_SW_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_2_OP_MODE_ADDR 0x1c0a
+#define MT6359P_RG_LDO_VCN33_2_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VCN33_2_HW0_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW1_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW2_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW3_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW4_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW5_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW6_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW7_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW8_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW9_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW10_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW11_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW12_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW13_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW14_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_SW_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW0_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW1_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW2_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW3_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW4_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW5_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW6_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW7_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW8_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW9_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW10_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW11_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW12_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW13_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW14_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_SW_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN13_OP_MODE_ADDR 0x1c1e
+#define MT6359P_RG_LDO_VCN13_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VCN13_HW0_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW1_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW2_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW3_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW4_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW5_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW6_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW7_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW8_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW9_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW10_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW11_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW12_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW13_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW14_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_SW_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW0_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW1_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW2_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW3_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW4_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW5_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW6_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW7_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW8_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW9_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW10_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW11_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW12_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW13_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW14_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_SW_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN18_OP_MODE_ADDR 0x1c30
+#define MT6359P_RG_LDO_VCN18_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VCN18_HW0_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW1_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW2_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW3_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW4_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW5_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW6_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW7_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW8_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW9_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW10_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW11_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW12_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW13_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW14_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_SW_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW0_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW1_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW2_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW3_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW4_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW5_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW6_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW7_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW8_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW9_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW10_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW11_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW12_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW13_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW14_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_SW_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VA09_OP_MODE_ADDR 0x1c42
+#define MT6359P_RG_LDO_VA09_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VA09_HW0_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW1_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW2_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW3_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW4_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW5_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW6_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW7_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW8_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW9_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW10_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW11_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW12_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW13_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW14_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_SW_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW0_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW1_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW2_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW3_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW4_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW5_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW6_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW7_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW8_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW9_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW10_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW11_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW12_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW13_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW14_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_SW_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VCAMIO_OP_MODE_ADDR 0x1c54
+#define MT6359P_RG_LDO_VCAMIO_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VCAMIO_HW0_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW1_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW2_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW3_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW4_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW5_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW6_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW7_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW8_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW9_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW10_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW11_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW12_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW13_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW14_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_SW_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW0_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW1_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW2_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW3_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW4_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW5_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW6_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW7_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW8_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW9_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW10_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW11_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW12_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW13_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW14_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_SW_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VA12_OP_MODE_ADDR 0x1c66
+#define MT6359P_RG_LDO_VA12_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VA12_HW0_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW1_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW2_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW3_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW4_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW5_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW6_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW7_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW8_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW9_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW10_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW11_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW12_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW13_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW14_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_SW_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW0_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW1_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW2_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW3_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW4_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW5_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW6_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW7_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW8_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW9_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW10_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW11_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW12_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW13_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW14_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_SW_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VAUX18_OP_MODE_ADDR 0x1c8a
+#define MT6359P_RG_LDO_VAUX18_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VAUX18_HW0_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW1_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW2_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW3_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW4_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW5_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW6_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW7_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW8_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW9_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW10_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW11_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW12_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW13_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW14_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_SW_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW0_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW1_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW2_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW3_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW4_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW5_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW6_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW7_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW8_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW9_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW10_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW11_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW12_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW13_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW14_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_SW_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUD18_OP_MODE_ADDR 0x1c9c
+#define MT6359P_RG_LDO_VAUD18_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VAUD18_HW0_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW1_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW2_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW3_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW4_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW5_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW6_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW7_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW8_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW9_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW10_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW11_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW12_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW13_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW14_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_SW_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW0_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW1_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW2_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW3_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW4_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW5_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW6_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW7_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW8_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW9_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW10_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW11_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW12_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW13_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW14_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_SW_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VIO18_OP_MODE_ADDR 0x1cae
+#define MT6359P_RG_LDO_VIO18_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VIO18_HW0_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW1_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW2_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW3_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW4_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW5_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW6_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW7_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW8_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW9_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW10_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW11_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW12_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW13_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW14_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_SW_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW0_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW1_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW2_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW3_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW4_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW5_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW6_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW7_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW8_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW9_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW10_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW11_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW12_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW13_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW14_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_SW_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VEMC_OP_MODE_ADDR 0x1cc0
+#define MT6359P_RG_LDO_VEMC_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VEMC_HW0_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW1_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW2_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW3_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW4_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW5_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW6_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW7_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW8_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW9_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW10_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW11_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW12_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW13_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW14_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_SW_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW0_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW1_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW2_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW3_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW4_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW5_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW6_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW7_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW8_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW9_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW10_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW11_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW12_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW13_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW14_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_SW_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VSIM1_OP_MODE_ADDR 0x1cd2
+#define MT6359P_RG_LDO_VSIM1_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VSIM1_HW0_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW1_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW2_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW3_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW4_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW5_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW6_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW7_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW8_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW9_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW10_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW11_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW12_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW13_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW14_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_SW_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW0_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW1_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW2_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW3_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW4_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW5_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW6_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW7_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW8_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW9_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW10_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW11_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW12_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW13_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW14_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_SW_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM2_OP_MODE_ADDR 0x1ce4
+#define MT6359P_RG_LDO_VSIM2_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VSIM2_HW0_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW1_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW2_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW3_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW4_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW5_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW6_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW7_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW8_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW9_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW10_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW11_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW12_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW13_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW14_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_SW_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW0_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW1_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW2_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW3_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW4_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW5_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW6_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW7_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW8_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW9_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW10_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW11_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW12_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW13_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW14_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_SW_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VUSB_OP_MODE_ADDR 0x1d0a
+#define MT6359P_RG_LDO_VUSB_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VUSB_HW0_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW1_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW2_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW3_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW4_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW5_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW6_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW7_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW8_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW9_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW10_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW11_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW12_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW13_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW14_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_SW_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW0_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW1_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW2_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW3_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW4_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW5_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW6_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW7_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW8_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW9_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW10_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW11_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW12_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW13_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW14_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_SW_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VRFCK_OP_MODE_ADDR 0x1d1e
+#define MT6359P_RG_LDO_VRFCK_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VRFCK_HW0_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW1_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW2_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW3_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW4_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW5_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW6_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW7_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW8_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW9_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW10_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW11_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW12_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW13_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW14_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_SW_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW0_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW1_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW2_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW3_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW4_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW5_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW6_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW7_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW8_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW9_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW10_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW11_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW12_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW13_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW14_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_SW_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VBBCK_OP_MODE_ADDR 0x1d30
+#define MT6359P_RG_LDO_VBBCK_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VBBCK_HW0_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW1_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW2_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW3_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW4_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW5_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW6_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW7_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW8_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW9_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW10_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW11_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW12_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW13_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW14_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_SW_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW0_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW1_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW2_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW3_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW4_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW5_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW6_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW7_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW8_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW9_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW10_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW11_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW12_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW13_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW14_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_SW_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBIF28_OP_MODE_ADDR 0x1d42
+#define MT6359P_RG_LDO_VBIF28_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VBIF28_HW0_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW1_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW2_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW3_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW4_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW5_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW6_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW7_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW8_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW9_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW10_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW11_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW12_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW13_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW14_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_SW_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW0_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW1_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW2_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW3_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW4_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW5_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW6_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW7_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW8_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW9_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW10_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW11_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW12_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW13_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW14_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_SW_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VIBR_OP_MODE_ADDR 0x1d54
+#define MT6359P_RG_LDO_VIBR_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VIBR_HW0_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW1_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW2_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW3_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW4_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW5_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW6_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW7_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW8_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW9_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW10_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW11_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW12_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW13_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW14_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_SW_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW0_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW1_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW2_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW3_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW4_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW5_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW6_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW7_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW8_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW9_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW10_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW11_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW12_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW13_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW14_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_SW_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIO28_OP_MODE_ADDR 0x1d66
+#define MT6359P_RG_LDO_VIO28_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VIO28_HW0_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW1_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW2_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW3_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW4_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW5_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW6_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW7_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW8_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW9_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW10_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW11_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW12_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW13_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW14_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_SW_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW0_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW1_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW2_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW3_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW4_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW5_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW6_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW7_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW8_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW9_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW10_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW11_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW12_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW13_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW14_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_SW_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VM18_OP_MODE_ADDR 0x1d8a
+#define MT6359P_RG_LDO_VM18_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VM18_HW0_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW1_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW2_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW3_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW4_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW5_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW6_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW7_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW8_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW9_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW10_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW11_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW12_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW13_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW14_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_SW_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW0_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW1_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW2_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW3_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW4_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW5_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW6_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW7_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW8_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW9_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW10_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW11_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW12_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW13_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW14_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_SW_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VUFS_OP_MODE_ADDR 0x1d9c
+#define MT6359P_RG_LDO_VUFS_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VUFS_HW0_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW1_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW2_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW3_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW4_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW5_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW6_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW7_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW8_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW9_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW10_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW11_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW12_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW13_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW14_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_SW_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW0_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW1_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW2_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW3_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW4_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW5_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW6_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW7_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW8_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW9_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW10_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW11_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW12_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW13_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW14_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_SW_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VSRAM_PROC1_OP_MODE_ADDR 0x1e8a
+#define MT6359P_RG_LDO_VSRAM_PROC1_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_SLEEP_ADDR 0x1e8e
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW0_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW1_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW2_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW3_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW4_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW5_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW6_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW7_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW8_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW9_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW10_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW11_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW12_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW13_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW14_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_SW_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW0_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW1_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW2_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW3_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW4_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW5_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW6_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW7_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW8_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW9_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW10_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW11_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW12_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW13_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW14_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_SW_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC2_OP_MODE_ADDR 0x1eaa
+#define MT6359P_RG_LDO_VSRAM_PROC2_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_SLEEP_ADDR 0x1eae
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW0_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW1_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW2_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW3_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW4_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW5_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW6_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW7_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW8_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW9_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW10_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW11_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW12_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW13_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW14_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_SW_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW0_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW1_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW2_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW3_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW4_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW5_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW6_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW7_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW8_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW9_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW10_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW11_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW12_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW13_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW14_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_SW_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_OTHERS_OP_MODE_ADDR 0x1f0a
+#define MT6359P_RG_LDO_VSRAM_OTHERS_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP_ADDR 0x1f0e
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW0_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW1_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW2_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW3_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW4_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW5_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW6_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW7_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW8_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW9_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW10_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW11_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW12_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW13_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW14_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_SW_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW0_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW1_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW2_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW3_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW4_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW5_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW6_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW7_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW8_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW9_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW10_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW11_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW12_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW13_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW14_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_SW_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP_ADDR 0x1f28
+#define MT6359P_RG_LDO_VSRAM_MD_OP_MODE_ADDR 0x1f30
+#define MT6359P_RG_LDO_VSRAM_MD_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VSRAM_MD_VOSEL_SLEEP_ADDR 0x1f34
+#define MT6359P_RG_LDO_VSRAM_MD_HW0_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW1_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW2_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW3_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW4_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW5_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW6_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW7_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW8_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW9_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW10_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW11_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW12_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW13_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW14_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_SW_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW0_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW1_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW2_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW3_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW4_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW5_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW6_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW7_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW8_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW9_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW10_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW11_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW12_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW13_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW14_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_SW_OP_CFG_ADDR 0x1f42
+
+#endif /* MT6359P_LOWPOWER_REG_H */
diff --git a/plat/mediatek/include/drivers/pmic/mt6359p_set_lowpower.h b/plat/mediatek/include/drivers/pmic/mt6359p_set_lowpower.h
new file mode 100644
index 0000000..60b49bf
--- /dev/null
+++ b/plat/mediatek/include/drivers/pmic/mt6359p_set_lowpower.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT6359P_SET_LOWPOWER_H
+#define MT6359P_SET_LOWPOWER_H
+
+#include <stdint.h>
+
+#include "mt6359p_lowpower_reg.h"
+#include <pmic_wrap_init_common.h>
+
+#define OP_MODE_MU (0)
+#define OP_MODE_LP (1)
+
+#define HW_OFF (0)
+#define HW_ON (0)
+#define HW_LP (1)
+
+enum {
+ HW0 = 0,
+ HW1,
+ HW2,
+ HW3,
+ HW4,
+ HW5,
+ HW6,
+ HW7,
+ HW8,
+ HW9,
+ HW10,
+ HW11,
+ HW12,
+ HW13,
+ HW14,
+};
+
+#define PMIC_BUCK_SET_LP(_chip, _name, _user, _en, _mode, _cfg) \
+{ \
+ pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_CFG_ADDR, \
+ 1 << _user, \
+ (_cfg & 0x1) ? 1 << _user : 0); \
+ pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_MODE_ADDR, \
+ 1 << _user, \
+ _mode ? 1 << _user : 0); \
+ pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_EN_ADDR, \
+ 1 << _user, \
+ _en ? 1 << _user : 0); \
+}
+
+#define PMIC_LDO_SET_LP(_chip, _name, _user, _en, _mode, _cfg) \
+{ \
+ if (_user <= HW2) { \
+ pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_OP_MODE_ADDR, \
+ 1 << (_user + _chip##_RG_LDO_##_name##_OP_MODE_SHIFT), \
+ _mode ? 1 << (_user + _chip##_RG_LDO_##_name##_OP_MODE_SHIFT) : 0); \
+ } \
+ pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_##_user##_OP_CFG_ADDR, \
+ 1 << _user, \
+ (_cfg & 0x1) ? 1 << _user : 0); \
+ pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_##_user##_OP_EN_ADDR, \
+ 1 << _user, \
+ _en ? 1 << _user : 0); \
+}
+
+static inline int pmic_wrap_update_bits(uint32_t reg, uint32_t mask, uint32_t val)
+{
+ uint32_t orig = 0;
+ int ret = 0;
+
+ ret = pwrap_read(reg, &orig);
+ if (ret < 0)
+ return ret;
+
+ orig &= ~mask;
+ orig |= val & mask;
+
+ ret = pwrap_write(reg, orig);
+ return ret;
+}
+
+#endif /* MT6359P_MT6359P_SET_LOWPOWER_H */
diff --git a/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h b/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h
index f79612d..4f0517f 100644
--- a/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h
+++ b/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h
@@ -12,6 +12,7 @@
#include <drivers/spmi_api.h>
#include "mt6316_lowpower_reg.h"
+#include "mt6319_lowpower_reg.h"
#include "mt6363_lowpower_reg.h"
#include "mt6373_lowpower_reg.h"
diff --git a/plat/mediatek/include/mtk_sip_def.h b/plat/mediatek/include/mtk_sip_def.h
index 2e0b501..1b51a4b 100644
--- a/plat/mediatek/include/mtk_sip_def.h
+++ b/plat/mediatek/include/mtk_sip_def.h
@@ -18,6 +18,7 @@
_func(MTK_SIP_EMIDBG_CONTROL, 0x50B) \
_func(MTK_SIP_IOMMU_CONTROL, 0x514) \
_func(MTK_SIP_AUDIO_CONTROL, 0x517) \
+ _func(MTK_SIP_DISP_CONTROL, 0x51C) \
_func(MTK_SIP_APUSYS_CONTROL, 0x51E) \
_func(MTK_SIP_DP_CONTROL, 0x523) \
_func(MTK_SIP_KERNEL_GIC_OP, 0x526) \
diff --git a/plat/mediatek/lib/pm/armv9_0/pwr_ctrl.c b/plat/mediatek/lib/pm/armv9_0/pwr_ctrl.c
index 19dcd33..3224244 100644
--- a/plat/mediatek/lib/pm/armv9_0/pwr_ctrl.c
+++ b/plat/mediatek/lib/pm/armv9_0/pwr_ctrl.c
@@ -388,10 +388,6 @@
ret = imtk_cpu_pwr.ops->pwr_domain_pwr_down_wfi(cpu);
if (ret == MTK_CPUPM_E_OK)
plat_panic_handler();
- else
- psci_power_down_wfi();
- /* should never reach here */
- panic();
}
static void pm_smp_init(unsigned int cpu_id, uintptr_t entry_point)
diff --git a/plat/mediatek/mt8189/include/platform_def.h b/plat/mediatek/mt8189/include/platform_def.h
index 067ebcc..0211c44 100644
--- a/plat/mediatek/mt8189/include/platform_def.h
+++ b/plat/mediatek/mt8189/include/platform_def.h
@@ -76,7 +76,17 @@
#define SMI_LARB_19_BASE (IO_PHYS + 0x0b10f000)
#define SMI_LARB_20_BASE (IO_PHYS + 0x0b00f000)
#define SMI_LARB_REG_RNG_SIZE (0x1000)
-
+#define MMSYS_CONFIG_BASE (IO_PHYS + 0x04000000)
+#define DISP_MUTEX_BASE (IO_PHYS + 0x04001000)
+#define DISP_OVL0_BASE (IO_PHYS + 0x04002000)
+#define DISP_OVL1_BASE (IO_PHYS + 0x04003000)
+#define DISP_RDMA0_BASE (IO_PHYS + 0x04006000)
+#define DISP_COLOR0_BASE (IO_PHYS + 0x04008000)
+#define DISP_CCORR0_BASE (IO_PHYS + 0x0400A000)
+#define DISP_CCORR2_BASE (IO_PHYS + 0x0400C000)
+#define DISP_AAL0_BASE (IO_PHYS + 0x0400E000)
+#define DISP_GAMMA0_BASE (IO_PHYS + 0x04010000)
+#define DISP_DITHER0_BASE (IO_PHYS + 0x04012000)
#define MM_IOMMU_BASE (IO_PHYS + 0x0e802000 + 0x4000)
#define APU_IOMMU_BASE (IO_PHYS + 0x09010000)
@@ -143,4 +153,54 @@
******************************************************************************/
#define SYSTIMER_BASE (IO_PHYS + 0x0CC10000)
+/*******************************************************************************
+ * SPMI related definitions
+ ******************************************************************************/
+#define SPMI_MST_P_BASE (IO_PHYS + 0x0CC00000)
+#define PMIF_SPMI_P_BASE (IO_PHYS + 0x0CC06000)
+#define SPMI_MST_P_SIZE (0x1000)
+
+/*******************************************************************************
+ * PWRAP related definitions
+ ******************************************************************************/
+#define PMICSPI_MST_BASE (IO_PHYS + 0x0c013000)
+#define PMICSPI_MST_SIZE (0x1000)
+#define PMIC_WRAP_BASE (IO_PHYS + 0x0CC04000)
+#define PMIF_SPI_BASE (0x1CC04000)
+#define PWRAP_REG_BASE (0x1C013000)
+#define PWRAP_WRAP_EN (PWRAP_REG_BASE + 0x14)
+
+/*******************************************************************************
+ * PMIC regsister related definitions
+ ******************************************************************************/
+#define PMIC_REG_BASE (0x0000)
+#define PWRAP_SIZE (0x1000)
+#define DEW_READ_TEST (PMIC_REG_BASE + 0x040e)
+#define DEW_WRITE_TEST (PMIC_REG_BASE + 0x0410)
+
+/*******************************************************************************
+ * Differentiate between 3G and 2.6G-related definitions
+ ******************************************************************************/
+#define EFUSEC_BASE (IO_PHYS + 0x01F10000)
+#define CHIP_ID_REG (EFUSEC_BASE + 0x7A0)
+#define CPU_SEG_ID_REG (EFUSEC_BASE + 0x7E0)
+
+#define MTK_CPU_ID_MT8189 0x81890000
+#define MTK_CPU_SEG_ID_MT8189G 0x20
+#define MTK_CPU_SEG_ID_MT8189H 0x21
+
+/*******************************************************************************
+ * CPU PM definitions
+ ******************************************************************************/
+#define PLAT_CPU_PM_B_BUCK_ISO_ID (6)
+#define PLAT_CPU_PM_ILDO_ID (6)
+#define CPU_IDLE_SRAM_BASE (0x11B000)
+#define CPU_IDLE_SRAM_SIZE (0x1000)
+
+/*******************************************************************************
+ * SPM related constants
+ ******************************************************************************/
+#define SPM_BASE (IO_PHYS + 0x0C001000)
+#define SPM_REG_SIZE (0x1000)
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/mediatek/mt8189/plat_config.mk b/plat/mediatek/mt8189/plat_config.mk
index f06555b..650f290 100644
--- a/plat/mediatek/mt8189/plat_config.mk
+++ b/plat/mediatek/mt8189/plat_config.mk
@@ -22,6 +22,20 @@
MCUSYS_VERSION := v1
PLAT_EXTRA_RODATA_INCLUDES := 1
CONFIG_MTK_DISABLE_CACHE_AS_RAM := $(COREBOOT)
+CONFIG_MTK_PM_SUPPORT := y
+CONFIG_MTK_PM_ARCH := 8_2
+CONFIG_MTK_CPU_PM_SUPPORT := y
+CONFIG_MTK_CPU_PM_ARCH := 3_2
+CONFIG_MTK_SMP_EN := y
+CPU_PM_SPM_CORE_POWERON := y
+
+CONFIG_MTK_PMIC := y
+CONFIG_MTK_PMIC_LOWPOWER := y
+CONFIG_MTK_PMIC_SHUTDOWN_CFG := y
+CONFIG_MTK_PMIC_SHUTDOWN_V2 := y
+CONFIG_MTK_SPMI := y
+PMIC_CHIP := mt6359p
+USE_PMIC_WRAP_INIT_V3 := 1
# Configs for A78 and A55
CTX_INCLUDE_AARCH32_REGS := 0
diff --git a/plat/mediatek/mt8189/platform.mk b/plat/mediatek/mt8189/platform.mk
index c0c0427..d8b90cd 100644
--- a/plat/mediatek/mt8189/platform.mk
+++ b/plat/mediatek/mt8189/platform.mk
@@ -14,6 +14,7 @@
PLAT_INCLUDES := -I${MTK_PLAT}/common \
-I${MTK_PLAT}/common/include \
+ -I${MTK_PLAT}/drivers/cpu_pm/topology/inc \
-I${MTK_PLAT}/drivers/gpio/ \
-I${MTK_PLAT}/include \
-I${MTK_PLAT}/include/${ARCH_VERSION} \
@@ -26,12 +27,23 @@
MODULES-y += $(MTK_PLAT)/helpers
MODULES-y += $(MTK_PLAT)/lib/mtk_init
MODULES-y += $(MTK_PLAT)/lib/pm
+MODULES-y += $(MTK_PLAT)/lib/system_reset
MODULES-y += $(MTK_PLAT)/topology
MODULES-y += $(MTK_PLAT)/drivers/cirq
+MODULES-y += $(MTK_PLAT)/drivers/dfd
+MODULES-y += $(MTK_PLAT)/drivers/disp
MODULES-y += $(MTK_PLAT)/drivers/gic600
MODULES-y += $(MTK_PLAT)/drivers/iommu
MODULES-y += $(MTK_PLAT)/drivers/mcusys
+MODULES-y += $(MTK_PLAT)/drivers/pmic_wrap
MODULES-y += $(MTK_PLAT)/drivers/timer
+MODULES-$(CONFIG_MTK_PMIC) += $(MTK_PLAT)/drivers/pmic
+MODULES-$(CONFIG_MTK_SPMI) += $(MTK_PLAT)/drivers/spmi
+MODULES-$(CONFIG_MTK_CPU_PM_SUPPORT) += $(MTK_PLAT)/drivers/cpu_pm
+
+ifneq ($(MTKLIB_PATH),)
+LDLIBS += -Wl,--whole-archive $(MTKLIB_PATH) -Wl,--no-whole-archive
+endif
PLAT_BL_COMMON_SOURCES := common/desc_image_load.c \
drivers/ti/uart/aarch64/16550_console.S \
diff --git a/plat/mediatek/mt8195/plat_sip_calls.c b/plat/mediatek/mt8195/plat_sip_calls.c
index 2debeff..faa0ba5 100644
--- a/plat/mediatek/mt8195/plat_sip_calls.c
+++ b/plat/mediatek/mt8195/plat_sip_calls.c
@@ -31,7 +31,7 @@
case MTK_SIP_TEE_MPU_PERM_SET_AARCH64:
case MTK_SIP_TEE_MPU_PERM_SET_AARCH32:
ret = emi_mpu_sip_handler(x1, x2, x3);
- SMC_RET2(handle, ret, ret_val);
+ SMC_RET1(handle, ret);
break;
case MTK_SIP_DP_CONTROL_AARCH32:
case MTK_SIP_DP_CONTROL_AARCH64:
diff --git a/plat/mediatek/mt8196/plat_config.mk b/plat/mediatek/mt8196/plat_config.mk
index e0dd87e..a7f17e1 100644
--- a/plat/mediatek/mt8196/plat_config.mk
+++ b/plat/mediatek/mt8196/plat_config.mk
@@ -59,6 +59,7 @@
CONFIG_MTK_PMIC := y
CONFIG_MTK_PMIC_LOWPOWER := y
CONFIG_MTK_PMIC_SHUTDOWN_CFG := y
+CONFIG_MTK_PMIC_SHUTDOWN_V2 := y
CONFIG_MTK_PMIC_SPT_SUPPORT := n
CONFIG_MTK_SMMU_SID := y
CONFIG_MTK_SPMI := y
diff --git a/plat/mediatek/mt8196/platform.mk b/plat/mediatek/mt8196/platform.mk
index e98ec4b..f473b8f 100644
--- a/plat/mediatek/mt8196/platform.mk
+++ b/plat/mediatek/mt8196/platform.mk
@@ -67,8 +67,7 @@
MODULES-$(CONFIG_MTK_MTCMOS) += $(MTK_PLAT)/drivers/mtcmos
ifneq ($(MTKLIB_PATH),)
-LDFLAGS += -L $(dir $(MTKLIB_PATH))
-LDLIBS += -Wl,--whole-archive -l$(patsubst lib%.a,%,$(notdir $(MTKLIB_PATH))) -Wl,--no-whole-archive
+LDLIBS += -Wl,--whole-archive $(MTKLIB_PATH) -Wl,--no-whole-archive
endif
PLAT_BL_COMMON_SOURCES := common/desc_image_load.c \
diff --git a/plat/nxp/common/sip_svc/sip_svc.c b/plat/nxp/common/sip_svc/sip_svc.c
index 1c8668e..4eec0ac 100644
--- a/plat/nxp/common/sip_svc/sip_svc.c
+++ b/plat/nxp/common/sip_svc/sip_svc.c
@@ -100,7 +100,7 @@
}
/* break is not required as SMC_RETx return */
case SIP_SVC_HUK:
- if (is_sec_enabled() == false) {
+ if (ns != 0 || is_sec_enabled() == false) {
NOTICE("SEC is disabled.\n");
SMC_RET1(handle, SMC_UNK);
}
diff --git a/plat/nxp/s32/s32g274ardb2/include/platform_def.h b/plat/nxp/s32/s32g274ardb2/include/platform_def.h
index cb16658..227c8e6 100644
--- a/plat/nxp/s32/s32g274ardb2/include/platform_def.h
+++ b/plat/nxp/s32/s32g274ardb2/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -44,24 +44,34 @@
#define BL33_BASE UL(0x34500000)
#define BL33_LIMIT UL(0x345FF000)
+/* IO buffer used to copy images from storage */
+#define IO_BUFFER_BASE BL33_LIMIT
+#define IO_BUFFER_SIZE U(0x13000)
+
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 36)
/* We'll be doing a 1:1 mapping anyway */
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 36)
-#define MAX_MMAP_REGIONS U(18)
-#define MAX_XLAT_TABLES U(32)
+#define MAX_MMAP_REGIONS U(21)
+#define MAX_XLAT_TABLES U(33)
/* Console settings */
#define UART_BASE UL(0x401C8000)
#define UART_BAUDRATE U(115200)
#define UART_CLOCK_HZ U(125000000)
+/* uSDHC */
+#define S32G_USDHC_BASE UL(0x402F0000)
+
#define S32G_FIP_BASE UL(0x34100000)
#define S32G_FIP_SIZE UL(0x100000)
#define MAX_IO_HANDLES U(2)
#define MAX_IO_DEVICES U(2)
+/* uSDHC as block device */
+#define MAX_IO_BLOCK_DEVICES U(1)
+
/* GIC settings */
#define S32G_GIC_BASE UL(0x50800000)
#define PLAT_GICD_BASE S32G_GIC_BASE
diff --git a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c
index 0929f9d..810b7bb 100644
--- a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c
+++ b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,7 +8,10 @@
#include <common/debug.h>
#include <common/desc_image_load.h>
+#include <drivers/generic_delay_timer.h>
+#include <imx_usdhc.h>
#include <lib/mmio.h>
+#include <lib/utils.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <plat_console.h>
@@ -70,6 +73,29 @@
mmio_write_32(SIUL2_PC10_LIN0_IMCR, LIN0_RX_IMCR_CFG);
}
+static void init_s32g_usdhc(void)
+{
+ static struct mmc_device_info sd_device_info = {
+ .mmc_dev_type = MMC_IS_SD_HC,
+ .ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4,
+ };
+ imx_usdhc_params_t params;
+
+ zeromem(¶ms, sizeof(imx_usdhc_params_t));
+
+ params.reg_base = S32G_USDHC_BASE;
+ params.clk_rate = 25000000;
+ params.bus_width = MMC_BUS_WIDTH_4;
+ params.flags = MMC_FLAG_SD_CMD6;
+
+ imx_usdhc_init(¶ms, &sd_device_info);
+}
+
+static void plat_s32_mmc_setup(void)
+{
+ init_s32g_usdhc();
+}
+
void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
@@ -103,9 +129,18 @@
panic();
}
+ generic_delay_timer_init();
+
+ /* Configure the generic timer frequency to ensure proper operation
+ * of the architectural timer in BL2.
+ */
+ write_cntfrq_el0(plat_get_syscnt_freq2());
+
linflex_config_pinctrl();
console_s32g2_register();
+ plat_s32_mmc_setup();
+
plat_s32g2_io_setup();
}
diff --git a/plat/nxp/s32/s32g274ardb2/plat_helpers.S b/plat/nxp/s32/s32g274ardb2/plat_helpers.S
index a7dda0d..924808b 100644
--- a/plat/nxp/s32/s32g274ardb2/plat_helpers.S
+++ b/plat/nxp/s32/s32g274ardb2/plat_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -121,6 +121,9 @@
mov_imm x1, BL33_LIMIT
sub x1, x1, x0
bl zeromem
+ mov_imm x0, IO_BUFFER_BASE
+ mov_imm x1, IO_BUFFER_SIZE
+ bl zeromem
mov x30, x10
ret
endfunc platform_mem_init
diff --git a/plat/nxp/s32/s32g274ardb2/plat_io_storage.c b/plat/nxp/s32/s32g274ardb2/plat_io_storage.c
index db6bcc5..c4efe01 100644
--- a/plat/nxp/s32/s32g274ardb2/plat_io_storage.c
+++ b/plat/nxp/s32/s32g274ardb2/plat_io_storage.c
@@ -1,14 +1,19 @@
/*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
+#include <drivers/io/io_block.h>
#include <drivers/io/io_driver.h>
#include <drivers/io/io_fip.h>
#include <drivers/io/io_memmap.h>
+#include <drivers/mmc.h>
+#include <drivers/partition/partition.h>
+#include <lib/utils.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <tools_share/firmware_image_package.h>
@@ -20,24 +25,23 @@
int (*check)(const uintptr_t spec);
};
-static int open_memmap(const uintptr_t spec);
-static int open_fip(const uintptr_t spec);
-
static uintptr_t fip_dev_handle;
-static uintptr_t memmap_dev_handle;
+static io_block_spec_t fip_mmc_spec;
-static int open_memmap(const uintptr_t spec)
+static uintptr_t mmc_dev_handle;
+
+static int open_mmc(const uintptr_t spec)
{
- uintptr_t temp_handle = 0U;
+ uintptr_t temp_handle;
int result;
- result = io_dev_init(memmap_dev_handle, (uintptr_t)0);
+ result = io_dev_init(mmc_dev_handle, (uintptr_t)0U);
if (result != 0) {
return result;
}
- result = io_open(memmap_dev_handle, spec, &temp_handle);
+ result = io_open(mmc_dev_handle, spec, &temp_handle);
if (result == 0) {
(void)io_close(temp_handle);
}
@@ -66,16 +70,43 @@
void plat_s32g2_io_setup(void)
{
- static const io_dev_connector_t *memmap_dev_con;
+ static const io_block_dev_spec_t mmc_dev_spec = {
+ /* It's used as temp buffer in block driver. */
+ .buffer = {
+ .offset = IO_BUFFER_BASE,
+ .length = IO_BUFFER_SIZE,
+ },
+ .ops = {
+ .read = mmc_read_blocks,
+ .write = mmc_write_blocks,
+ },
+ .block_size = MMC_BLOCK_SIZE,
+ };
static const io_dev_connector_t *fip_dev_con;
+ static const io_dev_connector_t *mmc_dev_con;
+ partition_entry_t fip_part;
+ uintptr_t io_buf_base;
int result __unused;
+ size_t io_buf_size;
+ int ret;
- result = register_io_dev_memmap(&memmap_dev_con);
+ io_buf_base = mmc_dev_spec.buffer.offset;
+ io_buf_size = mmc_dev_spec.buffer.length;
+
+ ret = mmap_add_dynamic_region(io_buf_base, io_buf_base,
+ io_buf_size,
+ MT_MEMORY | MT_RW | MT_SECURE);
+ if (ret != 0) {
+ ERROR("Failed to map the IO buffer\n");
+ panic();
+ }
+
+ result = register_io_dev_block(&mmc_dev_con);
assert(result == 0);
- result = io_dev_open(memmap_dev_con, (uintptr_t)0,
- &memmap_dev_handle);
+ result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_dev_spec,
+ &mmc_dev_handle);
assert(result == 0);
result = register_io_dev_fip(&fip_dev_con);
@@ -84,14 +115,24 @@
result = io_dev_open(fip_dev_con, (uintptr_t)0,
&fip_dev_handle);
assert(result == 0);
+
+ ret = gpt_partition_init();
+ if (ret != 0) {
+ ERROR("Could not load MBR partition table\n");
+ panic();
+ }
+
+ fip_part = get_partition_entry_list()->list[FIP_PART];
+ fip_mmc_spec.offset = fip_part.start;
+ fip_mmc_spec.length = fip_part.length;
}
int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
uintptr_t *image_spec)
{
- static const io_block_spec_t fip_block_spec = {
- .offset = S32G_FIP_BASE,
- .length = S32G_FIP_SIZE,
+ static const io_block_spec_t mbr_spec = {
+ .offset = 0,
+ .length = PLAT_PARTITION_BLOCK_SIZE,
};
static const io_uuid_spec_t bl31_uuid_spec = {
@@ -102,11 +143,11 @@
.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
};
- static const struct plat_io_policy policies[BL33_IMAGE_ID + 1] = {
+ static const struct plat_io_policy policies[GPT_IMAGE_ID + 1] = {
[FIP_IMAGE_ID] = {
- .dev_handle = &memmap_dev_handle,
- .image_spec = (uintptr_t)&fip_block_spec,
- .check = open_memmap,
+ .dev_handle = &mmc_dev_handle,
+ .image_spec = (uintptr_t)&fip_mmc_spec,
+ .check = open_mmc,
},
[BL31_IMAGE_ID] = {
.dev_handle = &fip_dev_handle,
@@ -118,6 +159,11 @@
.image_spec = (uintptr_t)&bl33_uuid_spec,
.check = open_fip,
},
+ [GPT_IMAGE_ID] = {
+ .dev_handle = &mmc_dev_handle,
+ .image_spec = (uintptr_t)&mbr_spec,
+ .check = open_mmc,
+ },
};
const struct plat_io_policy *policy;
int result;
diff --git a/plat/nxp/s32/s32g274ardb2/platform.mk b/plat/nxp/s32/s32g274ardb2/platform.mk
index 4ec7cd0..25e9ebd 100644
--- a/plat/nxp/s32/s32g274ardb2/platform.mk
+++ b/plat/nxp/s32/s32g274ardb2/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -20,7 +20,8 @@
S32_ERRATA_LIST += ERRATA_S32_051700
PLAT_INCLUDES = \
- -I${PLAT_S32G274ARDB2}/include
+ -I${PLAT_S32G274ARDB2}/include \
+ -Idrivers/imx/usdhc \
PROGRAMMABLE_RESET_ADDRESS := 1
@@ -41,12 +42,19 @@
PLAT_XLAT_TABLES_DYNAMIC := 1
$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
+NXP_ESDHC_LE := 1
+$(eval $(call add_define,NXP_ESDHC_LE))
+
# Selecting Drivers for SoC
$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
$(eval $(call SET_NXP_MAKE_FLAG,CLK_NEEDED,BL_COMM))
include ${PLAT_DRIVERS_PATH}/drivers.mk
+# Selecting the raw partition where the FIP image is stored
+FIP_PART ?= 0
+$(eval $(call add_define,FIP_PART))
+
BL_COMMON_SOURCES += \
${PLAT_S32G274ARDB2}/plat_console.c \
${PLAT_S32G274ARDB2}/plat_helpers.S \
@@ -60,11 +68,21 @@
${PLAT_S32G274ARDB2}/plat_io_storage.c \
${PLAT_S32G274ARDB2}/s32cc_ncore.c \
common/desc_image_load.c \
+ common/tf_crc32.c \
+ drivers/delay_timer/delay_timer.c \
+ drivers/delay_timer/generic_delay_timer.c \
+ drivers/imx/usdhc/imx_usdhc.c \
+ drivers/io/io_block.c \
drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
+ drivers/mmc/mmc.c \
+ drivers/partition/gpt.c \
+ drivers/partition/partition.c \
lib/cpus/aarch64/cortex_a53.S \
+BL2_CPPFLAGS += -march=armv8-a+crc
+
BL31_SOURCES += \
${GICV3_SOURCES} \
${PLAT_S32G274ARDB2}/plat_bl31_setup.c \
diff --git a/plat/nxp/s32/s32g274ardb2/s32cc_bl_common.c b/plat/nxp/s32/s32g274ardb2/s32cc_bl_common.c
index 4664438..eb903c5 100644
--- a/plat/nxp/s32/s32g274ardb2/s32cc_bl_common.c
+++ b/plat/nxp/s32/s32g274ardb2/s32cc_bl_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,6 +7,7 @@
#include <common/bl_common.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <plat/common/platform.h>
#include <s32cc-bl-common.h>
@@ -38,3 +39,8 @@
return 0;
}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+ return COUNTER_FREQUENCY;
+}
diff --git a/plat/nxp/s32/s32g274ardb2/s32g2_soc.c b/plat/nxp/s32/s32g274ardb2/s32g2_soc.c
index 0001352..c005bad 100644
--- a/plat/nxp/s32/s32g274ardb2/s32g2_soc.c
+++ b/plat/nxp/s32/s32g274ardb2/s32g2_soc.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -45,8 +45,3 @@
return (int)core_id;
}
-
-unsigned int plat_get_syscnt_freq2(void)
-{
- return COUNTER_FREQUENCY;
-}
diff --git a/plat/nxp/soc-lx2160a/aarch64/lx2160a_helpers.S b/plat/nxp/soc-lx2160a/aarch64/lx2160a_helpers.S
index c364dec..d44e9fc 100644
--- a/plat/nxp/soc-lx2160a/aarch64/lx2160a_helpers.S
+++ b/plat/nxp/soc-lx2160a/aarch64/lx2160a_helpers.S
@@ -7,6 +7,7 @@
#include <arch.h>
#include <asm_macros.S>
+#include <cpu_macros.S>
#include <platform_def.h>
@@ -36,6 +37,8 @@
mov x29, x30
bl apply_platform_errata
+ sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP
+
#if defined(IMAGE_BL31)
ldr x0, =POLICY_SMMU_PAGESZ_64K
cbz x0, 1f
diff --git a/plat/nxp/soc-lx2160a/ddr_tbbr.mk b/plat/nxp/soc-lx2160a/ddr_tbbr.mk
index 836a431..2bb05f1 100644
--- a/plat/nxp/soc-lx2160a/ddr_tbbr.mk
+++ b/plat/nxp/soc-lx2160a/ddr_tbbr.mk
@@ -24,11 +24,6 @@
# NON_TRUSTED_WORLD_KEY
#
-# Copy the tbbr.mk from PLAT_TOOL_PATH/cert_create_helper
-# to the ${PLAT_DIR}. So that cert_create is enabled
-# to create certificates for DDR
-$(shell cp ${PLAT_TOOL_PATH}/cert_create_helper/cert_create_tbbr.mk ${PLAT_DIR})
-
# Certificate generation tool default parameters
DDR_FW_CERT := ${BUILD_PLAT}/ddr_fw_key_cert.crt
diff --git a/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk b/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk
index 226b22b..12fbac4 100644
--- a/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk
+++ b/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk
@@ -12,8 +12,8 @@
NXP_COINED_BB := no
# DDR Compilation Configs
-NUM_OF_DDRC := 1
-DDRC_NUM_DIMM := 1
+NUM_OF_DDRC := 2
+DDRC_NUM_DIMM := 2
DDRC_NUM_CS := 2
DDR_ECC_EN := yes
#enable address decoding feature
diff --git a/tools/nxp/cert_create_helper/include/pdef_tbb_cert.h b/plat/nxp/soc-lx2160a/lx2162aqds/cert_create_helper/include/pdef_tbb_cert.h
similarity index 100%
rename from tools/nxp/cert_create_helper/include/pdef_tbb_cert.h
rename to plat/nxp/soc-lx2160a/lx2162aqds/cert_create_helper/include/pdef_tbb_cert.h
diff --git a/tools/nxp/cert_create_helper/include/pdef_tbb_ext.h b/plat/nxp/soc-lx2160a/lx2162aqds/cert_create_helper/include/pdef_tbb_ext.h
similarity index 100%
rename from tools/nxp/cert_create_helper/include/pdef_tbb_ext.h
rename to plat/nxp/soc-lx2160a/lx2162aqds/cert_create_helper/include/pdef_tbb_ext.h
diff --git a/tools/nxp/cert_create_helper/include/pdef_tbb_key.h b/plat/nxp/soc-lx2160a/lx2162aqds/cert_create_helper/include/pdef_tbb_key.h
similarity index 100%
rename from tools/nxp/cert_create_helper/include/pdef_tbb_key.h
rename to plat/nxp/soc-lx2160a/lx2162aqds/cert_create_helper/include/pdef_tbb_key.h
diff --git a/tools/nxp/cert_create_helper/src/pdef_tbb_cert.c b/plat/nxp/soc-lx2160a/lx2162aqds/cert_create_helper/src/pdef_tbb_cert.c
similarity index 100%
rename from tools/nxp/cert_create_helper/src/pdef_tbb_cert.c
rename to plat/nxp/soc-lx2160a/lx2162aqds/cert_create_helper/src/pdef_tbb_cert.c
diff --git a/tools/nxp/cert_create_helper/src/pdef_tbb_ext.c b/plat/nxp/soc-lx2160a/lx2162aqds/cert_create_helper/src/pdef_tbb_ext.c
similarity index 100%
rename from tools/nxp/cert_create_helper/src/pdef_tbb_ext.c
rename to plat/nxp/soc-lx2160a/lx2162aqds/cert_create_helper/src/pdef_tbb_ext.c
diff --git a/tools/nxp/cert_create_helper/src/pdef_tbb_key.c b/plat/nxp/soc-lx2160a/lx2162aqds/cert_create_helper/src/pdef_tbb_key.c
similarity index 100%
rename from tools/nxp/cert_create_helper/src/pdef_tbb_key.c
rename to plat/nxp/soc-lx2160a/lx2162aqds/cert_create_helper/src/pdef_tbb_key.c
diff --git a/plat/nxp/soc-lx2160a/lx2162aqds/cert_create_tbbr.mk b/plat/nxp/soc-lx2160a/lx2162aqds/cert_create_tbbr.mk
new file mode 100644
index 0000000..8d1a14c
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2162aqds/cert_create_tbbr.mk
@@ -0,0 +1,31 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Compile time defines used by NXP platforms
+
+PLAT_DEF_OID := yes
+
+ifeq (${PLAT_DEF_OID},yes)
+
+CRTTOOL_DEFINES += PLAT_DEF_OID
+CRTTOOL_DEFINES += PDEF_KEYS
+CRTTOOL_DEFINES += PDEF_CERTS
+CRTTOOL_DEFINES += PDEF_EXTS
+
+
+CRTTOOL_INCLUDE_DIRS += ${PLAT_DIR}/../common/fip_handler/common/
+
+PDEF_CERT_TOOL_PATH := ${PLAT_DIR}/cert_create_helper
+CRTTOOL_INCLUDE_DIRS += ${PDEF_CERT_TOOL_PATH}/include
+
+PLAT_OBJECTS += ${PDEF_CERT_TOOL_PATH}/src/pdef_tbb_cert.c \
+ ${PDEF_CERT_TOOL_PATH}/src/pdef_tbb_ext.c \
+ ${PDEF_CERT_TOOL_PATH}/src/pdef_tbb_key.c
+
+$(shell rm ${PLAT_OBJECTS})
+
+CRTTOOL_SOURCES += ${PLAT_OBJECTS}
+endif
diff --git a/plat/qemu/common/qemu_bl2_setup.c b/plat/qemu/common/qemu_bl2_setup.c
index 71f9cf7..209dcd7 100644
--- a/plat/qemu/common/qemu_bl2_setup.c
+++ b/plat/qemu/common/qemu_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,7 +19,9 @@
#include <common/fdt_fixup.h>
#include <common/fdt_wrappers.h>
#include <lib/optee_utils.h>
-#include <lib/transfer_list.h>
+#if TRANSFER_LIST
+#include <transfer_list.h>
+#endif
#include <lib/utils.h>
#include <plat/common/platform.h>
@@ -50,7 +52,7 @@
/* Data structure which holds the extents of the trusted SRAM for BL2 */
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
-static struct transfer_list_header *bl2_tl;
+static struct transfer_list_header __maybe_unused *bl2_tl;
void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
@@ -344,11 +346,11 @@
INFO("Handoff to BL32\n");
bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl32_entry();
- if (TRANSFER_LIST &&
- transfer_list_set_handoff_args(bl2_tl,
- &bl_mem_params->ep_info))
+#if TRANSFER_LIST
+ if (transfer_list_set_handoff_args(bl2_tl,
+ &bl_mem_params->ep_info))
break;
-
+#endif
INFO("Using default arguments\n");
#if defined(SPMC_OPTEE)
/*
diff --git a/plat/qemu/common/qemu_bl31_setup.c b/plat/qemu/common/qemu_bl31_setup.c
index 1c5e0ea..a350ce5 100644
--- a/plat/qemu/common/qemu_bl31_setup.c
+++ b/plat/qemu/common/qemu_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,7 +9,9 @@
#include <common/bl_common.h>
#include <drivers/arm/pl061_gpio.h>
#include <lib/gpt_rme/gpt_rme.h>
-#include <lib/transfer_list.h>
+#if TRANSFER_LIST
+#include <transfer_list.h>
+#endif
#include <plat/common/platform.h>
#if ENABLE_RME
#ifdef PLAT_qemu
@@ -79,7 +81,7 @@
#if ENABLE_RME
static entry_point_info_t rmm_image_ep_info;
#endif
-static struct transfer_list_header *bl31_tl;
+static struct transfer_list_header __maybe_unused *bl31_tl;
/*******************************************************************************
* Perform any BL3-1 early platform setup. Here is an opportunity to copy
@@ -92,8 +94,8 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- bool is64 = false;
- uint64_t hval;
+ bool __maybe_unused is64 = false;
+ uint64_t __maybe_unused hval;
/* Initialize the console to provide early debug support */
qemu_console_init();
@@ -119,11 +121,11 @@
* They are stored in Secure RAM, in BL2's address space.
*/
while (bl_params) {
-#ifdef __aarch64__
+#if defined(__aarch64__) && TRANSFER_LIST
if (bl_params->image_id == BL31_IMAGE_ID &&
GET_RW(bl_params->ep_info->spsr) == MODE_RW_64)
is64 = true;
-#endif
+#endif /* defined(__aarch64__) && TRANSFER_LIST */
if (bl_params->image_id == BL32_IMAGE_ID)
bl32_image_ep_info = *bl_params->ep_info;
@@ -145,8 +147,8 @@
panic();
#endif
- if (!TRANSFER_LIST ||
- !transfer_list_check_header((void *)arg3))
+#if TRANSFER_LIST
+ if (!transfer_list_check_header((void *)arg3))
return;
if (is64)
@@ -156,6 +158,7 @@
if (arg1 != hval)
return;
+#endif
bl31_tl = (void *)arg3; /* saved TL address from BL2 */
}
diff --git a/plat/qti/common/src/qti_pm.c b/plat/qti/common/src/qti_pm.c
index 2428126..3f919f2 100644
--- a/plat/qti/common/src/qti_pm.c
+++ b/plat/qti/common/src/qti_pm.c
@@ -211,15 +211,6 @@
}
}
-__dead2 void qti_domain_power_down_wfi(const psci_power_state_t *target_state)
-{
-
- /* For now just do WFI - add any target specific handling if needed */
- psci_power_down_wfi();
- /* We should never reach here */
- panic();
-}
-
static __dead2 void assert_ps_hold(void)
{
mmio_write_32(QTI_PS_HOLD_REG, 0);
@@ -278,7 +269,6 @@
.pwr_domain_off = qti_node_power_off,
.pwr_domain_suspend = qti_node_suspend,
.pwr_domain_suspend_finish = qti_node_suspend_finish,
- .pwr_domain_pwr_down = qti_domain_power_down_wfi,
.system_off = qti_system_off,
.system_reset = qti_system_reset,
.get_node_hw_state = NULL,
diff --git a/plat/qti/qcs615/inc/qti_secure_io_cfg.h b/plat/qti/qcs615/inc/qti_secure_io_cfg.h
index a78583e..c386e2b 100644
--- a/plat/qti/qcs615/inc/qti_secure_io_cfg.h
+++ b/plat/qti/qcs615/inc/qti_secure_io_cfg.h
@@ -12,6 +12,7 @@
* List of peripheral/IO memory areas that are protected from
* non-secure world but not required to be secure.
*/
+#define EUD_MODE_MANAGER2_EN 0x088E4000
#define APPS_SMMU_TBU_PWR_STATUS 0x15002204
#define APPS_SMMU_CUSTOM_CFG 0x15002300
#define APPS_SMMU_STATS_SYNC_INV_TBU_ACK 0x150025DC
@@ -19,6 +20,7 @@
#define APPS_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR 0x15002648
static const uintptr_t qti_secure_io_allowed_regs[] = {
+ EUD_MODE_MANAGER2_EN,
APPS_SMMU_TBU_PWR_STATUS,
APPS_SMMU_CUSTOM_CFG,
APPS_SMMU_STATS_SYNC_INV_TBU_ACK,
diff --git a/plat/qti/qcs615/platform.mk b/plat/qti/qcs615/platform.mk
index a3136cb..ff4489a 100644
--- a/plat/qti/qcs615/platform.mk
+++ b/plat/qti/qcs615/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
# Copyright (c) 2024, The Linux Foundation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -136,7 +136,6 @@
BL31_SOURCES += plat/qti/qtiseclib/src/qtiseclib_interface_stub.c
else
# use library provided by QTISECLIB_PATH
-LDFLAGS += -L $(dir $(QTISECLIB_PATH))
-LDLIBS += -l$(patsubst lib%.a,%,$(notdir $(QTISECLIB_PATH)))
+LDLIBS += $(QTISECLIB_PATH)
endif
diff --git a/plat/qti/sc7180/inc/qti_secure_io_cfg.h b/plat/qti/sc7180/inc/qti_secure_io_cfg.h
index 3de636d..5f07cb5 100644
--- a/plat/qti/sc7180/inc/qti_secure_io_cfg.h
+++ b/plat/qti/sc7180/inc/qti_secure_io_cfg.h
@@ -13,6 +13,7 @@
* non-secure world but not required to be secure.
*/
+#define EUD_MODE_MANAGER2_EN 0x088E2000
#define APPS_SMMU_TBU_PWR_STATUS 0x15002204
#define APPS_SMMU_CUSTOM_CFG 0x15002300
#define APPS_SMMU_STATS_SYNC_INV_TBU_ACK 0x150025DC
@@ -20,6 +21,7 @@
#define APPS_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR 0x15002670
static const uintptr_t qti_secure_io_allowed_regs[] = {
+ EUD_MODE_MANAGER2_EN,
APPS_SMMU_TBU_PWR_STATUS,
APPS_SMMU_CUSTOM_CFG,
APPS_SMMU_STATS_SYNC_INV_TBU_ACK,
diff --git a/plat/qti/sc7180/platform.mk b/plat/qti/sc7180/platform.mk
index b576649..adbaea5 100644
--- a/plat/qti/sc7180/platform.mk
+++ b/plat/qti/sc7180/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
# Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -120,7 +120,6 @@
BL31_SOURCES += plat/qti/qtiseclib/src/qtiseclib_interface_stub.c
else
# use library provided by QTISECLIB_PATH
-LDFLAGS += -L $(dir $(QTISECLIB_PATH))
-LDLIBS += -l$(patsubst lib%.a,%,$(notdir $(QTISECLIB_PATH)))
+LDLIBS += $(QTISECLIB_PATH)
endif
diff --git a/plat/qti/sc7280/inc/qti_secure_io_cfg.h b/plat/qti/sc7280/inc/qti_secure_io_cfg.h
index 058c5b5..24a0a34 100644
--- a/plat/qti/sc7280/inc/qti_secure_io_cfg.h
+++ b/plat/qti/sc7280/inc/qti_secure_io_cfg.h
@@ -13,6 +13,7 @@
* non-secure world but not required to be secure.
*/
+#define EUD_MODE_MANAGER2_EN 0x088E2000
#define APPS_SMMU_TBU_PWR_STATUS 0x15002204
#define APPS_SMMU_CUSTOM_CFG 0x15002300
#define APPS_SMMU_STATS_SYNC_INV_TBU_ACK 0x150025DC
@@ -20,6 +21,7 @@
#define APPS_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR 0x15002670
static const uintptr_t qti_secure_io_allowed_regs[] = {
+ EUD_MODE_MANAGER2_EN,
APPS_SMMU_TBU_PWR_STATUS,
APPS_SMMU_CUSTOM_CFG,
APPS_SMMU_STATS_SYNC_INV_TBU_ACK,
diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h
index 6388c47..7dcbec9 100644
--- a/plat/rockchip/common/include/plat_private.h
+++ b/plat/rockchip/common/include/plat_private.h
@@ -129,9 +129,9 @@
int rockchip_soc_cores_pwr_dm_resume(void);
void __dead2 rockchip_soc_soft_reset(void);
void __dead2 rockchip_soc_system_off(void);
-void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi(
+void rockchip_soc_cores_pd_pwr_dn_wfi(
const psci_power_state_t *target_state);
-void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void);
+void rockchip_soc_sys_pd_pwr_dn_wfi(void);
extern const unsigned char rockchip_power_domain_tree_desc[];
diff --git a/plat/rockchip/common/plat_pm.c b/plat/rockchip/common/plat_pm.c
index df74033..122bc85 100644
--- a/plat/rockchip/common/plat_pm.c
+++ b/plat/rockchip/common/plat_pm.c
@@ -114,19 +114,13 @@
;
}
-void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi(
+void rockchip_soc_cores_pd_pwr_dn_wfi(
const psci_power_state_t *target_state)
{
- psci_power_down_wfi();
- /* should never reach here */
- panic();
}
-void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void)
+void rockchip_soc_sys_pd_pwr_dn_wfi(void)
{
- psci_power_down_wfi();
- /* should never reach here */
- panic();
}
/*******************************************************************************
@@ -374,7 +368,7 @@
rockchip_soc_system_off();
}
-static void __dead2 rockchip_pd_pwr_down_wfi(
+static void rockchip_pd_pwr_down_wfi(
const psci_power_state_t *target_state)
{
if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
diff --git a/plat/rockchip/px30/drivers/pmu/pmu.c b/plat/rockchip/px30/drivers/pmu/pmu.c
index 6200cac..2d576bb 100644
--- a/plat/rockchip/px30/drivers/pmu/pmu.c
+++ b/plat/rockchip/px30/drivers/pmu/pmu.c
@@ -999,9 +999,9 @@
* Maybe the HW needs some times to reset the system,
* so we do not hope the core to execute valid codes.
*/
- psci_power_down_wfi();
- /* should never reach here */
- panic();
+ while (1) {
+ wfi();
+ }
}
void __dead2 rockchip_soc_system_off(void)
@@ -1026,9 +1026,9 @@
* Maybe the HW needs some times to reset the system,
* so we do not hope the core to execute valid codes.
*/
- psci_power_down_wfi();
- /* should never reach here */
- panic();
+ while (1) {
+ wfi();
+ }
}
void rockchip_plat_mmu_el3(void)
diff --git a/plat/rockchip/rk3328/drivers/pmu/pmu.c b/plat/rockchip/rk3328/drivers/pmu/pmu.c
index 41660e2..6fd1bfb 100644
--- a/plat/rockchip/rk3328/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3328/drivers/pmu/pmu.c
@@ -613,14 +613,9 @@
sram_soc_enter_lp();
}
-void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void)
+void rockchip_soc_sys_pd_pwr_dn_wfi(void)
{
sram_suspend();
-
- /* should never reach here */
- psci_power_down_wfi();
- /* should never reach here */
- panic();
}
int rockchip_soc_sys_pwr_dm_suspend(void)
diff --git a/plat/rockchip/rk3576/drivers/pmu/pmu.c b/plat/rockchip/rk3576/drivers/pmu/pmu.c
index c7db176..ad0132a 100644
--- a/plat/rockchip/rk3576/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3576/drivers/pmu/pmu.c
@@ -939,21 +939,6 @@
return 0;
}
-void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi(const
- psci_power_state_t *target_state)
-{
- psci_power_down_wfi();
- /* should never reach here */
- panic();
-}
-
-void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void)
-{
- psci_power_down_wfi();
- /* should never reach here */
- panic();
-}
-
static int rockchip_reboot_is_rbrom(void)
{
return mmio_read_32(PMU0_GRF_BASE + PMU0GRF_OS_REG(16)) ==
@@ -998,9 +983,9 @@
* Maybe the HW needs some times to reset the system,
* so we do not hope the core to execute valid codes.
*/
- psci_power_down_wfi();
- /* should never reach here */
- panic();
+ while (1) {
+ wfi();
+ }
}
void __dead2 rockchip_soc_system_off(void)
@@ -1020,9 +1005,9 @@
* Maybe the HW needs some times to reset the system,
* so we do not hope the core to execute valid codes.
*/
- psci_power_down_wfi();
- /* should never reach here */
- panic();
+ while (1) {
+ wfi();
+ }
}
static void rockchip_pmu_pd_repair_init(void)
diff --git a/plat/rockchip/rk3588/drivers/pmu/pmu.c b/plat/rockchip/rk3588/drivers/pmu/pmu.c
index 16436dd..1a6394d 100644
--- a/plat/rockchip/rk3588/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3588/drivers/pmu/pmu.c
@@ -1315,20 +1315,9 @@
return 0;
}
-void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi(const
- psci_power_state_t *target_state)
-{
- psci_power_down_wfi();
- /* should never reach here */
- panic();
-}
-
-void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void)
+void rockchip_soc_sys_pd_pwr_dn_wfi(void)
{
cpus_pd_req_enter_wfi();
- psci_power_down_wfi();
- /* should never reach here */
- panic();
}
void __dead2 rockchip_soc_soft_reset(void)
@@ -1355,9 +1344,9 @@
* Maybe the HW needs some times to reset the system,
* so we do not hope the core to execute valid codes.
*/
- psci_power_down_wfi();
- /* should never reach here */
- panic();
+ while (1) {
+ wfi();
+ }
}
void __dead2 rockchip_soc_system_off(void)
@@ -1378,9 +1367,9 @@
* Maybe the HW needs some times to reset the system,
* so we do not hope the core to execute valid codes.
*/
- psci_power_down_wfi();
- /* should never reach here */
- panic();
+ while (1) {
+ wfi();
+ }
}
static void rockchip_pmu_pd_init(void)
diff --git a/plat/st/common/common.mk b/plat/st/common/common.mk
index 4dbb949..0bedb72 100644
--- a/plat/st/common/common.mk
+++ b/plat/st/common/common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
+# Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
# Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -27,7 +27,10 @@
STM32_HEADER_BL2_BINARY_TYPE := 0x10
TF_CFLAGS += -Wsign-compare
+ifeq ($(findstring clang,$(notdir $(CC))),)
+# Only for GCC
TF_CFLAGS += -Wformat-signedness
+endif
# Number of TF-A copies in the device
STM32_TF_A_COPIES := 2
@@ -77,7 +80,7 @@
# Variables for use with stm32image
STM32IMAGEPATH ?= tools/stm32image
-STM32IMAGE ?= ${STM32IMAGEPATH}/stm32image$(.exe)
+STM32IMAGE ?= ${BUILD_PLAT}/${STM32IMAGEPATH}/stm32image$(.exe)
STM32IMAGE_SRC := ${STM32IMAGEPATH}/stm32image.c
STM32_DEPS += ${STM32IMAGE}
@@ -198,16 +201,9 @@
TF_MBEDTLS_KEY_ALG := ecdsa
KEY_SIZE := 256
-ifneq (${MBEDTLS_DIR},)
-MBEDTLS_MAJOR=$(shell grep -hP "define MBEDTLS_VERSION_MAJOR" \
-${MBEDTLS_DIR}/include/mbedtls/*.h | grep -oe '\([0-9.]*\)')
+PLAT_INCLUDES += -Iinclude/drivers/auth/mbedtls
-ifeq (${MBEDTLS_MAJOR}, 3)
-MBEDTLS_CONFIG_FILE ?= "<stm32mp_mbedtls_config-3.h>"
-else
-$(error Error: TF-A only supports MbedTLS versions > 3.x)
-endif
-endif
+MBEDTLS_CONFIG_FILE ?= "<stm32mp_mbedtls_config.h>"
include drivers/auth/mbedtls/mbedtls_x509.mk
diff --git a/plat/st/common/common_rules.mk b/plat/st/common/common_rules.mk
index 88c1087..864544f 100644
--- a/plat/st/common/common_rules.mk
+++ b/plat/st/common/common_rules.mk
@@ -28,10 +28,10 @@
stm32image: ${STM32IMAGE}
${STM32IMAGE}: ${STM32IMAGE_SRC}
- $(q)${MAKE} CPPFLAGS="" --no-print-directory -C ${STM32IMAGEPATH}
+ $(q)${MAKE} CPPFLAGS="" BUILD_PLAT=$(abspath ${BUILD_PLAT}) --no-print-directory -C ${STM32IMAGEPATH}
clean_stm32image:
- $(q)${MAKE} --no-print-directory -C ${STM32IMAGEPATH} clean
+ $(q)${MAKE} BUILD_PLAT=$(abspath ${BUILD_PLAT}) --no-print-directory -C ${STM32IMAGEPATH} clean
check_dtc_version:
$(q)if [ ${DTC_VERSION} -lt 10407 ]; then \
@@ -71,8 +71,13 @@
tf-a-%.stm32: tf-a-%.bin ${STM32_DEPS}
$(s)echo
$(s)echo "Generate $@"
+ifeq ($($(ARCH)-ld-id),llvm-lld)
+ $(eval LOADADDR = 0x$(shell cat $(@:.stm32=.map) | grep '\.data$$' | awk '{print $$1}'))
+ $(eval ENTRY = 0x$(shell cat $(@:.stm32=.map) | grep "__BL2_IMAGE_START" | awk '{print $$1}'))
+else
$(eval LOADADDR = $(shell cat $(@:.stm32=.map) | grep '^RAM' | awk '{print $$2}'))
$(eval ENTRY = $(shell cat $(@:.stm32=.map) | grep "__BL2_IMAGE_START" | awk '{print $$1}'))
+endif
$(q)${STM32IMAGE} -s $< -d $@ \
-l $(LOADADDR) -e ${ENTRY} \
-v ${STM32_TF_VERSION} \
diff --git a/plat/st/common/include/stm32mp_mbedtls_config-3.h b/plat/st/common/include/stm32mp_mbedtls_config-3.h
deleted file mode 100644
index 2dbf068..0000000
--- a/plat/st/common/include/stm32mp_mbedtls_config-3.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright (c) 2022-2024, STMicroelectronics - All Rights Reserved
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/*
- * Key algorithms currently supported on mbed TLS libraries
- */
-#define TF_MBEDTLS_USE_RSA 0
-#define TF_MBEDTLS_USE_ECDSA 1
-
-/*
- * Hash algorithms currently supported on mbed TLS libraries
- */
-#define TF_MBEDTLS_SHA256 1
-#define TF_MBEDTLS_SHA384 2
-#define TF_MBEDTLS_SHA512 3
-
-/*
- * Configuration file to build mbed TLS with the required features for
- * Trusted Boot
- */
-
-#define MBEDTLS_PLATFORM_MEMORY
-#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
-/* Prevent mbed TLS from using snprintf so that it can use tf_snprintf. */
-#define MBEDTLS_PLATFORM_SNPRINTF_ALT
-
-#define MBEDTLS_PKCS1_V21
-
-#define MBEDTLS_ASN1_PARSE_C
-#define MBEDTLS_ASN1_WRITE_C
-
-#define MBEDTLS_BASE64_C
-#define MBEDTLS_BIGNUM_C
-
-#define MBEDTLS_ERROR_C
-#define MBEDTLS_MD_C
-
-#define MBEDTLS_MEMORY_BUFFER_ALLOC_C
-#define MBEDTLS_OID_C
-
-#define MBEDTLS_PK_C
-#define MBEDTLS_PK_PARSE_C
-#define MBEDTLS_PK_WRITE_C
-
-#define MBEDTLS_PLATFORM_C
-
-#if TF_MBEDTLS_USE_ECDSA
-#define MBEDTLS_ECDSA_C
-#define MBEDTLS_ECP_C
-#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
-#endif
-#if TF_MBEDTLS_USE_RSA
-#define MBEDTLS_RSA_C
-#define MBEDTLS_X509_RSASSA_PSS_SUPPORT
-#endif
-
-/* The library does not currently support enabling SHA-256 without SHA-224. */
-#define MBEDTLS_SHA224_C
-#define MBEDTLS_SHA256_C
-
-#if (TF_MBEDTLS_HASH_ALG_ID != TF_MBEDTLS_SHA256)
-#define MBEDTLS_SHA384_C
-#define MBEDTLS_SHA512_C
-#endif
-
-#define MBEDTLS_VERSION_C
-
-#define MBEDTLS_X509_USE_C
-#define MBEDTLS_X509_CRT_PARSE_C
-
-#if TF_MBEDTLS_USE_AES_GCM
-#define MBEDTLS_AES_C
-#define MBEDTLS_CIPHER_C
-#define MBEDTLS_GCM_C
-#endif
-
-/* MPI / BIGNUM options */
-#define MBEDTLS_MPI_WINDOW_SIZE 2
-
-#if TF_MBEDTLS_USE_RSA
-#if TF_MBEDTLS_KEY_SIZE <= 2048
-#define MBEDTLS_MPI_MAX_SIZE 256
-#else
-#define MBEDTLS_MPI_MAX_SIZE 512
-#endif
-#else
-#define MBEDTLS_MPI_MAX_SIZE 256
-#endif
-
-/* Memory buffer allocator options */
-#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 8
-
-/*
- * Prevent the use of 128-bit division which
- * creates dependency on external libraries.
- */
-#define MBEDTLS_NO_UDBL_DIVISION
-
-#ifndef __ASSEMBLER__
-/* System headers required to build mbed TLS with the current configuration */
-#include <stdlib.h>
-#endif
-
-/*
- * Mbed TLS heap size is smal as we only use the asn1
- * parsing functions
- * digest, signature and crypto algorithm are done by
- * other library.
- */
-
-#define TF_MBEDTLS_HEAP_SIZE U(5120)
diff --git a/plat/st/common/include/stm32mp_mbedtls_config.h b/plat/st/common/include/stm32mp_mbedtls_config.h
new file mode 100644
index 0000000..d6a4cc3
--- /dev/null
+++ b/plat/st/common/include/stm32mp_mbedtls_config.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <default_mbedtls_config.h>
+
+/* MPI / BIGNUM options */
+#undef MBEDTLS_MPI_WINDOW_SIZE
+#define MBEDTLS_MPI_WINDOW_SIZE 2
+
+/*
+ * Mbed TLS heap size is small as we only use the asn1
+ * parsing functions
+ * digest, signature and crypto algorithm are done by
+ * other library.
+ */
+#undef TF_MBEDTLS_HEAP_SIZE
+#define TF_MBEDTLS_HEAP_SIZE U(5120)
diff --git a/plat/st/stm32mp1/cert_create_tbbr.mk b/plat/st/stm32mp1/cert_create_tbbr.mk
index fb9e5ec..a2daa6e 100644
--- a/plat/st/stm32mp1/cert_create_tbbr.mk
+++ b/plat/st/stm32mp1/cert_create_tbbr.mk
@@ -6,13 +6,8 @@
# Override TBBR Cert to update generic certificate
-$(eval $(call add_define,PDEF_CERTS))
+CRTTOOL_DEFINES += PDEF_CERTS
-PLAT_INCLUDE += -I${PLAT_DIR}include
+CRTTOOL_INCLUDE_DIRS += ${PLAT_DIR}include
-src/stm32mp1_tbb_cert.o: ${PLAT_DIR}stm32mp1_tbb_cert.c
- $(q)$(host-cc) -c ${HOSTCCFLAGS} ${INC_DIR} $< -o $@
-
-PLAT_OBJECTS = src/stm32mp1_tbb_cert.o
-
-OBJECTS += $(PLAT_OBJECTS)
+CRTTOOL_SOURCES += ${PLAT_DIR}stm32mp1_tbb_cert.c
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index e700823..0e0586b 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -17,6 +17,8 @@
# Default Device tree
DTB_FILE_NAME ?= stm32mp157c-ev1.dtb
+TF_CFLAGS += -DSTM32MP1X
+
STM32MP13 ?= 0
STM32MP15 ?= 0
diff --git a/plat/st/stm32mp1/stm32mp1.S b/plat/st/stm32mp1/stm32mp1.S
index aee4f0e..a688f4d 100644
--- a/plat/st/stm32mp1/stm32mp1.S
+++ b/plat/st/stm32mp1/stm32mp1.S
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-.section .bl2_image
+.section .bl2_image, "a"
.incbin BL2_BIN_PATH
-.section .dtb_image
+.section .dtb_image, "a"
.incbin DTB_BIN_PATH
diff --git a/plat/st/stm32mp1/stm32mp1.ld.S b/plat/st/stm32mp1/stm32mp1.ld.S
index 1be8219..c9d9873 100644
--- a/plat/st/stm32mp1/stm32mp1.ld.S
+++ b/plat/st/stm32mp1/stm32mp1.ld.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,17 +33,17 @@
} >HEADER
. = STM32MP_BINARY_BASE;
- .data . : {
+ .data : {
. = ALIGN(PAGE_SIZE);
__DATA_START__ = .;
- *(.data*)
+ FILL(0);
/*
* dtb.
* The strongest and only alignment contraint is MMU 4K page.
* Indeed as images below will be removed, 4K pages will be re-used.
*/
- . = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE );
+ . = ABSOLUTE( STM32MP_BL2_DTB_BASE );
__DTB_IMAGE_START__ = .;
*(.dtb_image*)
__DTB_IMAGE_END__ = .;
@@ -54,9 +54,9 @@
* Indeed as images below will be removed, 4K pages will be re-used.
*/
#if SEPARATE_CODE_AND_RODATA
- . = ( STM32MP_BL2_RO_BASE - STM32MP_BINARY_BASE );
+ . = ABSOLUTE( STM32MP_BL2_RO_BASE );
#else
- . = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE );
+ . = ABSOLUTE( STM32MP_BL2_BASE );
#endif
__BL2_IMAGE_START__ = .;
*(.bl2_image*)
diff --git a/plat/st/stm32mp2/aarch64/stm32mp2.S b/plat/st/stm32mp2/aarch64/stm32mp2.S
index 1866b8b..6c32972 100644
--- a/plat/st/stm32mp2/aarch64/stm32mp2.S
+++ b/plat/st/stm32mp2/aarch64/stm32mp2.S
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-.section .bl2_image
+.section .bl2_image, "a"
.incbin BL2_BIN_PATH
-.section .dtb_image
+.section .dtb_image, "a"
.incbin DTB_BIN_PATH
diff --git a/plat/st/stm32mp2/aarch64/stm32mp2.ld.S b/plat/st/stm32mp2/aarch64/stm32mp2.ld.S
index 48bf424..cf71f27 100644
--- a/plat/st/stm32mp2/aarch64/stm32mp2.ld.S
+++ b/plat/st/stm32mp2/aarch64/stm32mp2.ld.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,17 +33,17 @@
} >HEADER
. = STM32MP_BINARY_BASE;
- .data . : {
+ .data : {
. = ALIGN(PAGE_SIZE);
__DATA_START__ = .;
- *(.data*)
+ FILL(0);
/*
* dtb.
* The strongest and only alignment contraint is MMU 4K page.
* Indeed as images below will be removed, 4K pages will be re-used.
*/
- . = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE );
+ . = ABSOLUTE( STM32MP_BL2_DTB_BASE );
__DTB_IMAGE_START__ = .;
*(.dtb_image*)
__DTB_IMAGE_END__ = .;
@@ -54,9 +54,9 @@
* Indeed as images below will be removed, 4K pages will be re-used.
*/
#if SEPARATE_CODE_AND_RODATA
- . = ( STM32MP_BL2_RO_BASE - STM32MP_BINARY_BASE );
+ . = ABSOLUTE( STM32MP_BL2_RO_BASE );
#else
- . = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE );
+ . = ABSOLUTE( STM32MP_BL2_BASE );
#endif
__BL2_IMAGE_START__ = .;
*(.bl2_image*)
diff --git a/plat/st/stm32mp2/bl2_plat_setup.c b/plat/st/stm32mp2/bl2_plat_setup.c
index 621b784..1d49fe7 100644
--- a/plat/st/stm32mp2/bl2_plat_setup.c
+++ b/plat/st/stm32mp2/bl2_plat_setup.c
@@ -34,97 +34,46 @@
static void print_reset_reason(void)
{
uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_C1BOOTRSTSCLRR);
+ const char *reason_str = "Unidentified";
- if (rstsr == 0U) {
- WARN("Reset reason unknown\n");
- return;
+#if !STM32MP21
+ if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) {
+ INFO("CA35 processor core 1 reset\n");
}
-
- INFO("Reset reason (0x%x):\n", rstsr);
+#endif /* !STM32MP21 */
if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) == 0U) {
if ((rstsr & RCC_C1BOOTRSTSCLRR_STBYC1RSTF) != 0U) {
- INFO("System exits from Standby for CA35\n");
- return;
+ reason_str = "System exits from Standby for CA35";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) {
+ reason_str = "D1 domain exits from DStandby";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_VCPURSTF) != 0U) {
+ reason_str = "System reset from VCPU monitor";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) {
+ reason_str = "CA35 reset by CM33 (C1RST)";
+ } else {
+ reason_str = "Unidentified";
}
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) {
- INFO("D1 domain exits from DStandby\n");
- return;
+ } else {
+ if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) {
+ reason_str = "Power-on reset (por_rstn)";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) {
+ reason_str = "Brownout reset (bor_rstn)";
+ } else if ((rstsr & (RCC_C1BOOTRSTSSETR_SYSC2RSTF |
+ RCC_C1BOOTRSTSSETR_SYSC1RSTF)) != 0U) {
+ reason_str = "System reset (SYSRST)";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) {
+ reason_str = "Clock failure on HSE";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF) != 0U) {
+ reason_str = "IWDG system reset (iwdgX_out_rst)";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) {
+ reason_str = "Pin reset from NRST";
+ } else {
+ reason_str = "Unidentified";
}
}
- if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) {
- INFO(" Power-on Reset (rst_por)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) {
- INFO(" Brownout Reset (rst_bor)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC2RSTF) != 0U) {
- INFO(" System reset (SYSRST) by M33\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC1RSTF) != 0U) {
- INFO(" System reset (SYSRST) by A35\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) {
- INFO(" Clock failure on HSE\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF) != 0U) {
- INFO(" IWDG1 system reset (rst_iwdg1)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF) != 0U) {
- INFO(" IWDG2 system reset (rst_iwdg2)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF) != 0U) {
- INFO(" IWDG3 system reset (rst_iwdg3)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF) != 0U) {
- INFO(" IWDG4 system reset (rst_iwdg4)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF) != 0U) {
- INFO(" IWDG5 system reset (rst_iwdg5)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) {
- INFO(" A35 processor core 1 reset\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) {
- INFO(" Pad Reset from NRST\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_VCORERSTF) != 0U) {
- INFO(" Reset due to a failure of VDD_CORE\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) {
- INFO(" A35 processor reset\n");
- return;
- }
-
- ERROR(" Unidentified reset reason\n");
+ INFO("Reset reason: %s (0x%x)\n", reason_str, rstsr);
}
void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
@@ -164,11 +113,19 @@
* The protection is enable at each reset by hardware
* and must be disabled by software.
*/
+#if STM32MP21
+ mmio_setbits_32(pwr_base + PWR_BDCR, PWR_BDCR_DBP);
+
+ while ((mmio_read_32(pwr_base + PWR_BDCR) & PWR_BDCR_DBP) == 0U) {
+ ;
+ }
+#else /* STM32MP21 */
mmio_setbits_32(pwr_base + PWR_BDCR1, PWR_BDCR1_DBD3P);
while ((mmio_read_32(pwr_base + PWR_BDCR1) & PWR_BDCR1_DBD3P) == 0U) {
;
}
+#endif /* STM32MP21 */
/* Reset backup domain on cold boot cases */
if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) {
diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
index 06298a4..c20435b 100644
--- a/plat/st/stm32mp2/platform.mk
+++ b/plat/st/stm32mp2/platform.mk
@@ -30,11 +30,36 @@
# Default Device tree
DTB_FILE_NAME ?= stm32mp257f-ev1.dtb
-STM32MP25 := 1
+TF_CFLAGS += -DSTM32MP2X
-# STM32 image header version v2.2
+STM32MP21 ?= 0
+STM32MP23 ?= 0
+STM32MP25 ?= 0
+
+ifneq ($(findstring stm32mp21,$(DTB_FILE_NAME)),)
+STM32MP21 := 1
+endif
+ifneq ($(findstring stm32mp23,$(DTB_FILE_NAME)),)
+STM32MP23 := 1
+endif
+ifneq ($(findstring stm32mp25,$(DTB_FILE_NAME)),)
+STM32MP25 := 1
+endif
+ifneq ($(filter 1,$(STM32MP21) $(STM32MP23) $(STM32MP25)), 1)
+$(warning STM32MP21=$(STM32MP21))
+$(warning STM32MP23=$(STM32MP23))
+$(warning STM32MP25=$(STM32MP25))
+$(warning DTB_FILE_NAME=$(DTB_FILE_NAME))
+$(error Cannot enable more than one STM32MP2x flag)
+endif
+
+# STM32 image header version v2.2 or v2.3 for STM32MP21
STM32_HEADER_VERSION_MAJOR := 2
+ifeq ($(STM32MP21),1)
+STM32_HEADER_VERSION_MINOR := 3
+else
STM32_HEADER_VERSION_MINOR := 2
+endif
# Set load address for serial boot devices
DWL_BUFFER_BASE ?= 0x87000000
@@ -110,6 +135,8 @@
STM32MP_DDR3_TYPE \
STM32MP_DDR4_TYPE \
STM32MP_LPDDR4_TYPE \
+ STM32MP21 \
+ STM32MP23 \
STM32MP25 \
STM32MP_BL33_EL1 \
)))
@@ -133,6 +160,8 @@
STM32MP_DDR3_TYPE \
STM32MP_DDR4_TYPE \
STM32MP_LPDDR4_TYPE \
+ STM32MP21 \
+ STM32MP23 \
STM32MP25 \
STM32MP_BL33_EL1 \
)))
diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h
index 1b8c4f5..27fc5f9 100644
--- a/plat/st/stm32mp2/stm32mp2_def.h
+++ b/plat/st/stm32mp2/stm32mp2_def.h
@@ -10,16 +10,31 @@
#include <common/tbbr/tbbr_img_def.h>
#ifndef __ASSEMBLER__
#include <drivers/st/bsec.h>
-#endif
-#include <drivers/st/stm32mp25_rcc.h>
-#ifndef __ASSEMBLER__
#include <drivers/st/stm32mp2_clk.h>
#endif
+#if STM32MP21
+#include <drivers/st/stm32mp21_pwr.h>
+#include <drivers/st/stm32mp21_rcc.h>
+#else /* STM32MP21 */
#include <drivers/st/stm32mp2_pwr.h>
+#include <drivers/st/stm32mp25_rcc.h>
+#endif /* STM32MP21 */
+#if STM32MP21
+#include <dt-bindings/clock/st,stm32mp21-rcc.h>
+#include <dt-bindings/clock/stm32mp21-clksrc.h>
+#include <dt-bindings/reset/st,stm32mp21-rcc.h>
+#endif /* STM32MP21 */
+#if STM32MP23
#include <dt-bindings/clock/stm32mp25-clks.h>
#include <dt-bindings/clock/stm32mp25-clksrc.h>
-#include <dt-bindings/gpio/stm32-gpio.h>
#include <dt-bindings/reset/stm32mp25-resets.h>
+#endif /* STM32MP23 */
+#if STM32MP25
+#include <dt-bindings/clock/stm32mp25-clks.h>
+#include <dt-bindings/clock/stm32mp25-clksrc.h>
+#include <dt-bindings/reset/stm32mp25-resets.h>
+#endif /* STM32MP25 */
+#include <dt-bindings/gpio/stm32-gpio.h>
#ifndef __ASSEMBLER__
#include <boot_api.h>
@@ -386,7 +401,7 @@
#define DDRPHYC_BASE U(0x48C00000)
/*******************************************************************************
- * Miscellaneous STM32MP1 peripherals base address
+ * Miscellaneous STM32MP2 peripherals base address
******************************************************************************/
#define BSEC_BASE U(0x44000000)
#define DBGMCU_BASE U(0x4A010000)
@@ -422,7 +437,11 @@
#define DT_BSEC_COMPAT "st,stm32mp25-bsec"
#define DT_DDR_COMPAT "st,stm32mp2-ddr"
#define DT_PWR_COMPAT "st,stm32mp25-pwr"
+#if STM32MP21
+#define DT_RCC_CLK_COMPAT "st,stm32mp21-rcc"
+#else
#define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc"
+#endif
#define DT_SDMMC2_COMPAT "st,stm32mp25-sdmmc2"
#define DT_UART_COMPAT "st,stm32h7-uart"
diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c
index df49f48..ec37d9f 100644
--- a/plat/ti/k3/common/k3_psci.c
+++ b/plat/ti/k3/common/k3_psci.c
@@ -226,10 +226,24 @@
wfi();
}
-static int k3_validate_power_state(unsigned int power_state,
- psci_power_state_t *req_state)
+static int k3_validate_power_state(unsigned int power_state, psci_power_state_t *req_state)
{
- /* TODO: perform the proper validation */
+ unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
+ unsigned int pstate = psci_get_pstate_type(power_state);
+
+ if (pwr_lvl > PLAT_MAX_PWR_LVL)
+ return PSCI_E_INVALID_PARAMS;
+
+ if (pstate == PSTATE_TYPE_STANDBY) {
+ /*
+ * It's possible to enter standby only on power level 0
+ * Ignore any other power level.
+ */
+ if (pwr_lvl != MPIDR_AFFLVL0)
+ return PSCI_E_INVALID_PARAMS;
+
+ CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE;
+ }
return PSCI_E_SUCCESS;
}
diff --git a/plat/xilinx/common/include/plat_fdt.h b/plat/xilinx/common/include/plat_fdt.h
index 48ffff3..0c2b1df 100644
--- a/plat/xilinx/common/include/plat_fdt.h
+++ b/plat/xilinx/common/include/plat_fdt.h
@@ -11,4 +11,29 @@
uintptr_t plat_retrieve_dt_addr(void);
int32_t is_valid_dtb(void *fdt);
+#define MAX_RESERVE_ADDR_INDICES 32
+struct reserve_mem_range {
+ uintptr_t base;
+ size_t size;
+};
+
+#if (TRANSFER_LIST == 1)
+uint32_t retrieve_reserved_entries(void);
+struct reserve_mem_range *get_reserved_entries_fdt(uint32_t *reserve_nodes);
+#else
+static inline uint32_t retrieve_reserved_entries(void)
+{
+ return 0;
+}
+
+static inline struct reserve_mem_range *get_reserved_entries_fdt(uint32_t *reserve_nodes)
+{
+ if (reserve_nodes) {
+ *reserve_nodes = 0;
+ }
+
+ return NULL;
+}
+#endif
+
#endif /* PLAT_FDT_H */
diff --git a/plat/xilinx/common/include/pm_node.h b/plat/xilinx/common/include/pm_node.h
index 0efebdf..982a410 100644
--- a/plat/xilinx/common/include/pm_node.h
+++ b/plat/xilinx/common/include/pm_node.h
@@ -22,6 +22,7 @@
#define NODE_SUBCLASS_MASK_BITS GENMASK_32(5, 0)
#define NODE_TYPE_MASK_BITS GENMASK_32(5, 0)
#define NODE_INDEX_MASK_BITS GENMASK_32(13, 0)
+#define NODE_CLASS_MASK (NODE_CLASS_MASK_BITS << NODE_CLASS_SHIFT)
#define NODEID(CLASS, SUBCLASS, TYPE, INDEX) \
((((CLASS) & NODE_CLASS_MASK_BITS) << NODE_CLASS_SHIFT) | \
@@ -29,6 +30,8 @@
(((TYPE) & NODE_TYPE_MASK_BITS) << NODE_TYPE_SHIFT) | \
(((INDEX) & NODE_INDEX_MASK_BITS) << NODE_INDEX_SHIFT))
+#define NODECLASS(ID) (((ID) & NODE_CLASS_MASK) >> NODE_CLASS_SHIFT)
+
/*********************************************************************
* Enum definitions
********************************************************************/
diff --git a/plat/xilinx/common/include/pm_svc_main.h b/plat/xilinx/common/include/pm_svc_main.h
index 000f198..32a425c 100644
--- a/plat/xilinx/common/include/pm_svc_main.h
+++ b/plat/xilinx/common/include/pm_svc_main.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,8 +10,6 @@
#include <pm_common.h>
-extern bool pwrdwn_req_received;
-
#define PASS_THROUGH_FW_CMD_ID U(0xfff)
/******************************************************************************/
@@ -34,6 +32,7 @@
status_tmp = function(__VA_ARGS__); \
}
+bool pm_pwrdwn_req_status(void);
void request_cpu_pwrdwn(void);
int32_t pm_setup(void);
uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
diff --git a/plat/xilinx/common/pm_service/pm_svc_main.c b/plat/xilinx/common/pm_service/pm_svc_main.c
index 77ebb62..fd21917 100644
--- a/plat/xilinx/common/pm_service/pm_svc_main.c
+++ b/plat/xilinx/common/pm_service/pm_svc_main.c
@@ -67,7 +67,12 @@
/* pm_up = true - UP, pm_up = false - DOWN */
static bool pm_up;
static uint32_t sgi = (uint32_t)INVALID_SGI;
-bool pwrdwn_req_received;
+static bool pwrdwn_req_received;
+
+bool pm_pwrdwn_req_status(void)
+{
+ return pwrdwn_req_received;
+}
static void notify_os(void)
{
@@ -170,7 +175,8 @@
break;
case PM_NOTIFY_CB:
if (sgi != INVALID_SGI) {
- if (payload[2] == EVENT_CPU_PWRDWN) {
+ if ((payload[2] == EVENT_CPU_PWRDWN) &&
+ (NODECLASS(payload[1]) == (uint32_t)XPM_NODECLASS_DEVICE)) {
if (pwrdwn_req_received) {
pwrdwn_req_received = false;
request_cpu_pwrdwn();
@@ -182,7 +188,8 @@
}
notify_os();
} else {
- if (payload[2] == EVENT_CPU_PWRDWN) {
+ if ((payload[2] == EVENT_CPU_PWRDWN) &&
+ (NODECLASS(payload[1]) == (uint32_t)XPM_NODECLASS_DEVICE)) {
request_cpu_pwrdwn();
(void)psci_cpu_off();
}
@@ -255,6 +262,7 @@
pm_ipi_init(primary_proc);
pm_up = true;
+ pwrdwn_req_received = false;
/* register SGI handler for CPU power down request */
ret = request_intr_type_el3(CPU_PWR_DOWN_REQ_INTR, cpu_pwrdwn_req_handler);
diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c
index 1c365b4..2b1b075 100644
--- a/plat/xilinx/versal/plat_psci.c
+++ b/plat/xilinx/versal/plat_psci.c
@@ -182,7 +182,7 @@
* Send the system reset request to the firmware if power down request
* is not received from firmware.
*/
- if (!pwrdwn_req_received) {
+ if (!pm_pwrdwn_req_status()) {
(void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET,
pm_get_shutdown_scope(), SECURE_FLAG);
diff --git a/plat/xilinx/versal_net/plat_psci_pm.c b/plat/xilinx/versal_net/plat_psci_pm.c
index 6ec8649..6d69d52 100644
--- a/plat/xilinx/versal_net/plat_psci_pm.c
+++ b/plat/xilinx/versal_net/plat_psci_pm.c
@@ -133,7 +133,7 @@
* Send the system reset request to the firmware if power down request
* is not received from firmware.
*/
- if (!pwrdwn_req_received) {
+ if (!pm_pwrdwn_req_status()) {
(void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET,
scope, SECURE_FLAG);
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index b29e1c6..65616e5 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -64,6 +64,26 @@
DISABLE_ALL_EXCEPTIONS);
}
+static inline uint64_t read_cntvct_el0(void)
+{
+ uint64_t val;
+
+ asm volatile("mrs %0, cntvct_el0" : "=r" (val));
+ return val;
+}
+
+static inline void reset_cntvct_el0_to_zero(void)
+{
+ asm volatile(
+ "mrs x0, cntpct_el0\n" /* Read physical counter into x0 */
+ "neg x0, x0\n" /* Negate it: x0 = -x0 */
+ "msr cntvoff_el2, x0\n" /* Write offset to virtual counter */
+ :
+ :
+ : "x0", "memory"
+ );
+}
+
/*
* Perform any BL31 specific platform actions. Here is an opportunity to copy
* parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they
@@ -93,6 +113,10 @@
/* Initialize the platform config for future decision making */
zynqmp_config_setup();
+ INFO("Counter TICK 0x%lx\n", read_cntvct_el0());
+ reset_cntvct_el0_to_zero();
+ INFO("Counter TICK after reset 0x%lx\n", read_cntvct_el0());
+
/*
* Do initial security configuration to allow DRAM/device access. On
* Base ZYNQMP only DRAM security is programmable (via TrustZone), but
diff --git a/services/arm_arch_svc/arm_arch_svc_setup.c b/services/arm_arch_svc/arm_arch_svc_setup.c
index 6051de8..00026eb 100644
--- a/services/arm_arch_svc/arm_arch_svc_setup.c
+++ b/services/arm_arch_svc/arm_arch_svc_setup.c
@@ -17,7 +17,7 @@
static int32_t smccc_version(void)
{
- return MAKE_SMCCC_VERSION(SMCCC_MAJOR_VERSION, SMCCC_MINOR_VERSION);
+ return (int32_t)MAKE_SMCCC_VERSION(SMCCC_MAJOR_VERSION, SMCCC_MINOR_VERSION);
}
static int32_t smccc_arch_features(u_register_t arg1)
@@ -121,17 +121,53 @@
}
}
-/* return soc revision or soc version on success otherwise
- * return invalid parameter */
-static int32_t smccc_arch_id(u_register_t arg1)
+/*
+ * Handles SMCCC_ARCH_SOC_ID smc calls.
+ *
+ * - GET_SOC_REVISION: returns SoC revision (AArch32/AArch64)
+ * - GET_SOC_VERSION: returns SoC version (AArch32/AArch64)
+ * - GET_SOC_NAME: returns SoC name string (AArch64 only)
+ *
+ * Returns invalid parameter for unsupported calls.
+ */
+static uintptr_t smccc_arch_id(u_register_t arg1, void *handle, uint32_t is_smc64)
{
if (arg1 == SMCCC_GET_SOC_REVISION) {
- return plat_get_soc_revision();
+ SMC_RET1(handle, plat_get_soc_revision());
}
if (arg1 == SMCCC_GET_SOC_VERSION) {
- return plat_get_soc_version();
+ SMC_RET1(handle, plat_get_soc_version());
}
- return SMC_ARCH_CALL_INVAL_PARAM;
+#if __aarch64__
+ /* SoC Name is only present for SMC64 invocations */
+ if ((arg1 == SMCCC_GET_SOC_NAME) && is_smc64) {
+ uint64_t arg[SMCCC_SOC_NAME_LEN / 8];
+ int32_t ret;
+ char soc_name[SMCCC_SOC_NAME_LEN];
+
+ (void)memset(soc_name, 0U, SMCCC_SOC_NAME_LEN);
+ ret = plat_get_soc_name(soc_name);
+
+ if (ret == SMC_ARCH_CALL_SUCCESS) {
+ (void)memcpy(arg, soc_name, SMCCC_SOC_NAME_LEN);
+ /*
+ * The SoC name is returned as a null-terminated
+ * ASCII string, split across registers X1 to X17
+ * in little endian order.
+ * Each 64-bit register holds 8 consecutive bytes
+ * of the string.
+ */
+ SMC_RET18(handle, ret, arg[0], arg[1], arg[2],
+ arg[3], arg[4], arg[5], arg[6],
+ arg[7], arg[8], arg[9], arg[10],
+ arg[11], arg[12], arg[13], arg[14],
+ arg[15], arg[16]);
+ } else {
+ SMC_RET1(handle, ret);
+ }
+ }
+#endif /* __aarch64__ */
+ SMC_RET1(handle, SMC_ARCH_CALL_INVAL_PARAM);
}
/*
@@ -237,8 +273,10 @@
case SMCCC_ARCH_FEATURES:
SMC_RET1(handle, smccc_arch_features(x1));
case SMCCC_ARCH_SOC_ID:
- SMC_RET1(handle, smccc_arch_id(x1));
-#ifdef __aarch64__
+ case SMCCC_ARCH_SOC_ID | (SMC_64 << FUNCID_CC_SHIFT):
+ return smccc_arch_id(x1, handle, (smc_fid
+ & (SMC_64 << FUNCID_CC_SHIFT)));
+#if __aarch64__
#if WORKAROUND_CVE_2017_5715
case SMCCC_ARCH_WORKAROUND_1:
/*
@@ -294,7 +332,7 @@
arm_arch_svc,
OEN_ARM_START,
OEN_ARM_END,
- SMC_TYPE_FAST,
+ (uint8_t)SMC_TYPE_FAST,
NULL,
arm_arch_svc_smc_handler
);
diff --git a/services/el3/ven_el3_svc.c b/services/el3/ven_el3_svc.c
index 431bfbf..5117b90 100644
--- a/services/el3/ven_el3_svc.c
+++ b/services/el3/ven_el3_svc.c
@@ -13,6 +13,7 @@
#if PLAT_ARM_ACS_SMC_HANDLER
#include <plat/arm/common/plat_acs_smc_handler.h>
#endif /* PLAT_ARM_ACS_SMC_HANDLER */
+#include <services/spm_mm_svc.h>
#include <services/ven_el3_svc.h>
#include <tools_share/uuid.h>
@@ -91,6 +92,16 @@
case VEN_EL3_SVC_VERSION:
SMC_RET2(handle, VEN_EL3_SVC_VERSION_MAJOR, VEN_EL3_SVC_VERSION_MINOR);
break;
+#if SPM_MM
+ /*
+ * Handle TPM start SMC as mentioned in TCG ACPI specification.
+ */
+ case TPM_START_SMC_32:
+ case TPM_START_SMC_64:
+ return spm_mm_tpm_start_handler(smc_fid, x1, x2, x3, x4, cookie,
+ handle, flags);
+ break;
+#endif
default:
WARN("Unimplemented vendor-specific EL3 Service call: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK);
diff --git a/services/spd/opteed/opteed_main.c b/services/spd/opteed/opteed_main.c
index 8910ec6..adfb298 100644
--- a/services/spd/opteed/opteed_main.c
+++ b/services/spd/opteed/opteed_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,7 +27,9 @@
#include <lib/coreboot.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/optee_utils.h>
-#include <lib/transfer_list.h>
+#if TRANSFER_LIST
+#include <transfer_list.h>
+#endif
#include <lib/xlat_tables/xlat_tables_v2.h>
#if OPTEE_ALLOW_SMC_LOAD
#include <libfdt.h>
@@ -40,7 +42,7 @@
#include "teesmc_opteed.h"
#if OPTEE_ALLOW_SMC_LOAD
-static struct transfer_list_header *bl31_tl;
+static struct transfer_list_header __maybe_unused *bl31_tl;
#endif
/*******************************************************************************
@@ -163,9 +165,9 @@
uint64_t arg1;
uint64_t arg2;
uint64_t arg3;
- struct transfer_list_header *tl = NULL;
- struct transfer_list_entry *te = NULL;
- void *dt = NULL;
+ struct transfer_list_header __maybe_unused *tl = NULL;
+ struct transfer_list_entry __maybe_unused *te = NULL;
+ void __maybe_unused *dt = NULL;
linear_id = plat_my_core_pos();
@@ -190,8 +192,10 @@
if (!optee_ep_info->pc)
return 1;
+#if TRANSFER_LIST
tl = (void *)optee_ep_info->args.arg3;
- if (TRANSFER_LIST && transfer_list_check_header(tl)) {
+
+ if (transfer_list_check_header(tl)) {
te = transfer_list_find(tl, TL_TAG_FDT);
dt = transfer_list_entry_data(te);
@@ -199,7 +203,7 @@
if (opteed_rw == OPTEE_AARCH64) {
if (optee_ep_info->args.arg1 !=
TRANSFER_LIST_HANDOFF_X1_VALUE(
- REGISTER_CONVENTION_VERSION))
+ REGISTER_CONVENTION_VERSION))
return 1;
arg0 = (uint64_t)dt;
@@ -207,7 +211,7 @@
} else {
if (optee_ep_info->args.arg1 !=
TRANSFER_LIST_HANDOFF_R1_VALUE(
- REGISTER_CONVENTION_VERSION))
+ REGISTER_CONVENTION_VERSION))
return 1;
arg0 = 0;
@@ -216,7 +220,10 @@
arg1 = optee_ep_info->args.arg1;
arg3 = optee_ep_info->args.arg3;
- } else {
+
+ } else
+#endif /* TRANSFER_LIST */
+ {
/* Default handoff arguments */
opteed_rw = optee_ep_info->args.arg0;
arg0 = optee_ep_info->args.arg1; /* opteed_pageable_part */
@@ -225,9 +232,9 @@
arg3 = 0;
}
- opteed_init_optee_ep_state(optee_ep_info, opteed_rw, optee_ep_info->pc,
- arg0, arg1, arg2, arg3,
- &opteed_sp_context[linear_id]);
+ opteed_init_optee_ep_state(optee_ep_info, opteed_rw,
+ optee_ep_info->pc, arg0, arg1, arg2,
+ arg3, &opteed_sp_context[linear_id]);
/*
* All OPTEED initialization done. Now register our init function with
@@ -430,9 +437,9 @@
return fdt_finish(fdt_buf);
}
+#if TRANSFER_LIST
static int32_t create_smc_tl(const void *fdt, uint32_t fdt_sz)
{
-#if TRANSFER_LIST
bl31_tl = transfer_list_init((void *)(uintptr_t)FW_HANDOFF_BASE,
FW_HANDOFF_SIZE);
if (!bl31_tl) {
@@ -445,10 +452,8 @@
return -1;
}
return 0;
-#else
- return -1;
-#endif
}
+#endif
/*******************************************************************************
* This function is responsible for handling the SMC that loads the OP-TEE
@@ -546,8 +551,8 @@
dt_addr = (uint64_t)fdt_buf;
flush_dcache_range(dt_addr, OPTEED_FDT_SIZE);
- if (TRANSFER_LIST &&
- !create_smc_tl((void *)dt_addr, OPTEED_FDT_SIZE)) {
+#if TRANSFER_LIST
+ if (!create_smc_tl((void *)dt_addr, OPTEED_FDT_SIZE)) {
struct transfer_list_entry *te = NULL;
void *dt = NULL;
@@ -565,7 +570,9 @@
}
arg3 = (uint64_t)bl31_tl;
- } else {
+ } else
+#endif /* TRANSFER_LIST */
+ {
/* Default handoff arguments */
arg2 = dt_addr;
}
diff --git a/services/spd/opteed/opteed_pm.c b/services/spd/opteed/opteed_pm.c
index c949823..c4a79f5 100644
--- a/services/spd/opteed/opteed_pm.c
+++ b/services/spd/opteed/opteed_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -137,12 +137,15 @@
* completed the preceding suspend call. Use that context to program an entry
* into OPTEE to allow it to do any remaining book keeping
******************************************************************************/
-static void opteed_cpu_suspend_finish_handler(u_register_t max_off_pwrlvl)
+static void opteed_cpu_suspend_finish_handler(u_register_t max_off_pwrlvl, bool abandon)
{
int32_t rc = 0;
uint32_t linear_id = plat_my_core_pos();
optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
+ /* opteed is not expected to be used on platforms with pabandon */
+ assert(!abandon);
+
if (get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_UNKNOWN) {
return;
}
diff --git a/services/spd/tlkd/tlkd_pm.c b/services/spd/tlkd/tlkd_pm.c
index ed5bf77..ed66245 100644
--- a/services/spd/tlkd/tlkd_pm.c
+++ b/services/spd/tlkd/tlkd_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -69,12 +69,15 @@
* This cpu is being resumed. Inform TLK of the SYSTEM_SUSPEND exit, so
* that it can pass this information to its Trusted Apps.
******************************************************************************/
-static void cpu_resume_handler(u_register_t suspend_level)
+static void cpu_resume_handler(u_register_t suspend_level, bool abandon)
{
gp_regs_t *gp_regs;
int cpu = read_mpidr() & MPIDR_CPU_MASK;
int32_t rc = 0;
+ /* tlkd is not expected to be used on platforms with pabandon */
+ assert(!abandon);
+
/*
* TLK runs only on CPU0 and resumes its Trusted Apps during
* SYSTEM_SUSPEND exit. It has no role to play during CPU_SUSPEND
diff --git a/services/spd/trusty/trusty.c b/services/spd/trusty/trusty.c
index aae2d9a..4b44798 100644
--- a/services/spd/trusty/trusty.c
+++ b/services/spd/trusty/trusty.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -397,12 +397,21 @@
static void trusty_cpu_suspend_handler(u_register_t max_off_lvl)
{
+ /* Save NS context in case we need to return to it */
+ cm_el1_sysregs_context_save(NON_SECURE);
+
trusty_cpu_suspend(max_off_lvl);
}
-static void trusty_cpu_suspend_finish_handler(u_register_t max_off_lvl)
+static void trusty_cpu_suspend_finish_handler(u_register_t max_off_lvl, bool abandon)
{
trusty_cpu_resume(max_off_lvl);
+
+ /* We're returning back to NS so we need to put back its context */
+ if (abandon) {
+ cm_el1_sysregs_context_restore(NON_SECURE);
+ }
+
}
static const spd_pm_ops_t trusty_pm = {
diff --git a/services/spd/tspd/tspd_pm.c b/services/spd/tspd/tspd_pm.c
index b95ee8f..d44a807 100644
--- a/services/spd/tspd/tspd_pm.c
+++ b/services/spd/tspd/tspd_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -83,6 +83,10 @@
/* Program the entry point and enter the TSP */
cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_suspend_entry);
+
+ /* Save NS context in case we need to return to it */
+ cm_el1_sysregs_context_save(NON_SECURE);
+
rc = tspd_synchronous_sp_entry(tsp_ctx);
/*
@@ -147,7 +151,7 @@
* completed the preceding suspend call. Use that context to program an entry
* into the TSP to allow it to do any remaining book keeping
******************************************************************************/
-static void tspd_cpu_suspend_finish_handler(u_register_t max_off_pwrlvl)
+static void tspd_cpu_suspend_finish_handler(u_register_t max_off_pwrlvl, bool abandon)
{
int32_t rc = 0;
uint32_t linear_id = plat_my_core_pos();
@@ -170,6 +174,11 @@
if (rc != 0)
panic();
+ /* We're returning back to NS so we need to put back its context */
+ if (abandon) {
+ cm_el1_sysregs_context_restore(NON_SECURE);
+ }
+
/* Update its context to reflect the state the SP is in */
set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON);
}
diff --git a/services/std_svc/drtm/drtm_dma_prot.h b/services/std_svc/drtm/drtm_dma_prot.h
index 79dc9cb..5ccff87 100644
--- a/services/std_svc/drtm/drtm_dma_prot.h
+++ b/services/std_svc/drtm/drtm_dma_prot.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -20,7 +20,7 @@
enum dma_prot_type {
PROTECT_NONE = -1,
PROTECT_MEM_ALL = 0,
- PROTECT_MEM_REGION = 2,
+ PROTECT_MEM_REGION = 1,
};
struct dma_prot {
diff --git a/services/std_svc/drtm/drtm_measurements.c b/services/std_svc/drtm/drtm_measurements.c
index 7214e23..4518d37 100644
--- a/services/std_svc/drtm/drtm_measurements.c
+++ b/services/std_svc/drtm/drtm_measurements.c
@@ -138,7 +138,8 @@
/* PCR-17: End of DCE measurements. */
rc = drtm_event_log_measure_and_record((uintptr_t)drtm_event_arm_sep_data,
strlen(drtm_event_arm_sep_data),
- DRTM_EVENT_ARM_SEPARATOR, NULL,
+ DRTM_EVENT_ARM_SEPARATOR,
+ drtm_event_arm_sep_data,
PCR_17);
CHECK_RC(rc, drtm_event_log_measure_and_record(DRTM_EVENT_ARM_SEPARATOR));
@@ -188,7 +189,7 @@
/* PCR-18: Measure the DLME image entry point. */
dlme_img_ep = DL_ARGS_GET_DLME_ENTRY_POINT(a);
- drtm_event_log_measure_and_record((uintptr_t)&dlme_img_ep,
+ drtm_event_log_measure_and_record((uintptr_t)&(a->dlme_img_ep_off),
sizeof(dlme_img_ep),
DRTM_EVENT_ARM_DLME_EP, NULL,
PCR_18);
@@ -197,7 +198,8 @@
/* PCR-18: End of DCE measurements. */
rc = drtm_event_log_measure_and_record((uintptr_t)drtm_event_arm_sep_data,
strlen(drtm_event_arm_sep_data),
- DRTM_EVENT_ARM_SEPARATOR, NULL,
+ DRTM_EVENT_ARM_SEPARATOR,
+ drtm_event_arm_sep_data,
PCR_18);
CHECK_RC(rc,
drtm_event_log_measure_and_record(DRTM_EVENT_ARM_SEPARATOR));
diff --git a/services/std_svc/lfa/bl31_lfa.c b/services/std_svc/lfa/bl31_lfa.c
new file mode 100644
index 0000000..6f66826
--- /dev/null
+++ b/services/std_svc/lfa/bl31_lfa.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <services/bl31_lfa.h>
+#include <services/lfa_svc.h>
+
+static int32_t lfa_bl31_prime(struct lfa_component_status *activation)
+{
+ return LFA_WRONG_STATE;
+}
+
+static int32_t lfa_bl31_activate(struct lfa_component_status *activation,
+ uint64_t ep_address,
+ uint64_t context_id)
+{
+ return LFA_WRONG_STATE;
+}
+
+static struct lfa_component_ops bl31_activator = {
+ .prime = lfa_bl31_prime,
+ .activate = lfa_bl31_activate,
+ .may_reset_cpu = false,
+ .cpu_rendezvous_required = true,
+};
+
+struct lfa_component_ops *get_bl31_activator(void)
+{
+ return &bl31_activator;
+}
diff --git a/services/std_svc/lfa/lfa.mk b/services/std_svc/lfa/lfa.mk
new file mode 100644
index 0000000..056b537
--- /dev/null
+++ b/services/std_svc/lfa/lfa.mk
@@ -0,0 +1,14 @@
+#
+# Copyright (c) 2025, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LFA_SOURCES += $(addprefix services/std_svc/lfa/, \
+ lfa_main.c \
+ bl31_lfa.c \
+ lfa_holding_pen.c)
+
+ifeq (${ENABLE_RME}, 1)
+LFA_SOURCES += services/std_svc/rmmd/rmmd_rmm_lfa.c
+endif
diff --git a/services/std_svc/lfa/lfa_holding_pen.c b/services/std_svc/lfa/lfa_holding_pen.c
new file mode 100644
index 0000000..8ee260c
--- /dev/null
+++ b/services/std_svc/lfa/lfa_holding_pen.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <common/debug.h>
+#include <lib/psci/psci_lib.h>
+#include <lib/spinlock.h>
+#include <lib/utils_def.h>
+#include <plat/common/platform.h>
+#include <services/lfa_holding_pen.h>
+
+#include <platform_def.h>
+
+static spinlock_t holding_lock;
+static spinlock_t activation_lock;
+static uint32_t activation_count;
+static enum lfa_retc activation_status;
+
+/**
+ * lfa_holding_start - Called by each active CPU to coordinate live activation.
+ *
+ * Note that only CPUs that are active at the time of activation will
+ * participate in CPU rendezvous.
+ *
+ * This function is invoked by each CPU participating in the LFA Activate
+ * process. It increments the shared activation count under `activation_lock`
+ * to track how many CPUs have entered the activation phase.
+ *
+ * The first CPU to enter acquires the `holding_lock`, which ensures
+ * serialization during the wait and activation phases. This lock is
+ * released only after the last CPU completes the activation.
+ *
+ * The function returns `true` only for the last CPU to enter, allowing it
+ * to proceed with performing the live firmware activation. All other CPUs
+ * receive `false` and will wait in `lfa_holding_wait()` until activation
+ * is complete.
+ *
+ * @return `true` for the last CPU, `false` for all others.
+ */
+bool lfa_holding_start(void)
+{
+ bool status;
+ unsigned int no_of_cpus;
+
+ spin_lock(&activation_lock);
+
+ if (activation_count == 0U) {
+ /* First CPU locks holding lock */
+ spin_lock(&holding_lock);
+ }
+
+ activation_count += 1U;
+
+ no_of_cpus = psci_num_cpus_running_on_safe(plat_my_core_pos());
+ status = (activation_count == no_of_cpus);
+ if (!status) {
+ VERBOSE("Hold, %d CPU left\n",
+ PLATFORM_CORE_COUNT - activation_count);
+ }
+
+ spin_unlock(&activation_lock);
+
+ return status;
+}
+
+/**
+ * lfa_holding_wait - CPUs wait until activation is completed by the last CPU.
+ *
+ * All CPUs are serialized using `holding_lock`, which is initially acquired
+ * by the first CPU in `lfa_holding_start()` and only released by the last
+ * CPU through `lfa_holding_release()`. This ensures that no two CPUs enter
+ * the critical section at the same time during the wait phase. Once the
+ * last CPU completes activation, each CPU decrements the activation count
+ * and returns the final activation status, which was set by the last CPU
+ * to complete the activation process.
+ *
+ * @return Activation status set by the last CPU.
+ */
+enum lfa_retc lfa_holding_wait(void)
+{
+ spin_lock(&holding_lock);
+ activation_count -= 1U;
+ spin_unlock(&holding_lock);
+ return activation_status;
+}
+
+/**
+ * lfa_holding_release - Called by the last CPU to complete activation.
+ *
+ * This function is used by the last participating CPU after it completes
+ * live firmware activation. It updates the shared activation status and
+ * resets the activation count. Finally, it releases the `holding_lock` to
+ * allow other CPUs that were waiting in `lfa_holding_wait()` to proceed.
+ *
+ * @param status Activation status to be shared with other CPUs.
+ */
+void lfa_holding_release(enum lfa_retc status)
+{
+ activation_count = 0U;
+ activation_status = status;
+ spin_unlock(&holding_lock);
+}
diff --git a/services/std_svc/lfa/lfa_main.c b/services/std_svc/lfa/lfa_main.c
new file mode 100644
index 0000000..1cf65ae
--- /dev/null
+++ b/services/std_svc/lfa/lfa_main.c
@@ -0,0 +1,337 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <plat/common/platform.h>
+#include <services/bl31_lfa.h>
+#include <services/lfa_svc.h>
+#include <services/rmmd_rmm_lfa.h>
+#include <smccc_helpers.h>
+
+static uint32_t lfa_component_count;
+static plat_lfa_component_info_t *lfa_components;
+static struct lfa_component_status current_activation;
+static bool is_lfa_initialized;
+
+void lfa_reset_activation(void)
+{
+ current_activation.component_id = LFA_INVALID_COMPONENT;
+ current_activation.prime_status = PRIME_NONE;
+ current_activation.cpu_rendezvous_required = false;
+}
+
+static int convert_to_lfa_error(int ret)
+{
+ switch (ret) {
+ case 0:
+ return LFA_SUCCESS;
+ case -EAUTH:
+ return LFA_AUTH_ERROR;
+ case -ENOMEM:
+ return LFA_NO_MEMORY;
+ default:
+ return LFA_DEVICE_ERROR;
+ }
+}
+
+static bool lfa_initialize_components(void)
+{
+ lfa_component_count = plat_lfa_get_components(&lfa_components);
+
+ if (lfa_component_count == 0U || lfa_components == NULL) {
+ /* unlikely to reach here */
+ ERROR("Invalid LFA component setup: count = 0 or components are NULL");
+ return false;
+ }
+
+ return true;
+}
+
+static uint64_t get_fw_activation_flags(uint32_t fw_seq_id)
+{
+ const plat_lfa_component_info_t *comp =
+ &lfa_components[fw_seq_id];
+ uint64_t flags = 0ULL;
+
+ flags |= ((comp->activator == NULL ? 0ULL : 1ULL)
+ << LFA_ACTIVATION_CAPABLE_SHIFT);
+ flags |= (uint64_t)(comp->activation_pending)
+ << LFA_ACTIVATION_PENDING_SHIFT;
+
+ if (comp->activator != NULL) {
+ flags |= ((comp->activator->may_reset_cpu ? 1ULL : 0ULL)
+ << LFA_MAY_RESET_CPU_SHIFT);
+ flags |= ((comp->activator->cpu_rendezvous_required ? 0ULL : 1ULL)
+ << LFA_CPU_RENDEZVOUS_OPTIONAL_SHIFT);
+ }
+
+ return flags;
+}
+
+static int lfa_cancel(uint32_t component_id)
+{
+ int ret = LFA_SUCCESS;
+
+ if (lfa_component_count == 0U) {
+ return LFA_WRONG_STATE;
+ }
+
+ /* Check if component ID is in range. */
+ if ((component_id >= lfa_component_count) ||
+ (component_id != current_activation.component_id)) {
+ return LFA_INVALID_PARAMETERS;
+ }
+
+ ret = plat_lfa_cancel(component_id);
+ if (ret != LFA_SUCCESS) {
+ return LFA_BUSY;
+ }
+
+ /* TODO: add proper termination prime and activate phases */
+ lfa_reset_activation();
+
+ return ret;
+}
+
+static int lfa_activate(uint32_t component_id, uint64_t flags,
+ uint64_t ep_address, uint64_t context_id)
+{
+ int ret = LFA_ACTIVATION_FAILED;
+ struct lfa_component_ops *activator;
+
+ if ((lfa_component_count == 0U) ||
+ (!lfa_components[component_id].activation_pending) ||
+ (current_activation.prime_status != PRIME_COMPLETE)) {
+ return LFA_COMPONENT_WRONG_STATE;
+ }
+
+ /* Check if fw_seq_id is in range. */
+ if ((component_id >= lfa_component_count) ||
+ (current_activation.component_id != component_id)) {
+ return LFA_INVALID_PARAMETERS;
+ }
+
+ if (lfa_components[component_id].activator == NULL) {
+ return LFA_NOT_SUPPORTED;
+ }
+
+ activator = lfa_components[component_id].activator;
+ if (activator->activate != NULL) {
+ /*
+ * Pass skip_cpu_rendezvous (flag[0]) only if flag[0]==1
+ * & CPU_RENDEZVOUS is not required.
+ */
+ if (flags & LFA_SKIP_CPU_RENDEZVOUS_BIT) {
+ if (!activator->cpu_rendezvous_required) {
+ INFO("Skipping rendezvous requested by caller.\n");
+ current_activation.cpu_rendezvous_required = false;
+ }
+ /*
+ * Return error if caller tries to skip rendezvous when
+ * it is required.
+ */
+ else {
+ ERROR("CPU Rendezvous is required, can't skip.\n");
+ return LFA_INVALID_PARAMETERS;
+ }
+ }
+
+ ret = activator->activate(¤t_activation, ep_address,
+ context_id);
+ }
+
+ lfa_components[component_id].activation_pending = false;
+
+ return ret;
+}
+
+static int lfa_prime(uint32_t component_id, uint64_t *flags)
+{
+ int ret = LFA_SUCCESS;
+ struct lfa_component_ops *activator;
+
+ if (lfa_component_count == 0U ||
+ !lfa_components[component_id].activation_pending) {
+ return LFA_WRONG_STATE;
+ }
+
+ /* Check if fw_seq_id is in range. */
+ if (component_id >= lfa_component_count) {
+ return LFA_INVALID_PARAMETERS;
+ }
+
+ if (lfa_components[component_id].activator == NULL) {
+ return LFA_NOT_SUPPORTED;
+ }
+
+ switch (current_activation.prime_status) {
+ case PRIME_NONE:
+ current_activation.component_id = component_id;
+ current_activation.prime_status = PRIME_STARTED;
+ break;
+
+ case PRIME_STARTED:
+ if (current_activation.component_id != component_id) {
+ /* Mismatched component trying to continue PRIME - error */
+ return LFA_WRONG_STATE;
+ }
+ break;
+
+ case PRIME_COMPLETE:
+ default:
+ break;
+ }
+
+ ret = plat_lfa_load_auth_image(component_id);
+ ret = convert_to_lfa_error(ret);
+
+ activator = lfa_components[component_id].activator;
+ if (activator->prime != NULL) {
+ ret = activator->prime(¤t_activation);
+ if (ret != LFA_SUCCESS) {
+ /*
+ * TODO: it should be LFA_PRIME_FAILED but specification
+ * has not define this error yet
+ */
+ return ret;
+ }
+ }
+
+ current_activation.prime_status = PRIME_COMPLETE;
+
+ /* TODO: split this into multiple PRIME calls */
+ *flags = 0ULL;
+
+ return ret;
+}
+
+int lfa_setup(void)
+{
+ is_lfa_initialized = lfa_initialize_components();
+ if (!is_lfa_initialized) {
+ return -1;
+ }
+
+ lfa_reset_activation();
+
+ return 0;
+}
+
+uint64_t lfa_smc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
+ u_register_t x3, u_register_t x4, void *cookie,
+ void *handle, u_register_t flags)
+{
+ uint64_t retx1, retx2;
+ uint64_t lfa_flags;
+ uint8_t *uuid_p;
+ uint32_t fw_seq_id = (uint32_t)x1;
+ int ret;
+
+ /**
+ * TODO: Acquire serialization lock.
+ */
+
+ if (!is_lfa_initialized) {
+ return LFA_NOT_SUPPORTED;
+ }
+
+ switch (smc_fid) {
+ case LFA_VERSION:
+ SMC_RET1(handle, LFA_VERSION_VAL);
+ break;
+
+ case LFA_FEATURES:
+ SMC_RET1(handle, is_lfa_fid(x1) ? LFA_SUCCESS : LFA_NOT_SUPPORTED);
+ break;
+
+ case LFA_GET_INFO:
+ /**
+ * The current specification limits this input parameter to be zero for
+ * version 1.0 of LFA
+ */
+ if (x1 == 0ULL) {
+ SMC_RET3(handle, LFA_SUCCESS, lfa_component_count, 0);
+ } else {
+ SMC_RET1(handle, LFA_INVALID_PARAMETERS);
+ }
+ break;
+
+ case LFA_GET_INVENTORY:
+ if (lfa_component_count == 0U) {
+ SMC_RET1(handle, LFA_WRONG_STATE);
+ }
+
+ /*
+ * Check if fw_seq_id is in range. LFA_GET_INFO must be called first to scan
+ * platform firmware and create a valid number of firmware components.
+ */
+ if (fw_seq_id >= lfa_component_count) {
+ SMC_RET1(handle, LFA_INVALID_PARAMETERS);
+ }
+
+ /*
+ * grab the UUID of asked fw_seq_id and set the return UUID
+ * variables
+ */
+ uuid_p = (uint8_t *)&lfa_components[fw_seq_id].uuid;
+ memcpy(&retx1, uuid_p, sizeof(uint64_t));
+ memcpy(&retx2, uuid_p + sizeof(uint64_t), sizeof(uint64_t));
+
+ /*
+ * check the given fw_seq_id's update available
+ * and accordingly set the active_pending flag
+ */
+ lfa_components[fw_seq_id].activation_pending =
+ is_plat_lfa_activation_pending(fw_seq_id);
+
+ INFO("Component %lu %s live activation:\n", x1,
+ lfa_components[fw_seq_id].activator ? "supports" :
+ "does not support");
+
+ if (lfa_components[fw_seq_id].activator != NULL) {
+ INFO("Activation pending: %s\n",
+ lfa_components[fw_seq_id].activation_pending ? "true" : "false");
+ }
+
+ INFO("x1 = 0x%016lx, x2 = 0x%016lx\n", retx1, retx2);
+
+ SMC_RET4(handle, LFA_SUCCESS, retx1, retx2, get_fw_activation_flags(fw_seq_id));
+
+ break;
+
+ case LFA_PRIME:
+ ret = lfa_prime(x1, &lfa_flags);
+ if (ret != LFA_SUCCESS) {
+ SMC_RET1(handle, ret);
+ } else {
+ SMC_RET2(handle, ret, lfa_flags);
+ }
+ break;
+
+ case LFA_ACTIVATE:
+ ret = lfa_activate(fw_seq_id, x2, x3, x4);
+ /* TODO: implement activate again */
+ SMC_RET2(handle, ret, 0ULL);
+
+ break;
+
+ case LFA_CANCEL:
+ ret = lfa_cancel(x1);
+ SMC_RET1(handle, ret);
+ break;
+
+ default:
+ WARN("Unimplemented LFA Service Call: 0x%x\n", smc_fid);
+ SMC_RET1(handle, SMC_UNK);
+ break; /* unreachable */
+
+ }
+
+ SMC_RET1(handle, SMC_UNK);
+
+ return 0;
+}
diff --git a/services/std_svc/rmmd/rmmd_initial_context.h b/services/std_svc/rmmd/rmmd_initial_context.h
deleted file mode 100644
index d7a743d..0000000
--- a/services/std_svc/rmmd/rmmd_initial_context.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef RMMD_INITIAL_CONTEXT_H
-#define RMMD_INITIAL_CONTEXT_H
-
-#include <arch.h>
-
-/*
- * SPSR_EL2
- * M=0x9 (0b1001 EL2h)
- * M[4]=0
- * DAIF=0xF Exceptions masked on entry.
- * BTYPE=0 BTI not yet supported.
- * SSBS=0 Not yet supported.
- * IL=0 Not an illegal exception return.
- * SS=0 Not single stepping.
- * PAN=1 RMM shouldn't access realm memory.
- * UAO=0
- * DIT=0
- * TCO=0
- * NZCV=0
- */
-#define REALM_SPSR_EL2 ( \
- SPSR_M_EL2H | \
- (0xF << SPSR_DAIF_SHIFT) | \
- SPSR_PAN_BIT \
- )
-
-#endif /* RMMD_INITIAL_CONTEXT_H */
diff --git a/services/std_svc/rmmd/rmmd_main.c b/services/std_svc/rmmd/rmmd_main.c
index 35582dc..fd40f0f 100644
--- a/services/std_svc/rmmd/rmmd_main.c
+++ b/services/std_svc/rmmd/rmmd_main.c
@@ -36,7 +36,6 @@
#include <lib/extensions/sve.h>
#include <lib/extensions/spe.h>
#include <lib/extensions/trbe.h>
-#include "rmmd_initial_context.h"
#include "rmmd_private.h"
/*******************************************************************************
@@ -110,78 +109,6 @@
panic();
}
-static void rmm_el2_context_init(el2_sysregs_t *regs)
-{
- write_el2_ctx_common(regs, spsr_el2, REALM_SPSR_EL2);
- write_el2_ctx_common(regs, sctlr_el2, SCTLR_EL2_RES1);
-}
-
-/*******************************************************************************
- * Enable architecture extensions on first entry to Realm world.
- ******************************************************************************/
-
-static void manage_extensions_realm(cpu_context_t *ctx)
-{
- /*
- * Enable access to TPIDR2_EL0 if SME/SME2 is enabled for Non Secure world.
- */
- if (is_feat_sme_supported()) {
- sme_enable(ctx);
- }
-
- /*
- * SPE and TRBE cannot be fully disabled from EL3 registers alone, only
- * sysreg access can. In case the EL1 controls leave them active on
- * context switch, we want the owning security state to be NS so Realm
- * can't be DOSed.
- */
- if (is_feat_spe_supported()) {
- spe_disable(ctx);
- }
-
- if (is_feat_trbe_supported()) {
- trbe_disable(ctx);
- }
-}
-
-static void manage_extensions_realm_per_world(void)
-{
- cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_REALM]);
-
- if (is_feat_sve_supported()) {
- /*
- * Enable SVE and FPU in realm context when it is enabled for NS.
- * Realm manager must ensure that the SVE and FPU register
- * contexts are properly managed.
- */
- sve_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
- }
-
- /* NS can access this but Realm shouldn't */
- if (is_feat_sys_reg_trace_supported()) {
- sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
- }
-
- /*
- * If SME/SME2 is supported and enabled for NS world, then disable trapping
- * of SME instructions for Realm world. RMM will save/restore required
- * registers that are shared with SVE/FPU so that Realm can use FPU or SVE.
- */
- if (is_feat_sme_supported()) {
- sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
- }
-
- /*
- * If FEAT_MPAM is supported and enabled, then disable trapping access
- * to the MPAM registers for Realm world. Instead, RMM will configure
- * the access to be trapped by itself so it can inject undefined aborts
- * back to the Realm.
- */
- if (is_feat_mpam_supported()) {
- mpam_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
- }
-}
-
/*******************************************************************************
* Jump to the RMM for the first time.
******************************************************************************/
@@ -192,14 +119,6 @@
INFO("RMM init start.\n");
- /* Enable architecture extensions */
- manage_extensions_realm(&ctx->cpu_ctx);
-
- manage_extensions_realm_per_world();
-
- /* Initialize RMM EL2 context. */
- rmm_el2_context_init(&ctx->cpu_ctx.el2_sysregs_ctx);
-
rc = rmmd_rmm_sync_entry(ctx);
if (rc != E_RMM_BOOT_SUCCESS) {
ERROR("RMM init failed: %ld\n", rc);
@@ -424,12 +343,6 @@
/* Initialise RMM context with this entry point information */
cm_setup_context(&ctx->cpu_ctx, rmm_ep_info);
- /* Enable architecture extensions */
- manage_extensions_realm(&ctx->cpu_ctx);
-
- /* Initialize RMM EL2 context. */
- rmm_el2_context_init(&ctx->cpu_ctx.el2_sysregs_ctx);
-
rc = rmmd_rmm_sync_entry(ctx);
if (rc != E_RMM_BOOT_SUCCESS) {
diff --git a/services/std_svc/rmmd/rmmd_rmm_lfa.c b/services/std_svc/rmmd/rmmd_rmm_lfa.c
new file mode 100644
index 0000000..966266b
--- /dev/null
+++ b/services/std_svc/rmmd/rmmd_rmm_lfa.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <services/lfa_svc.h>
+#include <services/rmmd_rmm_lfa.h>
+
+static int32_t lfa_rmm_prime(struct lfa_component_status *activation)
+{
+ return LFA_WRONG_STATE;
+}
+
+static int32_t lfa_rmm_activate(struct lfa_component_status *activation,
+ uint64_t ep_address, uint64_t context_id)
+{
+ return LFA_WRONG_STATE;
+}
+
+static struct lfa_component_ops rmm_activator = {
+ .prime = lfa_rmm_prime,
+ .activate = lfa_rmm_activate,
+ .may_reset_cpu = false,
+ .cpu_rendezvous_required = true,
+};
+
+struct lfa_component_ops *get_rmm_activator(void)
+{
+ return &rmm_activator;
+}
diff --git a/services/std_svc/sdei/sdei_event.c b/services/std_svc/sdei/sdei_event.c
index cc8f557..9c7f74a 100644
--- a/services/std_svc/sdei/sdei_event.c
+++ b/services/std_svc/sdei/sdei_event.c
@@ -61,11 +61,13 @@
* Both shared and private maps are stored in single-dimensional array. Private
* event entries are kept for each PE forming a 2D array.
*/
-sdei_entry_t *get_event_entry_target_pe(long int mapsub, unsigned int nm, uint64_t target_pe)
+sdei_entry_t *get_event_entry_target_pe(long int mapsub, unsigned int nm,
+uint64_t target_pe)
{
sdei_entry_t *cpu_priv_base;
- unsigned int base_idx;
+ unsigned int base_idx = 0U;
long int idx;
+ int target_pos;
/*
* For a private map, find the index of the mapping in the
@@ -74,9 +76,17 @@
idx = mapsub;
/* Base of private mappings for this CPU */
- base_idx = (unsigned int) plat_core_pos_by_mpidr(target_pe);
+ target_pos = plat_core_pos_by_mpidr(target_pe);
+
+ if ((target_pos < 0) || ((unsigned int)target_pos >= PLATFORM_CORE_COUNT)) {
+ return NULL;
+ }
+
+ base_idx = (unsigned int) target_pos;
base_idx *= nm;
+
cpu_priv_base = &sdei_private_event_table[base_idx];
+
/*
* Return the address of the entry at the same index in the
* per-CPU event entry.
diff --git a/services/std_svc/sdei/sdei_intr_mgmt.c b/services/std_svc/sdei/sdei_intr_mgmt.c
index 4854b2e..40c3c24 100644
--- a/services/std_svc/sdei/sdei_intr_mgmt.c
+++ b/services/std_svc/sdei/sdei_intr_mgmt.c
@@ -61,9 +61,12 @@
bool sdei_is_target_pe_masked(uint64_t target_pe)
{
- const sdei_cpu_state_t *state = sdei_get_target_pe_state(target_pe);
-
- return state->pe_masked;
+ int errstat = plat_core_pos_by_mpidr(target_pe);
+ if (errstat >= 0) {
+ const sdei_cpu_state_t *state = &cpu_state[errstat];
+ return state->pe_masked;
+ }
+ return true;
}
int64_t sdei_pe_mask(void)
diff --git a/services/std_svc/sdei/sdei_main.c b/services/std_svc/sdei/sdei_main.c
index bbc9f73..52c01e8 100644
--- a/services/std_svc/sdei/sdei_main.c
+++ b/services/std_svc/sdei/sdei_main.c
@@ -948,6 +948,9 @@
if (map_priv->ev_num == SDEI_EVENT_0) {
se = get_event_entry_target_pe((long int) i,
(unsigned int) SDEI_PRIVATE_MAPPING()->num_maps, target_pe);
+ if (se == NULL) {
+ return SDEI_EINVAL;
+ }
if (!(GET_EV_STATE((se), REGISTERED))) {
return SDEI_EINVAL;
}
diff --git a/services/std_svc/spm/el3_spmc/spmc_main.c b/services/std_svc/spm/el3_spmc/spmc_main.c
index c67a6fc..5c4bd49 100644
--- a/services/std_svc/spm/el3_spmc/spmc_main.c
+++ b/services/std_svc/spm/el3_spmc/spmc_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2024, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2025, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -217,12 +217,13 @@
void *handle,
void *cookie,
uint64_t flags,
- uint16_t dst_id)
+ uint16_t dst_id,
+ uint32_t sp_ffa_version)
{
/* If the destination is in the normal world always go via the SPMD. */
if (ffa_is_normal_world_id(dst_id)) {
return spmd_smc_handler(smc_fid, x1, x2, x3, x4,
- cookie, handle, flags);
+ cookie, handle, flags, sp_ffa_version);
}
/*
* If the caller is secure and we want to return to the secure world,
@@ -234,7 +235,7 @@
/* If we originated in the normal world then switch contexts. */
else if (!secure_origin && ffa_is_secure_world_id(dst_id)) {
return spmd_smc_switch_state(smc_fid, secure_origin, x1, x2,
- x3, x4, handle, flags);
+ x3, x4, handle, flags, sp_ffa_version);
} else {
/* Unknown State. */
panic();
@@ -348,6 +349,18 @@
}
/*******************************************************************************
+ * Helper function to obtain the FF-A version of the calling partition.
+ ******************************************************************************/
+uint32_t get_partition_ffa_version(bool secure_origin)
+{
+ if (secure_origin) {
+ return spmc_get_current_sp_ctx()->ffa_version;
+ } else {
+ return spmc_get_hyp_ctx()->ffa_version;
+ }
+}
+
+/*******************************************************************************
* Handle direct request messages and route to the appropriate destination.
******************************************************************************/
static uint64_t direct_req_smc_handler(uint32_t smc_fid,
@@ -366,10 +379,16 @@
struct el3_lp_desc *el3_lp_descs;
struct secure_partition_desc *sp;
unsigned int idx;
+ uint32_t ffa_version = get_partition_ffa_version(secure_origin);
dir_req_funcid = (smc_fid != FFA_MSG_SEND_DIRECT_REQ2_SMC64) ?
FFA_FNUM_MSG_SEND_DIRECT_REQ : FFA_FNUM_MSG_SEND_DIRECT_REQ2;
+ if ((dir_req_funcid == FFA_FNUM_MSG_SEND_DIRECT_REQ2) &&
+ ffa_version < MAKE_FFA_VERSION(U(1), U(2))) {
+ return spmc_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED);
+ }
+
/*
* Sanity check for DIRECT_REQ:
* Check if arg2 has been populated correctly based on message type
@@ -469,7 +488,7 @@
}
return spmc_smc_return(smc_fid, secure_origin, x1, x2, x3, x4,
- handle, cookie, flags, dst_id);
+ handle, cookie, flags, dst_id, sp->ffa_version);
}
/*******************************************************************************
@@ -586,7 +605,7 @@
}
return spmc_smc_return(smc_fid, secure_origin, x1, x2, x3, x4,
- handle, cookie, flags, dst_id);
+ handle, cookie, flags, dst_id, sp->ffa_version);
}
/*******************************************************************************
@@ -666,7 +685,7 @@
return spmd_smc_switch_state(FFA_NORMAL_WORLD_RESUME, secure_origin,
FFA_PARAM_MBZ, FFA_PARAM_MBZ,
FFA_PARAM_MBZ, FFA_PARAM_MBZ,
- handle, flags);
+ handle, flags, sp->ffa_version);
}
/* Protect the runtime state of a S-EL0 SP with a lock. */
@@ -676,7 +695,7 @@
/* Forward the response to the Normal world. */
return spmc_smc_return(smc_fid, secure_origin, x1, x2, x3, x4,
- handle, cookie, flags, FFA_NWD_ID);
+ handle, cookie, flags, FFA_NWD_ID, sp->ffa_version);
}
static uint64_t ffa_error_handler(uint32_t smc_fid,
@@ -743,7 +762,7 @@
panic();
} else
return spmc_smc_return(smc_fid, secure_origin, x1, x2, x3, x4,
- handle, cookie, flags, dst_id);
+ handle, cookie, flags, dst_id, sp->ffa_version);
}
return spmc_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED);
@@ -790,18 +809,6 @@
FFA_VERSION_MINOR));
}
-/*******************************************************************************
- * Helper function to obtain the FF-A version of the calling partition.
- ******************************************************************************/
-uint32_t get_partition_ffa_version(bool secure_origin)
-{
- if (secure_origin) {
- return spmc_get_current_sp_ctx()->ffa_version;
- } else {
- return spmc_get_hyp_ctx()->ffa_version;
- }
-}
-
static uint64_t rxtx_map_handler(uint32_t smc_fid,
bool secure_origin,
uint64_t x1,
@@ -1534,7 +1541,7 @@
}
return spmc_smc_return(smc_fid, secure_origin, x1, 0, 0, 0,
- handle, cookie, flags, target_id);
+ handle, cookie, flags, target_id, sp->ffa_version);
}
static uint64_t rx_release_handler(uint32_t smc_fid,
@@ -1884,7 +1891,11 @@
struct secure_partition_desc *sp;
unsigned int idx;
uintptr_t base_va = (uintptr_t)x1;
- uint32_t tf_attr = 0;
+ uint64_t max_page_count = x2 + 1;
+ uint64_t page_count = 0;
+ uint32_t base_page_attr = 0;
+ uint32_t page_attr = 0;
+ unsigned int table_level;
int ret;
/* This request cannot originate from the Normal world. */
@@ -1916,17 +1927,49 @@
return spmc_ffa_error_return(handle, FFA_ERROR_DENIED);
}
+ base_va &= ~(PAGE_SIZE_MASK);
+
/* Request the permissions */
- ret = xlat_get_mem_attributes_ctx(sp->xlat_ctx_handle, base_va, &tf_attr);
+ ret = xlat_get_mem_attributes_ctx(sp->xlat_ctx_handle, base_va,
+ &base_page_attr, &table_level);
if (ret != 0) {
return spmc_ffa_error_return(handle,
FFA_ERROR_INVALID_PARAMETER);
}
- /* Convert TF-A permission to FF-A permissions attributes. */
- x2 = mmap_perm_to_ffa_perm(tf_attr);
+ /*
+ * Caculate how many pages in this block entry from base_va including
+ * its page.
+ */
+ page_count = ((XLAT_BLOCK_SIZE(table_level) -
+ (base_va & XLAT_BLOCK_MASK(table_level))) >> PAGE_SIZE_SHIFT);
+ base_va += XLAT_BLOCK_SIZE(table_level);
- SMC_RET3(handle, FFA_SUCCESS_SMC32, 0, x2);
+ while ((page_count < max_page_count) && (base_va != 0x00)) {
+ ret = xlat_get_mem_attributes_ctx(sp->xlat_ctx_handle, base_va,
+ &page_attr, &table_level);
+ if (ret != 0) {
+ return spmc_ffa_error_return(handle,
+ FFA_ERROR_INVALID_PARAMETER);
+ }
+
+ if (page_attr != base_page_attr) {
+ break;
+ }
+
+ base_va += XLAT_BLOCK_SIZE(table_level);
+ page_count += (XLAT_BLOCK_SIZE(table_level) >> PAGE_SIZE_SHIFT);
+ }
+
+ if (page_count > max_page_count) {
+ page_count = max_page_count;
+ }
+
+ /* Convert TF-A permission to FF-A permissions attributes. */
+ x2 = mmap_perm_to_ffa_perm(base_page_attr);
+
+ /* x3 should be page count - 1 */
+ SMC_RET4(handle, FFA_SUCCESS_SMC32, 0, x2, --page_count);
}
/*******************************************************************************
@@ -2577,5 +2620,5 @@
return spmd_smc_switch_state(FFA_INTERRUPT, false,
FFA_PARAM_MBZ, FFA_PARAM_MBZ,
FFA_PARAM_MBZ, FFA_PARAM_MBZ,
- handle, 0ULL);
+ handle, 0ULL, sp->ffa_version);
}
diff --git a/services/std_svc/spm/el3_spmc/spmc_pm.c b/services/std_svc/spm/el3_spmc/spmc_pm.c
index 0a6215c..b267212 100644
--- a/services/std_svc/spm/el3_spmc/spmc_pm.c
+++ b/services/std_svc/spm/el3_spmc/spmc_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -201,7 +201,7 @@
/*******************************************************************************
* spmc_cpu_suspend_finish_handler
******************************************************************************/
-static void spmc_cpu_suspend_finish_handler(u_register_t unused)
+static void spmc_cpu_suspend_finish_handler(u_register_t unused, bool abandon)
{
struct secure_partition_desc *sp = spmc_get_current_sp_ctx();
unsigned int linear_id = plat_my_core_pos();
@@ -210,6 +210,9 @@
/* Sanity check for a NULL pointer dereference. */
assert(sp != NULL);
+ /* EL3 SPMC is not expected to be used on platforms with pabandon */
+ assert(!abandon);
+
/*
* Check if the SP has subscribed for this power management message.
* If not then we don't have anything else to do here.
diff --git a/services/std_svc/spm/spm_mm/spm_mm_main.c b/services/std_svc/spm/spm_mm/spm_mm_main.c
index 7fe826d..c204987 100644
--- a/services/std_svc/spm/spm_mm/spm_mm_main.c
+++ b/services/std_svc/spm/spm_mm/spm_mm_main.c
@@ -21,6 +21,7 @@
#include <plat/common/platform.h>
#include <services/spm_mm_partition.h>
#include <services/spm_mm_svc.h>
+#include <services/ven_el3_svc.h>
#include <smccc_helpers.h>
#include "spm_common.h"
@@ -31,6 +32,14 @@
******************************************************************************/
static sp_context_t sp_ctx;
+/********************************************************************************
+ * TPM service UUID: 17b862a4-1806-4faf-86b3-089a58353861 as mentioned in
+ * https://developer.arm.com/documentation/den0138/latest/
+ *******************************************************************************/
+DEFINE_SVC_UUID2(tpm_service_uuid,
+ 0x17b862a4, 0x1806, 0x4faf, 0x86, 0xb3,
+ 0x08, 0x9a, 0x58, 0x35, 0x38, 0x61);
+
/*******************************************************************************
* Set state of a Secure Partition context.
******************************************************************************/
@@ -251,6 +260,46 @@
}
/*******************************************************************************
+ * SPM_MM TPM start handler as mentioned in section 3.3.1 of TCG ACPI
+ * specification version 1.4
+ ******************************************************************************/
+uint64_t spm_mm_tpm_start_handler(uint32_t smc_fid,
+ uint64_t x1,
+ uint64_t x2,
+ uint64_t x3,
+ uint64_t x4,
+ void *cookie,
+ void *handle,
+ uint64_t flags)
+{
+ mm_communicate_header_t *mm_comm_header = (void *)PLAT_SPM_BUF_BASE;
+ uint32_t spm_mm_smc_fid;
+
+ if (!is_caller_non_secure(flags)) {
+ ERROR("spm_mm TPM START must be requested from normal world only.\n");
+ SMC_RET1(handle, SMC_UNK);
+ }
+
+ switch (smc_fid) {
+ case TPM_START_SMC_32:
+ spm_mm_smc_fid = MM_COMMUNICATE_AARCH32;
+ break;
+ case TPM_START_SMC_64:
+ spm_mm_smc_fid = MM_COMMUNICATE_AARCH64;
+ break;
+ default:
+ ERROR("Unexpected SMC FID\n");
+ SMC_RET1(handle, SMC_UNK);
+ break;
+ }
+
+ memset(mm_comm_header, 0U, sizeof(mm_communicate_header_t));
+ memcpy(&mm_comm_header->header_guid, &tpm_service_uuid, sizeof(struct efi_guid));
+
+ return mm_communicate(spm_mm_smc_fid, x1, (uint64_t)mm_comm_header, x3, handle);
+}
+
+/*******************************************************************************
* Secure Partition Manager SMC handler.
******************************************************************************/
uint64_t spm_mm_smc_handler(uint32_t smc_fid,
@@ -263,6 +312,9 @@
uint64_t flags)
{
unsigned int ns;
+ int32_t ret;
+ uint32_t attr;
+ uint32_t page_count;
/* Determine which security state this SMC originated from */
ns = is_caller_non_secure(flags);
@@ -291,9 +343,17 @@
WARN("MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 is available at boot time only\n");
SMC_RET1(handle, SPM_MM_NOT_SUPPORTED);
}
- SMC_RET1(handle,
- spm_memory_attributes_get_smc_handler(
- &sp_ctx, x1));
+
+ /* x2 = page_count - 1 */
+ page_count = x2 + 1;
+
+ ret = spm_memory_attributes_get_smc_handler(
+ &sp_ctx, x1, &page_count, &attr);
+ if (ret != SPM_MM_SUCCESS) {
+ SMC_RET1(handle, ret);
+ } else {
+ SMC_RET2(handle, attr, --page_count);
+ }
case MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64:
INFO("Received MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64 SMC\n");
diff --git a/services/std_svc/spm/spm_mm/spm_mm_private.h b/services/std_svc/spm/spm_mm/spm_mm_private.h
index 3a52a3e..473d84d 100644
--- a/services/std_svc/spm/spm_mm/spm_mm_private.h
+++ b/services/std_svc/spm/spm_mm/spm_mm_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -56,7 +56,9 @@
void spm_sp_setup(sp_context_t *sp_ctx);
int32_t spm_memory_attributes_get_smc_handler(sp_context_t *sp_ctx,
- uintptr_t base_va);
+ uintptr_t base_va,
+ uint32_t *page_count,
+ uint32_t *attr);
int spm_memory_attributes_set_smc_handler(sp_context_t *sp_ctx,
u_register_t page_address,
u_register_t pages_count,
diff --git a/services/std_svc/spm/spm_mm/spm_mm_setup.c b/services/std_svc/spm/spm_mm/spm_mm_setup.c
index 66ce84c..ebc5387 100644
--- a/services/std_svc/spm/spm_mm/spm_mm_setup.c
+++ b/services/std_svc/spm/spm_mm/spm_mm_setup.c
@@ -20,7 +20,7 @@
#include <lib/hob/mpinfo.h>
#endif
#if TRANSFER_LIST
-#include <lib/transfer_list.h>
+#include <transfer_list.h>
#endif
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <platform_def.h>
diff --git a/services/std_svc/spm/spm_mm/spm_mm_xlat.c b/services/std_svc/spm/spm_mm/spm_mm_xlat.c
index 01d95c7..32eda3a 100644
--- a/services/std_svc/spm/spm_mm/spm_mm_xlat.c
+++ b/services/std_svc/spm/spm_mm/spm_mm_xlat.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2025, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -88,22 +88,61 @@
}
int32_t spm_memory_attributes_get_smc_handler(sp_context_t *sp_ctx,
- uintptr_t base_va)
+ uintptr_t base_va,
+ uint32_t *page_count,
+ uint32_t *attr)
{
- uint32_t attributes;
+ uint32_t cur_attr;
+ uint32_t table_level;
+ uint32_t count;
+ int rc;
+
+ assert((page_count != NULL) && (*page_count > 0));
+ assert(attr != NULL);
+
+ base_va &= ~(PAGE_SIZE_MASK);
spin_lock(&mem_attr_smc_lock);
- int rc = xlat_get_mem_attributes_ctx(sp_ctx->xlat_ctx_handle,
- base_va, &attributes);
+ rc = xlat_get_mem_attributes_ctx(sp_ctx->xlat_ctx_handle,
+ base_va, attr, &table_level);
+ if (rc != 0) {
+ goto err_out;
+ }
+ /*
+ * Caculate how many pages in this block entry from base_va including
+ * its page.
+ */
+ count = ((XLAT_BLOCK_SIZE(table_level) -
+ (base_va & XLAT_BLOCK_MASK(table_level))) >> PAGE_SIZE_SHIFT);
+ base_va += XLAT_BLOCK_SIZE(table_level);
+
+ while ((count < *page_count) && (base_va != 0x00)) {
+ rc = xlat_get_mem_attributes_ctx(sp_ctx->xlat_ctx_handle,
+ base_va, &cur_attr, &table_level);
+ if (rc != 0) {
+ goto err_out;
+ }
+
+ if (*attr != cur_attr) {
+ *page_count = count;
+ break;
+ }
+
+ base_va += XLAT_BLOCK_SIZE(table_level);
+ count += (XLAT_BLOCK_SIZE(table_level) >> PAGE_SIZE_SHIFT);
+ }
+
+ *attr = smc_mmap_to_smc_attr(*attr);
+
+err_out:
spin_unlock(&mem_attr_smc_lock);
-
/* Convert error codes of xlat_get_mem_attributes_ctx() into SPM. */
assert((rc == 0) || (rc == -EINVAL));
if (rc == 0) {
- return (int32_t) smc_mmap_to_smc_attr(attributes);
+ return SPM_MM_SUCCESS;
} else {
return SPM_MM_INVALID_PARAMETER;
}
diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
index 310610d..15addec 100644
--- a/services/std_svc/spmd/spmd_main.c
+++ b/services/std_svc/spmd/spmd_main.c
@@ -46,6 +46,21 @@
static spmc_manifest_attribute_t spmc_attrs;
/*******************************************************************************
+ * FFA version used by nonsecure endpoint.
+ ******************************************************************************/
+static uint32_t nonsecure_ffa_version;
+
+/*******************************************************************************
+ * Whether the normal world finished negotiating its version.
+ ******************************************************************************/
+static bool nonsecure_version_negotiated;
+
+/*******************************************************************************
+ * FFA version used by SPMC, as seen by the normal world.
+ ******************************************************************************/
+static uint32_t spmc_nwd_ffa_version;
+
+/*******************************************************************************
* SPM Core entry point information. Discovered on the primary core and reused
* on secondary cores.
******************************************************************************/
@@ -81,7 +96,8 @@
uint64_t x4,
void *cookie,
void *handle,
- uint64_t flags);
+ uint64_t flags,
+ uint32_t secure_ffa_version);
/******************************************************************************
* Builds an SPMD to SPMC direct message request.
@@ -672,10 +688,13 @@
uint64_t x3,
uint64_t x4,
void *handle,
- uint64_t flags)
+ uint64_t flags,
+ uint32_t secure_ffa_version)
{
unsigned int secure_state_in = (secure_origin) ? SECURE : NON_SECURE;
unsigned int secure_state_out = (!secure_origin) ? SECURE : NON_SECURE;
+ uint32_t version_in = (secure_origin) ? secure_ffa_version : nonsecure_ffa_version;
+ uint32_t version_out = (!secure_origin) ? secure_ffa_version : nonsecure_ffa_version;
void *ctx_out;
#if SPMD_SPM_AT_SEL2
@@ -715,40 +734,39 @@
SMC_RET0(ctx_out);
}
-#if SPMD_SPM_AT_SEL2
- /*
- * If SPMC is at SEL2, save additional registers x8-x17, which may
- * be used in FF-A calls such as FFA_PARTITION_INFO_GET_REGS.
- * Note that technically, all SPMCs can support this, but this code is
- * under ifdef to minimize breakage in case other SPMCs do not save
- * and restore x8-x17.
- * We also need to pass through these registers since not all FF-A ABIs
- * modify x8-x17, in which case, SMCCC requires that these registers be
- * preserved, so the SPMD passes through these registers and expects the
- * SPMC to save and restore (potentially also modify) them.
- */
- SMC_RET18(ctx_out, smc_fid, x1, x2, x3, x4,
- SMC_GET_GP(handle, CTX_GPREG_X5),
- SMC_GET_GP(handle, CTX_GPREG_X6),
- SMC_GET_GP(handle, CTX_GPREG_X7),
- SMC_GET_GP(handle, CTX_GPREG_X8),
- SMC_GET_GP(handle, CTX_GPREG_X9),
- SMC_GET_GP(handle, CTX_GPREG_X10),
- SMC_GET_GP(handle, CTX_GPREG_X11),
- SMC_GET_GP(handle, CTX_GPREG_X12),
- SMC_GET_GP(handle, CTX_GPREG_X13),
- SMC_GET_GP(handle, CTX_GPREG_X14),
- SMC_GET_GP(handle, CTX_GPREG_X15),
- SMC_GET_GP(handle, CTX_GPREG_X16),
- SMC_GET_GP(handle, CTX_GPREG_X17)
- );
-
-#else
- SMC_RET8(ctx_out, smc_fid, x1, x2, x3, x4,
- SMC_GET_GP(handle, CTX_GPREG_X5),
- SMC_GET_GP(handle, CTX_GPREG_X6),
- SMC_GET_GP(handle, CTX_GPREG_X7));
-#endif
+ if ((GET_SMC_CC(smc_fid) == SMC_64) && (version_out >= MAKE_FFA_VERSION(U(1), U(2)))) {
+ if (version_in < MAKE_FFA_VERSION(U(1), U(2))) {
+ /* FFA version mismatch, with dest >= 1.2 - set outgoing x8-x17 to zero */
+ SMC_RET18(ctx_out, smc_fid, x1, x2, x3, x4,
+ SMC_GET_GP(handle, CTX_GPREG_X5),
+ SMC_GET_GP(handle, CTX_GPREG_X6),
+ SMC_GET_GP(handle, CTX_GPREG_X7),
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+ } else {
+ /* Both FFA versions >= 1.2 - pass incoming x8-x17 to dest */
+ SMC_RET18(ctx_out, smc_fid, x1, x2, x3, x4,
+ SMC_GET_GP(handle, CTX_GPREG_X5),
+ SMC_GET_GP(handle, CTX_GPREG_X6),
+ SMC_GET_GP(handle, CTX_GPREG_X7),
+ SMC_GET_GP(handle, CTX_GPREG_X8),
+ SMC_GET_GP(handle, CTX_GPREG_X9),
+ SMC_GET_GP(handle, CTX_GPREG_X10),
+ SMC_GET_GP(handle, CTX_GPREG_X11),
+ SMC_GET_GP(handle, CTX_GPREG_X12),
+ SMC_GET_GP(handle, CTX_GPREG_X13),
+ SMC_GET_GP(handle, CTX_GPREG_X14),
+ SMC_GET_GP(handle, CTX_GPREG_X15),
+ SMC_GET_GP(handle, CTX_GPREG_X16),
+ SMC_GET_GP(handle, CTX_GPREG_X17)
+ );
+ }
+ } else {
+ /* 32 bit call or dest has FFA version < 1.2 or unknown */
+ SMC_RET8(ctx_out, smc_fid, x1, x2, x3, x4,
+ SMC_GET_GP(handle, CTX_GPREG_X5),
+ SMC_GET_GP(handle, CTX_GPREG_X6),
+ SMC_GET_GP(handle, CTX_GPREG_X7));
+ }
}
/*******************************************************************************
@@ -762,7 +780,8 @@
uint64_t x4,
void *cookie,
void *handle,
- uint64_t flags)
+ uint64_t flags,
+ uint32_t secure_ffa_version)
{
if (is_spmc_at_el3() && !secure_origin) {
return spmc_smc_handler(smc_fid, secure_origin, x1, x2, x3, x4,
@@ -770,7 +789,7 @@
}
return spmd_smc_switch_state(smc_fid, secure_origin, x1, x2, x3, x4,
- handle, flags);
+ handle, flags, secure_ffa_version);
}
@@ -835,7 +854,16 @@
}
}
return spmd_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
- handle, flags);
+ handle, flags, spmc_nwd_ffa_version);
+}
+
+static uint32_t get_common_ffa_version(uint32_t secure_ffa_version)
+{
+ if (secure_ffa_version <= nonsecure_ffa_version) {
+ return secure_ffa_version;
+ } else {
+ return nonsecure_ffa_version;
+ }
}
/*******************************************************************************
@@ -849,7 +877,8 @@
uint64_t x4,
void *cookie,
void *handle,
- uint64_t flags)
+ uint64_t flags,
+ uint32_t secure_ffa_version)
{
spmd_spm_core_context_t *ctx = spmd_get_context();
bool secure_origin;
@@ -876,6 +905,14 @@
spmd_spm_core_sync_exit(0ULL);
}
+ if ((!secure_origin) && (smc_fid != FFA_VERSION)) {
+ /*
+ * Once the caller invokes any FF-A ABI other than FFA_VERSION,
+ * the version negotiation phase is complete.
+ */
+ nonsecure_version_negotiated = true;
+ }
+
switch (smc_fid) {
case FFA_ERROR:
/*
@@ -903,7 +940,7 @@
return spmd_smc_forward(smc_fid, secure_origin,
x1, x2, x3, x4, cookie,
- handle, flags);
+ handle, flags, secure_ffa_version);
break; /* not reached */
case FFA_VERSION:
@@ -912,8 +949,10 @@
* If caller is secure and SPMC was initialized,
* return FFA_VERSION of SPMD.
* If caller is non secure and SPMC was initialized,
- * forward to the EL3 SPMC if enabled, otherwise return
- * the SPMC version if implemented at a lower EL.
+ * forward to the EL3 SPMC if enabled, otherwise send a
+ * framework message to the SPMC at the lower EL to
+ * negotiate a version that is compatible between the
+ * normal world and the SPMC.
* Sanity check to "input_version".
* If the EL3 SPMC is enabled, ignore the SPMC state as
* this is not used.
@@ -922,13 +961,25 @@
(!is_spmc_at_el3() && (ctx->state == SPMC_STATE_RESET))) {
ret = FFA_ERROR_NOT_SUPPORTED;
} else if (!secure_origin) {
+ if (!nonsecure_version_negotiated) {
+ /*
+ * Once an FF-A version has been negotiated
+ * between a caller and a callee, the version
+ * may not be changed for the lifetime of
+ * the calling component.
+ */
+ nonsecure_ffa_version = input_version;
+ }
+
if (is_spmc_at_el3()) {
/*
* Forward the call directly to the EL3 SPMC, if
* enabled, as we don't need to wrap the call in
* a direct request.
*/
- return spmd_smc_forward(smc_fid, secure_origin,
+ spmc_nwd_ffa_version =
+ MAKE_FFA_VERSION(FFA_VERSION_MAJOR, FFA_VERSION_MINOR);
+ return spmc_smc_handler(smc_fid, secure_origin,
x1, x2, x3, x4, cookie,
handle, flags);
}
@@ -940,6 +991,7 @@
spmc_attrs.minor_version == 0) {
ret = MAKE_FFA_VERSION(spmc_attrs.major_version,
spmc_attrs.minor_version);
+ spmc_nwd_ffa_version = (uint32_t)ret;
SMC_RET8(handle, (uint32_t)ret,
FFA_TARGET_INFO_MBZ,
FFA_TARGET_INFO_MBZ,
@@ -992,6 +1044,7 @@
ret = FFA_ERROR_NOT_SUPPORTED;
} else {
ret = SMC_GET_GP(gpregs, CTX_GPREG_X3);
+ spmc_nwd_ffa_version = (uint32_t)ret;
}
/*
@@ -1010,7 +1063,7 @@
return spmd_smc_forward(ret, true, FFA_PARAM_MBZ,
FFA_PARAM_MBZ, FFA_PARAM_MBZ,
FFA_PARAM_MBZ, cookie, gpregs,
- flags);
+ flags, spmc_nwd_ffa_version);
} else {
ret = MAKE_FFA_VERSION(FFA_VERSION_MAJOR,
FFA_VERSION_MINOR);
@@ -1031,7 +1084,7 @@
if (!secure_origin) {
return spmd_smc_forward(smc_fid, secure_origin,
x1, x2, x3, x4, cookie,
- handle, flags);
+ handle, flags, secure_ffa_version);
}
/*
@@ -1112,9 +1165,14 @@
break; /* not reached */
+ case FFA_MSG_SEND_DIRECT_REQ2_SMC64:
+ if (get_common_ffa_version(secure_ffa_version) < MAKE_FFA_VERSION(U(1), U(2))) {
+ /* Call not supported at this version */
+ return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED);
+ }
+ /* fallthrough */
case FFA_MSG_SEND_DIRECT_REQ_SMC32:
case FFA_MSG_SEND_DIRECT_REQ_SMC64:
- case FFA_MSG_SEND_DIRECT_REQ2_SMC64:
/*
* Regardless of secure_origin, SPMD logical partitions cannot
* handle direct messages. They can only initiate direct
@@ -1154,13 +1212,18 @@
/* Forward direct message to the other world */
return spmd_smc_forward(smc_fid, secure_origin,
x1, x2, x3, x4, cookie,
- handle, flags);
+ handle, flags, secure_ffa_version);
}
break; /* Not reached */
+ case FFA_MSG_SEND_DIRECT_RESP2_SMC64:
+ if (get_common_ffa_version(secure_ffa_version) < MAKE_FFA_VERSION(U(1), U(2))) {
+ /* Call not supported at this version */
+ return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED);
+ }
+ /* fallthrough */
case FFA_MSG_SEND_DIRECT_RESP_SMC32:
case FFA_MSG_SEND_DIRECT_RESP_SMC64:
- case FFA_MSG_SEND_DIRECT_RESP2_SMC64:
if (secure_origin && (spmd_is_spmc_message(x1) ||
is_spmd_logical_sp_dir_req_in_progress(ctx))) {
spmd_spm_core_sync_exit(0ULL);
@@ -1168,7 +1231,7 @@
/* Forward direct message to the other world */
return spmd_smc_forward(smc_fid, secure_origin,
x1, x2, x3, x4, cookie,
- handle, flags);
+ handle, flags, secure_ffa_version);
}
break; /* Not reached */
case FFA_RX_RELEASE:
@@ -1228,7 +1291,7 @@
return spmd_smc_forward(smc_fid, secure_origin,
x1, x2, x3, x4, cookie,
- handle, flags);
+ handle, flags, secure_ffa_version);
break; /* not reached */
case FFA_MSG_WAIT:
@@ -1259,7 +1322,7 @@
return spmd_smc_forward(smc_fid, secure_origin,
x1, x2, x3, x4, cookie,
- handle, flags);
+ handle, flags, secure_ffa_version);
break; /* not reached */
case FFA_NORMAL_WORLD_RESUME:
@@ -1283,7 +1346,7 @@
return spmd_smc_forward(smc_fid, secure_origin,
x1, x2, x3, x4, cookie,
- handle, flags);
+ handle, flags, secure_ffa_version);
break; /* Not reached */
#endif
case FFA_CONSOLE_LOG_SMC32:
diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c
index deca1c0..11c6031 100644
--- a/services/std_svc/std_svc_setup.c
+++ b/services/std_svc/std_svc_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,6 +15,7 @@
#include <lib/runtime_instr.h>
#include <services/drtm_svc.h>
#include <services/errata_abi_svc.h>
+#include <services/lfa_svc.h>
#include <services/pci_svc.h>
#include <services/rmmd_svc.h>
#include <services/sdei.h>
@@ -86,6 +87,15 @@
}
#endif /* DRTM_SUPPORT */
+#if LFA_SUPPORT
+ /*
+ * Setup/Initialize resources useful during LFA
+ */
+ if (lfa_setup() != 0) {
+ ret = 1;
+ }
+#endif /* LFA_SUPPORT */
+
return ret;
}
@@ -217,6 +227,13 @@
}
#endif /* DRTM_SUPPORT */
+#if LFA_SUPPORT
+ if (is_lfa_fid(smc_fid)) {
+ return lfa_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
+ }
+#endif /* LFA_SUPPORT */
+
+
switch (smc_fid) {
case ARM_STD_SVC_CALL_COUNT:
/*
diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile
index e403b2d..cd676f0 100644
--- a/tools/cert_create/Makefile
+++ b/tools/cert_create/Makefile
@@ -4,14 +4,9 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-PLAT := none
-DEBUG := 0
-CRTTOOL ?= cert_create$(.exe)
-BINARY := $(notdir ${CRTTOOL})
-COT := tbbr
-
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
+include ${MAKE_HELPERS_DIRECTORY}build-rules.mk
include ${MAKE_HELPERS_DIRECTORY}common.mk
include ${MAKE_HELPERS_DIRECTORY}defaults.mk
include ${MAKE_HELPERS_DIRECTORY}toolchain.mk
@@ -24,12 +19,12 @@
endif
# Common source files.
-OBJECTS := src/cert.o \
- src/cmd_opt.o \
- src/ext.o \
- src/key.o \
- src/main.o \
- src/sha.o
+CRTTOOL_SOURCES := src/cert.c \
+ src/cmd_opt.c \
+ src/ext.c \
+ src/key.c \
+ src/main.c \
+ src/sha.c
# Chain of trust.
ifeq (${COT},tbbr)
@@ -50,22 +45,24 @@
# from setting the OPENSSL_DIR path.
$(eval $(call SELECT_OPENSSL_API_VERSION))
-HOSTCCFLAGS := -Wall -std=c99
+CRTTOOL_CFLAGS := -Wall -std=c99
ifeq (${DEBUG},1)
- HOSTCCFLAGS += -g -O0 -DDEBUG -DLOG_LEVEL=40
+ CRTTOOL_DEFINES += DEBUG LOG_LEVEL=40
+ CRTTOOL_CFLAGS+= -g -O0
else
- HOSTCCFLAGS += -O2 -DLOG_LEVEL=20
+ CRTTOOL_DEFINES += LOG_LEVEL=20
+ CRTTOOL_CFLAGS += -O2
endif
-HOSTCCFLAGS += ${DEFINES} -DPLAT_MSG=$(call escape-shell,"$(PLAT_MSG)")
+CRTTOOL_DEFINES += PLAT_MSG=$(call escape-shell,"$(PLAT_MSG)")
# USING_OPENSSL3 flag will be added to the HOSTCCFLAGS variable with the proper
# computed value.
-HOSTCCFLAGS += -DUSING_OPENSSL3=$(USING_OPENSSL3)
+CRTTOOL_DEFINES += USING_OPENSSL3=$(USING_OPENSSL3)
# Make soft links and include from local directory otherwise wrong headers
# could get pulled in from firmware tree.
-INC_DIR += -I ./include -I ${PLAT_INCLUDE} -I ${OPENSSL_DIR}/include
+CRTTOOL_INCLUDE_DIRS += ./include ${PLAT_INCLUDE} ${OPENSSL_DIR}/include
# Include library directories where OpenSSL library files are located.
# For a normal installation (i.e.: when ${OPENSSL_DIR} = /usr or
@@ -73,20 +70,14 @@
# directory. However, for a local build of OpenSSL, the built binaries are
# located under the main project directory (i.e.: ${OPENSSL_DIR}, not
# ${OPENSSL_DIR}/lib/).
-LIB_DIR := -L ${OPENSSL_DIR}/lib -L ${OPENSSL_DIR}
-LIB := -lssl -lcrypto
+CRTTOOL_LDFLAGS += -L ${OPENSSL_DIR}/lib -L ${OPENSSL_DIR}
+CRTTOOL_LDFLAGS += -lssl -lcrypto
.PHONY: all clean realclean --openssl
-all: --openssl ${BINARY}
+$(eval $(call MAKE_TOOL,$(BUILD_PLAT)/tools,cert_create,CRTTOOL))
-${BINARY}: ${OBJECTS} Makefile
- $(s)echo " HOSTLD $@"
- $(q)$(host-cc) ${OBJECTS} ${LIB_DIR} ${LIB} -o $@
-
-%.o: %.c
- $(s)echo " HOSTCC $<"
- $(q)$(host-cc) -c ${HOSTCCFLAGS} ${INC_DIR} $< -o $@
+all: --openssl
--openssl:
ifeq ($(DEBUG),1)
@@ -94,7 +85,6 @@
endif
clean:
- $(q)rm -rf $(OBJECTS)
+ $(q)rm -rf $(BUILD_PLAT)/tools/cert_create
realclean: clean
- $(q)rm -f $(BINARY)
diff --git a/tools/cert_create/src/cca/cot.mk b/tools/cert_create/src/cca/cot.mk
index d0c80bb..869abe8 100644
--- a/tools/cert_create/src/cca/cot.mk
+++ b/tools/cert_create/src/cca/cot.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2022, Arm Limited. All rights reserved.
+# Copyright (c) 2022-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -7,4 +7,4 @@
PLAT_MSG := Confidential Compute Architecture root of trust
PLAT_INCLUDE := ../../include/tools_share
-OBJECTS += src/cca/cot.o
+CRTTOOL_SOURCES += src/cca/cot.c
diff --git a/tools/cert_create/src/dualroot/cot.mk b/tools/cert_create/src/dualroot/cot.mk
index a572484..53ded5c 100644
--- a/tools/cert_create/src/dualroot/cot.mk
+++ b/tools/cert_create/src/dualroot/cot.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2020, Arm Limited. All rights reserved.
+# Copyright (c) 2020-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -7,4 +7,4 @@
PLAT_MSG := Dual root of trust
PLAT_INCLUDE := ../../include/tools_share
-OBJECTS += src/dualroot/cot.o
+CRTTOOL_SOURCES += src/dualroot/cot.c
diff --git a/tools/cert_create/src/tbbr/tbbr.mk b/tools/cert_create/src/tbbr/tbbr.mk
index ee82d31..6ff8e9f 100644
--- a/tools/cert_create/src/tbbr/tbbr.mk
+++ b/tools/cert_create/src/tbbr/tbbr.mk
@@ -1,11 +1,11 @@
#
-# Copyright (c) 2020, Arm Limited. All rights reserved.
+# Copyright (c) 2020-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
USE_TBBR_DEFS := 1
-$(eval $(call add_define,USE_TBBR_DEFS))
+CRTTOOL_DEFINES += USE_TBBR_DEFS=${USE_TBBR_DEFS}
ifeq (${USE_TBBR_DEFS},1)
# In this case, cert_tool is platform-independent
@@ -24,6 +24,6 @@
endif
endif
-OBJECTS += src/tbbr/tbb_cert.o \
- src/tbbr/tbb_ext.o \
- src/tbbr/tbb_key.o
+CRTTOOL_SOURCES += src/tbbr/tbb_cert.c \
+ src/tbbr/tbb_ext.c \
+ src/tbbr/tbb_key.c
diff --git a/tools/encrypt_fw/Makefile b/tools/encrypt_fw/Makefile
index 14def1d..9552aa3 100644
--- a/tools/encrypt_fw/Makefile
+++ b/tools/encrypt_fw/Makefile
@@ -7,45 +7,44 @@
BUILD_INFO ?= 1
DEBUG := 0
-ENCTOOL ?= encrypt_fw$(.exe)
-BINARY := $(notdir ${ENCTOOL})
OPENSSL_DIR := /usr
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
+include ${MAKE_HELPERS_DIRECTORY}build-rules.mk
include ${MAKE_HELPERS_DIRECTORY}common.mk
include ${MAKE_HELPERS_DIRECTORY}defaults.mk
include ${MAKE_HELPERS_DIRECTORY}toolchain.mk
-OBJECTS := src/encrypt.o \
- src/cmd_opt.o \
- src/main.o
+ENCTOOL_SOURCES := src/encrypt.c \
+ src/cmd_opt.c \
+ src/main.c
-HOSTCCFLAGS := -Wall -std=c99
+ENCTOOL_CFLAGS := -Wall -std=c99
# Select OpenSSL version flag according to the OpenSSL build selected
# from setting the OPENSSL_DIR path.
$(eval $(call SELECT_OPENSSL_API_VERSION))
ifeq (${DEBUG},1)
- HOSTCCFLAGS += -g -O0 -DDEBUG -DLOG_LEVEL=40
+ ENCTOOL_CFLAGS += -g -O0
+ ENCTOOL_DEFINES += DEBUG LOG_LEVEL=40
else
+ ENCTOOL_CFLAGS += -O2
ifeq (${BUILD_INFO},1)
- HOSTCCFLAGS += -O2 -DLOG_LEVEL=20
+ ENCTOOL_DEFINES += LOG_LEVEL=20
else
- HOSTCCFLAGS += -O2 -DLOG_LEVEL=10
+ ENCTOOL_DEFINES += LOG_LEVEL=10
endif
endif
-HOSTCCFLAGS += ${DEFINES}
-# USING_OPENSSL3 flag will be added to the HOSTCCFLAGS variable with the proper
-# computed value.
-HOSTCCFLAGS += -DUSING_OPENSSL3=$(USING_OPENSSL3)
+# USING_OPENSSL3 flag will be added to the proper computed value.
+ENCTOOL_DEFINES += USING_OPENSSL3=$(USING_OPENSSL3)
# Make soft links and include from local directory otherwise wrong headers
# could get pulled in from firmware tree.
-INC_DIR := -I ./include -I ../../include/tools_share -I ${OPENSSL_DIR}/include
+ENCTOOL_INCLUDE_DIRS := ./include ../../include/tools_share ${OPENSSL_DIR}/include
# Include library directories where OpenSSL library files are located.
# For a normal installation (i.e.: when ${OPENSSL_DIR} = /usr or
@@ -53,20 +52,14 @@
# directory. However, for a local build of OpenSSL, the built binaries are
# located under the main project directory (i.e.: ${OPENSSL_DIR}, not
# ${OPENSSL_DIR}/lib/).
-LIB_DIR := -L ${OPENSSL_DIR}/lib -L ${OPENSSL_DIR}
-LIB := -lssl -lcrypto
+ENCTOOL_LDFLAGS := -L${OPENSSL_DIR}/lib -L${OPENSSL_DIR}
+ENCTOOL_LDFLAGS += -lssl -lcrypto
.PHONY: all clean realclean --openssl
-all: --openssl ${BINARY}
+all: --openssl
-${BINARY}: ${OBJECTS} Makefile
- $(s)echo " HOSTLD $@"
- $(q)$(host-cc) ${OBJECTS} ${LIB_DIR} ${LIB} -o $@
-
-%.o: %.c
- $(s)echo " HOSTCC $<"
- $(q)$(host-cc) -c ${HOSTCCFLAGS} ${INC_DIR} $< -o $@
+$(eval $(call MAKE_TOOL,$(BUILD_PLAT)/tools,encrypt_fw,ENCTOOL))
--openssl:
ifeq ($(DEBUG),1)
@@ -74,7 +67,6 @@
endif
clean:
- $(q)rm -rf $(OBJECTS)
+ $(q)rm -rf $(BUILD_PLAT)/tools/encrypt_fw
realclean: clean
- $(q)rm -f $(BINARY)
diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile
index a660a50..6deac9d 100644
--- a/tools/fiptool/Makefile
+++ b/tools/fiptool/Makefile
@@ -6,29 +6,28 @@
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
+include ${MAKE_HELPERS_DIRECTORY}build-rules.mk
include ${MAKE_HELPERS_DIRECTORY}common.mk
include ${MAKE_HELPERS_DIRECTORY}defaults.mk
include ${MAKE_HELPERS_DIRECTORY}toolchain.mk
-FIPTOOL ?= fiptool$(.exe)
-PROJECT := $(notdir ${FIPTOOL})
-OBJECTS := fiptool.o tbbr_config.o
+FIPTOOL_SOURCES := fiptool.c tbbr_config.c
STATIC ?= 0
-override CPPFLAGS += -D_GNU_SOURCE -D_XOPEN_SOURCE=700
-HOSTCCFLAGS := -Wall -Werror -pedantic -std=c99
+FIPTOOL_DEFINES += _GNU_SOURCE _XOPEN_SOURCE=700
+FIPTOOL_CFLAGS := -Wall -Werror -pedantic -std=c99
ifeq (${DEBUG},1)
- HOSTCCFLAGS += -g -O0 -DDEBUG
+ FIPTOOL_CFLAGS += -g -O0 -DDEBUG
else
- HOSTCCFLAGS += -O2
+ FIPTOOL_CFLAGS += -O2
endif
-INCLUDE_PATHS := -I../../include/tools_share
+FIPTOOL_INCLUDE_DIRS := ../../include/tools_share
-DEFINES += -DSTATIC=$(STATIC)
+FIPTOOL_DEFINES += STATIC=$(STATIC)
ifeq (${STATIC},1)
-LDOPTS := -static
+FIPTOOL_LDFLAGS := -static
else
OPENSSL_DIR := /usr
@@ -38,7 +37,7 @@
# USING_OPENSSL3 flag will be added to the HOSTCCFLAGS variable with the proper
# computed value.
-DEFINES += -DUSING_OPENSSL3=$(USING_OPENSSL3)
+FIPTOOL_DEFINES += USING_OPENSSL3=$(USING_OPENSSL3)
# Include library directories where OpenSSL library files are located.
# For a normal installation (i.e.: when ${OPENSSL_DIR} = /usr or
@@ -46,12 +45,10 @@
# directory. However, for a local build of OpenSSL, the built binaries are
# located under the main project directory (i.e.: ${OPENSSL_DIR}, not
# ${OPENSSL_DIR}/lib/).
-LDOPTS := -L${OPENSSL_DIR}/lib -L${OPENSSL_DIR} -lcrypto
-INCLUDE_PATHS += -I${OPENSSL_DIR}/include
+FIPTOOL_LDFLAGS := -L${OPENSSL_DIR}/lib -L${OPENSSL_DIR} -lcrypto
+FIPTOOL_INCLUDE_DIRS += ${OPENSSL_DIR}/include
endif # STATIC
-HOSTCCFLAGS += ${DEFINES}
-
ifneq (${PLAT},)
TF_PLATFORM_ROOT := ../../plat/
include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk
@@ -65,24 +62,11 @@
include ${PLAT_FIPTOOL_HELPER_MK}
endif
-DEPS := $(patsubst %.o,%.d,$(OBJECTS))
+$(eval $(call MAKE_TOOL,$(BUILD_PLAT)/tools,fiptool,FIPTOOL))
.PHONY: all clean distclean --openssl
-all: --openssl ${PROJECT}
-
-${PROJECT}: ${OBJECTS} Makefile
- $(s)echo " HOSTLD $@"
- $(q)$(host-cc) ${OBJECTS} -o $@ $(LDOPTS)
- $(s)echo
- $(s)echo "Built $@ successfully"
- $(s)echo
-
-%.o: %.c Makefile
- $(s)echo " HOSTCC $<"
- $(q)$(host-cc) -c ${CPPFLAGS} ${HOSTCCFLAGS} ${INCLUDE_PATHS} -MD -MP $< -o $@
-
--include $(DEPS)
+all: --openssl
--openssl:
ifeq ($(STATIC),0)
@@ -92,4 +76,4 @@
endif # STATIC
clean:
- $(q)rm -rf $(PROJECT) $(OBJECTS) $(DEPS)
+ $(q)rm -rf $(BUILD_PLAT)/tools/fiptool
diff --git a/tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk b/tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk
index 5549b0d..f36071f 100644
--- a/tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk
+++ b/tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2023, Arm Limited. All rights reserved.
+# Copyright (c) 2023-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -7,10 +7,10 @@
PLAT_DEF_UUID := yes
ifeq (${PLAT_DEF_UUID}, yes)
-HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
+FIPTOOL_DEFINES += PLAT_DEF_FIP_UUID
ifeq (${ETHOSN_NPU_TZMP1},1)
-HOSTCCFLAGS += -DETHOSN_NPU_TZMP1
+FIPTOOL_DEFINES += ETHOSN_NPU_TZMP1
endif
-INCLUDE_PATHS += -I./ -I../../plat/arm/board/juno/fip -I../../include
-OBJECTS += plat_fiptool/arm/board/juno/plat_def_uuid_config.o
+FIPTOOL_INCLUDE_DIRS += ./ ../../plat/arm/board/juno/fip ../../include
+FIPTOOL_SOURCES += plat_fiptool/arm/board/juno/plat_def_uuid_config.c
endif
diff --git a/tools/fiptool/plat_fiptool/arm/board/tc/plat_fiptool.mk b/tools/fiptool/plat_fiptool/arm/board/tc/plat_fiptool.mk
index 70ccfc5..d808451 100644
--- a/tools/fiptool/plat_fiptool/arm/board/tc/plat_fiptool.mk
+++ b/tools/fiptool/plat_fiptool/arm/board/tc/plat_fiptool.mk
@@ -1,12 +1,12 @@
#
# Copyright (c) 2021, NXP. All rights reserved.
-# Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+# Copyright (c) 2022-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
-INCLUDE_PATHS += -I./ \
- -I../../plat/arm/board/tc
+FIPTOOL_INCLUDE_DIRS += ./ \
+ ../../plat/arm/board/tc
-HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
-OBJECTS += plat_fiptool/arm/board/tc/plat_def_uuid_config.o
+FIPTOOL_DEFINES += PLAT_DEF_FIP_UUID
+FIPTOOL_SOURCES += plat_fiptool/arm/board/tc/plat_def_uuid_config.c
diff --git a/tools/fiptool/plat_fiptool/nxp/plat_fiptool.mk b/tools/fiptool/plat_fiptool/nxp/plat_fiptool.mk
index 6d7b07b..3d69500 100644
--- a/tools/fiptool/plat_fiptool/nxp/plat_fiptool.mk
+++ b/tools/fiptool/plat_fiptool/nxp/plat_fiptool.mk
@@ -1,6 +1,6 @@
#
# Copyright (c) 2021, NXP. All rights reserved.
-# Copyright (c) 2023, Arm Limited. All rights reserved.
+# Copyright (c) 2023-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -17,16 +17,14 @@
PLAT_DEF_UUID_OID_CONFIG_PATH := ../../plat/nxp/common/fip_handler/common
-INCLUDE_PATHS += -I${PLAT_DEF_UUID_OID_CONFIG_PATH} \
- -I./
+FIPTOOL_INCLUDE_DIRS += ${PLAT_DEF_UUID_OID_CONFIG_PATH} \
+ ./
ifeq (${PLAT_DEF_OID},yes)
-HOSTCCFLAGS += -DPLAT_DEF_OID
+FIPTOOL_DEFINES += PLAT_DEF_OID
endif
ifeq (${PLAT_DEF_UUID},yes)
-HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
-PLAT_OBJECTS += ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o
+FIPTOOL_DEFINES += PLAT_DEF_FIP_UUID
+FIPTOOL_SOURCES += ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.c
endif
-
-OBJECTS += ${PLAT_OBJECTS}
diff --git a/tools/fiptool/plat_fiptool/st/plat_fiptool.mk b/tools/fiptool/plat_fiptool/st/plat_fiptool.mk
index 494715c..02950e9 100644
--- a/tools/fiptool/plat_fiptool/st/plat_fiptool.mk
+++ b/tools/fiptool/plat_fiptool/st/plat_fiptool.mk
@@ -9,17 +9,12 @@
# in the plat_def_toc_entries[].
PLAT_DEF_UUID_FILE_NAME := plat_def_uuid_config
-INCLUDE_PATHS += -I../../plat/st/common/include -I./
+FIPTOOL_INCLUDE_DIRS += ../../plat/st/common/include ./
PLAT_DEF_UUID := yes
ifeq (${PLAT_DEF_UUID},yes)
-HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
+FIPTOOL_DEFINES += PLAT_DEF_FIP_UUID
-${PLAT_DEF_UUID_FILE_NAME}.o: plat_fiptool/st/${PLAT_DEF_UUID_FILE_NAME}.c
- $(host-cc) -c ${CPPFLAGS} ${HOSTCCFLAGS} ${INCLUDE_PATHS} $< -o $@
-
-PLAT_OBJECTS += ${PLAT_DEF_UUID_FILE_NAME}.o
+FIPTOOL_SOURCES += plat_fiptool/st/${PLAT_DEF_UUID_FILE_NAME}.c
endif
-
-OBJECTS += ${PLAT_OBJECTS}
diff --git a/tools/memory/poetry.lock b/tools/memory/poetry.lock
index 2747479..67641ee 100644
--- a/tools/memory/poetry.lock
+++ b/tools/memory/poetry.lock
@@ -40,6 +40,103 @@
]
[[package]]
+name = "jinja2"
+version = "3.1.6"
+description = "A very fast and expressive template engine."
+optional = false
+python-versions = ">=3.7"
+files = [
+ {file = "jinja2-3.1.6-py3-none-any.whl", hash = "sha256:85ece4451f492d0c13c5dd7c13a64681a86afae63a5f347908daf103ce6d2f67"},
+ {file = "jinja2-3.1.6.tar.gz", hash = "sha256:0137fb05990d35f1275a587e9aee6d56da821fc83491a0fb838183be43f66d6d"},
+]
+
+[package.dependencies]
+MarkupSafe = ">=2.0"
+
+[package.extras]
+i18n = ["Babel (>=2.7)"]
+
+[[package]]
+name = "markupsafe"
+version = "2.1.5"
+description = "Safely add untrusted strings to HTML/XML markup."
+optional = false
+python-versions = ">=3.7"
+files = [
+ {file = "MarkupSafe-2.1.5-cp310-cp310-macosx_10_9_universal2.whl", hash = "sha256:a17a92de5231666cfbe003f0e4b9b3a7ae3afb1ec2845aadc2bacc93ff85febc"},
+ {file = "MarkupSafe-2.1.5-cp310-cp310-macosx_10_9_x86_64.whl", hash = "sha256:72b6be590cc35924b02c78ef34b467da4ba07e4e0f0454a2c5907f473fc50ce5"},
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+ {file = "MarkupSafe-2.1.5.tar.gz", hash = "sha256:d283d37a890ba4c1ae73ffadf8046435c76e7bc2247bbb63c00bd1a709c6544b"},
+]
+
+[[package]]
+name = "nodeenv"
+version = "1.9.1"
+description = "Node.js virtual environment builder"
+optional = false
+python-versions = "!=3.0.*,!=3.1.*,!=3.2.*,!=3.3.*,!=3.4.*,!=3.5.*,!=3.6.*,>=2.7"
+files = [
+ {file = "nodeenv-1.9.1-py2.py3-none-any.whl", hash = "sha256:ba11c9782d29c27c70ffbdda2d7415098754709be8a7056d79a737cd901155c9"},
+ {file = "nodeenv-1.9.1.tar.gz", hash = "sha256:6ec12890a2dab7946721edbfbcd91f3319c6ccc9aec47be7c7e6b7011ee6645f"},
+]
+
+[[package]]
name = "prettytable"
version = "3.11.0"
description = "A simple Python library for easily displaying tabular data in a visually appealing ASCII table format"
@@ -68,6 +165,53 @@
]
[[package]]
+name = "pyright"
+version = "1.1.399"
+description = "Command line wrapper for pyright"
+optional = false
+python-versions = ">=3.7"
+files = [
+ {file = "pyright-1.1.399-py3-none-any.whl", hash = "sha256:55f9a875ddf23c9698f24208c764465ffdfd38be6265f7faf9a176e1dc549f3b"},
+ {file = "pyright-1.1.399.tar.gz", hash = "sha256:439035d707a36c3d1b443aec980bc37053fbda88158eded24b8eedcf1c7b7a1b"},
+]
+
+[package.dependencies]
+nodeenv = ">=1.6.0"
+typing-extensions = ">=4.1"
+
+[package.extras]
+all = ["nodejs-wheel-binaries", "twine (>=3.4.1)"]
+dev = ["twine (>=3.4.1)"]
+nodejs = ["nodejs-wheel-binaries"]
+
+[[package]]
+name = "ruff"
+version = "0.11.2"
+description = "An extremely fast Python linter and code formatter, written in Rust."
+optional = false
+python-versions = ">=3.7"
+files = [
+ {file = "ruff-0.11.2-py3-none-linux_armv6l.whl", hash = "sha256:c69e20ea49e973f3afec2c06376eb56045709f0212615c1adb0eda35e8a4e477"},
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+ {file = "ruff-0.11.2-py3-none-manylinux_2_17_ppc64le.manylinux2014_ppc64le.whl", hash = "sha256:a3b66a03b248c9fcd9d64d445bafdf1589326bee6fc5c8e92d7562e58883e30f"},
+ {file = "ruff-0.11.2-py3-none-manylinux_2_17_s390x.manylinux2014_s390x.whl", hash = "sha256:0397c2672db015be5aa3d4dac54c69aa012429097ff219392c018e21f5085147"},
+ {file = "ruff-0.11.2-py3-none-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:869bcf3f9abf6457fbe39b5a37333aa4eecc52a3b99c98827ccc371a8e5b6f1b"},
+ {file = "ruff-0.11.2-py3-none-musllinux_1_2_aarch64.whl", hash = "sha256:2a2b50ca35457ba785cd8c93ebbe529467594087b527a08d487cf0ee7b3087e9"},
+ {file = "ruff-0.11.2-py3-none-musllinux_1_2_armv7l.whl", hash = "sha256:7c69c74bf53ddcfbc22e6eb2f31211df7f65054bfc1f72288fc71e5f82db3eab"},
+ {file = "ruff-0.11.2-py3-none-musllinux_1_2_i686.whl", hash = "sha256:6e8fb75e14560f7cf53b15bbc55baf5ecbe373dd5f3aab96ff7aa7777edd7630"},
+ {file = "ruff-0.11.2-py3-none-musllinux_1_2_x86_64.whl", hash = "sha256:842a472d7b4d6f5924e9297aa38149e5dcb1e628773b70e6387ae2c97a63c58f"},
+ {file = "ruff-0.11.2-py3-none-win32.whl", hash = "sha256:aca01ccd0eb5eb7156b324cfaa088586f06a86d9e5314b0eb330cb48415097cc"},
+ {file = "ruff-0.11.2-py3-none-win_amd64.whl", hash = "sha256:3170150172a8f994136c0c66f494edf199a0bbea7a409f649e4bc8f4d7084080"},
+ {file = "ruff-0.11.2-py3-none-win_arm64.whl", hash = "sha256:52933095158ff328f4c77af3d74f0379e34fd52f175144cefc1b192e7ccd32b4"},
+ {file = "ruff-0.11.2.tar.gz", hash = "sha256:ec47591497d5a1050175bdf4e1a4e6272cddff7da88a2ad595e1e326041d8d94"},
+]
+
+[[package]]
name = "six"
version = "1.17.0"
description = "Python 2 and 3 compatibility utilities"
@@ -79,6 +223,17 @@
]
[[package]]
+name = "typing-extensions"
+version = "4.13.2"
+description = "Backported and Experimental Type Hints for Python 3.8+"
+optional = false
+python-versions = ">=3.8"
+files = [
+ {file = "typing_extensions-4.13.2-py3-none-any.whl", hash = "sha256:a439e7c04b49fec3e5d3e2beaa21755cadbbdc391694e28ccdd36ca4a1408f8c"},
+ {file = "typing_extensions-4.13.2.tar.gz", hash = "sha256:e6c81219bd689f51865d9e372991c540bda33a0379d5573cddb9a3a23f7caaef"},
+]
+
+[[package]]
name = "wcwidth"
version = "0.2.13"
description = "Measures the displayed width of unicode strings in a terminal"
@@ -92,4 +247,4 @@
[metadata]
lock-version = "2.0"
python-versions = "^3.8.0"
-content-hash = "d7c185b3dbfc9bba145f12146e18ce501caf081d7762f138bc5a7fde99f40543"
+content-hash = "72f05cdcfe5278c3fb4408ba76cc502c83a56615681d8307bf67fe759a9da442"
diff --git a/tools/memory/pyproject.toml b/tools/memory/pyproject.toml
index c2fdfcb..70d3de7 100644
--- a/tools/memory/pyproject.toml
+++ b/tools/memory/pyproject.toml
@@ -12,10 +12,18 @@
prettytable = "^3.5.0"
pyelftools = "^0.29.0"
python = "^3.8.0"
+jinja2 = "^3.1.6"
[tool.poetry.scripts]
memory = "memory.memmap:main"
+[tool.poetry.group.dev]
+optional = true
+
+[tool.poetry.group.dev.dependencies]
+ruff = "^0.11.2"
+pyright = "^1.1.399"
+
[build-system]
requires = ["poetry-core"]
build-backend = "poetry.core.masonry.api"
diff --git a/tools/memory/src/memory/buildparser.py b/tools/memory/src/memory/buildparser.py
deleted file mode 100755
index ea417e1..0000000
--- a/tools/memory/src/memory/buildparser.py
+++ /dev/null
@@ -1,88 +0,0 @@
-#
-# Copyright (c) 2023-2025, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-import re
-from pathlib import Path
-
-from memory.elfparser import TfaElfParser
-from memory.mapparser import TfaMapParser
-
-
-class TfaBuildParser:
- """A class for performing analysis on the memory layout of a TF-A build."""
-
- def __init__(self, path: Path, map_backend=False):
- self._modules = dict()
- self._path = path
- self.map_backend = map_backend
- self._parse_modules()
-
- def __getitem__(self, module: str):
- """Returns an TfaElfParser instance indexed by module."""
- return self._modules[module]
-
- def _parse_modules(self):
- """Parse the build files using the selected backend."""
- backend = TfaElfParser
- files = list(self._path.glob("**/*.elf"))
- io_perms = "rb"
-
- if self.map_backend or len(files) == 0:
- backend = TfaMapParser
- files = self._path.glob("**/*.map")
- io_perms = "r"
-
- for file in files:
- module_name = file.name.split("/")[-1].split(".")[0]
- with open(file, io_perms) as f:
- self._modules[module_name] = backend(f)
-
- if not len(self._modules):
- raise FileNotFoundError(
- f"failed to find files to analyse in path {self._path}!"
- )
-
- @property
- def symbols(self) -> list:
- return [
- (*sym, k) for k, v in self._modules.items() for sym in v.symbols
- ]
-
- @staticmethod
- def filter_symbols(symbols: list, regex: str = None) -> list:
- """Returns a map of symbols to modules."""
- regex = r".*" if not regex else regex
- return sorted(
- filter(lambda s: re.match(regex, s[0]), symbols),
- key=lambda s: (-s[1], s[0]),
- reverse=True,
- )
-
- def get_mem_usage_dict(self) -> dict:
- """Returns map of memory usage per memory type for each module."""
- mem_map = {}
- for k, v in self._modules.items():
- mod_mem_map = v.get_memory_layout()
- if len(mod_mem_map):
- mem_map[k] = mod_mem_map
- return mem_map
-
- def get_mem_tree_as_dict(self) -> dict:
- """Returns _tree of modules, segments and segments and their total
- memory usage."""
- return {
- k: {
- "name": k,
- **v.get_mod_mem_usage_dict(),
- **{"children": v.get_seg_map_as_dict()},
- }
- for k, v in self._modules.items()
- }
-
- @property
- def module_names(self):
- """Returns sorted list of module names."""
- return sorted(self._modules.keys())
diff --git a/tools/memory/src/memory/elfparser.py b/tools/memory/src/memory/elfparser.py
index e6581c9..019d6da 100644
--- a/tools/memory/src/memory/elfparser.py
+++ b/tools/memory/src/memory/elfparser.py
@@ -6,9 +6,22 @@
import re
from dataclasses import asdict, dataclass
-from typing import BinaryIO
+from typing import (
+ Any,
+ BinaryIO,
+ Dict,
+ Iterable,
+ List,
+ Optional,
+ Tuple,
+ Union,
+)
from elftools.elf.elffile import ELFFile
+from elftools.elf.sections import Section, SymbolTableSection
+from elftools.elf.segments import Segment
+
+from memory.image import Image, Region
@dataclass(frozen=True)
@@ -17,10 +30,10 @@
start: int
end: int
size: int
- children: list
+ children: List["TfaMemObject"]
-class TfaElfParser:
+class TfaElfParser(Image):
"""A class representing an ELF file built for TF-A.
Provides a basic interface for reading the symbol table and other
@@ -28,53 +41,70 @@
the contents an ELF file.
"""
- def __init__(self, elf_file: BinaryIO):
- self._segments = {}
- self._memory_layout = {}
+ def __init__(self, elf_file: BinaryIO) -> None:
+ self._segments: Dict[int, TfaMemObject] = {}
+ self._memory_layout: Dict[str, Dict[str, int]] = {}
elf = ELFFile(elf_file)
- self._symbols = {
- sym.name: sym.entry["st_value"]
- for sym in elf.get_section_by_name(".symtab").iter_symbols()
+ symtab = elf.get_section_by_name(".symtab")
+ assert isinstance(symtab, SymbolTableSection)
+
+ self._symbols: Dict[str, int] = {
+ sym.name: sym.entry["st_value"] for sym in symtab.iter_symbols()
}
self.set_segment_section_map(elf.iter_segments(), elf.iter_sections())
self._memory_layout = self.get_memory_layout_from_symbols()
- self._start = elf["e_entry"]
+ self._start: int = elf["e_entry"]
+ self._size: int
+ self._free: int
self._size, self._free = self._get_mem_usage()
- self._end = self._start + self._size
+ self._end: int = self._start + self._size
+
+ self._footprint: Dict[str, Region] = {}
+
+ for mem, attrs in self._memory_layout.items():
+ self._footprint[mem] = Region(
+ attrs["start"],
+ attrs["end"],
+ attrs["length"],
+ )
@property
- def symbols(self):
- return self._symbols.items()
+ def symbols(self) -> Dict[str, int]:
+ return self._symbols
@staticmethod
- def tfa_mem_obj_factory(elf_obj, name=None, children=None, segment=False):
+ def tfa_mem_obj_factory(
+ elf_obj: Union[Segment, Section],
+ name: Optional[str] = None,
+ children: Optional[List[TfaMemObject]] = None,
+ ) -> TfaMemObject:
"""Converts a pyelfparser Segment or Section to a TfaMemObject."""
# Ensure each segment is provided a name since they aren't in the
# program header.
- assert not (
- segment and name is None
- ), "Attempting to make segment without a name"
-
- if children is None:
- children = list()
+ assert not (isinstance(elf_obj, Segment) and name is None), (
+ "Attempting to make segment without a name"
+ )
# Segment and sections header keys have different prefixes.
- vaddr = "p_vaddr" if segment else "sh_addr"
- size = "p_memsz" if segment else "sh_size"
+ vaddr = "p_vaddr" if isinstance(elf_obj, Segment) else "sh_addr"
+ size = "p_memsz" if isinstance(elf_obj, Segment) else "sh_size"
+
+ name = name if isinstance(elf_obj, Segment) else elf_obj.name
+ assert name is not None
# TODO figure out how to handle free space for sections and segments
return TfaMemObject(
- name if segment else elf_obj.name,
+ name,
elf_obj[vaddr],
elf_obj[vaddr] + elf_obj[size],
elf_obj[size],
- [] if not children else children,
+ children or [],
)
- def _get_mem_usage(self) -> (int, int):
+ def _get_mem_usage(self) -> Tuple[int, int]:
"""Get total size and free space for this component."""
size = free = 0
@@ -89,36 +119,37 @@
return size, free
- def set_segment_section_map(self, segments, sections):
+ def set_segment_section_map(
+ self,
+ segments: Iterable[Segment],
+ sections: Iterable[Section],
+ ) -> None:
"""Set segment to section mappings."""
- segments = list(
- filter(lambda seg: seg["p_type"] == "PT_LOAD", segments)
- )
+ segments = filter(lambda seg: seg["p_type"] == "PT_LOAD", segments)
+ segments_list = list(segments)
for sec in sections:
- for n, seg in enumerate(segments):
+ for n, seg in enumerate(segments_list):
if seg.section_in_segment(sec):
- if n not in self._segments.keys():
+ if n not in self._segments:
self._segments[n] = self.tfa_mem_obj_factory(
- seg, name=f"{n:#02}", segment=True
+ seg, name=f"{n:#02}"
)
- self._segments[n].children.append(
- self.tfa_mem_obj_factory(sec)
- )
+ self._segments[n].children.append(self.tfa_mem_obj_factory(sec))
- def get_memory_layout_from_symbols(self, expr=None) -> dict:
+ def get_memory_layout_from_symbols(self) -> Dict[str, Dict[str, int]]:
"""Retrieve information about the memory configuration from the symbol
table.
"""
- assert len(self._symbols), "Symbol table is empty!"
+ assert self._symbols, "Symbol table is empty!"
- expr = r".*(.?R.M)_REGION.*(START|END|LENGTH)" if not expr else expr
+ expr = r".*(.?R.M)_REGION.*(START|END|LENGTH)"
region_symbols = filter(lambda s: re.match(expr, s), self._symbols)
- memory_layout = {}
+ memory_layout: Dict[str, Dict[str, int]] = {}
for symbol in region_symbols:
- region, _, attr = tuple(symbol.lower().strip("__").split("_"))
+ region, _, attr = symbol.lower().strip("__").split("_")
if region not in memory_layout:
memory_layout[region] = {}
@@ -127,29 +158,30 @@
return memory_layout
- def get_seg_map_as_dict(self):
+ def get_seg_map_as_dict(self) -> List[Dict[str, Any]]:
"""Get a dictionary of segments and their section mappings."""
- return [asdict(v) for k, v in self._segments.items()]
+ return [asdict(segment) for segment in self._segments.values()]
- def get_memory_layout(self):
+ def get_memory_layout(self) -> Dict[str, Region]:
"""Get the total memory consumed by this module from the memory
configuration.
- {"rom": {"start": 0x0, "end": 0xFF, "length": ... }
"""
- mem_dict = {}
+ mem_dict: Dict[str, Region] = {}
for mem, attrs in self._memory_layout.items():
- limit = attrs["start"] + attrs["length"]
- mem_dict[mem] = {
- "start": attrs["start"],
- "limit": limit,
- "size": attrs["end"] - attrs["start"],
- "free": limit - attrs["end"],
- "total": attrs["length"],
- }
+ mem_dict[mem] = Region(
+ attrs["start"],
+ attrs["end"],
+ attrs["length"],
+ )
+
return mem_dict
- def get_mod_mem_usage_dict(self):
+ @property
+ def footprint(self) -> Dict[str, Region]:
+ return self._footprint
+
+ def get_mod_mem_usage_dict(self) -> Dict[str, int]:
"""Get the total memory consumed by the module, this combines the
information in the memory configuration.
"""
diff --git a/tools/memory/src/memory/image.py b/tools/memory/src/memory/image.py
new file mode 100644
index 0000000..cda1d8a
--- /dev/null
+++ b/tools/memory/src/memory/image.py
@@ -0,0 +1,77 @@
+#
+# Copyright (c) 2023-2025, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+from abc import ABC, abstractmethod
+from dataclasses import dataclass
+from typing import Dict, Optional
+
+
+@dataclass
+class Region:
+ """Represents a memory region."""
+
+ start: Optional[int] = None
+ """Memory address of the beginning of the region."""
+
+ end: Optional[int] = None
+ """Memory address of the end of the region."""
+
+ length: Optional[int] = None
+ """Current size of the region in bytes."""
+
+ @property
+ def limit(self) -> Optional[int]:
+ """Largest possible end memory address of the region."""
+
+ if self.start is None:
+ return None
+
+ if self.length is None:
+ return None
+
+ return self.start + self.length
+
+ @property
+ def size(self) -> Optional[int]:
+ """Maximum possible size of the region in bytes."""
+
+ if self.end is None:
+ return None
+
+ if self.start is None:
+ return None
+
+ return self.end - self.start
+
+ @property
+ def free(self) -> Optional[int]:
+ """Number of bytes that the region is permitted to further expand."""
+
+ if self.limit is None:
+ return None
+
+ if self.end is None:
+ return None
+
+ return self.limit - self.end
+
+
+class Image(ABC):
+ """An image under analysis."""
+
+ @property
+ @abstractmethod
+ def footprint(self) -> Dict[str, Region]:
+ """Get metrics about the memory regions that this image occupies."""
+
+ pass
+
+ @property
+ @abstractmethod
+ def symbols(self) -> Dict[str, int]:
+ """Get a dictionary of the image's symbols and their corresponding addresses."""
+
+ pass
diff --git a/tools/memory/src/memory/mapparser.py b/tools/memory/src/memory/mapparser.py
index 1c28e71..24ee264 100644
--- a/tools/memory/src/memory/mapparser.py
+++ b/tools/memory/src/memory/mapparser.py
@@ -4,11 +4,14 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+from collections import defaultdict
from re import match, search
-from typing import TextIO
+from typing import Dict, TextIO
+
+from memory.image import Image, Region
-class TfaMapParser:
+class TfaMapParser(Image):
"""A class representing a map file built for TF-A.
Provides a basic interface for reading the symbol table. The constructor
@@ -16,17 +19,31 @@
are supported at this stage.
"""
- def __init__(self, map_file: TextIO):
- self._symbols = self.read_symbols(map_file)
+ def __init__(self, map_file: TextIO) -> None:
+ self._symbols: Dict[str, int] = self.read_symbols(map_file)
+ assert self._symbols, "Symbol table is empty!"
+
+ self._footprint: Dict[str, Region] = defaultdict(Region)
+
+ expr = r".*(.?R.M)_REGION.*(START|END|LENGTH)"
+ for symbol in filter(lambda s: match(expr, s), self._symbols):
+ region, _, attr = symbol.lower().strip("__").split("_")
+
+ if attr == "start":
+ self._footprint[region].start = self._symbols[symbol]
+ elif attr == "end":
+ self._footprint[region].end = self._symbols[symbol]
+ if attr == "length":
+ self._footprint[region].length = self._symbols[symbol]
@property
- def symbols(self):
- return self._symbols.items()
+ def symbols(self) -> Dict[str, int]:
+ return self._symbols
@staticmethod
- def read_symbols(file: TextIO, pattern: str = None) -> dict:
- pattern = r"\b(0x\w*)\s*(\w*)\s=" if not pattern else pattern
- symbols = {}
+ def read_symbols(file: TextIO) -> Dict[str, int]:
+ pattern = r"\b(0x\w*)\s*(\w*)\s="
+ symbols: Dict[str, int] = {}
for line in file.readlines():
match = search(pattern, line)
@@ -37,39 +54,6 @@
return symbols
- def get_memory_layout(self) -> dict:
- """Get the total memory consumed by this module from the memory
- configuration.
- {"rom": {"start": 0x0, "end": 0xFF, "length": ... }
- """
- assert len(self._symbols), "Symbol table is empty!"
- expr = r".*(.?R.M)_REGION.*(START|END|LENGTH)"
- memory_layout = {}
-
- region_symbols = filter(lambda s: match(expr, s), self._symbols)
-
- for symbol in region_symbols:
- region, _, attr = tuple(symbol.lower().strip("__").split("_"))
- if region not in memory_layout:
- memory_layout[region] = {}
-
- memory_layout[region][attr] = self._symbols[symbol]
-
- if "start" and "length" and "end" in memory_layout[region]:
- memory_layout[region]["limit"] = (
- memory_layout[region]["start"]
- + memory_layout[region]["length"]
- )
- memory_layout[region]["free"] = (
- memory_layout[region]["limit"]
- - memory_layout[region]["end"]
- )
- memory_layout[region]["total"] = memory_layout[region][
- "length"
- ]
- memory_layout[region]["size"] = (
- memory_layout[region]["end"]
- - memory_layout[region]["start"]
- )
-
- return memory_layout
+ @property
+ def footprint(self) -> Dict[str, Region]:
+ return self._footprint
diff --git a/tools/memory/src/memory/memmap.py b/tools/memory/src/memory/memmap.py
index f46db8c..e02010b 100755
--- a/tools/memory/src/memory/memmap.py
+++ b/tools/memory/src/memory/memmap.py
@@ -1,19 +1,32 @@
-#!/usr/bin/env python3
-
#
# Copyright (c) 2023-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
+import re
+import shutil
+from dataclasses import dataclass
from pathlib import Path
+from typing import Any, Dict, List, Optional
import click
-from memory.buildparser import TfaBuildParser
+
+from memory.elfparser import TfaElfParser
+from memory.image import Image
+from memory.mapparser import TfaMapParser
from memory.printer import TfaPrettyPrinter
+from memory.summary import MapParser
-@click.command()
+@dataclass
+class Context:
+ build_path: Optional[Path] = None
+ printer: Optional[TfaPrettyPrinter] = None
+
+
+@click.group()
+@click.pass_obj
@click.option(
"-r",
"--root",
@@ -36,75 +49,171 @@
type=click.Choice(["debug", "release"], case_sensitive=False),
)
@click.option(
- "-f",
- "--footprint",
- is_flag=True,
- show_default=True,
- help="Generate a high level view of memory usage by memory types.",
+ "-w",
+ "--width",
+ type=int,
+ default=shutil.get_terminal_size().columns,
+ help="Column width for printing.",
)
@click.option(
- "-t",
- "--tree",
- is_flag=True,
- help="Generate a hierarchical view of the modules, segments and sections.",
-)
-@click.option(
- "--depth",
- default=3,
- help="Generate a virtual address map of important TF symbols.",
-)
-@click.option(
- "-s",
- "--symbols",
- is_flag=True,
- help="Generate a map of important TF symbols.",
-)
-@click.option("-w", "--width", type=int, envvar="COLUMNS")
-@click.option(
"-d",
is_flag=True,
default=False,
help="Display numbers in decimal base.",
)
+def cli(
+ obj: Context,
+ root: Optional[Path],
+ platform: str,
+ build_type: str,
+ width: int,
+ d: bool,
+):
+ obj.build_path = root if root is not None else Path("build", platform, build_type)
+ click.echo(f"build-path: {obj.build_path.resolve()}")
+
+ obj.printer = TfaPrettyPrinter(columns=width, as_decimal=d)
+
+
+@cli.command()
+@click.pass_obj
@click.option(
"--no-elf-images",
is_flag=True,
help="Analyse the build's map files instead of ELF images.",
)
-def main(
- root: Path,
- platform: str,
- build_type: str,
- footprint: str,
- tree: bool,
- symbols: bool,
- depth: int,
- width: int,
- d: bool,
- no_elf_images: bool,
-):
- build_path = root if root else Path("build/", platform, build_type)
- click.echo(f"build-path: {build_path.resolve()}")
+def footprint(obj: Context, no_elf_images: bool):
+ """Generate a high level view of memory usage by memory types."""
- parser = TfaBuildParser(build_path, map_backend=no_elf_images)
- printer = TfaPrettyPrinter(columns=width, as_decimal=d)
+ assert obj.build_path is not None
+ assert obj.printer is not None
- if footprint or not (tree or symbols):
- printer.print_footprint(parser.get_mem_usage_dict())
+ elf_image_paths: List[Path] = (
+ [] if no_elf_images else list(obj.build_path.glob("**/*.elf"))
+ )
- if tree:
- printer.print_mem_tree(
- parser.get_mem_tree_as_dict(), parser.module_names, depth=depth
- )
+ map_file_paths: List[Path] = (
+ [] if not no_elf_images else list(obj.build_path.glob("**/*.map"))
+ )
- if symbols:
- expr = (
- r"(.*)(TEXT|BSS|RO|RODATA|STACKS|_OPS|PMF|XLAT|GOT|FCONF|RELA"
- r"|R.M)(.*)(START|UNALIGNED|END)__$"
- )
- printer.print_symbol_table(
- parser.filter_symbols(parser.symbols, expr), parser.module_names
- )
+ images: Dict[str, Image] = dict()
+
+ for elf_image_path in elf_image_paths:
+ with open(elf_image_path, "rb") as elf_image_io:
+ images[elf_image_path.stem.upper()] = TfaElfParser(elf_image_io)
+
+ for map_file_path in map_file_paths:
+ with open(map_file_path, "r") as map_file_io:
+ images[map_file_path.stem.upper()] = TfaMapParser(map_file_io)
+
+ obj.printer.print_footprint({k: v.footprint for k, v in images.items()})
+
+
+@cli.command()
+@click.pass_obj
+@click.option(
+ "--depth",
+ default=3,
+ show_default=True,
+ help="Generate a virtual address map of important TF symbols.",
+)
+def tree(obj: Context, depth: int):
+ """Generate a hierarchical view of the modules, segments and sections."""
+
+ assert obj.build_path is not None
+ assert obj.printer is not None
+
+ paths: List[Path] = list(obj.build_path.glob("**/*.elf"))
+ images: Dict[str, TfaElfParser] = dict()
+
+ for path in paths:
+ with open(path, "rb") as io:
+ images[path.stem] = TfaElfParser(io)
+
+ mtree: Dict[str, Dict[str, Any]] = {
+ k: {
+ "name": k,
+ **v.get_mod_mem_usage_dict(),
+ **{"children": v.get_seg_map_as_dict()},
+ }
+ for k, v in images.items()
+ }
+
+ obj.printer.print_mem_tree(mtree, list(mtree.keys()), depth=depth)
+
+
+@cli.command()
+@click.pass_obj
+@click.option(
+ "--no-elf-images",
+ is_flag=True,
+ help="Analyse the build's map files instead of ELF images.",
+)
+def symbols(obj: Context, no_elf_images: bool):
+ """Generate a map of important TF symbols."""
+
+ assert obj.build_path is not None
+ assert obj.printer is not None
+
+ expr: str = (
+ r"(.*)(TEXT|BSS|RO|RODATA|STACKS|_OPS|PMF|XLAT|GOT|FCONF|RELA"
+ r"|R.M)(.*)(START|UNALIGNED|END)__$"
+ )
+
+ elf_image_paths: List[Path] = (
+ [] if no_elf_images else list(obj.build_path.glob("**/*.elf"))
+ )
+
+ map_file_paths: List[Path] = (
+ [] if not no_elf_images else list(obj.build_path.glob("**/*.map"))
+ )
+
+ images: Dict[str, Image] = dict()
+
+ for elf_image_path in elf_image_paths:
+ with open(elf_image_path, "rb") as elf_image_io:
+ images[elf_image_path.stem] = TfaElfParser(elf_image_io)
+
+ for map_file_path in map_file_paths:
+ with open(map_file_path, "r") as map_file_io:
+ images[map_file_path.stem] = TfaMapParser(map_file_io)
+
+ symbols = {k: v.symbols for k, v in images.items()}
+ symbols = {
+ image: {
+ symbol: symbol_value
+ for symbol, symbol_value in symbols.items()
+ if re.match(expr, symbol)
+ }
+ for image, symbols in symbols.items()
+ }
+
+ obj.printer.print_symbol_table(symbols, list(images.keys()))
+
+
+@cli.command()
+@click.option("-o", "--old", type=click.Path(exists=True))
+@click.option("-d", "--depth", type=int, default=2)
+@click.option("-e", "--exclude-fill")
+@click.option(
+ "-t",
+ "--type",
+ type=click.Choice(MapParser.export_formats, case_sensitive=False),
+ default="table",
+)
+@click.argument("file", type=click.Path(exists=True))
+def summary(file: Path, old: Optional[Path], depth: int, exclude_fill: bool, type: str):
+ """Summarize the sizes of translation units within the resulting binary"""
+ memap = MapParser()
+
+ if not memap.parse(file, old, exclude_fill):
+ exit(1)
+
+ memap.generate_output(type, depth)
+
+
+def main():
+ cli(obj=Context())
if __name__ == "__main__":
diff --git a/tools/memory/src/memory/printer.py b/tools/memory/src/memory/printer.py
index f797139..6debf53 100755
--- a/tools/memory/src/memory/printer.py
+++ b/tools/memory/src/memory/printer.py
@@ -4,10 +4,14 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+from typing import Any, Dict, List, Optional, Tuple
+
from anytree import RenderTree
from anytree.importer import DictImporter
from prettytable import PrettyTable
+from memory.image import Region
+
class TfaPrettyPrinter:
"""A class for printing the memory layout of ELF files.
@@ -17,19 +21,29 @@
structured and consumed.
"""
- def __init__(self, columns: int = None, as_decimal: bool = False):
- self.term_size = columns if columns and columns > 120 else 120
- self._tree = None
- self._footprint = None
- self._symbol_map = None
- self.as_decimal = as_decimal
+ def __init__(self, columns: int, as_decimal: bool = False) -> None:
+ self.term_size: int = columns
+ self._tree: Optional[List[str]] = None
+ self._symbol_map: Optional[List[str]] = None
+ self.as_decimal: bool = as_decimal
- def format_args(self, *args, width=10, fmt=None):
- if not fmt and type(args[0]) is int:
+ def format_args(
+ self,
+ *args: Any,
+ width: int = 10,
+ fmt: Optional[str] = None,
+ ) -> List[str]:
+ if not fmt and isinstance(args[0], int):
fmt = f">{width}x" if not self.as_decimal else f">{width}"
- return [f"{arg:{fmt}}" if fmt else arg for arg in args]
+ return [f"{arg:{fmt}}" if fmt else str(arg) for arg in args]
- def format_row(self, leading, *args, width=10, fmt=None):
+ def format_row(
+ self,
+ leading: str,
+ *args: Any,
+ width: int = 10,
+ fmt: Optional[str] = None,
+ ) -> str:
formatted_args = self.format_args(*args, width=width, fmt=fmt)
return leading + " ".join(formatted_args)
@@ -39,9 +53,9 @@
section_name: str,
rel_pos: int,
columns: int,
- width: int = None,
+ width: int,
is_edge: bool = False,
- ):
+ ) -> str:
empty_col = "{:{}{}}"
# Some symbols are longer than the column width, truncate them until
@@ -50,28 +64,26 @@
if len_over > 0:
section_name = section_name[len_over:-len_over]
- sec_row = f"+{section_name:-^{width-1}}+"
+ sec_row = f"+{section_name:-^{width - 1}}+"
sep, fill = ("+", "-") if is_edge else ("|", "")
sec_row_l = empty_col.format(sep, fill + "<", width) * rel_pos
- sec_row_r = empty_col.format(sep, fill + ">", width) * (
- columns - rel_pos - 1
- )
+ sec_row_r = empty_col.format(sep, fill + ">", width) * (columns - rel_pos - 1)
return leading + sec_row_l + sec_row + sec_row_r
def print_footprint(
- self, app_mem_usage: dict, sort_key: str = None, fields: list = None
+ self,
+ app_mem_usage: Dict[str, Dict[str, Region]],
):
- assert len(app_mem_usage), "Empty memory layout dictionary!"
- if not fields:
- fields = ["Component", "Start", "Limit", "Size", "Free", "Total"]
+ assert app_mem_usage, "Empty memory layout dictionary!"
- sort_key = fields[0] if not sort_key else sort_key
+ fields = ["Component", "Start", "Limit", "Size", "Free", "Total"]
+ sort_key = fields[0]
# Iterate through all the memory types, create a table for each
# type, rows represent a single module.
- for mem in sorted(set(k for _, v in app_mem_usage.items() for k in v)):
+ for mem in sorted({k for v in app_mem_usage.values() for k in v}):
table = PrettyTable(
sortby=sort_key,
title=f"Memory Usage (bytes) [{mem.upper()}]",
@@ -79,13 +91,19 @@
)
for mod, vals in app_mem_usage.items():
- if mem in vals.keys():
+ if mem in vals:
val = vals[mem]
table.add_row(
[
- mod.upper(),
+ mod,
*self.format_args(
- *[val[k.lower()] for k in fields[1:]]
+ *[
+ val.start if val.start is not None else "?",
+ val.limit if val.limit is not None else "?",
+ val.size if val.size is not None else "?",
+ val.free if val.free is not None else "?",
+ val.length if val.length is not None else "?",
+ ]
),
]
)
@@ -93,31 +111,34 @@
def print_symbol_table(
self,
- symbols: list,
- modules: list,
+ symbol_table: Dict[str, Dict[str, int]],
+ modules: List[str],
start: int = 12,
- ):
- assert len(symbols), "Empty symbol list!"
+ ) -> None:
+ assert len(symbol_table), "Empty symbol list!"
modules = sorted(modules)
- col_width = int((self.term_size - start) / len(modules))
+ col_width = (self.term_size - start) // len(modules)
address_fixed_width = 11
- num_fmt = (
- f"0=#0{address_fixed_width}x" if not self.as_decimal else ">10"
- )
+ num_fmt = f"0=#0{address_fixed_width}x" if not self.as_decimal else ">10"
_symbol_map = [
- " " * start
- + "".join(self.format_args(*modules, fmt=f"^{col_width}"))
+ " " * start + "".join(self.format_args(*modules, fmt=f"^{col_width}"))
]
last_addr = None
- for i, (name, addr, mod) in enumerate(symbols):
+ symbols_list: List[Tuple[str, int, str]] = [
+ (name, addr, mod)
+ for mod, syms in symbol_table.items()
+ for name, addr in syms.items()
+ ]
+
+ symbols_list.sort(key=lambda x: (-x[1], x[0]), reverse=True)
+
+ for i, (name, addr, mod) in enumerate(symbols_list):
# Do not print out an address twice if two symbols overlap,
# for example, at the end of one region and start of another.
- leading = (
- f"{addr:{num_fmt}}" + " " if addr != last_addr else " " * start
- )
+ leading = f"{addr:{num_fmt}}" + " " if addr != last_addr else " " * start
_symbol_map.append(
self.map_elf_symbol(
@@ -125,28 +146,30 @@
name,
modules.index(mod),
len(modules),
- width=col_width,
- is_edge=(not i or i == len(symbols) - 1),
+ col_width,
+ is_edge=(i == 0 or i == len(symbols_list) - 1),
)
)
last_addr = addr
- self._symbol_map = ["Memory Layout:"]
- self._symbol_map += list(reversed(_symbol_map))
+ self._symbol_map = ["Memory Layout:"] + list(reversed(_symbol_map))
print("\n".join(self._symbol_map))
def print_mem_tree(
- self, mem_map_dict, modules, depth=1, min_pad=12, node_right_pad=12
- ):
+ self,
+ mem_map_dict: Dict[str, Any],
+ modules: List[str],
+ depth: int = 1,
+ min_pad: int = 12,
+ node_right_pad: int = 12,
+ ) -> None:
# Start column should have some padding between itself and its data
# values.
anchor = min_pad + node_right_pad * (depth - 1)
headers = ["start", "end", "size"]
- self._tree = [
- (f"{'name':<{anchor}}" + " ".join(f"{arg:>10}" for arg in headers))
- ]
+ self._tree = [f"{'name':<{anchor}}" + " ".join(f"{arg:>10}" for arg in headers)]
for mod in sorted(modules):
root = DictImporter().import_(mem_map_dict[mod])
diff --git a/tools/memory/src/memory/summary.py b/tools/memory/src/memory/summary.py
new file mode 100644
index 0000000..b116caa
--- /dev/null
+++ b/tools/memory/src/memory/summary.py
@@ -0,0 +1,557 @@
+#
+# Copyright (c) 2016-2025, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+import json
+import os
+import re
+from collections import defaultdict
+from copy import deepcopy
+from os.path import (
+ abspath,
+ basename,
+ commonprefix,
+ dirname,
+ join,
+ relpath,
+ splitext,
+)
+from pathlib import Path
+from sys import stdout
+from typing import IO, Any, Dict, List, Optional, Pattern, Tuple, Union
+
+from jinja2 import FileSystemLoader, StrictUndefined
+from jinja2.environment import Environment
+from prettytable import HEADER, PrettyTable
+
+ModuleStats = Dict[str, int]
+Modules = Dict[str, ModuleStats]
+
+SECTIONS: Tuple[str, ...] = (".text", ".data", ".bss", ".heap", ".stack")
+MISC_FLASH_SECTIONS: Tuple[str, ...] = (".interrupts", ".flash_config")
+OTHER_SECTIONS: Tuple[str, ...] = (
+ ".interrupts_ram",
+ ".init",
+ ".ARM.extab",
+ ".ARM.exidx",
+ ".ARM.attributes",
+ ".eh_frame",
+ ".init_array",
+ ".fini_array",
+ ".jcr",
+ ".stab",
+ ".stabstr",
+ ".ARM.exidx",
+ ".ARM",
+)
+ALL_SECTIONS: Tuple[str, ...] = (
+ SECTIONS + OTHER_SECTIONS + MISC_FLASH_SECTIONS + ("unknown", "OUTPUT")
+)
+
+
+class Parser:
+ """Internal interface for parsing"""
+
+ _RE_OBJECT_FILE: Pattern[str] = re.compile(r"^(.+\/.+\.o(bj)?)$")
+ _RE_LIBRARY_OBJECT: Pattern[str] = re.compile(
+ r"((^.+" + r"" + r"lib.+\.a)\((.+\.o(bj)?)\))$"
+ )
+ _RE_STD_SECTION: Pattern[str] = re.compile(r"^\s+.*0x(\w{8,16})\s+0x(\w+)\s(.+)$")
+ _RE_FILL_SECTION: Pattern[str] = re.compile(
+ r"^\s*\*fill\*\s+0x(\w{8,16})\s+0x(\w+).*$"
+ )
+ _RE_TRANS_FILE: Pattern[str] = re.compile(r"^(.+\/|.+\.ltrans.o(bj)?)$")
+ _OBJECT_EXTENSIONS: Tuple[str, ...] = (".o", ".obj")
+
+ _modules: Modules
+ _fill: bool
+
+ def __init__(self, fill: bool = True):
+ self._modules: Modules = {}
+ self._fill = fill
+
+ def module_add(self, object_name: str, size: int, section: str):
+ """Adds a module or section to the list
+
+ Positional arguments:
+ object_name - name of the entry to add
+ size - the size of the module being added
+ section - the section the module contributes to
+ """
+ if (
+ not object_name
+ or not size
+ or not section
+ or (not self._fill and object_name == "[fill]")
+ ):
+ return
+
+ if object_name in self._modules:
+ self._modules[object_name].setdefault(section, 0)
+ self._modules[object_name][section] += size
+ return
+
+ obj_split = os.sep + basename(object_name)
+ for module_path, contents in self._modules.items():
+ if module_path.endswith(obj_split) or module_path == object_name:
+ contents.setdefault(section, 0)
+ contents[section] += size
+ return
+
+ new_module: ModuleStats = defaultdict(int)
+ new_module[section] = size
+ self._modules[object_name] = new_module
+
+ def module_replace(self, old_object: str, new_object: str):
+ """Replaces an object name with a new one"""
+ if old_object in self._modules:
+ self._modules[new_object] = self._modules.pop(old_object)
+
+ def check_new_section(self, line: str) -> Optional[str]:
+ """Check whether a new section in a map file has been detected
+
+ Positional arguments:
+ line - the line to check for a new section
+
+ return value - A section name, if a new section was found, None
+ otherwise
+ """
+ line_s = line.strip()
+ for i in ALL_SECTIONS:
+ if line_s.startswith(i):
+ return i
+ if line.startswith("."):
+ return "unknown"
+ else:
+ return None
+
+ def parse_object_name(self, line: str) -> str:
+ """Parse a path to object file
+
+ Positional arguments:
+ line - the path to parse the object and module name from
+
+ return value - an object file name
+ """
+ if re.match(self._RE_TRANS_FILE, line):
+ return "[misc]"
+
+ test_re_file_name = re.match(self._RE_OBJECT_FILE, line)
+
+ if test_re_file_name:
+ object_name = test_re_file_name.group(1)
+
+ return object_name
+ else:
+ test_re_obj_name = re.match(self._RE_LIBRARY_OBJECT, line)
+
+ if test_re_obj_name:
+ return join(test_re_obj_name.group(2), test_re_obj_name.group(3))
+ else:
+ if not line.startswith("LONG") and not line.startswith("linker stubs"):
+ print("Unknown object name found in GCC map file: %s" % line)
+ return "[misc]"
+
+ def parse_section(self, line: str) -> Tuple[str, int]:
+ """Parse data from a section of gcc map file
+
+ examples:
+ 0x00004308 0x7c ./BUILD/K64F/GCC_ARM/spi_api.o
+ .text 0x00000608 0x198 ./BUILD/K64F/HAL_CM4.o
+
+ Positional arguments:
+ line - the line to parse a section from
+ """
+ is_fill = re.match(self._RE_FILL_SECTION, line)
+ if is_fill:
+ o_name: str = "[fill]"
+ o_size: int = int(is_fill.group(2), 16)
+ return o_name, o_size
+
+ is_section = re.match(self._RE_STD_SECTION, line)
+ if is_section:
+ o_size: int = int(is_section.group(2), 16)
+ if o_size:
+ o_name: str = self.parse_object_name(is_section.group(3))
+ return o_name, o_size
+
+ return "", 0
+
+ def parse_mapfile(self, file_desc: IO[str]) -> Modules:
+ """Main logic to decode gcc map files
+
+ Positional arguments:
+ file_desc - a stream object to parse as a gcc map file
+ """
+ current_section: str = "unknown"
+
+ with file_desc as infile:
+ for line in infile:
+ if line.startswith("Linker script and memory map"):
+ current_section = "unknown"
+ break
+
+ for line in infile:
+ next_section = self.check_new_section(line)
+
+ if next_section == "OUTPUT":
+ break
+ elif next_section:
+ current_section = next_section
+
+ object_name, object_size = self.parse_section(line)
+ self.module_add(object_name, object_size, current_section)
+
+ def is_obj(name: str) -> bool:
+ return not name.startswith("[") or not name.endswith("]")
+
+ common_prefix: str = dirname(
+ commonprefix([o for o in self._modules.keys() if is_obj(o)])
+ )
+ new_modules: Modules = {}
+ for name, stats in self._modules.items():
+ if is_obj(name):
+ new_modules[relpath(name, common_prefix)] = stats
+ else:
+ new_modules[name] = stats
+ return new_modules
+
+
+class MapParser(object):
+ """An object that represents parsed results, parses the memory map files,
+ and writes out different file types of memory results
+ """
+
+ print_sections: Tuple[str, ...] = (".text", ".data", ".bss")
+ delta_sections: Tuple[str, ...] = (".text-delta", ".data-delta", ".bss-delta")
+
+ # sections to print info (generic for all toolchains)
+ sections: Tuple[str, ...] = SECTIONS
+ misc_flash_sections: Tuple[str, ...] = MISC_FLASH_SECTIONS
+ other_sections: Tuple[str, ...] = OTHER_SECTIONS
+
+ modules: Modules
+ old_modules: Modules
+ short_modules: Modules
+ mem_report: List[Dict[str, Union[str, ModuleStats]]]
+ mem_summary: Dict[str, int]
+ subtotal: Dict[str, int]
+ tc_name: Optional[str]
+
+ RAM_FORMAT_STR: str = "Total Static RAM memory (data + bss): {}({:+}) bytes\n"
+ ROM_FORMAT_STR: str = "Total Flash memory (text + data): {}({:+}) bytes\n"
+
+ def __init__(self):
+ # list of all modules and their sections
+ # full list - doesn't change with depth
+ self.modules: Modules = {}
+ self.old_modules = {}
+ # short version with specific depth
+ self.short_modules: Modules = {}
+
+ # Memory report (sections + summary)
+ self.mem_report: List[Dict[str, Union[str, ModuleStats]]] = []
+
+ # Memory summary
+ self.mem_summary: Dict[str, int] = {}
+
+ # Totals of ".text", ".data" and ".bss"
+ self.subtotal: Dict[str, int] = {}
+
+ # Name of the toolchain, for better headings
+ self.tc_name = None
+
+ def reduce_depth(self, depth: Optional[int]):
+ """
+ populates the short_modules attribute with a truncated module list
+
+ (1) depth = 1:
+ main.o
+ mbed-os
+
+ (2) depth = 2:
+ main.o
+ mbed-os/test.o
+ mbed-os/drivers
+
+ """
+ if depth == 0 or depth is None:
+ self.short_modules = deepcopy(self.modules)
+ else:
+ self.short_modules = dict()
+ for module_name, v in self.modules.items():
+ split_name = module_name.split(os.sep)
+ if split_name[0] == "":
+ split_name = split_name[1:]
+ new_name = join(*split_name[:depth])
+ self.short_modules.setdefault(new_name, defaultdict(int))
+ for section_idx, value in v.items():
+ self.short_modules[new_name][section_idx] += value
+ delta_name = section_idx + "-delta"
+ self.short_modules[new_name][delta_name] += value
+
+ for module_name, v in self.old_modules.items():
+ split_name = module_name.split(os.sep)
+ if split_name[0] == "":
+ split_name = split_name[1:]
+ new_name = join(*split_name[:depth])
+ self.short_modules.setdefault(new_name, defaultdict(int))
+ for section_idx, value in v.items():
+ delta_name = section_idx + "-delta"
+ self.short_modules[new_name][delta_name] -= value
+
+ export_formats: List[str] = ["json", "html", "table"]
+
+ def generate_output(
+ self,
+ export_format: str,
+ depth: Optional[int],
+ file_output: Optional[str] = None,
+ ) -> Optional[bool]:
+ """Generates summary of memory map data
+
+ Positional arguments:
+ export_format - the format to dump
+
+ Keyword arguments:
+ file_desc - descriptor (either stdout or file)
+ depth - directory depth on report
+
+ Returns: generated string for the 'table' format, otherwise Nonef
+ """
+ if depth is None or depth > 0:
+ self.reduce_depth(depth)
+ self.compute_report()
+ try:
+ if file_output:
+ file_desc = open(file_output, "w")
+ else:
+ file_desc = stdout
+ except IOError as error:
+ print("I/O error({0}): {1}".format(error.errno, error.strerror))
+ return False
+
+ to_call = {
+ "json": self.generate_json,
+ "html": self.generate_html,
+ "table": self.generate_table,
+ }[export_format]
+ to_call(file_desc)
+
+ if file_desc is not stdout:
+ file_desc.close()
+
+ @staticmethod
+ def _move_up_tree(tree: Dict[str, Any], next_module: str) -> Dict[str, Any]:
+ tree.setdefault("children", [])
+ for child in tree["children"]:
+ if child["name"] == next_module:
+ return child
+
+ new_module = {"name": next_module, "value": 0, "delta": 0}
+ tree["children"].append(new_module)
+
+ return new_module
+
+ def generate_html(self, file_desc: IO[str]):
+ """Generate a json file from a memory map for D3
+
+ Positional arguments:
+ file_desc - the file to write out the final report to
+ """
+
+ tree_text = {"name": ".text", "value": 0, "delta": 0}
+ tree_bss = {"name": ".bss", "value": 0, "delta": 0}
+ tree_data = {"name": ".data", "value": 0, "delta": 0}
+
+ def accumulate(tree_root: Dict[str, Any], size_key: str, stats: ModuleStats):
+ parts = module_name.split(os.sep)
+
+ val = stats.get(size_key, 0)
+ tree_root["value"] += val
+ tree_root["delta"] += val
+
+ cur = tree_root
+ for part in parts:
+ cur = self._move_up_tree(cur, part)
+ cur["value"] += val
+ cur["delta"] += val
+
+ def subtract(tree_root: Dict[str, Any], size_key: str, stats: ModuleStats):
+ parts = module_name.split(os.sep)
+
+ cur = tree_root
+ cur["delta"] -= stats.get(size_key, 0)
+
+ for part in parts:
+ children = {c["name"]: c for c in cur.get("children", [])}
+ if part not in children:
+ return
+
+ cur = children[part]
+ cur["delta"] -= stats.get(size_key, 0)
+
+ for module_name, dct in self.modules.items():
+ accumulate(tree_text, ".text", dct)
+ accumulate(tree_data, ".data", dct)
+ accumulate(tree_bss, ".bss", dct)
+
+ for module_name, dct in self.old_modules.items():
+ subtract(tree_text, ".text", dct)
+ subtract(tree_data, ".data", dct)
+ subtract(tree_bss, ".bss", dct)
+
+ jinja_loader = FileSystemLoader(dirname(abspath(__file__)))
+ jinja_environment = Environment(loader=jinja_loader, undefined=StrictUndefined)
+ template = jinja_environment.get_template("templates/summary-flamegraph.html")
+
+ name, _ = splitext(basename(file_desc.name))
+
+ if name.endswith("_map"):
+ name = name[:-4]
+ if self.tc_name:
+ name = f"{name} {self.tc_name}"
+
+ file_desc.write(
+ template.render(
+ {
+ "name": name,
+ "rom": json.dumps(
+ {
+ "name": "ROM",
+ "value": tree_text["value"] + tree_data["value"],
+ "delta": tree_text["delta"] + tree_data["delta"],
+ "children": [tree_text, tree_data],
+ }
+ ),
+ "ram": json.dumps(
+ {
+ "name": "RAM",
+ "value": tree_bss["value"] + tree_data["value"],
+ "delta": tree_bss["delta"] + tree_data["delta"],
+ "children": [tree_bss, tree_data],
+ }
+ ),
+ }
+ )
+ )
+
+ def generate_json(self, file_desc: IO[str]):
+ """Generate a json file from a memory map
+
+ Positional arguments:
+ file_desc - the file to write out the final report to
+ """
+ file_desc.write(json.dumps(self.mem_report, indent=4))
+ file_desc.write("\n")
+
+ def generate_table(self, file_desc: IO[str]):
+ """Generate a table from a memory map
+
+ Returns: string of the generated table
+ """
+ # Create table
+ columns = ["Module"]
+ columns.extend(self.print_sections)
+
+ table = PrettyTable(columns, junction_char="|", hrules=HEADER)
+ table.align["Module"] = "l"
+
+ for col in self.print_sections:
+ table.align[col] = "r"
+
+ for i in sorted(self.short_modules):
+ row = [i]
+
+ for k in self.print_sections:
+ row.append(
+ "{}({:+})".format(
+ self.short_modules[i][k], self.short_modules[i][k + "-delta"]
+ )
+ )
+
+ table.add_row(row)
+
+ subtotal_row = ["Subtotals"]
+ for k in self.print_sections:
+ subtotal_row.append(
+ "{}({:+})".format(self.subtotal[k], self.subtotal[k + "-delta"])
+ )
+
+ table.add_row(subtotal_row)
+
+ output = table.get_string()
+ output += "\n"
+
+ output += self.RAM_FORMAT_STR.format(
+ self.mem_summary["static_ram"], self.mem_summary["static_ram_delta"]
+ )
+ output += self.ROM_FORMAT_STR.format(
+ self.mem_summary["total_flash"], self.mem_summary["total_flash_delta"]
+ )
+ file_desc.write(output)
+
+ def compute_report(self):
+ """Generates summary of memory usage for main areas"""
+ self.subtotal = defaultdict(int)
+
+ for mod in self.modules.values():
+ for k in self.sections:
+ self.subtotal[k] += mod[k]
+ self.subtotal[k + "-delta"] += mod[k]
+
+ for mod in self.old_modules.values():
+ for k in self.sections:
+ self.subtotal[k + "-delta"] -= mod[k]
+
+ self.mem_summary = {
+ "static_ram": self.subtotal[".data"] + self.subtotal[".bss"],
+ "static_ram_delta": self.subtotal[".data-delta"]
+ + self.subtotal[".bss-delta"],
+ "total_flash": (self.subtotal[".text"] + self.subtotal[".data"]),
+ "total_flash_delta": self.subtotal[".text-delta"]
+ + self.subtotal[".data-delta"],
+ }
+
+ self.mem_report = []
+ if self.short_modules:
+ for name, sizes in sorted(self.short_modules.items()):
+ self.mem_report.append(
+ {
+ "module": name,
+ "size": {
+ k: sizes.get(k, 0)
+ for k in (self.print_sections + self.delta_sections)
+ },
+ }
+ )
+
+ self.mem_report.append({"summary": self.mem_summary})
+
+ def parse(
+ self, mapfile: Path, oldfile: Optional[Path] = None, no_fill: bool = False
+ ) -> bool:
+ """Parse and decode map file depending on the toolchain
+
+ Positional arguments:
+ mapfile - the file name of the memory map file
+ toolchain - the toolchain used to create the file
+ """
+ try:
+ with open(mapfile, "r") as file_input:
+ self.modules = Parser(not no_fill).parse_mapfile(file_input)
+ try:
+ if oldfile is not None:
+ with open(oldfile, "r") as old_input:
+ self.old_modules = Parser(not no_fill).parse_mapfile(old_input)
+ else:
+ self.old_modules = self.modules
+ except IOError:
+ self.old_modules = {}
+ return True
+
+ except IOError as error:
+ print("I/O error({0}): {1}".format(error.errno, error.strerror))
+ return False
diff --git a/tools/memory/src/memory/templates/summary-flamegraph.html b/tools/memory/src/memory/templates/summary-flamegraph.html
new file mode 100644
index 0000000..9ec8ecb
--- /dev/null
+++ b/tools/memory/src/memory/templates/summary-flamegraph.html
@@ -0,0 +1,110 @@
+<!DOCTYPE html>
+<html lang="en">
+
+<head>
+ <meta charset="utf-8">
+ <meta http-equiv="X-UA-Compatible" content="IE=edge">
+ <meta name="viewport" content="width=device-width, initial-scale=1">
+
+ <link rel="stylesheet" type="text/css" href="https://maxcdn.bootstrapcdn.com/bootstrap/3.3.7/css/bootstrap.min.css"
+ integrity="sha256-916EbMg70RQy9LHiGkXzG8hSg9EdNy97GazNG/aiY1w=" crossorigin="anonymous" />
+ <link rel="stylesheet" type="text/css"
+ href="https://cdn.jsdelivr.net/gh/spiermar/d3-flame-graph@1.0.4/dist/d3.flameGraph.min.css"
+ integrity="sha256-w762vSe6WGrkVZ7gEOpnn2Y+FSmAGlX77jYj7nhuCyY=" crossorigin="anonymous" />
+
+ <style>
+ /* Space out content a bit */
+ body {
+ padding-top: 20px;
+ padding-bottom: 20px;
+ }
+
+ /* Custom page header */
+ .header {
+ padding-bottom: 20px;
+ padding-right: 15px;
+ padding-left: 15px;
+ border-bottom: 1px solid #e5e5e5;
+ }
+
+ /* Make the masthead heading the same height as the navigation */
+ .header h3 {
+ margin-top: 0;
+ margin-bottom: 0;
+ line-height: 40px;
+ }
+ </style>
+
+ <title>{{name}} Memory Details</title>
+</head>
+
+<body>
+ <div class="container">
+ <div class="header clearfix">
+ <h3 class="text-muted">{{name}} Memory Details</h3>
+ </div>
+ <div id="chart-rom">
+ </div>
+ <hr />
+ <div id="chart-ram">
+ </div>
+ <hr />
+ <div id="details"></div>
+ </div>
+
+ <script type="text/javascript" src="https://cdnjs.cloudflare.com/ajax/libs/d3/4.10.0/d3.min.js"
+ integrity="sha256-r7j1FXNTvPzHR41+V71Jvej6fIq4v4Kzu5ee7J/RitM=" crossorigin="anonymous">
+ </script>
+ <script type="text/javascript" src="https://cdnjs.cloudflare.com/ajax/libs/d3-tip/0.7.1/d3-tip.min.js"
+ integrity="sha256-z0A2CQF8xxCKuOJsn4sJ5HBjxiHHRAfTX8hDF4RSN5s=" crossorigin="anonymous">
+ </script>
+ <script type="text/javascript"
+ src="https://cdn.jsdelivr.net/gh/spiermar/d3-flame-graph@1.0.4/dist/d3.flameGraph.min.js"
+ integrity="sha256-I1CkrWbmjv+GWjgbulJ4i0vbzdrDGfxqdye2qNlhG3Q=" crossorigin="anonymous">
+ </script>
+
+ <script type="text/javascript">
+ var tip = d3.tip()
+ .direction("s")
+ .offset([8, 0])
+ .attr('class', 'd3-flame-graph-tip')
+ .html(function (d) { return "module: " + d.data.name + ", bytes: " + d.data.value + ", delta: " + d.data.delta; });
+ var colorizer = function (d) {
+ if (d.data.delta > 0) {
+ ratio = (d.data.value - d.data.delta) / d.data.value;
+ green = ("0" + (Number(ratio * 0xFF | 0).toString(16))).slice(-2).toUpperCase();
+ blue = ("0" + (Number(ratio * 0xEE | 0).toString(16))).slice(-2).toUpperCase();
+ console.log(d.data.name, green, blue);
+ return "#EE" + green + blue
+ } else if (d.data.delta < 0) {
+ ratio = (d.data.value + d.data.delta) / d.data.value;
+ green = ("0" + (Number(ratio * 0xFF | 0).toString(16))).slice(-2).toUpperCase();
+ red = ("0" + (Number(ratio * 0xFF | 0).toString(16))).slice(-2).toUpperCase();
+ console.log(d.data.name, red, green);
+ return "#" + red + green + "EE";
+ } else {
+ return "#FFFFEE";
+ }
+ }
+ var flameGraph_rom = d3.flameGraph()
+ .transitionDuration(250)
+ .transitionEase(d3.easeCubic)
+ .sort(true)
+ .color(colorizer)
+ .tooltip(tip);
+ var flameGraph_ram = d3.flameGraph()
+ .transitionDuration(250)
+ .transitionEase(d3.easeCubic)
+ .sort(true)
+ .color(colorizer)
+ .tooltip(tip);
+ var rom_elem = d3.select("#chart-rom");
+ flameGraph_rom.width(rom_elem.node().getBoundingClientRect().width);
+ rom_elem.datum({{ rom }}).call(flameGraph_rom);
+ var ram_elem = d3.select("#chart-ram");
+ flameGraph_ram.width(ram_elem.node().getBoundingClientRect().width);
+ ram_elem.datum({{ ram }}).call(flameGraph_ram);
+ </script>
+</body>
+
+</html>
diff --git a/tools/nxp/cert_create_helper/cert_create_tbbr.mk b/tools/nxp/cert_create_helper/cert_create_tbbr.mk
deleted file mode 100644
index e3b2e91..0000000
--- a/tools/nxp/cert_create_helper/cert_create_tbbr.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# Copyright 2021 NXP
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# Compile time defines used by NXP platforms
-
-PLAT_DEF_OID := yes
-
-ifeq (${PLAT_DEF_OID},yes)
-
-$(eval $(call add_define, PLAT_DEF_OID))
-$(eval $(call add_define, PDEF_KEYS))
-$(eval $(call add_define, PDEF_CERTS))
-$(eval $(call add_define, PDEF_EXTS))
-
-
-INC_DIR += -I../../plat/nxp/common/fip_handler/common/
-
-PDEF_CERT_TOOL_PATH := ../nxp/cert_create_helper
-PLAT_INCLUDE += -I${PDEF_CERT_TOOL_PATH}/include
-
-PLAT_OBJECTS += ${PDEF_CERT_TOOL_PATH}/src/pdef_tbb_cert.o \
- ${PDEF_CERT_TOOL_PATH}/src/pdef_tbb_ext.o \
- ${PDEF_CERT_TOOL_PATH}/src/pdef_tbb_key.o
-
-$(shell rm ${PLAT_OBJECTS})
-
-OBJECTS += ${PLAT_OBJECTS}
-endif
diff --git a/tools/sptool/sp_mk_generator.py b/tools/sptool/sp_mk_generator.py
index 9a00c74..3dd1d4e 100644
--- a/tools/sptool/sp_mk_generator.py
+++ b/tools/sptool/sp_mk_generator.py
@@ -1,5 +1,5 @@
#!/usr/bin/python3
-# Copyright (c) 2020-2024, Arm Limited. All rights reserved.
+# Copyright (c) 2020-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -156,7 +156,7 @@
def get_load_address(sp_layout, sp, args :dict):
''' Helper to fetch load-address from pm file listed in sp_layout.json'''
with open(get_sp_manifest_full_path(sp_layout[sp], args), "r") as pm_f:
- load_address_lines = [l for l in pm_f if 'load-address' in l]
+ load_address_lines = [l for l in pm_f if re.search(r'load-address[^-]', l)]
if len(load_address_lines) != 1:
return None
diff --git a/tools/stm32image/Makefile b/tools/stm32image/Makefile
index 64b6ccf..a89029e 100644
--- a/tools/stm32image/Makefile
+++ b/tools/stm32image/Makefile
@@ -6,36 +6,29 @@
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
+include ${MAKE_HELPERS_DIRECTORY}build-rules.mk
include ${MAKE_HELPERS_DIRECTORY}common.mk
include ${MAKE_HELPERS_DIRECTORY}toolchain.mk
-PROJECT := stm32image$(.exe)
-OBJECTS := stm32image.o
+STM32IMAGE_SOURCES := stm32image.c
-HOSTCCFLAGS := -Wall -Werror -pedantic -std=c99 -D_GNU_SOURCE
+STM32IMAGE_CFLAGS := -Wall -Werror -pedantic -std=c99
+STM32IMAGE_DEFINES := _GNU_SOURCE
ifeq (${DEBUG},1)
- HOSTCCFLAGS += -g -O0 -DDEBUG
+ STM32IMAGE_CFLAGS += -g -O0
+ STM32IMAGE_DEFINES += DEBUG
else
- HOSTCCFLAGS += -O2
+ STM32IMAGE_CFLAGS += -O2
endif
.PHONY: all clean distclean
-all: ${PROJECT}
+all:
-${PROJECT}: ${OBJECTS} Makefile
- $(s)echo " HOSTLD $@"
- $(q)$(host-cc) ${OBJECTS} -o $@
- $(s)echo
- $(s)echo "Built $@ successfully"
- $(s)echo
-
-%.o: %.c Makefile
- $(s)echo " HOSTCC $<"
- $(q)$(host-cc) -c ${HOSTCCFLAGS} $< -o $@
+$(eval $(call MAKE_TOOL,$(BUILD_PLAT)/tools,stm32image,STM32IMAGE))
clean:
- $(q)rm -rf $(PROJECT) $(OBJECTS)
+ $(q)rm -rf $(BUILD_PLAT)/tools/stm32image
distclean: clean