Fix the Cortex-A57 reset handler register usage
The CPU specific reset handlers no longer have the freedom
of using any general purpose register because it is being invoked
by the BL3-1 entry point in addition to BL1. The Cortex-A57 CPU
specific reset handler was overwriting x20 register which was being
used by the BL3-1 entry point to save the entry point information.
This patch fixes this bug by reworking the register allocation in the
Cortex-A57 reset handler to avoid using x20. The patch also
explicitly mentions the register clobber list for each of the
callee functions invoked by the reset handler
Change-Id: I28fcff8e742aeed883eaec8f6c4ee2bd3fce30df
diff --git a/docs/porting-guide.md b/docs/porting-guide.md
index a30535d..09cd7d5 100644
--- a/docs/porting-guide.md
+++ b/docs/porting-guide.md
@@ -491,8 +491,7 @@
A platform may need to do additional initialization after reset. This function
allows the platform to do the platform specific intializations. Platform
specific errata workarounds could also be implemented here. The api should
-preserve the value in x10 register as it is used by the caller to store the
-return address.
+preserve the values of callee saved registers x19 to x29.
The default implementation doesn't do anything. If a platform needs to override
the default implementation, refer to the [Firmware Design Guide] for general