Revert "Move architecture timer setup to platform-specific code"
This reverts commit 1c297bf015226c182b66498d5a64b8b51c7624f5
because it introduced a bug: the CNTFRQ_EL0 register was no
longer programmed by all CPUs. bl31_platform_setup() function
is invoked only in the cold boot path and consequently only
on the primary cpu.
A subsequent commit will correctly implement the necessary changes
to the counter frequency setup code.
Fixes ARM-software/tf-issues#125
Conflicts:
docs/firmware-design.md
plat/fvp/bl31_plat_setup.c
Change-Id: Ib584ad7ed069707ac04cf86717f836136ad3ab54
diff --git a/docs/firmware-design.md b/docs/firmware-design.md
index e92042d..2bf57ca 100644
--- a/docs/firmware-design.md
+++ b/docs/firmware-design.md
@@ -151,16 +151,19 @@
and Advanced SIMD execution are configured to not trap to EL3 by
clearing the `CPTR_EL3.TFP` bit.
+ - `CNTFRQ_EL0`. The `CNTFRQ_EL0` register is programmed with the base
+ frequency of the system counter, which is retrieved from the first entry
+ in the frequency modes table.
+
+ - Generic Timer. The system level implementation of the generic timer is
+ enabled through the memory mapped interface.
+
#### Platform initialization
-BL1 enables issuing of snoop and DVM (Distributed Virtual Memory) requests
-from the CCI-400 slave interface corresponding to the cluster that includes
-the primary CPU. BL1 also initializes UART0 (PL011 console), which enables
-access to the `printf` family of functions in BL1. The `CNTFRQ_EL0` register is
-programmed with the base frequency of the system counter, which is retrieved
-from the first entry in the frequency modes table. The system level
-implementation of the generic timer is enabled through the memory mapped
-interface.
+BL1 enables issuing of snoop and DVM (Distributed Virtual Memory) requests from
+the CCI-400 slave interface corresponding to the cluster that includes the
+primary CPU. BL1 also initializes UART0 (PL011 console), which enables access to
+the `printf` family of functions in BL1.
#### BL2 image load and execution
diff --git a/docs/porting-guide.md b/docs/porting-guide.md
index 6bba360..56467fb 100644
--- a/docs/porting-guide.md
+++ b/docs/porting-guide.md
@@ -446,9 +446,8 @@
for performing any remaining platform-specific setup that can occur after the
MMU and data cache have been enabled.
-In the ARM FVP port, this function enables system-level implementation of the
-generic timer counter. It also initializes counter frequency for CPU's generic
-timers.
+In the ARM FVP port, it zeros out the ZI section and enables the system level
+implementation of the generic timer counter.
This function is also responsible for initializing the storage abstraction layer
which is used to load further bootloader images.
@@ -772,7 +771,6 @@
The ARM FVP port does the following:
* Initializes the generic interrupt controller.
* Configures the CLCD controller.
-* Initializes counter frequency for CPU's generic timer
* Grants access to the system counter timer module
* Initializes the FVP power controller device
* Detects the system topology.