fix(cpus): workaround for Cortex-X4 erratum 3887999
Cortex-X4 erratum 3887999 is a Cat B erratum that applies
to all revisions <= r0p3 and is still open.
The erratum can be avoided by setting CPUACTLR2[22] to 1'b1 which will
disable linking multiple Non-Cacheable or Device GRE loads to the same
read request for the cache-line. This might have a significant
performance impact to Non-cacheable and Device GRE read bandwidth for
streaming scenarios
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2432808/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I851746b7b430eac85184c8d402d1aa5bb3c94a8e
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 71316ef..40aab4e 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -927,6 +927,10 @@
CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 and r0p3.
It is still open.
+- ``ERRATA_X4_3887999``: This applies errata 3887999 workaround to Cortex-X4
+ CPU. This needs to be enabled for revision r0p0, r0p1, r0p2 and r0p3.
+ It is still open.
+
For Cortex-X925, the following errata build flags are defined :
- ``ERRATA_X925_2963999``: This applies errata 2963999 workaround to Cortex-X925