fix(cpus): workaround for Cortex-X4 erratum 3887999
Cortex-X4 erratum 3887999 is a Cat B erratum that applies
to all revisions <= r0p3 and is still open.
The erratum can be avoided by setting CPUACTLR2[22] to 1'b1 which will
disable linking multiple Non-Cacheable or Device GRE loads to the same
read request for the cache-line. This might have a significant
performance impact to Non-cacheable and Device GRE read bandwidth for
streaming scenarios
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2432808/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I851746b7b430eac85184c8d402d1aa5bb3c94a8e
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 71316ef..40aab4e 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -927,6 +927,10 @@
CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 and r0p3.
It is still open.
+- ``ERRATA_X4_3887999``: This applies errata 3887999 workaround to Cortex-X4
+ CPU. This needs to be enabled for revision r0p0, r0p1, r0p2 and r0p3.
+ It is still open.
+
For Cortex-X925, the following errata build flags are defined :
- ``ERRATA_X925_2963999``: This applies errata 2963999 workaround to Cortex-X925
diff --git a/include/lib/cpus/aarch64/cortex_x4.h b/include/lib/cpus/aarch64/cortex_x4.h
index 8ef830a..6d89c95 100644
--- a/include/lib/cpus/aarch64/cortex_x4.h
+++ b/include/lib/cpus/aarch64/cortex_x4.h
@@ -27,6 +27,7 @@
* CPU Auxiliary control register specific definitions
******************************************************************************/
#define CORTEX_X4_CPUACTLR_EL1 S3_0_C15_C1_0
+#define CORTEX_X4_CPUACTLR2_EL1 S3_0_C15_C1_1
#define CORTEX_X4_CPUACTLR3_EL1 S3_0_C15_C1_2
#define CORTEX_X4_CPUACTLR4_EL1 S3_0_C15_C1_3
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index 260b012..f2e4243 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -120,6 +120,12 @@
check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3)
+workaround_reset_start cortex_x4, ERRATUM(3887999), ERRATA_X4_3887999
+ sysreg_bit_set CORTEX_X4_CPUACTLR2_EL1, BIT(22)
+workaround_reset_end cortex_x4, ERRATUM(3887999)
+
+check_erratum_ls cortex_x4, ERRATUM(3887999), CPU_REV(0, 3)
+
workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 77bdeed..92b605c 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -942,6 +942,10 @@
# of the Cortex-X4 cpu and is still open.
CPU_FLAG_LIST += ERRATA_X4_3701758
+# Flag to apply erratum 3887999 workaround on reset. This erratum applies to
+# revisions r0p0, r0p1, r0p2 and r0p3 of the Cortex-X4 cpu and is still open.
+CPU_FLAG_LIST += ERRATA_X4_3887999
+
# Flag to apply erratum 2963999 workaround during reset. This erratum applies
# to revisions r0p0 of the Cortex-X925 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_X925_2963999