fix(cpus): workaround for Cortex-X4 erratum 3133195
Cortex-X4 erratum 3133195 is a Cat B erratum that applies
to all revisions = r0p2 and is fixed in r0p3.
This erratum can be avoided by writing to a set of implementation
defined registers which will execute a PSB instruction following
the TSB CSYNC instruction.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2432808/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Id44daf950124e7c2d46cb5d6d6a1083d06fad12d
3 files changed