fix(cpus): workaround for Cortex-X4 erratum 3133195
Cortex-X4 erratum 3133195 is a Cat B erratum that applies
to all revisions = r0p2 and is fixed in r0p3.
This erratum can be avoided by writing to a set of implementation
defined registers which will execute a PSB instruction following
the TSB CSYNC instruction.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2432808/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Id44daf950124e7c2d46cb5d6d6a1083d06fad12d
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index be40d5d..71316ef 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -920,6 +920,9 @@
- ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
+- ``ERRATA_X4_3133195``: This applies errata 3133195 workaround to Cortex-X4
+ CPU. This needs to be enabled for revision r0p2. It is fixed in r0p3.
+
- ``ERRATA_X4_3701758``: This applies errata 3701758 workaround to Cortex-X4
CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 and r0p3.
It is still open.