feat(st-drivers): add RISAF driver
Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(through FCONF compliance) or statically.
The driver is enabled as BL2 sources. Add driver-related platform
services.
RISAF base addresses and key size are set in platform definitions.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iae99985e8db7cb2b27f9ca25669e74c8e08792d2
diff --git a/plat/st/stm32mp2/bl2_plat_setup.c b/plat/st/stm32mp2/bl2_plat_setup.c
index 1d49fe7..3b94989 100644
--- a/plat/st/stm32mp2/bl2_plat_setup.c
+++ b/plat/st/stm32mp2/bl2_plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -94,6 +94,10 @@
panic();
}
+ if (stm32mp2_risaf_init() < 0) {
+ panic();
+ }
+
/* Map DDR for binary load, now with cacheable attribute */
ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE);
diff --git a/plat/st/stm32mp2/include/stm32mp2_private.h b/plat/st/stm32mp2/include/stm32mp2_private.h
index 4bb8c52..fda2276 100644
--- a/plat/st/stm32mp2/include/stm32mp2_private.h
+++ b/plat/st/stm32mp2/include/stm32mp2_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,6 +11,21 @@
uint32_t stm32mp_syscfg_get_chip_dev_id(void);
+/* Get RISAF platform instance ID from peripheral IO memory base address */
+int stm32_risaf_get_instance(uintptr_t base);
+
+/* Get RISAF peripheral IO memory base address from platform instance ID */
+uintptr_t stm32_risaf_get_base(int instance);
+
+/* Get RISAF maximum number of regions from platform instance ID */
+int stm32_risaf_get_max_region(int instance);
+
+/* Get RISAF memory base address from platform instance ID */
+uintptr_t stm32_risaf_get_memory_base(int instance);
+
+/* Get RISAF memory size in bytes from platform instance ID */
+size_t stm32_risaf_get_memory_size(int instance);
+
/* Get DDRDBG peripheral IO memory base address */
uintptr_t stm32_ddrdbg_get_base(void);
diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
index a7cd991..5d6b0d3 100644
--- a/plat/st/stm32mp2/platform.mk
+++ b/plat/st/stm32mp2/platform.mk
@@ -215,6 +215,8 @@
BL2_SOURCES += drivers/st/crypto/stm32_hash.c
+BL2_SOURCES += drivers/st/rif/stm32mp2_risaf.c
+
ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),)
BL2_SOURCES += drivers/st/mmc/stm32_sdmmc2.c
endif
diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h
index 27fc5f9..e978b77 100644
--- a/plat/st/stm32mp2/stm32mp2_def.h
+++ b/plat/st/stm32mp2/stm32mp2_def.h
@@ -11,6 +11,7 @@
#ifndef __ASSEMBLER__
#include <drivers/st/bsec.h>
#include <drivers/st/stm32mp2_clk.h>
+#include <drivers/st/stm32mp2_risaf.h>
#endif
#if STM32MP21
#include <drivers/st/stm32mp21_pwr.h>
@@ -35,6 +36,7 @@
#include <dt-bindings/reset/stm32mp25-resets.h>
#endif /* STM32MP25 */
#include <dt-bindings/gpio/stm32-gpio.h>
+#include <dt-bindings/soc/rif.h>
#ifndef __ASSEMBLER__
#include <boot_api.h>
@@ -276,6 +278,13 @@
#define STM32MP_SDMMC3_BASE U(0x48240000)
/*******************************************************************************
+ * STM32MP2 OSPI
+ ******************************************************************************/
+/* OSPI 1 & 2 memory map area */
+#define STM32MP_OSPI_MM_BASE U(0x60000000)
+#define STM32MP_OSPI_MM_SIZE U(0x10000000)
+
+/*******************************************************************************
* STM32MP2 BSEC / OTP
******************************************************************************/
/*
@@ -413,9 +422,52 @@
/*******************************************************************************
* STM32MP RIF
******************************************************************************/
+#define RISAB1_BASE U(0x420F0000)
+#define RISAB2_BASE U(0x42100000)
#define RISAB3_BASE U(0x42110000)
#define RISAB5_BASE U(0x42130000)
+#define RISAF1_INST 0
+#define RISAF2_INST 1
+#define RISAF4_INST 3
+#define RISAF5_INST 4
+#define RISAF_MAX_INSTANCE 5
+
+#define RISAF1_BASE U(0x420A0000)
+#define RISAF2_BASE U(0x420B0000)
+#define RISAF4_BASE U(0x420D0000)
+#define RISAF5_BASE U(0x420E0000)
+
+#define USE_RISAF2
+#define USE_RISAF4
+
+#ifdef USE_RISAF1
+#define RISAF1_MAX_REGION 4
+#else
+#define RISAF1_MAX_REGION 0
+#endif
+#ifdef USE_RISAF2
+#define RISAF2_MAX_REGION 4
+#else
+#define RISAF2_MAX_REGION 0
+#endif
+#ifdef USE_RISAF4
+/* Consider only encrypted region maximum number, to save memory consumption */
+#define RISAF4_MAX_REGION 4
+#else
+#define RISAF4_MAX_REGION 0
+#endif
+#ifdef USE_RISAF5
+#define RISAF5_MAX_REGION 2
+#else
+#define RISAF5_MAX_REGION 0
+#endif
+#define RISAF_MAX_REGION (RISAF1_MAX_REGION + RISAF2_MAX_REGION + \
+ RISAF4_MAX_REGION + RISAF5_MAX_REGION)
+
+#define RISAF_KEY_SIZE_IN_BYTES RISAF_ENCRYPTION_KEY_SIZE_IN_BYTES
+#define RISAF_SEED_SIZE_IN_BYTES U(4)
+
/*******************************************************************************
* STM32MP CA35SSC
******************************************************************************/
diff --git a/plat/st/stm32mp2/stm32mp2_private.c b/plat/st/stm32mp2/stm32mp2_private.c
index ea9d2fc..2070cea 100644
--- a/plat/st/stm32mp2/stm32mp2_private.c
+++ b/plat/st/stm32mp2/stm32mp2_private.c
@@ -1,10 +1,11 @@
/*
- * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
+#include <errno.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
@@ -324,6 +325,66 @@
return false;
}
+int stm32_risaf_get_instance(uintptr_t base)
+{
+ switch (base) {
+ case RISAF2_BASE:
+ return (int)RISAF2_INST;
+ case RISAF4_BASE:
+ return (int)RISAF4_INST;
+ default:
+ return -ENODEV;
+ }
+}
+
+uintptr_t stm32_risaf_get_base(int instance)
+{
+ switch (instance) {
+ case RISAF2_INST:
+ return (uintptr_t)RISAF2_BASE;
+ case RISAF4_INST:
+ return (uintptr_t)RISAF4_BASE;
+ default:
+ return 0U;
+ }
+}
+
+int stm32_risaf_get_max_region(int instance)
+{
+ switch (instance) {
+ case RISAF2_INST:
+ return (int)RISAF2_MAX_REGION;
+ case RISAF4_INST:
+ return (int)RISAF4_MAX_REGION;
+ default:
+ return 0;
+ }
+}
+
+uintptr_t stm32_risaf_get_memory_base(int instance)
+{
+ switch (instance) {
+ case RISAF2_INST:
+ return (uintptr_t)STM32MP_OSPI_MM_BASE;
+ case RISAF4_INST:
+ return (uintptr_t)STM32MP_DDR_BASE;
+ default:
+ return 0U;
+ }
+}
+
+size_t stm32_risaf_get_memory_size(int instance)
+{
+ switch (instance) {
+ case RISAF2_INST:
+ return STM32MP_OSPI_MM_SIZE;
+ case RISAF4_INST:
+ return dt_get_ddr_size();
+ default:
+ return 0U;
+ }
+}
+
uintptr_t stm32_get_bkpr_boot_mode_addr(void)
{
return tamp_bkpr(BKPR_BOOT_MODE);